diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/ID.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/ID.v" new file mode 100644 index 0000000000000000000000000000000000000000..6f4f42c75aa53532df4e522e1fdc4bdac4b09b9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/ID.v" @@ -0,0 +1,118 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:56:51 11/23/2018 +// Design Name: +// Module Name: ID +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ID( + input clk, + input reset, + input en, + input [31:0] Instr, + input [31:0] PC, + output reg[31:0] IR_D, + output reg[31:0] PC_D, + output reg[31:0] PC4_D, + output reg[31:0] PC8_D, + output [4:0] excode_D + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define j 6'b000010 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + initial begin + IR_D <= 0; + end + + wire RI;//译码异常 不认识的op func + assign RI = (IR_D[`op]==`j)||(IR_D[`op]==`jal) + ||(IR_D[`op]==`beq)||(IR_D[`op]==`bne)||(IR_D[`op]==`blez)||(IR_D[`op]==`bgtz)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00000)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00001) + ||IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu + ||IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu + ||IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb + ||(IR_D[`op]==6'b010000&&(IR_D[`rs]==5'b00000||IR_D[`rs]==5'b00100)) + ||(IR_D==32'h42000018) + ||(IR_D[`op]==`R&&(IR_D[`func]==`jr||IR_D[`func]==`jalr||IR_D[`func]==`addu||IR_D[`func]==`subu||IR_D[`func]==`add||IR_D[`func]==`sub||IR_D[`func]==`sll||IR_D[`func]==`srl||IR_D[`func]==`sra + ||IR_D[`func]==`sllv||IR_D[`func]==`srlv||IR_D[`func]==`srav||IR_D[`func]==`and_||IR_D[`func]==`or_||IR_D[`func]==`nor_||IR_D[`func]==`xor_||IR_D[`func]==`slt||IR_D[`func]==`sltu + ||IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu||IR_D[`func]==`mfhi||IR_D[`func]==`mflo||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)); + + assign excode_D = (RI==0) ? 10 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_D <= 32'h00000000; + end + else if(en) begin + IR_D <= Instr; + PC_D <= PC; + PC4_D <= PC+4; + PC8_D <= PC+8; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/MEM.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/MEM.v" new file mode 100644 index 0000000000000000000000000000000000000000..b85d5c05ef685643f157f17cda0f77adcd844440 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/MEM.v" @@ -0,0 +1,91 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:27:06 11/23/2018 +// Design Name: +// Module Name: MEM +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module MEM( + input clk, + input reset, + input en, + input [31:0] IR_E, + input [31:0] PC_E, + input [31:0] PC4_E, + input [31:0] PC8_E, + input [31:0] ALU, + input [31:0] Mult_Div, + input [31:0] RT_E, + input Zero_E, + input more_E, + input less_E, + output reg[31:0] IR_M, + output reg[31:0] PC_M, + output reg[31:0] PC4_M, + output reg[31:0] PC8_M, + output reg[31:0] AO_M, + output reg[31:0] MDO_M, + output reg[31:0] RT_M, + output [6:2] excode_M, + output reg Zero_M, + output reg more_M, + output reg less_M + ); + + `define op 31:26 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + + initial begin + IR_M <= 0; + end + + assign excode_M = ((IR_M[`op]==`lw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`lh&&AO_M[0]!=1'b0)||(IR_M[`op]==`lhu&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f0b&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| + ((IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 4 : + ((IR_M[`op]==`sw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`sh&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`sw||IR_M[`op]==`sb||IR_M[`op]==`sh)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f07&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| //不能向COUNT写 7f07 + ((IR_M[`op]==`sb||IR_M[`op]==`sh)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 5 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_M <= 32'h00000000; + end + else if(en) begin + IR_M <= IR_E; + PC_M <= PC_E; + PC4_M <= PC4_E; + PC8_M <= PC8_E; + AO_M <= ALU; + MDO_M <= Mult_Div; + RT_M <= RT_E; + Zero_M <= Zero_E; + more_M <= more_E; + less_M <= less_E; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/Mult_Div.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/Mult_Div.v" new file mode 100644 index 0000000000000000000000000000000000000000..17902f23aeb76b4e7bfc95d2ac782847068d23c8 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/Mult_Div.v" @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 11/30/2018 +// Design Name: +// Module Name: Mult_Div +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Mult_Div( + input clk, + input reset, + input [31:0] A, + input [31:0] B, + input [1:0] op, + input start, + input if_mthi, + input if_mtlo, + output reg Busy, + output [31:0] High, + output [31:0] Low + ); + reg [31:0] Hi; + reg [31:0] Lo; + assign High = Hi; + assign Low = Lo; + reg[31:0] cycles; + reg [63:0] tmp; + + initial begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + + always@(posedge clk) begin + if(reset) begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + else if(!Busy) begin + if(start) begin + case(op) + 2'b00: begin//mult + tmp<=$signed(A)*$signed(B); + cycles=5; + end + 2'b01: begin//multu + tmp<=A*B; + cycles=5; + end + 2'b10: begin//div + tmp<={$signed(A)%$signed(B),$signed(A)/$signed(B)}; + cycles=10; + end + 2'b11: begin//divu + tmp<={A%B,A/B}; + cycles=10; + end + endcase + Busy<=1; + end + if(if_mthi) begin + Hi<=A; + end + if(if_mtlo) begin + Lo<=A; + end + end + else if(Busy) begin + if(cycles>0) begin + cycles=cycles-1; + if(cycles==0) begin + {Hi,Lo}<=tmp; + Busy<=0; + end + end + end + end +endmodule \ No newline at end of file diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/WB.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/WB.v" new file mode 100644 index 0000000000000000000000000000000000000000..6ad1438e720b13966f9f1d7bbff398e41f1f031d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/WB.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:30:22 11/23/2018 +// Design Name: +// Module Name: WB +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module WB( + input clk, + input reset, + input en, + input [31:0] IR_M, + input [31:0] PC_M, + input [31:0] PC4_M, + input [31:0] PC8_M, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] DM, + input [31:0] CP0_M, + output reg[31:0] IR_W, + output reg[31:0] PC_W, + output reg[31:0] PC4_W, + output reg[31:0] PC8_W, + output reg[31:0] AO_W, + output reg[31:0] MDO_W, + output reg[31:0] DR_W, + output reg[31:0] CP0_W + ); + initial begin + IR_W <= 0; + end + always@(posedge clk) begin + if(reset) begin + IR_W <= 32'h00000000; + end + else if(en) begin + IR_W <= IR_M; + PC_W <= PC_M; + PC4_W <= PC4_M; + PC8_W <= PC8_M; + AO_W <= AO_M; + MDO_W <= MDO_M; + DR_W <= DM; + CP0_W <= CP0_M; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/alu.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/alu.v" new file mode 100644 index 0000000000000000000000000000000000000000..779fa26f44d1c9563d8acfa5e6eb6c115d67b156 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/alu.v" @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:01:30 11/23/2018 +// Design Name: +// Module Name: alu +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module alu( + input [31:0] A, + input [31:0] B, + input [3:0] ALUCtrl, + output reg[31:0] Result, + output over + ); + + reg[32:0] temp; + + assign over = (temp[32]!=temp[31]); + + always@(*) begin + case(ALUCtrl) + 4'b0000: begin + Result = A & B; + end + 4'b0001: begin + Result = A | B; + end + 4'b0010: begin + temp = {A[31],A[31:0]} + {B[31],B[31:0]}; + Result = A + B; + end + 4'b0011: begin + temp = {A[31],A[31:0]} - {B[31],B[31:0]}; + Result = A - B; + end + 4'b0100: begin + Result = A^B; + end + 4'b0101: begin + Result = ~(A|B); + end + 4'b0110: begin//sll sllv 逻辑左 + Result = B << A[4:0]; + end + 4'b0111: begin//srl srlv 逻辑右 + Result = B >> A[4:0]; + end + 4'b1000: begin//sra srav 算数右 + Result = $signed($signed(B) >>> A[4:0]); + end + 4'b1001: begin + Result = ($signed(A)<$signed(B)) ? 32'b1 : 32'b0; + end + 4'b1010: begin + Result = (A0) ? 1'b1 : 1'b0; + assign less = ($signed(D1)<0) ? 1'b1 : 1'b0; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/controller.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/controller.v" new file mode 100644 index 0000000000000000000000000000000000000000..097ebdd236cebd4bba9b639c9d30df8e4e6bef5d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/controller.v" @@ -0,0 +1,1330 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:53:56 11/24/2018 +// Design Name: +// Module Name: controller +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module controller( + input [5:0] op, + input [5:0] func, + input [4:0] rs, + input [4:0] rt, + output reg[3:0] ALUCtrl, + output reg[1:0] RegDst, + output reg ALUASrc, + output reg ALUBSrc, + output reg RegWrite, + output reg MemRead, + output reg MemWrite, + output reg [2:0] MemtoReg, + output reg [1:0]ExtOp, + output reg if_beq, + output reg if_bne, + output reg if_blez, + output reg if_bgez, + output reg if_bltz, + output reg if_bgtz, + output reg if_j, + output reg [1:0]PCsel, + output reg if_sh, + output reg if_sb, + output reg[2:0] dataOp, + output reg[1:0] multdivOp, + output reg start, + output reg if_mthi, + output reg if_mtlo, + output reg if_mfhi, + output reg if_mflo, + output reg if_1, + output reg if_2, + output reg if_3, + output reg cp0WE + ); + initial begin + PCsel <= 2'b00; + end + always@(*) + begin + case (op) + 6'b000000://R + begin + RegDst<=2'b01; + ALUBSrc<=0; + MemRead<=0; + MemWrite<=0; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + if_sh<=0; + if_sb<=0; + if_j<=0; + dataOp<=3'b000; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(func) + 6'b100001: begin //addu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100000: begin //add + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100011: begin //subu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100010: begin //sub + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100100: begin //and + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100101: begin //or + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100110: begin //xor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0100; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100111: begin //nor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0101; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001000: begin //jr + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001001: begin //jalr + ALUASrc<=0; + MemtoReg<=3'b010; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000000: begin //sll nop + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000100: begin //sllv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000010: begin //srl + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000110: begin //srlv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000011: begin //sra + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000111: begin //srav + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101010: begin //slt + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101011: begin //sltu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011000: begin //mult + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011001: begin //multu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b01; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011010: begin //div + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b10; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011011: begin //divu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b11; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010000: begin //mfhi + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=1; + if_mflo<=0; + end + 6'b010010: begin //mflo + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=1; + end + 6'b010001: begin //mthi + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=1; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010011: begin //mtlo + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=1; + if_mfhi<=0; + if_mflo<=0; + end + default: begin + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + endcase + end + 6'b100011://lw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100000://lb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b010; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100100://lbu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b001; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100001://lh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b100; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100101://lhu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b011; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101011://sw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101001://sh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=1; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101000://sb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=1; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000100://beq + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=1; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000101://bne + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=1; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000111://bgtz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=1; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000110://blez + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=1; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000001://bgez/bltz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(rt) + 5'b00001:begin//bgez + if_bgez<=1; + if_bltz<=0; + end + 5'b00000:begin//bltz + if_bgez<=0; + if_bltz<=1; + end + default:begin + if_bgez<=0; + if_bltz<=0; + end + endcase + end + + 6'b001111://lui + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b10; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001101://ori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001010://slti + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001011://sltiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001100://andi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001110://xori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0100; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001001://addiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001000://addi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000011://jal + begin + RegDst<=2'b10; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b010; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000010://j + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b010000: + begin + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ExtOp<=2'b00; + ALUCtrl<=4'b0000; + ALUASrc<=0; + ALUBSrc<=0; + if_j<=0; + MemRead<=0; + MemWrite<=0; + RegDst<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + case(rs) + 5'b00100: //mtc0 + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b00; + cp0WE<=1; + end + 5'b00000: //mfc0 + begin + RegWrite<=1; + MemtoReg<=3'b100; + PCsel<=2'b00; + cp0WE<=0; + end + default: + begin + + end + endcase + case(func) + 6'b011000://eret + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b11; + cp0WE<=0; + end + default: begin + + end + endcase + end + + default: + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/dm.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/dm.v" new file mode 100644 index 0000000000000000000000000000000000000000..8dc235f6441786a2939b96423488a07d442966e3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/dm.v" @@ -0,0 +1,89 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:57 11/23/2018 +// Design Name: +// Module Name: dm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dm( + input clk, + input reset, + input MemWrite, + input MemRead, + input if_sh, + input if_sb, + input [31:0] MemAddr, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD + ); + + reg[31:0] dm[0:4095]; + integer i; + initial begin + for(i=0;i<4096;i=i+1) begin //1024 + dm[i]<=0; + end + end + + assign RD = MemRead ? dm[MemAddr[13:2]] : 0; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<4096;i=i+1) begin//1024 + dm[i]<=0; + end + end + else begin + if(MemWrite) begin + if(if_sh) begin + if(MemAddr[1]==1'b1) begin + dm[MemAddr[13:2]][31:16] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[15:0],dm[MemAddr[13:2]][15:0]}); + end + else if(MemAddr[1]==1'b0) begin + dm[MemAddr[13:2]][15:0] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[15:0]}); + end + end + else if(if_sb) begin + case(MemAddr[1:0]) + 2'b00: begin + dm[MemAddr[13:2]][7:0] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:8],WD[7:0]}); + end + 2'b01: begin + dm[MemAddr[13:2]][15:8] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[7:0],dm[MemAddr[13:2]][7:0]}); + end + 2'b10: begin + dm[MemAddr[13:2]][23:16] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:24],WD[7:0],dm[MemAddr[13:2]][15:0]}); + end + 2'b11: begin + dm[MemAddr[13:2]][31:24] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[7:0],dm[MemAddr[13:2]][23:0]}); + end + endcase + end + else begin + dm[MemAddr[13:2]] <= WD; + $display("%d@%h: *%h <= %h",$time,PC,MemAddr,WD); + end + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/ext.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/ext.v" new file mode 100644 index 0000000000000000000000000000000000000000..ab616813a96964cd24ece2c94644f7d546a4fafe --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/ext.v" @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:59:19 11/23/2018 +// Design Name: +// Module Name: ext +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ext( + input [15:0] in, + input [1:0] ExtOp, + output reg [31:0] out + ); + + always@(*) begin + case(ExtOp) + 2'b00: out <= {{16{in[15]}},in}; + 2'b01: out <= {{16{1'b0}},in}; + 2'b10: out <= {in,{16{1'b0}}}; + 2'b11: out <= 0; + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/forward_mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/forward_mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..fd11f054c798b464df7a722b129173f8280ec259 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/forward_mux.v" @@ -0,0 +1,117 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:34 11/24/2018 +// Design Name: +// Module Name: forward_mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module forward_mux( + input [31:0] RS_E, + input [31:0] RT_E, + input [31:0] RT_M, + input [31:0] WD, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] CP0_M, + input [31:0] MD_out, + input [31:0] PC8_E, + input [31:0] PC8_M, + input [31:0] PC8_W, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EPCout, + input [2:0] ForwardRSD, + input [2:0] ForwardRTD, + input [2:0] ForwardRSE, + input [2:0] ForwardRTE, + input [2:0] ForwardRTM, + input [2:0] ForwardERET, + output reg[31:0] MFRSD, + output reg[31:0] MFRTD, + output reg[31:0] MFRSE, + output reg[31:0] MFRTE, + output reg[31:0] MFRTM, + output reg[31:0] MFERET + ); + + always@(*) begin + case(ForwardRSD) + 3'b000 : MFRSD <= RF_RD1; + 3'b001 : MFRSD <= AO_M; + 3'b010 : MFRSD <= WD; + 3'b011 : MFRSD <= PC8_E; + 3'b100 : MFRSD <= PC8_M; + 3'b101 : MFRSD <= CP0_M; + 3'b110 : MFRSD <= MD_out; + 3'b111 : MFRSD <= MDO_M; + default : MFRSD <= 0; + endcase + + case(ForwardRTD) + 0: MFRTD <= RF_RD2; + 1: MFRTD <= AO_M; + 2: MFRTD <= WD; + 3: MFRTD <= PC8_E; + 4: MFRTD <= PC8_M; + 5: MFRTD <= CP0_M; + 6: MFRTD <= MD_out; + 7: MFRTD <= MDO_M; + default: MFRTD <= 0; + endcase + + case(ForwardRSE) + 0:MFRSE <= RS_E; + 1:MFRSE <= AO_M; + 2:MFRSE <= WD; + 3:MFRSE <= 0; + 4:MFRSE <= PC8_M; + 5:MFRSE <= CP0_M; + 6:MFRSE <= 0; + 7:MFRSE <= MDO_M; + default:MFRSE <= 0; + endcase + + case(ForwardRTE) + 0:MFRTE <= RT_E; + 1:MFRTE <= AO_M; + 2:MFRTE <= WD; + 3:MFRTE <= 0; + 4:MFRTE <= PC8_M; + 5:MFRTE <= CP0_M; + 6:MFRTE <= 0; + 7:MFRTE <= MDO_M; + default:MFRTE <= 0; + endcase + + case(ForwardRTM) + 0:MFRTM <= RT_M; + 1:MFRTM <= 0; + 2:MFRTM <= WD; + 3:MFRTM <= 0; + 4:MFRTM <= 0; + 5:MFRTM <= 0; + 6:MFRTM <= 0; + 7:MFRTM <= 0; + default:MFRTM <= 0; + endcase + + case(ForwardERET) + 0:MFERET <= EPCout; + 1:MFERET <= MFRTM; + default:MFERET <= 0; + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/grf.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/grf.v" new file mode 100644 index 0000000000000000000000000000000000000000..90307bafbb30dc6650cbb3441f5711e3396f9a9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/grf.v" @@ -0,0 +1,59 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:24 11/23/2018 +// Design Name: +// Module Name: grf +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module grf( + input clk, + input reset, + input RegWrite, + input [4:0] RA1, + input [4:0] RA2, + input [4:0] WA, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD1, + output [31:0] RD2 + ); + + reg[31:0] register[31:0]; + integer i; + initial begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + + assign RD1 = register[RA1]; + assign RD2 = register[RA2]; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + else begin + if(RegWrite&&WA!=5'b00000) begin + register[WA] <= WD; + //$display("@%h: $%d <= %h", PC, WA,WD); + $display("%d@%h: $%d <= %h",$time,PC,WA,WD); + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/hazardUnit.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/hazardUnit.v" new file mode 100644 index 0000000000000000000000000000000000000000..14bd798e84ac5caaaa3a6f3e5a3d60a39869d4d3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/hazardUnit.v" @@ -0,0 +1,271 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:55:59 11/24/2018 +// Design Name: +// Module Name: hazardUnit +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module hazardUnit( + input [31:0] IR_D, + input [31:0] IR_E, + input [31:0] IR_M, + input [31:0] IR_W, + input Busy, + input start, + output IR_D_en, + output IR_E_clr, + output PC_en, + output [2:0]ForwardRSD, + output [2:0]ForwardRTD, + output [2:0]ForwardRSE, + output [2:0]ForwardRTE, + output [2:0]ForwardRTM, + output [2:0]ForwardERET + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + `define cal_r_D (IR_D[`op]==`R&&IR_D[`func]!=`jalr&&IR_D[`func]!=`jr&&IR_D[`func]!=`mfhi&&IR_D[`func]!=`mflo&&IR_D!=0) + `define cal_r_E (IR_E[`op]==`R&&IR_E[`func]!=`jalr&&IR_E[`func]!=`jr&&IR_E[`func]!=`mfhi&&IR_E[`func]!=`mflo&&IR_E!=0) + `define cal_r_M (IR_M[`op]==`R&&IR_M[`func]!=`jalr&&IR_M[`func]!=`jr&&IR_M[`func]!=`mfhi&&IR_M[`func]!=`mflo&&IR_M!=0) + `define cal_r_W (IR_W[`op]==`R&&IR_W[`func]!=`jalr&&IR_W[`func]!=`jr&&IR_W[`func]!=`mfhi&&IR_W[`func]!=`mflo&&IR_W!=0) + + `define cal_i_D (IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu) + `define cal_i_E (IR_E[`op]==`lui||IR_E[`op]==`ori||IR_E[`op]==`addi||IR_E[`op]==`addiu||IR_E[`op]==`andi||IR_E[`op]==`xori||IR_E[`op]==`slti||IR_E[`op]==`sltiu) + `define cal_i_M (IR_M[`op]==`lui||IR_M[`op]==`ori||IR_M[`op]==`addi||IR_M[`op]==`addiu||IR_M[`op]==`andi||IR_M[`op]==`xori||IR_M[`op]==`slti||IR_M[`op]==`sltiu) + `define cal_i_W (IR_W[`op]==`lui||IR_W[`op]==`ori||IR_W[`op]==`addi||IR_W[`op]==`addiu||IR_W[`op]==`andi||IR_W[`op]==`xori||IR_W[`op]==`slti||IR_W[`op]==`sltiu) + + `define load_D (IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu) + `define load_E (IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu) + `define load_M (IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu) + `define load_W (IR_W[`op]==`lw||IR_W[`op]==`lb||IR_W[`op]==`lbu||IR_W[`op]==`lh||IR_W[`op]==`lhu) + + `define store_D (IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb) + `define store_E (IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb) + `define store_M (IR_M[`op]==`sw||IR_M[`op]==`sh||IR_M[`op]==`sb) + `define store_W (IR_W[`op]==`sw||IR_W[`op]==`sh||IR_W[`op]==`sb) + + `define beq_D (IR_D[`op]==`beq||IR_D[`op]==`bne||IR_D[`op]==`bgtz||IR_D[`op]==`blez||(IR_D[`op]==6'b000001&&(IR_D[`rt]==5'b00000||IR_D[`rt]==5'b00001))) + `define beq_E (IR_E[`op]==`beq||IR_E[`op]==`bne||IR_E[`op]==`bgtz||IR_E[`op]==`blez||(IR_E[`op]==6'b000001&&(IR_E[`rt]==5'b00000||IR_E[`rt]==5'b00001))) + `define beq_M (IR_M[`op]==`beq||IR_M[`op]==`bne||IR_M[`op]==`bgtz||IR_M[`op]==`blez||(IR_M[`op]==6'b000001&&(IR_M[`rt]==5'b00000||IR_M[`rt]==5'b00001))) + `define beq_W (IR_W[`op]==`beq||IR_W[`op]==`bne||IR_W[`op]==`bgtz||IR_W[`op]==`blez||(IR_W[`op]==6'b000001&&(IR_W[`rt]==5'b00000||IR_W[`rt]==5'b00001))) + + `define jal_D (IR_D[`op]==`jal) + `define jal_E (IR_E[`op]==`jal) + `define jal_M (IR_M[`op]==`jal) + `define jal_W (IR_W[`op]==`jal) + + `define jalr_D (IR_D[`op]==`R&&IR_D[`func]==`jalr) + `define jalr_E (IR_E[`op]==`R&&IR_E[`func]==`jalr) + `define jalr_M (IR_M[`op]==`R&&IR_M[`func]==`jalr) + `define jalr_W (IR_W[`op]==`R&&IR_W[`func]==`jalr) + + `define jr_D (IR_D[`op]==`R&&IR_D[`func]==`jr) + `define jr_E (IR_E[`op]==`R&&IR_E[`func]==`jr) + `define jr_M (IR_M[`op]==`R&&IR_M[`func]==`jr) + `define jr_W (IR_W[`op]==`R&&IR_W[`func]==`jr) + + `define mfhi_D (IR_D[`op]==`R&&IR_D[`func]==`mfhi) + `define mfhi_E (IR_E[`op]==`R&&IR_E[`func]==`mfhi) + `define mfhi_M (IR_M[`op]==`R&&IR_M[`func]==`mfhi) + `define mfhi_W (IR_W[`op]==`R&&IR_W[`func]==`mfhi) + + `define mflo_D (IR_D[`op]==`R&&IR_D[`func]==`mflo) + `define mflo_E (IR_E[`op]==`R&&IR_E[`func]==`mflo) + `define mflo_M (IR_M[`op]==`R&&IR_M[`func]==`mflo) + `define mflo_W (IR_W[`op]==`R&&IR_W[`func]==`mflo) + + `define mf_D (`mfhi_D||`mflo_D) + `define mf_E (`mfhi_E||`mflo_E) + `define mf_M (`mfhi_M||`mflo_M) + `define mf_W (`mfhi_W||`mflo_W) + + `define mfc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00000) + `define mfc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00000) + `define mfc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00000) + `define mfc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00000) + + `define mtc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00100) + `define mtc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100) + `define mtc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100) + `define mtc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00100) + + reg stall=0; + wire stall_b,stall_cal_r,stall_cal_i,stall_load,stall_store,stall_jr,stall_jalr,stall_busy,stall_mfmt,stall_eret; + + assign stall_b = (`beq_D & `cal_r_E & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0||IR_D[`rt]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`beq_D & `cal_i_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_M & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0||IR_D[`rt]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_cal_r = (`cal_r_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_cal_i = (`cal_i_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_load = (`load_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_store = (`store_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_jr = (`jr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_jalr = (`jalr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jalr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_busy = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) & (Busy||start); + //assign stall_mfmt = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + // IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) + // &(IR_E[`op]==`R&(IR_E[`func]==`mult||IR_E[`func]==`multu||IR_E[`func]==`div||IR_E[`func]==`divu)); + assign stall_eret = (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100&&IR_E[`rd]==14)&&IR_D==32'h42000018; + always@(*) begin + stall <= stall_b||stall_cal_r||stall_cal_i||stall_load||stall_store||stall_jr||stall_jalr||stall_busy||stall_eret; + end + + assign IR_D_en = !stall; + assign IR_E_clr = stall; + assign PC_en = !stall; + + `define RSD (`cal_r_D||`cal_i_D||`load_D||`store_D||`beq_D||`jr_D||`jalr_D) + `define RTD (`cal_r_D||`store_D||`beq_D||`mtc0_D) + `define RSE (`cal_r_E||`cal_i_E||`load_E||`store_E) + `define RTE (`cal_r_E||`store_E||`mtc0_E) + `define RTM (`store_M||`mtc0_M) + + assign ForwardRSD = (`RSD & `jal_E & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 3 : + (`RSD & `jalr_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 3 : + (`RSD & `mf_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 6 : + (`RSD & `cal_r_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 1 : + (`RSD & `cal_i_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 1 : + (`RSD & `jal_M & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 4 : + (`RSD & `jalr_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 4 : + (`RSD & `mf_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 5 : + (`RSD & `mfc0_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 7 : + (`RSD & `cal_r_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `cal_i_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `load_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mf_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mfc0_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `jal_W & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 2 : + (`RSD & `jalr_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : 0 ; + + assign ForwardRTD = (`RTD & `jal_E & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 3 : + (`RTD & `jalr_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 3 : + (`RTD & `mf_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 6 : + (`RTD & `cal_r_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 1 : + (`RTD & `cal_i_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 1 : + (`RTD & `jal_M & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 4 : + (`RTD & `jalr_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 4 : + (`RTD & `mf_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 7 : + (`RTD & `mfc0_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 5 : + (`RTD & `cal_r_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `cal_i_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `load_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mf_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mfc0_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `jal_W & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 2 : + (`RTD & `jalr_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : 0; + + assign ForwardRSE = (`RSE & `cal_r_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `cal_i_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `jal_M & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 4 : + (`RSE & `jalr_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 4 : + (`RSE & `mf_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 7 : + (`RSE & `mfc0_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 5 : + (`RSE & `cal_r_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `cal_i_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `load_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mf_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mfc0_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jal_W & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jalr_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : 0; + + assign ForwardRTE = (`RTE & `cal_r_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `cal_i_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `jal_M & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 4 : + (`RTE & `jalr_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 4 : + (`RTE & `mf_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 7 : + (`RTE & `mfc0_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 5 : + (`RTE & `cal_r_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `cal_i_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `load_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mf_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mfc0_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jal_W & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jalr_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : 0; + + assign ForwardRTM = (`RTM & `cal_r_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `cal_i_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `load_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mf_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mfc0_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jal_W & (IR_M[`rt]==31) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jalr_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : 0; + + assign ForwardERET = ((IR_D==32'h42000018)&&(IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100&&IR_M[`rd]==14)) ? 1 : 0; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/im.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/im.v" new file mode 100644 index 0000000000000000000000000000000000000000..5743ec5f2b17e42b6512c62f08070c6b86a83cca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/im.v" @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:01 11/23/2018 +// Design Name: +// Module Name: im +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module im( + input [31:0] PC, + output[31:0] instruction + ); + + reg[31:0] im[0:4095]; + initial begin + $readmemh("code.txt",im); + $readmemh("code_handler.txt",im,1120,2047); + end + + wire[31:0] pc=PC-32'h00003000; + assign instruction = im[pc[13:2]]; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/mips.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/mips.v" new file mode 100644 index 0000000000000000000000000000000000000000..d011fae91ff309813c5ac4a0812a1a4f11c36a74 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/mips.v" @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:46:09 11/23/2018 +// Design Name: +// Module Name: mips +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mips( + input clk, + input reset + ); + + wire [31:0] PrRD; + wire [6:2] ExcCode; + wire [31:0] PrAddr; + wire [31:0] PrWD; + wire PrWe; + wire [31:0] DEV_Addr; + wire [31:0] DEV_WD; + wire [31:0] DEV0_RD; + wire [31:0] DEV1_RD; + wire WeDEV0; + wire WeDEV1; + wire IRQ0; + wire IRQ1; + + CPU my_CPU(.clk(clk),.reset(reset),.HWInt({4'b0,IRQ1,IRQ0}),.PrRD(PrRD),.ExcCode(ExcCode),.PrAddr(PrAddr),.PrWD(PrWD),.PrWe(PrWe)); + Bridge my_Bridge(PrAddr,PrWe,PrRD,PrWD,DEV_Addr,DEV_WD,DEV0_RD,DEV1_RD,WeDEV0,WeDEV1); + DEV0 my_time0(clk,reset,DEV_Addr,WeDEV0,DEV_WD,DEV0_RD,IRQ0); + DEV1 my_time1(clk,reset,DEV_Addr,WeDEV1,DEV_WD,DEV1_RD,IRQ1); + + assign ExcCode = (IRQ0||IRQ1) ? 5'b00000 : 5'b11111; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..02d800057a121623b1cb76181c21a974d0f6e996 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/mux.v" @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:31:53 11/23/2018 +// Design Name: +// Module Name: mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux( + input [31:0] EXT_E, + input [31:0] IR_E, + input [31:0] IR_W, + input [31:0] DR_Wnew, + input [31:0] AO_W, + input [31:0] MDO_W, + input [31:0] PC8_W, + input [31:0] CP0_W, + input [31:0] MFRSE, + input [31:0] MFRTE, + input [31:0] High, + input [31:0] Low, + input ALUasel, + input ALUbsel, + input if_mfhi, + input if_mflo, + input [1:0] RegDst, + input [2:0] MemtoReg, + output reg[31:0] ALU_A, + output reg[31:0] ALU_B, + output reg[4:0] MUX_A3, + output reg[31:0] MUX_WD, + output reg[31:0] MD_out + ); + + always@(*) begin + case(ALUasel) + 1'b0: ALU_A<=MFRSE; + 1'b1: ALU_A<={27'b0,IR_E[10:6]}; + endcase + + case(ALUbsel) + 1'b0: ALU_B<=MFRTE; + 1'b1: ALU_B<=EXT_E; + endcase + + case(RegDst) + 2'b00: MUX_A3<=IR_W[20:16]; + 2'b01: MUX_A3<=IR_W[15:11]; + 2'b10: MUX_A3<=32'h1f; + 2'b11: MUX_A3<=0; + endcase + + case(MemtoReg) + 3'b000: MUX_WD<=AO_W; + 3'b001: MUX_WD<=DR_Wnew; + 3'b010: MUX_WD<=PC8_W; + 3'b011: MUX_WD<=MDO_W; + 3'b100: MUX_WD<=CP0_W; + endcase + + if(if_mfhi) MD_out<=High; + else if(if_mflo) MD_out<=Low; + else MD_out<=0; + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/npc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/npc.v" new file mode 100644 index 0000000000000000000000000000000000000000..2326b32486b61ad162e0643debbddbdf4235c924 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/npc.v" @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:13:22 11/23/2018 +// Design Name: +// Module Name: npc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module npc( + input [31:0] PC4, + input [31:0] PC4D, + input [25:0] I26, + input [31:0] MFRSD, + input [31:0] EPC, + input Zero, + input more, + input less, + input if_beq, + input if_bne, + input if_bgtz, + input if_blez, + input if_bgez, + input if_bltz, + input if_j,//j或jal + input[1:0] PC_sel, + input Interrupt, + output reg[31:0] next_pc + ); + reg[31:0] NPC; + always@(*) begin + if((if_beq&&Zero)||(if_bne&&!Zero)||(if_bgtz&&more)||(if_blez&&!more)||(if_bgez&&!less)||(if_bltz&&less)) begin + NPC<=PC4D+{{14{I26[15]}},I26[15:0],2'b00}; + end + else if(if_j) begin + NPC<={PC4D[31:28],I26[25:0],2'b00}; + end + else begin + NPC<=PC4D+4; + end + case(PC_sel) + 2'b00: next_pc<=PC4; + 2'b01: next_pc<=MFRSD; + 2'b10: next_pc<=NPC; + 2'b11: next_pc<=EPC; + endcase + if(Interrupt) begin + next_pc<=32'h00004180; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/pc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/pc.v" new file mode 100644 index 0000000000000000000000000000000000000000..06a0733bb46e61a82eeecb3b568f77b00d2eea5a --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/pc.v" @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:00 11/23/2018 +// Design Name: +// Module Name: pc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module pc( + input clk, + input reset, + input en, + input[31:0] next_pc, + output reg[31:0] pc, + output [4:0] excode_F + ); + + initial begin + pc<=32'h00003000; + end + + assign excode_F = ((pc[1:0]!=2'b00)||(pc < 32'h00003000)||(pc > 32'h00004ffc)) ? 4 : 0; + + always@(posedge clk) begin + if(reset) begin + pc <= 32'h00003000; + end + else if(en) begin + pc <= next_pc; + end + else begin + pc <= pc; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/test.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/test.v" new file mode 100644 index 0000000000000000000000000000000000000000..e5caf7ea5fe230bbd63b23a8c12df7473769acca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_6bd\344\275\215\344\277\235\346\214\2011/test.v" @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:00 11/25/2018 +// Design Name: mips +// Module Name: E:/Verilog/p5/test.v +// Project Name: p5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: mips +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module test; + + // Inputs + reg clk; + reg reset; + + // Instantiate the Unit Under Test (UUT) + mips uut ( + .clk(clk), + .reset(reset) + ); + + initial begin + clk = 0; + reset = 1; + #12 reset = 0; + end + + always #10 clk = ~clk; + + +endmodule + + diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/Bridge.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/Bridge.v" new file mode 100644 index 0000000000000000000000000000000000000000..dd788614ad6e56748e6d45767d860c460250ba97 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/Bridge.v" @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:11 12/12/2018 +// Design Name: +// Module Name: Bridge +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bridge( + input [31:0] PrAddr, + input PrWE, + output [31:0] PrRD, + input [31:0] PrWD, + output [31:0] DEV_Addr, + output [31:0] DEV_WD, + input [31:0] DEV0_RD, + input [31:0] DEV1_RD, + output WeDEV0, + output WeDEV1 + ); + + `define DEBUG_DEV_DATA 32'b0 + + //DEV0 00007F00-00007F0B + //DEV1 00007F10-00007F1B + wire HitDEV0,HitDEV1; + assign HitDEV0 = (PrAddr[31:4]==28'h00007F0); + assign HitDEV1 = (PrAddr[31:4]==28'h00007F1); + + assign PrRD = (HitDEV0) ? DEV0_RD : + (HitDEV1) ? DEV1_RD : + `DEBUG_DEV_DATA; + + assign WeDEV0 = PrWE&&HitDEV0; + assign WeDEV1 = PrWE&&HitDEV1; + + assign DEV_Addr = PrAddr; + assign DEV_WD = PrWD; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/CP0.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/CP0.v" new file mode 100644 index 0000000000000000000000000000000000000000..15a2510804a9dcc8533627c6cf1027873ca13cbc --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/CP0.v" @@ -0,0 +1,133 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:46:14 12/13/2018 +// Design Name: +// Module Name: CP0 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CP0( + input[4:0] A1,//读CP0寄存器编号 执行MFC0指令时产生 + input[4:0] A2,//写CP0寄存器编号 执行MTC0指令时产生 + input[31:0] DIn,//CP0寄存器的写入数据 执行MTC0指令时产生 数据来自GPR + input[31:0] PC,//中断/异常时的PC + input[31:0] IR_M,//指令 + input Zero, + input more, + input less, + input if_bd, + input[6:2] ExcCode,//中断/异常的类型 + input[5:0] HWInt,//6个设备中断 + input We,//CP0写使能 执行MTC0指令时产生 + input EXLSet,//用于置位SR的EXL(EXL为1) 流水线在M阶段产生 + input EXLClr,//用于清除SR的EXL(EXL为0) 执行ERET指令时产生 + input clk, + input reset, + output Interrupt,//中断和异常 是HWInt/IM/EXL/IE的函数 + output[31:0] EPC,//EPC寄存器输出至NPC + output[31:0] DOut //CP0寄存器的输出数据 执行MFC0指令时产生，输出数据至GRF + ); + + `define SR 12 + `define CAUSE 13 + `define EPC 14 + `define PRID 15 + + `define R 6'b000000 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define jr 6'b001000 + `define j 6'b000010 + `define jalr 6'b001001 + + //SR {16'b0, im, 8'b0, exl, ie} + reg[15:10] im; //6位中断屏蔽位，分别对应6个外部中断 1-允许中断，0-禁止中断 + reg exl;//EXL：异常级 1-进入异常，不允许再中断；0-允许中断 + reg ie;//全局中断使能 1-允许中断；0-禁止中断 + //CAUSE {bd, 15'b0, hwint_pend[15:10], 3'b0, exccode[6:2], 2'b0} + reg bd;//异常发生在延迟槽的指令的话 bd=1 + reg[6:2] exccode; + reg[15:10] hwint_pend;//在clock上升沿不断的保存外部6个中断(HWInt[5:0]) + //EPC + reg[31:0] epc; + //PRID + reg[31:0] prid = 32'h12345678; + wire Exception;//异常 + wire IntReq;//中断 + assign EPC = epc; + //读 除了SR/Cause/EPC/PRId外，不用的寄存器一律输出0 + assign DOut = (A1==`SR) ? {16'b0, im, 8'b0, exl, ie} : + (A1==`CAUSE) ? {bd, 15'b0, hwint_pend[15:10], 3'b0, exccode[6:2], 2'b0} : + (A1==`EPC) ? epc : + (A1==`PRID) ? prid : 0; + assign IntReq = (|(HWInt[5:0] & im[15:10])) & ie & !exl ; + assign Exception = (ExcCode>0) ? 1'b1 : 1'b0; + assign Interrupt = IntReq||Exception; + + integer i; + always@(posedge clk) begin + hwint_pend <= HWInt;//在clock上升沿不断的保存外部6个中断(HWInt[5:0]) + if(reset) begin + im<=6'b0;//SR + exl<=1'b0; + ie<=1'b0; + hwint_pend<=6'b0;//CAUSE + bd<=0; + exccode<=0; + epc<=0;//EPC + end + else begin + epc <= (Interrupt&&bd) ? {PC[31:2], 2'b00} - 4 : + (Interrupt&&!bd) ? {PC[31:2], 2'b00} : + epc; + if(bd==1'b0) begin + bd <= (((IR_M[31:26]==`j)||(IR_M[31:26]==`jal)||(IR_M[31:26]==`beq&&Zero)||(IR_M[31:26]==`bne&&!Zero)||(IR_M[31:26]==`blez&&!more)||(IR_M[31:26]==`bgtz&&more) + ||(IR_M[31:26]==`R&&(IR_M[5:0]==`jr||IR_M[5:0]==`jalr))||(IR_M[31:26]==6'b000001&&IR_M[20:16]==5'b00000&&less)||(IR_M[31:26]==6'b000001&&IR_M[20:16]==5'b00001&&!less))); + end + if(We) begin //写入 + case(A2) + `SR: begin + {im, exl, ie} <= {DIn[15:10], DIn[1], DIn[0]}; + end + `CAUSE: begin + hwint_pend <= DIn[15:10]; + end + `EPC: begin + epc <= DIn; + end + `PRID: begin + prid <= DIn; + end + default: begin + end + endcase + end + if(EXLSet||Interrupt) begin + exl<=1'b1; + exccode<=ExcCode; + end + if(EXLClr) begin + exl<=1'b0; + bd<=1'b0; + end + //if(IntReq) begin + // bd<=1'b0; + //end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/CPU.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/CPU.v" new file mode 100644 index 0000000000000000000000000000000000000000..41e2a8b129092d09ff758d86dd4709b0d6ce2ece --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/CPU.v" @@ -0,0 +1,212 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:30:40 12/15/2018 +// Design Name: +// Module Name: CPU +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CPU( + input clk, + input reset, + input [7:2] HWInt, + input [31:0] PrRD, + input [6:2] ExcCode, + output [31:0] PrAddr, + output [31:0] PrWD, + output PrWe + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + `define imm26 25:0 + + wire PC_en; + wire[1:0] PC_sel; + wire[31:0] PC; + wire[31:0] PC4; + wire[31:0] Instr; + wire ID_en; + wire EX_en; + wire MEM_en; + wire WB_en; + wire ID_reset; + wire EX_reset; + wire MEM_reset; + wire WB_reset; + wire[31:0] IR_D; + wire[31:0] PC_D; + wire[31:0] PC4_D; + wire[31:0] PC8_D; + wire[31:0] IR_E; + wire[31:0] PC_E; + wire[31:0] PC4_E; + wire[31:0] PC8_E; + wire[31:0] IR_M; + wire[31:0] PC_M; + wire[31:0] PC4_M; + wire[31:0] PC8_M; + wire[31:0] IR_W; + wire[31:0] PC_W; + wire[31:0] PC4_W; + wire[31:0] PC8_W; + wire Zero; + wire Zero_E; + wire Zero_M; + wire more; + wire less; + wire more_E; + wire less_E; + wire more_M; + wire less_M; + wire if_beq; + wire if_bne; + wire if_blez; + wire if_bgtz; + wire if_bltz; + wire if_bgez; + wire if_j; + wire[1:0] EXTop; + wire if_sh; + wire if_sb; + + wire[3:0] ALUCtrl; + wire[1:0] RegDst; + wire ALUASrc; + wire ALUBSrc; + wire RegWrite; + wire MemRead; + wire MemWrite; + wire [2:0] MemtoReg; + wire [2:0] dataOp; + wire [1:0] multdivOp; + wire if_mthi; + wire if_mtlo; + wire if_mfhi; + wire if_mflo; + wire start; + wire Busy; + wire[31:0] High; + wire[31:0] Low; + + wire [31:0] RS_E; + wire [31:0] RT_E; + wire [31:0] EXT_E; + wire [31:0] AO_M; + wire [31:0] MDO_M; + wire [31:0] RT_M; + wire [31:0] DR_W; + wire [31:0] DR_Wnew; + wire [31:0] AO_W; + wire [31:0] MDO_W; + + wire[4:0] MUX_A3; + wire[31:0] MUX_WD; + wire[31:0] RF_RD1; + wire[31:0] RF_RD2; + wire[31:0] MFRSD; + wire[31:0] MFRTD; + wire[31:0] MFRSE; + wire[31:0] MFRTE; + wire[31:0] MFRTM; + wire[31:0] MFERET; + wire[31:0] EXT_out; + wire[31:0] ALU_A; + wire[31:0] ALU_B; + wire[31:0] ALU_out; + wire[31:0] MD_out; + wire[31:0] DM_out; + wire[31:0] next_pc; + wire[2:0] ForwardRSD; + wire[2:0] ForwardRTD; + wire[2:0] ForwardRSE; + wire[2:0] ForwardRTE; + wire[2:0] ForwardRTM; + wire[2:0] ForwardERET; + + assign EX_en = 1; + assign MEM_en = 1; + assign WB_en = 1; + assign ID_reset = 0; + assign MEM_reset = 0; + assign WB_reset = 0; + assign PC4 = PC + 4; + + wire[6:2] excode_F,excode_D,excode_E,excode_M; + wire[6:2] excode_outF,excode_outD,excode_outE,excode_outM; + wire over; + wire cp0WE; + wire[31:0] CP0_M; + wire[31:0] CP0_W; + wire[31:0] EPCout; + wire Interrupt; + wire EXLSet; + wire EXLClr; + wire[31:0] DMDEV; + wire if_eret; + + assign PrAddr = AO_M; + assign PrWD = MFRTM; + assign PrWe = (MemWrite&&(~Interrupt));//没出现异常才可以写 + assign EXLSet = Interrupt; + assign EXLClr = (IR_M[`op]==6'b010000&&IR_M[`func]==6'b011000); //eret + + pc my_pc(clk,reset,PC_en||Interrupt,next_pc,PC,excode_F); + im my_im(PC,Instr); + + ID my_ID(clk,(ID_reset||reset||Interrupt||(IR_D==32'h42000018&&ID_en)),ID_en,Instr,PC,IR_D,PC_D,PC4_D,PC8_D,excode_D); + ExcCode my_exc_D(clk,ID_reset||reset||Interrupt,ID_en,excode_F,excode_outD); + controller my_controllerD(.op(IR_D[`op]),.func(IR_D[`func]),.rs(IR_D[`rs]),.rt(IR_D[`rt]),.ExtOp(EXTop),.if_beq(if_beq),.if_bne(if_bne), + .if_blez(if_blez),.if_bgtz(if_bgtz),.if_bgez(if_bgez),.if_bltz(if_bltz),.if_j(if_j),.PCsel(PC_sel)); + grf my_grf(clk,reset,RegWrite,IR_D[`rs],IR_D[`rt],MUX_A3,MUX_WD,PC_W,RF_RD1,RF_RD2); + cmp my_cmp(MFRSD,MFRTD,Zero,more,less); + ext my_ext(IR_D[`imm16],EXTop,EXT_out); + npc my_npc(PC4,PC4_D,IR_D[`imm26],MFRSD,MFERET,Zero,more,less,if_beq,if_bne,if_bgtz,if_blez,if_bgez,if_bltz,if_j,PC_sel,Interrupt,next_pc); + + EX my_EX(clk,EX_reset||reset||Interrupt,EX_en,over,IR_D,PC_D,PC4_D,PC8_D,MFRSD,MFRTD,EXT_out,Zero,more,less,IR_E,PC_E,PC4_E,PC8_E,RS_E,RT_E,EXT_E,excode_E,Zero_E,more_E,less_E); + ExcCode my_exc_E(clk,EX_reset||reset||Interrupt,EX_en,(excode_outD==0?excode_D:excode_outD),excode_outE); + controller my_controllerE(.op(IR_E[`op]),.func(IR_E[`func]),.rs(IR_E[`rs]),.rt(IR_E[`rt]),.ALUCtrl(ALUCtrl),.ALUASrc(ALUASrc),.ALUBSrc(ALUBSrc), + .multdivOp(multdivOp),.start(start),.if_mthi(if_mthi),.if_mtlo(if_mtlo),.if_mfhi(if_mfhi),.if_mflo(if_mflo)); + alu my_alu(ALU_A,ALU_B,ALUCtrl,ALU_out,over); + Mult_Div my_Mult_Div(clk,reset,MFRSE,MFRTE,multdivOp,start,if_mthi,if_mtlo,Busy,High,Low); + + MEM my_MEM(clk,MEM_reset||reset||Interrupt,MEM_en,IR_E,PC_E,PC4_E,PC8_E,ALU_out,MD_out,MFRTE,Zero_E,more_E,less_E,IR_M,PC_M,PC4_M,PC8_M,AO_M,MDO_M,RT_M,excode_M,Zero_M,more_M,less_M); + ExcCode my_exc_M(clk,MEM_reset||reset||Interrupt,MEM_en,(excode_outE==0?excode_E:excode_outE),excode_outM); + controller my_controllerM(.op(IR_M[`op]),.func(IR_M[`func]),.rs(IR_M[`rs]),.rt(IR_M[`rt]),.MemRead(MemRead),.MemWrite(MemWrite),.if_sh(if_sh),.if_sb(if_sb),.cp0WE(cp0WE)); + dm my_dm(clk,reset,(MemWrite&&~Interrupt),MemRead,if_sh,if_sb,AO_M,MFRTM,PC_M,DM_out); + + //中断优先级高 + CP0 my_CP0(.A1(IR_M[`rd]),.A2(IR_M[`rd]),.DIn(MFRTM),.PC(PC_M),.IR_M(IR_M),.Zero(Zero_M),.more(more_M),.less(less_M),.if_bd(excode_E>0||excode_outE>0), + .ExcCode(((|HWInt)? ExcCode : (excode_outM==0) ? excode_M : excode_outM)),.HWInt(HWInt),.We(cp0WE),.EXLSet(EXLSet),.EXLClr(EXLClr), + .clk(clk),.reset(reset),.Interrupt(Interrupt),.EPC(EPCout),.DOut(CP0_M)); + + WB my_WB(clk,WB_reset||reset||Interrupt,WB_en,IR_M,PC_M,PC4_M,PC8_M,AO_M,MDO_M,DM_out,CP0_M,IR_W,PC_W,PC4_W,PC8_W,AO_W,MDO_W,DR_W,CP0_W); + controller my_controllerW(.op(IR_W[`op]),.func(IR_W[`func]),.rs(IR_W[`rs]),.rt(IR_W[`rt]),.RegDst(RegDst),.RegWrite(RegWrite),.MemtoReg(MemtoReg),.dataOp(dataOp)); + DataExt my_DataExt(DR_W,dataOp,AO_W[1:0],DR_Wnew); + + assign DMDEV = (AO_W>=32'h00000000&&AO_W<=32'h00002ffc) ? DR_Wnew : PrRD;//读dm还是dev + + mux my_mux(EXT_E,IR_E,IR_W,DMDEV,AO_W,MDO_W,PC8_W,CP0_W,MFRSE,MFRTE,High,Low,ALUASrc,ALUBSrc,if_mfhi,if_mflo,RegDst,MemtoReg,ALU_A,ALU_B,MUX_A3,MUX_WD,MD_out); + forward_mux my_forward(RS_E,RT_E,RT_M,MUX_WD,AO_M,MDO_M,CP0_M,MD_out,PC8_E,PC8_M,PC8_W,RF_RD1,RF_RD2,EPCout, + ForwardRSD,ForwardRTD,ForwardRSE,ForwardRTE,ForwardRTM,ForwardERET,MFRSD,MFRTD,MFRSE,MFRTE,MFRTM,MFERET); + hazardUnit my_hazard(IR_D,IR_E,IR_M,IR_W,Busy,start,ID_en,EX_reset,PC_en,ForwardRSD,ForwardRTD,ForwardRSE,ForwardRTE,ForwardRTM,ForwardERET); + +endmodule + diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DEV0.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DEV0.v" new file mode 100644 index 0000000000000000000000000000000000000000..1722e2d56078af44ae00b093d1163c73e093f750 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DEV0.v" @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:05:26 12/12/2018 +// Design Name: +// Module Name: DEV0 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DEV0( + input clk, + input reset, + input [31:0] Addr, + input WE, + input [31:0] DataIn, + output reg [31:0] DataOut, + output reg IRQ + ); + + `define Idle 2'b00 + `define Counting 2'b01 + `define Interrupt 2'b10 + + reg[1:0] state; + reg[31:0] PRESET; + reg[31:0] COUNT; + reg[2:1] Mode;//模式选择 + reg IM;//中断屏蔽 + reg Enable;//计数器使能 + reg irq; + + always@(posedge clk) begin + if(reset) begin + PRESET<=0; + COUNT<=0; + state<=`Idle; + IM<=0; + Enable<=0; + irq<=0; + end + if(WE) begin + case(Addr) + 32'h0000_7f00: begin //ctrl + {IM,Mode,Enable} <= DataIn[3:0]; + //当计数器计数时，若计数器使能被 store 类指令修改为 0 则停止计数 + if(state == `Counting && DataIn[0]==1'b0) begin + COUNT<=PRESET; + end + end + 32'h0000_7f04: begin + PRESET<=DataIn; + end + 32'h0000_7f08: begin + //COUNT不会被写的 + end + default: begin + //什么都不做 + end + endcase + end + else begin + case(state) + `Idle: begin + if(Enable==1'b1) begin + state<=`Counting; + COUNT<=PRESET; + irq<=0; + end + else begin + state<=`Idle; + end + end + + `Counting: begin + if(Enable==1'b0) begin + state<=`Idle; + end + else if(Enable==1'b1&&COUNT<=1) begin + state<=`Interrupt; + irq<=0; + end + else if(Enable==1'b1) begin + state<=`Counting; + COUNT<=COUNT-1; + irq<=0; + end + end + + `Interrupt: begin + if(Enable==1'b1) begin + irq<=1; + if(Mode==2'b00) begin + Enable<=0; + state<=`Idle; + end + else if(Mode==2'b01) begin + state<=`Counting; + COUNT<=PRESET; + end + end + end + endcase + end + //IRQ<=IM&&(Mode==2'b0)&&(COUNT==0); + IRQ<=IM&&irq; + case(Addr[3:2]) + 2'b00: begin + DataOut<={28'b0,IM,Mode,Enable}; + end + 2'b01: begin + DataOut<=PRESET; + end + 2'b10: begin + DataOut<=COUNT; + end + 2'b11: begin + DataOut<=0; + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DEV1.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DEV1.v" new file mode 100644 index 0000000000000000000000000000000000000000..61e4a2f11b44edbc2578118a8d20cc5405288282 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DEV1.v" @@ -0,0 +1,131 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:40:05 12/12/2018 +// Design Name: +// Module Name: DEV1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DEV1( + input clk, + input reset, + input [31:0] Addr, + input WE, + input [31:0] DataIn, + output reg [31:0] DataOut, + output reg IRQ + ); + + `define Idle 2'b00 + `define Counting 2'b01 + `define Interrupt 2'b10 + + reg[1:0] state; + reg[31:0] PRESET; + reg[31:0] COUNT; + reg[2:1] Mode; + reg IM; + reg Enable; + reg irq; + + always@(posedge clk) begin + if(reset) begin + PRESET<=0; + COUNT<=0; + state<=`Idle; + IM<=0; + Enable<=0; + irq<=0; + end + if(WE) begin + case(Addr) + 32'h0000_7f10: begin //ctrl + {IM,Mode,Enable} <= DataIn[3:0]; + //当计数器计数时，若计数器使能被 store 类指令修改为 0 则停止计数 + if(state == `Counting && DataIn[0]==1'b0) begin + COUNT<=PRESET; + end + end + 32'h0000_7f14: begin + PRESET<=DataIn; + end + 32'h0000_7f18: begin + + end + default: begin + + end + endcase + end + else begin + case(state) + `Idle: begin + if(Enable==1'b1) begin + state<=`Counting; + COUNT<=PRESET; + irq<=0; + end + else begin + state<=`Idle; + end + end + + `Counting: begin + if(Enable==1'b0) begin + state<=`Idle; + end + else if(Enable==1'b1&&COUNT<=1) begin + state<=`Interrupt; + irq<=0; + end + else if(Enable==1'b1) begin + state<=`Counting; + COUNT<=COUNT-1; + irq<=0; + end + end + + `Interrupt: begin + if(Enable==1'b1) begin + irq<=1; + if(Mode==2'b00) begin + Enable<=0; + state<=`Idle; + end + else if(Mode==2'b01) begin + state<=`Counting; + COUNT<=PRESET; + end + end + end + endcase + end + IRQ<=irq&&IM; + case({WE,Addr[3:2]}) + 3'b000: begin + DataOut<={28'b0,IM,Mode,Enable}; + end + 3'b001: begin + DataOut<=PRESET; + end + 3'b010: begin + DataOut<=COUNT; + end + 3'b011: begin + DataOut<=0; + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DataExt.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DataExt.v" new file mode 100644 index 0000000000000000000000000000000000000000..2b3947861b1773030df5b548e5966b3362f4296b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/DataExt.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 12/01/2018 +// Design Name: +// Module Name: DataExt +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DataExt( + input [31:0] Din, + input [2:0] dataOp, + input [1:0] Addr, + output reg[31:0] Dout + ); + + always@(*) begin + case(dataOp) + 3'b000: Dout<=Din; + 3'b001: begin//lbu + case(Addr) + 2'b00: Dout<={24'b0,Din[7:0]}; + 2'b01: Dout<={24'b0,Din[15:8]}; + 2'b10: Dout<={24'b0,Din[23:16]}; + 2'b11: Dout<={24'b0,Din[31:24]}; + endcase + end + 3'b010: begin//lb + case(Addr) + 2'b00: Dout<={{24{Din[7]}},Din[7:0]}; + 2'b01: Dout<={{24{Din[15]}},Din[15:8]}; + 2'b10: Dout<={{24{Din[23]}},Din[23:16]}; + 2'b11: Dout<={{24{Din[31]}},Din[31:24]}; + endcase + end + 3'b011: begin//lhu + case(Addr[1]) + 1'b0: Dout<={24'b0,Din[15:0]}; + 1'b1: Dout<={24'b0,Din[31:16]}; + endcase + end + 3'b100: begin//lh + case(Addr[1]) + 1'b0: Dout<={{16{Din[15]}},Din[15:0]}; + 1'b1: Dout<={{16{Din[31]}},Din[31:16]}; + endcase + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/EX.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/EX.v" new file mode 100644 index 0000000000000000000000000000000000000000..054aa54db731509a0074e784c5827ac77bf6397b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/EX.v" @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:21:31 11/23/2018 +// Design Name: +// Module Name: EX +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module EX( + input clk, + input reset, + input en, + input over, + input [31:0] IR_D, + input [31:0] PC_D, + input [31:0] PC4_D, + input [31:0] PC8_D, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EXT, + input Zero, + input more, + input less, + output reg[31:0] IR_E, + output reg[31:0] PC_E, + output reg[31:0] PC4_E, + output reg[31:0] PC8_E, + output reg[31:0] RS_E, + output reg[31:0] RT_E, + output reg[31:0] EXT_E, + output [6:2] excode_E, + output reg Zero_E, + output reg more_E, + output reg less_E + ); + + `define op 31:26 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define add 6'b100000 + `define sub 6'b100010 + `define addi 6'b001000 + + initial begin + IR_E <= 0; + end + + assign excode_E = ((IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu)&&over) ? 4 : + ((IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb)&&over) ? 5 : + (IR_E[`op]==`R&&(IR_E[`func]==`add||IR_E[`func]==`sub||IR_E[`func]==`addi)&&over) ? 12 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_E <= 32'h00000000; + end + else if(en) begin + IR_E <= IR_D; + PC_E <= PC_D; + PC4_E <= PC4_D; + PC8_E <= PC8_D; + RS_E <= RF_RD1; + RT_E <= RF_RD2; + EXT_E <= EXT; + Zero_E <= Zero; + more_E <= more; + less_E <= less; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ExcCode.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ExcCode.v" new file mode 100644 index 0000000000000000000000000000000000000000..5751fd1ac713acae06ec0bfc7f176f6b1873000b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ExcCode.v" @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 00:29:07 12/15/2018 +// Design Name: +// Module Name: ExcCode +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ExcCode( + input clk, + input reset, + input en, + input [4:0] ExcCodeIn, + output reg[4:0] ExcCodeOut + ); + + initial begin + ExcCodeOut<=0; + end + + always@(posedge clk) begin + if(reset) begin + ExcCodeOut<=0; + end + else if(en) begin + ExcCodeOut<=ExcCodeIn; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ID.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ID.v" new file mode 100644 index 0000000000000000000000000000000000000000..6f4f42c75aa53532df4e522e1fdc4bdac4b09b9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ID.v" @@ -0,0 +1,118 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:56:51 11/23/2018 +// Design Name: +// Module Name: ID +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ID( + input clk, + input reset, + input en, + input [31:0] Instr, + input [31:0] PC, + output reg[31:0] IR_D, + output reg[31:0] PC_D, + output reg[31:0] PC4_D, + output reg[31:0] PC8_D, + output [4:0] excode_D + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define j 6'b000010 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + initial begin + IR_D <= 0; + end + + wire RI;//译码异常 不认识的op func + assign RI = (IR_D[`op]==`j)||(IR_D[`op]==`jal) + ||(IR_D[`op]==`beq)||(IR_D[`op]==`bne)||(IR_D[`op]==`blez)||(IR_D[`op]==`bgtz)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00000)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00001) + ||IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu + ||IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu + ||IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb + ||(IR_D[`op]==6'b010000&&(IR_D[`rs]==5'b00000||IR_D[`rs]==5'b00100)) + ||(IR_D==32'h42000018) + ||(IR_D[`op]==`R&&(IR_D[`func]==`jr||IR_D[`func]==`jalr||IR_D[`func]==`addu||IR_D[`func]==`subu||IR_D[`func]==`add||IR_D[`func]==`sub||IR_D[`func]==`sll||IR_D[`func]==`srl||IR_D[`func]==`sra + ||IR_D[`func]==`sllv||IR_D[`func]==`srlv||IR_D[`func]==`srav||IR_D[`func]==`and_||IR_D[`func]==`or_||IR_D[`func]==`nor_||IR_D[`func]==`xor_||IR_D[`func]==`slt||IR_D[`func]==`sltu + ||IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu||IR_D[`func]==`mfhi||IR_D[`func]==`mflo||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)); + + assign excode_D = (RI==0) ? 10 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_D <= 32'h00000000; + end + else if(en) begin + IR_D <= Instr; + PC_D <= PC; + PC4_D <= PC+4; + PC8_D <= PC+8; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/MEM.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/MEM.v" new file mode 100644 index 0000000000000000000000000000000000000000..b85d5c05ef685643f157f17cda0f77adcd844440 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/MEM.v" @@ -0,0 +1,91 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:27:06 11/23/2018 +// Design Name: +// Module Name: MEM +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module MEM( + input clk, + input reset, + input en, + input [31:0] IR_E, + input [31:0] PC_E, + input [31:0] PC4_E, + input [31:0] PC8_E, + input [31:0] ALU, + input [31:0] Mult_Div, + input [31:0] RT_E, + input Zero_E, + input more_E, + input less_E, + output reg[31:0] IR_M, + output reg[31:0] PC_M, + output reg[31:0] PC4_M, + output reg[31:0] PC8_M, + output reg[31:0] AO_M, + output reg[31:0] MDO_M, + output reg[31:0] RT_M, + output [6:2] excode_M, + output reg Zero_M, + output reg more_M, + output reg less_M + ); + + `define op 31:26 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + + initial begin + IR_M <= 0; + end + + assign excode_M = ((IR_M[`op]==`lw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`lh&&AO_M[0]!=1'b0)||(IR_M[`op]==`lhu&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f0b&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| + ((IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 4 : + ((IR_M[`op]==`sw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`sh&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`sw||IR_M[`op]==`sb||IR_M[`op]==`sh)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f07&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| //不能向COUNT写 7f07 + ((IR_M[`op]==`sb||IR_M[`op]==`sh)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 5 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_M <= 32'h00000000; + end + else if(en) begin + IR_M <= IR_E; + PC_M <= PC_E; + PC4_M <= PC4_E; + PC8_M <= PC8_E; + AO_M <= ALU; + MDO_M <= Mult_Div; + RT_M <= RT_E; + Zero_M <= Zero_E; + more_M <= more_E; + less_M <= less_E; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/Mult_Div.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/Mult_Div.v" new file mode 100644 index 0000000000000000000000000000000000000000..17902f23aeb76b4e7bfc95d2ac782847068d23c8 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/Mult_Div.v" @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 11/30/2018 +// Design Name: +// Module Name: Mult_Div +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Mult_Div( + input clk, + input reset, + input [31:0] A, + input [31:0] B, + input [1:0] op, + input start, + input if_mthi, + input if_mtlo, + output reg Busy, + output [31:0] High, + output [31:0] Low + ); + reg [31:0] Hi; + reg [31:0] Lo; + assign High = Hi; + assign Low = Lo; + reg[31:0] cycles; + reg [63:0] tmp; + + initial begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + + always@(posedge clk) begin + if(reset) begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + else if(!Busy) begin + if(start) begin + case(op) + 2'b00: begin//mult + tmp<=$signed(A)*$signed(B); + cycles=5; + end + 2'b01: begin//multu + tmp<=A*B; + cycles=5; + end + 2'b10: begin//div + tmp<={$signed(A)%$signed(B),$signed(A)/$signed(B)}; + cycles=10; + end + 2'b11: begin//divu + tmp<={A%B,A/B}; + cycles=10; + end + endcase + Busy<=1; + end + if(if_mthi) begin + Hi<=A; + end + if(if_mtlo) begin + Lo<=A; + end + end + else if(Busy) begin + if(cycles>0) begin + cycles=cycles-1; + if(cycles==0) begin + {Hi,Lo}<=tmp; + Busy<=0; + end + end + end + end +endmodule \ No newline at end of file diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/WB.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/WB.v" new file mode 100644 index 0000000000000000000000000000000000000000..6ad1438e720b13966f9f1d7bbff398e41f1f031d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/WB.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:30:22 11/23/2018 +// Design Name: +// Module Name: WB +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module WB( + input clk, + input reset, + input en, + input [31:0] IR_M, + input [31:0] PC_M, + input [31:0] PC4_M, + input [31:0] PC8_M, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] DM, + input [31:0] CP0_M, + output reg[31:0] IR_W, + output reg[31:0] PC_W, + output reg[31:0] PC4_W, + output reg[31:0] PC8_W, + output reg[31:0] AO_W, + output reg[31:0] MDO_W, + output reg[31:0] DR_W, + output reg[31:0] CP0_W + ); + initial begin + IR_W <= 0; + end + always@(posedge clk) begin + if(reset) begin + IR_W <= 32'h00000000; + end + else if(en) begin + IR_W <= IR_M; + PC_W <= PC_M; + PC4_W <= PC4_M; + PC8_W <= PC8_M; + AO_W <= AO_M; + MDO_W <= MDO_M; + DR_W <= DM; + CP0_W <= CP0_M; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/alu.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/alu.v" new file mode 100644 index 0000000000000000000000000000000000000000..779fa26f44d1c9563d8acfa5e6eb6c115d67b156 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/alu.v" @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:01:30 11/23/2018 +// Design Name: +// Module Name: alu +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module alu( + input [31:0] A, + input [31:0] B, + input [3:0] ALUCtrl, + output reg[31:0] Result, + output over + ); + + reg[32:0] temp; + + assign over = (temp[32]!=temp[31]); + + always@(*) begin + case(ALUCtrl) + 4'b0000: begin + Result = A & B; + end + 4'b0001: begin + Result = A | B; + end + 4'b0010: begin + temp = {A[31],A[31:0]} + {B[31],B[31:0]}; + Result = A + B; + end + 4'b0011: begin + temp = {A[31],A[31:0]} - {B[31],B[31:0]}; + Result = A - B; + end + 4'b0100: begin + Result = A^B; + end + 4'b0101: begin + Result = ~(A|B); + end + 4'b0110: begin//sll sllv 逻辑左 + Result = B << A[4:0]; + end + 4'b0111: begin//srl srlv 逻辑右 + Result = B >> A[4:0]; + end + 4'b1000: begin//sra srav 算数右 + Result = $signed($signed(B) >>> A[4:0]); + end + 4'b1001: begin + Result = ($signed(A)<$signed(B)) ? 32'b1 : 32'b0; + end + 4'b1010: begin + Result = (A0) ? 1'b1 : 1'b0; + assign less = ($signed(D1)<0) ? 1'b1 : 1'b0; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/controller.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/controller.v" new file mode 100644 index 0000000000000000000000000000000000000000..097ebdd236cebd4bba9b639c9d30df8e4e6bef5d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/controller.v" @@ -0,0 +1,1330 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:53:56 11/24/2018 +// Design Name: +// Module Name: controller +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module controller( + input [5:0] op, + input [5:0] func, + input [4:0] rs, + input [4:0] rt, + output reg[3:0] ALUCtrl, + output reg[1:0] RegDst, + output reg ALUASrc, + output reg ALUBSrc, + output reg RegWrite, + output reg MemRead, + output reg MemWrite, + output reg [2:0] MemtoReg, + output reg [1:0]ExtOp, + output reg if_beq, + output reg if_bne, + output reg if_blez, + output reg if_bgez, + output reg if_bltz, + output reg if_bgtz, + output reg if_j, + output reg [1:0]PCsel, + output reg if_sh, + output reg if_sb, + output reg[2:0] dataOp, + output reg[1:0] multdivOp, + output reg start, + output reg if_mthi, + output reg if_mtlo, + output reg if_mfhi, + output reg if_mflo, + output reg if_1, + output reg if_2, + output reg if_3, + output reg cp0WE + ); + initial begin + PCsel <= 2'b00; + end + always@(*) + begin + case (op) + 6'b000000://R + begin + RegDst<=2'b01; + ALUBSrc<=0; + MemRead<=0; + MemWrite<=0; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + if_sh<=0; + if_sb<=0; + if_j<=0; + dataOp<=3'b000; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(func) + 6'b100001: begin //addu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100000: begin //add + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100011: begin //subu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100010: begin //sub + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100100: begin //and + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100101: begin //or + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100110: begin //xor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0100; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100111: begin //nor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0101; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001000: begin //jr + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001001: begin //jalr + ALUASrc<=0; + MemtoReg<=3'b010; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000000: begin //sll nop + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000100: begin //sllv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000010: begin //srl + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000110: begin //srlv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000011: begin //sra + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000111: begin //srav + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101010: begin //slt + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101011: begin //sltu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011000: begin //mult + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011001: begin //multu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b01; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011010: begin //div + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b10; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011011: begin //divu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b11; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010000: begin //mfhi + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=1; + if_mflo<=0; + end + 6'b010010: begin //mflo + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=1; + end + 6'b010001: begin //mthi + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=1; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010011: begin //mtlo + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=1; + if_mfhi<=0; + if_mflo<=0; + end + default: begin + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + endcase + end + 6'b100011://lw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100000://lb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b010; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100100://lbu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b001; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100001://lh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b100; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100101://lhu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b011; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101011://sw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101001://sh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=1; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101000://sb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=1; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000100://beq + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=1; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000101://bne + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=1; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000111://bgtz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=1; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000110://blez + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=1; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000001://bgez/bltz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(rt) + 5'b00001:begin//bgez + if_bgez<=1; + if_bltz<=0; + end + 5'b00000:begin//bltz + if_bgez<=0; + if_bltz<=1; + end + default:begin + if_bgez<=0; + if_bltz<=0; + end + endcase + end + + 6'b001111://lui + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b10; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001101://ori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001010://slti + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001011://sltiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001100://andi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001110://xori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0100; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001001://addiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001000://addi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000011://jal + begin + RegDst<=2'b10; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b010; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000010://j + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b010000: + begin + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ExtOp<=2'b00; + ALUCtrl<=4'b0000; + ALUASrc<=0; + ALUBSrc<=0; + if_j<=0; + MemRead<=0; + MemWrite<=0; + RegDst<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + case(rs) + 5'b00100: //mtc0 + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b00; + cp0WE<=1; + end + 5'b00000: //mfc0 + begin + RegWrite<=1; + MemtoReg<=3'b100; + PCsel<=2'b00; + cp0WE<=0; + end + default: + begin + + end + endcase + case(func) + 6'b011000://eret + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b11; + cp0WE<=0; + end + default: begin + + end + endcase + end + + default: + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/dm.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/dm.v" new file mode 100644 index 0000000000000000000000000000000000000000..8dc235f6441786a2939b96423488a07d442966e3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/dm.v" @@ -0,0 +1,89 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:57 11/23/2018 +// Design Name: +// Module Name: dm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dm( + input clk, + input reset, + input MemWrite, + input MemRead, + input if_sh, + input if_sb, + input [31:0] MemAddr, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD + ); + + reg[31:0] dm[0:4095]; + integer i; + initial begin + for(i=0;i<4096;i=i+1) begin //1024 + dm[i]<=0; + end + end + + assign RD = MemRead ? dm[MemAddr[13:2]] : 0; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<4096;i=i+1) begin//1024 + dm[i]<=0; + end + end + else begin + if(MemWrite) begin + if(if_sh) begin + if(MemAddr[1]==1'b1) begin + dm[MemAddr[13:2]][31:16] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[15:0],dm[MemAddr[13:2]][15:0]}); + end + else if(MemAddr[1]==1'b0) begin + dm[MemAddr[13:2]][15:0] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[15:0]}); + end + end + else if(if_sb) begin + case(MemAddr[1:0]) + 2'b00: begin + dm[MemAddr[13:2]][7:0] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:8],WD[7:0]}); + end + 2'b01: begin + dm[MemAddr[13:2]][15:8] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[7:0],dm[MemAddr[13:2]][7:0]}); + end + 2'b10: begin + dm[MemAddr[13:2]][23:16] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:24],WD[7:0],dm[MemAddr[13:2]][15:0]}); + end + 2'b11: begin + dm[MemAddr[13:2]][31:24] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[7:0],dm[MemAddr[13:2]][23:0]}); + end + endcase + end + else begin + dm[MemAddr[13:2]] <= WD; + $display("%d@%h: *%h <= %h",$time,PC,MemAddr,WD); + end + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ext.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ext.v" new file mode 100644 index 0000000000000000000000000000000000000000..ab616813a96964cd24ece2c94644f7d546a4fafe --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/ext.v" @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:59:19 11/23/2018 +// Design Name: +// Module Name: ext +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ext( + input [15:0] in, + input [1:0] ExtOp, + output reg [31:0] out + ); + + always@(*) begin + case(ExtOp) + 2'b00: out <= {{16{in[15]}},in}; + 2'b01: out <= {{16{1'b0}},in}; + 2'b10: out <= {in,{16{1'b0}}}; + 2'b11: out <= 0; + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/forward_mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/forward_mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..fd11f054c798b464df7a722b129173f8280ec259 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/forward_mux.v" @@ -0,0 +1,117 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:34 11/24/2018 +// Design Name: +// Module Name: forward_mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module forward_mux( + input [31:0] RS_E, + input [31:0] RT_E, + input [31:0] RT_M, + input [31:0] WD, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] CP0_M, + input [31:0] MD_out, + input [31:0] PC8_E, + input [31:0] PC8_M, + input [31:0] PC8_W, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EPCout, + input [2:0] ForwardRSD, + input [2:0] ForwardRTD, + input [2:0] ForwardRSE, + input [2:0] ForwardRTE, + input [2:0] ForwardRTM, + input [2:0] ForwardERET, + output reg[31:0] MFRSD, + output reg[31:0] MFRTD, + output reg[31:0] MFRSE, + output reg[31:0] MFRTE, + output reg[31:0] MFRTM, + output reg[31:0] MFERET + ); + + always@(*) begin + case(ForwardRSD) + 3'b000 : MFRSD <= RF_RD1; + 3'b001 : MFRSD <= AO_M; + 3'b010 : MFRSD <= WD; + 3'b011 : MFRSD <= PC8_E; + 3'b100 : MFRSD <= PC8_M; + 3'b101 : MFRSD <= CP0_M; + 3'b110 : MFRSD <= MD_out; + 3'b111 : MFRSD <= MDO_M; + default : MFRSD <= 0; + endcase + + case(ForwardRTD) + 0: MFRTD <= RF_RD2; + 1: MFRTD <= AO_M; + 2: MFRTD <= WD; + 3: MFRTD <= PC8_E; + 4: MFRTD <= PC8_M; + 5: MFRTD <= CP0_M; + 6: MFRTD <= MD_out; + 7: MFRTD <= MDO_M; + default: MFRTD <= 0; + endcase + + case(ForwardRSE) + 0:MFRSE <= RS_E; + 1:MFRSE <= AO_M; + 2:MFRSE <= WD; + 3:MFRSE <= 0; + 4:MFRSE <= PC8_M; + 5:MFRSE <= CP0_M; + 6:MFRSE <= 0; + 7:MFRSE <= MDO_M; + default:MFRSE <= 0; + endcase + + case(ForwardRTE) + 0:MFRTE <= RT_E; + 1:MFRTE <= AO_M; + 2:MFRTE <= WD; + 3:MFRTE <= 0; + 4:MFRTE <= PC8_M; + 5:MFRTE <= CP0_M; + 6:MFRTE <= 0; + 7:MFRTE <= MDO_M; + default:MFRTE <= 0; + endcase + + case(ForwardRTM) + 0:MFRTM <= RT_M; + 1:MFRTM <= 0; + 2:MFRTM <= WD; + 3:MFRTM <= 0; + 4:MFRTM <= 0; + 5:MFRTM <= 0; + 6:MFRTM <= 0; + 7:MFRTM <= 0; + default:MFRTM <= 0; + endcase + + case(ForwardERET) + 0:MFERET <= EPCout; + 1:MFERET <= MFRTM; + default:MFERET <= 0; + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/grf.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/grf.v" new file mode 100644 index 0000000000000000000000000000000000000000..90307bafbb30dc6650cbb3441f5711e3396f9a9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/grf.v" @@ -0,0 +1,59 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:24 11/23/2018 +// Design Name: +// Module Name: grf +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module grf( + input clk, + input reset, + input RegWrite, + input [4:0] RA1, + input [4:0] RA2, + input [4:0] WA, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD1, + output [31:0] RD2 + ); + + reg[31:0] register[31:0]; + integer i; + initial begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + + assign RD1 = register[RA1]; + assign RD2 = register[RA2]; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + else begin + if(RegWrite&&WA!=5'b00000) begin + register[WA] <= WD; + //$display("@%h: $%d <= %h", PC, WA,WD); + $display("%d@%h: $%d <= %h",$time,PC,WA,WD); + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/hazardUnit.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/hazardUnit.v" new file mode 100644 index 0000000000000000000000000000000000000000..14bd798e84ac5caaaa3a6f3e5a3d60a39869d4d3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/hazardUnit.v" @@ -0,0 +1,271 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:55:59 11/24/2018 +// Design Name: +// Module Name: hazardUnit +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module hazardUnit( + input [31:0] IR_D, + input [31:0] IR_E, + input [31:0] IR_M, + input [31:0] IR_W, + input Busy, + input start, + output IR_D_en, + output IR_E_clr, + output PC_en, + output [2:0]ForwardRSD, + output [2:0]ForwardRTD, + output [2:0]ForwardRSE, + output [2:0]ForwardRTE, + output [2:0]ForwardRTM, + output [2:0]ForwardERET + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + `define cal_r_D (IR_D[`op]==`R&&IR_D[`func]!=`jalr&&IR_D[`func]!=`jr&&IR_D[`func]!=`mfhi&&IR_D[`func]!=`mflo&&IR_D!=0) + `define cal_r_E (IR_E[`op]==`R&&IR_E[`func]!=`jalr&&IR_E[`func]!=`jr&&IR_E[`func]!=`mfhi&&IR_E[`func]!=`mflo&&IR_E!=0) + `define cal_r_M (IR_M[`op]==`R&&IR_M[`func]!=`jalr&&IR_M[`func]!=`jr&&IR_M[`func]!=`mfhi&&IR_M[`func]!=`mflo&&IR_M!=0) + `define cal_r_W (IR_W[`op]==`R&&IR_W[`func]!=`jalr&&IR_W[`func]!=`jr&&IR_W[`func]!=`mfhi&&IR_W[`func]!=`mflo&&IR_W!=0) + + `define cal_i_D (IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu) + `define cal_i_E (IR_E[`op]==`lui||IR_E[`op]==`ori||IR_E[`op]==`addi||IR_E[`op]==`addiu||IR_E[`op]==`andi||IR_E[`op]==`xori||IR_E[`op]==`slti||IR_E[`op]==`sltiu) + `define cal_i_M (IR_M[`op]==`lui||IR_M[`op]==`ori||IR_M[`op]==`addi||IR_M[`op]==`addiu||IR_M[`op]==`andi||IR_M[`op]==`xori||IR_M[`op]==`slti||IR_M[`op]==`sltiu) + `define cal_i_W (IR_W[`op]==`lui||IR_W[`op]==`ori||IR_W[`op]==`addi||IR_W[`op]==`addiu||IR_W[`op]==`andi||IR_W[`op]==`xori||IR_W[`op]==`slti||IR_W[`op]==`sltiu) + + `define load_D (IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu) + `define load_E (IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu) + `define load_M (IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu) + `define load_W (IR_W[`op]==`lw||IR_W[`op]==`lb||IR_W[`op]==`lbu||IR_W[`op]==`lh||IR_W[`op]==`lhu) + + `define store_D (IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb) + `define store_E (IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb) + `define store_M (IR_M[`op]==`sw||IR_M[`op]==`sh||IR_M[`op]==`sb) + `define store_W (IR_W[`op]==`sw||IR_W[`op]==`sh||IR_W[`op]==`sb) + + `define beq_D (IR_D[`op]==`beq||IR_D[`op]==`bne||IR_D[`op]==`bgtz||IR_D[`op]==`blez||(IR_D[`op]==6'b000001&&(IR_D[`rt]==5'b00000||IR_D[`rt]==5'b00001))) + `define beq_E (IR_E[`op]==`beq||IR_E[`op]==`bne||IR_E[`op]==`bgtz||IR_E[`op]==`blez||(IR_E[`op]==6'b000001&&(IR_E[`rt]==5'b00000||IR_E[`rt]==5'b00001))) + `define beq_M (IR_M[`op]==`beq||IR_M[`op]==`bne||IR_M[`op]==`bgtz||IR_M[`op]==`blez||(IR_M[`op]==6'b000001&&(IR_M[`rt]==5'b00000||IR_M[`rt]==5'b00001))) + `define beq_W (IR_W[`op]==`beq||IR_W[`op]==`bne||IR_W[`op]==`bgtz||IR_W[`op]==`blez||(IR_W[`op]==6'b000001&&(IR_W[`rt]==5'b00000||IR_W[`rt]==5'b00001))) + + `define jal_D (IR_D[`op]==`jal) + `define jal_E (IR_E[`op]==`jal) + `define jal_M (IR_M[`op]==`jal) + `define jal_W (IR_W[`op]==`jal) + + `define jalr_D (IR_D[`op]==`R&&IR_D[`func]==`jalr) + `define jalr_E (IR_E[`op]==`R&&IR_E[`func]==`jalr) + `define jalr_M (IR_M[`op]==`R&&IR_M[`func]==`jalr) + `define jalr_W (IR_W[`op]==`R&&IR_W[`func]==`jalr) + + `define jr_D (IR_D[`op]==`R&&IR_D[`func]==`jr) + `define jr_E (IR_E[`op]==`R&&IR_E[`func]==`jr) + `define jr_M (IR_M[`op]==`R&&IR_M[`func]==`jr) + `define jr_W (IR_W[`op]==`R&&IR_W[`func]==`jr) + + `define mfhi_D (IR_D[`op]==`R&&IR_D[`func]==`mfhi) + `define mfhi_E (IR_E[`op]==`R&&IR_E[`func]==`mfhi) + `define mfhi_M (IR_M[`op]==`R&&IR_M[`func]==`mfhi) + `define mfhi_W (IR_W[`op]==`R&&IR_W[`func]==`mfhi) + + `define mflo_D (IR_D[`op]==`R&&IR_D[`func]==`mflo) + `define mflo_E (IR_E[`op]==`R&&IR_E[`func]==`mflo) + `define mflo_M (IR_M[`op]==`R&&IR_M[`func]==`mflo) + `define mflo_W (IR_W[`op]==`R&&IR_W[`func]==`mflo) + + `define mf_D (`mfhi_D||`mflo_D) + `define mf_E (`mfhi_E||`mflo_E) + `define mf_M (`mfhi_M||`mflo_M) + `define mf_W (`mfhi_W||`mflo_W) + + `define mfc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00000) + `define mfc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00000) + `define mfc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00000) + `define mfc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00000) + + `define mtc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00100) + `define mtc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100) + `define mtc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100) + `define mtc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00100) + + reg stall=0; + wire stall_b,stall_cal_r,stall_cal_i,stall_load,stall_store,stall_jr,stall_jalr,stall_busy,stall_mfmt,stall_eret; + + assign stall_b = (`beq_D & `cal_r_E & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0||IR_D[`rt]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`beq_D & `cal_i_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_M & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0||IR_D[`rt]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_cal_r = (`cal_r_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_cal_i = (`cal_i_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_load = (`load_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_store = (`store_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_jr = (`jr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_jalr = (`jalr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jalr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_busy = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) & (Busy||start); + //assign stall_mfmt = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + // IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) + // &(IR_E[`op]==`R&(IR_E[`func]==`mult||IR_E[`func]==`multu||IR_E[`func]==`div||IR_E[`func]==`divu)); + assign stall_eret = (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100&&IR_E[`rd]==14)&&IR_D==32'h42000018; + always@(*) begin + stall <= stall_b||stall_cal_r||stall_cal_i||stall_load||stall_store||stall_jr||stall_jalr||stall_busy||stall_eret; + end + + assign IR_D_en = !stall; + assign IR_E_clr = stall; + assign PC_en = !stall; + + `define RSD (`cal_r_D||`cal_i_D||`load_D||`store_D||`beq_D||`jr_D||`jalr_D) + `define RTD (`cal_r_D||`store_D||`beq_D||`mtc0_D) + `define RSE (`cal_r_E||`cal_i_E||`load_E||`store_E) + `define RTE (`cal_r_E||`store_E||`mtc0_E) + `define RTM (`store_M||`mtc0_M) + + assign ForwardRSD = (`RSD & `jal_E & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 3 : + (`RSD & `jalr_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 3 : + (`RSD & `mf_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 6 : + (`RSD & `cal_r_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 1 : + (`RSD & `cal_i_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 1 : + (`RSD & `jal_M & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 4 : + (`RSD & `jalr_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 4 : + (`RSD & `mf_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 5 : + (`RSD & `mfc0_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 7 : + (`RSD & `cal_r_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `cal_i_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `load_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mf_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mfc0_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `jal_W & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 2 : + (`RSD & `jalr_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : 0 ; + + assign ForwardRTD = (`RTD & `jal_E & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 3 : + (`RTD & `jalr_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 3 : + (`RTD & `mf_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 6 : + (`RTD & `cal_r_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 1 : + (`RTD & `cal_i_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 1 : + (`RTD & `jal_M & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 4 : + (`RTD & `jalr_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 4 : + (`RTD & `mf_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 7 : + (`RTD & `mfc0_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 5 : + (`RTD & `cal_r_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `cal_i_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `load_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mf_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mfc0_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `jal_W & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 2 : + (`RTD & `jalr_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : 0; + + assign ForwardRSE = (`RSE & `cal_r_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `cal_i_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `jal_M & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 4 : + (`RSE & `jalr_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 4 : + (`RSE & `mf_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 7 : + (`RSE & `mfc0_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 5 : + (`RSE & `cal_r_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `cal_i_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `load_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mf_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mfc0_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jal_W & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jalr_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : 0; + + assign ForwardRTE = (`RTE & `cal_r_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `cal_i_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `jal_M & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 4 : + (`RTE & `jalr_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 4 : + (`RTE & `mf_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 7 : + (`RTE & `mfc0_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 5 : + (`RTE & `cal_r_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `cal_i_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `load_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mf_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mfc0_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jal_W & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jalr_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : 0; + + assign ForwardRTM = (`RTM & `cal_r_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `cal_i_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `load_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mf_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mfc0_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jal_W & (IR_M[`rt]==31) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jalr_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : 0; + + assign ForwardERET = ((IR_D==32'h42000018)&&(IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100&&IR_M[`rd]==14)) ? 1 : 0; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/im.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/im.v" new file mode 100644 index 0000000000000000000000000000000000000000..5743ec5f2b17e42b6512c62f08070c6b86a83cca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/im.v" @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:01 11/23/2018 +// Design Name: +// Module Name: im +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module im( + input [31:0] PC, + output[31:0] instruction + ); + + reg[31:0] im[0:4095]; + initial begin + $readmemh("code.txt",im); + $readmemh("code_handler.txt",im,1120,2047); + end + + wire[31:0] pc=PC-32'h00003000; + assign instruction = im[pc[13:2]]; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/mips.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/mips.v" new file mode 100644 index 0000000000000000000000000000000000000000..d011fae91ff309813c5ac4a0812a1a4f11c36a74 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/mips.v" @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:46:09 11/23/2018 +// Design Name: +// Module Name: mips +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mips( + input clk, + input reset + ); + + wire [31:0] PrRD; + wire [6:2] ExcCode; + wire [31:0] PrAddr; + wire [31:0] PrWD; + wire PrWe; + wire [31:0] DEV_Addr; + wire [31:0] DEV_WD; + wire [31:0] DEV0_RD; + wire [31:0] DEV1_RD; + wire WeDEV0; + wire WeDEV1; + wire IRQ0; + wire IRQ1; + + CPU my_CPU(.clk(clk),.reset(reset),.HWInt({4'b0,IRQ1,IRQ0}),.PrRD(PrRD),.ExcCode(ExcCode),.PrAddr(PrAddr),.PrWD(PrWD),.PrWe(PrWe)); + Bridge my_Bridge(PrAddr,PrWe,PrRD,PrWD,DEV_Addr,DEV_WD,DEV0_RD,DEV1_RD,WeDEV0,WeDEV1); + DEV0 my_time0(clk,reset,DEV_Addr,WeDEV0,DEV_WD,DEV0_RD,IRQ0); + DEV1 my_time1(clk,reset,DEV_Addr,WeDEV1,DEV_WD,DEV1_RD,IRQ1); + + assign ExcCode = (IRQ0||IRQ1) ? 5'b00000 : 5'b11111; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..02d800057a121623b1cb76181c21a974d0f6e996 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/mux.v" @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:31:53 11/23/2018 +// Design Name: +// Module Name: mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux( + input [31:0] EXT_E, + input [31:0] IR_E, + input [31:0] IR_W, + input [31:0] DR_Wnew, + input [31:0] AO_W, + input [31:0] MDO_W, + input [31:0] PC8_W, + input [31:0] CP0_W, + input [31:0] MFRSE, + input [31:0] MFRTE, + input [31:0] High, + input [31:0] Low, + input ALUasel, + input ALUbsel, + input if_mfhi, + input if_mflo, + input [1:0] RegDst, + input [2:0] MemtoReg, + output reg[31:0] ALU_A, + output reg[31:0] ALU_B, + output reg[4:0] MUX_A3, + output reg[31:0] MUX_WD, + output reg[31:0] MD_out + ); + + always@(*) begin + case(ALUasel) + 1'b0: ALU_A<=MFRSE; + 1'b1: ALU_A<={27'b0,IR_E[10:6]}; + endcase + + case(ALUbsel) + 1'b0: ALU_B<=MFRTE; + 1'b1: ALU_B<=EXT_E; + endcase + + case(RegDst) + 2'b00: MUX_A3<=IR_W[20:16]; + 2'b01: MUX_A3<=IR_W[15:11]; + 2'b10: MUX_A3<=32'h1f; + 2'b11: MUX_A3<=0; + endcase + + case(MemtoReg) + 3'b000: MUX_WD<=AO_W; + 3'b001: MUX_WD<=DR_Wnew; + 3'b010: MUX_WD<=PC8_W; + 3'b011: MUX_WD<=MDO_W; + 3'b100: MUX_WD<=CP0_W; + endcase + + if(if_mfhi) MD_out<=High; + else if(if_mflo) MD_out<=Low; + else MD_out<=0; + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/npc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/npc.v" new file mode 100644 index 0000000000000000000000000000000000000000..2326b32486b61ad162e0643debbddbdf4235c924 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/npc.v" @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:13:22 11/23/2018 +// Design Name: +// Module Name: npc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module npc( + input [31:0] PC4, + input [31:0] PC4D, + input [25:0] I26, + input [31:0] MFRSD, + input [31:0] EPC, + input Zero, + input more, + input less, + input if_beq, + input if_bne, + input if_bgtz, + input if_blez, + input if_bgez, + input if_bltz, + input if_j,//j或jal + input[1:0] PC_sel, + input Interrupt, + output reg[31:0] next_pc + ); + reg[31:0] NPC; + always@(*) begin + if((if_beq&&Zero)||(if_bne&&!Zero)||(if_bgtz&&more)||(if_blez&&!more)||(if_bgez&&!less)||(if_bltz&&less)) begin + NPC<=PC4D+{{14{I26[15]}},I26[15:0],2'b00}; + end + else if(if_j) begin + NPC<={PC4D[31:28],I26[25:0],2'b00}; + end + else begin + NPC<=PC4D+4; + end + case(PC_sel) + 2'b00: next_pc<=PC4; + 2'b01: next_pc<=MFRSD; + 2'b10: next_pc<=NPC; + 2'b11: next_pc<=EPC; + endcase + if(Interrupt) begin + next_pc<=32'h00004180; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/pc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/pc.v" new file mode 100644 index 0000000000000000000000000000000000000000..06a0733bb46e61a82eeecb3b568f77b00d2eea5a --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/pc.v" @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:00 11/23/2018 +// Design Name: +// Module Name: pc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module pc( + input clk, + input reset, + input en, + input[31:0] next_pc, + output reg[31:0] pc, + output [4:0] excode_F + ); + + initial begin + pc<=32'h00003000; + end + + assign excode_F = ((pc[1:0]!=2'b00)||(pc < 32'h00003000)||(pc > 32'h00004ffc)) ? 4 : 0; + + always@(posedge clk) begin + if(reset) begin + pc <= 32'h00003000; + end + else if(en) begin + pc <= next_pc; + end + else begin + pc <= pc; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/test.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/test.v" new file mode 100644 index 0000000000000000000000000000000000000000..e5caf7ea5fe230bbd63b23a8c12df7473769acca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_7/test.v" @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:00 11/25/2018 +// Design Name: mips +// Module Name: E:/Verilog/p5/test.v +// Project Name: p5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: mips +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module test; + + // Inputs + reg clk; + reg reset; + + // Instantiate the Unit Under Test (UUT) + mips uut ( + .clk(clk), + .reset(reset) + ); + + initial begin + clk = 0; + reset = 1; + #12 reset = 0; + end + + always #10 clk = ~clk; + + +endmodule + + diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/Bridge.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/Bridge.v" new file mode 100644 index 0000000000000000000000000000000000000000..dd788614ad6e56748e6d45767d860c460250ba97 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/Bridge.v" @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:11 12/12/2018 +// Design Name: +// Module Name: Bridge +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bridge( + input [31:0] PrAddr, + input PrWE, + output [31:0] PrRD, + input [31:0] PrWD, + output [31:0] DEV_Addr, + output [31:0] DEV_WD, + input [31:0] DEV0_RD, + input [31:0] DEV1_RD, + output WeDEV0, + output WeDEV1 + ); + + `define DEBUG_DEV_DATA 32'b0 + + //DEV0 00007F00-00007F0B + //DEV1 00007F10-00007F1B + wire HitDEV0,HitDEV1; + assign HitDEV0 = (PrAddr[31:4]==28'h00007F0); + assign HitDEV1 = (PrAddr[31:4]==28'h00007F1); + + assign PrRD = (HitDEV0) ? DEV0_RD : + (HitDEV1) ? DEV1_RD : + `DEBUG_DEV_DATA; + + assign WeDEV0 = PrWE&&HitDEV0; + assign WeDEV1 = PrWE&&HitDEV1; + + assign DEV_Addr = PrAddr; + assign DEV_WD = PrWD; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/CP0.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/CP0.v" new file mode 100644 index 0000000000000000000000000000000000000000..4afb24e30f922fc2192647edecb864d0c40ac909 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/CP0.v" @@ -0,0 +1,136 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:46:14 12/13/2018 +// Design Name: +// Module Name: CP0 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CP0( + input[4:0] A1,//读CP0寄存器编号 执行MFC0指令时产生 + input[4:0] A2,//写CP0寄存器编号 执行MTC0指令时产生 + input[31:0] DIn,//CP0寄存器的写入数据 执行MTC0指令时产生 数据来自GPR + input[31:0] PC,//中断/异常时的PC + input[31:0] IR_M,//指令 + input Zero, + input more, + input less, + input if_bd, + input[6:2] ExcCode,//中断/异常的类型 + input[5:0] HWInt,//6个设备中断 + input We,//CP0写使能 执行MTC0指令时产生 + input EXLSet,//用于置位SR的EXL(EXL为1) 流水线在M阶段产生 + input EXLClr,//用于清除SR的EXL(EXL为0) 执行ERET指令时产生 + input clk, + input reset, + output Interrupt,//中断和异常 是HWInt/IM/EXL/IE的函数 + output[31:0] EPC,//EPC寄存器输出至NPC + output[31:0] DOut //CP0寄存器的输出数据 执行MFC0指令时产生，输出数据至GRF + ); + + `define SR 12 + `define CAUSE 13 + `define EPC 14 + `define PRID 15 + + `define R 6'b000000 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define jr 6'b001000 + `define j 6'b000010 + `define jalr 6'b001001 + + //SR {16'b0, im, 8'b0, exl, ie} + reg[15:10] im; //6位中断屏蔽位，分别对应6个外部中断 1-允许中断，0-禁止中断 + reg exl;//EXL：异常级 1-进入异常，不允许再中断；0-允许中断 + reg ie;//全局中断使能 1-允许中断；0-禁止中断 + //CAUSE {bd, 15'b0, hwint_pend[15:10], 3'b0, exccode[6:2], 2'b0} + reg bd;//异常发生在延迟槽的指令的话 bd=1 + reg[6:2] exccode; + reg[15:10] hwint_pend;//在clock上升沿不断的保存外部6个中断(HWInt[5:0]) + //EPC + reg[31:0] epc; + //PRID + reg[31:0] prid = 32'h12345678; + wire Exception;//异常 + wire IntReq;//中断 + assign EPC = epc; + //读 除了SR/Cause/EPC/PRId外，不用的寄存器一律输出0 + assign DOut = (A1==`SR) ? {16'b0, im, 8'b0, exl, ie} : + (A1==`CAUSE) ? {bd, 15'b0, hwint_pend[15:10], 3'b0, exccode[6:2], 2'b0} : + (A1==`EPC) ? epc : + (A1==`PRID) ? prid : 0; + assign IntReq = (|(HWInt[5:0] & im[15:10])) & ie & !exl ; + assign Exception = (ExcCode>0) ? 1'b1 : 1'b0; + assign Interrupt = IntReq||Exception; + + integer i; + always@(posedge clk) begin + hwint_pend <= HWInt;//在clock上升沿不断的保存外部6个中断(HWInt[5:0]) + if(reset) begin + im<=6'b0;//SR + exl<=1'b0; + ie<=1'b0; + hwint_pend<=6'b0;//CAUSE + bd<=0; + exccode<=0; + epc<=0;//EPC + end + else begin + epc <= (Interrupt&&bd) ? {PC[31:2], 2'b00} - 4 : + (Interrupt&&!bd) ? {PC[31:2], 2'b00} : + epc; + if(bd==1'b0) begin + bd <= (((IR_M[31:26]==`j)||(IR_M[31:26]==`jal)||(IR_M[31:26]==`beq&&Zero)||(IR_M[31:26]==`bne&&!Zero)||(IR_M[31:26]==`blez&&!more)||(IR_M[31:26]==`bgtz&&more) + ||(IR_M[31:26]==`R&&(IR_M[5:0]==`jr||IR_M[5:0]==`jalr))||(IR_M[31:26]==6'b000001&&IR_M[20:16]==5'b00000&&less)||(IR_M[31:26]==6'b000001&&IR_M[20:16]==5'b00001&&!less))); + end + else begin + if(exl==1'b0&&Interrupt==1'b0) bd<=1'b0; + end + if(We) begin //写入 + case(A2) + `SR: begin + {im, exl, ie} <= {DIn[15:10], DIn[1], DIn[0]}; + end + `CAUSE: begin + hwint_pend <= DIn[15:10]; + end + `EPC: begin + epc <= DIn; + end + `PRID: begin + prid <= DIn; + end + default: begin + end + endcase + end + if(EXLSet||Interrupt) begin + exl<=1'b1; + exccode<=ExcCode; + end + if(EXLClr) begin + exl<=1'b0; + bd<=1'b0; + end + //if(IntReq) begin + // bd<=1'b0; + //end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/CPU.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/CPU.v" new file mode 100644 index 0000000000000000000000000000000000000000..41e2a8b129092d09ff758d86dd4709b0d6ce2ece --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/CPU.v" @@ -0,0 +1,212 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:30:40 12/15/2018 +// Design Name: +// Module Name: CPU +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CPU( + input clk, + input reset, + input [7:2] HWInt, + input [31:0] PrRD, + input [6:2] ExcCode, + output [31:0] PrAddr, + output [31:0] PrWD, + output PrWe + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + `define imm26 25:0 + + wire PC_en; + wire[1:0] PC_sel; + wire[31:0] PC; + wire[31:0] PC4; + wire[31:0] Instr; + wire ID_en; + wire EX_en; + wire MEM_en; + wire WB_en; + wire ID_reset; + wire EX_reset; + wire MEM_reset; + wire WB_reset; + wire[31:0] IR_D; + wire[31:0] PC_D; + wire[31:0] PC4_D; + wire[31:0] PC8_D; + wire[31:0] IR_E; + wire[31:0] PC_E; + wire[31:0] PC4_E; + wire[31:0] PC8_E; + wire[31:0] IR_M; + wire[31:0] PC_M; + wire[31:0] PC4_M; + wire[31:0] PC8_M; + wire[31:0] IR_W; + wire[31:0] PC_W; + wire[31:0] PC4_W; + wire[31:0] PC8_W; + wire Zero; + wire Zero_E; + wire Zero_M; + wire more; + wire less; + wire more_E; + wire less_E; + wire more_M; + wire less_M; + wire if_beq; + wire if_bne; + wire if_blez; + wire if_bgtz; + wire if_bltz; + wire if_bgez; + wire if_j; + wire[1:0] EXTop; + wire if_sh; + wire if_sb; + + wire[3:0] ALUCtrl; + wire[1:0] RegDst; + wire ALUASrc; + wire ALUBSrc; + wire RegWrite; + wire MemRead; + wire MemWrite; + wire [2:0] MemtoReg; + wire [2:0] dataOp; + wire [1:0] multdivOp; + wire if_mthi; + wire if_mtlo; + wire if_mfhi; + wire if_mflo; + wire start; + wire Busy; + wire[31:0] High; + wire[31:0] Low; + + wire [31:0] RS_E; + wire [31:0] RT_E; + wire [31:0] EXT_E; + wire [31:0] AO_M; + wire [31:0] MDO_M; + wire [31:0] RT_M; + wire [31:0] DR_W; + wire [31:0] DR_Wnew; + wire [31:0] AO_W; + wire [31:0] MDO_W; + + wire[4:0] MUX_A3; + wire[31:0] MUX_WD; + wire[31:0] RF_RD1; + wire[31:0] RF_RD2; + wire[31:0] MFRSD; + wire[31:0] MFRTD; + wire[31:0] MFRSE; + wire[31:0] MFRTE; + wire[31:0] MFRTM; + wire[31:0] MFERET; + wire[31:0] EXT_out; + wire[31:0] ALU_A; + wire[31:0] ALU_B; + wire[31:0] ALU_out; + wire[31:0] MD_out; + wire[31:0] DM_out; + wire[31:0] next_pc; + wire[2:0] ForwardRSD; + wire[2:0] ForwardRTD; + wire[2:0] ForwardRSE; + wire[2:0] ForwardRTE; + wire[2:0] ForwardRTM; + wire[2:0] ForwardERET; + + assign EX_en = 1; + assign MEM_en = 1; + assign WB_en = 1; + assign ID_reset = 0; + assign MEM_reset = 0; + assign WB_reset = 0; + assign PC4 = PC + 4; + + wire[6:2] excode_F,excode_D,excode_E,excode_M; + wire[6:2] excode_outF,excode_outD,excode_outE,excode_outM; + wire over; + wire cp0WE; + wire[31:0] CP0_M; + wire[31:0] CP0_W; + wire[31:0] EPCout; + wire Interrupt; + wire EXLSet; + wire EXLClr; + wire[31:0] DMDEV; + wire if_eret; + + assign PrAddr = AO_M; + assign PrWD = MFRTM; + assign PrWe = (MemWrite&&(~Interrupt));//没出现异常才可以写 + assign EXLSet = Interrupt; + assign EXLClr = (IR_M[`op]==6'b010000&&IR_M[`func]==6'b011000); //eret + + pc my_pc(clk,reset,PC_en||Interrupt,next_pc,PC,excode_F); + im my_im(PC,Instr); + + ID my_ID(clk,(ID_reset||reset||Interrupt||(IR_D==32'h42000018&&ID_en)),ID_en,Instr,PC,IR_D,PC_D,PC4_D,PC8_D,excode_D); + ExcCode my_exc_D(clk,ID_reset||reset||Interrupt,ID_en,excode_F,excode_outD); + controller my_controllerD(.op(IR_D[`op]),.func(IR_D[`func]),.rs(IR_D[`rs]),.rt(IR_D[`rt]),.ExtOp(EXTop),.if_beq(if_beq),.if_bne(if_bne), + .if_blez(if_blez),.if_bgtz(if_bgtz),.if_bgez(if_bgez),.if_bltz(if_bltz),.if_j(if_j),.PCsel(PC_sel)); + grf my_grf(clk,reset,RegWrite,IR_D[`rs],IR_D[`rt],MUX_A3,MUX_WD,PC_W,RF_RD1,RF_RD2); + cmp my_cmp(MFRSD,MFRTD,Zero,more,less); + ext my_ext(IR_D[`imm16],EXTop,EXT_out); + npc my_npc(PC4,PC4_D,IR_D[`imm26],MFRSD,MFERET,Zero,more,less,if_beq,if_bne,if_bgtz,if_blez,if_bgez,if_bltz,if_j,PC_sel,Interrupt,next_pc); + + EX my_EX(clk,EX_reset||reset||Interrupt,EX_en,over,IR_D,PC_D,PC4_D,PC8_D,MFRSD,MFRTD,EXT_out,Zero,more,less,IR_E,PC_E,PC4_E,PC8_E,RS_E,RT_E,EXT_E,excode_E,Zero_E,more_E,less_E); + ExcCode my_exc_E(clk,EX_reset||reset||Interrupt,EX_en,(excode_outD==0?excode_D:excode_outD),excode_outE); + controller my_controllerE(.op(IR_E[`op]),.func(IR_E[`func]),.rs(IR_E[`rs]),.rt(IR_E[`rt]),.ALUCtrl(ALUCtrl),.ALUASrc(ALUASrc),.ALUBSrc(ALUBSrc), + .multdivOp(multdivOp),.start(start),.if_mthi(if_mthi),.if_mtlo(if_mtlo),.if_mfhi(if_mfhi),.if_mflo(if_mflo)); + alu my_alu(ALU_A,ALU_B,ALUCtrl,ALU_out,over); + Mult_Div my_Mult_Div(clk,reset,MFRSE,MFRTE,multdivOp,start,if_mthi,if_mtlo,Busy,High,Low); + + MEM my_MEM(clk,MEM_reset||reset||Interrupt,MEM_en,IR_E,PC_E,PC4_E,PC8_E,ALU_out,MD_out,MFRTE,Zero_E,more_E,less_E,IR_M,PC_M,PC4_M,PC8_M,AO_M,MDO_M,RT_M,excode_M,Zero_M,more_M,less_M); + ExcCode my_exc_M(clk,MEM_reset||reset||Interrupt,MEM_en,(excode_outE==0?excode_E:excode_outE),excode_outM); + controller my_controllerM(.op(IR_M[`op]),.func(IR_M[`func]),.rs(IR_M[`rs]),.rt(IR_M[`rt]),.MemRead(MemRead),.MemWrite(MemWrite),.if_sh(if_sh),.if_sb(if_sb),.cp0WE(cp0WE)); + dm my_dm(clk,reset,(MemWrite&&~Interrupt),MemRead,if_sh,if_sb,AO_M,MFRTM,PC_M,DM_out); + + //中断优先级高 + CP0 my_CP0(.A1(IR_M[`rd]),.A2(IR_M[`rd]),.DIn(MFRTM),.PC(PC_M),.IR_M(IR_M),.Zero(Zero_M),.more(more_M),.less(less_M),.if_bd(excode_E>0||excode_outE>0), + .ExcCode(((|HWInt)? ExcCode : (excode_outM==0) ? excode_M : excode_outM)),.HWInt(HWInt),.We(cp0WE),.EXLSet(EXLSet),.EXLClr(EXLClr), + .clk(clk),.reset(reset),.Interrupt(Interrupt),.EPC(EPCout),.DOut(CP0_M)); + + WB my_WB(clk,WB_reset||reset||Interrupt,WB_en,IR_M,PC_M,PC4_M,PC8_M,AO_M,MDO_M,DM_out,CP0_M,IR_W,PC_W,PC4_W,PC8_W,AO_W,MDO_W,DR_W,CP0_W); + controller my_controllerW(.op(IR_W[`op]),.func(IR_W[`func]),.rs(IR_W[`rs]),.rt(IR_W[`rt]),.RegDst(RegDst),.RegWrite(RegWrite),.MemtoReg(MemtoReg),.dataOp(dataOp)); + DataExt my_DataExt(DR_W,dataOp,AO_W[1:0],DR_Wnew); + + assign DMDEV = (AO_W>=32'h00000000&&AO_W<=32'h00002ffc) ? DR_Wnew : PrRD;//读dm还是dev + + mux my_mux(EXT_E,IR_E,IR_W,DMDEV,AO_W,MDO_W,PC8_W,CP0_W,MFRSE,MFRTE,High,Low,ALUASrc,ALUBSrc,if_mfhi,if_mflo,RegDst,MemtoReg,ALU_A,ALU_B,MUX_A3,MUX_WD,MD_out); + forward_mux my_forward(RS_E,RT_E,RT_M,MUX_WD,AO_M,MDO_M,CP0_M,MD_out,PC8_E,PC8_M,PC8_W,RF_RD1,RF_RD2,EPCout, + ForwardRSD,ForwardRTD,ForwardRSE,ForwardRTE,ForwardRTM,ForwardERET,MFRSD,MFRTD,MFRSE,MFRTE,MFRTM,MFERET); + hazardUnit my_hazard(IR_D,IR_E,IR_M,IR_W,Busy,start,ID_en,EX_reset,PC_en,ForwardRSD,ForwardRTD,ForwardRSE,ForwardRTE,ForwardRTM,ForwardERET); + +endmodule + diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DEV0.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DEV0.v" new file mode 100644 index 0000000000000000000000000000000000000000..1722e2d56078af44ae00b093d1163c73e093f750 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DEV0.v" @@ -0,0 +1,132 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:05:26 12/12/2018 +// Design Name: +// Module Name: DEV0 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DEV0( + input clk, + input reset, + input [31:0] Addr, + input WE, + input [31:0] DataIn, + output reg [31:0] DataOut, + output reg IRQ + ); + + `define Idle 2'b00 + `define Counting 2'b01 + `define Interrupt 2'b10 + + reg[1:0] state; + reg[31:0] PRESET; + reg[31:0] COUNT; + reg[2:1] Mode;//模式选择 + reg IM;//中断屏蔽 + reg Enable;//计数器使能 + reg irq; + + always@(posedge clk) begin + if(reset) begin + PRESET<=0; + COUNT<=0; + state<=`Idle; + IM<=0; + Enable<=0; + irq<=0; + end + if(WE) begin + case(Addr) + 32'h0000_7f00: begin //ctrl + {IM,Mode,Enable} <= DataIn[3:0]; + //当计数器计数时，若计数器使能被 store 类指令修改为 0 则停止计数 + if(state == `Counting && DataIn[0]==1'b0) begin + COUNT<=PRESET; + end + end + 32'h0000_7f04: begin + PRESET<=DataIn; + end + 32'h0000_7f08: begin + //COUNT不会被写的 + end + default: begin + //什么都不做 + end + endcase + end + else begin + case(state) + `Idle: begin + if(Enable==1'b1) begin + state<=`Counting; + COUNT<=PRESET; + irq<=0; + end + else begin + state<=`Idle; + end + end + + `Counting: begin + if(Enable==1'b0) begin + state<=`Idle; + end + else if(Enable==1'b1&&COUNT<=1) begin + state<=`Interrupt; + irq<=0; + end + else if(Enable==1'b1) begin + state<=`Counting; + COUNT<=COUNT-1; + irq<=0; + end + end + + `Interrupt: begin + if(Enable==1'b1) begin + irq<=1; + if(Mode==2'b00) begin + Enable<=0; + state<=`Idle; + end + else if(Mode==2'b01) begin + state<=`Counting; + COUNT<=PRESET; + end + end + end + endcase + end + //IRQ<=IM&&(Mode==2'b0)&&(COUNT==0); + IRQ<=IM&&irq; + case(Addr[3:2]) + 2'b00: begin + DataOut<={28'b0,IM,Mode,Enable}; + end + 2'b01: begin + DataOut<=PRESET; + end + 2'b10: begin + DataOut<=COUNT; + end + 2'b11: begin + DataOut<=0; + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DEV1.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DEV1.v" new file mode 100644 index 0000000000000000000000000000000000000000..61e4a2f11b44edbc2578118a8d20cc5405288282 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DEV1.v" @@ -0,0 +1,131 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:40:05 12/12/2018 +// Design Name: +// Module Name: DEV1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DEV1( + input clk, + input reset, + input [31:0] Addr, + input WE, + input [31:0] DataIn, + output reg [31:0] DataOut, + output reg IRQ + ); + + `define Idle 2'b00 + `define Counting 2'b01 + `define Interrupt 2'b10 + + reg[1:0] state; + reg[31:0] PRESET; + reg[31:0] COUNT; + reg[2:1] Mode; + reg IM; + reg Enable; + reg irq; + + always@(posedge clk) begin + if(reset) begin + PRESET<=0; + COUNT<=0; + state<=`Idle; + IM<=0; + Enable<=0; + irq<=0; + end + if(WE) begin + case(Addr) + 32'h0000_7f10: begin //ctrl + {IM,Mode,Enable} <= DataIn[3:0]; + //当计数器计数时，若计数器使能被 store 类指令修改为 0 则停止计数 + if(state == `Counting && DataIn[0]==1'b0) begin + COUNT<=PRESET; + end + end + 32'h0000_7f14: begin + PRESET<=DataIn; + end + 32'h0000_7f18: begin + + end + default: begin + + end + endcase + end + else begin + case(state) + `Idle: begin + if(Enable==1'b1) begin + state<=`Counting; + COUNT<=PRESET; + irq<=0; + end + else begin + state<=`Idle; + end + end + + `Counting: begin + if(Enable==1'b0) begin + state<=`Idle; + end + else if(Enable==1'b1&&COUNT<=1) begin + state<=`Interrupt; + irq<=0; + end + else if(Enable==1'b1) begin + state<=`Counting; + COUNT<=COUNT-1; + irq<=0; + end + end + + `Interrupt: begin + if(Enable==1'b1) begin + irq<=1; + if(Mode==2'b00) begin + Enable<=0; + state<=`Idle; + end + else if(Mode==2'b01) begin + state<=`Counting; + COUNT<=PRESET; + end + end + end + endcase + end + IRQ<=irq&&IM; + case({WE,Addr[3:2]}) + 3'b000: begin + DataOut<={28'b0,IM,Mode,Enable}; + end + 3'b001: begin + DataOut<=PRESET; + end + 3'b010: begin + DataOut<=COUNT; + end + 3'b011: begin + DataOut<=0; + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DataExt.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DataExt.v" new file mode 100644 index 0000000000000000000000000000000000000000..2b3947861b1773030df5b548e5966b3362f4296b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/DataExt.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 12/01/2018 +// Design Name: +// Module Name: DataExt +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DataExt( + input [31:0] Din, + input [2:0] dataOp, + input [1:0] Addr, + output reg[31:0] Dout + ); + + always@(*) begin + case(dataOp) + 3'b000: Dout<=Din; + 3'b001: begin//lbu + case(Addr) + 2'b00: Dout<={24'b0,Din[7:0]}; + 2'b01: Dout<={24'b0,Din[15:8]}; + 2'b10: Dout<={24'b0,Din[23:16]}; + 2'b11: Dout<={24'b0,Din[31:24]}; + endcase + end + 3'b010: begin//lb + case(Addr) + 2'b00: Dout<={{24{Din[7]}},Din[7:0]}; + 2'b01: Dout<={{24{Din[15]}},Din[15:8]}; + 2'b10: Dout<={{24{Din[23]}},Din[23:16]}; + 2'b11: Dout<={{24{Din[31]}},Din[31:24]}; + endcase + end + 3'b011: begin//lhu + case(Addr[1]) + 1'b0: Dout<={24'b0,Din[15:0]}; + 1'b1: Dout<={24'b0,Din[31:16]}; + endcase + end + 3'b100: begin//lh + case(Addr[1]) + 1'b0: Dout<={{16{Din[15]}},Din[15:0]}; + 1'b1: Dout<={{16{Din[31]}},Din[31:16]}; + endcase + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/EX.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/EX.v" new file mode 100644 index 0000000000000000000000000000000000000000..054aa54db731509a0074e784c5827ac77bf6397b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/EX.v" @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:21:31 11/23/2018 +// Design Name: +// Module Name: EX +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module EX( + input clk, + input reset, + input en, + input over, + input [31:0] IR_D, + input [31:0] PC_D, + input [31:0] PC4_D, + input [31:0] PC8_D, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EXT, + input Zero, + input more, + input less, + output reg[31:0] IR_E, + output reg[31:0] PC_E, + output reg[31:0] PC4_E, + output reg[31:0] PC8_E, + output reg[31:0] RS_E, + output reg[31:0] RT_E, + output reg[31:0] EXT_E, + output [6:2] excode_E, + output reg Zero_E, + output reg more_E, + output reg less_E + ); + + `define op 31:26 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define add 6'b100000 + `define sub 6'b100010 + `define addi 6'b001000 + + initial begin + IR_E <= 0; + end + + assign excode_E = ((IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu)&&over) ? 4 : + ((IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb)&&over) ? 5 : + (IR_E[`op]==`R&&(IR_E[`func]==`add||IR_E[`func]==`sub||IR_E[`func]==`addi)&&over) ? 12 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_E <= 32'h00000000; + end + else if(en) begin + IR_E <= IR_D; + PC_E <= PC_D; + PC4_E <= PC4_D; + PC8_E <= PC8_D; + RS_E <= RF_RD1; + RT_E <= RF_RD2; + EXT_E <= EXT; + Zero_E <= Zero; + more_E <= more; + less_E <= less; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ExcCode.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ExcCode.v" new file mode 100644 index 0000000000000000000000000000000000000000..5751fd1ac713acae06ec0bfc7f176f6b1873000b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ExcCode.v" @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 00:29:07 12/15/2018 +// Design Name: +// Module Name: ExcCode +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ExcCode( + input clk, + input reset, + input en, + input [4:0] ExcCodeIn, + output reg[4:0] ExcCodeOut + ); + + initial begin + ExcCodeOut<=0; + end + + always@(posedge clk) begin + if(reset) begin + ExcCodeOut<=0; + end + else if(en) begin + ExcCodeOut<=ExcCodeIn; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ID.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ID.v" new file mode 100644 index 0000000000000000000000000000000000000000..6f4f42c75aa53532df4e522e1fdc4bdac4b09b9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ID.v" @@ -0,0 +1,118 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:56:51 11/23/2018 +// Design Name: +// Module Name: ID +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ID( + input clk, + input reset, + input en, + input [31:0] Instr, + input [31:0] PC, + output reg[31:0] IR_D, + output reg[31:0] PC_D, + output reg[31:0] PC4_D, + output reg[31:0] PC8_D, + output [4:0] excode_D + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define j 6'b000010 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + initial begin + IR_D <= 0; + end + + wire RI;//译码异常 不认识的op func + assign RI = (IR_D[`op]==`j)||(IR_D[`op]==`jal) + ||(IR_D[`op]==`beq)||(IR_D[`op]==`bne)||(IR_D[`op]==`blez)||(IR_D[`op]==`bgtz)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00000)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00001) + ||IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu + ||IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu + ||IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb + ||(IR_D[`op]==6'b010000&&(IR_D[`rs]==5'b00000||IR_D[`rs]==5'b00100)) + ||(IR_D==32'h42000018) + ||(IR_D[`op]==`R&&(IR_D[`func]==`jr||IR_D[`func]==`jalr||IR_D[`func]==`addu||IR_D[`func]==`subu||IR_D[`func]==`add||IR_D[`func]==`sub||IR_D[`func]==`sll||IR_D[`func]==`srl||IR_D[`func]==`sra + ||IR_D[`func]==`sllv||IR_D[`func]==`srlv||IR_D[`func]==`srav||IR_D[`func]==`and_||IR_D[`func]==`or_||IR_D[`func]==`nor_||IR_D[`func]==`xor_||IR_D[`func]==`slt||IR_D[`func]==`sltu + ||IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu||IR_D[`func]==`mfhi||IR_D[`func]==`mflo||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)); + + assign excode_D = (RI==0) ? 10 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_D <= 32'h00000000; + end + else if(en) begin + IR_D <= Instr; + PC_D <= PC; + PC4_D <= PC+4; + PC8_D <= PC+8; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/MEM.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/MEM.v" new file mode 100644 index 0000000000000000000000000000000000000000..b85d5c05ef685643f157f17cda0f77adcd844440 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/MEM.v" @@ -0,0 +1,91 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:27:06 11/23/2018 +// Design Name: +// Module Name: MEM +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module MEM( + input clk, + input reset, + input en, + input [31:0] IR_E, + input [31:0] PC_E, + input [31:0] PC4_E, + input [31:0] PC8_E, + input [31:0] ALU, + input [31:0] Mult_Div, + input [31:0] RT_E, + input Zero_E, + input more_E, + input less_E, + output reg[31:0] IR_M, + output reg[31:0] PC_M, + output reg[31:0] PC4_M, + output reg[31:0] PC8_M, + output reg[31:0] AO_M, + output reg[31:0] MDO_M, + output reg[31:0] RT_M, + output [6:2] excode_M, + output reg Zero_M, + output reg more_M, + output reg less_M + ); + + `define op 31:26 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + + initial begin + IR_M <= 0; + end + + assign excode_M = ((IR_M[`op]==`lw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`lh&&AO_M[0]!=1'b0)||(IR_M[`op]==`lhu&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f0b&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| + ((IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 4 : + ((IR_M[`op]==`sw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`sh&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`sw||IR_M[`op]==`sb||IR_M[`op]==`sh)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f07&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| //不能向COUNT写 7f07 + ((IR_M[`op]==`sb||IR_M[`op]==`sh)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 5 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_M <= 32'h00000000; + end + else if(en) begin + IR_M <= IR_E; + PC_M <= PC_E; + PC4_M <= PC4_E; + PC8_M <= PC8_E; + AO_M <= ALU; + MDO_M <= Mult_Div; + RT_M <= RT_E; + Zero_M <= Zero_E; + more_M <= more_E; + less_M <= less_E; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/Mult_Div.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/Mult_Div.v" new file mode 100644 index 0000000000000000000000000000000000000000..17902f23aeb76b4e7bfc95d2ac782847068d23c8 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/Mult_Div.v" @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 11/30/2018 +// Design Name: +// Module Name: Mult_Div +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Mult_Div( + input clk, + input reset, + input [31:0] A, + input [31:0] B, + input [1:0] op, + input start, + input if_mthi, + input if_mtlo, + output reg Busy, + output [31:0] High, + output [31:0] Low + ); + reg [31:0] Hi; + reg [31:0] Lo; + assign High = Hi; + assign Low = Lo; + reg[31:0] cycles; + reg [63:0] tmp; + + initial begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + + always@(posedge clk) begin + if(reset) begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + else if(!Busy) begin + if(start) begin + case(op) + 2'b00: begin//mult + tmp<=$signed(A)*$signed(B); + cycles=5; + end + 2'b01: begin//multu + tmp<=A*B; + cycles=5; + end + 2'b10: begin//div + tmp<={$signed(A)%$signed(B),$signed(A)/$signed(B)}; + cycles=10; + end + 2'b11: begin//divu + tmp<={A%B,A/B}; + cycles=10; + end + endcase + Busy<=1; + end + if(if_mthi) begin + Hi<=A; + end + if(if_mtlo) begin + Lo<=A; + end + end + else if(Busy) begin + if(cycles>0) begin + cycles=cycles-1; + if(cycles==0) begin + {Hi,Lo}<=tmp; + Busy<=0; + end + end + end + end +endmodule \ No newline at end of file diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/WB.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/WB.v" new file mode 100644 index 0000000000000000000000000000000000000000..6ad1438e720b13966f9f1d7bbff398e41f1f031d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/WB.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:30:22 11/23/2018 +// Design Name: +// Module Name: WB +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module WB( + input clk, + input reset, + input en, + input [31:0] IR_M, + input [31:0] PC_M, + input [31:0] PC4_M, + input [31:0] PC8_M, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] DM, + input [31:0] CP0_M, + output reg[31:0] IR_W, + output reg[31:0] PC_W, + output reg[31:0] PC4_W, + output reg[31:0] PC8_W, + output reg[31:0] AO_W, + output reg[31:0] MDO_W, + output reg[31:0] DR_W, + output reg[31:0] CP0_W + ); + initial begin + IR_W <= 0; + end + always@(posedge clk) begin + if(reset) begin + IR_W <= 32'h00000000; + end + else if(en) begin + IR_W <= IR_M; + PC_W <= PC_M; + PC4_W <= PC4_M; + PC8_W <= PC8_M; + AO_W <= AO_M; + MDO_W <= MDO_M; + DR_W <= DM; + CP0_W <= CP0_M; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/alu.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/alu.v" new file mode 100644 index 0000000000000000000000000000000000000000..779fa26f44d1c9563d8acfa5e6eb6c115d67b156 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/alu.v" @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:01:30 11/23/2018 +// Design Name: +// Module Name: alu +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module alu( + input [31:0] A, + input [31:0] B, + input [3:0] ALUCtrl, + output reg[31:0] Result, + output over + ); + + reg[32:0] temp; + + assign over = (temp[32]!=temp[31]); + + always@(*) begin + case(ALUCtrl) + 4'b0000: begin + Result = A & B; + end + 4'b0001: begin + Result = A | B; + end + 4'b0010: begin + temp = {A[31],A[31:0]} + {B[31],B[31:0]}; + Result = A + B; + end + 4'b0011: begin + temp = {A[31],A[31:0]} - {B[31],B[31:0]}; + Result = A - B; + end + 4'b0100: begin + Result = A^B; + end + 4'b0101: begin + Result = ~(A|B); + end + 4'b0110: begin//sll sllv 逻辑左 + Result = B << A[4:0]; + end + 4'b0111: begin//srl srlv 逻辑右 + Result = B >> A[4:0]; + end + 4'b1000: begin//sra srav 算数右 + Result = $signed($signed(B) >>> A[4:0]); + end + 4'b1001: begin + Result = ($signed(A)<$signed(B)) ? 32'b1 : 32'b0; + end + 4'b1010: begin + Result = (A0) ? 1'b1 : 1'b0; + assign less = ($signed(D1)<0) ? 1'b1 : 1'b0; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/controller.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/controller.v" new file mode 100644 index 0000000000000000000000000000000000000000..097ebdd236cebd4bba9b639c9d30df8e4e6bef5d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/controller.v" @@ -0,0 +1,1330 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:53:56 11/24/2018 +// Design Name: +// Module Name: controller +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module controller( + input [5:0] op, + input [5:0] func, + input [4:0] rs, + input [4:0] rt, + output reg[3:0] ALUCtrl, + output reg[1:0] RegDst, + output reg ALUASrc, + output reg ALUBSrc, + output reg RegWrite, + output reg MemRead, + output reg MemWrite, + output reg [2:0] MemtoReg, + output reg [1:0]ExtOp, + output reg if_beq, + output reg if_bne, + output reg if_blez, + output reg if_bgez, + output reg if_bltz, + output reg if_bgtz, + output reg if_j, + output reg [1:0]PCsel, + output reg if_sh, + output reg if_sb, + output reg[2:0] dataOp, + output reg[1:0] multdivOp, + output reg start, + output reg if_mthi, + output reg if_mtlo, + output reg if_mfhi, + output reg if_mflo, + output reg if_1, + output reg if_2, + output reg if_3, + output reg cp0WE + ); + initial begin + PCsel <= 2'b00; + end + always@(*) + begin + case (op) + 6'b000000://R + begin + RegDst<=2'b01; + ALUBSrc<=0; + MemRead<=0; + MemWrite<=0; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + if_sh<=0; + if_sb<=0; + if_j<=0; + dataOp<=3'b000; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(func) + 6'b100001: begin //addu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100000: begin //add + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100011: begin //subu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100010: begin //sub + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100100: begin //and + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100101: begin //or + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100110: begin //xor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0100; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100111: begin //nor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0101; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001000: begin //jr + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001001: begin //jalr + ALUASrc<=0; + MemtoReg<=3'b010; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000000: begin //sll nop + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000100: begin //sllv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000010: begin //srl + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000110: begin //srlv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000011: begin //sra + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000111: begin //srav + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101010: begin //slt + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101011: begin //sltu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011000: begin //mult + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011001: begin //multu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b01; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011010: begin //div + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b10; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011011: begin //divu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b11; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010000: begin //mfhi + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=1; + if_mflo<=0; + end + 6'b010010: begin //mflo + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=1; + end + 6'b010001: begin //mthi + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=1; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010011: begin //mtlo + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=1; + if_mfhi<=0; + if_mflo<=0; + end + default: begin + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + endcase + end + 6'b100011://lw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100000://lb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b010; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100100://lbu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b001; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100001://lh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b100; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100101://lhu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b011; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101011://sw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101001://sh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=1; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101000://sb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=1; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000100://beq + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=1; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000101://bne + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=1; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000111://bgtz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=1; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000110://blez + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=1; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000001://bgez/bltz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(rt) + 5'b00001:begin//bgez + if_bgez<=1; + if_bltz<=0; + end + 5'b00000:begin//bltz + if_bgez<=0; + if_bltz<=1; + end + default:begin + if_bgez<=0; + if_bltz<=0; + end + endcase + end + + 6'b001111://lui + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b10; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001101://ori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001010://slti + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001011://sltiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001100://andi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001110://xori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0100; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001001://addiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001000://addi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000011://jal + begin + RegDst<=2'b10; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b010; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000010://j + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b010000: + begin + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ExtOp<=2'b00; + ALUCtrl<=4'b0000; + ALUASrc<=0; + ALUBSrc<=0; + if_j<=0; + MemRead<=0; + MemWrite<=0; + RegDst<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + case(rs) + 5'b00100: //mtc0 + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b00; + cp0WE<=1; + end + 5'b00000: //mfc0 + begin + RegWrite<=1; + MemtoReg<=3'b100; + PCsel<=2'b00; + cp0WE<=0; + end + default: + begin + + end + endcase + case(func) + 6'b011000://eret + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b11; + cp0WE<=0; + end + default: begin + + end + endcase + end + + default: + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/dm.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/dm.v" new file mode 100644 index 0000000000000000000000000000000000000000..8dc235f6441786a2939b96423488a07d442966e3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/dm.v" @@ -0,0 +1,89 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:57 11/23/2018 +// Design Name: +// Module Name: dm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dm( + input clk, + input reset, + input MemWrite, + input MemRead, + input if_sh, + input if_sb, + input [31:0] MemAddr, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD + ); + + reg[31:0] dm[0:4095]; + integer i; + initial begin + for(i=0;i<4096;i=i+1) begin //1024 + dm[i]<=0; + end + end + + assign RD = MemRead ? dm[MemAddr[13:2]] : 0; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<4096;i=i+1) begin//1024 + dm[i]<=0; + end + end + else begin + if(MemWrite) begin + if(if_sh) begin + if(MemAddr[1]==1'b1) begin + dm[MemAddr[13:2]][31:16] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[15:0],dm[MemAddr[13:2]][15:0]}); + end + else if(MemAddr[1]==1'b0) begin + dm[MemAddr[13:2]][15:0] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[15:0]}); + end + end + else if(if_sb) begin + case(MemAddr[1:0]) + 2'b00: begin + dm[MemAddr[13:2]][7:0] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:8],WD[7:0]}); + end + 2'b01: begin + dm[MemAddr[13:2]][15:8] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[7:0],dm[MemAddr[13:2]][7:0]}); + end + 2'b10: begin + dm[MemAddr[13:2]][23:16] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:24],WD[7:0],dm[MemAddr[13:2]][15:0]}); + end + 2'b11: begin + dm[MemAddr[13:2]][31:24] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[7:0],dm[MemAddr[13:2]][23:0]}); + end + endcase + end + else begin + dm[MemAddr[13:2]] <= WD; + $display("%d@%h: *%h <= %h",$time,PC,MemAddr,WD); + end + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ext.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ext.v" new file mode 100644 index 0000000000000000000000000000000000000000..ab616813a96964cd24ece2c94644f7d546a4fafe --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/ext.v" @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:59:19 11/23/2018 +// Design Name: +// Module Name: ext +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ext( + input [15:0] in, + input [1:0] ExtOp, + output reg [31:0] out + ); + + always@(*) begin + case(ExtOp) + 2'b00: out <= {{16{in[15]}},in}; + 2'b01: out <= {{16{1'b0}},in}; + 2'b10: out <= {in,{16{1'b0}}}; + 2'b11: out <= 0; + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/forward_mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/forward_mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..fd11f054c798b464df7a722b129173f8280ec259 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/forward_mux.v" @@ -0,0 +1,117 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:34 11/24/2018 +// Design Name: +// Module Name: forward_mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module forward_mux( + input [31:0] RS_E, + input [31:0] RT_E, + input [31:0] RT_M, + input [31:0] WD, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] CP0_M, + input [31:0] MD_out, + input [31:0] PC8_E, + input [31:0] PC8_M, + input [31:0] PC8_W, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EPCout, + input [2:0] ForwardRSD, + input [2:0] ForwardRTD, + input [2:0] ForwardRSE, + input [2:0] ForwardRTE, + input [2:0] ForwardRTM, + input [2:0] ForwardERET, + output reg[31:0] MFRSD, + output reg[31:0] MFRTD, + output reg[31:0] MFRSE, + output reg[31:0] MFRTE, + output reg[31:0] MFRTM, + output reg[31:0] MFERET + ); + + always@(*) begin + case(ForwardRSD) + 3'b000 : MFRSD <= RF_RD1; + 3'b001 : MFRSD <= AO_M; + 3'b010 : MFRSD <= WD; + 3'b011 : MFRSD <= PC8_E; + 3'b100 : MFRSD <= PC8_M; + 3'b101 : MFRSD <= CP0_M; + 3'b110 : MFRSD <= MD_out; + 3'b111 : MFRSD <= MDO_M; + default : MFRSD <= 0; + endcase + + case(ForwardRTD) + 0: MFRTD <= RF_RD2; + 1: MFRTD <= AO_M; + 2: MFRTD <= WD; + 3: MFRTD <= PC8_E; + 4: MFRTD <= PC8_M; + 5: MFRTD <= CP0_M; + 6: MFRTD <= MD_out; + 7: MFRTD <= MDO_M; + default: MFRTD <= 0; + endcase + + case(ForwardRSE) + 0:MFRSE <= RS_E; + 1:MFRSE <= AO_M; + 2:MFRSE <= WD; + 3:MFRSE <= 0; + 4:MFRSE <= PC8_M; + 5:MFRSE <= CP0_M; + 6:MFRSE <= 0; + 7:MFRSE <= MDO_M; + default:MFRSE <= 0; + endcase + + case(ForwardRTE) + 0:MFRTE <= RT_E; + 1:MFRTE <= AO_M; + 2:MFRTE <= WD; + 3:MFRTE <= 0; + 4:MFRTE <= PC8_M; + 5:MFRTE <= CP0_M; + 6:MFRTE <= 0; + 7:MFRTE <= MDO_M; + default:MFRTE <= 0; + endcase + + case(ForwardRTM) + 0:MFRTM <= RT_M; + 1:MFRTM <= 0; + 2:MFRTM <= WD; + 3:MFRTM <= 0; + 4:MFRTM <= 0; + 5:MFRTM <= 0; + 6:MFRTM <= 0; + 7:MFRTM <= 0; + default:MFRTM <= 0; + endcase + + case(ForwardERET) + 0:MFERET <= EPCout; + 1:MFERET <= MFRTM; + default:MFERET <= 0; + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/grf.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/grf.v" new file mode 100644 index 0000000000000000000000000000000000000000..90307bafbb30dc6650cbb3441f5711e3396f9a9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/grf.v" @@ -0,0 +1,59 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:24 11/23/2018 +// Design Name: +// Module Name: grf +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module grf( + input clk, + input reset, + input RegWrite, + input [4:0] RA1, + input [4:0] RA2, + input [4:0] WA, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD1, + output [31:0] RD2 + ); + + reg[31:0] register[31:0]; + integer i; + initial begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + + assign RD1 = register[RA1]; + assign RD2 = register[RA2]; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + else begin + if(RegWrite&&WA!=5'b00000) begin + register[WA] <= WD; + //$display("@%h: $%d <= %h", PC, WA,WD); + $display("%d@%h: $%d <= %h",$time,PC,WA,WD); + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/hazardUnit.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/hazardUnit.v" new file mode 100644 index 0000000000000000000000000000000000000000..14bd798e84ac5caaaa3a6f3e5a3d60a39869d4d3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/hazardUnit.v" @@ -0,0 +1,271 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:55:59 11/24/2018 +// Design Name: +// Module Name: hazardUnit +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module hazardUnit( + input [31:0] IR_D, + input [31:0] IR_E, + input [31:0] IR_M, + input [31:0] IR_W, + input Busy, + input start, + output IR_D_en, + output IR_E_clr, + output PC_en, + output [2:0]ForwardRSD, + output [2:0]ForwardRTD, + output [2:0]ForwardRSE, + output [2:0]ForwardRTE, + output [2:0]ForwardRTM, + output [2:0]ForwardERET + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + `define cal_r_D (IR_D[`op]==`R&&IR_D[`func]!=`jalr&&IR_D[`func]!=`jr&&IR_D[`func]!=`mfhi&&IR_D[`func]!=`mflo&&IR_D!=0) + `define cal_r_E (IR_E[`op]==`R&&IR_E[`func]!=`jalr&&IR_E[`func]!=`jr&&IR_E[`func]!=`mfhi&&IR_E[`func]!=`mflo&&IR_E!=0) + `define cal_r_M (IR_M[`op]==`R&&IR_M[`func]!=`jalr&&IR_M[`func]!=`jr&&IR_M[`func]!=`mfhi&&IR_M[`func]!=`mflo&&IR_M!=0) + `define cal_r_W (IR_W[`op]==`R&&IR_W[`func]!=`jalr&&IR_W[`func]!=`jr&&IR_W[`func]!=`mfhi&&IR_W[`func]!=`mflo&&IR_W!=0) + + `define cal_i_D (IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu) + `define cal_i_E (IR_E[`op]==`lui||IR_E[`op]==`ori||IR_E[`op]==`addi||IR_E[`op]==`addiu||IR_E[`op]==`andi||IR_E[`op]==`xori||IR_E[`op]==`slti||IR_E[`op]==`sltiu) + `define cal_i_M (IR_M[`op]==`lui||IR_M[`op]==`ori||IR_M[`op]==`addi||IR_M[`op]==`addiu||IR_M[`op]==`andi||IR_M[`op]==`xori||IR_M[`op]==`slti||IR_M[`op]==`sltiu) + `define cal_i_W (IR_W[`op]==`lui||IR_W[`op]==`ori||IR_W[`op]==`addi||IR_W[`op]==`addiu||IR_W[`op]==`andi||IR_W[`op]==`xori||IR_W[`op]==`slti||IR_W[`op]==`sltiu) + + `define load_D (IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu) + `define load_E (IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu) + `define load_M (IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu) + `define load_W (IR_W[`op]==`lw||IR_W[`op]==`lb||IR_W[`op]==`lbu||IR_W[`op]==`lh||IR_W[`op]==`lhu) + + `define store_D (IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb) + `define store_E (IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb) + `define store_M (IR_M[`op]==`sw||IR_M[`op]==`sh||IR_M[`op]==`sb) + `define store_W (IR_W[`op]==`sw||IR_W[`op]==`sh||IR_W[`op]==`sb) + + `define beq_D (IR_D[`op]==`beq||IR_D[`op]==`bne||IR_D[`op]==`bgtz||IR_D[`op]==`blez||(IR_D[`op]==6'b000001&&(IR_D[`rt]==5'b00000||IR_D[`rt]==5'b00001))) + `define beq_E (IR_E[`op]==`beq||IR_E[`op]==`bne||IR_E[`op]==`bgtz||IR_E[`op]==`blez||(IR_E[`op]==6'b000001&&(IR_E[`rt]==5'b00000||IR_E[`rt]==5'b00001))) + `define beq_M (IR_M[`op]==`beq||IR_M[`op]==`bne||IR_M[`op]==`bgtz||IR_M[`op]==`blez||(IR_M[`op]==6'b000001&&(IR_M[`rt]==5'b00000||IR_M[`rt]==5'b00001))) + `define beq_W (IR_W[`op]==`beq||IR_W[`op]==`bne||IR_W[`op]==`bgtz||IR_W[`op]==`blez||(IR_W[`op]==6'b000001&&(IR_W[`rt]==5'b00000||IR_W[`rt]==5'b00001))) + + `define jal_D (IR_D[`op]==`jal) + `define jal_E (IR_E[`op]==`jal) + `define jal_M (IR_M[`op]==`jal) + `define jal_W (IR_W[`op]==`jal) + + `define jalr_D (IR_D[`op]==`R&&IR_D[`func]==`jalr) + `define jalr_E (IR_E[`op]==`R&&IR_E[`func]==`jalr) + `define jalr_M (IR_M[`op]==`R&&IR_M[`func]==`jalr) + `define jalr_W (IR_W[`op]==`R&&IR_W[`func]==`jalr) + + `define jr_D (IR_D[`op]==`R&&IR_D[`func]==`jr) + `define jr_E (IR_E[`op]==`R&&IR_E[`func]==`jr) + `define jr_M (IR_M[`op]==`R&&IR_M[`func]==`jr) + `define jr_W (IR_W[`op]==`R&&IR_W[`func]==`jr) + + `define mfhi_D (IR_D[`op]==`R&&IR_D[`func]==`mfhi) + `define mfhi_E (IR_E[`op]==`R&&IR_E[`func]==`mfhi) + `define mfhi_M (IR_M[`op]==`R&&IR_M[`func]==`mfhi) + `define mfhi_W (IR_W[`op]==`R&&IR_W[`func]==`mfhi) + + `define mflo_D (IR_D[`op]==`R&&IR_D[`func]==`mflo) + `define mflo_E (IR_E[`op]==`R&&IR_E[`func]==`mflo) + `define mflo_M (IR_M[`op]==`R&&IR_M[`func]==`mflo) + `define mflo_W (IR_W[`op]==`R&&IR_W[`func]==`mflo) + + `define mf_D (`mfhi_D||`mflo_D) + `define mf_E (`mfhi_E||`mflo_E) + `define mf_M (`mfhi_M||`mflo_M) + `define mf_W (`mfhi_W||`mflo_W) + + `define mfc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00000) + `define mfc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00000) + `define mfc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00000) + `define mfc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00000) + + `define mtc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00100) + `define mtc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100) + `define mtc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100) + `define mtc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00100) + + reg stall=0; + wire stall_b,stall_cal_r,stall_cal_i,stall_load,stall_store,stall_jr,stall_jalr,stall_busy,stall_mfmt,stall_eret; + + assign stall_b = (`beq_D & `cal_r_E & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0||IR_D[`rt]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`beq_D & `cal_i_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_M & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0||IR_D[`rt]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_cal_r = (`cal_r_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_cal_i = (`cal_i_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_load = (`load_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_store = (`store_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_jr = (`jr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_jalr = (`jalr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jalr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_busy = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) & (Busy||start); + //assign stall_mfmt = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + // IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) + // &(IR_E[`op]==`R&(IR_E[`func]==`mult||IR_E[`func]==`multu||IR_E[`func]==`div||IR_E[`func]==`divu)); + assign stall_eret = (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100&&IR_E[`rd]==14)&&IR_D==32'h42000018; + always@(*) begin + stall <= stall_b||stall_cal_r||stall_cal_i||stall_load||stall_store||stall_jr||stall_jalr||stall_busy||stall_eret; + end + + assign IR_D_en = !stall; + assign IR_E_clr = stall; + assign PC_en = !stall; + + `define RSD (`cal_r_D||`cal_i_D||`load_D||`store_D||`beq_D||`jr_D||`jalr_D) + `define RTD (`cal_r_D||`store_D||`beq_D||`mtc0_D) + `define RSE (`cal_r_E||`cal_i_E||`load_E||`store_E) + `define RTE (`cal_r_E||`store_E||`mtc0_E) + `define RTM (`store_M||`mtc0_M) + + assign ForwardRSD = (`RSD & `jal_E & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 3 : + (`RSD & `jalr_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 3 : + (`RSD & `mf_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 6 : + (`RSD & `cal_r_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 1 : + (`RSD & `cal_i_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 1 : + (`RSD & `jal_M & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 4 : + (`RSD & `jalr_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 4 : + (`RSD & `mf_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 5 : + (`RSD & `mfc0_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 7 : + (`RSD & `cal_r_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `cal_i_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `load_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mf_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mfc0_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `jal_W & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 2 : + (`RSD & `jalr_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : 0 ; + + assign ForwardRTD = (`RTD & `jal_E & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 3 : + (`RTD & `jalr_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 3 : + (`RTD & `mf_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 6 : + (`RTD & `cal_r_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 1 : + (`RTD & `cal_i_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 1 : + (`RTD & `jal_M & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 4 : + (`RTD & `jalr_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 4 : + (`RTD & `mf_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 7 : + (`RTD & `mfc0_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 5 : + (`RTD & `cal_r_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `cal_i_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `load_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mf_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mfc0_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `jal_W & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 2 : + (`RTD & `jalr_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : 0; + + assign ForwardRSE = (`RSE & `cal_r_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `cal_i_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `jal_M & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 4 : + (`RSE & `jalr_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 4 : + (`RSE & `mf_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 7 : + (`RSE & `mfc0_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 5 : + (`RSE & `cal_r_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `cal_i_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `load_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mf_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mfc0_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jal_W & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jalr_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : 0; + + assign ForwardRTE = (`RTE & `cal_r_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `cal_i_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `jal_M & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 4 : + (`RTE & `jalr_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 4 : + (`RTE & `mf_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 7 : + (`RTE & `mfc0_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 5 : + (`RTE & `cal_r_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `cal_i_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `load_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mf_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mfc0_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jal_W & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jalr_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : 0; + + assign ForwardRTM = (`RTM & `cal_r_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `cal_i_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `load_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mf_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mfc0_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jal_W & (IR_M[`rt]==31) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jalr_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : 0; + + assign ForwardERET = ((IR_D==32'h42000018)&&(IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100&&IR_M[`rd]==14)) ? 1 : 0; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/im.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/im.v" new file mode 100644 index 0000000000000000000000000000000000000000..5743ec5f2b17e42b6512c62f08070c6b86a83cca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/im.v" @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:01 11/23/2018 +// Design Name: +// Module Name: im +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module im( + input [31:0] PC, + output[31:0] instruction + ); + + reg[31:0] im[0:4095]; + initial begin + $readmemh("code.txt",im); + $readmemh("code_handler.txt",im,1120,2047); + end + + wire[31:0] pc=PC-32'h00003000; + assign instruction = im[pc[13:2]]; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/mips.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/mips.v" new file mode 100644 index 0000000000000000000000000000000000000000..d011fae91ff309813c5ac4a0812a1a4f11c36a74 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/mips.v" @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:46:09 11/23/2018 +// Design Name: +// Module Name: mips +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mips( + input clk, + input reset + ); + + wire [31:0] PrRD; + wire [6:2] ExcCode; + wire [31:0] PrAddr; + wire [31:0] PrWD; + wire PrWe; + wire [31:0] DEV_Addr; + wire [31:0] DEV_WD; + wire [31:0] DEV0_RD; + wire [31:0] DEV1_RD; + wire WeDEV0; + wire WeDEV1; + wire IRQ0; + wire IRQ1; + + CPU my_CPU(.clk(clk),.reset(reset),.HWInt({4'b0,IRQ1,IRQ0}),.PrRD(PrRD),.ExcCode(ExcCode),.PrAddr(PrAddr),.PrWD(PrWD),.PrWe(PrWe)); + Bridge my_Bridge(PrAddr,PrWe,PrRD,PrWD,DEV_Addr,DEV_WD,DEV0_RD,DEV1_RD,WeDEV0,WeDEV1); + DEV0 my_time0(clk,reset,DEV_Addr,WeDEV0,DEV_WD,DEV0_RD,IRQ0); + DEV1 my_time1(clk,reset,DEV_Addr,WeDEV1,DEV_WD,DEV1_RD,IRQ1); + + assign ExcCode = (IRQ0||IRQ1) ? 5'b00000 : 5'b11111; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..02d800057a121623b1cb76181c21a974d0f6e996 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/mux.v" @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:31:53 11/23/2018 +// Design Name: +// Module Name: mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux( + input [31:0] EXT_E, + input [31:0] IR_E, + input [31:0] IR_W, + input [31:0] DR_Wnew, + input [31:0] AO_W, + input [31:0] MDO_W, + input [31:0] PC8_W, + input [31:0] CP0_W, + input [31:0] MFRSE, + input [31:0] MFRTE, + input [31:0] High, + input [31:0] Low, + input ALUasel, + input ALUbsel, + input if_mfhi, + input if_mflo, + input [1:0] RegDst, + input [2:0] MemtoReg, + output reg[31:0] ALU_A, + output reg[31:0] ALU_B, + output reg[4:0] MUX_A3, + output reg[31:0] MUX_WD, + output reg[31:0] MD_out + ); + + always@(*) begin + case(ALUasel) + 1'b0: ALU_A<=MFRSE; + 1'b1: ALU_A<={27'b0,IR_E[10:6]}; + endcase + + case(ALUbsel) + 1'b0: ALU_B<=MFRTE; + 1'b1: ALU_B<=EXT_E; + endcase + + case(RegDst) + 2'b00: MUX_A3<=IR_W[20:16]; + 2'b01: MUX_A3<=IR_W[15:11]; + 2'b10: MUX_A3<=32'h1f; + 2'b11: MUX_A3<=0; + endcase + + case(MemtoReg) + 3'b000: MUX_WD<=AO_W; + 3'b001: MUX_WD<=DR_Wnew; + 3'b010: MUX_WD<=PC8_W; + 3'b011: MUX_WD<=MDO_W; + 3'b100: MUX_WD<=CP0_W; + endcase + + if(if_mfhi) MD_out<=High; + else if(if_mflo) MD_out<=Low; + else MD_out<=0; + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/npc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/npc.v" new file mode 100644 index 0000000000000000000000000000000000000000..2326b32486b61ad162e0643debbddbdf4235c924 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/npc.v" @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:13:22 11/23/2018 +// Design Name: +// Module Name: npc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module npc( + input [31:0] PC4, + input [31:0] PC4D, + input [25:0] I26, + input [31:0] MFRSD, + input [31:0] EPC, + input Zero, + input more, + input less, + input if_beq, + input if_bne, + input if_bgtz, + input if_blez, + input if_bgez, + input if_bltz, + input if_j,//j或jal + input[1:0] PC_sel, + input Interrupt, + output reg[31:0] next_pc + ); + reg[31:0] NPC; + always@(*) begin + if((if_beq&&Zero)||(if_bne&&!Zero)||(if_bgtz&&more)||(if_blez&&!more)||(if_bgez&&!less)||(if_bltz&&less)) begin + NPC<=PC4D+{{14{I26[15]}},I26[15:0],2'b00}; + end + else if(if_j) begin + NPC<={PC4D[31:28],I26[25:0],2'b00}; + end + else begin + NPC<=PC4D+4; + end + case(PC_sel) + 2'b00: next_pc<=PC4; + 2'b01: next_pc<=MFRSD; + 2'b10: next_pc<=NPC; + 2'b11: next_pc<=EPC; + endcase + if(Interrupt) begin + next_pc<=32'h00004180; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/pc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/pc.v" new file mode 100644 index 0000000000000000000000000000000000000000..06a0733bb46e61a82eeecb3b568f77b00d2eea5a --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/pc.v" @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:00 11/23/2018 +// Design Name: +// Module Name: pc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module pc( + input clk, + input reset, + input en, + input[31:0] next_pc, + output reg[31:0] pc, + output [4:0] excode_F + ); + + initial begin + pc<=32'h00003000; + end + + assign excode_F = ((pc[1:0]!=2'b00)||(pc < 32'h00003000)||(pc > 32'h00004ffc)) ? 4 : 0; + + always@(posedge clk) begin + if(reset) begin + pc <= 32'h00003000; + end + else if(en) begin + pc <= next_pc; + end + else begin + pc <= pc; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/test.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/test.v" new file mode 100644 index 0000000000000000000000000000000000000000..e5caf7ea5fe230bbd63b23a8c12df7473769acca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_8\346\224\271bd/test.v" @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:00 11/25/2018 +// Design Name: mips +// Module Name: E:/Verilog/p5/test.v +// Project Name: p5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: mips +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module test; + + // Inputs + reg clk; + reg reset; + + // Instantiate the Unit Under Test (UUT) + mips uut ( + .clk(clk), + .reset(reset) + ); + + initial begin + clk = 0; + reset = 1; + #12 reset = 0; + end + + always #10 clk = ~clk; + + +endmodule + + diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/Bridge.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/Bridge.v" new file mode 100644 index 0000000000000000000000000000000000000000..dd788614ad6e56748e6d45767d860c460250ba97 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/Bridge.v" @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:11 12/12/2018 +// Design Name: +// Module Name: Bridge +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bridge( + input [31:0] PrAddr, + input PrWE, + output [31:0] PrRD, + input [31:0] PrWD, + output [31:0] DEV_Addr, + output [31:0] DEV_WD, + input [31:0] DEV0_RD, + input [31:0] DEV1_RD, + output WeDEV0, + output WeDEV1 + ); + + `define DEBUG_DEV_DATA 32'b0 + + //DEV0 00007F00-00007F0B + //DEV1 00007F10-00007F1B + wire HitDEV0,HitDEV1; + assign HitDEV0 = (PrAddr[31:4]==28'h00007F0); + assign HitDEV1 = (PrAddr[31:4]==28'h00007F1); + + assign PrRD = (HitDEV0) ? DEV0_RD : + (HitDEV1) ? DEV1_RD : + `DEBUG_DEV_DATA; + + assign WeDEV0 = PrWE&&HitDEV0; + assign WeDEV1 = PrWE&&HitDEV1; + + assign DEV_Addr = PrAddr; + assign DEV_WD = PrWD; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/CP0.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/CP0.v" new file mode 100644 index 0000000000000000000000000000000000000000..4943be8e86dc2f4d8863065fb902c88c3959ce1b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/CP0.v" @@ -0,0 +1,138 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:46:14 12/13/2018 +// Design Name: +// Module Name: CP0 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CP0( + input[4:0] A1,//读CP0寄存器编号 执行MFC0指令时产生 + input[4:0] A2,//写CP0寄存器编号 执行MTC0指令时产生 + input[31:0] DIn,//CP0寄存器的写入数据 执行MTC0指令时产生 数据来自GPR + input[31:0] PC,//中断/异常时的PC + input[31:0] IR_M,//指令 + input Zero, + input more, + input less, + input if_bd, + input[6:2] ExcCode,//中断/异常的类型 + input[5:0] HWInt,//6个设备中断 + input We,//CP0写使能 执行MTC0指令时产生 + input EXLSet,//用于置位SR的EXL(EXL为1) 流水线在M阶段产生 + input EXLClr,//用于清除SR的EXL(EXL为0) 执行ERET指令时产生 + input clk, + input reset, + output Interrupt,//中断和异常 是HWInt/IM/EXL/IE的函数 + output[31:0] EPC,//EPC寄存器输出至NPC + output[31:0] DOut //CP0寄存器的输出数据 执行MFC0指令时产生，输出数据至GRF + ); + + `define SR 12 + `define CAUSE 13 + `define EPC 14 + `define PRID 15 + + `define R 6'b000000 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define jr 6'b001000 + `define j 6'b000010 + `define jalr 6'b001001 + + //SR {16'b0, im, 8'b0, exl, ie} + reg[15:10] im; //6位中断屏蔽位，分别对应6个外部中断 1-允许中断，0-禁止中断 + reg exl;//EXL：异常级 1-进入异常，不允许再中断；0-允许中断 + reg ie;//全局中断使能 1-允许中断；0-禁止中断 + //CAUSE {bd, 15'b0, hwint_pend[15:10], 3'b0, exccode[6:2], 2'b0} + reg bd;//异常发生在延迟槽的指令的话 bd=1 + reg[6:2] exccode; + reg[15:10] hwint_pend;//在clock上升沿不断的保存外部6个中断(HWInt[5:0]) + //EPC + reg[31:0] epc; + //PRID + reg[31:0] prid = 32'h12345678; + wire Exception;//异常 + wire IntReq;//中断 + assign EPC = epc; + //读 除了SR/Cause/EPC/PRId外，不用的寄存器一律输出0 + assign DOut = (A1==`SR) ? {16'b0, im, 8'b0, exl, ie} : + (A1==`CAUSE) ? {bd, 15'b0, hwint_pend[15:10], 3'b0, exccode[6:2], 2'b0} : + (A1==`EPC) ? epc : + (A1==`PRID) ? prid : 0; + assign IntReq = (|(HWInt[5:0] & im[15:10])) & ie & !exl ; + assign Exception = (ExcCode>0) ? 1'b1 : 1'b0; + assign Interrupt = IntReq||Exception; + + integer i; + always@(posedge clk) begin + hwint_pend <= HWInt;//在clock上升沿不断的保存外部6个中断(HWInt[5:0]) + if(reset) begin + im<=6'b0;//SR + exl<=1'b0; + ie<=1'b0; + hwint_pend<=6'b0;//CAUSE + bd<=0; + exccode<=0; + epc<=0;//EPC + end + else begin + epc <= (Interrupt&&bd) ? {PC[31:2], 2'b00} - 4 : + (Interrupt&&!bd) ? {PC[31:2], 2'b00} : + epc; + if(bd==1'b0) begin + bd <= (((IR_M[31:26]==`j)||(IR_M[31:26]==`jal)||(IR_M[31:26]==`beq&&Zero)||(IR_M[31:26]==`bne&&!Zero)||(IR_M[31:26]==`blez&&!more)||(IR_M[31:26]==`bgtz&&more) + ||(IR_M[31:26]==`R&&(IR_M[5:0]==`jr||IR_M[5:0]==`jalr))||(IR_M[31:26]==6'b000001&&IR_M[20:16]==5'b00000&&less)||(IR_M[31:26]==6'b000001&&IR_M[20:16]==5'b00001&&!less))); + end + else if(bd==1'b1)begin + if(exl==1'b0&&Interrupt==1'b0) begin + bd<=1'b0; + end + end + if(We) begin //写入 + case(A2) + `SR: begin + {im, exl, ie} <= {DIn[15:10], DIn[1], DIn[0]}; + end + `CAUSE: begin + hwint_pend <= DIn[15:10]; + end + `EPC: begin + epc <= DIn; + end + `PRID: begin + prid <= DIn; + end + default: begin + end + endcase + end + if(EXLSet||Interrupt) begin + exl<=1'b1; + exccode<=ExcCode; + end + if(EXLClr) begin + exl<=1'b0; + bd<=1'b0; + end + //if(IntReq) begin + // bd<=1'b0; + //end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/CPU.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/CPU.v" new file mode 100644 index 0000000000000000000000000000000000000000..41e2a8b129092d09ff758d86dd4709b0d6ce2ece --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/CPU.v" @@ -0,0 +1,212 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:30:40 12/15/2018 +// Design Name: +// Module Name: CPU +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CPU( + input clk, + input reset, + input [7:2] HWInt, + input [31:0] PrRD, + input [6:2] ExcCode, + output [31:0] PrAddr, + output [31:0] PrWD, + output PrWe + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + `define imm26 25:0 + + wire PC_en; + wire[1:0] PC_sel; + wire[31:0] PC; + wire[31:0] PC4; + wire[31:0] Instr; + wire ID_en; + wire EX_en; + wire MEM_en; + wire WB_en; + wire ID_reset; + wire EX_reset; + wire MEM_reset; + wire WB_reset; + wire[31:0] IR_D; + wire[31:0] PC_D; + wire[31:0] PC4_D; + wire[31:0] PC8_D; + wire[31:0] IR_E; + wire[31:0] PC_E; + wire[31:0] PC4_E; + wire[31:0] PC8_E; + wire[31:0] IR_M; + wire[31:0] PC_M; + wire[31:0] PC4_M; + wire[31:0] PC8_M; + wire[31:0] IR_W; + wire[31:0] PC_W; + wire[31:0] PC4_W; + wire[31:0] PC8_W; + wire Zero; + wire Zero_E; + wire Zero_M; + wire more; + wire less; + wire more_E; + wire less_E; + wire more_M; + wire less_M; + wire if_beq; + wire if_bne; + wire if_blez; + wire if_bgtz; + wire if_bltz; + wire if_bgez; + wire if_j; + wire[1:0] EXTop; + wire if_sh; + wire if_sb; + + wire[3:0] ALUCtrl; + wire[1:0] RegDst; + wire ALUASrc; + wire ALUBSrc; + wire RegWrite; + wire MemRead; + wire MemWrite; + wire [2:0] MemtoReg; + wire [2:0] dataOp; + wire [1:0] multdivOp; + wire if_mthi; + wire if_mtlo; + wire if_mfhi; + wire if_mflo; + wire start; + wire Busy; + wire[31:0] High; + wire[31:0] Low; + + wire [31:0] RS_E; + wire [31:0] RT_E; + wire [31:0] EXT_E; + wire [31:0] AO_M; + wire [31:0] MDO_M; + wire [31:0] RT_M; + wire [31:0] DR_W; + wire [31:0] DR_Wnew; + wire [31:0] AO_W; + wire [31:0] MDO_W; + + wire[4:0] MUX_A3; + wire[31:0] MUX_WD; + wire[31:0] RF_RD1; + wire[31:0] RF_RD2; + wire[31:0] MFRSD; + wire[31:0] MFRTD; + wire[31:0] MFRSE; + wire[31:0] MFRTE; + wire[31:0] MFRTM; + wire[31:0] MFERET; + wire[31:0] EXT_out; + wire[31:0] ALU_A; + wire[31:0] ALU_B; + wire[31:0] ALU_out; + wire[31:0] MD_out; + wire[31:0] DM_out; + wire[31:0] next_pc; + wire[2:0] ForwardRSD; + wire[2:0] ForwardRTD; + wire[2:0] ForwardRSE; + wire[2:0] ForwardRTE; + wire[2:0] ForwardRTM; + wire[2:0] ForwardERET; + + assign EX_en = 1; + assign MEM_en = 1; + assign WB_en = 1; + assign ID_reset = 0; + assign MEM_reset = 0; + assign WB_reset = 0; + assign PC4 = PC + 4; + + wire[6:2] excode_F,excode_D,excode_E,excode_M; + wire[6:2] excode_outF,excode_outD,excode_outE,excode_outM; + wire over; + wire cp0WE; + wire[31:0] CP0_M; + wire[31:0] CP0_W; + wire[31:0] EPCout; + wire Interrupt; + wire EXLSet; + wire EXLClr; + wire[31:0] DMDEV; + wire if_eret; + + assign PrAddr = AO_M; + assign PrWD = MFRTM; + assign PrWe = (MemWrite&&(~Interrupt));//没出现异常才可以写 + assign EXLSet = Interrupt; + assign EXLClr = (IR_M[`op]==6'b010000&&IR_M[`func]==6'b011000); //eret + + pc my_pc(clk,reset,PC_en||Interrupt,next_pc,PC,excode_F); + im my_im(PC,Instr); + + ID my_ID(clk,(ID_reset||reset||Interrupt||(IR_D==32'h42000018&&ID_en)),ID_en,Instr,PC,IR_D,PC_D,PC4_D,PC8_D,excode_D); + ExcCode my_exc_D(clk,ID_reset||reset||Interrupt,ID_en,excode_F,excode_outD); + controller my_controllerD(.op(IR_D[`op]),.func(IR_D[`func]),.rs(IR_D[`rs]),.rt(IR_D[`rt]),.ExtOp(EXTop),.if_beq(if_beq),.if_bne(if_bne), + .if_blez(if_blez),.if_bgtz(if_bgtz),.if_bgez(if_bgez),.if_bltz(if_bltz),.if_j(if_j),.PCsel(PC_sel)); + grf my_grf(clk,reset,RegWrite,IR_D[`rs],IR_D[`rt],MUX_A3,MUX_WD,PC_W,RF_RD1,RF_RD2); + cmp my_cmp(MFRSD,MFRTD,Zero,more,less); + ext my_ext(IR_D[`imm16],EXTop,EXT_out); + npc my_npc(PC4,PC4_D,IR_D[`imm26],MFRSD,MFERET,Zero,more,less,if_beq,if_bne,if_bgtz,if_blez,if_bgez,if_bltz,if_j,PC_sel,Interrupt,next_pc); + + EX my_EX(clk,EX_reset||reset||Interrupt,EX_en,over,IR_D,PC_D,PC4_D,PC8_D,MFRSD,MFRTD,EXT_out,Zero,more,less,IR_E,PC_E,PC4_E,PC8_E,RS_E,RT_E,EXT_E,excode_E,Zero_E,more_E,less_E); + ExcCode my_exc_E(clk,EX_reset||reset||Interrupt,EX_en,(excode_outD==0?excode_D:excode_outD),excode_outE); + controller my_controllerE(.op(IR_E[`op]),.func(IR_E[`func]),.rs(IR_E[`rs]),.rt(IR_E[`rt]),.ALUCtrl(ALUCtrl),.ALUASrc(ALUASrc),.ALUBSrc(ALUBSrc), + .multdivOp(multdivOp),.start(start),.if_mthi(if_mthi),.if_mtlo(if_mtlo),.if_mfhi(if_mfhi),.if_mflo(if_mflo)); + alu my_alu(ALU_A,ALU_B,ALUCtrl,ALU_out,over); + Mult_Div my_Mult_Div(clk,reset,MFRSE,MFRTE,multdivOp,start,if_mthi,if_mtlo,Busy,High,Low); + + MEM my_MEM(clk,MEM_reset||reset||Interrupt,MEM_en,IR_E,PC_E,PC4_E,PC8_E,ALU_out,MD_out,MFRTE,Zero_E,more_E,less_E,IR_M,PC_M,PC4_M,PC8_M,AO_M,MDO_M,RT_M,excode_M,Zero_M,more_M,less_M); + ExcCode my_exc_M(clk,MEM_reset||reset||Interrupt,MEM_en,(excode_outE==0?excode_E:excode_outE),excode_outM); + controller my_controllerM(.op(IR_M[`op]),.func(IR_M[`func]),.rs(IR_M[`rs]),.rt(IR_M[`rt]),.MemRead(MemRead),.MemWrite(MemWrite),.if_sh(if_sh),.if_sb(if_sb),.cp0WE(cp0WE)); + dm my_dm(clk,reset,(MemWrite&&~Interrupt),MemRead,if_sh,if_sb,AO_M,MFRTM,PC_M,DM_out); + + //中断优先级高 + CP0 my_CP0(.A1(IR_M[`rd]),.A2(IR_M[`rd]),.DIn(MFRTM),.PC(PC_M),.IR_M(IR_M),.Zero(Zero_M),.more(more_M),.less(less_M),.if_bd(excode_E>0||excode_outE>0), + .ExcCode(((|HWInt)? ExcCode : (excode_outM==0) ? excode_M : excode_outM)),.HWInt(HWInt),.We(cp0WE),.EXLSet(EXLSet),.EXLClr(EXLClr), + .clk(clk),.reset(reset),.Interrupt(Interrupt),.EPC(EPCout),.DOut(CP0_M)); + + WB my_WB(clk,WB_reset||reset||Interrupt,WB_en,IR_M,PC_M,PC4_M,PC8_M,AO_M,MDO_M,DM_out,CP0_M,IR_W,PC_W,PC4_W,PC8_W,AO_W,MDO_W,DR_W,CP0_W); + controller my_controllerW(.op(IR_W[`op]),.func(IR_W[`func]),.rs(IR_W[`rs]),.rt(IR_W[`rt]),.RegDst(RegDst),.RegWrite(RegWrite),.MemtoReg(MemtoReg),.dataOp(dataOp)); + DataExt my_DataExt(DR_W,dataOp,AO_W[1:0],DR_Wnew); + + assign DMDEV = (AO_W>=32'h00000000&&AO_W<=32'h00002ffc) ? DR_Wnew : PrRD;//读dm还是dev + + mux my_mux(EXT_E,IR_E,IR_W,DMDEV,AO_W,MDO_W,PC8_W,CP0_W,MFRSE,MFRTE,High,Low,ALUASrc,ALUBSrc,if_mfhi,if_mflo,RegDst,MemtoReg,ALU_A,ALU_B,MUX_A3,MUX_WD,MD_out); + forward_mux my_forward(RS_E,RT_E,RT_M,MUX_WD,AO_M,MDO_M,CP0_M,MD_out,PC8_E,PC8_M,PC8_W,RF_RD1,RF_RD2,EPCout, + ForwardRSD,ForwardRTD,ForwardRSE,ForwardRTE,ForwardRTM,ForwardERET,MFRSD,MFRTD,MFRSE,MFRTE,MFRTM,MFERET); + hazardUnit my_hazard(IR_D,IR_E,IR_M,IR_W,Busy,start,ID_en,EX_reset,PC_en,ForwardRSD,ForwardRTD,ForwardRSE,ForwardRTE,ForwardRTM,ForwardERET); + +endmodule + diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DEV0.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DEV0.v" new file mode 100644 index 0000000000000000000000000000000000000000..c3de6ebea5cda3d12d7d622958a0b293fd5e1b58 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DEV0.v" @@ -0,0 +1,138 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:05:26 12/12/2018 +// Design Name: +// Module Name: DEV0 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DEV0( + input clk, + input reset, + input [31:0] Addr, + input WE, + input [31:0] DataIn, + output [31:0] DataOut, + output IRQ + ); + + `define Idle 2'b00 + `define Counting 2'b01 + `define Interrupt 2'b10 + + reg[1:0] state; + reg[31:0] PRESET; + reg[31:0] COUNT; + reg[2:1] Mode;//模式选择 + reg IM;//中断屏蔽 + reg Enable;//计数器使能 + reg irq; + + assign IRQ = IM && irq; + + assign DataOut = (Addr[3:2]==2'b00) ? {28'b0,IM,Mode,Enable} : + (Addr[3:2]==2'b01) ? PRESET : + (Addr[3:2]==2'b10) ? COUNT : 0; + + always@(posedge clk) begin + if(reset) begin + PRESET<=0; + COUNT<=0; + state<=`Idle; + IM<=0; + Enable<=0; + irq<=0; + end + if(WE) begin + case(Addr) + 32'h0000_7f00: begin //ctrl + {IM,Mode,Enable} <= DataIn[3:0]; + //当计数器计数时，若计数器使能被 store 类指令修改为 0 则停止计数 + if(state == `Counting && DataIn[0]==1'b0) begin + COUNT<=PRESET; + end + end + 32'h0000_7f04: begin + PRESET<=DataIn; + end + 32'h0000_7f08: begin + //COUNT不会被写的 + end + default: begin + //什么都不做 + end + endcase + end + else begin + case(state) + `Idle: begin + if(Enable==1'b1) begin + state<=`Counting; + COUNT<=PRESET; + irq<=0; + end + else begin + state<=`Idle; + end + end + + `Counting: begin + if(Enable==1'b0) begin + state<=`Idle; + end + else if(Enable==1'b1&&COUNT<=1) begin + state<=`Interrupt; + irq<=0; + end + else if(Enable==1'b1) begin + state<=`Counting; + COUNT<=COUNT-1; + irq<=0; + end + end + + `Interrupt: begin + if(Enable==1'b1) begin + irq<=1; + if(Mode==2'b00) begin + Enable<=0; + state<=`Idle; + end + else if(Mode==2'b01) begin + state<=`Counting; + COUNT<=PRESET; + end + end + end + endcase + end + //IRQ<=IM&&(Mode==2'b0)&&(COUNT==0); + //IRQ<=IM&&irq; + //case(Addr[3:2]) + // 2'b00: begin + // DataOut<={28'b0,IM,Mode,Enable}; + // end + // 2'b01: begin + // DataOut<=PRESET; + // end + // 2'b10: begin + // DataOut<=COUNT; + // end + // 2'b11: begin + // DataOut<=0; + // end + //endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DEV1.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DEV1.v" new file mode 100644 index 0000000000000000000000000000000000000000..069a72592576bf087cd8a097182e9211663fcec5 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DEV1.v" @@ -0,0 +1,122 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:40:05 12/12/2018 +// Design Name: +// Module Name: DEV1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DEV1( + input clk, + input reset, + input [31:0] Addr, + input WE, + input [31:0] DataIn, + output [31:0] DataOut, + output IRQ + ); + + `define Idle 2'b00 + `define Counting 2'b01 + `define Interrupt 2'b10 + + reg[1:0] state; + reg[31:0] PRESET; + reg[31:0] COUNT; + reg[2:1] Mode; + reg IM; + reg Enable; + reg irq; + + assign IRQ = IM && irq; + + assign DataOut = (Addr[3:2]==2'b00) ? {28'b0,IM,Mode,Enable} : + (Addr[3:2]==2'b01) ? PRESET : + (Addr[3:2]==2'b10) ? COUNT : 0; + + always@(posedge clk) begin + if(reset) begin + PRESET<=0; + COUNT<=0; + state<=`Idle; + IM<=0; + Enable<=0; + irq<=0; + end + if(WE) begin + case(Addr) + 32'h0000_7f10: begin //ctrl + {IM,Mode,Enable} <= DataIn[3:0]; + //当计数器计数时，若计数器使能被 store 类指令修改为 0 则停止计数 + if(state == `Counting && DataIn[0]==1'b0) begin + COUNT<=PRESET; + end + end + 32'h0000_7f14: begin + PRESET<=DataIn; + end + 32'h0000_7f18: begin + + end + default: begin + + end + endcase + end + else begin + case(state) + `Idle: begin + if(Enable==1'b1) begin + state<=`Counting; + COUNT<=PRESET; + irq<=0; + end + else begin + state<=`Idle; + end + end + + `Counting: begin + if(Enable==1'b0) begin + state<=`Idle; + end + else if(Enable==1'b1&&COUNT<=1) begin + state<=`Interrupt; + irq<=0; + end + else if(Enable==1'b1) begin + state<=`Counting; + COUNT<=COUNT-1; + irq<=0; + end + end + + `Interrupt: begin + if(Enable==1'b1) begin + irq<=1; + if(Mode==2'b00) begin + Enable<=0; + state<=`Idle; + end + else if(Mode==2'b01) begin + state<=`Counting; + COUNT<=PRESET; + end + end + end + endcase + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DataExt.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DataExt.v" new file mode 100644 index 0000000000000000000000000000000000000000..2b3947861b1773030df5b548e5966b3362f4296b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/DataExt.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 12/01/2018 +// Design Name: +// Module Name: DataExt +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DataExt( + input [31:0] Din, + input [2:0] dataOp, + input [1:0] Addr, + output reg[31:0] Dout + ); + + always@(*) begin + case(dataOp) + 3'b000: Dout<=Din; + 3'b001: begin//lbu + case(Addr) + 2'b00: Dout<={24'b0,Din[7:0]}; + 2'b01: Dout<={24'b0,Din[15:8]}; + 2'b10: Dout<={24'b0,Din[23:16]}; + 2'b11: Dout<={24'b0,Din[31:24]}; + endcase + end + 3'b010: begin//lb + case(Addr) + 2'b00: Dout<={{24{Din[7]}},Din[7:0]}; + 2'b01: Dout<={{24{Din[15]}},Din[15:8]}; + 2'b10: Dout<={{24{Din[23]}},Din[23:16]}; + 2'b11: Dout<={{24{Din[31]}},Din[31:24]}; + endcase + end + 3'b011: begin//lhu + case(Addr[1]) + 1'b0: Dout<={24'b0,Din[15:0]}; + 1'b1: Dout<={24'b0,Din[31:16]}; + endcase + end + 3'b100: begin//lh + case(Addr[1]) + 1'b0: Dout<={{16{Din[15]}},Din[15:0]}; + 1'b1: Dout<={{16{Din[31]}},Din[31:16]}; + endcase + end + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/EX.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/EX.v" new file mode 100644 index 0000000000000000000000000000000000000000..054aa54db731509a0074e784c5827ac77bf6397b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/EX.v" @@ -0,0 +1,92 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:21:31 11/23/2018 +// Design Name: +// Module Name: EX +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module EX( + input clk, + input reset, + input en, + input over, + input [31:0] IR_D, + input [31:0] PC_D, + input [31:0] PC4_D, + input [31:0] PC8_D, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EXT, + input Zero, + input more, + input less, + output reg[31:0] IR_E, + output reg[31:0] PC_E, + output reg[31:0] PC4_E, + output reg[31:0] PC8_E, + output reg[31:0] RS_E, + output reg[31:0] RT_E, + output reg[31:0] EXT_E, + output [6:2] excode_E, + output reg Zero_E, + output reg more_E, + output reg less_E + ); + + `define op 31:26 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define add 6'b100000 + `define sub 6'b100010 + `define addi 6'b001000 + + initial begin + IR_E <= 0; + end + + assign excode_E = ((IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu)&&over) ? 4 : + ((IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb)&&over) ? 5 : + (IR_E[`op]==`R&&(IR_E[`func]==`add||IR_E[`func]==`sub||IR_E[`func]==`addi)&&over) ? 12 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_E <= 32'h00000000; + end + else if(en) begin + IR_E <= IR_D; + PC_E <= PC_D; + PC4_E <= PC4_D; + PC8_E <= PC8_D; + RS_E <= RF_RD1; + RT_E <= RF_RD2; + EXT_E <= EXT; + Zero_E <= Zero; + more_E <= more; + less_E <= less; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ExcCode.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ExcCode.v" new file mode 100644 index 0000000000000000000000000000000000000000..5751fd1ac713acae06ec0bfc7f176f6b1873000b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ExcCode.v" @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 00:29:07 12/15/2018 +// Design Name: +// Module Name: ExcCode +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ExcCode( + input clk, + input reset, + input en, + input [4:0] ExcCodeIn, + output reg[4:0] ExcCodeOut + ); + + initial begin + ExcCodeOut<=0; + end + + always@(posedge clk) begin + if(reset) begin + ExcCodeOut<=0; + end + else if(en) begin + ExcCodeOut<=ExcCodeIn; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ID.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ID.v" new file mode 100644 index 0000000000000000000000000000000000000000..6f4f42c75aa53532df4e522e1fdc4bdac4b09b9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ID.v" @@ -0,0 +1,118 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:56:51 11/23/2018 +// Design Name: +// Module Name: ID +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ID( + input clk, + input reset, + input en, + input [31:0] Instr, + input [31:0] PC, + output reg[31:0] IR_D, + output reg[31:0] PC_D, + output reg[31:0] PC4_D, + output reg[31:0] PC8_D, + output [4:0] excode_D + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define func 5:0 + + `define R 6'b000000 + `define j 6'b000010 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + initial begin + IR_D <= 0; + end + + wire RI;//译码异常 不认识的op func + assign RI = (IR_D[`op]==`j)||(IR_D[`op]==`jal) + ||(IR_D[`op]==`beq)||(IR_D[`op]==`bne)||(IR_D[`op]==`blez)||(IR_D[`op]==`bgtz)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00000)||(IR_D[`op]==6'b000001&&IR_D[`rt]==5'b00001) + ||IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu + ||IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu + ||IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb + ||(IR_D[`op]==6'b010000&&(IR_D[`rs]==5'b00000||IR_D[`rs]==5'b00100)) + ||(IR_D==32'h42000018) + ||(IR_D[`op]==`R&&(IR_D[`func]==`jr||IR_D[`func]==`jalr||IR_D[`func]==`addu||IR_D[`func]==`subu||IR_D[`func]==`add||IR_D[`func]==`sub||IR_D[`func]==`sll||IR_D[`func]==`srl||IR_D[`func]==`sra + ||IR_D[`func]==`sllv||IR_D[`func]==`srlv||IR_D[`func]==`srav||IR_D[`func]==`and_||IR_D[`func]==`or_||IR_D[`func]==`nor_||IR_D[`func]==`xor_||IR_D[`func]==`slt||IR_D[`func]==`sltu + ||IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu||IR_D[`func]==`mfhi||IR_D[`func]==`mflo||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)); + + assign excode_D = (RI==0) ? 10 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_D <= 32'h00000000; + end + else if(en) begin + IR_D <= Instr; + PC_D <= PC; + PC4_D <= PC+4; + PC8_D <= PC+8; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/MEM.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/MEM.v" new file mode 100644 index 0000000000000000000000000000000000000000..b85d5c05ef685643f157f17cda0f77adcd844440 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/MEM.v" @@ -0,0 +1,91 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:27:06 11/23/2018 +// Design Name: +// Module Name: MEM +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module MEM( + input clk, + input reset, + input en, + input [31:0] IR_E, + input [31:0] PC_E, + input [31:0] PC4_E, + input [31:0] PC8_E, + input [31:0] ALU, + input [31:0] Mult_Div, + input [31:0] RT_E, + input Zero_E, + input more_E, + input less_E, + output reg[31:0] IR_M, + output reg[31:0] PC_M, + output reg[31:0] PC4_M, + output reg[31:0] PC8_M, + output reg[31:0] AO_M, + output reg[31:0] MDO_M, + output reg[31:0] RT_M, + output [6:2] excode_M, + output reg Zero_M, + output reg more_M, + output reg less_M + ); + + `define op 31:26 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + + initial begin + IR_M <= 0; + end + + assign excode_M = ((IR_M[`op]==`lw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`lh&&AO_M[0]!=1'b0)||(IR_M[`op]==`lhu&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f0b&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| + ((IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 4 : + ((IR_M[`op]==`sw&&AO_M[1:0]!=2'b00)||(IR_M[`op]==`sh&&AO_M[0]!=1'b0)|| + ((IR_M[`op]==`sw||IR_M[`op]==`sb||IR_M[`op]==`sh)&&(AO_M<32'h00000000|| + (AO_M>32'h00002fff&&AO_M<32'h00007f00)||(AO_M>32'h00007f07&&AO_M<32'h00007f10)||AO_M>32'h00007f1b))|| //不能向COUNT写 7f07 + ((IR_M[`op]==`sb||IR_M[`op]==`sh)&&((AO_M>=32'h00007f00&&AO_M<=32'h00007f0b)|| + (AO_M>=32'h00007f10&&AO_M<=32'h00007f1b)))) ? 5 : 0; + + always@(posedge clk) begin + if(reset) begin + IR_M <= 32'h00000000; + end + else if(en) begin + IR_M <= IR_E; + PC_M <= PC_E; + PC4_M <= PC4_E; + PC8_M <= PC8_E; + AO_M <= ALU; + MDO_M <= Mult_Div; + RT_M <= RT_E; + Zero_M <= Zero_E; + more_M <= more_E; + less_M <= less_E; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/Mult_Div.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/Mult_Div.v" new file mode 100644 index 0000000000000000000000000000000000000000..17902f23aeb76b4e7bfc95d2ac782847068d23c8 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/Mult_Div.v" @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:13:10 11/30/2018 +// Design Name: +// Module Name: Mult_Div +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Mult_Div( + input clk, + input reset, + input [31:0] A, + input [31:0] B, + input [1:0] op, + input start, + input if_mthi, + input if_mtlo, + output reg Busy, + output [31:0] High, + output [31:0] Low + ); + reg [31:0] Hi; + reg [31:0] Lo; + assign High = Hi; + assign Low = Lo; + reg[31:0] cycles; + reg [63:0] tmp; + + initial begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + + always@(posedge clk) begin + if(reset) begin + Hi<=0; + Lo<=0; + cycles=0; + Busy<=0; + end + else if(!Busy) begin + if(start) begin + case(op) + 2'b00: begin//mult + tmp<=$signed(A)*$signed(B); + cycles=5; + end + 2'b01: begin//multu + tmp<=A*B; + cycles=5; + end + 2'b10: begin//div + tmp<={$signed(A)%$signed(B),$signed(A)/$signed(B)}; + cycles=10; + end + 2'b11: begin//divu + tmp<={A%B,A/B}; + cycles=10; + end + endcase + Busy<=1; + end + if(if_mthi) begin + Hi<=A; + end + if(if_mtlo) begin + Lo<=A; + end + end + else if(Busy) begin + if(cycles>0) begin + cycles=cycles-1; + if(cycles==0) begin + {Hi,Lo}<=tmp; + Busy<=0; + end + end + end + end +endmodule \ No newline at end of file diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/WB.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/WB.v" new file mode 100644 index 0000000000000000000000000000000000000000..6ad1438e720b13966f9f1d7bbff398e41f1f031d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/WB.v" @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:30:22 11/23/2018 +// Design Name: +// Module Name: WB +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module WB( + input clk, + input reset, + input en, + input [31:0] IR_M, + input [31:0] PC_M, + input [31:0] PC4_M, + input [31:0] PC8_M, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] DM, + input [31:0] CP0_M, + output reg[31:0] IR_W, + output reg[31:0] PC_W, + output reg[31:0] PC4_W, + output reg[31:0] PC8_W, + output reg[31:0] AO_W, + output reg[31:0] MDO_W, + output reg[31:0] DR_W, + output reg[31:0] CP0_W + ); + initial begin + IR_W <= 0; + end + always@(posedge clk) begin + if(reset) begin + IR_W <= 32'h00000000; + end + else if(en) begin + IR_W <= IR_M; + PC_W <= PC_M; + PC4_W <= PC4_M; + PC8_W <= PC8_M; + AO_W <= AO_M; + MDO_W <= MDO_M; + DR_W <= DM; + CP0_W <= CP0_M; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/alu.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/alu.v" new file mode 100644 index 0000000000000000000000000000000000000000..779fa26f44d1c9563d8acfa5e6eb6c115d67b156 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/alu.v" @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:01:30 11/23/2018 +// Design Name: +// Module Name: alu +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module alu( + input [31:0] A, + input [31:0] B, + input [3:0] ALUCtrl, + output reg[31:0] Result, + output over + ); + + reg[32:0] temp; + + assign over = (temp[32]!=temp[31]); + + always@(*) begin + case(ALUCtrl) + 4'b0000: begin + Result = A & B; + end + 4'b0001: begin + Result = A | B; + end + 4'b0010: begin + temp = {A[31],A[31:0]} + {B[31],B[31:0]}; + Result = A + B; + end + 4'b0011: begin + temp = {A[31],A[31:0]} - {B[31],B[31:0]}; + Result = A - B; + end + 4'b0100: begin + Result = A^B; + end + 4'b0101: begin + Result = ~(A|B); + end + 4'b0110: begin//sll sllv 逻辑左 + Result = B << A[4:0]; + end + 4'b0111: begin//srl srlv 逻辑右 + Result = B >> A[4:0]; + end + 4'b1000: begin//sra srav 算数右 + Result = $signed($signed(B) >>> A[4:0]); + end + 4'b1001: begin + Result = ($signed(A)<$signed(B)) ? 32'b1 : 32'b0; + end + 4'b1010: begin + Result = (A0) ? 1'b1 : 1'b0; + assign less = ($signed(D1)<0) ? 1'b1 : 1'b0; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/controller.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/controller.v" new file mode 100644 index 0000000000000000000000000000000000000000..097ebdd236cebd4bba9b639c9d30df8e4e6bef5d --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/controller.v" @@ -0,0 +1,1330 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 11:53:56 11/24/2018 +// Design Name: +// Module Name: controller +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module controller( + input [5:0] op, + input [5:0] func, + input [4:0] rs, + input [4:0] rt, + output reg[3:0] ALUCtrl, + output reg[1:0] RegDst, + output reg ALUASrc, + output reg ALUBSrc, + output reg RegWrite, + output reg MemRead, + output reg MemWrite, + output reg [2:0] MemtoReg, + output reg [1:0]ExtOp, + output reg if_beq, + output reg if_bne, + output reg if_blez, + output reg if_bgez, + output reg if_bltz, + output reg if_bgtz, + output reg if_j, + output reg [1:0]PCsel, + output reg if_sh, + output reg if_sb, + output reg[2:0] dataOp, + output reg[1:0] multdivOp, + output reg start, + output reg if_mthi, + output reg if_mtlo, + output reg if_mfhi, + output reg if_mflo, + output reg if_1, + output reg if_2, + output reg if_3, + output reg cp0WE + ); + initial begin + PCsel <= 2'b00; + end + always@(*) + begin + case (op) + 6'b000000://R + begin + RegDst<=2'b01; + ALUBSrc<=0; + MemRead<=0; + MemWrite<=0; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + if_sh<=0; + if_sb<=0; + if_j<=0; + dataOp<=3'b000; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(func) + 6'b100001: begin //addu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100000: begin //add + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100011: begin //subu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100010: begin //sub + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0011; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100100: begin //and + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100101: begin //or + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100110: begin //xor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0100; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b100111: begin //nor + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0101; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001000: begin //jr + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b001001: begin //jalr + ALUASrc<=0; + MemtoReg<=3'b010; + ALUCtrl<=4'b0000; + PCsel<=2'b01; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000000: begin //sll nop + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000100: begin //sllv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0110; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000010: begin //srl + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000110: begin //srlv + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0111; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000011: begin //sra + ALUASrc<=1; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b000111: begin //srav + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101010: begin //slt + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1001; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b101011: begin //sltu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b1010; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011000: begin //mult + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011001: begin //multu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b01; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011010: begin //div + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b10; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b011011: begin //divu + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b11; + start<=1; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010000: begin //mfhi + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=1; + if_mflo<=0; + end + 6'b010010: begin //mflo + ALUASrc<=0; + MemtoReg<=3'b011; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=1; + end + 6'b010001: begin //mthi + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=1; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + 6'b010011: begin //mtlo + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=0; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=1; + if_mfhi<=0; + if_mflo<=0; + end + default: begin + ALUASrc<=0; + MemtoReg<=3'b000; + ALUCtrl<=4'b0000; + PCsel<=2'b00; + RegWrite<=1; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + end + endcase + end + 6'b100011://lw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100000://lb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b010; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100100://lbu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b001; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100001://lh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b100; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b100101://lhu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=1; + MemWrite<=0; + MemtoReg<=3'b001; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b011; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101011://sw + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101001://sh + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=1; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b101000://sb + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=0; + MemRead<=0; + MemWrite<=1; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=1; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000100://beq + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=1; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000101://bne + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=1; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000111://bgtz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=1; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000110://blez + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=1; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000001://bgez/bltz + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + case(rt) + 5'b00001:begin//bgez + if_bgez<=1; + if_bltz<=0; + end + 5'b00000:begin//bltz + if_bgez<=0; + if_bltz<=1; + end + default:begin + if_bgez<=0; + if_bltz<=0; + end + endcase + end + + 6'b001111://lui + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b10; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001101://ori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001010://slti + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1001; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001011://sltiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b1010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001100://andi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001110://xori + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b01; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0100; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001001://addiu + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b001000://addi + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=1; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0010; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000011://jal + begin + RegDst<=2'b10; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=1; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b010; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b000010://j + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=1; + PCsel<=2'b10; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + + 6'b010000: + begin + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ExtOp<=2'b00; + ALUCtrl<=4'b0000; + ALUASrc<=0; + ALUBSrc<=0; + if_j<=0; + MemRead<=0; + MemWrite<=0; + RegDst<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + case(rs) + 5'b00100: //mtc0 + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b00; + cp0WE<=1; + end + 5'b00000: //mfc0 + begin + RegWrite<=1; + MemtoReg<=3'b100; + PCsel<=2'b00; + cp0WE<=0; + end + default: + begin + + end + endcase + case(func) + 6'b011000://eret + begin + RegWrite<=0; + MemtoReg<=3'b000; + PCsel<=2'b11; + cp0WE<=0; + end + default: begin + + end + endcase + end + + default: + begin + RegDst<=2'b00; + ALUASrc<=0; + ALUBSrc<=0; + RegWrite<=0; + MemRead<=0; + MemWrite<=0; + MemtoReg<=3'b000; + ExtOp<=2'b00; + if_beq<=0; + if_bne<=0; + if_bgtz<=0; + if_blez<=0; + if_bgez<=0; + if_bltz<=0; + ALUCtrl<=4'b0000; + if_j<=0; + PCsel<=2'b00; + if_sh<=0; + if_sb<=0; + dataOp<=3'b000; + multdivOp<=2'b00; + start<=0; + if_mthi<=0; + if_mtlo<=0; + if_mfhi<=0; + if_mflo<=0; + if_1<=0; + if_2<=0; + if_3<=0; + cp0WE<=0; + end + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/dm.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/dm.v" new file mode 100644 index 0000000000000000000000000000000000000000..8dc235f6441786a2939b96423488a07d442966e3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/dm.v" @@ -0,0 +1,89 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:57 11/23/2018 +// Design Name: +// Module Name: dm +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module dm( + input clk, + input reset, + input MemWrite, + input MemRead, + input if_sh, + input if_sb, + input [31:0] MemAddr, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD + ); + + reg[31:0] dm[0:4095]; + integer i; + initial begin + for(i=0;i<4096;i=i+1) begin //1024 + dm[i]<=0; + end + end + + assign RD = MemRead ? dm[MemAddr[13:2]] : 0; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<4096;i=i+1) begin//1024 + dm[i]<=0; + end + end + else begin + if(MemWrite) begin + if(if_sh) begin + if(MemAddr[1]==1'b1) begin + dm[MemAddr[13:2]][31:16] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[15:0],dm[MemAddr[13:2]][15:0]}); + end + else if(MemAddr[1]==1'b0) begin + dm[MemAddr[13:2]][15:0] <= WD[15:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[15:0]}); + end + end + else if(if_sb) begin + case(MemAddr[1:0]) + 2'b00: begin + dm[MemAddr[13:2]][7:0] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:8],WD[7:0]}); + end + 2'b01: begin + dm[MemAddr[13:2]][15:8] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:16],WD[7:0],dm[MemAddr[13:2]][7:0]}); + end + 2'b10: begin + dm[MemAddr[13:2]][23:16] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{dm[MemAddr[13:2]][31:24],WD[7:0],dm[MemAddr[13:2]][15:0]}); + end + 2'b11: begin + dm[MemAddr[13:2]][31:24] <= WD[7:0]; + $display("%d@%h: *%h <= %h",$time,PC,{MemAddr[31:2],2'b00},{WD[7:0],dm[MemAddr[13:2]][23:0]}); + end + endcase + end + else begin + dm[MemAddr[13:2]] <= WD; + $display("%d@%h: *%h <= %h",$time,PC,MemAddr,WD); + end + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ext.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ext.v" new file mode 100644 index 0000000000000000000000000000000000000000..ab616813a96964cd24ece2c94644f7d546a4fafe --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/ext.v" @@ -0,0 +1,36 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:59:19 11/23/2018 +// Design Name: +// Module Name: ext +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ext( + input [15:0] in, + input [1:0] ExtOp, + output reg [31:0] out + ); + + always@(*) begin + case(ExtOp) + 2'b00: out <= {{16{in[15]}},in}; + 2'b01: out <= {{16{1'b0}},in}; + 2'b10: out <= {in,{16{1'b0}}}; + 2'b11: out <= 0; + endcase + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/forward_mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/forward_mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..fd11f054c798b464df7a722b129173f8280ec259 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/forward_mux.v" @@ -0,0 +1,117 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:34 11/24/2018 +// Design Name: +// Module Name: forward_mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module forward_mux( + input [31:0] RS_E, + input [31:0] RT_E, + input [31:0] RT_M, + input [31:0] WD, + input [31:0] AO_M, + input [31:0] MDO_M, + input [31:0] CP0_M, + input [31:0] MD_out, + input [31:0] PC8_E, + input [31:0] PC8_M, + input [31:0] PC8_W, + input [31:0] RF_RD1, + input [31:0] RF_RD2, + input [31:0] EPCout, + input [2:0] ForwardRSD, + input [2:0] ForwardRTD, + input [2:0] ForwardRSE, + input [2:0] ForwardRTE, + input [2:0] ForwardRTM, + input [2:0] ForwardERET, + output reg[31:0] MFRSD, + output reg[31:0] MFRTD, + output reg[31:0] MFRSE, + output reg[31:0] MFRTE, + output reg[31:0] MFRTM, + output reg[31:0] MFERET + ); + + always@(*) begin + case(ForwardRSD) + 3'b000 : MFRSD <= RF_RD1; + 3'b001 : MFRSD <= AO_M; + 3'b010 : MFRSD <= WD; + 3'b011 : MFRSD <= PC8_E; + 3'b100 : MFRSD <= PC8_M; + 3'b101 : MFRSD <= CP0_M; + 3'b110 : MFRSD <= MD_out; + 3'b111 : MFRSD <= MDO_M; + default : MFRSD <= 0; + endcase + + case(ForwardRTD) + 0: MFRTD <= RF_RD2; + 1: MFRTD <= AO_M; + 2: MFRTD <= WD; + 3: MFRTD <= PC8_E; + 4: MFRTD <= PC8_M; + 5: MFRTD <= CP0_M; + 6: MFRTD <= MD_out; + 7: MFRTD <= MDO_M; + default: MFRTD <= 0; + endcase + + case(ForwardRSE) + 0:MFRSE <= RS_E; + 1:MFRSE <= AO_M; + 2:MFRSE <= WD; + 3:MFRSE <= 0; + 4:MFRSE <= PC8_M; + 5:MFRSE <= CP0_M; + 6:MFRSE <= 0; + 7:MFRSE <= MDO_M; + default:MFRSE <= 0; + endcase + + case(ForwardRTE) + 0:MFRTE <= RT_E; + 1:MFRTE <= AO_M; + 2:MFRTE <= WD; + 3:MFRTE <= 0; + 4:MFRTE <= PC8_M; + 5:MFRTE <= CP0_M; + 6:MFRTE <= 0; + 7:MFRTE <= MDO_M; + default:MFRTE <= 0; + endcase + + case(ForwardRTM) + 0:MFRTM <= RT_M; + 1:MFRTM <= 0; + 2:MFRTM <= WD; + 3:MFRTM <= 0; + 4:MFRTM <= 0; + 5:MFRTM <= 0; + 6:MFRTM <= 0; + 7:MFRTM <= 0; + default:MFRTM <= 0; + endcase + + case(ForwardERET) + 0:MFERET <= EPCout; + 1:MFERET <= MFRTM; + default:MFERET <= 0; + endcase + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/grf.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/grf.v" new file mode 100644 index 0000000000000000000000000000000000000000..90307bafbb30dc6650cbb3441f5711e3396f9a9b --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/grf.v" @@ -0,0 +1,59 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:24 11/23/2018 +// Design Name: +// Module Name: grf +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module grf( + input clk, + input reset, + input RegWrite, + input [4:0] RA1, + input [4:0] RA2, + input [4:0] WA, + input [31:0] WD, + input [31:0] PC, + output [31:0] RD1, + output [31:0] RD2 + ); + + reg[31:0] register[31:0]; + integer i; + initial begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + + assign RD1 = register[RA1]; + assign RD2 = register[RA2]; + + always@(posedge clk) begin + if(reset) begin + for(i=0;i<32;i=i+1) begin + register[i] <= 0; + end + end + else begin + if(RegWrite&&WA!=5'b00000) begin + register[WA] <= WD; + //$display("@%h: $%d <= %h", PC, WA,WD); + $display("%d@%h: $%d <= %h",$time,PC,WA,WD); + end + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/hazardUnit.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/hazardUnit.v" new file mode 100644 index 0000000000000000000000000000000000000000..14bd798e84ac5caaaa3a6f3e5a3d60a39869d4d3 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/hazardUnit.v" @@ -0,0 +1,271 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:55:59 11/24/2018 +// Design Name: +// Module Name: hazardUnit +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module hazardUnit( + input [31:0] IR_D, + input [31:0] IR_E, + input [31:0] IR_M, + input [31:0] IR_W, + input Busy, + input start, + output IR_D_en, + output IR_E_clr, + output PC_en, + output [2:0]ForwardRSD, + output [2:0]ForwardRTD, + output [2:0]ForwardRSE, + output [2:0]ForwardRTE, + output [2:0]ForwardRTM, + output [2:0]ForwardERET + ); + + `define op 31:26 + `define rs 25:21 + `define rt 20:16 + `define rd 15:11 + `define shamt 10:6 + `define func 5:0 + `define imm16 15:0 + + `define R 6'b000000 + `define lw 6'b100011 + `define lb 6'b100000 + `define lbu 6'b100100 + `define lh 6'b100001 + `define lhu 6'b100101 + `define sw 6'b101011 + `define sb 6'b101000 + `define sh 6'b101001 + `define lui 6'b001111 + `define ori 6'b001101 + `define andi 6'b001100 + `define xori 6'b001110 + `define addi 6'b001000 + `define addiu 6'b001001 + `define slti 6'b001010 + `define sltiu 6'b001011 + `define beq 6'b000100 + `define bne 6'b000101 + `define bgtz 6'b000111 + `define blez 6'b000110 + `define jal 6'b000011 + `define addu 6'b100001 + `define add 6'b100000 + `define subu 6'b100011 + `define sub 6'b100010 + `define and_ 6'b100100 + `define or_ 6'b100101 + `define xor_ 6'b100110 + `define nor_ 6'b100111 + `define sll 6'b000000 + `define srl 6'b000010 + `define sra 6'b000011 + `define sllv 6'b000100 + `define srlv 6'b000110 + `define srav 6'b000111 + `define jr 6'b001000 + `define jalr 6'b001001 + `define mult 6'b011000 + `define multu 6'b011001 + `define div 6'b011010 + `define divu 6'b011011 + `define mfhi 6'b010000 + `define mflo 6'b010010 + `define mthi 6'b010001 + `define mtlo 6'b010011 + `define slt 6'b101010 + `define sltu 6'b101011 + + `define cal_r_D (IR_D[`op]==`R&&IR_D[`func]!=`jalr&&IR_D[`func]!=`jr&&IR_D[`func]!=`mfhi&&IR_D[`func]!=`mflo&&IR_D!=0) + `define cal_r_E (IR_E[`op]==`R&&IR_E[`func]!=`jalr&&IR_E[`func]!=`jr&&IR_E[`func]!=`mfhi&&IR_E[`func]!=`mflo&&IR_E!=0) + `define cal_r_M (IR_M[`op]==`R&&IR_M[`func]!=`jalr&&IR_M[`func]!=`jr&&IR_M[`func]!=`mfhi&&IR_M[`func]!=`mflo&&IR_M!=0) + `define cal_r_W (IR_W[`op]==`R&&IR_W[`func]!=`jalr&&IR_W[`func]!=`jr&&IR_W[`func]!=`mfhi&&IR_W[`func]!=`mflo&&IR_W!=0) + + `define cal_i_D (IR_D[`op]==`lui||IR_D[`op]==`ori||IR_D[`op]==`addi||IR_D[`op]==`addiu||IR_D[`op]==`andi||IR_D[`op]==`xori||IR_D[`op]==`slti||IR_D[`op]==`sltiu) + `define cal_i_E (IR_E[`op]==`lui||IR_E[`op]==`ori||IR_E[`op]==`addi||IR_E[`op]==`addiu||IR_E[`op]==`andi||IR_E[`op]==`xori||IR_E[`op]==`slti||IR_E[`op]==`sltiu) + `define cal_i_M (IR_M[`op]==`lui||IR_M[`op]==`ori||IR_M[`op]==`addi||IR_M[`op]==`addiu||IR_M[`op]==`andi||IR_M[`op]==`xori||IR_M[`op]==`slti||IR_M[`op]==`sltiu) + `define cal_i_W (IR_W[`op]==`lui||IR_W[`op]==`ori||IR_W[`op]==`addi||IR_W[`op]==`addiu||IR_W[`op]==`andi||IR_W[`op]==`xori||IR_W[`op]==`slti||IR_W[`op]==`sltiu) + + `define load_D (IR_D[`op]==`lw||IR_D[`op]==`lb||IR_D[`op]==`lbu||IR_D[`op]==`lh||IR_D[`op]==`lhu) + `define load_E (IR_E[`op]==`lw||IR_E[`op]==`lb||IR_E[`op]==`lbu||IR_E[`op]==`lh||IR_E[`op]==`lhu) + `define load_M (IR_M[`op]==`lw||IR_M[`op]==`lb||IR_M[`op]==`lbu||IR_M[`op]==`lh||IR_M[`op]==`lhu) + `define load_W (IR_W[`op]==`lw||IR_W[`op]==`lb||IR_W[`op]==`lbu||IR_W[`op]==`lh||IR_W[`op]==`lhu) + + `define store_D (IR_D[`op]==`sw||IR_D[`op]==`sh||IR_D[`op]==`sb) + `define store_E (IR_E[`op]==`sw||IR_E[`op]==`sh||IR_E[`op]==`sb) + `define store_M (IR_M[`op]==`sw||IR_M[`op]==`sh||IR_M[`op]==`sb) + `define store_W (IR_W[`op]==`sw||IR_W[`op]==`sh||IR_W[`op]==`sb) + + `define beq_D (IR_D[`op]==`beq||IR_D[`op]==`bne||IR_D[`op]==`bgtz||IR_D[`op]==`blez||(IR_D[`op]==6'b000001&&(IR_D[`rt]==5'b00000||IR_D[`rt]==5'b00001))) + `define beq_E (IR_E[`op]==`beq||IR_E[`op]==`bne||IR_E[`op]==`bgtz||IR_E[`op]==`blez||(IR_E[`op]==6'b000001&&(IR_E[`rt]==5'b00000||IR_E[`rt]==5'b00001))) + `define beq_M (IR_M[`op]==`beq||IR_M[`op]==`bne||IR_M[`op]==`bgtz||IR_M[`op]==`blez||(IR_M[`op]==6'b000001&&(IR_M[`rt]==5'b00000||IR_M[`rt]==5'b00001))) + `define beq_W (IR_W[`op]==`beq||IR_W[`op]==`bne||IR_W[`op]==`bgtz||IR_W[`op]==`blez||(IR_W[`op]==6'b000001&&(IR_W[`rt]==5'b00000||IR_W[`rt]==5'b00001))) + + `define jal_D (IR_D[`op]==`jal) + `define jal_E (IR_E[`op]==`jal) + `define jal_M (IR_M[`op]==`jal) + `define jal_W (IR_W[`op]==`jal) + + `define jalr_D (IR_D[`op]==`R&&IR_D[`func]==`jalr) + `define jalr_E (IR_E[`op]==`R&&IR_E[`func]==`jalr) + `define jalr_M (IR_M[`op]==`R&&IR_M[`func]==`jalr) + `define jalr_W (IR_W[`op]==`R&&IR_W[`func]==`jalr) + + `define jr_D (IR_D[`op]==`R&&IR_D[`func]==`jr) + `define jr_E (IR_E[`op]==`R&&IR_E[`func]==`jr) + `define jr_M (IR_M[`op]==`R&&IR_M[`func]==`jr) + `define jr_W (IR_W[`op]==`R&&IR_W[`func]==`jr) + + `define mfhi_D (IR_D[`op]==`R&&IR_D[`func]==`mfhi) + `define mfhi_E (IR_E[`op]==`R&&IR_E[`func]==`mfhi) + `define mfhi_M (IR_M[`op]==`R&&IR_M[`func]==`mfhi) + `define mfhi_W (IR_W[`op]==`R&&IR_W[`func]==`mfhi) + + `define mflo_D (IR_D[`op]==`R&&IR_D[`func]==`mflo) + `define mflo_E (IR_E[`op]==`R&&IR_E[`func]==`mflo) + `define mflo_M (IR_M[`op]==`R&&IR_M[`func]==`mflo) + `define mflo_W (IR_W[`op]==`R&&IR_W[`func]==`mflo) + + `define mf_D (`mfhi_D||`mflo_D) + `define mf_E (`mfhi_E||`mflo_E) + `define mf_M (`mfhi_M||`mflo_M) + `define mf_W (`mfhi_W||`mflo_W) + + `define mfc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00000) + `define mfc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00000) + `define mfc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00000) + `define mfc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00000) + + `define mtc0_D (IR_D[`op]==6'b010000&&IR_D[`rs]==5'b00100) + `define mtc0_E (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100) + `define mtc0_M (IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100) + `define mtc0_W (IR_W[`op]==6'b010000&&IR_W[`rs]==5'b00100) + + reg stall=0; + wire stall_b,stall_cal_r,stall_cal_i,stall_load,stall_store,stall_jr,stall_jalr,stall_busy,stall_mfmt,stall_eret; + + assign stall_b = (`beq_D & `cal_r_E & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0||IR_D[`rt]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`beq_D & `cal_i_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_E & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`beq_D & `load_M & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0||IR_D[`rt]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_cal_r = (`cal_r_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0||IR_D[`rt]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_cal_i = (`cal_i_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_load = (`load_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_store = (`store_D) && (`load_E) && (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0); + assign stall_jr = (`jr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_jalr = (`jalr_D & (`cal_r_E) & (IR_D[`rs]==IR_E[`rd]&IR_E[`rd]!=0))|| + (`jalr_D & (`cal_i_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_E) & (IR_D[`rs]==IR_E[`rt]&IR_E[`rt]!=0))|| + (`jalr_D & (`load_M) & (IR_D[`rs]==IR_M[`rt]&IR_M[`rt]!=0)); + assign stall_busy = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) & (Busy||start); + //assign stall_mfmt = (IR_D[`op]==`R&(IR_D[`func]==`mult||IR_D[`func]==`multu||IR_D[`func]==`div||IR_D[`func]==`divu|| + // IR_D[`func]==`mflo||IR_D[`func]==`mfhi||IR_D[`func]==`mthi||IR_D[`func]==`mtlo)) + // &(IR_E[`op]==`R&(IR_E[`func]==`mult||IR_E[`func]==`multu||IR_E[`func]==`div||IR_E[`func]==`divu)); + assign stall_eret = (IR_E[`op]==6'b010000&&IR_E[`rs]==5'b00100&&IR_E[`rd]==14)&&IR_D==32'h42000018; + always@(*) begin + stall <= stall_b||stall_cal_r||stall_cal_i||stall_load||stall_store||stall_jr||stall_jalr||stall_busy||stall_eret; + end + + assign IR_D_en = !stall; + assign IR_E_clr = stall; + assign PC_en = !stall; + + `define RSD (`cal_r_D||`cal_i_D||`load_D||`store_D||`beq_D||`jr_D||`jalr_D) + `define RTD (`cal_r_D||`store_D||`beq_D||`mtc0_D) + `define RSE (`cal_r_E||`cal_i_E||`load_E||`store_E) + `define RTE (`cal_r_E||`store_E||`mtc0_E) + `define RTM (`store_M||`mtc0_M) + + assign ForwardRSD = (`RSD & `jal_E & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 3 : + (`RSD & `jalr_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 3 : + (`RSD & `mf_E & IR_D[`rs]==IR_E[`rd] & IR_D[`rs]!=0) ? 6 : + (`RSD & `cal_r_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 1 : + (`RSD & `cal_i_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 1 : + (`RSD & `jal_M & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 4 : + (`RSD & `jalr_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 4 : + (`RSD & `mf_M & IR_D[`rs]==IR_M[`rd] & IR_D[`rs]!=0) ? 5 : + (`RSD & `mfc0_M & IR_D[`rs]==IR_M[`rt] & IR_D[`rs]!=0) ? 7 : + (`RSD & `cal_r_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `cal_i_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `load_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mf_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : + (`RSD & `mfc0_W & IR_D[`rs]==IR_W[`rt] & IR_D[`rs]!=0) ? 2 : + (`RSD & `jal_W & IR_D[`rs]==31 & IR_D[`rs]!=0) ? 2 : + (`RSD & `jalr_W & IR_D[`rs]==IR_W[`rd] & IR_D[`rs]!=0) ? 2 : 0 ; + + assign ForwardRTD = (`RTD & `jal_E & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 3 : + (`RTD & `jalr_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 3 : + (`RTD & `mf_E & IR_D[`rt]==IR_E[`rd] & IR_D[`rt]!=0) ? 6 : + (`RTD & `cal_r_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 1 : + (`RTD & `cal_i_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 1 : + (`RTD & `jal_M & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 4 : + (`RTD & `jalr_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 4 : + (`RTD & `mf_M & IR_D[`rt]==IR_M[`rd] & IR_D[`rt]!=0) ? 7 : + (`RTD & `mfc0_M & IR_D[`rt]==IR_M[`rt] & IR_D[`rt]!=0) ? 5 : + (`RTD & `cal_r_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `cal_i_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `load_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mf_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : + (`RTD & `mfc0_W & IR_D[`rt]==IR_W[`rt] & IR_D[`rt]!=0) ? 2 : + (`RTD & `jal_W & IR_D[`rt]==31 & IR_D[`rt]!=0) ? 2 : + (`RTD & `jalr_W & IR_D[`rt]==IR_W[`rd] & IR_D[`rt]!=0) ? 2 : 0; + + assign ForwardRSE = (`RSE & `cal_r_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `cal_i_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 1 : + (`RSE & `jal_M & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 4 : + (`RSE & `jalr_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 4 : + (`RSE & `mf_M & (IR_E[`rs]==IR_M[`rd]) & IR_E[`rs]!=0) ? 7 : + (`RSE & `mfc0_M & (IR_E[`rs]==IR_M[`rt]) & IR_E[`rs]!=0) ? 5 : + (`RSE & `cal_r_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `cal_i_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `load_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mf_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `mfc0_W & (IR_E[`rs]==IR_W[`rt]) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jal_W & (IR_E[`rs]==31) & IR_E[`rs]!=0) ? 2 : + (`RSE & `jalr_W & (IR_E[`rs]==IR_W[`rd]) & IR_E[`rs]!=0) ? 2 : 0; + + assign ForwardRTE = (`RTE & `cal_r_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `cal_i_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 1 : + (`RTE & `jal_M & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 4 : + (`RTE & `jalr_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 4 : + (`RTE & `mf_M & (IR_E[`rt]==IR_M[`rd]) & IR_E[`rt]!=0) ? 7 : + (`RTE & `mfc0_M & (IR_E[`rt]==IR_M[`rt]) & IR_E[`rt]!=0) ? 5 : + (`RTE & `cal_r_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `cal_i_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `load_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mf_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `mfc0_W & (IR_E[`rt]==IR_W[`rt]) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jal_W & (IR_E[`rt]==31) & IR_E[`rt]!=0) ? 2 : + (`RTE & `jalr_W & (IR_E[`rt]==IR_W[`rd]) & IR_E[`rt]!=0) ? 2 : 0; + + assign ForwardRTM = (`RTM & `cal_r_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `cal_i_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `load_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mf_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `mfc0_W & (IR_M[`rt]==IR_W[`rt]) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jal_W & (IR_M[`rt]==31) & IR_M[`rt]!=0) ? 2 : + (`RTM & `jalr_W & (IR_M[`rt]==IR_W[`rd]) & IR_M[`rt]!=0) ? 2 : 0; + + assign ForwardERET = ((IR_D==32'h42000018)&&(IR_M[`op]==6'b010000&&IR_M[`rs]==5'b00100&&IR_M[`rd]==14)) ? 1 : 0; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/im.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/im.v" new file mode 100644 index 0000000000000000000000000000000000000000..5743ec5f2b17e42b6512c62f08070c6b86a83cca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/im.v" @@ -0,0 +1,35 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:57:01 11/23/2018 +// Design Name: +// Module Name: im +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module im( + input [31:0] PC, + output[31:0] instruction + ); + + reg[31:0] im[0:4095]; + initial begin + $readmemh("code.txt",im); + $readmemh("code_handler.txt",im,1120,2047); + end + + wire[31:0] pc=PC-32'h00003000; + assign instruction = im[pc[13:2]]; + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/mips.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/mips.v" new file mode 100644 index 0000000000000000000000000000000000000000..d011fae91ff309813c5ac4a0812a1a4f11c36a74 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/mips.v" @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:46:09 11/23/2018 +// Design Name: +// Module Name: mips +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mips( + input clk, + input reset + ); + + wire [31:0] PrRD; + wire [6:2] ExcCode; + wire [31:0] PrAddr; + wire [31:0] PrWD; + wire PrWe; + wire [31:0] DEV_Addr; + wire [31:0] DEV_WD; + wire [31:0] DEV0_RD; + wire [31:0] DEV1_RD; + wire WeDEV0; + wire WeDEV1; + wire IRQ0; + wire IRQ1; + + CPU my_CPU(.clk(clk),.reset(reset),.HWInt({4'b0,IRQ1,IRQ0}),.PrRD(PrRD),.ExcCode(ExcCode),.PrAddr(PrAddr),.PrWD(PrWD),.PrWe(PrWe)); + Bridge my_Bridge(PrAddr,PrWe,PrRD,PrWD,DEV_Addr,DEV_WD,DEV0_RD,DEV1_RD,WeDEV0,WeDEV1); + DEV0 my_time0(clk,reset,DEV_Addr,WeDEV0,DEV_WD,DEV0_RD,IRQ0); + DEV1 my_time1(clk,reset,DEV_Addr,WeDEV1,DEV_WD,DEV1_RD,IRQ1); + + assign ExcCode = (IRQ0||IRQ1) ? 5'b00000 : 5'b11111; +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/mux.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/mux.v" new file mode 100644 index 0000000000000000000000000000000000000000..02d800057a121623b1cb76181c21a974d0f6e996 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/mux.v" @@ -0,0 +1,78 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:31:53 11/23/2018 +// Design Name: +// Module Name: mux +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux( + input [31:0] EXT_E, + input [31:0] IR_E, + input [31:0] IR_W, + input [31:0] DR_Wnew, + input [31:0] AO_W, + input [31:0] MDO_W, + input [31:0] PC8_W, + input [31:0] CP0_W, + input [31:0] MFRSE, + input [31:0] MFRTE, + input [31:0] High, + input [31:0] Low, + input ALUasel, + input ALUbsel, + input if_mfhi, + input if_mflo, + input [1:0] RegDst, + input [2:0] MemtoReg, + output reg[31:0] ALU_A, + output reg[31:0] ALU_B, + output reg[4:0] MUX_A3, + output reg[31:0] MUX_WD, + output reg[31:0] MD_out + ); + + always@(*) begin + case(ALUasel) + 1'b0: ALU_A<=MFRSE; + 1'b1: ALU_A<={27'b0,IR_E[10:6]}; + endcase + + case(ALUbsel) + 1'b0: ALU_B<=MFRTE; + 1'b1: ALU_B<=EXT_E; + endcase + + case(RegDst) + 2'b00: MUX_A3<=IR_W[20:16]; + 2'b01: MUX_A3<=IR_W[15:11]; + 2'b10: MUX_A3<=32'h1f; + 2'b11: MUX_A3<=0; + endcase + + case(MemtoReg) + 3'b000: MUX_WD<=AO_W; + 3'b001: MUX_WD<=DR_Wnew; + 3'b010: MUX_WD<=PC8_W; + 3'b011: MUX_WD<=MDO_W; + 3'b100: MUX_WD<=CP0_W; + endcase + + if(if_mfhi) MD_out<=High; + else if(if_mflo) MD_out<=Low; + else MD_out<=0; + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/npc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/npc.v" new file mode 100644 index 0000000000000000000000000000000000000000..2326b32486b61ad162e0643debbddbdf4235c924 --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/npc.v" @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:13:22 11/23/2018 +// Design Name: +// Module Name: npc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module npc( + input [31:0] PC4, + input [31:0] PC4D, + input [25:0] I26, + input [31:0] MFRSD, + input [31:0] EPC, + input Zero, + input more, + input less, + input if_beq, + input if_bne, + input if_bgtz, + input if_blez, + input if_bgez, + input if_bltz, + input if_j,//j或jal + input[1:0] PC_sel, + input Interrupt, + output reg[31:0] next_pc + ); + reg[31:0] NPC; + always@(*) begin + if((if_beq&&Zero)||(if_bne&&!Zero)||(if_bgtz&&more)||(if_blez&&!more)||(if_bgez&&!less)||(if_bltz&&less)) begin + NPC<=PC4D+{{14{I26[15]}},I26[15:0],2'b00}; + end + else if(if_j) begin + NPC<={PC4D[31:28],I26[25:0],2'b00}; + end + else begin + NPC<=PC4D+4; + end + case(PC_sel) + 2'b00: next_pc<=PC4; + 2'b01: next_pc<=MFRSD; + 2'b10: next_pc<=NPC; + 2'b11: next_pc<=EPC; + endcase + if(Interrupt) begin + next_pc<=32'h00004180; + end + end + +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/pc.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/pc.v" new file mode 100644 index 0000000000000000000000000000000000000000..06a0733bb46e61a82eeecb3b568f77b00d2eea5a --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/pc.v" @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:02:00 11/23/2018 +// Design Name: +// Module Name: pc +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module pc( + input clk, + input reset, + input en, + input[31:0] next_pc, + output reg[31:0] pc, + output [4:0] excode_F + ); + + initial begin + pc<=32'h00003000; + end + + assign excode_F = ((pc[1:0]!=2'b00)||(pc < 32'h00003000)||(pc > 32'h00004ffc)) ? 4 : 0; + + always@(posedge clk) begin + if(reset) begin + pc <= 32'h00003000; + end + else if(en) begin + pc <= next_pc; + end + else begin + pc <= pc; + end + end +endmodule diff --git "a/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/test.v" "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/test.v" new file mode 100644 index 0000000000000000000000000000000000000000..e5caf7ea5fe230bbd63b23a8c12df7473769acca --- /dev/null +++ "b/aptx1231_BUAA_CO/P7/p7_\346\227\247/p7_9\346\224\271timer/test.v" @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 23:05:00 11/25/2018 +// Design Name: mips +// Module Name: E:/Verilog/p5/test.v +// Project Name: p5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: mips +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module test; + + // Inputs + reg clk; + reg reset; + + // Instantiate the Unit Under Test (UUT) + mips uut ( + .clk(clk), + .reset(reset) + ); + + initial begin + clk = 0; + reset = 1; + #12 reset = 0; + end + + always #10 clk = ~clk; + + +endmodule + + diff --git a/aptx1231_BUAA_CO/README.md b/aptx1231_BUAA_CO/README.md new file mode 100644 index 0000000000000000000000000000000000000000..4f4c37f50d7ee65d2e27b4081c2053869e794de9 --- /dev/null +++ b/aptx1231_BUAA_CO/README.md @@ -0,0 +1,56 @@ +# BUAA CO # + +## 鍖楄埅璁＄畻鏈哄闄㈣绠楁満缁勬垚鍘熺悊璇剧▼璁捐 ## + +### P0 椤圭洰鍚嶇О锛 閮ㄤ欢鍙婄姸鎬佹満璁捐(Logisim) ### + +璇句笅娴嬭瘯锛圥W锛: 鎼缓CRC鏍￠獙鐮佽绠楃數璺紝ALU锛屾鍒欒〃杈惧紡鍖归厤 + +璇句笂娴嬭瘯 锛圥T锛: Logisim瀹屾垚閮ㄤ欢鍙奆SM璁捐 + +### P1 椤圭洰鍚嶇О锛氶儴浠跺強鐘舵佹満璁捐(Verilog-HDL) ### +璇句笅娴嬭瘯锛圥W锛: 瀹炵幇splitter, ALU锛屾牸闆风爜璁℃暟鍣紝鍚堟硶琛ㄨ揪寮忚瘑鍒 + +璇句笂娴嬭瘯 锛圥T锛: Verilog-HDL瀹屾垚閮ㄤ欢鍙奆SM璁捐 + +### P2 椤圭洰鍚嶇О锛氭眹缂栬瑷 ### + +璇句笅娴嬭瘯锛圥W锛: 鐭╅樀涔樻硶銆佹帓搴忋佸洖鏂囦覆鍒ゆ柇 + +璇句笂娴嬭瘯 锛圥T锛: 閫夋嫨棰+缂栫▼棰 + +### P3 椤圭洰鍚嶇О锛歀ogisim寮鍙戝崟鍛ㄦ湡CPU ### + +璇句笅娴嬭瘯锛圥W锛: 瀹屾垚鏀寔7鏉℃寚浠ょ殑鍗曞懆鏈烠PU璁捐 + +璇句笂娴嬭瘯 锛圥T锛: 鏂板鎸囦护 + +### P4 椤圭洰鍚嶇О锛歏erilog寮鍙戝崟鍛ㄦ湡CPU ### + +璇句笅娴嬭瘯锛圥W锛: 瀹屾垚鏀寔7鏉℃寚浠ょ殑鍗曞懆鏈烠PU璁捐 + +璇句笂娴嬭瘯 锛圥T锛: 鏂板鎸囦护 + +### P5 椤圭洰鍚嶇О锛歏erilog寮鍙戞祦姘寸嚎CPU(1) ### + +璇句笅娴嬭瘯锛圥W锛: 瀹屾垚鏀寔10鎸囦护娴佹按绾緾PU璁捐 + +璇句笂娴嬭瘯 锛圥T锛: 娴佹按绾垮伐绋嬪寲鏂规硶 + +### P6 椤圭洰鍚嶇О锛歏erilog寮鍙戞祦姘寸嚎CPU(2) ### + +璇句笅娴嬭瘯锛圥W锛: 瀹屾垚鏀寔50鎸囦护娴佹按绾緾PU璁捐 + +璇句笂娴嬭瘯 锛圥T锛: 娴佹按绾垮伐绋嬪寲鏂规硶 + +### P7 椤圭洰鍚嶇О锛歏erilog寮鍙慚IPS寰郴缁(1) ### + +璇句笅娴嬭瘯锛圥W锛: 瀹屾垚寰瀷MIPS绯荤粺璁捐,寮鍙戠畝鍗旾/O锛岄獙璇佷腑鏂 + +璇句笂娴嬭瘯 锛圥T锛: 鐜板満娴嬭瘯 + +### P8 椤圭洰鍚嶇О锛歏erilog寮鍙慚IPS寰郴缁(2) ### + +璇句笅娴嬭瘯锛圥W锛: 瀹屾垚寰瀷MIPS绯荤粺璁捐,闆嗘垚涓插彛鎺у埗鍣紝鏉跨骇杩愯 + +璇句笂娴嬭瘯 锛圥T锛: 鐜板満娴嬭瘯 \ No newline at end of file