Add Repo: Jed-Z_computer-organization-lab

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sim_1/new/CPU_sim_1.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/13 16:02:28
+// Design Name: 
+// Module Name: CPU_sim_1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module CPU_sim_1;
+    reg clk, Reset;
+    wire [31:0] currentIAddr, nextIAddr;
+    wire [4:0] rs, rt;
+    wire [31:0] ReadData1, ReadData2;
+    wire [31:0] ALU_result, DataBus;
+    
+    top_CPU uut(
+        .clk(clk),
+        .Reset(Reset),
+        .currentIAddr(currentIAddr), .nextIAddr(nextIAddr),
+        .rs(rs), .rt(rt),
+        .ReadData1(ReadData1), .ReadData2(ReadData2),
+        .ALU_result(ALU_result), .DataBus(DataBus)
+    );
+    
+    always #50 clk = ~clk;    // ����ʱ������Ϊ100ns
+    
+    initial begin
+        clk = 1;
+        Reset = 0;
+        #25;
+        Reset = 1;    // ��ʼ����
+        #11000;        // ����11000ns�ķ���
+        $stop;  // �ϵ�
+    end
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/ALU.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:11:01
+// Design Name: 
+// Module Name: ALU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ALU(
+    input [2:0] ALUOp,
+    input [31:0] A,
+    input [31:0] B,
+    output reg [31:0] result,
+    output zero,    // ����Ƿ�Ϊ0����Ϊ1����Ϊ0
+    output sign    // ����Ƿ�Ϊ������Ϊ1����Ϊ0
+    );
+    
+    assign zero = (result == 0) ? 1 : 0;
+    assign sign = result[31];
+    
+    always @(ALUOp or A or B) begin
+        case(ALUOp)
+            3'b000: result = A + B;
+            3'b001: result = A - B;
+            3'b010: result = B << A;
+            3'b011: result = A | B;
+            3'b100: result = A & B;
+            3'b101: result = (A < B) ? 1 : 0; // 5: �Ƚ��޷�����
+            3'b110: begin                     // 6: �Ƚϴ�������
+                        if((A[31] == B[31]) && (A < B)) result = 1;
+                        else if(A[31]==1 && B[31]==0) result = 1;
+                        else result = 0;
+                    end
+            3'b111: result = A ^ B;
+        endcase
+    end
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Basys3_CPU.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:40:04
+// Design Name: 
+// Module Name: Basys3_CPU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Basys3_CPU(
+    input basys3_clock,
+    input reset_sw,
+    input [1:0] SW_in,
+    input next_button,
+    output [3:0] enable,
+    output [7:0] dispcode
+    );
+    
+    wire [31:0] currentIAddr, nextIAddr;
+    wire [4:0] rs, rt;
+    wire [31:0] ReadData1, ReadData2;
+    wire [31:0] ALU_result, DataBus;
+    
+    wire next_signal;    // ��������ֶ������ź�
+    wire [15:0] DisplayData;
+    
+    top_CPU top_CPU(
+        .clk(next_signal),    // ȡ����ʹ�ð��°�ť�ṩ�͵�ƽ���ɿ���PC�ŵ���
+        .Reset(reset_sw),
+        .currentIAddr(currentIAddr), .nextIAddr(nextIAddr),
+        .rs(rs), .rt(rt),
+        .ReadData1(ReadData1), .ReadData2(ReadData2),
+        .ALU_result(ALU_result), .DataBus(DataBus)
+    );
+        
+    Four_LED Four_LED(
+        .clock(basys3_clock),
+        .reset(reset_sw),
+        .hex3(DisplayData[15:12]),
+        .hex2(DisplayData[11:8]),
+        .hex1(DisplayData[7:4]),
+        .hex0(DisplayData[3:0]),
+        .enable(enable),
+        .dispcode(dispcode)
+    );
+    
+    Mux4_16bits Mux4_16bits(
+        .choice(SW_in),
+        .in0({currentIAddr[7:0], nextIAddr[7:0]}),
+        .in1({3'b000, rs, ReadData1[7:0]}),
+        .in2({3'b000, rt, ReadData2[7:0]}),
+        .in3({ALU_result[7:0], DataBus[7:0]}),
+        .out(DisplayData)
+    );
+    
+    Button_Debounce Button_Debounce(
+        .clk(basys3_clock),
+        .btn_in(next_button),
+        .btn_out(next_signal)
+    );
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/ControlUnit.v

@@ -0,0 +1,238 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/12 22:03:51
+// Design Name: 
+// Module Name: ControlUnit
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ControlUnit(
+    input clk, rst,
+    input zero, sign,
+    input [5:0] opcode,
+    output wire InsMemRW,
+    output reg PCWre, ALUSrcA, ALUSrcB, DBDataSrc, RegWre, WrRegDSrc, mRD, mWR, IRWre, ExtSel,
+    output reg [1:0] PCSrc,
+    output reg [1:0] RegDst,
+    output reg [2:0] ALUOp
+    );
+    
+    reg [2:0] state;
+    assign InsMemRW = 1;    // ����ʵ���У�ָ��洢��ֻ��
+    
+    /* ״̬ת�� */
+    always @(posedge clk or negedge rst) begin
+        if(rst==0) begin
+            state <= 3'b000;
+            PCWre <= 1;
+            IRWre <= 1;
+        end
+        else begin
+            case(state)
+                3'b000: state <= 3'b001;
+                3'b001: begin
+                        if(opcode==6'b110100 || opcode==6'b110101 || opcode==6'b110110) state <= 3'b101;
+                        else if(opcode==6'b110000 || opcode==6'b110001) state <= 3'b010;
+                        else if(opcode==6'b111000 || opcode==6'b111001 || opcode==6'b111010 || opcode==6'b111111)
+                            state <= 3'b000;
+                        else state <= 3'b110;
+                    end
+                3'b110: state <= 3'b111;
+                3'b010: state <= 3'b011;
+                3'b011: begin
+                        if(opcode==6'b110001) state <= 3'b100;
+                        else state <= 3'b000;
+                    end
+                3'b111, 3'b101, 3'b100: state <= 3'b000;
+            endcase
+        end
+    end
+    
+    /* ������� */
+    always @(state or opcode or zero or sign) begin  // ע�ⴥ������
+        case(opcode)
+            6'b000000: begin  // add
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_00_10_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b000001: begin  // sub
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_00_10_001;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b000010: begin  // addiu
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b010101_00_01_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b010000: begin  // and
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_00_10_100;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b010001: begin  // andi
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b010100_00_01_100;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b010010: begin  // ori
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b010100_00_01_011;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b010011: begin  // xori
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b010100_00_01_111;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b011000: begin  // sll
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b100100_00_10_010;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+           end
+            6'b100110: begin  // slti
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b010101_00_01_110;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b100111: begin  // slt
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_00_10_110;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b110: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b111: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b110000: begin  // sw
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b010101_00_00_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b010: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b011: {IRWre, mWR, RegWre} = 4'b110;
+                endcase
+            end
+            6'b110001: begin  // lw
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b011111_00_01_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b010: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b011: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b100: {IRWre, mWR, RegWre} = 4'b101;
+                endcase
+            end
+            6'b110100: begin  // beq
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, RegDst[1:0], ALUOp[2:0]} <= 11'b000101_00_001;
+                PCSrc[1:0] <= (zero==1) ? 2'b01 : 2'b00;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    default: {IRWre, mWR, RegWre} = 4'b100;
+                endcase
+            end
+            6'b110101: begin  // bne
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, RegDst[1:0], ALUOp[2:0]} <= 11'b000101_00_001;
+                PCSrc[1:0] <= (zero==0) ? 2'b01 : 2'b00;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    default: {IRWre, mWR, RegWre} = 4'b100;
+                endcase
+            end
+            6'b110110: begin  // bltz
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, RegDst[1:0], ALUOp[2:0]} <= 11'b000101_00_000;
+                PCSrc[1:0] <= (sign==1) ? 2'b01 : 2'b00;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    default: {IRWre, mWR, RegWre} = 4'b100;
+                endcase
+            end
+            6'b111000: begin  // j
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_11_00_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                endcase
+            end
+            6'b111001: begin  // jr
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_10_00_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b100;
+                endcase
+            end
+            6'b111010: begin  // jal
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000000_11_00_000;
+                case(state)
+                    3'b000: {IRWre, mWR, RegWre} = 4'b100;
+                    3'b001: {IRWre, mWR, RegWre} = 4'b101;  // jal��ID�׶���001��д�Ĵ���
+                endcase
+            end
+            6'b111111: begin  // halt
+                {ALUSrcA, ALUSrcB, DBDataSrc, WrRegDSrc, mRD, ExtSel, PCSrc[1:0], RegDst[1:0], ALUOp[2:0]} <= 13'b000100_00_00_000;
+                {IRWre, mWR, RegWre} = 4'b100;
+            end
+        endcase
+    end
+    
+    always @(negedge clk) begin
+        case(state)
+            3'b111, 3'b101, 3'b100: PCWre <= 1;
+            3'b011: PCWre <= (opcode==6'b110000 ? 1 : 0);   // sw
+            3'b001: PCWre <= (opcode==6'b111000||opcode==6'b111001||opcode==6'b111010 ? 1 : 0);  // j, jr, jal
+            default: PCWre <= 0;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Counter4.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:47:02
+// Design Name: 
+// Module Name: Counter4
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Counter4(
+    input clk,
+    output reg [1:0] count
+    );
+    
+    always @(posedge clk) begin
+        if(count == 2'b11) count <= 0;
+        else count <= count + 1;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/DFF_32bits.v

@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 20:07:17
+// Design Name: 
+// Module Name: DFF_32bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DFF_32bits(
+    input clk,
+    input Reset,
+    input [31:0] in,
+    output reg [31:0] out
+    );
+    
+    always @(posedge clk/* or negedge Reset*/) begin
+        //if(Reset==0) out <= 0;
+        /*else*/ out <= in;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/DataMemory.v

@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:14:50
+// Design Name: 
+// Module Name: DataMemory
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DataMemory(
+    input clk,
+    input [31:0] DAddr,
+    input [31:0] DataIn,
+    input RD,    // �����ƣ�1��Ч
+    input WR,    // д���ƣ�1��Ч
+    output [31:0] DataOut    // ����32���
+    );
+    
+    reg [7:0] RAM [0:63];    // ÿ���ڴ浥ԪΪ8λ����һ���ֽ�
+    
+    /* �� */
+    assign DataOut[7:0]   = (RD==1) ? RAM[DAddr+3] : 8'bz;
+    assign DataOut[15:8]  = (RD==1) ? RAM[DAddr+2] : 8'bz;
+    assign DataOut[23:16] = (RD==1) ? RAM[DAddr+1] : 8'bz;
+    assign DataOut[31:24] = (RD==1) ? RAM[DAddr+0] : 8'bz;
+    
+    /* д */
+    always @(negedge clk) begin
+        if(WR == 1) begin
+            RAM[DAddr+0] <= DataIn[31:24];
+            RAM[DAddr+1] <= DataIn[23:16];
+            RAM[DAddr+2] <= DataIn[15:8];
+            RAM[DAddr+3] <= DataIn[7:0];
+        end
+    end
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Four_LED.v

@@ -0,0 +1,65 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:39:17
+// Design Name: 
+// Module Name: Four_LED
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Four_LED(
+    input clock,
+    input reset,
+    input [3:0] hex0,
+    input [3:0] hex1,
+    input [3:0] hex2,
+    input [3:0] hex3,
+    output reg [3:0] enable,
+    output [7:0] dispcode // �߶�����ܵ�����
+    );
+    
+    wire clk_sys;
+    wire [1:0] count;
+    wire [3:0] hex_num;
+    
+    clk_div clk_div(
+        .clk(clock),
+        .clk_sys(clk_sys)
+    );
+    Counter4 Counter4(
+        .clk(clk_sys),
+        .count(count)
+    );
+    Hex_To_7Seg Hex_To_7Seg(
+        .hex(hex_num),
+        .dispcode(dispcode)
+    );
+    Mux4_4bits Mux4_4bits(
+        .choice(count),
+        .in0(hex0), .in1(hex1), .in2(hex2), .in3(hex3),
+        .out(hex_num)
+    );
+    
+    always @(count) begin
+        case(count)
+            2'b00: enable = 4'b1110;
+            2'b01: enable = 4'b1101;
+            2'b10: enable = 4'b1011;
+            2'b11: enable = 4'b0111;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Hex_To_7Seg.v

@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:47:40
+// Design Name: 
+// Module Name: Hex_To_7Seg
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Hex_To_7Seg(
+    input [3:0] hex,
+    output reg [7:0] dispcode
+    );
+    
+    always @(hex) begin
+        //  '0'- ���ƣ�'1'- Ϩ��
+        // [7:0] �����ң�DP,g,f,e,d,c,b,a
+        case(hex)
+            4'h0: dispcode <= 8'b1100_0000; //0
+            4'h1: dispcode <= 8'b1111_1001; //1
+            4'h2: dispcode <= 8'b1010_0100; //2
+            4'h3: dispcode <= 8'b1011_0000; //3
+            4'h4: dispcode <= 8'b1001_1001; //4
+            4'h5: dispcode <= 8'b1001_0010; //5
+            4'h6: dispcode <= 8'b1000_0010; //6
+            4'h7: dispcode <= 8'b1101_1000; //7
+            4'h8: dispcode <= 8'b1000_0000; //8
+            4'h9: dispcode <= 8'b1001_0000; //9
+            4'hA: dispcode <= 8'b1000_1000; //A
+            4'hB: dispcode <= 8'b1000_0011; //b
+            4'hC: dispcode <= 8'b1100_0110; //C
+            4'hD: dispcode <= 8'b1010_0001; //d
+            4'hE: dispcode <= 8'b1000_0110; //E
+            4'hF: dispcode <= 8'b1000_1110; //F
+            default: dispcode <= 8'b0000_0000; // ����
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/IR.v

@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/13 16:52:35
+// Design Name: 
+// Module Name: IR
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module IR(
+    input clk,
+    input IRWre,
+    input [31:0] insIn,
+    output reg [31:0] insOut
+    );
+    
+    always @(negedge clk) begin
+        /*if(IRWre==1)*/ insOut <= insIn;
+       /* else insOut <= insOut;*/
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/ImmediateExtend.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:21:36
+// Design Name: 
+// Module Name: ImmediateExtend
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ImmediateExtend(
+    input [15:0] original,
+    input ExtSel,    // 0: Zero-extend; 1: Sign-extend.
+    output reg [31:0] extended
+    );
+    
+    always @(*) begin
+        extended[15:0] <= original;    // ??16��???????
+        if(ExtSel == 0) begin    // Zero-extend ?????
+            extended[31:16] <= 0;
+        end
+        else begin    // Sign-extended ???????
+            if(original[15] == 0) extended[31:16] <= 0;
+            else extended[31:16] <= 16'hFFFF;
+        end
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/InstructionMemory.v

@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:17:34
+// Design Name: 
+// Module Name: InstructionMemory
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module InstructionMemory(
+    input [31:0] IAddr,
+    //input [31:0] IDataIn,
+    //input RW,    // ָ��洢����д�����źţ�Ϊ0д��Ϊ1��
+    output [31:0] IDataOut
+    );
+    
+    reg [7:0] ROM [0:127];
+    
+    initial begin
+        $readmemb("E:/_Vivado/MIPS_CPU_Design/MultiCycleCPU/test_instructions.txt", ROM);
+    end
+    
+    assign IDataOut[31:24] = ROM[IAddr+0];
+    assign IDataOut[23:16] = ROM[IAddr+1];
+    assign IDataOut[15:8]  = ROM[IAddr+2];
+    assign IDataOut[7:0]   = ROM[IAddr+3];
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Mux2_32bits.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:31:00
+// Design Name: 
+// Module Name: Mux2_32bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux2_32bits(
+    input choice,
+    input [31:0] in0,
+    input [31:0] in1,
+    output [31:0] out
+    );
+    
+    assign out = (choice==0) ? in0 : in1;
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Mux4_16bits.v

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:40:56
+// Design Name: 
+// Module Name: Mux4_16bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_16bits(
+    input [1:0] choice,
+    input [15:0] in0,
+    input [15:0] in1,
+    input [15:0] in2,
+    input [15:0] in3,
+    output reg [15:0] out
+    );
+    
+    always @(choice or in0 or in1 or in2 or in3) begin
+        case(choice)
+            2'b00: out = in0;
+            2'b01: out = in1;
+            2'b10: out = in2;
+            2'b11: out = in3;
+            default: out = 0;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Mux4_32bits.v

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:27:41
+// Design Name: 
+// Module Name: Mux4_32bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_32bits(
+    input [1:0] choice,
+    input [31:0] in0,
+    input [31:0] in1,
+    input [31:0] in2,
+    input [31:0] in3,
+    output reg [31:0] out
+    );
+    
+    always @(choice or in0 or in1 or in2 or in3) begin
+        case(choice)
+            2'b00: out = in0;
+            2'b01: out = in1;
+            2'b10: out = in2;
+            2'b11: out = in3;
+            default: out = 0;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Mux4_4bits.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:48:38
+// Design Name: 
+// Module Name: Mux4_4bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_4bits(
+    input [1:0] choice,
+    input [3:0] in0, in1, in2, in3,
+    output reg [3:0] out
+    );
+    
+    always @(*) begin
+        case(choice)
+            0: out <= in0;
+            1: out <= in1;
+            2: out <= in2;
+            3: out <= in3;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/Mux4_5bits.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:28:44
+// Design Name: 
+// Module Name: Mux4_5bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_5bits(
+    input [1:0] choice,
+    input [4:0] in0, in1, in2, in3,
+    output reg [4:0] out
+    );
+    
+    always @(*) begin
+        case(choice)
+            0: out <= in0;
+            1: out <= in1;
+            2: out <= in2;
+            3: out <= in3;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/PC.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:22:47
+// Design Name: 
+// Module Name: PC
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module PC(
+    input clk,
+    input Reset,
+    input PCWre,
+    input [31:0] nextIAddr,
+    output reg [31:0] currentIAddr
+    );
+    
+    initial currentIAddr <= 0;
+    
+    always @(posedge clk or negedge Reset) begin
+        if(Reset == 0) currentIAddr <= 0;
+        else begin
+            if(PCWre == 1) currentIAddr <= nextIAddr;
+            else currentIAddr <= currentIAddr;
+        end
+    end
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/RegisterFile.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/11 19:19:48
+// Design Name: 
+// Module Name: RegisterFile
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module RegisterFile(
+    input clk,
+    input Reset,
+    input WE,    // �Ĵ�����дʹ�ܣ�1Ϊ��Ч
+    input [4:0] ReadReg1,
+    input [4:0] ReadReg2,
+    input [4:0] WriteReg,
+    input [31:0] WriteData,
+    output [31:0] ReadData1,
+    output [31:0] ReadData2
+    );
+    
+    reg [31:0] file [1:31];
+    integer i;
+    
+    assign ReadData1 = (ReadReg1 == 0) ? 0 : file[ReadReg1];
+    assign ReadData2 = (ReadReg2 == 0) ? 0 : file[ReadReg2];
+    
+    always @(negedge clk or negedge Reset) begin
+        if(Reset == 0) begin
+            for(i = 1; i <= 31; i=i+1) begin
+                file[i] <= 0;
+            end
+        end
+        else if(WE == 1 && WriteReg != 0)
+            file[WriteReg] <= WriteData;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/clk_div.v

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/18 20:46:27
+// Design Name: 
+// Module Name: clk_div
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clk_div(
+    input clk,
+    output reg clk_sys = 0
+    );
+    
+    reg [25:0] div_counter = 0;
+    always @(posedge clk) begin
+        if(div_counter >= 50000) begin
+            clk_sys <= ~clk_sys;
+            div_counter <= 0;
+        end
+        else div_counter <= div_counter + 1;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/MultiCycleCPU.srcs/sources_1/new/top_CPU.v

@@ -0,0 +1,138 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/12/13 16:57:32
+// Design Name: 
+// Module Name: top_CPU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_CPU(
+    input clk,
+    input Reset,
+    output [31:0] currentIAddr, nextIAddr,
+    output [4:0] rs, rt,
+    output [31:0] ReadData1, ReadData2,
+    output [31:0] ALU_result, DataBus
+    );
+    /* ��������ͨ· */
+    wire [31:0] bincode, IDataOut;
+    wire [31:0] ALU_inA, ALU_inB;
+    wire [31:0] DataOut;
+    wire [5:0] opcode;
+    wire ALU_zero, ALU_sign;
+    wire [15:0] immediate;
+    wire [31:0] extended;
+    wire [31:0] ADR_out, BDR_out, ALUoutDR_out, DataBus_before;
+    wire [4:0] rd;
+    
+    assign opcode = bincode[31:26];
+    assign rs = bincode[25:21];
+    assign rt = bincode[20:16];
+    assign rd = bincode[15:11];
+    assign immediate = bincode[15:0];
+    
+    /* �����ź� */
+    wire PCWre, ALUSrcA, ALUSrcB, DBDataSrc, RegWre, WrRegDSrc, InsMemRW, mRD, mWR, IRWre, ExtSel;
+    wire [1:0] PCSrc;
+    wire [1:0] RegDst;
+    wire [2:0] ALUOp;
+    wire [5:0] WriteReg;
+    wire [31:0] WriteData;
+    
+    /* CPU�Ĺؼ����� */
+    ControlUnit ControlUnit(
+        .clk(clk), .rst(Reset),
+        .zero(ALU_zero), .sign(ALU_sign),
+        .opcode(opcode),
+        .PCWre(PCWre), .ALUSrcA(ALUSrcA), .ALUSrcB(ALUSrcB), .DBDataSrc(DBDataSrc), .RegWre(RegWre), .WrRegDSrc(WrRegDSrc), .InsMemRW(InsMemRW), .mRD(mRD), .mWR(mWR), .IRWre(IRWre), .ExtSel(ExtSel),
+        .PCSrc(PCSrc),
+        .RegDst(RegDst),
+        .ALUOp(ALUOp)
+    );
+    PC PC(
+        .clk(clk), .Reset(Reset), .PCWre(PCWre), .nextIAddr(nextIAddr),
+        .currentIAddr(currentIAddr)
+    );
+    InstructionMemory InstructionMemory(
+        .IAddr(currentIAddr),
+        .IDataOut(IDataOut)
+    );
+    RegisterFile RegisterFile(
+        .clk(clk), .Reset(Reset), .WE(RegWre),
+        .ReadReg1(rs), .ReadReg2(rt), .WriteReg(WriteReg), .WriteData(WriteData),
+        .ReadData1(ReadData1), .ReadData2(ReadData2)
+    );
+    ALU ALU(
+        .ALUOp(ALUOp), .A(ALU_inA), .B(ALU_inB),
+        .result(ALU_result), .zero(ALU_zero), .sign(ALU_sign)
+    );
+    DataMemory DataMemory(
+        .clk(clk), .DAddr(ALU_result), .DataIn(ReadData2), .RD(mRD), .WR(mWR),
+        .DataOut(DataOut)
+    );
+    ImmediateExtend ImmediateExtend(
+        .original(immediate), .ExtSel(ExtSel),
+        .extended(extended)
+    );
+    
+    /* ������CPU���еļĴ��� */
+    IR IR(
+        .clk(clk), .IRWre(IRWre), .insIn(IDataOut),
+        .insOut(bincode)
+    );
+    DFF_32bits ADR(
+        .clk(clk), .Reset(Reset), .in(ReadData1),
+        .out(ADR_out)
+    );
+    DFF_32bits BDR(
+        .clk(clk), .Reset(Reset), .in(ReadData2),
+        .out(BDR_out)
+    );
+    DFF_32bits ALUoutDR(
+        .clk(clk), .Reset(Reset), .in(ALU_result),
+        .out(ALUoutDR_out)
+    );
+    DFF_32bits DBDR(
+        .clk(clk), .Reset(Reset), .in(DataBus_before),
+        .out(DataBus)
+    );
+    /* ����ѡ���� */
+    Mux4_32bits Mux_nextIAddr(
+        .choice(PCSrc), .in0(currentIAddr+4), .in1(currentIAddr+4+(extended<<2)), .in2(ReadData1), .in3({currentIAddr[31:28], bincode[25:0], 2'b00}),
+        .out(nextIAddr)
+    );
+    Mux4_5bits Mux_WriteReg(
+        .choice(RegDst), .in0(5'd31), .in1(rt), .in2(rd), .in3(5'bzzzzz),
+        .out(WriteReg)
+    );
+    Mux2_32bits Mux_WriteData(
+        .choice(WrRegDSrc), .in0(currentIAddr+4), .in1(DataBus),
+        .out(WriteData)
+    );
+    Mux2_32bits Mux_ALU_inA(
+        .choice(ALUSrcA), .in0(ADR_out), .in1({27'd0, immediate[10:6]}),
+        .out(ALU_inA)
+    );
+    Mux2_32bits Mux_ALU_inB(
+        .choice(ALUSrcB), .in0(BDR_out), .in1(extended),
+        .out(ALU_inB)
+    );
+    Mux2_32bits Mux_DBDR(
+        .choice(DBDataSrc), .in0(ALU_result), .in1(DataOut),
+        .out(DataBus_before)
+    );
+endmodule

Jed-Z_computer-organization-lab/MultiCycleCPU/test_instructions.txt

@@ -0,0 +1,24 @@
+00001000 00000001 00000000 00001000
+01001000 00000010 00000000 00000010
+01001100 01000011 00000000 00001000
+00000100 01100001 00100000 00000000
+01000000 10000010 00101000 00000000
+01100000 00000101 00101000 10000000
+11010000 10100001 11111111 11111110
+11101000 00000000 00000000 00010100
+10011101 10100001 01000000 00000000
+00001000 00001110 11111111 11111110
+10011101 00001110 01001000 00000000
+10011001 00101010 00000000 00000010
+10011001 01001011 00000000 00000000
+00000001 01101010 01011000 00000000
+11010101 01100010 11111111 11111110
+00001000 00001100 11111111 11111110
+00001001 10001100 00000000 00000001
+11011001 10000000 11111111 11111110
+01000100 01001100 00000000 00000010
+11100000 00000000 00000000 00010111
+11000000 00100010 00000000 00000100
+11000100 00101101 00000000 00000100
+11100111 11100000 00000000 00000000
+11111100 00000000 00000000 00000000

Jed-Z_computer-organization-lab/README.md

@@ -0,0 +1,17 @@
+# 计算机组成原理实验（课程项目）
+
+使用 Verilog HDL 实现的简易单周期和多周期 CPU 设计。
+
+* 中山大学计算机学院
+* 操作系统原理实验（Laboratory of Computer Organization, DCS209）
+* 教师：何朝东
+* 2018-2019 学年第一学期（大二上）
+
+
+## 目录说明
+
+这些文件是从 Vivado 2018.1 的工程中提取的，仅保留了`.srcs`目录。
+
+* [MultiCycleCPU](MultiCycleCPU)：多周期 CPU 设计与实现。
+* [SingleCycleCPU](SingleCycleCPU)：单周期 CPU 设计与实现。
+* [hex_to_7seg](hex_to_7seg)：子模块，作用是将十六进制数转换为可供七段数码管显示的编码。

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sim_1/new/CPU_sim_1.v

@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/14 15:44:41
+// Design Name: 
+// Module Name: CPU_sim_1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module CPU_sim_1;
+    reg clk, Reset;
+    wire [31:0] currentIAddr, nextIAddr;
+    wire [4:0] rs, rt;
+    wire [31:0] ReadData1, ReadData2;
+    wire [31:0] ALU_result, DataBus;
+    
+    top_CPU uut(
+        .clk(clk),
+        .Reset(Reset),
+        .currentIAddr(currentIAddr), .nextIAddr(nextIAddr),
+        .rs(rs), .rt(rt),
+        .ReadData1(ReadData1), .ReadData2(ReadData2),
+        .ALU_result(ALU_result), .DataBus(DataBus)
+    );
+    
+    always #50 clk = ~clk;    // ����ʱ������Ϊ100ns
+    
+    initial begin
+        clk = 1;
+        Reset = 0;
+        #25;
+        Reset = 1;    // ��ʼ����
+        #3000;        // ����3000ns�ķ���
+        #100; $stop; // �ϵ�
+    end
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/ALU.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/12 14:47:50
+// Design Name: 
+// Module Name: ALU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ALU(
+    input [2:0] ALUOp,
+    input [31:0] A,
+    input [31:0] B,
+    output reg [31:0] result,
+    output zero,    // ����Ƿ�Ϊ0����Ϊ1����Ϊ0
+    output sign    // ����Ƿ�Ϊ������Ϊ1����Ϊ0
+    );
+    
+    assign zero = (result == 0) ? 1 : 0;
+    assign sign = result[31];
+    
+    always @(ALUOp or A or B) begin
+        case(ALUOp)
+            3'b000: result = A + B;
+            3'b001: result = A - B;
+            3'b010: result = B << A;
+            3'b011: result = A | B;
+            3'b100: result = A & B;
+            3'b101: result = (A < B) ? 1 : 0; // 5: �Ƚ��޷�����
+            3'b110: begin                     // 6: �Ƚϴ�������
+                        if((A[31] == B[31]) && (A < B)) result = 1;
+                        else if(A[31]==1 && B[31]==0) result = 1;
+                        else result = 0;
+                    end
+            3'b111: result = A ^ B;
+        endcase
+    end
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Basys3_CPU.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/16 22:11:31
+// Design Name: 
+// Module Name: Basys3_CPU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Basys3_CPU(
+    input basys3_clock,
+    input reset_sw,
+    input [1:0] SW_in,
+    input next_button,
+    output [3:0] enable,
+    output [7:0] dispcode
+    );
+    
+    wire [31:0] currentIAddr, nextIAddr;
+    wire [4:0] rs, rt;
+    wire [31:0] ReadData1, ReadData2;
+    wire [31:0] ALU_result, DataBus;
+    
+    wire next_signal;    // ��������ֶ������ź�
+    wire [15:0] DisplayData;
+    
+    top_CPU top_CPU(
+        .clk(next_signal),    // ȡ����ʹ�ð��°�ť�ṩ�͵�ƽ���ɿ���PC�ŵ���
+        .Reset(reset_sw),
+        .currentIAddr(currentIAddr), .nextIAddr(nextIAddr),
+        .rs(rs), .rt(rt),
+        .ReadData1(ReadData1), .ReadData2(ReadData2),
+        .ALU_result(ALU_result), .DataBus(DataBus)
+    );
+        
+    Four_LED Four_LED(
+        .clock(basys3_clock),
+        .reset(reset_sw),
+        .hex3(DisplayData[15:12]),
+        .hex2(DisplayData[11:8]),
+        .hex1(DisplayData[7:4]),
+        .hex0(DisplayData[3:0]),
+        .enable(enable),
+        .dispcode(dispcode)
+    );
+    
+    Mux4_16bits Mux4_16bits(
+        .choice(SW_in),
+        .in0({currentIAddr[7:0], nextIAddr[7:0]}),
+        .in1({3'b000, rs, ReadData1[7:0]}),
+        .in2({3'b000, rt, ReadData2[7:0]}),
+        .in3({ALU_result[7:0], DataBus[7:0]}),
+        .out(DisplayData)
+    );
+    
+    Button_Debounce Button_Debounce(
+        .clk(basys3_clock),
+        .btn_in(next_button),
+        .btn_out(next_signal)
+    );
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Button_Debounce.v

@@ -0,0 +1,59 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/16 23:55:36
+// Design Name: 
+// Module Name: Button_Debounce
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Button_Debounce(
+    input clk,
+    input btn_in,
+    output btn_out
+    );
+    
+    reg [2:0] btn=0;
+    wire clk_20ms;
+    
+    ClockDivisor #(1000000) t_20ms(clk,clk_20ms);
+    
+    always @(posedge clk_20ms) begin
+        btn[0]<=btn_in;
+        btn[1]<=btn[0];
+        btn[2]<=btn[1];
+    end
+    assign btn_out=(btn[2]&btn[1]&btn[0])|(~btn[2]&btn[1]&btn[0]);
+endmodule
+
+
+module ClockDivisor(
+    input clkin,
+    output reg clkout=0
+    );
+    parameter n=50000000;
+    reg [31:0] count=1;
+    always @ (posedge clkin)
+    begin
+        if(count<n)
+            count<=count+1;
+        else
+        begin
+            count<=1;
+            clkout<=~clkout;
+        end
+    end
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/ControlUnit.v

@@ -0,0 +1,129 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/14 13:49:51
+// Design Name: 
+// Module Name: ControlUnit
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ControlUnit(
+    input [5:0] opcode,
+    input zero,
+    input sign,
+    output reg PCWre,
+    output reg ALUSrcA,
+    output reg ALUSrcB,
+    output reg DBDataSrc,
+    output reg RegWre,
+    output reg InsMemRW,
+    output reg mRD,
+    output reg mWR,
+    output reg RegDst,
+    output reg ExtSel,
+    output reg [1:0] PCSrc,
+    output reg [2:0] ALUOp
+    );
+    
+    always @(opcode or zero or sign) begin
+        case(opcode)
+            6'b000000: begin    // add
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000110010;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_000;
+            end
+            6'b000001: begin    // sub
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000110010;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_001;
+            end
+            6'b000010: begin    // addiu
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b010110001;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_000;
+            end
+            6'b010000: begin    // andi
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b010110000;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_100;
+            end
+            6'b010001: begin    // and
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000110010;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_100;
+            end
+            6'b010010: begin    // ori
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b010110000;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_011;
+            end
+            6'b010011: begin    // or
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000110010;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_011;
+            end
+            6'b011000: begin    // sll
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b100110010;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_010;
+            end
+            6'b011100: begin    // slti
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b010110001;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_110;
+            end
+            6'b100110: begin    // sw
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b010010101;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_000;
+            end
+            6'b100111: begin    // lw
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b011111001;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b00_000;
+            end
+            6'b110000: begin    // beq
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000010001;
+                PCSrc[1:0] <= (zero==1) ? 2'b01 : 2'b00;
+                ALUOp[2:0] <= 3'b001;
+            end
+            6'b110001: begin    // bne
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000010001;
+                PCSrc[1:0] <= (zero==0) ? 2'b01 : 2'b00;
+                ALUOp[2:0] <= 3'b001;
+            end
+            6'b110010: begin    // bltz
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000010001;
+                PCSrc[1:0] <= (sign==1) ? 2'b01 : 2'b00;
+                ALUOp[2:0] <= 3'b000;
+            end
+            6'b111000: begin    // j
+                PCWre <= 1;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000010000;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b10_000;
+            end
+            6'b111111: begin    // halt
+                PCWre <= 0;
+                {ALUSrcA, ALUSrcB, DBDataSrc, RegWre, InsMemRW, mRD, mWR, RegDst, ExtSel} <= 9'b000010000;
+                {PCSrc[1:0], ALUOp[2:0]} <= 5'b11_000;
+            end
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Counter4.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 14:03:28
+// Design Name: 
+// Module Name: Counter4
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Counter4(
+    input clk,
+    output reg [1:0] count
+    );
+    
+    always @(posedge clk) begin
+        if(count == 2'b11) count <= 0;
+        else count <= count + 1;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/DataMemory.v

@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/12 15:08:38
+// Design Name: 
+// Module Name: DataMemory
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DataMemory(
+    input clk,
+    input [31:0] DAddr,
+    input [31:0] DataIn,
+    input RD,    // �����ƣ�1��Ч
+    input WR,    // д���ƣ�1��Ч
+    output [31:0] DataOut    // ����32���
+    );
+    
+    reg [7:0] RAM [0:63];    // ÿ���ڴ浥ԪΪ8λ����һ���ֽ�
+    
+    /* �� */
+    assign DataOut[7:0]   = (RD==1) ? RAM[DAddr+3] : 8'bz;
+    assign DataOut[15:8]  = (RD==1) ? RAM[DAddr+2] : 8'bz;
+    assign DataOut[23:16] = (RD==1) ? RAM[DAddr+1] : 8'bz;
+    assign DataOut[31:24] = (RD==1) ? RAM[DAddr+0] : 8'bz;
+    
+    /* д */
+    always @(negedge clk) begin
+        if(WR == 1) begin
+            RAM[DAddr+0] <= DataIn[31:24];
+            RAM[DAddr+1] <= DataIn[23:16];
+            RAM[DAddr+2] <= DataIn[15:8];
+            RAM[DAddr+3] <= DataIn[7:0];
+        end
+    end
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Four_LED.v

@@ -0,0 +1,65 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 17:29:57
+// Design Name: 
+// Module Name: top_LEDs
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Four_LED(
+    input clock,
+    input reset,
+    input [3:0] hex0,
+    input [3:0] hex1,
+    input [3:0] hex2,
+    input [3:0] hex3,
+    output reg [3:0] enable,
+    output [7:0] dispcode // �߶�����ܵ�����
+    );
+    
+    wire clk_sys;
+    wire [1:0] count;
+    wire [3:0] hex_num;
+    
+    clk_div clk_div(
+        .clk(clock),
+        .clk_sys(clk_sys)
+    );
+    Counter4 Counter4(
+        .clk(clk_sys),
+        .count(count)
+    );
+    Hex_To_7Seg Hex_To_7Seg(
+        .hex(hex_num),
+        .dispcode(dispcode)
+    );
+    Mux4_4bits Mux4_4bits(
+        .choice(count),
+        .in0(hex0), .in1(hex1), .in2(hex2), .in3(hex3),
+        .out(hex_num)
+    );
+    
+    always @(count) begin
+        case(count)
+            2'b00: enable = 4'b1110;
+            2'b01: enable = 4'b1101;
+            2'b10: enable = 4'b1011;
+            2'b11: enable = 4'b0111;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Hex_To_7Seg.v

@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 13:52:22
+// Design Name: 
+// Module Name: Hex_To_7Seg
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Hex_To_7Seg(
+    input [3:0] hex,
+    output reg [7:0] dispcode
+    );
+    
+    always @(hex) begin
+        //  '0'- ���ƣ�'1'- Ϩ��
+        // [7:0] �����ң�DP,g,f,e,d,c,b,a
+        case(hex)
+            4'h0: dispcode <= 8'b1100_0000; //0
+            4'h1: dispcode <= 8'b1111_1001; //1
+            4'h2: dispcode <= 8'b1010_0100; //2
+            4'h3: dispcode <= 8'b1011_0000; //3
+            4'h4: dispcode <= 8'b1001_1001; //4
+            4'h5: dispcode <= 8'b1001_0010; //5
+            4'h6: dispcode <= 8'b1000_0010; //6
+            4'h7: dispcode <= 8'b1101_1000; //7
+            4'h8: dispcode <= 8'b1000_0000; //8
+            4'h9: dispcode <= 8'b1001_0000; //9
+            4'hA: dispcode <= 8'b1000_1000; //A
+            4'hB: dispcode <= 8'b1000_0011; //b
+            4'hC: dispcode <= 8'b1100_0110; //C
+            4'hD: dispcode <= 8'b1010_0001; //d
+            4'hE: dispcode <= 8'b1000_0110; //E
+            4'hF: dispcode <= 8'b1000_1110; //F
+            default: dispcode <= 8'b0000_0000; // ����
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/ImmediateExtend.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/13 19:57:33
+// Design Name: 
+// Module Name: ImmediateExtend
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ImmediateExtend(
+    input [15:0] original,
+    input ExtSel,    // 0: Zero-extend; 1: Sign-extend.
+    output reg [31:0] extended
+    );
+    
+    always @(*) begin
+        extended[15:0] <= original;    // ��16λ���ֲ���
+        if(ExtSel == 0) begin    // Zero-extend ����չ
+            extended[31:16] <= 0;
+        end
+        else begin    // Sign-extended ������չ
+            if(original[15] == 0) extended[31:16] <= 0;
+            else extended[31:16] <= 16'hFFFF;
+        end
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/InstructionMemory.v

@@ -0,0 +1,55 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/12 16:38:30
+// Design Name: 
+// Module Name: InstructionMemory
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module InstructionMemory(
+    input [31:0] IAddr,
+    //input [31:0] IDataIn,
+    //input RW,    // ָ��洢����д�����źţ�Ϊ0д��Ϊ1��
+    output [31:0] IDataOut
+    );
+    
+    reg [7:0] ROM [0:95];
+    
+    initial begin
+        $readmemb("E:/_Vivado/MIPS_CPU_Design/SingleCycleCPU/test_instructions.txt", ROM);
+    end
+    
+    assign IDataOut[31:24] = ROM[IAddr+0];
+    assign IDataOut[23:16] = ROM[IAddr+1];
+    assign IDataOut[15:8]  = ROM[IAddr+2];
+    assign IDataOut[7:0]   = ROM[IAddr+3];
+//    always @(RW or Iaddr) begin
+//        if(RW == 1) begin
+//            IDataOut[31:24] <= ROM[Iaddr+0];
+//            IDataOut[23:16] <= ROM[Iaddr+1];
+//            IDataOut[15:8]  <= ROM[Iaddr+2];
+//            IDataOut[7:0]   <= ROM[Iaddr+3];
+//        end
+//        else begin
+//            ROM[Iaddr+0] <= IDataIn[31:24];
+//            ROM[Iaddr+1] <= IDataIn[23:16];
+//            ROM[Iaddr+2] <= IDataIn[15:8];
+//            ROM[Iaddr+3] <= IDataIn[7:0];
+//        end
+//    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Mux2_32bits.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/12 16:57:22
+// Design Name: 
+// Module Name: Mux2_32bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux2_32bits(
+    input choice,
+    input [31:0] in0,
+    input [31:0] in1,
+    output [31:0] out
+    );
+    
+    assign out = (choice==0) ? in0 : in1;
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Mux2_5bits.v

@@ -0,0 +1,32 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/12 16:59:42
+// Design Name: 
+// Module Name: Mux2_5bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux2_5bits(
+    input choice,
+    input [4:0] in0,
+    input [4:0] in1,
+    output [4:0] out
+    );
+    
+    assign out = (choice==0) ? in0 : in1;
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Mux4_16bits.v

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/17 00:14:34
+// Design Name: 
+// Module Name: Mux4_16bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_16bits(
+    input [1:0] choice,
+    input [15:0] in0,
+    input [15:0] in1,
+    input [15:0] in2,
+    input [15:0] in3,
+    output reg [15:0] out
+    );
+    
+    always @(choice or in0 or in1 or in2 or in3) begin
+        case(choice)
+            2'b00: out = in0;
+            2'b01: out = in1;
+            2'b10: out = in2;
+            2'b11: out = in3;
+            default: out = 0;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Mux4_32bits.v

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/14 13:56:31
+// Design Name: 
+// Module Name: Mux4_32bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_32bits(
+    input [1:0] choice,
+    input [31:0] in0,
+    input [31:0] in1,
+    input [31:0] in2,
+    input [31:0] in3,
+    output reg [31:0] out
+    );
+    
+    always @(choice or in0 or in1 or in2 or in3) begin
+        case(choice)
+            2'b00: out = in0;
+            2'b01: out = in1;
+            2'b10: out = in2;
+            2'b11: out = in3;
+            default: out = 0;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/Mux4_4bits.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 14:00:50
+// Design Name: 
+// Module Name: Mux4_8bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_4bits(
+    input [1:0] choice,
+    input [3:0] in0, in1, in2, in3,
+    output reg [3:0] out
+    );
+    
+    always @(*) begin
+        case(choice)
+            0: out <= in0;
+            1: out <= in1;
+            2: out <= in2;
+            3: out <= in3;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/PC.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/13 18:50:14
+// Design Name: 
+// Module Name: PC
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module PC(
+    input clk,
+    input Reset,
+    input PCWre,
+    input [31:0] nextIAddr,
+    output reg [31:0] currentIAddr
+    );
+    
+    initial currentIAddr <= 0;
+    
+    always @(posedge clk or negedge Reset) begin
+        if(Reset == 0) currentIAddr <= 0;
+        else begin
+            if(PCWre == 1) currentIAddr <= nextIAddr;
+            else currentIAddr <= currentIAddr;
+        end
+    end
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/RegisterFile.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/12 15:40:53
+// Design Name: 
+// Module Name: RegisterFile
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module RegisterFile(
+    input clk,
+    input Reset,
+    input WE,    // �Ĵ�����дʹ�ܣ�1Ϊ��Ч
+    input [4:0] ReadReg1,
+    input [4:0] ReadReg2,
+    input [4:0] WriteReg,
+    input [31:0] WriteData,
+    output [31:0] ReadData1,
+    output [31:0] ReadData2
+    );
+    
+    reg [31:0] file [1:31];
+    integer i;
+    
+    assign ReadData1 = (ReadReg1 == 0) ? 0 : file[ReadReg1];
+    assign ReadData2 = (ReadReg2 == 0) ? 0 : file[ReadReg2];
+    
+    always @(negedge clk or negedge Reset) begin
+        if(Reset == 0) begin
+            for(i = 1; i <= 31; i=i+1) begin
+                file[i] <= 0;
+            end
+        end
+        else if(WE == 1 && WriteReg != 0)
+            file[WriteReg] <= WriteData;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/clk_div.v

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 14:08:04
+// Design Name: 
+// Module Name: clk_div
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clk_div(
+    input clk,
+    output reg clk_sys = 0
+    );
+    
+    reg [25:0] div_counter = 0;
+    always @(posedge clk) begin
+        if(div_counter >= 50000) begin
+            clk_sys <= ~clk_sys;
+            div_counter <= 0;
+        end
+        else div_counter <= div_counter + 1;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/SingleCycleCPU.srcs/sources_1/new/top_CPU.v

@@ -0,0 +1,115 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/14 21:32:32
+// Design Name: 
+// Module Name: top_CPU
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_CPU(
+    input clk,
+    input Reset,
+    output [31:0] currentIAddr, nextIAddr,
+    output [4:0] rs, rt,
+    output [31:0] ReadData1, ReadData2,
+    output [31:0] ALU_result, DataBus
+    );
+    
+    wire [5:0] opcode;
+    wire [4:0] rd;
+    wire [15:0] immediate;
+    
+    wire [31:0] bincode;
+    wire [31:0] extended;
+    wire PCWre, RegWre, RegDst, DBDataSrc, ALUSrcA, ALUSrcB, mRD, mWR, ExtSel;
+    wire [1:0] PCSrc;
+    wire [2:0] ALUOp;
+    wire ALU_zero, ALU_sign;
+    wire [5:0] WriteReg;
+    wire [31:0] WriteData;
+    wire [31:0] ALU_inA, ALU_inB;
+    wire [31:0] DataOut;
+    
+    wire [31:0] next_in0, next_in1, next_in2;
+    assign opcode = bincode[31:26];
+    assign rs = bincode[25:21];
+    assign rt = bincode[20:16];
+    assign rd = bincode[15:11];
+    assign immediate = bincode[15:0];
+    
+    assign next_in0 = currentIAddr + 4;
+    assign next_in1 = next_in0 + (extended<<2);
+    assign next_in2 = {currentIAddr[31:28], bincode[25:0], 2'b00};
+    
+    assign DataBus = WriteData;
+    /* ���Ƶ�Ԫ */
+    ControlUnit ControlUnit(
+        .opcode(opcode), .zero(ALU_zero), .sign(ALU_sign),
+        .PCWre(PCWre), .ALUSrcA(ALUSrcA), .ALUSrcB(ALUSrcB), .DBDataSrc(DBDataSrc), .RegWre(RegWre), /*.InsMemRW(InsMemRW),*/ .mRD(mRD), .mWR(mWR), .RegDst(RegDst), .ExtSel(ExtSel),
+        .PCSrc(PCSrc), .ALUOp(ALUOp)
+    );
+    
+    /* 5���ؼ��ײ�ģ�� */
+    PC PC(
+        .clk(clk), .Reset(Reset), .PCWre(PCWre), .nextIAddr(nextIAddr),
+        .currentIAddr(currentIAddr)
+    );
+    InstructionMemory InstructionMemory(
+        .IAddr(currentIAddr),
+        .IDataOut(bincode)
+    );
+    RegisterFile RegisterFile(
+        .clk(clk), .Reset(Reset), .WE(RegWre),
+        .ReadReg1(rs), .ReadReg2(rt), .WriteReg(WriteReg), .WriteData(WriteData),
+        .ReadData1(ReadData1), .ReadData2(ReadData2)
+    );
+    ALU ALU(
+        .ALUOp(ALUOp), .A(ALU_inA), .B(ALU_inB),
+        .result(ALU_result), .zero(ALU_zero), .sign(ALU_sign)
+    );
+    DataMemory DataMemory(
+        .clk(clk), .DAddr(ALU_result), .DataIn(ReadData2), .RD(mRD), .WR(mWR),
+        .DataOut(DataOut)
+    );
+    
+    /* ��������չ */
+    ImmediateExtend ImmediateExtend(
+        .original(immediate), .ExtSel(ExtSel),
+        .extended(extended)
+    );
+    /* ����ѡ���� */
+    Mux4_32bits Mux_nextIAddr(
+        .choice(PCSrc), .in0(next_in0), .in1(next_in1), .in2(next_in2), .in3(currentIAddr),
+        .out(nextIAddr)
+    );
+    Mux2_5bits Mux_WriteReg(
+        .choice(RegDst), .in0(rt), .in1(rd),
+        .out(WriteReg)
+    );
+    Mux2_32bits Mux_WriteData(
+        .choice(DBDataSrc), .in0(ALU_result), .in1(DataOut),
+        .out(WriteData)
+    );
+    Mux2_32bits Mux_ALU_inA(
+        .choice(ALUSrcA), .in0(ReadData1), .in1({27'd0, immediate[10:6]}),
+        .out(ALU_inA)
+    );
+    Mux2_32bits Mux_ALU_inB(
+        .choice(ALUSrcB), .in0(ReadData2), .in1(extended),
+        .out(ALU_inB)
+    );
+endmodule

Jed-Z_computer-organization-lab/SingleCycleCPU/test_instructions.txt

@@ -0,0 +1,21 @@
+00001000 00000001 00000000 00001000
+01001000 00000010 00000000 00000010
+00000000 01000001 00011000 00000000
+00000100 01100010 00101000 00000000
+01000100 10100010 00100000 00000000
+01001100 10000010 01000000 00000000
+01100000 00001000 01000000 01000000
+11000101 00000001 11111111 11111110
+01110000 01000110 00000000 00000100
+01110000 11000111 00000000 00000000
+00001000 11100111 00000000 00001000
+11000000 11100001 11111111 11111110
+10011000 00100010 00000000 00000100
+10011100 00101001 00000000 00000100
+00001000 00001010 11111111 11111110
+00001001 01001010 00000000 00000001
+11001001 01000000 11111111 11111110
+01000000 01001011 00000000 00000010
+11100000 00000000 00000000 00010100
+01001100 10000010 01000000 00000000
+11111100 00000000 00000000 00000000

Jed-Z_computer-organization-lab/hex_to_7seg/hex_to_7seg.srcs/sim_1/new/sim1.v

@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 17:40:44
+// Design Name: 
+// Module Name: sim1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module sim1;
+    reg clock;
+    reg reset;
+    wire [1:0] count;
+    Counter4 uut(
+        .clk(clock),
+        .reset(reset),
+        .count(count)
+    );
+    
+    always #5 clock = ~clock;
+    
+    initial begin
+        clock = 0;
+        reset = 0;
+        #100;
+        reset = 1;
+        
+        
+        #100;
+        $stop;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/hex_to_7seg/hex_to_7seg.srcs/sources_1/new/Counter4.v

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 14:03:28
+// Design Name: 
+// Module Name: Counter4
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Counter4(
+    input clk,
+    input reset,
+    output reg [1:0] count
+    );
+    
+    always @(posedge clk or posedge reset) begin
+        if(reset == 1) count <= 0;
+        else begin
+            if(count == 2'b11) count <= 0;
+            else count <= count + 1;
+        end
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/hex_to_7seg/hex_to_7seg.srcs/sources_1/new/Hex_To_7Seg.v

@@ -0,0 +1,52 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 13:52:22
+// Design Name: 
+// Module Name: Hex_To_7Seg
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Hex_To_7Seg(
+    input [3:0] hex,
+    output reg [7:0] dispcode
+    );
+    
+    always @(hex) begin
+        //  '0'- ���ƣ�'1'- Ϩ��
+        // [7:0] �����ң�DP,g,f,e,d,c,b,a
+        case(hex)
+            4'h0: dispcode <= 8'b1100_0000; //0
+            4'h1: dispcode <= 8'b1111_1001; //1
+            4'h2: dispcode <= 8'b1010_0100; //2
+            4'h3: dispcode <= 8'b1011_0000; //3
+            4'h4: dispcode <= 8'b1001_1001; //4
+            4'h5: dispcode <= 8'b1001_0010; //5
+            4'h6: dispcode <= 8'b1000_0010; //6
+            4'h7: dispcode <= 8'b1101_1000; //7
+            4'h8: dispcode <= 8'b1000_0000; //8
+            4'h9: dispcode <= 8'b1001_0000; //9
+            4'hA: dispcode <= 8'b1000_1000; //A
+            4'hB: dispcode <= 8'b1000_0011; //b
+            4'hC: dispcode <= 8'b1100_0110; //C
+            4'hD: dispcode <= 8'b1010_0001; //d
+            4'hE: dispcode <= 8'b1000_0110; //E
+            4'hF: dispcode <= 8'b1000_1110; //F
+            default: dispcode <= 8'b0000_0000; // ����
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/hex_to_7seg/hex_to_7seg.srcs/sources_1/new/Mux4_8bits.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 14:00:50
+// Design Name: 
+// Module Name: Mux4_8bits
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mux4_4bits(
+    input [1:0] choice,
+    input [3:0] in0, in1, in2, in3,
+    output reg [3:0] out
+    );
+    
+    always @(*) begin
+        case(choice)
+            0: out <= in0;
+            1: out <= in1;
+            2: out <= in2;
+            3: out <= in3;
+        endcase
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/hex_to_7seg/hex_to_7seg.srcs/sources_1/new/clk_div.v

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 14:08:04
+// Design Name: 
+// Module Name: clk_div
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clk_div(
+    input clk,
+    output reg clk_sys = 0
+    );
+    
+    reg [25:0] div_counter = 0;
+    always @(posedge clk) begin
+        if(div_counter >= 50000) begin
+            clk_sys <= ~clk_sys;
+            div_counter <= 0;
+        end
+        else div_counter <= div_counter + 1;
+    end
+    
+endmodule

Jed-Z_computer-organization-lab/hex_to_7seg/hex_to_7seg.srcs/sources_1/new/top_LEDs.v

@@ -0,0 +1,68 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/11/15 17:29:57
+// Design Name: 
+// Module Name: top_LEDs
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module top_LEDs(
+    input clock,
+    input reset,
+    input [3:0] hex0,
+    input [3:0] hex1,
+    input [3:0] hex2,
+    input [3:0] hex3,
+    output reg [3:0] enable,
+    output [7:0] dispcode, // �߶�����ܵ�����
+    output light
+    );
+    
+    wire clk_sys;
+    wire [1:0] count;
+    wire [3:0] hex_num;
+    
+    assign light = clk_sys;
+    
+    clk_div clk_div(
+        .clk(clock),
+        .clk_sys(clk_sys)
+    );
+    Counter4 Counter4(
+        .clk(clk_sys), .reset(reset),
+        .count(count)
+    );
+    Hex_To_7Seg Hex_To_7Seg(
+        .hex(hex_num),
+        .dispcode(dispcode)
+    );
+    Mux4_4bits Mux4_4bits(
+        .choice(count),
+        .in0(hex0), .in1(hex1), .in2(hex2), .in3(hex3),
+        .out(hex_num)
+    );
+    
+    always @(count) begin
+        case(count)
+            2'b00: enable = 4'b1110;
+            2'b01: enable = 4'b1101;
+            2'b10: enable = 4'b1011;
+            2'b11: enable = 4'b0111;
+        endcase
+    end
+    
+endmodule