Add Repo: MIPSfpga_mipsfpga-plus

MIPSfpga_mipsfpga-plus/.vscode/launch.json

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+{
+    "version": "0.2.0",
+    "configurations": [
+        
+        {
+            "name": "MIPS Load",
+            "type": "cppdbg",
+            "request": "launch",
+            "program": "${fileDirname}/program.elf",
+            "cwd": "${fileDirname}",
+            "MIMode" : "gdb",
+            "windows": {
+                "miDebuggerPath": "mips-mti-elf-gdb.exe"
+            },
+            "linux": {
+                "miDebuggerPath": "mips-mti-elf-gdb"
+            },
+            "setupCommands": [
+                {"text": "cd ${fileDirname}"},
+                {"text": "file program.elf"},
+                {"text": "target remote | openocd -f ../../scripts/load/openocd.cfg -p -c 'log_output openocd.log'"},
+                {"text": "set endian little"},
+                {"text": "monitor reset halt"}, 
+                {"text": "load"},
+                {"text": "compare-sections"},
+                {"text": "break main"},
+                {"text": "monitor continue"}
+            ],
+            "launchCompleteCommand": "None",
+            "targetArchitecture": "mips"
+
+            //Uncomment this to debug
+            //,"logging": { "engineLogging": true }
+            //or this for verbose debug
+            //,"logging": { "engineLogging": true, "trace": true, "traceResponse": true }
+        },
+        {
+            "name": "MIPS Attach",
+            "type": "cppdbg",
+            "request": "launch",
+            "program": "${fileDirname}/program.elf",
+            "cwd": "${fileDirname}",
+            "windows": {
+                "miDebuggerPath": "mips-mti-elf-gdb.exe"
+            },
+            "linux": {
+                "miDebuggerPath": "mips-mti-elf-gdb"
+            },
+            "setupCommands": [
+                {"text": "cd ${fileDirname}"},
+                {"text": "file program.elf"},
+                {"text": "target remote | openocd -f ../../scripts/load/openocd.cfg -p -c 'log_output openocd.log'"},
+                {"text": "set endian little"}
+            ],
+            "customLaunchSetupCommands": [],
+            "launchCompleteCommand": "None",
+            "targetArchitecture": "mips"
+
+            //Uncomment this to debug
+            //,"logging": { "engineLogging": true }
+            //or this for verbose debug
+            //,"logging": { "engineLogging": true, "trace": true, "traceResponse": true }
+        }
+    ]
+}

MIPSfpga_mipsfpga-plus/README.md

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+MIPSfpga+ / mipsfpga-plus / MFP is a cleaned-up and improved variant of MIPSfpga-based system defined in MIPSfpga Getting Started package (MFGS). The new features include:
+
+<ol>
+<li>The ability to load a software program using ubiquitous $5 FTDI-based USB-to-UART connector instead of $50 Bus Blaster that is difficult to get in some places of the globe</li>
+<li>The ability to change the clock frequency on the fly from 50 or 25 MHz down to 1 Hz (one cycle a second) to observe the work of CPU in real time, including cache misses and pipeline forwarding</li>
+<li>An example of integration of a light sensor with SPI protocol</li>
+<li>Smaller software initialization sequence that fits in 1 KB instead of 32 KB memory, which allows porting MIPSfpga to a wider selection of FPGA boards, without using external memory</li>
+<li>Miscellaneous fixes like improving AHB-Lite slave to handle narrow uncached writes of sizes 1 or 2-bytes</li>
+<li>Easy to use configurable SDRAM interface module</li>
+<li>Altera MAX10 ADC interface module support</li>
+<li>Widely used UART16550 interface module</li>
+<li>External interrupt controller that is working throw MIPS microAptiv core Interrupt Interface</li>
+</ol>
+
+The hierarchy of synthesizable modules for Digilent Nexys 4 DDR with Xilinx Artix-7 FPGA:
+
+<a href="https://cdn.rawgit.com/zhelnio/mipsfpga-plus/a36be531/documentation/edited_figures/hierarchy_nexys4_ddr_full.html"><img src="https://raw.githubusercontent.com/zhelnio/mipsfpga-plus/master/documentation/edited_figures/hierarchy_nexys4_ddr_full.png"></a>
+
+MIPSfpga+ currently works on these FPGA boards:
+
+<ol>
+<li><a href="http://store.digilentinc.com/nexys-4-ddr-artix-7-fpga-trainer-board-recommended-for-ece-curriculum/">Digilent Nexys 4 DDR</a> board with Xilinx Artix-7 FPGA. See the Appendix A about how the board is connected with the applicable peripherals.</li>
+<li><a href="http://store.digilentinc.com/nexys-4-artix-7-fpga-trainer-board-limited-time-see-nexys4-ddr/">Digilent Nexys 4</a> board with Xilinx Artix-7 FPGA (no DDR, soon to be discontinued).</li>
+<li><a href="http://store.digilentinc.com/basys-3-artix-7-fpga-trainer-board-recommended-for-introductory-users/">Digilent Basys 3</a> with Xilinx Artix-7.</li>
+<li><a href="http://de0-cv.terasic.com.tw">Terasic DE0-CV</a> with Altera Cyclone V. See the Appendix B about how the board is connected with the applicable peripherals.</li>
+<li><a href="http://de2-115.terasic.com">Terasic DE2-115</a> with Altera Cyclone IV</li>
+<li><a href="http://de0-nano.terasic.com.tw">Terasic DE0-Nano</a> board with Altera Cyclone IV FPGA.</li>
+<li><a href="http://de0.terasic.com">Terasic DE0</a> with Altera Cyclone III</li>
+<li><a href="http://de1.terasic.com">Terasic DE1</a> with Altera Cyclone II</li>
+<li><a href="http://de10-lite.terasic.com">Terasic DE10-Lite</a> with Altera MAX10</li>
+<li><a href="http://de10-nano.terasic.com">Terasic DE10-Nano</a> with Altera Cyclone V</li>
+</ol>
+
+There are three planned ports:
+
+<ol>
+<li><a href="http://marsohod.org/plata-marsokhod3">Marsohod 3</a> board with Altera MAX10 FPGA</li>
+<li><a href="http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/">Digilent Arty</a> with Xilinx Artix-7. MIPSfpga+ is likely to work on this board with no modification except adding the board wrapper (top-level Verilog and pin constraints).</li>
+<li><a href="http://de2.terasic.com">Terasic DE2</a> with Altera Cyclone II</li>
+</ol>
+
+The source code for MIPSfpga+ is located at <a href="http://github.com/MIPSfpga/mipsfpga-plus">http://github.com/MIPSfpga/mipsfpga-plus</a>; this code does not include any source code of MIPS microAptiv UP CPU core from MIPSfpga Getting Started package. A user of MIPSfpga+ is supposed to download Getting Started package from Imagination Technologies web site: <a href="https://community.imgtec.com/downloads/mipsfpga-getting-started-guide-2-0/">MIPSfpga Getting Started Guide 2.0</a> or <a href="http://community.imgtec.com/downloads/mipsfpga-getting-started-v1-3">MIPSfpga Getting Started Guide 1.3</a>.
+
+After downloading both MIPSfpga from Imagination site and MIPSfpga+ from GitHub, the user is expected to install MIPSfpga under 64-bit Microsoft Windows (either Windows 7 or Windows 8) by placing MIPSfpga core source files to MIPSfpga+\core directory. To do this one need to copy to MIPSfpga+\core all the files from 'MIPSfpga_GSG_1.3\MIPSfpga\rtl_up' when using MIPSfpga 1.3 or from 'MIPSfpga_GSG_v2.0\MIPSfpga_GSG\rtl_up\core' in the case of using MIPSfpga 2.0. The paths inside MIPSfpga+ synthesis and simulation scripts rely on such installation.
+
+MIPSfpga+ (as well as the original MFGS package) can be also used on a workstation with 32-bit Windows, 32-bit Linux, 64-bit Linux, with or without Windows or Linux virtual machine. It is possible to install MIPSfpga+ in different directories, and use it with a number of Verilog simulators and synthesis tools: Synopsys VCS, Cadence IES, Mentor ModelSim, Icarus Verilog with GTKWave, Xilinx ISim and Vivado, Altera Quartus II, Synopsys Synplify Pro and others. Some usage scenarios require modifying the scripts and adhering to specific versions of EDA and software development tools, for example:
+
+<ul>
+<li>In order to use MIPSfpga or MIPSfpga+ on a workstation with 32-bit Windows, it is necessary to use <a href="https://sourcery.mentor.com/GNUToolchain/subscription3537?lite=MIPS">Mentor Sourcery CodeBench Lite Edition for MIPS ELF</a> instead of <a href="https://community.imgtec.com/developers/mips/tools/codescape-mips-sdk/download-codescape-mips-sdk-essentials/">Imagination Codescape MIPS SDK Essentials</a>. This requires some minimal modifications of certain scripts (changing the program name prefixes).</li>
+<li>In order to use MIPSfpga or MIPSfpga+ with Altera FPGAs on a workstation with 32-bit Windows <i>or</i> 32-Linux, it is necessary to use <a href="http://dl.altera.com/13.1/?edition=web">Altera Quartus II Web Edition version 13.1</a> instead of the latest <a href="http://dl.altera.com/15.1/?edition=lite">version 15.1</a> that does not work on workstations with 32-bit operating systems.</li>
+</ul> 
+
+How to synthesize mipsfpga-plus for Terasic DE0-CV board:
+
+<ol>
+<li>Unzip MIPSfpga 2.0 Getting Started Guide to C:\MIPSfpga</li>
+<li>Get mipsfpgfa-plus into C:\github\mipsfpga-plus</li>
+<li>copy all the files from C:\MIPSfpga\MIPSfpga_GSG\rtl_up\core to C:\github\mipsfpga-plus\core</li>
+<li>cd C:\github\mipsfpga-plus\boards\de0_cv</li>
+<li>make_project.bat</li>
+<li>Run Altera Quartus II</li>
+<li>Open project C:\github\mipsfpga-plus\boards\de0_cv\project\de0_cv.qpf</li>
+<li>Analyze/Synthesize/Place&Route/Assemble</li>
+<li>Open Device / Hardware Setup / ByteBlaster / Set file / ouput_files / de0_cv.sof / Start</li>
+</ol>
+
+How to load a software example into mipsfpga-plus using BusBlaster and OpenOCD:
+
+<pre>
+cd C:\github\mipsfpga-plus\programs\00_counter
+02_compile_and_link.bat
+11_upload_to_the_board.bat
+</pre>
+
+How to load a software example into mipsfpga-plus using USB-to-UART-based serial loader:
+
+<pre>
+cd C:\github\mipsfpga-plus\programs\00_counter
+02_compile_and_link.bat
+08_generate_motorola_s_record_file.bat
+09_check_which_com_port_is_used.bat
+</pre>
+
+Modify <i>10_upload_to_the_board_using_uart.bat</i>.
+
+<pre>
+10_upload_to_the_board_using_uart.bat
+</pre>
+
+Some details about scripts using: <a href="programs/README.md">programs/README.md</a>
+
+

MIPSfpga_mipsfpga-plus/boards/basys3/basys3.v

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+`include "mfp_ahb_lite_matrix_config.vh"
+
+module basys3
+(
+    input         clk,
+
+    input         btnC,
+    input         btnU,
+    input         btnL,
+    input         btnR,
+    input         btnD,
+
+    input  [15:0] sw,
+
+    output [15:0] led,
+
+    output [ 6:0] seg,
+    output        dp,
+    output [ 3:0] an,
+
+    inout  [ 7:0] JA,
+    inout  [ 7:0] JB,
+
+    input         RsRx
+);
+
+    wire clock;
+    wire reset = btnU;
+
+    `define MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( clk      ),
+        .sw_in  ( sw [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( clk       ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    BUFG BUFG_slow_clk (.O ( clock ), .I ( muxed_clk ));
+
+    `else
+
+    clk_wiz_0 clk_wiz_0 (.clk_in1 (clk), .clk_out1 (clock));
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 16 { 1'b0 } } , sw  [15:0] };
+
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  5 { 1'b0 } } ,
+                           btnU, btnD, btnL, btnC, btnR };
+
+    assign led = IO_GreenLEDs [15:0];
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    wire ejtag_tck_in, ejtag_tck;
+
+    IBUF IBUF           (.O ( ejtag_tck_in ), .I ( JB [3]       ));
+    BUFG BUFG_ejtag_tck (.O ( ejtag_tck    ), .I ( ejtag_tck_in ));
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         ( clock           ),
+        .SI_Reset         ( reset           ),
+                          
+        .HADDR            ( HADDR           ),
+        .HRDATA           ( HRDATA          ),
+        .HWDATA           ( HWDATA          ),
+        .HWRITE           ( HWRITE          ),
+
+        .EJ_TRST_N_probe  (   JB [4]        ),
+        .EJ_TDI           (   JB [1]        ),
+        .EJ_TDO           (   JB [2]        ),
+        .EJ_TMS           (   JB [0]        ),
+        .EJ_TCK           (   ejtag_tck_in  ),
+        .SI_ColdReset     ( ~ JB [5]        ),
+        .EJ_DINT          (   1'b0          ),
+
+        .IO_Switches      ( IO_Switches      ),
+        .IO_Buttons       ( IO_Buttons       ),
+        .IO_RedLEDs       ( IO_RedLEDs       ),
+        .IO_GreenLEDs     ( IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  ( IO_7_SegmentHEX  ),
+
+        .UART_RX          ( RsRx /* Alternative: JA [7] */ ),
+        .UART_TX          ( /* TODO */       ),
+
+        .SPI_CS           (   JA [0]         ),
+        .SPI_SCK          (   JA [3]         ),
+        .SPI_SDO          (   JA [2]         )
+    );
+
+    assign JA [4] = 1'b0;
+
+    wire display_clock;
+
+    mfp_clock_divider_100_MHz_to_763_Hz mfp_clock_divider_100_MHz_to_763_Hz
+        (clk, display_clock);
+
+    wire [7:0] anodes;
+    assign an = anodes [3:0];
+
+    mfp_multi_digit_display multi_digit_display
+    (
+        .clock          (   display_clock   ),
+        .resetn         ( ~ reset           ),
+        .number         (   IO_7_SegmentHEX ),
+
+        .seven_segments (   seg             ),
+        .dot            (   dp              ),
+        .anodes         (   anodes          )
+    );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/basys3/system_create.tcl

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+
+# path where project will be created
+set project_path [pwd]
+set script_path [file dirname [file normalize [info script]]]
+
+# global settings
+set project_name    "system"
+set project_part    "xc7a35tcpg236-1"
+set testbench_top   "mfp_testbench"
+
+# source files path
+set rtl_path $project_path/../rtl
+set tb_path  $project_path/../tb
+
+# project local settings
+set source_files [list \
+    "[file normalize "../basys3.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_gpio_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_adc_max10.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_eic.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix_config.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix_with_loader.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_pmod_als.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_uart16550.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_busy.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_sdram.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_clock_dividers.v"]" \
+    "[file normalize "../../../system_rtl/mfp_dual_port_ram.v"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_core.v"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_core.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_handler.v"]" \
+    "[file normalize "../../../system_rtl/mfp_pmod_als_spi_receiver.v"]" \
+    "[file normalize "../../../system_rtl/mfp_priority_encoder.v"]" \
+    "[file normalize "../../../system_rtl/mfp_register.v"]" \
+    "[file normalize "../../../system_rtl/mfp_seven_segment_displays.v"]" \
+    "[file normalize "../../../system_rtl/mfp_srec_parser_to_ahb_lite_bridge.v"]" \
+    "[file normalize "../../../system_rtl/mfp_srec_parser.v"]" \
+    "[file normalize "../../../system_rtl/mfp_switch_and_button_debouncers.v"]" \
+    "[file normalize "../../../system_rtl/mfp_system.v"]" \
+    "[file normalize "../../../system_rtl/mfp_uart_loader.v"]" \
+    "[file normalize "../../../system_rtl/mfp_uart_receiver.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/raminfr.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_defines.vh"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_receiver.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_regs.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_rfifo.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_sync_flops.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_tfifo.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_transmitter.v"]" \
+    "[file normalize "../../../core/dataram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/d_wsram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/i_wsram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/m14k_alu_dsp_stub.v"]" \
+    "[file normalize "../../../core/m14k_alu_shft_32bit.v"]" \
+    "[file normalize "../../../core/m14k_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_biu.v"]" \
+    "[file normalize "../../../core/m14k_cache_cmp.v"]" \
+    "[file normalize "../../../core/m14k_cache_mux.v"]" \
+    "[file normalize "../../../core/m14k_cdmm_ctl.v"]" \
+    "[file normalize "../../../core/m14k_cdmm_mpustub.v"]" \
+    "[file normalize "../../../core/m14k_cdmmstub.v"]" \
+    "[file normalize "../../../core/m14k_cdmm.v"]" \
+    "[file normalize "../../../core/m14k_clockandlatch.v"]" \
+    "[file normalize "../../../core/m14k_clock_buf.v"]" \
+    "[file normalize "../../../core/m14k_clock_nogate.v"]" \
+    "[file normalize "../../../core/m14k_clockxnorgate.v"]" \
+    "[file normalize "../../../core/m14k_config.vh"]" \
+    "[file normalize "../../../core/m14k_const.vh"]" \
+    "[file normalize "../../../core/m14k_cop1_stub.v"]" \
+    "[file normalize "../../../core/m14k_cop2_stub.v"]" \
+    "[file normalize "../../../core/m14k_core.v"]" \
+    "[file normalize "../../../core/m14k_cp1_stub.v"]" \
+    "[file normalize "../../../core/m14k_cp2_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpu.v"]" \
+    "[file normalize "../../../core/m14k_cpz_antitamper_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_eicoffset_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_guest_srs1.v"]" \
+    "[file normalize "../../../core/m14k_cpz_guest_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_pc_top.v"]" \
+    "[file normalize "../../../core/m14k_cpz_pc.v"]" \
+    "[file normalize "../../../core/m14k_cpz_prid.v"]" \
+    "[file normalize "../../../core/m14k_cpz_root_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_sps_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_srs1.v"]" \
+    "[file normalize "../../../core/m14k_cpz.v"]" \
+    "[file normalize "../../../core/m14k_cpz_watch_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_scanio_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_tpl.v"]" \
+    "[file normalize "../../../core/m14k_dc_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_dcc_fb.v"]" \
+    "[file normalize "../../../core/m14k_dcc_mb_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_parity_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_spmb_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_spstub.v"]" \
+    "[file normalize "../../../core/m14k_dcc.v"]" \
+    "[file normalize "../../../core/m14k_dc.v"]" \
+    "[file normalize "../../../core/m14k_dsp_const.vh"]" \
+    "[file normalize "../../../core/m14k_dspram_ext_stub.v"]" \
+    "[file normalize "../../../core/m14k_edp_add_simple.v"]" \
+    "[file normalize "../../../core/m14k_edp_buf_misc_pro.v"]" \
+    "[file normalize "../../../core/m14k_edp_buf_misc.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz_16b.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz_4b.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz.v"]" \
+    "[file normalize "../../../core/m14k_edp.v"]" \
+    "[file normalize "../../../core/m14k_ejt_and2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_area.v"]" \
+    "[file normalize "../../../core/m14k_ejt_async_rec.v"]" \
+    "[file normalize "../../../core/m14k_ejt_async_snd.v"]" \
+    "[file normalize "../../../core/m14k_ejt_brk21.v"]" \
+    "[file normalize "../../../core/m14k_ejt_bus32mux2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_dbrk.v"]" \
+    "[file normalize "../../../core/m14k_ejt_fifo_1r1w_stub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_gate.v"]" \
+    "[file normalize "../../../core/m14k_ejt_ibrk.v"]" \
+    "[file normalize "../../../core/m14k_ejt_mux2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_pdttcb_stub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_dasamstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_dasam.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_fdcstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_fdc.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_pcsamstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_pcsam.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tck.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tripsync.v"]" \
+    "[file normalize "../../../core/m14k_ejt.v"]" \
+    "[file normalize "../../../core/m14k_fpuclk1_nogate.v"]" \
+    "[file normalize "../../../core/m14k_gf_mux2.v"]" \
+    "[file normalize "../../../core/m14k_glue.v"]" \
+    "[file normalize "../../../core/m14k_ic_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_icc_mb_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_parity_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_spmb_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_spstub.v"]" \
+    "[file normalize "../../../core/m14k_icc_umips_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc.v"]" \
+    "[file normalize "../../../core/m14k_ic.v"]" \
+    "[file normalize "../../../core/m14k_ispram_ext_stub.v"]" \
+    "[file normalize "../../../core/m14k_mdl_add_simple.v"]" \
+    "[file normalize "../../../core/m14k_mdl_ctl.v"]" \
+    "[file normalize "../../../core/m14k_mdl_dp.v"]" \
+    "[file normalize "../../../core/m14k_mdl.v"]" \
+    "[file normalize "../../../core/m14k_mmuc.v"]" \
+    "[file normalize "../../../core/m14k_mmu.vh"]" \
+    "[file normalize "../../../core/m14k_mpc_ctl.v"]" \
+    "[file normalize "../../../core/m14k_mpc_dec.v"]" \
+    "[file normalize "../../../core/m14k_mpc_exc.v"]" \
+    "[file normalize "../../../core/m14k_mpc.v"]" \
+    "[file normalize "../../../core/m14k_rf_reg.v"]" \
+    "[file normalize "../../../core/m14k_rf_rngc.v"]" \
+    "[file normalize "../../../core/m14k_rf_stub.v"]" \
+    "[file normalize "../../../core/m14k_siu_int_sync.v"]" \
+    "[file normalize "../../../core/m14k_siu.v"]" \
+    "[file normalize "../../../core/m14k_spram_top.v"]" \
+    "[file normalize "../../../core/m14k_tlb_collector.v"]" \
+    "[file normalize "../../../core/m14k_tlb_cpy.v"]" \
+    "[file normalize "../../../core/m14k_tlb_ctl.v"]" \
+    "[file normalize "../../../core/m14k_tlb_dtlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb_itlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb16entries.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb16.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb1entry.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb4entries.v"]" \
+    "[file normalize "../../../core/m14k_tlb_utlbentry.v"]" \
+    "[file normalize "../../../core/m14k_tlb_utlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb.v"]" \
+    "[file normalize "../../../core/m14k_top.v"]" \
+    "[file normalize "../../../core/m14k_udi_custom.v"]" \
+    "[file normalize "../../../core/m14k_udi_scanio_stub.v"]" \
+    "[file normalize "../../../core/m14k_udi_stub.v"]" \
+    "[file normalize "../../../core/mvp_cregister_c.v"]" \
+    "[file normalize "../../../core/mvp_cregister_ngc.v"]" \
+    "[file normalize "../../../core/mvp_cregister_s.v"]" \
+    "[file normalize "../../../core/mvp_cregister.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide_tlb.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide_utlb.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide.v"]" \
+    "[file normalize "../../../core/mvp_latchn.v"]" \
+    "[file normalize "../../../core/mvp_mux16.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_10.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_13.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_24.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_3.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_4.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_5.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_6.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_8.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_9.v"]" \
+    "[file normalize "../../../core/mvp_mux2.v"]" \
+    "[file normalize "../../../core/mvp_mux4.v"]" \
+    "[file normalize "../../../core/mvp_mux8.v"]" \
+    "[file normalize "../../../core/mvp_register_c.v"]" \
+    "[file normalize "../../../core/mvp_register_ngc.v"]" \
+    "[file normalize "../../../core/mvp_register_s.v"]" \
+    "[file normalize "../../../core/mvp_register.v"]" \
+    "[file normalize "../../../core/mvp_ucregister_wide.v"]" \
+    "[file normalize "../../../core/RAMB4K_S16.v"]" \
+    "[file normalize "../../../core/RAMB4K_S2.v"]" \
+    "[file normalize "../../../core/RAMB4K_S8.v"]" \
+    "[file normalize "../../../core/ram_dual_port.v"]" \
+    "[file normalize "../../../core/ram_reset_dual_port.v"]" \
+    "[file normalize "../../../core/tagram_2k2way_xilinx.v"]" \
+]
+
+set constr_files [list \
+    "[file normalize "../basys3.xdc"]" \
+]
+
+set sim_files [list \
+    "[file normalize "../../../testbench/sdr_sdram"]" \
+    "[file normalize "../../../testbench/sdr_sdram/sdr.v"]" \
+    "[file normalize "../../../testbench/sdr_sdram/sdr_parameters.vh"]" \
+    "[file normalize "../../../testbench/mfp_testbench.v"]" \
+    "[file normalize "../../../testbench/mfp_uart_testbench.v"]" \
+]
+
+# create project
+create_project $project_name $project_path -part $project_part -force
+
+# fill 'sources_1' fileset
+if {[info exists source_files]} {
+    add_files -norecurse -fileset [get_filesets sources_1] $source_files
+}
+
+# fill 'constrs_1' fileset
+if {[info exists constr_files]} {
+    add_files -norecurse -fileset [get_filesets constrs_1] $constr_files
+}
+
+# fill 'sim_1' fileset
+if {[info exists sim_files]} {
+    set obj [get_filesets sim_1]
+    add_files -norecurse -fileset $obj $sim_files
+    set_property top $testbench_top $obj
+}
+
+# define macros VIVADO_SYNTHESIS
+set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define VIVADO_SYNTHESIS} -objects [get_runs synth_1]
+
+puts "INFO: Project created:$project_name"

MIPSfpga_mipsfpga-plus/boards/basys3/system_load.tcl

@@ -0,0 +1,21 @@
+
+set project_name    "system"
+set hw_device       "xc7a35t_0"
+
+open_project "$project_name.xpr"; # open Vivado project
+open_hw;                          # open the Hardware Manager
+connect_hw_server;                # open a connection to a hardware server
+open_hw_target;                   # connect to the board
+
+# set a file to be programmed
+set_property PROGRAM.FILE "$project_name.bit" [get_hw_devices $hw_device];
+
+# chip programming
+program_hw_devices [get_hw_devices $hw_device]
+#refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $hw_device] 0]
+
+# connections and project closing
+close_hw_target
+disconnect_hw_server
+close_hw
+close_project

MIPSfpga_mipsfpga-plus/boards/basys3/system_synth.tcl

@@ -0,0 +1,19 @@
+
+set project_name  "system"
+set synth_task    "synth_1"
+set impl_task     "impl_1"
+set timing_report "timing_1"
+
+open_project "$project_name.xpr"
+
+# run synthesis
+launch_runs $synth_task
+wait_on_run -verbose $synth_task
+
+# run implementation
+launch_runs $impl_task
+wait_on_run -verbose $impl_task
+
+# write bitstream
+open_run $impl_task -name $impl_task
+write_bitstream "$project_name.bit"

MIPSfpga_mipsfpga-plus/boards/de0/de0.sdc

@@ -0,0 +1,81 @@
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -period 20 [get_ports CLOCK_50_2]
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 40 [get_nets mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz|clko]
+create_clock -period 20 [get_nets de0|clk]
+create_clock -period 20 [get_ports GPIO1_D[14]]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+##**************************************************************
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+

MIPSfpga_mipsfpga-plus/boards/de0/de0.v

@@ -0,0 +1,177 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de0
+(
+    input         CLOCK_50,
+    input         CLOCK_50_2,
+    input  [ 2:0] BUTTON,
+    input  [ 9:0] SW,
+    output [ 6:0] HEX0_D,
+    output        HEX0_DP,
+    output [ 6:0] HEX1_D,
+    output        HEX1_DP,
+    output [ 6:0] HEX2_D,
+    output        HEX2_DP,
+    output [ 6:0] HEX3_D,
+    output        HEX3_DP,
+    output [ 9:0] LEDG,
+
+`ifdef UNUSED
+
+    output        UART_TXD,
+    input         UART_RXD,
+    output        UART_CTS,
+    input         UART_RTS,
+    inout  [15:0] DRAM_DQ,
+    output [12:0] DRAM_ADDR,
+    output        DRAM_LDQM,
+    output        DRAM_UDQM,
+    output        DRAM_WE_N,
+    output        DRAM_CAS_N,
+    output        DRAM_RAS_N,
+    output        DRAM_CS_N,
+    output        DRAM_BA_0,
+    output        DRAM_BA_1,
+    output        DRAM_CLK,
+    output        DRAM_CKE,
+    inout  [14:0] FL_DQ,
+    inout         FL_DQ15_AM1,
+    output [21:0] FL_ADDR,
+    output        FL_WE_N,
+    output        FL_RST_N,
+    output        FL_OE_N,
+    output        FL_CE_N,
+    output        FL_WP_N,
+    output        FL_BYTE_N,
+    input         FL_RY,
+    inout  [ 7:0] LCD_DATA,
+    output        LCD_BLON,
+    output        LCD_RW,
+    output        LCD_EN,
+    output        LCD_RS,
+    inout         SD_DAT0,
+    inout         SD_DAT3,
+    inout         SD_CMD,
+    output        SD_CLK,
+    input         SD_WP_N,
+    inout         PS2_KBDAT,
+    inout         PS2_KBCLK,
+    inout         PS2_MSDAT,
+    inout         PS2_MSCLK,
+    output        VGA_HS,
+    output        VGA_VS,
+    output [ 3:0] VGA_R,
+    output [ 3:0] VGA_G,
+    output [ 3:0] VGA_B,
+
+`endif
+
+    input  [ 1:0] GPIO0_CLKIN,
+    output [ 1:0] GPIO0_CLKOUT,
+    inout  [31:0] GPIO0_D,
+    input  [ 1:0] GPIO1_CLKIN,
+    output [ 1:0] GPIO1_CLKOUT,
+    inout  [31:0] GPIO1_D
+);
+
+    wire clk;
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( CLOCK_50 ),
+        .sw_in  ( SW [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( CLOCK_50  ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    global gclk
+    (
+        .in     ( muxed_clk  ), 
+        .out    ( clk        )
+    );
+
+    `else
+
+    assign clk = CLOCK_50;
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 10 { 1'b0 } } ,   SW     [9:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  3 { 1'b0 } } , ~ BUTTON [2:0] };
+
+    assign LEDG = IO_GreenLEDs [9:0];
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk            ),
+        .SI_Reset         ( ~ BUTTON [0]     ),
+                          
+        .HADDR            ( HADDR            ),
+        .HRDATA           ( HRDATA           ),
+        .HWDATA           ( HWDATA           ),
+        .HWRITE           ( HWRITE           ),
+
+        .EJ_TRST_N_probe  (   GPIO1_D [18]   ),
+        .EJ_TDI           (   GPIO1_D [17]   ),
+        .EJ_TDO           (   GPIO1_D [15]   ),
+        .EJ_TMS           (   GPIO1_D [19]   ),
+        .EJ_TCK           (   GPIO1_D [14]   ),
+        .SI_ColdReset     ( ~ GPIO1_D [16]   ),
+        .EJ_DINT          (   1'b0           ),
+
+        .IO_Switches      ( IO_Switches      ),
+        .IO_Buttons       ( IO_Buttons       ),
+        .IO_RedLEDs       ( IO_RedLEDs       ),
+        .IO_GreenLEDs     ( IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  ( IO_7_SegmentHEX  ),
+
+        .UART_RX          ( GPIO1_D [27]    ),
+        .UART_TX          ( /* TODO */      ),
+
+        .SPI_CS           ( GPIO1_D [30]    ),
+        .SPI_SCK          ( GPIO1_D [24]    ),
+        .SPI_SDO          ( GPIO1_D [26]    )
+    );
+
+    assign GPIO1_D [13] = 1'b0;
+    assign GPIO1_D [12] = 1'b0;
+    assign GPIO1_D [11] = 1'b1;
+    assign GPIO1_D [10] = 1'b1;
+
+    assign GPIO1_D [22] = 1'b0;
+
+    assign HEX0_DP = 1'b1;
+    assign HEX1_DP = 1'b1;
+    assign HEX2_DP = 1'b1;
+    assign HEX3_DP = 1'b1;
+
+    mfp_single_digit_seven_segment_display digit_3 ( IO_7_SegmentHEX [15:12] , HEX3_D );
+    mfp_single_digit_seven_segment_display digit_2 ( IO_7_SegmentHEX [11: 8] , HEX2_D );
+    mfp_single_digit_seven_segment_display digit_1 ( IO_7_SegmentHEX [ 7: 4] , HEX1_D );
+    mfp_single_digit_seven_segment_display digit_0 ( IO_7_SegmentHEX [ 3: 0] , HEX0_D );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/de0_cv/board_config.vh

@@ -0,0 +1,24 @@
+//board specific settings
+
+//SDRAM parameters for 64MB (Terasic DE0-CV)
+`ifdef MFP_USE_SDRAM_MEMORY
+    `define SDRAM_ADDR_BITS         13
+    `define SDRAM_ROW_BITS          13
+    `define SDRAM_COL_BITS          10
+    `define SDRAM_DQ_BITS           16
+    `define SDRAM_BA_BITS           2
+    `define SDRAM_DM_BITS           2
+    `define MFP_RAM_ADDR_WIDTH      (`SDRAM_ROW_BITS + `SDRAM_COL_BITS + `SDRAM_BA_BITS)
+
+    //values for fclk=50 MHz
+    `define SDRAM_DELAY_nCKE        10000
+    `define SDRAM_DELAY_tREF        360
+    `define SDRAM_DELAY_tRP         0
+    `define SDRAM_DELAY_tRFC        2
+    `define SDRAM_DELAY_tMRD        0
+    `define SDRAM_DELAY_tRCD        0
+    `define SDRAM_DELAY_tCAS        0
+    `define SDRAM_DELAY_afterREAD   0
+    `define SDRAM_DELAY_afterWRITE  2
+    `define SDRAM_COUNT_initAutoRef 8
+`endif

MIPSfpga_mipsfpga-plus/boards/de0_cv/de0_cv.sdc

@@ -0,0 +1,83 @@
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 20 [get_ports CLOCK4_50]
+create_clock -period 40 [get_nets mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz|clko]
+create_clock -period 20 [get_nets de0_cv|clk]
+create_clock -period 20 [get_ports GPIO_1[17]]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+##**************************************************************
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+

MIPSfpga_mipsfpga-plus/boards/de0_cv/de0_cv.v

@@ -0,0 +1,230 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de0_cv
+(
+    input           CLOCK2_50,
+    input           CLOCK3_50,
+    inout           CLOCK4_50,
+    input           CLOCK_50,
+                   
+    input           RESET_N,
+
+    input   [ 3:0]  KEY,
+    input   [ 9:0]  SW,
+
+    output  [ 9:0]  LEDR,
+
+    output  [ 6:0]  HEX0,
+    output  [ 6:0]  HEX1,
+    output  [ 6:0]  HEX2,
+    output  [ 6:0]  HEX3,
+    output  [ 6:0]  HEX4,
+    output  [ 6:0]  HEX5,
+                   
+    output  [12:0]  DRAM_ADDR,
+    output  [ 1:0]  DRAM_BA,
+    output          DRAM_CAS_N,
+    output          DRAM_CKE,
+    output          DRAM_CLK,
+    output          DRAM_CS_N,
+    inout   [15:0]  DRAM_DQ,
+    output          DRAM_LDQM,
+    output          DRAM_RAS_N,
+    output          DRAM_UDQM,
+    output          DRAM_WE_N,
+                   
+    output  [ 3:0]  VGA_B,
+    output  [ 3:0]  VGA_G,
+    output          VGA_HS,
+    output  [ 3:0]  VGA_R,
+    output          VGA_VS,
+
+    inout           PS2_CLK,
+    inout           PS2_CLK2,
+    inout           PS2_DAT,
+    inout           PS2_DAT2,
+                   
+    output          SD_CLK,
+    inout           SD_CMD,
+    inout   [ 3:0]  SD_DATA,
+                   
+    inout   [35:0]  GPIO_0,
+    inout   [35:0]  GPIO_1
+);
+
+    wire clk;
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( CLOCK_50 ),
+        .sw_in  ( SW [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( CLOCK_50  ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    global gclk
+    (
+        .in     ( muxed_clk  ), 
+        .out    ( clk        )
+    );
+
+    `else
+
+    assign clk = CLOCK_50;
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 10 { 1'b0 } } ,   SW  [9:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  4 { 1'b0 } } , ~ KEY [3:0] };
+
+    assign LEDR = IO_GreenLEDs [9:0];
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    `define MFP_EJTAG_DEBUGGER
+    `ifdef MFP_EJTAG_DEBUGGER
+        // MIPSfpga EJTAG BusBluster 3 connector pinout
+        // EJTAG     DIRECTION    PIN       CONN      PIN    DIRECTION EJTAG 
+        // =====     ========= ========== ========= ======== ========= ======
+        //  VCC       output   GPIO_1[12]  15 | 16  GPIO_1[13]  output    VCC  
+        //  GND       output   GPIO_1[14]  17 | 18  GPIO_1[15]  output    GND  
+        //  NC        output   GPIO_1[16]  19 | 20  GPIO_1[17]  input    EJ_TCK
+        //  NC        output   GPIO_1[18]  21 | 22  GPIO_1[19]  output   EJ_TDO
+        //  EJ_RST    input    GPIO_1[20]  23 | 24  GPIO_1[21]  input    EJ_TDI
+        //  EJ_TRST   input    GPIO_1[22]  25 | 26  GPIO_1[23]  input    EJ_TMS
+
+        wire EJ_VCC  = 1'b1;
+        wire EJ_GND  = 1'b0;
+        wire EJ_NC   = 1'bz;
+        wire EJ_TCK  = GPIO_1[17];
+        wire EJ_RST  = GPIO_1[20];
+        wire EJ_TDI  = GPIO_1[21];
+        wire EJ_TRST = GPIO_1[22];
+        wire EJ_TMS  = GPIO_1[23];
+        wire EJ_DINT = 1'b0;
+        wire EJ_TDO;
+
+        assign GPIO_1[12] = EJ_VCC;
+        assign GPIO_1[13] = EJ_VCC;
+        assign GPIO_1[14] = EJ_GND;
+        assign GPIO_1[15] = EJ_GND;
+        assign GPIO_1[16] = EJ_NC;
+        assign GPIO_1[18] = EJ_NC;
+        assign GPIO_1[19] = EJ_TDO;
+    `endif
+
+    `ifdef MFP_DEMO_LIGHT_SENSOR
+        //  ALS   CONN    PIN          DIRECTION
+        // ===== ======  =====       =============
+        //  VCC  JP2 29  3.3V
+        //  GND  JP2 31  GPIO_1[26]   output
+        //  SCK  JP2 33  GPIO_1[28]   output
+        //  SDO  JP2 35  GPIO_1[30]   input
+        //  NC   JP2 37  GPIO_1[32]   not connected
+        //  CS   JP2 39  GPIO_1[34]   output
+
+        wire    ALS_GND = 1'b0;
+        wire    ALS_SCK;
+        wire    ALS_SDO;
+        wire    ALS_NC  = 1'bz;
+        wire    ALS_CS;
+
+        assign GPIO_1[26] = ALS_GND;
+        assign GPIO_1[28] = ALS_SCK;
+        assign ALS_SDO    = GPIO_1[30];
+        assign GPIO_1[32] = ALS_NC;
+        assign GPIO_1[34] = ALS_CS;
+    `endif
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk             ),
+        .SI_Reset         ( ~ RESET_N         ),
+                          
+        .HADDR            (   HADDR           ),
+        .HRDATA           (   HRDATA          ),
+        .HWDATA           (   HWDATA          ),
+        .HWRITE           (   HWRITE          ),
+
+        `ifdef MFP_USE_SDRAM_MEMORY
+        .SDRAM_CKE        (   DRAM_CKE        ),
+        .SDRAM_CSn        (   DRAM_CS_N       ),
+        .SDRAM_RASn       (   DRAM_RAS_N      ),
+        .SDRAM_CASn       (   DRAM_CAS_N      ),
+        .SDRAM_WEn        (   DRAM_WE_N       ),
+        .SDRAM_ADDR       (   DRAM_ADDR       ),
+        .SDRAM_BA         (   DRAM_BA         ),
+        .SDRAM_DQ         (   DRAM_DQ         ),
+        .SDRAM_DQM   ( {DRAM_UDQM, DRAM_LDQM} ),
+        `endif
+
+        `ifdef MFP_EJTAG_DEBUGGER
+        .EJ_TRST_N_probe  (   EJ_TRST         ),
+        .EJ_TDI           (   EJ_TDI          ),
+        .EJ_TDO           (   EJ_TDO          ),
+        .EJ_TMS           (   EJ_TMS          ),
+        .EJ_TCK           (   EJ_TCK          ),
+        .SI_ColdReset     ( ~ EJ_RST          ),
+        .EJ_DINT          (   EJ_DINT         ),
+        `endif
+
+        .IO_Switches      (   IO_Switches     ),
+        .IO_Buttons       (   IO_Buttons      ),
+        .IO_RedLEDs       (   IO_RedLEDs      ),
+        .IO_GreenLEDs     (   IO_GreenLEDs    ), 
+        .IO_7_SegmentHEX  (   IO_7_SegmentHEX ),
+
+        `ifdef MFP_DEMO_LIGHT_SENSOR
+        .SPI_CS           (   ALS_CS          ),
+        .SPI_SCK          (   ALS_SCK         ),
+        .SPI_SDO          (   ALS_SDO         ),
+        `endif
+                                              
+        .UART_RX          (   GPIO_1 [31]     ),
+        .UART_TX          (   /* TODO */      )
+    );
+
+    `ifdef MFP_USE_SDRAM_MEMORY
+        //SDRAM controller delay params
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_nCKE          = `SDRAM_DELAY_nCKE;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tREF          = `SDRAM_DELAY_tREF;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tRP           = `SDRAM_DELAY_tRP;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tRFC          = `SDRAM_DELAY_tRFC;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tMRD          = `SDRAM_DELAY_tMRD;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tRCD          = `SDRAM_DELAY_tRCD;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tCAS          = `SDRAM_DELAY_tCAS;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_afterREAD     = `SDRAM_DELAY_afterREAD;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_afterWRITE    = `SDRAM_DELAY_afterWRITE;
+        defparam mfp_system.matrix_loader.matrix.ram.COUNT_initAutoRef   = `SDRAM_COUNT_initAutoRef;
+    `endif
+
+    mfp_single_digit_seven_segment_display digit_5 ( IO_7_SegmentHEX [23:20] , HEX5 );
+    mfp_single_digit_seven_segment_display digit_4 ( IO_7_SegmentHEX [19:16] , HEX4 );
+    mfp_single_digit_seven_segment_display digit_3 ( IO_7_SegmentHEX [15:12] , HEX3 );
+    mfp_single_digit_seven_segment_display digit_2 ( IO_7_SegmentHEX [11: 8] , HEX2 );
+    mfp_single_digit_seven_segment_display digit_1 ( IO_7_SegmentHEX [ 7: 4] , HEX1 );
+    mfp_single_digit_seven_segment_display digit_0 ( IO_7_SegmentHEX [ 3: 0] , HEX0 );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/de0_nano/de0_nano.sdc

@@ -0,0 +1,87 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 40 [get_nets mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz|clko]
+create_clock -period 20 [get_nets de0_nano|clk]
+create_clock -period 20 [get_ports GPIO_0_D[15]]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

MIPSfpga_mipsfpga-plus/boards/de0_nano/de0_nano.v

@@ -0,0 +1,144 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de0_nano
+(
+    input         CLOCK_50,
+    output [ 7:0] LED,
+    input  [ 1:0] KEY,
+    input  [ 3:0] SW,
+
+    `ifdef UNUSED
+
+    output [12:0] DRAM_ADDR,
+    output [ 1:0] DRAM_BA,
+    output        DRAM_CAS_N,
+    output        DRAM_CKE,
+    output        DRAM_CLK,
+    output        DRAM_CS_N,
+    inout  [15:0] DRAM_DQ,
+    output [ 1:0] DRAM_DQM,
+    output        DRAM_RAS_N,
+    output        DRAM_WE_N,
+
+    output        EPCS_ASDO,
+    input         EPCS_DATA0,
+    output        EPCS_DCLK,
+    output        EPCS_NCSO,
+
+    output        G_SENSOR_CS_N,
+    input         G_SENSOR_INT,
+
+    output        I2C_SCLK,
+    inout         I2C_SDAT,
+
+    output        ADC_CS_N,
+    output        ADC_SADDR,
+    output        ADC_SCLK,
+    input         ADC_SDAT,
+
+    inout  [12:0] GPIO_2,
+    input  [ 2:0] GPIO_2_IN,
+
+    `endif
+
+    inout  [33:0] GPIO_0_D,
+    input  [ 1:0] GPIO_0_IN
+
+    `ifdef UNUSED
+
+    ,
+    inout  [33:0] GPIO_1_D,
+    input  [ 1:0] GPIO_1_IN
+
+    `endif
+);
+
+    wire clk;
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( CLOCK_50 ),
+        .sw_in  ( SW [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( CLOCK_50  ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    global gclk
+    (
+        .in     ( muxed_clk  ), 
+        .out    ( clk        )
+    );
+
+    `else
+
+    assign clk = CLOCK_50;
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 4 { 1'b0 } } ,   SW  [3:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  - 2 { 1'b0 } } , ~ KEY [1:0] };
+
+    assign LED = SW [3] ? IO_GreenLEDs [7:0] : IO_RedLEDs [7:0];
+                          
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk           ),
+        .SI_Reset         ( ~ KEY [0]       ),
+                          
+        .HADDR            ( HADDR           ),
+        .HRDATA           ( HRDATA          ),
+        .HWDATA           ( HWDATA          ),
+        .HWRITE           ( HWRITE          ),
+                          
+        .EJ_TRST_N_probe  (   GPIO_0_D [20] ),
+        .EJ_TDI           (   GPIO_0_D [19] ),
+        .EJ_TDO           (   GPIO_0_D [17] ),
+        .EJ_TMS           (   GPIO_0_D [21] ),
+        .EJ_TCK           (   GPIO_0_D [15] ),
+        .SI_ColdReset     ( ~ GPIO_0_D [18] ),
+        .EJ_DINT          (   1'b0          ),
+
+        .IO_Switches      ( IO_Switches      ),
+        .IO_Buttons       ( IO_Buttons       ),
+        .IO_RedLEDs       ( IO_RedLEDs       ),
+        .IO_GreenLEDs     ( IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  ( IO_7_SegmentHEX  ),
+                                               
+        .UART_RX          ( /* GPIO_0_IN [0] */ GPIO_0_D [29] ),
+        .UART_TX          ( /* TODO */      ),
+
+        .SPI_CS           ( GPIO_0_D [32]   ),
+        .SPI_SCK          ( GPIO_0_D [26]   ),
+        .SPI_SDO          ( GPIO_0_D [28]   )
+    );
+
+    assign GPIO_0_D [13] = 1'b0;
+    assign GPIO_0_D [12] = 1'b0;
+    assign GPIO_0_D [11] = 1'b1;
+    assign GPIO_0_D [10] = 1'b1;
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/de1/de1.sdc

@@ -0,0 +1,61 @@
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 37 [get_ports CLOCK_27[1]]
+create_clock -period 40 [get_nets mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz|clko]
+#create_clock -period 40 [get_nets de1|clk]
+create_clock -period 20 [get_ports GPIO_1[17]]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+derive_pll_clocks
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+#**************************************************************
+# Set Clock Groups
+##**************************************************************
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+#**************************************************************
+# Set Load
+#**************************************************************

MIPSfpga_mipsfpga-plus/boards/de1/de1.v

@@ -0,0 +1,182 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de1
+(
+    input  [ 1:0] CLOCK_24,
+    input  [ 1:0] CLOCK_27,
+    input         CLOCK_50,
+    input         EXT_CLOCK,
+
+    input  [ 3:0] KEY,
+
+    input  [ 9:0] SW,
+
+    output [ 6:0] HEX0,
+    output [ 6:0] HEX1,
+    output [ 6:0] HEX2,
+    output [ 6:0] HEX3,
+
+    output [ 7:0] LEDG,
+    output [ 9:0] LEDR,
+
+    output        UART_TXD,
+    input         UART_RXD,
+
+    inout  [15:0] DRAM_DQ,
+    output [11:0] DRAM_ADDR,
+    output        DRAM_LDQM,
+    output        DRAM_UDQM,
+    output        DRAM_WE_N,
+    output        DRAM_CAS_N,
+    output        DRAM_RAS_N,
+    output        DRAM_CS_N,
+    output        DRAM_BA_0,
+    output        DRAM_BA_1,
+    output        DRAM_CLK,
+    output        DRAM_CKE,
+
+    inout  [ 7:0] FL_DQ,
+    output [21:0] FL_ADDR,
+    output        FL_WE_N,
+    output        FL_RST_N,
+    output        FL_OE_N,
+    output        FL_CE_N,
+
+    inout  [15:0] SRAM_DQ,
+    output [17:0] SRAM_ADDR,
+    output        SRAM_UB_N,
+    output        SRAM_LB_N,
+    output        SRAM_WE_N,
+    output        SRAM_CE_N,
+    output        SRAM_OE_N,
+
+    inout         SD_DAT,
+    inout         SD_DAT3,
+    inout         SD_CMD,
+    output        SD_CLK,
+
+    inout         I2C_SDAT,
+    output        I2C_SCLK,
+
+    input         PS2_DAT,
+    input         PS2_CLK,
+
+    input         TDI,
+    input         TCK,
+    input         TCS,
+    output        TDO,
+
+    output        VGA_HS,
+    output        VGA_VS,
+    output [ 3:0] VGA_R,
+    output [ 3:0] VGA_G,
+    output [ 3:0] VGA_B,
+
+    output        AUD_ADCLRCK,
+    input         AUD_ADCDAT,
+    output        AUD_DACLRCK,
+    output        AUD_DACDAT,
+    inout         AUD_BCLK,
+    output        AUD_XCK,
+
+    inout  [35:0] GPIO_0,
+    inout  [35:0] GPIO_1
+);
+
+    wire clk;
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( CLOCK_50 ),
+        .sw_in  ( SW [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( CLOCK_50  ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    global gclk
+    (
+        .in     ( muxed_clk  ), 
+        .out    ( clk        )
+    );
+
+    `else
+
+    assign clk = CLOCK_27 [1];
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 10 { 1'b0 } } ,   SW  [9:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  4 { 1'b0 } } , ~ KEY [3:0] };
+
+    assign LEDG = IO_GreenLEDs [7:0];
+    assign LEDR = IO_RedLEDs   [9:0];
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk           ),
+        .SI_Reset         ( ~ KEY [0]       ),
+                          
+        .HADDR            ( HADDR           ),
+        .HRDATA           ( HRDATA          ),
+        .HWDATA           ( HWDATA          ),
+        .HWRITE           ( HWRITE          ),
+                          
+        .EJ_TRST_N_probe  (   GPIO_1 [22]   ),
+        .EJ_TDI           (   GPIO_1 [21]   ),
+        .EJ_TDO           (   GPIO_1 [19]   ),
+        .EJ_TMS           (   GPIO_1 [23]   ),
+        .EJ_TCK           (   GPIO_1 [17]   ),
+        .SI_ColdReset     ( ~ GPIO_1 [20]   ),
+        .EJ_DINT          (   1'b0          ),
+
+        .IO_Switches      ( IO_Switches      ),
+        .IO_Buttons       ( IO_Buttons       ),
+        .IO_RedLEDs       ( IO_RedLEDs       ),
+        .IO_GreenLEDs     ( IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  ( IO_7_SegmentHEX  ),
+                                                                         
+        .UART_RX          ( GPIO_1 [31]     ),
+        .UART_TX          ( /* TODO */      ),
+
+        .SPI_CS           ( GPIO_1 [34]     ),
+        .SPI_SCK          ( GPIO_1 [28]     ),
+        .SPI_SDO          ( GPIO_1 [30]     )
+    );
+
+    assign GPIO_1 [15] = 1'b0;
+    assign GPIO_1 [14] = 1'b0;
+    assign GPIO_1 [13] = 1'b1;
+    assign GPIO_1 [12] = 1'b1;
+
+    assign GPIO_1 [26] = 1'b0;
+
+    mfp_single_digit_seven_segment_display digit_3 ( IO_7_SegmentHEX [15:12] , HEX3 );
+    mfp_single_digit_seven_segment_display digit_2 ( IO_7_SegmentHEX [11: 8] , HEX2 );
+    mfp_single_digit_seven_segment_display digit_1 ( IO_7_SegmentHEX [ 7: 4] , HEX1 );
+    mfp_single_digit_seven_segment_display digit_0 ( IO_7_SegmentHEX [ 3: 0] , HEX0 );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/de10_lite/board_config.vh

@@ -0,0 +1,24 @@
+//board specific settings
+
+//SDRAM parameters for 64MB (Terasic DE10-Lite)
+`ifdef MFP_USE_SDRAM_MEMORY
+    `define SDRAM_ADDR_BITS         13
+    `define SDRAM_ROW_BITS          13
+    `define SDRAM_COL_BITS          10
+    `define SDRAM_DQ_BITS           16
+    `define SDRAM_BA_BITS           2
+    `define SDRAM_DM_BITS           2
+    `define MFP_RAM_ADDR_WIDTH      (`SDRAM_ROW_BITS + `SDRAM_COL_BITS + `SDRAM_BA_BITS)
+
+    //values for fclk=50 MHz
+    `define SDRAM_DELAY_nCKE        10000
+    `define SDRAM_DELAY_tREF        360
+    `define SDRAM_DELAY_tRP         0
+    `define SDRAM_DELAY_tRFC        2
+    `define SDRAM_DELAY_tMRD        0
+    `define SDRAM_DELAY_tRCD        0
+    `define SDRAM_DELAY_tCAS        0
+    `define SDRAM_DELAY_afterREAD   0
+    `define SDRAM_DELAY_afterWRITE  2
+    `define SDRAM_COUNT_initAutoRef 8
+`endif

MIPSfpga_mipsfpga-plus/boards/de10_lite/de10_lite.sdc

@@ -0,0 +1,84 @@
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period "10.0 MHz" [get_ports ADC_CLK_10]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports MAX10_CLK2_50]
+create_clock -period 40 [get_nets mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz|clko]
+create_clock -period 20 [get_nets de10_lite|clk]
+create_clock -period 20 [get_ports GPIO[17]]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

MIPSfpga_mipsfpga-plus/boards/de10_lite/de10_lite.v

@@ -0,0 +1,306 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de10_lite
+(
+    input           ADC_CLK_10,
+    input           MAX10_CLK1_50,
+    input           MAX10_CLK2_50,
+
+    input   [ 1:0]  KEY,
+    input   [ 9:0]  SW,
+    output  [ 7:0]  HEX0,
+    output  [ 7:0]  HEX1,
+    output  [ 7:0]  HEX2,
+    output  [ 7:0]  HEX3,
+    output  [ 7:0]  HEX4,
+    output  [ 7:0]  HEX5,
+    output  [ 9:0]  LEDR,
+
+    `ifdef MFP_USE_SDRAM_MEMORY
+        output  [12:0]  DRAM_ADDR,
+        output  [ 1:0]  DRAM_BA,
+        output          DRAM_CAS_N,
+        output          DRAM_CKE,
+        output          DRAM_CLK,
+        output          DRAM_CS_N,
+        inout   [15:0]  DRAM_DQ,
+        output          DRAM_LDQM,
+        output          DRAM_RAS_N,
+        output          DRAM_UDQM,
+        output          DRAM_WE_N,
+    `endif
+    
+    `ifdef UNUSED
+        output  [ 3:0]  VGA_B,
+        output  [ 3:0]  VGA_G,
+        output          VGA_HS,
+        output  [ 3:0]  VGA_R,
+        output          VGA_VS,
+        output          GSENSOR_CS_N,
+        input   [ 2:1]  GSENSOR_INT,
+        output          GSENSOR_SCLK,
+        inout           GSENSOR_SDI,
+        inout           GSENSOR_SDO,
+        inout   [15:0]  ARDUINO_IO,
+        inout           ARDUINO_RESET_N,
+    `endif
+
+    inout   [35:0]  GPIO
+);
+
+    // global clock signals
+    wire clk;
+    wire ADC_CLK;
+    wire clk200;  //for phase shift debug with logic analyser
+
+    `ifdef MFP_USE_SDRAM_MEMORY
+        wire CLK_Lock;
+        pll pll(MAX10_CLK1_50, ADC_CLK, clk, DRAM_CLK, clk200, CLK_Lock);
+
+    `elsif MFP_USE_ADC_MAX10
+        wire CLK_Lock;
+        pll pll(MAX10_CLK1_50, ADC_CLK, clk, DRAM_CLK, clk200, CLK_Lock);
+
+    `elsif MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+        wire       CLK_Lock = 1'b1;
+        wire       muxed_clk;
+        wire [1:0] sw_db;
+
+        mfp_multi_switch_or_button_sync_and_debouncer
+        # (.WIDTH (2))
+        mfp_multi_switch_or_button_sync_and_debouncer
+        (   
+            .clk    ( MAX10_CLK1_50 ),
+            .sw_in  ( SW [1:0] ),
+            .sw_out ( sw_db    )
+        );
+
+        mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+        mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+        (
+            .clki    ( MAX10_CLK1_50  ),
+            .sel_lo  ( sw_db [0] ),
+            .sel_mid ( sw_db [1] ),
+            .clko    ( muxed_clk )
+        );
+
+        global gclk
+        (
+            .in     ( muxed_clk  ), 
+            .out    ( clk        )
+        );
+
+    `else
+        wire   CLK_Lock = 1'b1;
+        assign clk = MAX10_CLK1_50;
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 10 { 1'b0 } } ,   SW  [9:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  2 { 1'b0 } } , ~ KEY [1:0] };
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    `ifdef MFP_USE_SDRAM_MEMORY
+        assign LEDR[9] = ~DRAM_CKE;
+        assign LEDR[8:0] = IO_RedLEDs [8:0];
+    `elsif MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+        assign LEDR = (sw_db == 2'b00 ? IO_RedLEDs [9:0] : IO_GreenLEDs [9:0]);
+    `else
+        assign LEDR = IO_RedLEDs [9:0];
+    `endif
+
+    `ifdef MFP_USE_ADC_MAX10
+        wire          ADC_C_Valid;
+        wire [  4:0 ] ADC_C_Channel;
+        wire          ADC_C_SOP;
+        wire          ADC_C_EOP;
+        wire          ADC_C_Ready;
+        wire          ADC_R_Valid;
+        wire [  4:0 ] ADC_R_Channel;
+        wire [ 11:0 ] ADC_R_Data;
+        wire          ADC_R_SOP;
+        wire          ADC_R_EOP;
+    `endif
+
+    `define MFP_EJTAG_DEBUGGER
+    `ifdef MFP_EJTAG_DEBUGGER
+        // MIPSfpga EJTAG BusBluster 3 connector pinout
+        // EJTAG     DIRECTION   PIN      CONN      PIN    DIRECTION EJTAG 
+        // =====     ========= ======== ========= ======== ========= ======
+        //  VCC       output   GPIO[12]  15 | 16  GPIO[13]  output    VCC  
+        //  GND       output   GPIO[14]  17 | 18  GPIO[15]  output    GND  
+        //  NC        output   GPIO[16]  19 | 20  GPIO[17]  input    EJ_TCK
+        //  NC        output   GPIO[18]  21 | 22  GPIO[19]  output   EJ_TDO
+        //  EJ_RST    input    GPIO[20]  23 | 24  GPIO[21]  input    EJ_TDI
+        //  EJ_TRST   input    GPIO[22]  25 | 26  GPIO[23]  input    EJ_TMS
+
+        wire EJ_VCC  = 1'b1;
+        wire EJ_GND  = 1'b0;
+        wire EJ_NC   = 1'bz;
+        wire EJ_TCK  = GPIO[17];
+        wire EJ_RST  = GPIO[20];
+        wire EJ_TDI  = GPIO[21];
+        wire EJ_TRST = GPIO[22];
+        wire EJ_TMS  = GPIO[23];
+        wire EJ_DINT = 1'b0;
+        wire EJ_TDO;
+
+        assign GPIO[12] = EJ_VCC;
+        assign GPIO[13] = EJ_VCC;
+        assign GPIO[14] = EJ_GND;
+        assign GPIO[15] = EJ_GND;
+        assign GPIO[16] = EJ_NC;
+        assign GPIO[18] = EJ_NC;
+        assign GPIO[19] = EJ_TDO;
+    `endif
+
+    `ifdef MFP_DEMO_LIGHT_SENSOR
+        //  ALS   CONN   PIN         DIRECTION
+        // ===== ====== =====      =============
+        //  VCC    29   3.3V
+        //  GND    31   GPIO[26]   output
+        //  SCK    33   GPIO[28]   output
+        //  SDO    35   GPIO[30]   input
+        //  NC     37   GPIO[32]   not connected
+        //  CS     39   GPIO[34]   output
+
+        wire    ALS_GND = 1'b0;
+        wire    ALS_SCK;
+        wire    ALS_SDO;
+        wire    ALS_NC  = 1'bz;
+        wire    ALS_CS;
+
+        assign GPIO[26] = ALS_GND;
+        assign GPIO[28] = ALS_SCK;
+        assign ALS_SDO  = GPIO[30];
+        assign GPIO[32] = ALS_NC;
+        assign GPIO[34] = ALS_CS;
+    `endif
+
+    //This is a workaround to make EJTAG working
+    //TODO: add complex reset signals handling module
+    wire RESETn = KEY [0] & GPIO [20] & CLK_Lock;
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk             ),
+        .SI_Reset         (   ~RESETn         ),
+                          
+        .HADDR            (   HADDR           ),
+        .HRDATA           (   HRDATA          ),
+        .HWDATA           (   HWDATA          ),
+        .HWRITE           (   HWRITE          ),
+
+        `ifdef MFP_USE_SDRAM_MEMORY
+        .SDRAM_CKE        (   DRAM_CKE        ),
+        .SDRAM_CSn        (   DRAM_CS_N       ),
+        .SDRAM_RASn       (   DRAM_RAS_N      ),
+        .SDRAM_CASn       (   DRAM_CAS_N      ),
+        .SDRAM_WEn        (   DRAM_WE_N       ),
+        .SDRAM_ADDR       (   DRAM_ADDR       ),
+        .SDRAM_BA         (   DRAM_BA         ),
+        .SDRAM_DQ         (   DRAM_DQ         ),
+        .SDRAM_DQM   ( {DRAM_UDQM, DRAM_LDQM} ),
+        `endif
+
+        `ifdef MFP_EJTAG_DEBUGGER
+        .EJ_TRST_N_probe  (   EJ_TRST         ),
+        .EJ_TDI           (   EJ_TDI          ),
+        .EJ_TDO           (   EJ_TDO          ),
+        .EJ_TMS           (   EJ_TMS          ),
+        .EJ_TCK           (   EJ_TCK          ),
+        .SI_ColdReset     ( ~ EJ_RST          ),
+        .EJ_DINT          (   EJ_DINT         ),
+        `endif
+
+        .IO_Switches      (   IO_Switches     ),
+        .IO_Buttons       (   IO_Buttons      ),
+        .IO_RedLEDs       (   IO_RedLEDs      ),
+        .IO_GreenLEDs     (   IO_GreenLEDs    ), 
+        .IO_7_SegmentHEX  (   IO_7_SegmentHEX ),
+
+        `ifdef MFP_USE_DUPLEX_UART
+        .UART_SRX         (   GPIO [33]       ), 
+        .UART_STX         (   GPIO [35]       ),
+        `endif
+
+        `ifdef MFP_DEMO_LIGHT_SENSOR
+        .SPI_CS           (   ALS_CS          ),
+        .SPI_SCK          (   ALS_SCK         ),
+        .SPI_SDO          (   ALS_SDO         ),
+        `endif
+
+        `ifdef MFP_USE_ADC_MAX10
+        .ADC_C_Valid      (  ADC_C_Valid      ),
+        .ADC_C_Channel    (  ADC_C_Channel    ),
+        .ADC_C_SOP        (  ADC_C_SOP        ),
+        .ADC_C_EOP        (  ADC_C_EOP        ),
+        .ADC_C_Ready      (  ADC_C_Ready      ),
+        .ADC_R_Valid      (  ADC_R_Valid      ),
+        .ADC_R_Channel    (  ADC_R_Channel    ),
+        .ADC_R_Data       (  ADC_R_Data       ),
+        .ADC_R_SOP        (  ADC_R_SOP        ),
+        .ADC_R_EOP        (  ADC_R_EOP        ),
+        `endif
+
+        .UART_RX          (   GPIO [31]       ),
+        .UART_TX          (   GPIO [32]       )
+    );
+
+    `ifdef MFP_USE_ADC_MAX10
+        adc adc
+        (
+            .adc_pll_clock_clk      ( ADC_CLK       ),
+            .adc_pll_locked_export  ( CLK_Lock      ),
+            .clock_clk              ( clk           ),
+            .command_valid          ( ADC_C_Valid   ),
+            .command_channel        ( ADC_C_Channel ),
+            .command_startofpacket  ( ADC_C_SOP     ),
+            .command_endofpacket    ( ADC_C_EOP     ),
+            .command_ready          ( ADC_C_Ready   ),
+            .reset_sink_reset_n     ( RESETn        ),
+            .response_valid         ( ADC_R_Valid   ),
+            .response_channel       ( ADC_R_Channel ),
+            .response_data          ( ADC_R_Data    ),
+            .response_startofpacket ( ADC_R_SOP     ),
+            .response_endofpacket   ( ADC_R_EOP     ) 
+        );
+    `endif
+
+    `ifdef MFP_USE_SDRAM_MEMORY
+        //SDRAM controller delay params
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_nCKE          = `SDRAM_DELAY_nCKE;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tREF          = `SDRAM_DELAY_tREF;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tRP           = `SDRAM_DELAY_tRP;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tRFC          = `SDRAM_DELAY_tRFC;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tMRD          = `SDRAM_DELAY_tMRD;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tRCD          = `SDRAM_DELAY_tRCD;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_tCAS          = `SDRAM_DELAY_tCAS;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_afterREAD     = `SDRAM_DELAY_afterREAD;
+        defparam mfp_system.matrix_loader.matrix.ram.DELAY_afterWRITE    = `SDRAM_DELAY_afterWRITE;
+        defparam mfp_system.matrix_loader.matrix.ram.COUNT_initAutoRef   = `SDRAM_COUNT_initAutoRef;
+    `endif
+
+    assign HEX0 [ 7] = 1'b1;
+    assign HEX1 [ 7] = 1'b1;
+    assign HEX2 [ 7] = 1'b1;
+    assign HEX3 [ 7] = 1'b1;
+    assign HEX4 [ 7] = 1'b1;
+    assign HEX5 [ 7] = 1'b1;
+
+    mfp_single_digit_seven_segment_display digit_5 ( IO_7_SegmentHEX [23:20] , HEX5 [6:0] );
+    mfp_single_digit_seven_segment_display digit_4 ( IO_7_SegmentHEX [19:16] , HEX4 [6:0] );
+    mfp_single_digit_seven_segment_display digit_3 ( IO_7_SegmentHEX [15:12] , HEX3 [6:0] );
+    mfp_single_digit_seven_segment_display digit_2 ( IO_7_SegmentHEX [11: 8] , HEX2 [6:0] );
+    mfp_single_digit_seven_segment_display digit_1 ( IO_7_SegmentHEX [ 7: 4] , HEX1 [6:0] );
+    mfp_single_digit_seven_segment_display digit_0 ( IO_7_SegmentHEX [ 3: 0] , HEX0 [6:0] );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/de10_lite/pll.v

@@ -0,0 +1,395 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+// ************************************************************
+
+
+//Copyright (C) 2016  Intel Corporation. All rights reserved.
+//Your use of Intel Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Intel Program License 
+//Subscription Agreement, the Intel Quartus Prime License Agreement,
+//the Intel MegaCore Function License Agreement, or other 
+//applicable license agreement, including, without limitation, 
+//that your use is for the sole purpose of programming logic 
+//devices manufactured by Intel and sold by Intel or its 
+//authorized distributors.  Please refer to the applicable 
+//agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0,
+	c1,
+	c2,
+	c3,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+	output	  c3;
+	output	  locked;
+
+	wire [0:0] sub_wire2 = 1'h0;
+	wire [4:0] sub_wire3;
+	wire  sub_wire8;
+	wire  sub_wire0 = inclk0;
+	wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
+	wire [3:3] sub_wire7 = sub_wire3[3:3];
+	wire [2:2] sub_wire6 = sub_wire3[2:2];
+	wire [1:1] sub_wire5 = sub_wire3[1:1];
+	wire [0:0] sub_wire4 = sub_wire3[0:0];
+	wire  c0 = sub_wire4;
+	wire  c1 = sub_wire5;
+	wire  c2 = sub_wire6;
+	wire  c3 = sub_wire7;
+	wire  locked = sub_wire8;
+
+	altpll	altpll_component (
+				.inclk (sub_wire1),
+				.clk (sub_wire3),
+				.locked (sub_wire8),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 5,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 1,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 1,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 1,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 1,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 1,
+		altpll_component.clk2_phase_shift = "-12000",
+		altpll_component.clk3_divide_by = 1,
+		altpll_component.clk3_duty_cycle = 50,
+		altpll_component.clk3_multiply_by = 4,
+		altpll_component.clk3_phase_shift = "-833",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 20000,
+		altpll_component.intended_device_family = "MAX 10",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_USED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "50.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "200.000000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-12.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-60.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-12000"
+// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
+// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "4"
+// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

MIPSfpga_mipsfpga-plus/boards/de10_nano/de10_nano.sdc

@@ -0,0 +1,92 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK1_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK2_50]
+create_clock -period "50.0 MHz" [get_ports FPGA_CLK3_50]
+
+# for enhancing USB BlasterII to be reliable, 25MHz
+create_clock -name {altera_reserved_tck} -period 40 {altera_reserved_tck}
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
+set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
+set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+

MIPSfpga_mipsfpga-plus/boards/de10_nano/de10_nano.v

@@ -0,0 +1,148 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de10_nano(
+
+	//////////// ADC //////////
+	output		          		ADC_CONVST,
+	output		          		ADC_SCK,
+	output		          		ADC_SDI,
+	input 		          		ADC_SDO,
+
+	//////////// ARDUINO //////////
+	inout 		    [15:0]		ARDUINO_IO,
+	inout 		          		ARDUINO_RESET_N,
+
+	//////////// CLOCK //////////
+	input 		          		FPGA_CLK1_50,
+	input 		          		FPGA_CLK2_50,
+	input 		          		FPGA_CLK3_50,
+
+	//////////// HDMI //////////
+	inout 		          		HDMI_I2C_SCL,
+	inout 		          		HDMI_I2C_SDA,
+	inout 		          		HDMI_I2S,
+	inout 		          		HDMI_LRCLK,
+	inout 		          		HDMI_MCLK,
+	inout 		          		HDMI_SCLK,
+	output		          		HDMI_TX_CLK,
+	output		          		HDMI_TX_DE,
+	output		    [23:0]		HDMI_TX_D,
+	output		          		HDMI_TX_HS,
+	input 		          		HDMI_TX_INT,
+	output		          		HDMI_TX_VS,
+
+	//////////// KEY //////////
+	input 		     [1:0]		KEY,
+
+	//////////// LED //////////
+	output		     [7:0]		LED,
+
+	//////////// SW //////////
+	input 		     [3:0]		SW,
+
+	//////////// GPIO_0, GPIO connect to GPIO Default //////////
+	inout 		    [35:0]		GPIO_0,
+
+	//////////// GPIO_1, GPIO connect to GPIO Default //////////
+	inout 		    [35:0]		GPIO_1
+);
+
+    // global clock signals
+    wire clk;
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+        wire       muxed_clk;
+        wire [1:0] sw_db;
+
+        mfp_multi_switch_or_button_sync_and_debouncer
+        # (.WIDTH (2))
+        mfp_multi_switch_or_button_sync_and_debouncer
+        (   
+            .clk    ( FPGA_CLK1_50 ),
+            .sw_in  ( SW [1:0]     ),
+            .sw_out ( sw_db        )
+        );
+
+        mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+        mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+        (
+            .clki    ( FPGA_CLK1_50  ),
+            .sel_lo  ( sw_db [0]     ),
+            .sel_mid ( sw_db [1]     ),
+            .clko    ( muxed_clk     )
+        );
+
+        global gclk
+        (
+            .in     ( muxed_clk  ), 
+            .out    ( clk        )
+        );
+
+    `else
+        assign clk = FPGA_CLK1_50;
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 4 { 1'b0 } } ,   SW  [3:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  - 2 { 1'b0 } } , ~ KEY [1:0] };
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+	assign LED = IO_GreenLEDs [7:0];
+
+    //This is a workaround to make EJTAG working
+    //TODO: add complex reset signals handling module
+    wire RESETn = KEY [0] & GPIO_0 [20];
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk             ),
+        .SI_Reset         (   ~RESETn         ),
+                          
+        .HADDR            (   HADDR           ),
+        .HRDATA           (   HRDATA          ),
+        .HWDATA           (   HWDATA          ),
+        .HWRITE           (   HWRITE          ),
+
+        .EJ_TRST_N_probe  (   GPIO_0 [22]     ),
+        .EJ_TDI           (   GPIO_0 [21]     ),
+        .EJ_TDO           (   GPIO_0 [19]     ),
+        .EJ_TMS           (   GPIO_0 [23]     ),
+        .EJ_TCK           (   GPIO_0 [17]     ),
+        .SI_ColdReset     ( ~ GPIO_0 [20]     ),
+        .EJ_DINT          (   1'b0            ),
+
+        .IO_Switches      (   IO_Switches     ),
+        .IO_Buttons       (   IO_Buttons      ),
+        .IO_RedLEDs       (   IO_RedLEDs      ),
+        .IO_GreenLEDs     (   IO_GreenLEDs    ), 
+        .IO_7_SegmentHEX  (   IO_7_SegmentHEX ),
+
+        .UART_RX          (   GPIO_0 [31]     ),
+        .UART_TX          (   GPIO_0 [32]     ),
+
+        `ifdef MFP_USE_DUPLEX_UART
+        .UART_SRX         (   GPIO_0 [33]     ), 
+        .UART_STX         (   GPIO_0 [35]     ),
+        `endif
+
+        .SPI_CS           (   GPIO_0 [34]     ),
+        .SPI_SCK          (   GPIO_0 [28]     ),
+        .SPI_SDO          (   GPIO_0 [30]     )
+    );
+
+    assign GPIO_0 [15] = 1'b0;
+    assign GPIO_0 [14] = 1'b0;
+    assign GPIO_0 [13] = 1'b1;
+    assign GPIO_0 [12] = 1'b1;
+   
+    assign GPIO_0 [26] = 1'b0;
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/de2_115/de2_115.sdc

@@ -0,0 +1,62 @@
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -period 20 [get_ports CLOCK_50]
+create_clock -period 20 [get_ports CLOCK2_50]
+create_clock -period 20 [get_ports CLOCK3_50]
+create_clock -period 40 [get_nets mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz|clko]
+#create_clock -period 40 [get_nets de1|clk]
+create_clock -period 20 [get_ports GPIO_1[17]]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+derive_pll_clocks
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+#**************************************************************
+# Set Clock Groups
+##**************************************************************
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+#**************************************************************
+# Set Load
+#**************************************************************

MIPSfpga_mipsfpga-plus/boards/de2_115/de2_115.v

@@ -0,0 +1,343 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module de2_115
+(
+    input         CLOCK_50,
+    input         CLOCK2_50,
+    input         CLOCK3_50,
+    input         ENETCLK_25,
+
+    // Sma
+
+    input         SMA_CLKIN,
+    output        SMA_CLKOUT,
+
+    // LED
+
+    output [ 8:0] LEDG,
+    output [17:0] LEDR,
+
+    // KEY
+
+    input  [ 3:0] KEY,
+
+    // SW
+
+    input  [17:0] SW,
+
+    // SEG7
+
+    output [ 6:0] HEX0,
+    output [ 6:0] HEX1,
+    output [ 6:0] HEX2,
+    output [ 6:0] HEX3,
+    output [ 6:0] HEX4,
+    output [ 6:0] HEX5,
+    output [ 6:0] HEX6,
+    output [ 6:0] HEX7,
+
+`ifdef UNUSED
+
+    // LCD
+
+    output        LCD_BLON,
+    inout  [ 7:0] LCD_DATA,
+    output        LCD_EN,
+    output        LCD_ON,
+    output        LCD_RS,
+    output        LCD_RW,
+
+    // RS232
+
+    output        UART_CTS,
+    input         UART_RTS,
+    input         UART_RXD,
+    output        UART_TXD,
+
+    // PS2
+
+    inout         PS2_CLK,
+    inout         PS2_DAT,
+    inout         PS2_CLK2,
+    inout         PS2_DAT2,
+
+    // SDCARD
+
+    output        SD_CLK,
+    inout         SD_CMD,
+    inout  [ 3:0] SD_DAT,
+    input         SD_WP_N,
+
+    // VGA
+
+    output [ 7:0] VGA_B,
+    output        VGA_BLANK_N,
+    output        VGA_CLK,
+    output [ 7:0] VGA_G,
+    output        VGA_HS,
+    output [ 7:0] VGA_R,
+    output        VGA_SYNC_N,
+    output        VGA_VS,
+
+    // Audio
+
+    input         AUD_ADCDAT,
+    inout         AUD_ADCLRCK,
+    inout         AUD_BCLK,
+    output        AUD_DACDAT,
+    inout         AUD_DACLRCK,
+    output        AUD_XCK,
+
+    // I2C for EEPROM
+
+    output        EEP_I2C_SCLK,
+    inout         EEP_I2C_SDAT,
+
+    // I2C for Audio and Tv-Decode
+
+    output        I2C_SCLK,
+    inout         I2C_SDAT,
+
+    // Ethernet 0
+
+    output        ENET0_GTX_CLK,
+    input         ENET0_INT_N,
+    output        ENET0_MDC,
+    input         ENET0_MDIO,
+    output        ENET0_RST_N,
+    input         ENET0_RX_CLK,
+    input         ENET0_RX_COL,
+    input         ENET0_RX_CRS,
+    input  [ 3:0] ENET0_RX_DATA,
+    input         ENET0_RX_DV,
+    input         ENET0_RX_ER,
+    input         ENET0_TX_CLK,
+    output [ 3:0] ENET0_TX_DATA,
+    output        ENET0_TX_EN,
+    output        ENET0_TX_ER,
+    input         ENET0_LINK100,
+
+    // Ethernet 1
+
+    output        ENET1_GTX_CLK,
+    input         ENET1_INT_N,
+    output        ENET1_MDC,
+    input         ENET1_MDIO,
+    output        ENET1_RST_N,
+    input         ENET1_RX_CLK,
+    input         ENET1_RX_COL,
+    input         ENET1_RX_CRS,
+    input  [ 3:0] ENET1_RX_DATA,
+    input         ENET1_RX_DV,
+    input         ENET1_RX_ER,
+    input         ENET1_TX_CLK,
+    output [ 3:0] ENET1_TX_DATA,
+    output        ENET1_TX_EN,
+    output        ENET1_TX_ER,
+    input         ENET1_LINK100,
+
+    // TV Decoder 1
+
+    input         TD_CLK27,
+    input  [ 7:0] TD_DATA,
+    input         TD_HS,
+    output        TD_RESET_N,
+    input         TD_VS,
+
+
+    // USB OTG controller
+
+    inout  [15:0] OTG_DATA,
+    output [ 1:0] OTG_ADDR,
+    output        OTG_CS_N,
+    output        OTG_WR_N,
+    output        OTG_RD_N,
+    input         OTG_INT,
+    output        OTG_RST_N,
+
+    // IR Receiver
+
+    input         IRDA_RXD,
+
+    // SDRAM
+
+    output [12:0] DRAM_ADDR,
+    output [ 1:0] DRAM_BA,
+    output        DRAM_CAS_N,
+    output        DRAM_CKE,
+    output        DRAM_CLK,
+    output        DRAM_CS_N,
+    inout  [31:0] DRAM_DQ,
+    output [ 3:0] DRAM_DQM,
+    output        DRAM_RAS_N,
+    output        DRAM_WE_N,
+
+    // SRAM
+
+    output [19:0] SRAM_ADDR,
+    output        SRAM_CE_N,
+    inout  [15:0] SRAM_DQ,
+    output        SRAM_LB_N,
+    output        SRAM_OE_N,
+    output        SRAM_UB_N,
+    output        SRAM_WE_N,
+
+    // Flash
+
+    output [22:0] FL_ADDR,
+    output        FL_CE_N,
+    inout  [ 7:0] FL_DQ,
+    output        FL_OE_N,
+    output        FL_RST_N,
+    input         FL_RY,
+    output        FL_WE_N,
+    output        FL_WP_N,
+
+`endif
+
+    // GPIO
+
+    inout  [35:0] GPIO,
+
+`ifdef UNUSED
+
+    // HSMC (LVDS)
+
+ // input         HSMC_CLKIN_N1,
+ // input         HSMC_CLKIN_N2,
+    input         HSMC_CLKIN_P1,
+    input         HSMC_CLKIN_P2,
+    input         HSMC_CLKIN0,
+ // output        HSMC_CLKOUT_N1,
+ // output        HSMC_CLKOUT_N2,
+    output        HSMC_CLKOUT_P1,
+    output        HSMC_CLKOUT_P2,
+    output        HSMC_CLKOUT0,
+    inout  [ 3:0] HSMC_D,
+ // input  [16:0] HSMC_RX_D_N,
+    input  [16:0] HSMC_RX_D_P,
+ // output [16:0] HSMC_TX_D_N,
+    output [16:0] HSMC_TX_D_P,
+
+`endif
+
+    // EXTEND IO
+
+    inout  [ 6:0] EX_IO
+);
+
+    wire clk;
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( CLOCK_50 ),
+        .sw_in  ( SW [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( CLOCK_50  ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    global gclk
+    (
+        .in     ( muxed_clk  ), 
+        .out    ( clk        )
+    );
+
+    `else
+
+    assign clk = CLOCK_50;
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 18 { 1'b0 } } ,   SW  [17:0] };
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  4 { 1'b0 } } , ~ KEY [ 3:0] };
+
+    assign LEDG = IO_GreenLEDs [ 8:0];
+    assign LEDR = IO_RedLEDs   [17:0];
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk              ),
+        .SI_Reset         ( ~ KEY [0]          ),
+                          
+        .HADDR            (   HADDR            ),
+        .HRDATA           (   HRDATA           ),
+        .HWDATA           (   HWDATA           ),
+        .HWRITE           (   HWRITE           ),
+
+        `ifdef MFP_USE_GPIO_FOR_EJTAG
+                          
+        .EJ_TRST_N_probe  (   GPIO [22]        ),
+        .EJ_TDI           (   GPIO [21]        ),
+        .EJ_TDO           (   GPIO [19]        ),
+        .EJ_TMS           (   GPIO [23]        ),
+        .EJ_TCK           (   GPIO [17]        ),
+        .SI_ColdReset     ( ~ GPIO [20]        ),
+        .EJ_DINT          (   1'b0             ),
+
+        `else                                  
+                                               
+        .EJ_TRST_N_probe  (   EX_IO [6]        ),
+        .EJ_TDI           (   EX_IO [5]        ),
+        .EJ_TDO           (   EX_IO [4]        ),
+        .EJ_TMS           (   EX_IO [3]        ),
+        .EJ_TCK           (   EX_IO [2]        ),
+        .SI_ColdReset     ( ~ EX_IO [1]        ),
+        .EJ_DINT          (   EX_IO [0]        ),
+                                               
+        `endif
+
+        .IO_Switches      (   IO_Switches      ),
+        .IO_Buttons       (   IO_Buttons       ),
+        .IO_RedLEDs       (   IO_RedLEDs       ),
+        .IO_GreenLEDs     (   IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  (   IO_7_SegmentHEX  ),
+                                               
+        .UART_RX          (   GPIO [31]        ),
+        .UART_TX          (   /* TODO */       ),
+
+        .SPI_CS           (   GPIO [34]        ),
+        .SPI_SCK          (   GPIO [28]        ),
+        .SPI_SDO          (   GPIO [30]        )
+    );
+
+    assign GPIO [15] = 1'b0;
+    assign GPIO [14] = 1'b0;
+    assign GPIO [13] = 1'b1;
+    assign GPIO [12] = 1'b1;
+
+    assign GPIO [26] = 1'b0;
+
+    mfp_single_digit_seven_segment_display digit_7 ( IO_7_SegmentHEX [31:28] , HEX7 );
+    mfp_single_digit_seven_segment_display digit_6 ( IO_7_SegmentHEX [27:24] , HEX6 );
+    mfp_single_digit_seven_segment_display digit_5 ( IO_7_SegmentHEX [23:20] , HEX5 );
+    mfp_single_digit_seven_segment_display digit_4 ( IO_7_SegmentHEX [19:16] , HEX4 );
+    mfp_single_digit_seven_segment_display digit_3 ( IO_7_SegmentHEX [15:12] , HEX3 );
+    mfp_single_digit_seven_segment_display digit_2 ( IO_7_SegmentHEX [11: 8] , HEX2 );
+    mfp_single_digit_seven_segment_display digit_1 ( IO_7_SegmentHEX [ 7: 4] , HEX1 );
+    mfp_single_digit_seven_segment_display digit_0 ( IO_7_SegmentHEX [ 3: 0] , HEX0 );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/nexys4/nexys4.v

@@ -0,0 +1,148 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module nexys4
+(
+    input         clk,
+    input         btnCpuReset,
+
+    input         btnC,
+    input         btnU,
+    input         btnL,
+    input         btnR,
+    input         btnD,
+
+    input  [15:0] sw,
+
+    output [15:0] led,
+
+    output        RGB1_Red,
+    output        RGB1_Green,
+    output        RGB1_Blue,
+    output        RGB2_Red,
+    output        RGB2_Green,
+    output        RGB2_Blue,
+
+    output [ 6:0] seg,
+    output        dp,
+    output [ 7:0] an,
+
+    inout  [ 7:0] JA,
+    inout  [ 7:0] JB,
+
+    input         RsRx
+);
+
+    wire clock;
+    wire reset = ~ btnCpuReset;
+
+    `define MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( clk      ),
+        .sw_in  ( sw [1:0] ),
+        .sw_out ( sw_db    )
+    );
+
+    mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( clk       ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    BUFG BUFG_slow_clk (.O ( clock ), .I ( muxed_clk ));
+
+    `else
+
+    clk_wiz_0 clk_wiz_0 (.clk_in1 (clk), .clk_out1 (clock));
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 16 { 1'b0 } } , sw  [15:0] };
+
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  5 { 1'b0 } } ,
+                           btnU, btnD, btnL, btnC, btnR };
+
+    assign led = IO_GreenLEDs [15:0];
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    wire ejtag_tck_in, ejtag_tck;
+
+    IBUF IBUF           (.O ( ejtag_tck_in ), .I ( JB [3]       ));
+    BUFG BUFG_ejtag_tck (.O ( ejtag_tck    ), .I ( ejtag_tck_in ));
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         ( clock           ),
+        .SI_Reset         ( reset           ),
+                          
+        .HADDR            ( HADDR           ),
+        .HRDATA           ( HRDATA          ),
+        .HWDATA           ( HWDATA          ),
+        .HWRITE           ( HWRITE          ),
+
+        .EJ_TRST_N_probe  (   JB [4]        ),
+        .EJ_TDI           (   JB [1]        ),
+        .EJ_TDO           (   JB [2]        ),
+        .EJ_TMS           (   JB [0]        ),
+        .EJ_TCK           (   ejtag_tck_in  ),
+        .SI_ColdReset     ( ~ JB [5]        ),
+        .EJ_DINT          (   1'b0          ),
+
+        .IO_Switches      ( IO_Switches      ),
+        .IO_Buttons       ( IO_Buttons       ),
+        .IO_RedLEDs       ( IO_RedLEDs       ),
+        .IO_GreenLEDs     ( IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  ( IO_7_SegmentHEX  ),
+
+        .UART_RX          ( RsRx /* Alternative: JA [7] */ ),
+        .UART_TX          ( /* TODO */       ),
+
+        .SPI_CS           (   JA [0]         ),
+        .SPI_SCK          (   JA [3]         ),
+        .SPI_SDO          (   JA [2]         )
+    );
+
+    assign JA [4] = 1'b0;
+
+    wire display_clock;
+
+    mfp_clock_divider_100_MHz_to_763_Hz mfp_clock_divider_100_MHz_to_763_Hz
+        (clk, display_clock);
+
+    mfp_multi_digit_display multi_digit_display
+    (
+        .clock          (   display_clock   ),
+        .resetn         ( ~ reset           ),
+        .number         (   IO_7_SegmentHEX ),
+
+        .seven_segments (   seg             ),
+        .dot            (   dp              ),
+        .anodes         (   an              )
+    );
+
+    assign RGB1_Red   = 1'b0; 
+    assign RGB1_Green = 1'b0; 
+    assign RGB1_Blue  = 1'b0; 
+    assign RGB2_Red   = 1'b0; 
+    assign RGB2_Green = 1'b0; 
+    assign RGB2_Blue  = 1'b0; 
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/nexys4/system_create.tcl

@@ -0,0 +1,246 @@
+
+# path where project will be created
+set project_path [pwd]
+set script_path [file dirname [file normalize [info script]]]
+
+# global settings
+set project_name    "system"
+set project_part    "xc7a100tcsg324-1"
+set testbench_top   "mfp_testbench"
+
+# source files path
+set rtl_path $project_path/../rtl
+set tb_path  $project_path/../tb
+
+# project local settings
+set source_files [list \
+    "[file normalize "../nexys4.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_gpio_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_adc_max10.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_eic.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix_config.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix_with_loader.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_pmod_als.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_uart16550.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_busy.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_sdram.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_clock_dividers.v"]" \
+    "[file normalize "../../../system_rtl/mfp_dual_port_ram.v"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_core.v"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_core.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_handler.v"]" \
+    "[file normalize "../../../system_rtl/mfp_pmod_als_spi_receiver.v"]" \
+    "[file normalize "../../../system_rtl/mfp_priority_encoder.v"]" \
+    "[file normalize "../../../system_rtl/mfp_register.v"]" \
+    "[file normalize "../../../system_rtl/mfp_seven_segment_displays.v"]" \
+    "[file normalize "../../../system_rtl/mfp_srec_parser_to_ahb_lite_bridge.v"]" \
+    "[file normalize "../../../system_rtl/mfp_srec_parser.v"]" \
+    "[file normalize "../../../system_rtl/mfp_switch_and_button_debouncers.v"]" \
+    "[file normalize "../../../system_rtl/mfp_system.v"]" \
+    "[file normalize "../../../system_rtl/mfp_uart_loader.v"]" \
+    "[file normalize "../../../system_rtl/mfp_uart_receiver.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/raminfr.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_defines.vh"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_receiver.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_regs.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_rfifo.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_sync_flops.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_tfifo.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_transmitter.v"]" \
+    "[file normalize "../../../core/dataram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/d_wsram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/i_wsram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/m14k_alu_dsp_stub.v"]" \
+    "[file normalize "../../../core/m14k_alu_shft_32bit.v"]" \
+    "[file normalize "../../../core/m14k_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_biu.v"]" \
+    "[file normalize "../../../core/m14k_cache_cmp.v"]" \
+    "[file normalize "../../../core/m14k_cache_mux.v"]" \
+    "[file normalize "../../../core/m14k_cdmm_ctl.v"]" \
+    "[file normalize "../../../core/m14k_cdmm_mpustub.v"]" \
+    "[file normalize "../../../core/m14k_cdmmstub.v"]" \
+    "[file normalize "../../../core/m14k_cdmm.v"]" \
+    "[file normalize "../../../core/m14k_clockandlatch.v"]" \
+    "[file normalize "../../../core/m14k_clock_buf.v"]" \
+    "[file normalize "../../../core/m14k_clock_nogate.v"]" \
+    "[file normalize "../../../core/m14k_clockxnorgate.v"]" \
+    "[file normalize "../../../core/m14k_config.vh"]" \
+    "[file normalize "../../../core/m14k_const.vh"]" \
+    "[file normalize "../../../core/m14k_cop1_stub.v"]" \
+    "[file normalize "../../../core/m14k_cop2_stub.v"]" \
+    "[file normalize "../../../core/m14k_core.v"]" \
+    "[file normalize "../../../core/m14k_cp1_stub.v"]" \
+    "[file normalize "../../../core/m14k_cp2_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpu.v"]" \
+    "[file normalize "../../../core/m14k_cpz_antitamper_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_eicoffset_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_guest_srs1.v"]" \
+    "[file normalize "../../../core/m14k_cpz_guest_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_pc_top.v"]" \
+    "[file normalize "../../../core/m14k_cpz_pc.v"]" \
+    "[file normalize "../../../core/m14k_cpz_prid.v"]" \
+    "[file normalize "../../../core/m14k_cpz_root_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_sps_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_srs1.v"]" \
+    "[file normalize "../../../core/m14k_cpz.v"]" \
+    "[file normalize "../../../core/m14k_cpz_watch_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_scanio_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_tpl.v"]" \
+    "[file normalize "../../../core/m14k_dc_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_dcc_fb.v"]" \
+    "[file normalize "../../../core/m14k_dcc_mb_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_parity_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_spmb_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_spstub.v"]" \
+    "[file normalize "../../../core/m14k_dcc.v"]" \
+    "[file normalize "../../../core/m14k_dc.v"]" \
+    "[file normalize "../../../core/m14k_dsp_const.vh"]" \
+    "[file normalize "../../../core/m14k_dspram_ext_stub.v"]" \
+    "[file normalize "../../../core/m14k_edp_add_simple.v"]" \
+    "[file normalize "../../../core/m14k_edp_buf_misc_pro.v"]" \
+    "[file normalize "../../../core/m14k_edp_buf_misc.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz_16b.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz_4b.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz.v"]" \
+    "[file normalize "../../../core/m14k_edp.v"]" \
+    "[file normalize "../../../core/m14k_ejt_and2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_area.v"]" \
+    "[file normalize "../../../core/m14k_ejt_async_rec.v"]" \
+    "[file normalize "../../../core/m14k_ejt_async_snd.v"]" \
+    "[file normalize "../../../core/m14k_ejt_brk21.v"]" \
+    "[file normalize "../../../core/m14k_ejt_bus32mux2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_dbrk.v"]" \
+    "[file normalize "../../../core/m14k_ejt_fifo_1r1w_stub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_gate.v"]" \
+    "[file normalize "../../../core/m14k_ejt_ibrk.v"]" \
+    "[file normalize "../../../core/m14k_ejt_mux2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_pdttcb_stub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_dasamstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_dasam.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_fdcstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_fdc.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_pcsamstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_pcsam.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tck.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tripsync.v"]" \
+    "[file normalize "../../../core/m14k_ejt.v"]" \
+    "[file normalize "../../../core/m14k_fpuclk1_nogate.v"]" \
+    "[file normalize "../../../core/m14k_gf_mux2.v"]" \
+    "[file normalize "../../../core/m14k_glue.v"]" \
+    "[file normalize "../../../core/m14k_ic_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_icc_mb_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_parity_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_spmb_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_spstub.v"]" \
+    "[file normalize "../../../core/m14k_icc_umips_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc.v"]" \
+    "[file normalize "../../../core/m14k_ic.v"]" \
+    "[file normalize "../../../core/m14k_ispram_ext_stub.v"]" \
+    "[file normalize "../../../core/m14k_mdl_add_simple.v"]" \
+    "[file normalize "../../../core/m14k_mdl_ctl.v"]" \
+    "[file normalize "../../../core/m14k_mdl_dp.v"]" \
+    "[file normalize "../../../core/m14k_mdl.v"]" \
+    "[file normalize "../../../core/m14k_mmuc.v"]" \
+    "[file normalize "../../../core/m14k_mmu.vh"]" \
+    "[file normalize "../../../core/m14k_mpc_ctl.v"]" \
+    "[file normalize "../../../core/m14k_mpc_dec.v"]" \
+    "[file normalize "../../../core/m14k_mpc_exc.v"]" \
+    "[file normalize "../../../core/m14k_mpc.v"]" \
+    "[file normalize "../../../core/m14k_rf_reg.v"]" \
+    "[file normalize "../../../core/m14k_rf_rngc.v"]" \
+    "[file normalize "../../../core/m14k_rf_stub.v"]" \
+    "[file normalize "../../../core/m14k_siu_int_sync.v"]" \
+    "[file normalize "../../../core/m14k_siu.v"]" \
+    "[file normalize "../../../core/m14k_spram_top.v"]" \
+    "[file normalize "../../../core/m14k_tlb_collector.v"]" \
+    "[file normalize "../../../core/m14k_tlb_cpy.v"]" \
+    "[file normalize "../../../core/m14k_tlb_ctl.v"]" \
+    "[file normalize "../../../core/m14k_tlb_dtlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb_itlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb16entries.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb16.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb1entry.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb4entries.v"]" \
+    "[file normalize "../../../core/m14k_tlb_utlbentry.v"]" \
+    "[file normalize "../../../core/m14k_tlb_utlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb.v"]" \
+    "[file normalize "../../../core/m14k_top.v"]" \
+    "[file normalize "../../../core/m14k_udi_custom.v"]" \
+    "[file normalize "../../../core/m14k_udi_scanio_stub.v"]" \
+    "[file normalize "../../../core/m14k_udi_stub.v"]" \
+    "[file normalize "../../../core/mvp_cregister_c.v"]" \
+    "[file normalize "../../../core/mvp_cregister_ngc.v"]" \
+    "[file normalize "../../../core/mvp_cregister_s.v"]" \
+    "[file normalize "../../../core/mvp_cregister.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide_tlb.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide_utlb.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide.v"]" \
+    "[file normalize "../../../core/mvp_latchn.v"]" \
+    "[file normalize "../../../core/mvp_mux16.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_10.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_13.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_24.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_3.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_4.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_5.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_6.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_8.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_9.v"]" \
+    "[file normalize "../../../core/mvp_mux2.v"]" \
+    "[file normalize "../../../core/mvp_mux4.v"]" \
+    "[file normalize "../../../core/mvp_mux8.v"]" \
+    "[file normalize "../../../core/mvp_register_c.v"]" \
+    "[file normalize "../../../core/mvp_register_ngc.v"]" \
+    "[file normalize "../../../core/mvp_register_s.v"]" \
+    "[file normalize "../../../core/mvp_register.v"]" \
+    "[file normalize "../../../core/mvp_ucregister_wide.v"]" \
+    "[file normalize "../../../core/RAMB4K_S16.v"]" \
+    "[file normalize "../../../core/RAMB4K_S2.v"]" \
+    "[file normalize "../../../core/RAMB4K_S8.v"]" \
+    "[file normalize "../../../core/ram_dual_port.v"]" \
+    "[file normalize "../../../core/ram_reset_dual_port.v"]" \
+    "[file normalize "../../../core/tagram_2k2way_xilinx.v"]" \
+]
+
+set constr_files [list \
+    "[file normalize "../nexys4.xdc"]" \
+]
+
+set sim_files [list \
+    "[file normalize "../../../testbench/sdr_sdram"]" \
+    "[file normalize "../../../testbench/sdr_sdram/sdr.v"]" \
+    "[file normalize "../../../testbench/sdr_sdram/sdr_parameters.vh"]" \
+    "[file normalize "../../../testbench/mfp_testbench.v"]" \
+    "[file normalize "../../../testbench/mfp_uart_testbench.v"]" \
+]
+
+# create project
+create_project $project_name $project_path -part $project_part -force
+
+# fill 'sources_1' fileset
+if {[info exists source_files]} {
+    add_files -norecurse -fileset [get_filesets sources_1] $source_files
+}
+
+# fill 'constrs_1' fileset
+if {[info exists constr_files]} {
+    add_files -norecurse -fileset [get_filesets constrs_1] $constr_files
+}
+
+# fill 'sim_1' fileset
+if {[info exists sim_files]} {
+    set obj [get_filesets sim_1]
+    add_files -norecurse -fileset $obj $sim_files
+    set_property top $testbench_top $obj
+}
+
+# define macros VIVADO_SYNTHESIS
+set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define VIVADO_SYNTHESIS} -objects [get_runs synth_1]
+
+puts "INFO: Project created:$project_name"

MIPSfpga_mipsfpga-plus/boards/nexys4/system_load.tcl

@@ -0,0 +1,21 @@
+
+set project_name    "system"
+set hw_device       "xc7a100t_0"
+
+open_project "$project_name.xpr"; # open Vivado project
+open_hw;                          # open the Hardware Manager
+connect_hw_server;                # open a connection to a hardware server
+open_hw_target;                   # connect to the board
+
+# set a file to be programmed
+set_property PROGRAM.FILE "$project_name.bit" [get_hw_devices $hw_device];
+
+# chip programming
+program_hw_devices [get_hw_devices $hw_device]
+#refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $hw_device] 0]
+
+# connections and project closing
+close_hw_target
+disconnect_hw_server
+close_hw
+close_project

MIPSfpga_mipsfpga-plus/boards/nexys4/system_synth.tcl

@@ -0,0 +1,19 @@
+
+set project_name  "system"
+set synth_task    "synth_1"
+set impl_task     "impl_1"
+set timing_report "timing_1"
+
+open_project "$project_name.xpr"
+
+# run synthesis
+launch_runs $synth_task
+wait_on_run -verbose $synth_task
+
+# run implementation
+launch_runs $impl_task
+wait_on_run -verbose $impl_task
+
+# write bitstream
+open_run $impl_task -name $impl_task
+write_bitstream "$project_name.bit"

MIPSfpga_mipsfpga-plus/boards/nexys4_ddr/nexys4_ddr.v

@@ -0,0 +1,158 @@
+`include "mfp_ahb_lite_matrix_config.vh"
+
+module nexys4_ddr
+(
+    input         CLK100MHZ,
+    input         CPU_RESETN,
+
+    input         BTNC,
+    input         BTNU,
+    input         BTNL,
+    input         BTNR,
+    input         BTND,
+
+    input  [15:0] SW, 
+
+    output [15:0] LED,
+
+    output        LED16_B,
+    output        LED16_G,
+    output        LED16_R,
+    output        LED17_B,
+    output        LED17_G,
+    output        LED17_R,
+
+    output        CA,
+    output        CB,
+    output        CC,
+    output        CD,
+    output        CE,
+    output        CF,
+    output        CG,
+    output        DP,
+
+    output [ 7:0] AN,
+
+    inout  [12:1] JA,
+    inout  [12:1] JB,
+
+    input         UART_TXD_IN
+);
+
+    wire clk;
+
+    `define MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+
+    wire       muxed_clk;
+    wire [1:0] sw_db;
+
+    mfp_multi_switch_or_button_sync_and_debouncer
+    # (.WIDTH (2))
+    mfp_multi_switch_or_button_sync_and_debouncer
+    (   
+        .clk    ( CLK100MHZ ),
+        .sw_in  ( SW [1:0]  ),
+        .sw_out ( sw_db     )
+    );
+
+    mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz 
+    mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz
+    (
+        .clki    ( CLK100MHZ ),
+        .sel_lo  ( sw_db [0] ),
+        .sel_mid ( sw_db [1] ),
+        .clko    ( muxed_clk )
+    );
+
+    BUFG BUFG_slow_clk (.O ( clk ), .I ( muxed_clk ));
+
+    `else
+
+    clk_wiz_0 clk_wiz_0 (.clk_in1 (CLK100MHZ), .clk_out1 (clk));
+
+    `endif
+
+    wire [`MFP_N_SWITCHES          - 1:0] IO_Switches;
+    wire [`MFP_N_BUTTONS           - 1:0] IO_Buttons;
+    wire [`MFP_N_RED_LEDS          - 1:0] IO_RedLEDs;
+    wire [`MFP_N_GREEN_LEDS        - 1:0] IO_GreenLEDs;
+    wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
+
+    assign IO_Switches = { { `MFP_N_SWITCHES - 16 { 1'b0 } } , SW  [15:0] };
+
+    assign IO_Buttons  = { { `MFP_N_BUTTONS  -  5 { 1'b0 } } ,
+                           BTNU, BTND, BTNL, BTNC, BTNR };
+
+    `ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
+    assign LED = (sw_db == 2'b00 ? IO_RedLEDs [15:0] : IO_GreenLEDs [15:0]);
+    `else
+    assign LED = IO_RedLEDs [15:0];
+    `endif
+
+    assign LED16_B = 1'b0;
+    assign LED16_G = 1'b0;
+    assign LED16_R = 1'b0;
+    assign LED17_B = 1'b0;
+    assign LED17_G = 1'b0;
+    assign LED17_R = 1'b0;
+
+    wire [31:0] HADDR, HRDATA, HWDATA;
+    wire        HWRITE;
+
+    wire ejtag_tck_in, ejtag_tck;
+
+    IBUF IBUF           (.O ( ejtag_tck_in ), .I ( JB [4]       ));
+    BUFG BUFG_ejtag_tck (.O ( ejtag_tck    ), .I ( ejtag_tck_in ));
+
+    mfp_system mfp_system
+    (
+        .SI_ClkIn         (   clk           ),
+        .SI_Reset         ( ~ CPU_RESETN    ),
+                          
+        .HADDR            ( HADDR           ),
+        .HRDATA           ( HRDATA          ),
+        .HWDATA           ( HWDATA          ),
+        .HWRITE           ( HWRITE          ),
+
+        .EJ_TRST_N_probe  (   JB [7]        ),
+        .EJ_TDI           (   JB [2]        ),
+        .EJ_TDO           (   JB [3]        ),
+        .EJ_TMS           (   JB [1]        ),
+        .EJ_TCK           (   ejtag_tck_in  ),
+        .SI_ColdReset     ( ~ JB [8]        ),
+        .EJ_DINT          (   1'b0          ),
+
+        .IO_Switches      ( IO_Switches      ),
+        .IO_Buttons       ( IO_Buttons       ),
+        .IO_RedLEDs       ( IO_RedLEDs       ),
+        .IO_GreenLEDs     ( IO_GreenLEDs     ), 
+        .IO_7_SegmentHEX  ( IO_7_SegmentHEX  ),
+
+        .UART_RX          ( UART_TXD_IN /* Alternative: JA [10] */ ),
+        .UART_TX          ( /* TODO */      ),
+
+        .SPI_CS           (   JA [ 1]       ),
+        .SPI_SCK          (   JA [ 4]       ),
+        .SPI_SDO          (   JA [ 3]       )
+    );
+
+    assign JA [7] = 1'b0;
+
+    wire display_clock;
+
+    mfp_clock_divider_100_MHz_to_763_Hz mfp_clock_divider_100_MHz_to_763_Hz
+        (CLK100MHZ, display_clock);
+
+    mfp_multi_digit_display multi_digit_display
+    (
+        .clock          ( display_clock                  ),
+        .resetn         ( CPU_RESETN                     ),
+        .number         ( IO_7_SegmentHEX                ),
+
+        .seven_segments ( { CG, CF, CE, CD, CC, CB, CA } ),
+        .dot            ( DP                             ),
+        .anodes         ( AN                             )
+    );
+
+endmodule

MIPSfpga_mipsfpga-plus/boards/nexys4_ddr/system_create.tcl

@@ -0,0 +1,246 @@
+
+# path where project will be created
+set project_path [pwd]
+set script_path [file dirname [file normalize [info script]]]
+
+# global settings
+set project_name    "system"
+set project_part    "xc7a100tcsg324-1"
+set testbench_top   "mfp_testbench"
+
+# source files path
+set rtl_path $project_path/../rtl
+set tb_path  $project_path/../tb
+
+# project local settings
+set source_files [list \
+    "[file normalize "../nexys4_ddr.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_gpio_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_adc_max10.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_eic.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix_config.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_matrix_with_loader.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_pmod_als.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite_uart16550.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_lite.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_busy.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_sdram.v"]" \
+    "[file normalize "../../../system_rtl/mfp_ahb_ram_slave.v"]" \
+    "[file normalize "../../../system_rtl/mfp_clock_dividers.v"]" \
+    "[file normalize "../../../system_rtl/mfp_dual_port_ram.v"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_core.v"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_core.vh"]" \
+    "[file normalize "../../../system_rtl/mfp_eic_handler.v"]" \
+    "[file normalize "../../../system_rtl/mfp_pmod_als_spi_receiver.v"]" \
+    "[file normalize "../../../system_rtl/mfp_priority_encoder.v"]" \
+    "[file normalize "../../../system_rtl/mfp_register.v"]" \
+    "[file normalize "../../../system_rtl/mfp_seven_segment_displays.v"]" \
+    "[file normalize "../../../system_rtl/mfp_srec_parser_to_ahb_lite_bridge.v"]" \
+    "[file normalize "../../../system_rtl/mfp_srec_parser.v"]" \
+    "[file normalize "../../../system_rtl/mfp_switch_and_button_debouncers.v"]" \
+    "[file normalize "../../../system_rtl/mfp_system.v"]" \
+    "[file normalize "../../../system_rtl/mfp_uart_loader.v"]" \
+    "[file normalize "../../../system_rtl/mfp_uart_receiver.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/raminfr.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_defines.vh"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_receiver.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_regs.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_rfifo.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_sync_flops.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_tfifo.v"]" \
+    "[file normalize "../../../system_rtl/uart16550/uart_transmitter.v"]" \
+    "[file normalize "../../../core/dataram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/d_wsram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/i_wsram_2k2way_xilinx.v"]" \
+    "[file normalize "../../../core/m14k_alu_dsp_stub.v"]" \
+    "[file normalize "../../../core/m14k_alu_shft_32bit.v"]" \
+    "[file normalize "../../../core/m14k_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_biu.v"]" \
+    "[file normalize "../../../core/m14k_cache_cmp.v"]" \
+    "[file normalize "../../../core/m14k_cache_mux.v"]" \
+    "[file normalize "../../../core/m14k_cdmm_ctl.v"]" \
+    "[file normalize "../../../core/m14k_cdmm_mpustub.v"]" \
+    "[file normalize "../../../core/m14k_cdmmstub.v"]" \
+    "[file normalize "../../../core/m14k_cdmm.v"]" \
+    "[file normalize "../../../core/m14k_clockandlatch.v"]" \
+    "[file normalize "../../../core/m14k_clock_buf.v"]" \
+    "[file normalize "../../../core/m14k_clock_nogate.v"]" \
+    "[file normalize "../../../core/m14k_clockxnorgate.v"]" \
+    "[file normalize "../../../core/m14k_config.vh"]" \
+    "[file normalize "../../../core/m14k_const.vh"]" \
+    "[file normalize "../../../core/m14k_cop1_stub.v"]" \
+    "[file normalize "../../../core/m14k_cop2_stub.v"]" \
+    "[file normalize "../../../core/m14k_core.v"]" \
+    "[file normalize "../../../core/m14k_cp1_stub.v"]" \
+    "[file normalize "../../../core/m14k_cp2_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpu.v"]" \
+    "[file normalize "../../../core/m14k_cpz_antitamper_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_eicoffset_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_guest_srs1.v"]" \
+    "[file normalize "../../../core/m14k_cpz_guest_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_pc_top.v"]" \
+    "[file normalize "../../../core/m14k_cpz_pc.v"]" \
+    "[file normalize "../../../core/m14k_cpz_prid.v"]" \
+    "[file normalize "../../../core/m14k_cpz_root_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_sps_stub.v"]" \
+    "[file normalize "../../../core/m14k_cpz_srs1.v"]" \
+    "[file normalize "../../../core/m14k_cpz.v"]" \
+    "[file normalize "../../../core/m14k_cpz_watch_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_scanio_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_stub.v"]" \
+    "[file normalize "../../../core/m14k_cscramble_tpl.v"]" \
+    "[file normalize "../../../core/m14k_dc_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_dcc_fb.v"]" \
+    "[file normalize "../../../core/m14k_dcc_mb_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_parity_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_spmb_stub.v"]" \
+    "[file normalize "../../../core/m14k_dcc_spstub.v"]" \
+    "[file normalize "../../../core/m14k_dcc.v"]" \
+    "[file normalize "../../../core/m14k_dc.v"]" \
+    "[file normalize "../../../core/m14k_dsp_const.vh"]" \
+    "[file normalize "../../../core/m14k_dspram_ext_stub.v"]" \
+    "[file normalize "../../../core/m14k_edp_add_simple.v"]" \
+    "[file normalize "../../../core/m14k_edp_buf_misc_pro.v"]" \
+    "[file normalize "../../../core/m14k_edp_buf_misc.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz_16b.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz_4b.v"]" \
+    "[file normalize "../../../core/m14k_edp_clz.v"]" \
+    "[file normalize "../../../core/m14k_edp.v"]" \
+    "[file normalize "../../../core/m14k_ejt_and2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_area.v"]" \
+    "[file normalize "../../../core/m14k_ejt_async_rec.v"]" \
+    "[file normalize "../../../core/m14k_ejt_async_snd.v"]" \
+    "[file normalize "../../../core/m14k_ejt_brk21.v"]" \
+    "[file normalize "../../../core/m14k_ejt_bus32mux2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_dbrk.v"]" \
+    "[file normalize "../../../core/m14k_ejt_fifo_1r1w_stub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_gate.v"]" \
+    "[file normalize "../../../core/m14k_ejt_ibrk.v"]" \
+    "[file normalize "../../../core/m14k_ejt_mux2.v"]" \
+    "[file normalize "../../../core/m14k_ejt_pdttcb_stub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_dasamstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_dasam.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_fdcstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_fdc.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_pcsamstub.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap_pcsam.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tap.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tck.v"]" \
+    "[file normalize "../../../core/m14k_ejt_tripsync.v"]" \
+    "[file normalize "../../../core/m14k_ejt.v"]" \
+    "[file normalize "../../../core/m14k_fpuclk1_nogate.v"]" \
+    "[file normalize "../../../core/m14k_gf_mux2.v"]" \
+    "[file normalize "../../../core/m14k_glue.v"]" \
+    "[file normalize "../../../core/m14k_ic_bistctl.v"]" \
+    "[file normalize "../../../core/m14k_icc_mb_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_parity_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_spmb_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc_spstub.v"]" \
+    "[file normalize "../../../core/m14k_icc_umips_stub.v"]" \
+    "[file normalize "../../../core/m14k_icc.v"]" \
+    "[file normalize "../../../core/m14k_ic.v"]" \
+    "[file normalize "../../../core/m14k_ispram_ext_stub.v"]" \
+    "[file normalize "../../../core/m14k_mdl_add_simple.v"]" \
+    "[file normalize "../../../core/m14k_mdl_ctl.v"]" \
+    "[file normalize "../../../core/m14k_mdl_dp.v"]" \
+    "[file normalize "../../../core/m14k_mdl.v"]" \
+    "[file normalize "../../../core/m14k_mmuc.v"]" \
+    "[file normalize "../../../core/m14k_mmu.vh"]" \
+    "[file normalize "../../../core/m14k_mpc_ctl.v"]" \
+    "[file normalize "../../../core/m14k_mpc_dec.v"]" \
+    "[file normalize "../../../core/m14k_mpc_exc.v"]" \
+    "[file normalize "../../../core/m14k_mpc.v"]" \
+    "[file normalize "../../../core/m14k_rf_reg.v"]" \
+    "[file normalize "../../../core/m14k_rf_rngc.v"]" \
+    "[file normalize "../../../core/m14k_rf_stub.v"]" \
+    "[file normalize "../../../core/m14k_siu_int_sync.v"]" \
+    "[file normalize "../../../core/m14k_siu.v"]" \
+    "[file normalize "../../../core/m14k_spram_top.v"]" \
+    "[file normalize "../../../core/m14k_tlb_collector.v"]" \
+    "[file normalize "../../../core/m14k_tlb_cpy.v"]" \
+    "[file normalize "../../../core/m14k_tlb_ctl.v"]" \
+    "[file normalize "../../../core/m14k_tlb_dtlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb_itlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb16entries.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb16.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb1entry.v"]" \
+    "[file normalize "../../../core/m14k_tlb_jtlb4entries.v"]" \
+    "[file normalize "../../../core/m14k_tlb_utlbentry.v"]" \
+    "[file normalize "../../../core/m14k_tlb_utlb.v"]" \
+    "[file normalize "../../../core/m14k_tlb.v"]" \
+    "[file normalize "../../../core/m14k_top.v"]" \
+    "[file normalize "../../../core/m14k_udi_mipsfpga_ai.v"]" \
+    "[file normalize "../../../core/m14k_udi_scanio_stub.v"]" \
+    "[file normalize "../../../core/m14k_udi_stub.v"]" \
+    "[file normalize "../../../core/mvp_cregister_c.v"]" \
+    "[file normalize "../../../core/mvp_cregister_ngc.v"]" \
+    "[file normalize "../../../core/mvp_cregister_s.v"]" \
+    "[file normalize "../../../core/mvp_cregister.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide_tlb.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide_utlb.v"]" \
+    "[file normalize "../../../core/mvp_cregister_wide.v"]" \
+    "[file normalize "../../../core/mvp_latchn.v"]" \
+    "[file normalize "../../../core/mvp_mux16.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_10.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_13.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_24.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_3.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_4.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_5.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_6.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_8.v"]" \
+    "[file normalize "../../../core/mvp_mux1hot_9.v"]" \
+    "[file normalize "../../../core/mvp_mux2.v"]" \
+    "[file normalize "../../../core/mvp_mux4.v"]" \
+    "[file normalize "../../../core/mvp_mux8.v"]" \
+    "[file normalize "../../../core/mvp_register_c.v"]" \
+    "[file normalize "../../../core/mvp_register_ngc.v"]" \
+    "[file normalize "../../../core/mvp_register_s.v"]" \
+    "[file normalize "../../../core/mvp_register.v"]" \
+    "[file normalize "../../../core/mvp_ucregister_wide.v"]" \
+    "[file normalize "../../../core/RAMB4K_S16.v"]" \
+    "[file normalize "../../../core/RAMB4K_S2.v"]" \
+    "[file normalize "../../../core/RAMB4K_S8.v"]" \
+    "[file normalize "../../../core/ram_dual_port.v"]" \
+    "[file normalize "../../../core/ram_reset_dual_port.v"]" \
+    "[file normalize "../../../core/tagram_2k2way_xilinx.v"]" \
+]
+
+set constr_files [list \
+    "[file normalize "../nexys4_ddr.xdc"]" \
+]
+
+set sim_files [list \
+    "[file normalize "../../../testbench/sdr_sdram"]" \
+    "[file normalize "../../../testbench/sdr_sdram/sdr.v"]" \
+    "[file normalize "../../../testbench/sdr_sdram/sdr_parameters.vh"]" \
+    "[file normalize "../../../testbench/mfp_testbench.v"]" \
+    "[file normalize "../../../testbench/mfp_uart_testbench.v"]" \
+]
+
+# create project
+create_project $project_name $project_path -part $project_part -force
+
+# fill 'sources_1' fileset
+if {[info exists source_files]} {
+    add_files -norecurse -fileset [get_filesets sources_1] $source_files
+}
+
+# fill 'constrs_1' fileset
+if {[info exists constr_files]} {
+    add_files -norecurse -fileset [get_filesets constrs_1] $constr_files
+}
+
+# fill 'sim_1' fileset
+if {[info exists sim_files]} {
+    set obj [get_filesets sim_1]
+    add_files -norecurse -fileset $obj $sim_files
+    set_property top $testbench_top $obj
+}
+
+# define macros VIVADO_SYNTHESIS
+set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-verilog_define VIVADO_SYNTHESIS} -objects [get_runs synth_1]
+
+puts "INFO: Project created:$project_name"

MIPSfpga_mipsfpga-plus/boards/nexys4_ddr/system_load.tcl

@@ -0,0 +1,21 @@
+
+set project_name    "system"
+set hw_device       "xc7a100t_0"
+
+open_project "$project_name.xpr"; # open Vivado project
+open_hw;                          # open the Hardware Manager
+connect_hw_server;                # open a connection to a hardware server
+open_hw_target;                   # connect to the board
+
+# set a file to be programmed
+set_property PROGRAM.FILE "$project_name.bit" [get_hw_devices $hw_device];
+
+# chip programming
+program_hw_devices [get_hw_devices $hw_device]
+#refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $hw_device] 0]
+
+# connections and project closing
+close_hw_target
+disconnect_hw_server
+close_hw
+close_project

MIPSfpga_mipsfpga-plus/boards/nexys4_ddr/system_synth.tcl

@@ -0,0 +1,19 @@
+
+set project_name  "system"
+set synth_task    "synth_1"
+set impl_task     "impl_1"
+set timing_report "timing_1"
+
+open_project "$project_name.xpr"
+
+# run synthesis
+launch_runs $synth_task
+wait_on_run -verbose $synth_task
+
+# run implementation
+launch_runs $impl_task
+wait_on_run -verbose $impl_task
+
+# write bitstream
+open_run $impl_task -name $impl_task
+write_bitstream "$project_name.bit"

MIPSfpga_mipsfpga-plus/documentation/figure_generator/generator.cpp

@@ -0,0 +1,336 @@
+#include "utilities.cpp"
+
+struct board_descriptor
+{
+    char const * module_name;
+    int          testbench;
+    int          clock_frequency;
+    int          altera;
+    int          static_7_segment_display;
+    int          dynamic_7_segment_display;
+    char const * description;
+}
+boards [] =
+{
+    { "mfp_testbench" , 1 ,   0 , 0 , 0 , 0 , "Testbench for RTL simulation"                                                                       },
+    { "nexys4_ddr"    , 0 , 100 , 0 , 0 , 1 , "Wrapper for Digilent Nexys 4 DDR board with Xilinx Artix-7 FPGA"                                    },
+    { "de0_cv"        , 0 ,  50 , 1 , 1 , 0 , "Wrapper for Terasic DE0-CV board with Altera Cyclone V FPGA"                                        }, 
+    { "nexys4_ddr"    , 0 , 100 , 0 , 0 , 1 , "Wrapper for Digilent Nexys 4 DDR board with Xilinx Artix-7 FPGA (without 7-segment display module)" },
+    { "de0_cv"        , 0 ,  50 , 1 , 1 , 0 , "Wrapper for Terasic DE0-CV board with Altera Cyclone V FPGA (without 7-segment display module)"     }, 
+    { "de0_nano"      , 0 ,  50 , 1 , 0 , 0 , "Wrapper for Terasic DE0-Nano board with Altera Cyclone IV FPGA"                                     },
+    { "basys3"        , 0 , 100 , 0 , 0 , 1 , "Wrapper for Digilent Basys 3 board with Xilinx Artix-7 FPGA"                                        },
+    { "marsohod3"     , 0 ,  50 , 1 , 0 , 0 , "Wrapper for Marsohod 3 board with Altera MAX10 FPGA"                                                }
+};
+
+int i_board;
+int narrow_write_support;
+int switchable_clock;
+int light_sensor;
+int serial_loader;
+int without_7_segment_display;
+
+void print_hierarchy ()
+{
+    current_module_is_already_described = 0;
+
+    board_descriptor * b = & boards [i_board];
+
+    char buf [BUFSIZ];
+
+    sprintf
+    (
+        buf,
+        "../run/hierarchy_%s%s%s%s%s%s%s.html",
+        b -> module_name,
+        narrow_write_support        ? "__narrow_write_support" : "",
+        light_sensor                ? "__light_sensor"         : "", 
+        serial_loader               ? "__serial_loader"        : "",
+        switchable_clock            ? "__switchable_clock"     : "", 
+        without_7_segment_display   ? "__wo_7_segment_display" : "", 
+        current_module_name != NULL ? "__"                     : "",  
+        current_module_name != NULL ? current_module_name      : ""
+    );
+
+    freopen (buf, "w", stdout);
+
+    char const * file_url = NULL;
+
+    if (! b -> testbench)
+    {
+        sprintf (buf, "boards/%s/%s.v",
+            b -> module_name,
+            b -> module_name);
+
+        file_url = buf;
+    }
+
+    header
+
+    module
+    (
+        file_url,
+        b -> module_name,
+        NULL,
+        b -> description
+    );
+
+        if (   switchable_clock
+            || 
+                  ! without_7_segment_display
+               && (b -> static_7_segment_display || b -> dynamic_7_segment_display))
+        {
+            group
+            
+            if (switchable_clock)
+            {
+                group
+            
+                    module ("mfp_switch_and_button_debouncers.v", "mfp_multi_switch_or_button_sync_and_debouncer");
+                        leaf ("mfp_switch_and_button_debouncers.v", "mfp_switch_or_button_sync_and_debouncer", NULL,
+                            "Debouncer for the switches that control the clock");
+                    _module
+            
+                    vbreak
+            
+                if (b -> clock_frequency == 50)
+                    module ("mfp_clock_dividers.v", "mfp_clock_divider_50_MHz_to_25_MHz_12_Hz_0_75_Hz");
+                else if (b -> clock_frequency == 100)
+                    module ("mfp_clock_dividers.v", "mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz");
+            
+                        leaf ("mfp_clock_dividers.v", "mfp_clock_divider");
+            
+                    _module
+            
+                    vbreak
+            
+                if (b -> altera)
+                    leaf (NULL, "global", "gclk", "Needed for the divided clock");
+                else
+                    leaf (NULL, "BUFG", NULL, "Needed for the divided clock");
+            
+                _group
+            }
+            
+            if (   ! without_7_segment_display
+                && (b -> static_7_segment_display || b -> dynamic_7_segment_display))
+            {
+                hbreak
+
+                if (b -> static_7_segment_display)
+                {
+                    group
+                    leaf ("mfp_seven_segment_displays.v", "mfp_single_digit_seven_segment_display", "digit_0");
+                    vbreak
+                    leaf ("mfp_seven_segment_displays.v", "mfp_single_digit_seven_segment_display", "digit_1");
+                    vbreak
+                    leaf ("mfp_seven_segment_displays.v", "mfp_single_digit_seven_segment_display", "digit_2");
+                    vbreak
+                    ellipsis
+                    _group
+                }
+                
+                if (b -> dynamic_7_segment_display)
+                {
+                    group
+                    leaf ("mfp_clock_dividers.v", "mfp_clock_divider_100_MHz_to_763_Hz", NULL, "Clock for 7-segment display");
+                    vbreak
+                    leaf ("mfp_seven_segment_displays.v", "mfp_multi_digit_display");
+                    _group
+                }
+            }
+            
+            _group
+            
+            vbreak
+        }
+
+        module ("mfp_system.v", "mfp_system", NULL, NULL, 2 + light_sensor);
+            group
+            leaf (mipsfpga_download_instruction, "m14k_top", NULL, "The CPU core");
+            vbreak
+            leaf ("mfp_system.v", "mfp_ejtag_reset");
+            _group
+
+            hbreak
+
+            if (serial_loader)
+            {
+                module ("mfp_ahb_lite_matrix_with_loader.v", "mfp_ahb_lite_matrix_with_loader", NULL, NULL, 2);
+                    group
+                    leaf ("mfp_uart_receiver.v", "mfp_uart_receiver", NULL, "Receives data bytes from the PC via UART");
+                    vbreak
+                    leaf ("mfp_srec_parser.v", "mfp_srec_parser", NULL, "Parses data received via UART as text in Motorola S-Record format and issues transactions to fill the system memory with this data");
+                    vbreak
+                    leaf ("mfp_srec_parser_to_ahb_lite_bridge.v", "mfp_srec_parser_to_ahb_lite_bridge", NULL, "Converts the transactions from S-Record parser into AHB-Lite protocol. Also converts virtual addresses into physical using fixed mapping");
+                    _group
+
+                    hbreak
+            }
+
+            module ("mfp_ahb_lite_matrix.v", "mfp_ahb_lite_matrix" );
+
+                leaf ("mfp_ahb_lite_matrix.v", "mfp_ahb_lite_decoder" );
+                vbreak
+
+                module ("mfp_ahb_ram_slave.v", "mfp_ahb_ram_slave", "reset_ram");
+
+                    if (narrow_write_support)
+                    {
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram", "i0");
+                        vbreak
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram", "i1");
+                        vbreak
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram", "i2");
+                        vbreak
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram", "i3");
+                    }
+                    else
+                    {
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram");
+                    }
+                _module
+            
+                vbreak
+
+                module ("mfp_ahb_ram_slave.v", "mfp_ahb_ram_slave", "ram");
+                    if (narrow_write_support)
+                    {
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram", "i0");
+                        vbreak
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram", "i1");
+                        vbreak
+                        ellipsis
+                    }
+                    else
+                    {
+                        leaf ("mfp_dual_port_ram.v", "mfp_dual_port_ram");
+                    }
+                _module
+            
+                vbreak
+                leaf ("mfp_ahb_gpio_slave.v", "mfp_ahb_gpio_slave", "gpio");
+                vbreak
+                leaf ("mfp_ahb_lite_matrix.v", "mfp_ahb_lite_response_mux");
+
+            _module
+
+            if (serial_loader)
+                _module
+
+            if (light_sensor)
+            {
+                hbreak
+                leaf ("mfp_pmod_als_spi_receiver.v", "mfp_pmod_als_spi_receiver", NULL, "Receives data from the light sensor using a version of SPI protocol");
+            }
+
+        _module
+
+    _module
+    footer
+}
+
+//----------------------------------------------------------------------------
+
+int main ()
+{
+    if (0)
+    {
+    for (i_board              = 0; i_board < sizeof (boards) / sizeof (* boards); i_board ++)
+    for (narrow_write_support = 0; narrow_write_support <= 1; narrow_write_support ++)
+    for (switchable_clock     = 0; switchable_clock     <= 1; switchable_clock     ++)
+    for (light_sensor         = 0; light_sensor         <= 1; light_sensor         ++)
+    for (serial_loader        = 0; serial_loader        <= 1; serial_loader        ++)
+    {
+        int features =   narrow_write_support
+                       + switchable_clock + light_sensor + serial_loader;
+
+        if (    i_board == 0 && (switchable_clock + light_sensor + serial_loader) != 0
+             || i_board != 0 && narrow_write_support == 0
+             || i_board >  2 )
+        {
+            continue;
+        }
+
+        // module_names and n_module_names are extracted when current_module_name is NULL
+
+        n_module_names      = 0;
+        current_module_name = NULL;
+
+        print_hierarchy ();
+
+        for (int i = 0; i < n_module_names; i ++)
+        {
+            current_module_name = module_names [i];
+
+            if (current_module_name != NULL)
+                print_hierarchy ();
+        }
+    }
+    }
+
+    if (0)
+    {
+    // Special cases
+
+    current_module_name = NULL;
+
+    i_board              = 0;
+    narrow_write_support = 0;
+    switchable_clock     = 0;
+    light_sensor         = 0;
+    serial_loader        = 0;
+
+    print_hierarchy ();
+
+    narrow_write_support = 1;
+
+    print_hierarchy ();
+
+    light_sensor         = 1;
+    serial_loader        = 1;
+
+    print_hierarchy ();
+
+    for (i_board = 1; i_board <= 2; i_board ++)
+    {
+        narrow_write_support = 0;
+        switchable_clock     = 0;
+        light_sensor         = 0;
+        serial_loader        = 0;
+
+        print_hierarchy ();
+
+        narrow_write_support = 1;
+        print_hierarchy ();
+
+        light_sensor = 1;
+        print_hierarchy ();
+
+        serial_loader = 1;
+        print_hierarchy ();
+
+        switchable_clock = 1;
+        print_hierarchy ();
+    }
+    }
+
+    // Support for Lab YP1. Serial Loader Flow
+
+    current_module_name = NULL;
+
+    for (i_board = 3; i_board <= 4; i_board ++)
+    {
+        narrow_write_support      = 1;
+        switchable_clock          = 0;
+        light_sensor              = 0;
+        without_7_segment_display = 1;
+
+        serial_loader = 0;
+        print_hierarchy ();
+
+        serial_loader = 1;
+        print_hierarchy ();
+    }
+
+    return 0;
+}

MIPSfpga_mipsfpga-plus/documentation/figure_generator/utilities.cpp

@@ -0,0 +1,143 @@
+# include "stdio.h"
+# include "string.h"
+
+char const mipsfpga_plus_github_location [] = "http://github.com/MIPSfpga/mipsfpga-plus/blob/master";
+char const mipsfpga_download_instruction [] = "http://www.silicon-russia.com/2015/12/11/mipsfpga-download-instructions";
+
+const char * module_names [1000];
+int          n_module_names;
+
+const char * current_module_name;
+int          current_module_is_already_described;
+
+int level = 0;
+
+//----------------------------------------------------------------------------
+
+#define p         printf
+
+#define header    p ("<font size=2 face=\"Verdana, Arial, Helvetica, sans_serif\">\n");
+#define footer    p ("</font>\n");
+
+#define tr        p ("<tr>\n");
+#define td        p ("<td valign=top>\n");
+#define _tr       p ("</tr>\n");
+#define _td       p ("</td>\n");
+#define hbreak    _td td
+#define vbreak    _td _tr tr td
+#define ellipsis  p (". . . . . . . . . .<br><br>\n");
+
+//----------------------------------------------------------------------------
+
+void module
+(
+    const char * file_url      = NULL,
+    const char * module_name   = NULL,
+    const char * instance_name = NULL,
+    const char * description   = NULL,
+    int          colspan       = 1
+)
+{
+    level ++;
+
+    if (current_module_name == NULL && module_name != NULL)
+        module_names [n_module_names ++] = module_name;
+
+    int the_module_is_current
+
+        =    current_module_name != NULL
+          && module_name         != NULL
+          && strcmp (module_name, current_module_name) == 0;
+
+    // if (! the_module_is_current || current_module_is_already_described)
+    //     description = NULL;
+
+    if (the_module_is_current)
+        current_module_is_already_described = 1;
+
+    char buf [BUFSIZ];
+
+    if (file_url != NULL && strstr (file_url, "http") == NULL)
+    {
+        sprintf (buf, "%s/%s", mipsfpga_plus_github_location, file_url);
+        file_url = buf;
+    }
+
+    p ("<table width=%s", level == 1 ? "1000" : "100%%");
+
+    char const * level_colors []
+        = { "A3FFD1", "A3FFFF", "A3D1FF" };
+
+    p (" bgcolor=#%s", the_module_is_current ? "FFFF29"
+        : level_colors [level % (sizeof (level_colors) / sizeof (* level_colors))]);
+        
+    if (module_name != NULL || instance_name != NULL || description != NULL) p (" border=2");
+
+    p (" cellpadding=10 cellspacing=0 rules=none>\n");
+
+    if (module_name != NULL || instance_name != NULL || description != NULL)
+    {
+        // p ("<tr><td valign=top nowrap=nowrap");
+        p ("<tr><td valign=top");
+        
+        if (colspan != 1)
+            p (" colspan=%d", colspan);
+        
+        p (">\n");
+
+        if (module_name != NULL || instance_name != NULL) p ("<b>");
+        
+        if (module_name != NULL)
+        {
+            if (file_url != NULL) p ("<a href=\"%s\">", file_url);
+        
+            p ("%s", module_name);
+        
+            if (file_url != NULL) p ("</a>");
+        }
+        
+        if (module_name != NULL && instance_name != NULL) p (" ");
+        
+        if (instance_name != NULL) p ("%s", instance_name);
+        
+        if (module_name != NULL || instance_name != NULL) p ("</b>");
+        
+        if ((module_name != NULL || instance_name != NULL) && description != NULL) p ("<br><br>\n");
+        
+        if (description != NULL) p ("%s", description);
+        
+        p ("\n</td></tr>\n");
+    }
+
+    p ("<tr><td valign=top>\n");
+
+    colspan = 1;
+}
+
+//----------------------------------------------------------------------------
+
+#define _module  p ("</td></tr>\n</table>\n"), level --;
+
+#define group   module ();
+#define _group  _module
+
+//----------------------------------------------------------------------------
+
+void leaf
+(
+    const char * file_url      = NULL,
+    const char * module_name   = NULL,
+    const char * instance_name = NULL,
+    const char * description   = NULL
+)
+{
+    module
+    (
+        file_url,
+        module_name,
+        instance_name,
+        description
+    );
+
+    _module
+}

MIPSfpga_mipsfpga-plus/documentation/html_labs_for_blog/convert_html_to_wordpress.c

@@ -0,0 +1,78 @@
+#include <stdio.h>
+
+/*
+
+<pre>
+<font face="Courier"><pre>
+
+</pre>
+</pre></font>
+
+<p><big><big><b>
+<h2>
+
+<p><big><b>
+<h3>
+
+<p><b>
+<h4>
+
+</b></big></big></p>
+</h2>
+
+</b></big></p>
+</h3>
+
+</b></p>
+</h4>
+
+
+
+
+final_rename \<pre\> \<font face=\"Courier\"\>\<pre\>
+
+final_rename \<\/pre\> \<\/pre\>\<font face=\"Courier\"\>
+
+final_rename \<p\>\<big\>\<big\>\<b\> \<h2\>
+
+final_rename \<p\>\<big\>\<b\> \<h3\>
+
+final_rename \<p\>\<b\> \<h4\>
+
+final_rename \<\/b\>\<\/big\>\<\/big\>\<\/p\> \<\/h2\>
+
+final_rename \<\/b\>\<\/big\>\<\/p\> \<\/h3\>
+
+final_rename \<\/b\>\<\/p\> \<\/h4\>
+
+*/
+
+int main ()
+{
+    int c, pc = 0, ppc = 0, pppc = 0, ppppc = 0, mode = 0;
+
+    while ((c = getchar ()) != EOF)
+    {
+        if (      ppc == '<' &&               pc == 'p' &&  c == '>')
+            mode = 1;
+        else if (pppc == '<' && ppc == '/' && pc == 'p' && c == '>')
+            mode = 0;
+
+        if (      pppc == '<' &&                ppc == 'l' && pc == 'i' && c == '>')
+            mode = 1;
+        else if (ppppc == '<' && pppc == '/' && ppc == 'l' && pc == 'i' && c == '>')
+            mode = 0;
+
+        if (mode && c == '\n')
+            c = ' ';
+        else if (c == '\r')
+            continue;
+            
+        putchar (c);
+    
+        ppppc = pppc;
+        pppc  = ppc;
+        ppc   = pc;
+        pc    = c;
+    }
+}

MIPSfpga_mipsfpga-plus/exercises/module_to_use/hc_sr04_ultrasonic_distance_sensor.v

@@ -0,0 +1,122 @@
+// Note active positive reset
+
+module hc_sr04_ultrasonic_distance_sensor
+# (
+    parameter clk_frequency           = 50000000,
+              relative_distance_width = 8
+)
+(
+    input      clk,
+    input      reset,
+    output reg trig,
+    input      echo,
+
+    output reg [relative_distance_width - 1:0] relative_distance
+);
+
+    // Datasheet: http://www.micropik.com/PDF/HCSR04.pdf
+    // Time is measured in clk cycles unless noted otherwise
+
+    localparam
+
+        speed_of_sound_meters_per_second   = 343,
+        max_range_in_centimeters           = 400,  // From datasheet
+
+        measurement_cycle_in_milliseconds  = 200,  // From datasheet min is 60
+        trig_time_in_microseconds          = 10,   // From datasheet
+
+        measurement_cycle_time
+            = measurement_cycle_in_milliseconds * (clk_frequency / 1000),
+
+        trig_time
+            = trig_time_in_microseconds * (clk_frequency / 1000000),
+        
+        echo_clk_cycles_per_centimeters
+        
+            =   clk_frequency
+              * 2    // Sound wave goes 2 ways
+              / speed_of_sound_meters_per_second
+              / 100, // Number of centimeters in meter
+              
+        max_echo_time
+            = max_range_in_centimeters * echo_clk_cycles_per_centimeters,
+
+        // To accomodate values up to measurement_cycle_time - 1
+        trig_cnt_width = $clog2 (measurement_cycle_time),
+        
+        // To accomodate values up to max_echo_time
+        echo_cnt_width = $clog2 (max_echo_time + 1);
+
+    `ifndef SIMULATION_ONLY
+    
+    initial
+    begin
+        $display ( "speed_of_sound_meters_per_second  : %0d", speed_of_sound_meters_per_second  );
+        $display ( "max_range_in_centimeters          : %0d", max_range_in_centimeters          );
+        $display ( "measurement_cycle_in_milliseconds : %0d", measurement_cycle_in_milliseconds );
+        $display ( "trig_time_in_microseconds         : %0d", trig_time_in_microseconds         );
+        $display ( "measurement_cycle_time            : %0d", measurement_cycle_time            );
+        $display ( "trig_time                         : %0d", trig_time                         );
+        $display ( "echo_clk_cycles_per_centimeters   : %0d", echo_clk_cycles_per_centimeters   );
+        $display ( "max_echo_time                     : %0d", max_echo_time                     );
+        $display ( "trig_cnt_width                    : %0d", trig_cnt_width                    );
+        $display ( "echo_cnt_width                    : %0d", echo_cnt_width                    );
+    end
+    
+    `endif
+
+    reg [trig_cnt_width - 1:0] trig_cnt;
+
+    always @ (posedge clk or posedge reset)
+        if (reset)
+            trig_cnt <= 0;
+        else if (trig_cnt == measurement_cycle_time - 1)
+            trig_cnt <= 0;
+        else
+            trig_cnt <= trig_cnt + 1;
+
+    // We have to wait after reset and after each measurement
+
+    always @ (posedge clk or posedge reset)
+        if (reset)
+            trig <= 0;
+        else if (trig_cnt == measurement_cycle_time - trig_time - 1)
+            trig <= 1;
+        else if (trig_cnt == measurement_cycle_time - 1)
+            trig <= 0;
+
+    reg prev_echo;
+    
+    always @ (posedge clk or posedge reset)
+        if (reset)
+            prev_echo <= 0;
+        else
+            prev_echo <= echo;
+
+    wire posedge_echo = ~ prev_echo &   echo;
+    wire negedge_echo =   prev_echo & ~ echo;
+
+    reg [echo_cnt_width - 1:0] echo_cnt;
+
+    always @ (posedge clk or posedge reset)
+        if (reset)
+        begin
+            echo_cnt          <= 0;
+            relative_distance <= 0;
+        end
+        else if (posedge_echo)
+        begin
+            echo_cnt <= 0;
+        end
+        else if (negedge_echo)
+        begin
+            relative_distance
+                <= echo_cnt [   echo_cnt_width - 1 
+                              : echo_cnt_width - relative_distance_width ];
+        end
+        else
+        begin
+            echo_cnt <= echo_cnt + 1;
+        end
+
+endmodule

MIPSfpga_mipsfpga-plus/exercises/module_to_use/m14k_udi_mipsfpga_ai.v

@@ -0,0 +1,149 @@
+//
+//          mips_start_of_legal_notice
+//          **********************************************************************
+//        
+//    Copyright (c) 2019 MIPS Tech, LLC, 300 Orchard City Dr., Suite 170, 
+//    Campbell, CA 95008 USA.  All rights reserved.
+//    This document contains information and code that is proprietary to 
+//    MIPS Tech, LLC and MIPS' affiliates, as applicable, ("MIPS").  If this 
+//    document is obtained pursuant to a MIPS Open license, the sole 
+//    licensor under such license is MIPS Tech, LLC. This document and any 
+//    information or code therein are protected by patent, copyright, 
+//    trademarks and unfair competition laws, among others, and are 
+//    distributed under a license restricting their use. MIPS has 
+//    intellectual property rights, including patents or pending patent 
+//    applications in the U.S. and in other countries, relating to the 
+//    technology embodied in the product that is described in this document. 
+//    Any distribution release of this document may include or be 
+//    accompanied by materials developed by third parties. Any copying, 
+//    reproducing, modifying or use of this information (in whole or in part) 
+//    that is not expressly permitted in writing by MIPS or an authorized 
+//    third party is strictly prohibited.  Any document provided in source 
+//    format (i.e., in a modifiable form such as in FrameMaker or 
+//    Microsoft Word format) may be subject to separate use and distribution 
+//    restrictions applicable to such document. UNDER NO CIRCUMSTANCES MAY A 
+//    DOCUMENT PROVIDED IN SOURCE FORMAT BE DISTRIBUTED TO A THIRD PARTY IN 
+//    SOURCE FORMAT WITHOUT THE EXPRESS WRITTEN PERMISSION OF, OR LICENSED 
+//    FROM, MIPS.  MIPS reserves the right to change the information or code 
+//    contained in this document to improve function, design or otherwise.  
+//    MIPS does not assume any liability arising out of the application or 
+//    use of this information, or of any error or omission in such 
+//    information. DOCUMENTATION AND CODE ARE PROVIDED "AS IS" AND ANY 
+//    WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR OTHERWISE, 
+//    INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, 
+//    FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE EXCLUDED, 
+//    EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO BE LEGALLY 
+//    INVALID IN A COMPETENT JURISDICTION. Except as expressly provided in 
+//    any written license agreement from MIPS or an authorized third party, 
+//    the furnishing or distribution of this document does not give recipient 
+//    any license to any intellectual property rights, including any patent 
+//    rights, that cover the information in this document.  
+//    Products covered by, and information or code, contained this document 
+//    are controlled by U.S. export control laws and may be subject to the 
+//    expert or import laws in other countries. The information contained 
+//    in this document shall not be exported, reexported, transferred, or 
+//    released, directly or indirectly, in violation of the law of any 
+//    country or international law, regulation, treaty, executive order, 
+//    statute, amendments or supplements thereto. Nuclear, missile, chemical 
+//    weapons, biological weapons or nuclear maritime end uses, whether 
+//    direct or indirect, are strictly prohibited.  Should a conflict arise 
+//    regarding the export, reexport, transfer, or release of the information 
+//    contained in this document, the laws of the United States of America 
+//    shall be the governing law.  
+//    U.S Government Rights - Commercial software.  Government users are 
+//    subject to the MIPS Tech, LLC standard license agreement and applicable 
+//    provisions of the FAR and its supplements.
+//    MIPS and MIPS Open are trademarks or registered trademarks of MIPS in 
+//    the United States and other countries.  All other trademarks referred 
+//    to herein are the property of their respective owners.  
+//      
+//      
+//    **********************************************************************
+//    mips_end_of_legal_notice
+//
+
+`include "m14k_const.vh"
+
+module m14k_udi_mipsfpga_ai
+(
+    input         UDI_gclk,         // Clock
+    input         UDI_greset,       // Reset
+    input         UDI_gscanenable,  // Scan enable
+
+    // Static signals
+    
+    input         UDI_endianb_e,    // Endian : 0 = little , 1 = big
+    input         UDI_kd_mode_e,    // Mode   : 0 = user   , 1 = kernel or debug
+    output        UDI_present,      // UDI module is present
+
+    // E-stage signals (in the order of their timing)
+
+    input  [31:0] UDI_ir_e,         // Instruction register
+    input         UDI_irvalid_e,    // Instruction register valid
+
+    output        UDI_ri_e,         // The instruction is illegal
+
+    input  [31:0] UDI_rs_e,         // Value of register RS from register file
+    input  [31:0] UDI_rt_e,         // Value of register RT from register file
+
+    output [ 4:0] UDI_wrreg_e,      // Register file index to write the result
+                                    // Zero index indicates don't write
+
+    input         UDI_start_e,      // Values of RS and RT valid
+
+    // M-stage signals (in the order of their timing)
+
+    output        UDI_stall_m,      // Stall the pipeline
+    output [31:0] UDI_rd_m,         // Result to write back
+
+    input         UDI_run_m,        // Qualify UDI_kill_m
+    input         UDI_kill_m,       // Kill the instruction
+
+    // Other signals
+
+    output        UDI_honor_cee,    // UDI module has local state
+
+    input  [`M14K_UDI_EXT_TOUDI_WIDTH   - 1:0]  UDI_toudi,   // External input to UDI module
+    output [`M14K_UDI_EXT_FROMUDI_WIDTH - 1:0]  UDI_fromudi  // Output from UDI module to external system
+);
+
+    assign UDI_present    = 1'b1;
+    assign UDI_wrreg_e    = UDI_ir_e [25:21];  // RS register
+    assign UDI_stall_m    = 1'b0;
+    assign UDI_honor_cee  = 1'b0;
+    assign UDI_fromudi    = { `M14K_UDI_EXT_FROMUDI_WIDTH { 1'b0 } };
+
+    wire   spc2           = ( UDI_ir_e [31:26] == 6'b011100 );
+    wire   udi            = ( UDI_ir_e [ 5: 4] == 2'b01     );
+    wire   usr_udi_vld    = ( UDI_ir_e [ 3: 1] == 3'b000    );
+
+    wire   ir_ok          = spc2 & udi & usr_udi_vld & UDI_irvalid_e;
+    assign UDI_ri_e       = ! ir_ok;
+
+    wire   run_instr      = ir_ok & UDI_start_e;
+
+    wire [15:0] imm16 = { UDI_ir_e [0], UDI_ir_e [20:6] };
+
+    wire [31:0] e_res, e_res_q;
+
+    assign e_res [ 7: 0] = UDI_rs_e [ 7: 0] * imm16 [ 3: 0];
+    assign e_res [15: 8] = UDI_rs_e [15: 8] * imm16 [ 7: 4];
+    assign e_res [23:16] = UDI_rs_e [23:16] * imm16 [11: 8];
+    assign e_res [31:24] = UDI_rs_e [31:24] * imm16 [15:12];
+
+    mvp_cregister_wide # (32) e_res_r
+    (
+        .q          ( e_res_q         ),
+        .scanenable ( UDI_gscanenable ),
+        .cond       ( run_instr       ),
+        .clk        ( UDI_gclk        ),
+        .d          ( e_res           )
+    );
+
+    wire [7:0] m_res_01 = e_res_q [15: 8] + e_res_q [ 7:0];
+    wire [7:0] m_res_23 = e_res_q [31:24] + e_res_q [23:16];
+    wire [7:0] m_res    = m_res_01 + m_res_23;
+
+    assign UDI_rd_m = { 24'b0, m_res };
+
+endmodule

MIPSfpga_mipsfpga-plus/exercises/module_to_use/pmod_als_light_sensor.v

@@ -0,0 +1,47 @@
+// Note active positive reset
+
+module pmod_als_light_sensor
+(
+    input             clk,
+    input             reset,
+    output            cs,
+    output            sck,
+    input             sdo,
+    output reg [15:0] value
+);
+
+    reg [ 8:0] cnt;
+    reg [15:0] shift;
+
+    always @ (posedge clk or posedge reset)
+    begin       
+        if (reset)
+            cnt <= 8'b100;
+        else
+            cnt <= cnt + 8'b1;
+    end
+
+    assign sck = ~ cnt [3];
+    assign cs  =   cnt [8];
+
+    wire sample_bit = ( cs == 1'b0 && cnt [3:0] == 4'b1111 );
+    wire value_done = ( cs == 1'b1 && cnt [7:0] == 8'b0 );
+
+    always @ (posedge clk or posedge reset)
+    begin       
+        if (reset)
+        begin       
+            shift <= 16'h0000;
+            value <= 16'h0000;
+        end
+        else if (sample_bit)
+        begin       
+            shift <= (shift << 1) | sdo;
+        end
+        else if (value_done)
+        begin       
+            value <= shift;
+        end
+    end
+
+endmodule

MIPSfpga_mipsfpga-plus/exercises/module_to_use/pmod_enc_rotary_encoder.v

@@ -0,0 +1,33 @@
+// Note active positive reset
+
+module pmod_enc_rotary_encoder
+(
+    input             clk,
+    input             reset,
+    input             a,
+    input             b,
+    output reg [15:0] value
+);
+
+    reg prev_a;
+
+    always @ (posedge clk or posedge reset)
+        if (reset)
+            prev_a <= 1'b1;
+        else
+            prev_a <= a;
+
+    always @ (posedge clk or posedge reset)
+        if (reset)
+        begin
+            value <= - 16'd1;  // To do: figure out why we have to start with -1 and not 0
+        end
+        else if (a && ! prev_a)
+        begin
+            if (b)
+                value <= value + 16'd1;
+            else
+                value <= value - 16'd1;
+        end
+
+endmodule

MIPSfpga_mipsfpga-plus/programs/00_counter/main.c

@@ -0,0 +1,26 @@
+#include "mfp_memory_mapped_registers.h"
+
+int main ()
+{
+    long long int n = 0;
+
+    for (;;)
+    {
+        /*
+        MFP_RED_LEDS      = n;
+        MFP_GREEN_LEDS    = n;
+        MFP_7_SEGMENT_HEX = n;
+        */
+
+        MFP_RED_LEDS   = n >> 16;
+        MFP_GREEN_LEDS = n >> 16;
+        MFP_7_SEGMENT_HEX = ((n >> 8) & 0xffffff00) | (n & 0xff);
+
+        n ++;
+
+        // asm ("mfc0 $8, $15, 0");
+        // MFP_7_SEGMENT_HEX = 1;
+    }
+
+    return 0;
+}

MIPSfpga_mipsfpga-plus/programs/00_counter/mfp_memory_mapped_registers.h

@@ -0,0 +1,20 @@
+#ifndef MFP_MEMORY_MAPPED_REGISTERS_H
+#define MFP_MEMORY_MAPPED_REGISTERS_H
+
+#define MFP_RED_LEDS_ADDR       0xBF800000
+#define MFP_GREEN_LEDS_ADDR     0xBF800004
+#define MFP_SWITCHES_ADDR       0xBF800008
+#define MFP_BUTTONS_ADDR        0xBF80000C
+#define MFP_7_SEGMENT_HEX_ADDR  0xBF800010
+
+#define MFP_RED_LEDS            (* (volatile unsigned *) MFP_RED_LEDS_ADDR      )
+#define MFP_GREEN_LEDS          (* (volatile unsigned *) MFP_GREEN_LEDS_ADDR    )
+#define MFP_SWITCHES            (* (volatile unsigned *) MFP_SWITCHES_ADDR      )
+#define MFP_BUTTONS             (* (volatile unsigned *) MFP_BUTTONS_ADDR       )
+#define MFP_7_SEGMENT_HEX       (* (volatile unsigned *) MFP_7_SEGMENT_HEX_ADDR )
+
+// This define is used in boot.S code
+
+#define BOARD_16_LEDS_ADDR      MFP_RED_LEDS_ADDR
+
+#endif

MIPSfpga_mipsfpga-plus/programs/00_counter/modelsim_script.tcl

@@ -0,0 +1,27 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../core
+set i1 +incdir+../../../system_rtl
+set i2 +incdir+../../../system_rtl/uart16550
+set i3 +incdir+../../../testbench
+set i4 +incdir+../../../testbench/sdr_sdram
+
+set s0 ../../../core/*.v
+set s1 ../../../system_rtl/*.v
+set s2 ../../../system_rtl/uart16550/*.v
+set s3 ../../../testbench/*.v
+set s4 ../../../testbench/sdr_sdram/*.v
+
+vlog $p0 $p1  $i0 $i1 $i2 $i3 $i4  $s0 $s1 $s2 $s3 $s4
+
+vsim work.mfp_testbench
+
+add wave -radix hex sim:/mfp_testbench/*
+
+run -all
+
+wave zoom full

MIPSfpga_mipsfpga-plus/programs/01_light_sensor/main.c

@@ -0,0 +1,24 @@
+#include "mfp_memory_mapped_registers.h"
+
+#define DELAY_VALUE (10*1024*1024)
+
+void inline delay()
+{
+    for (long i=0; i < DELAY_VALUE ; i++);
+}
+
+int main ()
+{
+    int n = 0;
+
+    for (;;)
+    {
+        MFP_RED_LEDS      = MFP_LIGHT_SENSOR >> 4;
+        MFP_7_SEGMENT_HEX = MFP_LIGHT_SENSOR;
+        MFP_GREEN_LEDS    = n ++;
+
+        delay();
+    }
+
+    return 0;
+}

MIPSfpga_mipsfpga-plus/programs/01_light_sensor/mfp_memory_mapped_registers.h

@@ -0,0 +1,23 @@
+#ifndef MFP_MEMORY_MAPPED_REGISTERS_H
+#define MFP_MEMORY_MAPPED_REGISTERS_H
+
+#define MFP_RED_LEDS_ADDR       0xBF800000
+#define MFP_GREEN_LEDS_ADDR     0xBF800004
+#define MFP_SWITCHES_ADDR       0xBF800008
+#define MFP_BUTTONS_ADDR        0xBF80000C
+#define MFP_7_SEGMENT_HEX_ADDR  0xBF800010
+
+#define MFP_LIGHT_SENSOR_ADDR   0xB0404000
+
+#define MFP_RED_LEDS            (* (volatile unsigned *) MFP_RED_LEDS_ADDR      )
+#define MFP_GREEN_LEDS          (* (volatile unsigned *) MFP_GREEN_LEDS_ADDR    )
+#define MFP_SWITCHES            (* (volatile unsigned *) MFP_SWITCHES_ADDR      )
+#define MFP_BUTTONS             (* (volatile unsigned *) MFP_BUTTONS_ADDR       )
+#define MFP_7_SEGMENT_HEX       (* (volatile unsigned *) MFP_7_SEGMENT_HEX_ADDR )
+#define MFP_LIGHT_SENSOR        (* (volatile unsigned *) MFP_LIGHT_SENSOR_ADDR  )
+
+// This define is used in boot.S code
+
+#define BOARD_16_LEDS_ADDR      MFP_RED_LEDS_ADDR
+
+#endif

MIPSfpga_mipsfpga-plus/programs/01_light_sensor/modelsim_script.tcl

@@ -0,0 +1,27 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../core
+set i1 +incdir+../../../system_rtl
+set i2 +incdir+../../../system_rtl/uart16550
+set i3 +incdir+../../../testbench
+set i4 +incdir+../../../testbench/sdr_sdram
+
+set s0 ../../../core/*.v
+set s1 ../../../system_rtl/*.v
+set s2 ../../../system_rtl/uart16550/*.v
+set s3 ../../../testbench/*.v
+set s4 ../../../testbench/sdr_sdram/*.v
+
+vlog $p0 $p1  $i0 $i1 $i2 $i3 $i4  $s0 $s1 $s2 $s3 $s4
+
+vsim work.mfp_testbench
+
+add wave -radix hex sim:/mfp_testbench/*
+
+run -all
+
+wave zoom full

MIPSfpga_mipsfpga-plus/programs/02_interrupts/main.c

@@ -0,0 +1,62 @@
+#include <mips/cpu.h>
+
+#include "mfp_memory_mapped_registers.h"
+
+volatile int n;
+
+void __attribute__ ((interrupt, keep_interrupts_masked)) general_exception_handler ()
+{
+    unsigned cause = mips32_getcr ();  // Coprocessor 0 Cause register
+
+    if (cause & CR_HINT0)  // Checking whether interrupt 0 is pending
+        n = 0;
+    else if (cause & CR_HINT1)  // Checking whether interrupt 1 is pending
+        n = 0x100000;
+}
+
+int main ()
+{
+    if (MFP_SWITCHES & 4)  // Switch 2 is on
+    {
+        // Count without interrupts, polling buttons in the loop
+        
+        for (n = 0;; n ++)
+        {
+            unsigned buttons = MFP_BUTTONS;
+
+            if (buttons & 1)
+                n = 0;
+            else if (buttons & 2)
+                n = 0x100000;
+
+            // Assigning to 7-segment indicator this value
+            // makes count visible with both slow and fast clock
+
+            MFP_7_SEGMENT_HEX = ((n >> 8) & 0xffffff00) | (n & 0xff);
+        }
+    }
+    else
+    {
+        // Count with interrupts, without polling buttons in the loop
+        
+        // Clear boot interrupt vector bit in Coprocessor 0 Status register
+
+        mips32_bicsr (SR_BEV);
+        
+        // Set master interrupt enable bit, as well as individual interrupt enable bits
+        // in Coprocessor 0 Status register
+
+        mips32_bissr (SR_IE | SR_HINT0 | SR_HINT1 | SR_HINT2 | SR_HINT3 | SR_HINT4 | SR_HINT5);
+
+        for (n = 0;;)
+        {
+            MFP_7_SEGMENT_HEX = ((n >> 8) & 0xffffff00) | (n & 0xff);
+            
+            __asm__ volatile ("di");  // Disable interrupts
+            n ++;
+            __asm__ volatile ("ei");  // Enable interrupts
+        }
+    }
+
+    return 0;
+}

MIPSfpga_mipsfpga-plus/programs/02_interrupts/mfp_memory_mapped_registers.h

@@ -0,0 +1,20 @@
+#ifndef MFP_MEMORY_MAPPED_REGISTERS_H
+#define MFP_MEMORY_MAPPED_REGISTERS_H
+
+#define MFP_RED_LEDS_ADDR       0xBF800000
+#define MFP_GREEN_LEDS_ADDR     0xBF800004
+#define MFP_SWITCHES_ADDR       0xBF800008
+#define MFP_BUTTONS_ADDR        0xBF80000C
+#define MFP_7_SEGMENT_HEX_ADDR  0xBF800010
+
+#define MFP_RED_LEDS            (* (volatile unsigned *) MFP_RED_LEDS_ADDR      )
+#define MFP_GREEN_LEDS          (* (volatile unsigned *) MFP_GREEN_LEDS_ADDR    )
+#define MFP_SWITCHES            (* (volatile unsigned *) MFP_SWITCHES_ADDR      )
+#define MFP_BUTTONS             (* (volatile unsigned *) MFP_BUTTONS_ADDR       )
+#define MFP_7_SEGMENT_HEX       (* (volatile unsigned *) MFP_7_SEGMENT_HEX_ADDR )
+
+// This define is used in boot.S code
+
+#define BOARD_16_LEDS_ADDR      MFP_RED_LEDS_ADDR
+
+#endif

MIPSfpga_mipsfpga-plus/programs/02_interrupts/modelsim_script.tcl

@@ -0,0 +1,27 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../core
+set i1 +incdir+../../../system_rtl
+set i2 +incdir+../../../system_rtl/uart16550
+set i3 +incdir+../../../testbench
+set i4 +incdir+../../../testbench/sdr_sdram
+
+set s0 ../../../core/*.v
+set s1 ../../../system_rtl/*.v
+set s2 ../../../system_rtl/uart16550/*.v
+set s3 ../../../testbench/*.v
+set s4 ../../../testbench/sdr_sdram/*.v
+
+vlog $p0 $p1  $i0 $i1 $i2 $i3 $i4  $s0 $s1 $s2 $s3 $s4
+
+vsim work.mfp_testbench
+
+add wave -radix hex sim:/mfp_testbench/*
+
+run -all
+
+wave zoom full

MIPSfpga_mipsfpga-plus/programs/03_cache_misses/main.c

@@ -0,0 +1,22 @@
+#include "mfp_memory_mapped_registers.h"
+
+int a [8][8];
+
+int main ()
+{
+    int n = 0;
+    int i, j;
+
+    // Wait for switch 2
+
+    while ((MFP_SWITCHES & 4) == 0)
+        ;
+
+
+    for (i = 0; i < 8; i ++)
+        for (j = 0; j < 8; j ++)
+            // a [i][j] = i + j;
+            a [j][i] = i + j;
+
+    return 0;
+}

MIPSfpga_mipsfpga-plus/programs/03_cache_misses/mfp_memory_mapped_registers.h

@@ -0,0 +1,20 @@
+#ifndef MFP_MEMORY_MAPPED_REGISTERS_H
+#define MFP_MEMORY_MAPPED_REGISTERS_H
+
+#define MFP_RED_LEDS_ADDR       0xBF800000
+#define MFP_GREEN_LEDS_ADDR     0xBF800004
+#define MFP_SWITCHES_ADDR       0xBF800008
+#define MFP_BUTTONS_ADDR        0xBF80000C
+#define MFP_7_SEGMENT_HEX_ADDR  0xBF800010
+
+#define MFP_RED_LEDS            (* (volatile unsigned *) MFP_RED_LEDS_ADDR      )
+#define MFP_GREEN_LEDS          (* (volatile unsigned *) MFP_GREEN_LEDS_ADDR    )
+#define MFP_SWITCHES            (* (volatile unsigned *) MFP_SWITCHES_ADDR      )
+#define MFP_BUTTONS             (* (volatile unsigned *) MFP_BUTTONS_ADDR       )
+#define MFP_7_SEGMENT_HEX       (* (volatile unsigned *) MFP_7_SEGMENT_HEX_ADDR )
+
+// This define is used in boot.S code
+
+#define BOARD_16_LEDS_ADDR      MFP_RED_LEDS_ADDR
+
+#endif

MIPSfpga_mipsfpga-plus/programs/03_cache_misses/modelsim_script.tcl

@@ -0,0 +1,27 @@
+
+vlib work
+
+set p0 -vlog01compat
+set p1 +define+SIMULATION
+
+set i0 +incdir+../../../core
+set i1 +incdir+../../../system_rtl
+set i2 +incdir+../../../system_rtl/uart16550
+set i3 +incdir+../../../testbench
+set i4 +incdir+../../../testbench/sdr_sdram
+
+set s0 ../../../core/*.v
+set s1 ../../../system_rtl/*.v
+set s2 ../../../system_rtl/uart16550/*.v
+set s3 ../../../testbench/*.v
+set s4 ../../../testbench/sdr_sdram/*.v
+
+vlog $p0 $p1  $i0 $i1 $i2 $i3 $i4  $s0 $s1 $s2 $s3 $s4
+
+vsim work.mfp_testbench
+
+add wave -radix hex sim:/mfp_testbench/*
+
+run -all
+
+wave zoom full