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  1. ChFrenkel_ReckOn/README.md +30 -0
  2. ChFrenkel_ReckOn/doc/README.md +243 -0
  3. ChFrenkel_ReckOn/src/fifo.v +123 -0
  4. ChFrenkel_ReckOn/src/lfsr/lfsr_neur_stochround.v +251 -0
  5. ChFrenkel_ReckOn/src/lfsr/lfsr_noise_neur.v +366 -0
  6. ChFrenkel_ReckOn/src/lfsr/lfsr_oneur_stochround.v +202 -0
  7. ChFrenkel_ReckOn/src/lfsr/lfsr_winp_wrec.v +3302 -0
  8. ChFrenkel_ReckOn/src/lfsr/lfsr_wout.v +2897 -0
  9. ChFrenkel_ReckOn/src/reckon.v +472 -0
  10. ChFrenkel_ReckOn/src/spi_slave.v +631 -0
  11. ChFrenkel_ReckOn/src/srnn.v +1605 -0
  12. ChFrenkel_ReckOn/src/tbench.h +96 -0
  13. ChFrenkel_ReckOn/src/tbench.sv +662 -0
ChFrenkel_ReckOn/README.md ADDED
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+ # ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales
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+
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+ ReckOn is a spiking **rec**urrent neural network (RNN) processor enabling **on**-chip learning over second-long timescales based on a modified version of the e-prop algorithm (we released a PyTorch implementation of the vanilla e-prop algorithm for leaky integrate-and-fire neurons [here](https://github.com/ChFrenkel/eprop-PyTorch)). It was prototyped and measured in 28-nm FDSOI CMOS at the Institute of Neuroinformatics, University of Zurich and ETH Zurich, and published at the 2022 *IEEE International Solid-State Circuits Conference (ISSCC)* with the following three main claims:
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+
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+ * ReckOn demonstrates **end-to-end on-chip learning over second-long timescales** while keeping a milli-second temporal resolution,
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+ * it provides a low-cost solution with a 0.45-mm² core area, 5.3pJ/SOP at 0.5V, and a **memory overhead of only 0.8%** compared to the equivalent inference-only network,
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+ * it exploits a **spike-based representation for task-agnostic learning** toward user customization and chip repurposing at the edge.
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+
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+ In case you decide to use the ReckOn HDL source code for academic or commercial use, we would appreciate it if you let us know; **feedback is welcome**.
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+
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+
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+ ## Citation
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+
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+ Upon usage of the HDL source code of ReckOn, please cite the associated paper:
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+
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+ > [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales," *IEEE International Solid-State Circuits Conference (ISSCC)*, 2022]
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+
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+
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+ ## Documentation
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+
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+ Documentation on the contents, usage and features of the ReckOn HDL source code can be found in the [doc folder](doc/).
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+
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+
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+ ## Licenses
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+
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+ > *Copyright (C) 2020-2022 University of Zurich*
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+
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+ > *The HDL source code of ReckOn is under a Solderpad Hardware License v2.1 (see [LICENSE](LICENSE) file or https://solderpad.org/licenses/SHL-2.1/).*
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+
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+ > *The documentation of ReckOn is under a Creative Commons Attribution 4.0 International License (see [doc/LICENSE](doc/LICENSE) file or http://creativecommons.org/licenses/by/4.0/).*
ChFrenkel_ReckOn/doc/README.md ADDED
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+ # ReckOn Online-Learning Spiking RNN Processor Documentation
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+
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+
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+ > Copyright (C) 2020-2022 University of Zurich
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+
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+ > The documentation for ReckOn is under a Creative Commons Attribution 4.0 International License (see [doc/LICENSE](LICENSE) file or http://creativecommons.org/licenses/by/4.0/), while the ReckOn HDL source code is under a Solderpad Hardware License v2.1 (see [LICENSE](../LICENSE) file or https://solderpad.org/licenses/SHL-2.1/).
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+
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+ > [![Creative Commons Attribution 4.0 International License](https://i.creativecommons.org/l/by/4.0/88x31.png)](http://creativecommons.org/licenses/by/4.0/)
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+
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+ Before reading the documentation, it is strongly advised to read our [*ISSCC 2022* paper](#6-citing-reckon) in order to have a clear overview of the ReckOn online-learning spiking RNN processor.
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+ Part of the documentation structure, formatting and contents is adapted from the documentation of the [ODIN SNN processor](https://github.com/ChFrenkel/ODIN/).
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+ **Current documentation revision: v1.0.** It only contains basic descriptions on the chip communication buses, memory addressing schemes and main configuration registers. Unpublished parts of the chip have been removed from the currently-released HDL code, as well as from the documentation. A documentation and HDL update will take place upon publication of the omitted parts.
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+
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+
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+
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+ ## Contents
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+
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+ 1. [Architecture](#1-architecture)
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+ 2. [Interfaces and commands](#2-interfaces-and-commands)
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+ 3. [Global configuration registers](#3-global-configuration-registers)
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+ 4. [Testbench](#4-testbench)
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+ 5. [Implementation tips](#5-implementation-tips)
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+ 6. [Citing ReckOn](#6-citing-reckon)
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+ 7. [Revision history](#7-revision-history)
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+
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+
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+
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+ ## 1. Architecture
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+
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+ ReckOn is a spiking **rec**urrent neural network (RNN) processor enabling **on**-chip learning over second-long timescales based on a modified version of the e-prop algorithm (we released a PyTorch implementation of the vanilla e-prop algorithm for leaky integrate-and-fire neurons [here](https://github.com/ChFrenkel/eprop-PyTorch)). It was prototyped and measured in 28-nm FDSOI CMOS at the Institute of Neuroinformatics, University of Zurich and ETH Zurich, and published at the 2022 *IEEE International Solid-State Circuits Conference (ISSCC)* with the following three main claims:
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+
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+ * ReckOn demonstrates **end-to-end on-chip learning over second-long timescales** while keeping a milli-second temporal resolution,
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+ * it provides a low-cost solution with a 0.45-mm² core area, 5.3pJ/SOP at 0.5V, and a **memory overhead of only 0.8%** compared to the equivalent inference-only network,
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+ * it exploits a **spike-based representation for task-agnostic learning** toward user customization and chip repurposing at the edge.
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+
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+ ReckOn implements a (256)-r256-16 network topology with 256 virtual input neurons, 256 recurrent leaky integrate-and-fire (LIF) neurons with all-to-all connectivity and 16 output leaky integrator (LI) neurons. A future revision of the documentation will extensively cover architectural details of ReckOn, including the embedded FSMs. For the time being, we briefly describe hereunder how the main SRAM resources of ReckOn are accessed. We refer the reader to [the paper](#6-citing-reckon) for more information on the network architecture, as well as for block diagrams of the complete system and of the e-prop-based learning scheme.
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+
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+ * **Neuron SRAM:** This 2-kB SRAM contains 128 words of 128 bits. Each word contains the individual state data of two neurons (i.e. current membrane potential and eligibility trace values) and their shared parameters (i.e. leakage decay factor *alpha* and firing threshold) as follows:
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+
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+ | Word bit range | Description (N represents the 7-bit word address) |
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+ |----------------|------------------------------------------------------------------------|
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+ | <127:116> | 12 LSBs of the fractional part of the 16-bit leakage decay factor *alpha* (see [Section 3](#3-global-configuration-registers) for the 4 MSBs). Shared parameter between neurons 2N and 2N+1. |
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+ | <115:100> | 16-bit firing threshold. Shared parameter between neurons 2N and 2N+1. |
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+ | <99:90> | 10-bit output eligibility trace associated to neuron 2N+1. |
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+ | <89:78> | 12-bit recurrent eligibility trace associated to neuron 2N+1. |
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+ | <77:66> | 12-bit input eligibility trace associated to neuron 2N+1. |
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+ | <65:50> | 16-bit membrane potential associated to neuron 2N+1. |
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+ | <49:40> | 10-bit output eligibility trace associated to neuron 2N. |
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+ | <39:28> | 12-bit recurrent eligibility trace associated to neuron 2N. |
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+ | <27:16> | 12-bit input eligibility trace associated to neuron 2N. |
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+ | <15:0> | 16-bit membrane potential associated to neuron 2N. |
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+
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+ * **Input/recurrent weight SRAMs:** These 64-kB SRAMs contain 4k words of 128 bits for the storage of 8-bit input/recurrent weights. The 8 MSBs of the 12-bit word address contain the pre-synaptic neuron index, the 4 LSBs of the 12-bit word address contain the 4 MSBs of the post-synaptic neuron index. The 4 LSBs of the post-synaptic neuron index represent the byte address of the target weight in the accessed 128-bit word.
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+
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+ * **Output weight SRAM:** This 8-kB SRAM contains 512 words of 128 bits for the storage of 8-bit output weights. Only the first 256 words are used, the MSB of the 9-bit word address is thus fixed to 0 and the 8 LSBs represent the pre-synaptic neuron index. The accessed 128-bit word thus contains the output weights of all 16 output neurons.
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+
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+
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+
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+ ## 2. Interfaces and commands
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+
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+ The top-level file [reckon.v](../src/reckon.v) contains three main interfaces: the SPI bus ([Section 2.1](#21-spi-bus)), the input AER bus ([Section 2.2](#22-address-event-representation-aer-input-bus)) and an output bus ([Section 2.3](#23-output-bus)). Other I/O pins are described as follows:
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+
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+ | Pin | Direction | Description |
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+ |---------------------|-----------|----------------------------------------------------------------------|
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+ |*CLK\_EXT* | Input | External clock. |
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+ |*CLK\_INT_EN* | Input | Enable signal for the internal clock generator. |
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+ |*RST* | Input | Global reset signal. |
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+ |*SAMPLE* | Input | Signals the start and the end of an input data sample. |
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+ |*TIME\_TICK* | Input | Signals the start of a new timestep (rising edge). |
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+ |*TARGET\_VALID* | Input | Signals timesteps for which a target is expected for e-prop updates. |
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+ |*INFER\_ACC* | Input | Signals timesteps for which counts of the winning output neurons are to be updated (for classification tasks, over the course of timesteps during which *INFER\_ACC* was enabled, the label of the output neuron with the highest output over most timesteps will represent the network inference). |
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+ |*SPI\_RDY* | Output | [For debug/monitoring purposes] Signals when the global FSM enters the *CONFIG* state, during which the network state is frozen and can be safely read/written through SPI. |
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+ |*TIMING\_ERROR\_RDY* | Output | If *SPI\_TIMING\_MODE*=1, signals the occurrence of a timing error (*TIME\_TICK* was asserted before the global FSM finished processing the current timestep). If *SPI\_TIMING\_MODE*=0, signals when the global FSM finished processing the current timestep and *TIME\_TICK* can be safely asserted. |
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+
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+
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+ ### 2.1. SPI bus
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+
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+ | ![SPI](figs/spi.png) |
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+ |:--:|
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+ | *Fig. 1 - 32-bit SPI timing diagram for (a) write and (b) read operations.* |
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+
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+ ReckOn implements a standard 32-bit SPI slave bus with the following interface:
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+
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+ | Pin | Direction | Width | Description |
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+ |--------|-----------|-------|----------------------------------------|
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+ |*SCK* | Input | 1-bit | SPI clock generated by the SPI master. |
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+ |*MOSI* | Input | 1-bit | Master output, slave input. |
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+ |*MISO* | Output | 1-bit | Master input, slave output. As the fabricated chip was pad-limited, other signals can be displayed on the *MISO* pin (see [Section 3](#3-global-configuration-registers)). |
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+
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+ When using the SPI bus, the *SPI\_EN\_CONF* configuration register should be asserted first ([Section 3](#3-global-configuration-registers)). In order to ensure proper operation, the SCK SPI clock should operate at a frequency at least 4x smaller than the clock frequency of ReckOn. The SPI write and read operations follow the timing diagram shown in Figs. 1(a) and 1(b), respectively: a 32-bit address field is first transmitted by the SPI master, before data associated to this address is sent by the master (write) or received from ReckOn (read). Depending on the contents of the 32-bit address field *a*, where *a<31>* indicates whether a write (0) or read (1) operation should be pursued, the SPI bus can be used to access the [configuration registers](#3-global-configuration-registers) or the on-chip SRAM / register file contents as follows:
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+
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+ | *code<2:0>* (*a<30:28>*) | *addr<15:0>* (*a<15:0>*) | Description |
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+ |---------------------------|---------------------------------------------|-------------------------------------------------------------------------|
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+ | 3'b000 | {*addr\_conf<15:0>*} | Write to configuration register at address *addr\_conf* (not readable). |
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+ | 3'b001 | {n/a,*addr\_word<6:0>*,*addr\_32b<1:0>*} | Read/write to the neuron SRAM (128 128-bit words). 4-byte chunk *addr\_32b* from word address *addr\_word* of the SRAM is read/written. |
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+ | 3'b010 | {n/a,*addr\_oneur<3:0>*} | Read/write to the 16-bit membrane potential of output neuron *addr\_oneur* (register-file-based storage). |
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+ | 3'b011 | {n/a,*addr\_word<11:0>*,*addr\_32b<1:0>*} | Read/write to the input weight SRAM (4096 128-bit words). 4-byte chunk *addr\_32b* from word address *addr\_word* of the SRAM is read/written. |
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+ | 3'b100 | {n/a,*addr\_word<11:0>*,*addr\_32b<1:0>*} | Read/write to the recurrent weight SRAM (4096 128-bit words). 4-byte chunk *addr\_32b* from word address *addr\_word* of the SRAM is read/written. |
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+ | 3'b101 | {n/a,*addr\_word<8:0>*,*addr\_32b<1:0>*} | Read/write to the output weight SRAM (512 128-bit words, of which only the first 256 words are used). 4-byte chunk *addr\_32b* from word address *addr\_word* of the SRAM is read/written. |
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+
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+ In order to accelerate initialization/readback of the ReckOn SRAMs, grouped data read/write operations can be performed over SPI from a single address field. To do so, *a<27:16>* contains the number of SPI data transactions to be performed from a starting address of *a<15:0>*, which will then be incremented internally in the SPI module. If *a<27:16>* is given a value of 1, a standard SPI transaction with a single data field is performed.
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+
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+
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+ ### 2.2. Address-event representation (AER) input bus
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+
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+ | ![AER](figs/aer.png) |
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+ |:--:|
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+ | *Fig. 2 - Input AER four-phase handshake timing diagram.* |
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+
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+ Address-event representation (AER) buses follow a four-phase-handshake protocol for asynchronous communication between neuromorphic chips. As ReckOn follows a synchronous digital IC design flow, a double-latching barrier is placed on the *REQ* line of the input AER bus in order to limit metastability issues.
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+ The input AER bus has the following interface:
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+
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+ | Pin | Direction | Width | Description |
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+ |-----------------|-----------|-------|---------------------------------|
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+ | *AERIN\_ADDR* | Input | 8-bit | AER address field. |
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+ | *AERIN\_TAR_EN* | Input | 1-bit | Indicates whether data in *AERIN\_ADDR* represents the address of a virtual input neuron (0) or target data for e-prop-based learning (1). |
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+ | *AERIN\_REQ* | Input | 1-bit | AER request handshake line. |
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+ | *AERIN\_ACK* | Output | 1-bit | AER acknowledge handshake line. |
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+
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+
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+ ### 2.3. Output bus
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+
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+ The output bus interface has been simplified compared to the one in the fabricated chip in order to remove unpublished blocks.
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+ The output bus in the currently-released version of the HDL has a format similar to the AER interface described in [Section 2.2](#22-address-event-representation-aer-input-bus) and its sole purpose is to transmit inference results.
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+
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+ | Pin | Direction | Width | Description |
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+ |----------------|-----------|--------|---------------------------------|
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+ | *OUT\_DATA* | Output | 8-bit | Data field. |
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+ | *OUT\_REQ* | Output | 1-bit | Request handshake line. |
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+ | *OUT\_ACK* | Input | 1-bit | Acknowledge handshake line. |
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+
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+ For classification setups (see [Section 3](#3-global-configuration-registers) for the associated configuration registers), only one transaction takes place at the end of the sample and the 4 LSBs of *OUT\_DATA* contain the index of the output neuron with the highest output averaged over the timesteps during which the *INFER\_ACC* pin was asserted. For regression setups, a series of output transactions takes place at each timestep, where the 16-bit membrane potential values of active output neurons are successively transmitted (the 8 LSBs first, followed by the 8 MSBs).
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+
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+
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+
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+ ## 3. Global configuration registers
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+ Configuration registers can be written through the SPI bus (no readback operation is available) and are defined as follows:
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+
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+
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+ | Register Name |Addr<15:0>| Width | Reset value | Description |
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+ |---------------------------|----------|---------|-------------|---------------------------------|
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+ |*SPI\_EN\_CONF* | 0 | 1-bit | 1'b1 | Enables access to the network internal state through SPI and ensures the control FSM goes into a safe state to do so, which will be signalled through the *SPI\_RDY* pin. |
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+ |*SPI\_RO\_STAGE\_SEL* | 1 | 9-bit | / | Selects the stage of the ring-oscillator-based local clock generator (not used in the released HDL code as technology-specific blocks, incl. clock gen and frequency divider, were removed). |
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+ |*SPI\_GET\_CLKINT\_OUT* | 2 | 1-bit | 1'b0 | Enables a frequency-divided copy of the locally generated clock to be displayed on the SPI *MISO* pin for monitoring purposes (not used in the released HDL code as technology-specific blocks, incl. clock gen and frequency divider, were removed). |
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+ |*SPI\_GET\_TAR\_REQ\_OUT* | 3 | 1-bit | 1'b1 | Enables the target request signal to be displayed on the *MISO* pin. |
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+ |*SPI\_RST\_MODE* | 8 | 1-bit | 1'b0 | Selects the spike reset mode of LIF neurons (1: reset to zero, 0: reset by subtraction). |
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+ |*SPI\_DO\_EPROP* | 9 | 3-bit | 3'b111 | Enables e-prop updates (bit 0: input weight updates, bit 1: recurrent weight updates, bit 2: output weight updates). Input/recurrent/output weights can be independently configured in any plastic/frozen configuration. |
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+ |*SPI\_LOCAL\_TICK* | 10 | 1-bit | 1'b0 | Enables local generation of timestep ticks (see *SPI\_CYCLES\_PER\_TICK* for the timestep duration). If configured to 0, timestep ticks are provided externally through the *TIME\_TICK* pin. |
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+ |*SPI\_ERROR\_HALT* | 11 | 1-bit | 1'b1 | Enables halting the network operation if a timing error takes place (i.e. a timestep tick occurred before the global FSM finished processing the current timestep) for debugging purposes. A network reset will be necessary. |
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+ |*SPI\_FP\_LOC\_WINP* | 12 | 3-bit | 3'd0 | Input weight scaling parameter. The stored 8-bit input weights are sign-extended to 16 bits and left-shifted by the value of *SPI\_FP\_LOC\_WINP* before being added to the neuron membrane potentials. |
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+ |*SPI\_FP\_LOC\_WREC* | 13 | 3-bit | 3'd0 | Recurrent weight scaling parameter. The stored 8-bit recurrent weights are sign-extended to 16 bits and left-shifted by the value of *SPI\_FP\_LOC\_WREC* before being added to the neuron membrane potentials. |
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+ |*SPI\_FP\_LOC\_WOUT* | 14 | 3-bit | 3'd0 | Output weight scaling parameter. The stored 8-bit output weights are sign-extended to 16 bits and left-shifted by the value of *SPI\_FP\_LOC\_WOUT* before being added to the neuron membrane potentials. |
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+ |*SPI\_FP\_LOC\_TINP* | 15 | 3-bit | 3'd0 | Radix point location of input traces (left-shifted by the value of *SPI\_FP\_LOC\_TINP*). |
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+ |*SPI\_FP\_LOC\_TREC* | 16 | 3-bit | 3'd0 | Radix point location of recurrent traces (left-shifted by the value of *SPI\_FP\_LOC\_TREC*). |
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+ |*SPI\_FP\_LOC\_TOUT* | 17 | 3-bit | 3'd0 | Radix point location of output traces (left-shifted by the value of *SPI\_FP\_LOC\_TOUT*). |
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+ |*SPI\_LEARN\_SIG\_SCALE* | 18 | 4-bit | 4'd0 | Learning signals scaling parameter, which are left-shifted by the value of *SPI\_LEARN\_SIG\_SCALE*. |
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+ |*SPI\_REGUL\_MODE* | 19 | 3-bit | 3'b000 | Selects the weight regularization mode (bit 0: multiplicative regularization, bit 1: additive regularization). If bit 2 is asserted, regularization is enabled during all timesteps, not only when the *TARGET\_VALID* pin is asserted (for use only with additive regularization). |
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+ |*SPI\_REGUL\_W* | 20 | 2-bit | 2'b00 | Enables weight regularization (bit 0: input weights, bit 1: recurrent weights). Input/recurrent weights can be independently configured in any regularized/non-regularized configuration. | |
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+ |*SPI\_EN\_STOCH\_ROUND* | 21 | 1-bit | 1'b0 | Enables stochastic rounding in the eligibility traces and neuron membrane potentials. |
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+ |*SPI\_SRAM\_SPEEDMODE* | 22 | 8-bit | 8'h00 | Configuration of the SRAM macro speed modes (not used in the released HDL code as technology-specific blocks were removed). |
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+ |*SPI\_TIMING_MODE* | 23 | 1-bit | 1'b0 | Controls the pin function of *TIMING\_ERROR\_RDY* (see pin description in [Section 2](#2-interfaces-and-commands)). |
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+ |*SPI\_REGRESSION* | 25 | 1-bit | 1'b0 | Should be programmed to 1 for regression tasks and 0 for classification tasks. |
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+ |*SPI\_SINGLE\_LABEL* | 26 | 1-bit | 1'b1 | Should be programmed to 1 for classification tasks in order to provide the classification label only once per sample, instead of at every timestep. |
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+ |*SPI\_NO\_OUT\_ACT* | 27 | 1-bit | 1'b0 | Disables the hard-sigmoid non-linearity applied to the membrane potential of output neurons. |
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+ |*SPI\_SEND\_PER\_TIMESTEP* | 30 | 1-bit | 1'b0 | Enables sending the network output (format conditioned by *SPI\_SEND\_LABEL\_ONLY*) at every timestep instead of once at the end of the sample. Typically for use in regression tasks. |
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+ |*SPI\_SEND\_LABEL\_ONLY* | 31 | 1-bit | 1'b1 | Configures the network output contents sent over the output bus (1: winning neuron label, 0: membrane potential values of all enabled output neurons). Typically configured to 1 for classification tasks and 0 for regression tasks. |
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+ |*SPI\_NOISE\_EN* | 32 | 1-bit | 1'b0 | Enables the addition of random noise to membrane potential updates of LIF neurons (noise magnitude configured with *SPI\_NOISE\_STR*). |
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+ |*SPI\_FORCE\_TRACES* | 33 | 1-bit | 1'b0 | Forces eligibility trace computation even if e-prop updates are disabled (for monitoring purposes). |
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+ |*SPI\_CYCLES\_PER\_TICK* | 64 | 32-bit | / | Number of clock cycles per locally generated timestep tick (used only if *SPI\_LOCAL\_TICK* is enabled). |
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+ |*SPI\_ALPHA\_CONF* | 65-68 | 128-bit | 128'h0 | Each bit of *SPI\_ALPHA\_CONF* selects the 4 MSBs of the 16-bit leakage decay factors *alpha* associated to every pair of two LIF neurons, which consist of a single-bit integer part and a 15-bit fractional part (1: the integer part bit is 1 and the three MSBs of the fractional part are 3'b000, 0: the integer part bit is 0 and the three MSBs of the fractional part are 3'b111). The 12 LSBs of *alpha*'s for every pair of two LIF neurons are defined in the neuron memory ([Section 1](#1-architecture)). |
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+ |*SPI\_KAPPA* | 69 | 8-bit | 8'h7A | Defines the value of the 8-bit leakage factor *kappa* shared among all output LI neurons, which consists of a single-bit integer part and a 7-bit fractional part. |
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+ |*SPI\_THR\_H\_0* | 70 | 16-bit | / | Defines the membrane potential threshold separating the first and second segments of the straight-through-estimator (STE) function. |
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+ |*SPI\_THR\_H\_1* | 71 | 16-bit | / | Defines the membrane potential threshold separating the second and third segments of the straight-through-estimator (STE) function. |
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+ |*SPI\_THR\_H\_2* | 72 | 16-bit | / | Defines the membrane potential threshold separating the third and fourth segments of the straight-through-estimator (STE) function. |
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+ |*SPI\_THR\_H\_3* | 73 | 16-bit | / | Defines the membrane potential threshold separating the fourth and fifth segments of the straight-through-estimator (STE) function. |
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+ |*SPI\_H\_0* | 74 | 5-bit | / | Defines the value of the first segment of the straight-through-estimator (STE) function. |
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+ |*SPI\_H\_1* | 75 | 5-bit | / | Defines the value of the second segment of the straight-through-estimator (STE) function. |
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+ |*SPI\_H\_2* | 76 | 5-bit | / | Defines the value of the third segment of the straight-through-estimator (STE) function. |
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+ |*SPI\_H\_3* | 77 | 5-bit | / | Defines the value of the fourth segment of the straight-through-estimator (STE) function. |
184
+ |*SPI\_H\_4* | 78 | 5-bit | / | Defines the value of the fifth segment of the straight-through-estimator (STE) function. |
185
+ |*SPI\_LR\_R\_WINP* | 79 | 5-bit | / | Input weight update probability scaling parameter (applies a right shift by the value of *SPI\_LR\_R\_WINP*). |
186
+ |*SPI\_LR\_P\_WINP* | 80 | 5-bit | / | Input weight update probability scaling parameter (applies a left shift by the value of *SPI\_LR\_P\_WINP*). |
187
+ |*SPI\_LR\_R\_WREC* | 81 | 5-bit | / | Recurrent weight update probability scaling parameter (applies a right shift by the value of *SPI\_LR\_R\_WREC*). |
188
+ |*SPI\_LR\_P\_WREC* | 82 | 5-bit | / | Recurrent weight update probability scaling parameter (applies a left shift by the value of *SPI\_LR\_P\_WREC*). |
189
+ |*SPI\_LR\_R\_WOUT* | 83 | 5-bit | / | Output weight update probability scaling parameter (applies a right shift by the value of *SPI\_LR\_R\_WOUT*). |
190
+ |*SPI\_LR\_P\_WOUT* | 84 | 5-bit | / | Output weight update probability scaling parameter (applies a left shift by the value of *SPI\_LR\_P\_WOUT*). |
191
+ |*SPI\_SEED\_INP* | 85 | 25-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic input weight updates. |
192
+ |*SPI\_SEED\_REC* | 86 | 25-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic recurrent weight updates. |
193
+ |*SPI\_SEED\_OUT* | 87 | 22-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic output weight updates. |
194
+ |*SPI\_SEED\_STRND\_NEUR* | 88 | 30-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic rounding of the LIF neuron membrane potentials. |
195
+ |*SPI\_SEED\_STRND\_ONEUR* | 89 | 15-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic rounding of the output neuron membrane potentials. |
196
+ |*SPI\_SEED\_STRND\_TINP* | 90 | 30-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic rounding of the input eligibility traces. |
197
+ |*SPI\_SEED\_STRND\_TREC* | 91 | 30-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic rounding of the recurrent eligibility traces. |
198
+ |*SPI\_SEED\_STRND\_TOUT* | 92 | 30-bit | / | Seed of the unfolded LFSR generating random numbers for stochastic rounding of the output eligibility traces. |
199
+ |*SPI\_SEED\_NOISE\_NEUR* | 93 | 17-bit | / | Seed of the unfolded LFSR generating random numbers for the configurable amount of noise added to the LIF neuron membrane potentials. |
200
+ |*SPI\_NUM\_INP\_NEUR* | 94 | 8-bit | 8'hFF | Number of input neurons enabled in the network (should be configured to the target number of neurons -1). |
201
+ |*SPI\_NUM\_REC\_NEUR* | 95 | 8-bit | 8'hFF | Number of recurrent neurons enabled in the network (should be configured to the target number of neurons -1). |
202
+ |*SPI\_NUM\_OUT\_NEUR* | 96 | 4-bit | 4'hF | Number of output neurons enabled in the network (should be configured to the target number of neurons -1). |
203
+ |*SPI\_REGUL\_F0* | 98 | 12-bit | / | Value of the post-synaptic recurrent eligibility traces above which regularization on the pre-synaptic weights is turned on. |
204
+ |*SPI\_REGUL\_K\_INP\_R* | 99 | 5-bit | / | Input weight additive regularization scaling parameter (applies a right shift by the value of *SPI\_REGUL\_K\_INP\_R*). |
205
+ |*SPI\_REGUL\_K\_INP\_P* | 100 | 5-bit | / | Input weight additive regularization scaling parameter (applies a left shift by the value of *SPI\_REGUL\_K\_INP\_P*). |
206
+ |*SPI\_REGUL\_K\_REC\_R* | 101 | 5-bit | / | Recurrent weight additive regularization scaling parameter (applies a right shift by the value of *SPI\_REGUL\_K\_REC\_R*). |
207
+ |*SPI\_REGUL\_K\_REC\_P* | 102 | 5-bit | / | Recurrent weight additive regularization scaling parameter (applies a left shift by the value of *SPI\_REGUL\_K\_REC\_P*). |
208
+ |*SPI\_REGUL\_K\_MUL* | 103 | 5-bit | / | Input and recurrent weight multiplicative regularization scaling parameter (applies a right shift by the value of *SPI\_REGUL\_K\_MUL*). |
209
+ |*SPI\_NOISE\_STR* | 104 | 4-bit | / | Neuron noise scaling parameter. Noise is generated as pseudo-random 16-bit words to be added to the LIF neuron membrane potentials, right-shifted by the value of *SPI\_NOISE\_STR*. |
210
+
211
+
212
+
213
+ ## 4. Testbench
214
+
215
+ A simple testbench file demonstrating online learning is provided (see [testbench.sv](../src/tbench.sv) file, you may want to update paths listed in lines 33-37). The [data](../src/data/) folder contains two single 50-sample batches ([one for training](../src/data/dataset_cueAcc_train.dat), [one for test](../src/data/dataset_cueAcc_test.dat)) of the delayed-supervision navigation task, whose size and complexity are suitable for RTL simulations (see [paper](#6-citing-reckon) for details). The first line of these dataset files indicates the number of samples, the subsequent lines represent events: the first tuple element contains the input neuron index, the second one the time in milliseconds. Special events are used to represent the end of the sample (the first element has index -1) and the start of the delayed supervision (the first element has index -2, the second represents the target label). Random [input](../src/data/init_rand_weights_inp_cueAcc.dat), [recurrent](../src/data/init_rand_weights_rec_cueAcc.dat) and [output](../src/data/init_rand_weights_out_cueAcc.dat) weight initialization files are provided as well.
216
+
217
+
218
+
219
+ ## 5. Implementation tips
220
+
221
+ When implementing ReckOn or adapting it for a particular application, care should be taken with the following points:
222
+
223
+ * The provided Verilog HDL code can directly be used for behavioral simulation. For implementation with a specific technology node, the behavioral descriptions of the neuron and weight SRAMs in [srnn.v](../src/srnn.v) need to be replaced with SRAM macros. Block RAM (BRAM) instances can be used for FPGA implementations.
224
+
225
+ * The different Verilog modules contain as parameters N and M, where N represents the number of neurons in the input and recurrent layers and M is log2(N). These parameters help rescaling ReckOn to different network dimensions, however the datapath is not entirely generic in N and M and further adaptations are needed if the dimensions are changed.
226
+
227
+
228
+
229
+ ## 6. Citing ReckOn
230
+
231
+ Upon usage of the documentation or source code, please cite the paper associated to ReckOn:
232
+
233
+ > [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network processor enabling on-chip learning over second-long timescales," *IEEE International Solid-State Circuits Conference (ISSCC)*, 2022]
234
+
235
+
236
+
237
+ ## 7. Revision history
238
+
239
+ | Rev | Date | Author | Description |
240
+ |--------|--------------|------------|---------------------------------------|
241
+ | 1.0 | 18 Feb. 2022 | C. Frenkel | Basic doc without unpublished parts |
242
+
243
+
ChFrenkel_ReckOn/src/fifo.v ADDED
@@ -0,0 +1,123 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "fifo.v" - FIFO module
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: -
25
+ //
26
+ //------------------------------------------------------------------------------
27
+
28
+ module fifo #(
29
+ parameter width = 9,
30
+ parameter depth = 4,
31
+ parameter depth_addr = 2 // Should never be less than 2
32
+ )(
33
+ input wire clk,
34
+ input wire rst_n,
35
+ input wire push_req_n,
36
+ input wire pop_req_n,
37
+ input wire [ width-1:0] data_in,
38
+ output reg empty,
39
+ output wire full,
40
+ output wire [depth_addr-1:0] free_space,
41
+ output wire [ width-1:0] data_out,
42
+ output wire [ width-1:0] data_out_next);
43
+
44
+
45
+ //Wires and internal registers
46
+ reg [width-1:0] mem [0:depth-1];
47
+
48
+ reg [depth_addr-1:0] write_ptr;
49
+ reg [depth_addr-1:0] read_ptr;
50
+ wire [depth_addr-1:0] next_read_ptr;
51
+ reg [depth_addr-1:0] fill_cnt;
52
+
53
+ genvar i;
54
+
55
+
56
+ always @(posedge clk, negedge rst_n) begin
57
+ if (!rst_n)
58
+ write_ptr <= {(depth_addr){1'b0}};
59
+ else if (!push_req_n && (!full || !pop_req_n))
60
+ write_ptr <= write_ptr + {{(depth_addr-1){1'b0}},1'b1};
61
+ else
62
+ write_ptr <= write_ptr;
63
+ end
64
+
65
+ always @(posedge clk, negedge rst_n) begin
66
+ if (!rst_n)
67
+ read_ptr <= {(depth_addr){1'b0}};
68
+ else if (!pop_req_n && !empty)
69
+ read_ptr <= next_read_ptr;
70
+ else
71
+ read_ptr <= read_ptr;
72
+ end
73
+ assign next_read_ptr = read_ptr + {{(depth_addr-1){1'b0}},1'b1};
74
+
75
+ always @(posedge clk, negedge rst_n) begin
76
+ if (!rst_n)
77
+ fill_cnt <= {(depth_addr){1'b0}};
78
+ else if (!push_req_n && pop_req_n && !empty && !full)
79
+ fill_cnt <= fill_cnt + {{(depth_addr-1){1'b0}},1'b1};
80
+ else if (!push_req_n && !pop_req_n)
81
+ fill_cnt <= fill_cnt;
82
+ else if (!pop_req_n && |fill_cnt)
83
+ fill_cnt <= fill_cnt - {{(depth_addr-1){1'b0}},1'b1};
84
+ else
85
+ fill_cnt <= fill_cnt;
86
+ end
87
+
88
+ always @(posedge clk, negedge rst_n) begin
89
+ if (!rst_n)
90
+ empty <= 1'b1;
91
+ else if (!push_req_n)
92
+ empty <= 1'b0;
93
+ else if (!pop_req_n)
94
+ empty <= ~|fill_cnt;
95
+ else
96
+ empty <= empty;
97
+ end
98
+
99
+ assign free_space = {(depth_addr){1'b1}} - fill_cnt;
100
+
101
+ assign full = &fill_cnt;
102
+
103
+
104
+ generate
105
+
106
+ for (i=0; i<depth; i=i+1) begin
107
+
108
+ always @(posedge clk) begin
109
+ if (!push_req_n && (!full || !pop_req_n) && (write_ptr == i))
110
+ mem[i] <= data_in;
111
+ else
112
+ mem[i] <= mem[i];
113
+ end
114
+
115
+ end
116
+
117
+ endgenerate
118
+
119
+ assign data_out = mem[read_ptr];
120
+ assign data_out_next = mem[next_read_ptr];
121
+
122
+
123
+ endmodule
ChFrenkel_ReckOn/src/lfsr/lfsr_neur_stochround.v ADDED
@@ -0,0 +1,251 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "lfsr_neur_stochround.v" - Unfolded LFSR module for stochastic rounding on the recurrent neuron membrane potentials
15
+ // and eligibility traces
16
+ //
17
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
18
+ //
19
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
20
+ //
21
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
22
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
23
+ // Circuits Conference (ISSCC), 2022]
24
+ //
25
+ // Comments: This module has been automatically generated by a custom Python script applying the unfolding algorithm to
26
+ // arbitrary LFSRs (k pseudo-random outputs generated at every clock cycle, where k is the unfolding factor), see
27
+ // [C. Frenkel, J.D. Legat and D. Bol, "MorphIC: A 65-nm 738k-synapse/mm² quad-core binary-weight digital
28
+ // neuromorphic processor with stochastic spike-driven online learning", IEEE. Trans. on Biomedical Circuits
29
+ // and Systems, vol. 13, no. 5, pp. 999-1010, 2019]
30
+ // for details of the LFSR unfolding procedure.
31
+ //
32
+ //------------------------------------------------------------------------------
33
+
34
+
35
+ module lfsr_neur_stochround (
36
+ // Inputs
37
+ input wire clk,
38
+ input wire rst,
39
+ input wire en,
40
+ input wire [14:0] rst_val,
41
+ input wire [14:0] seed,
42
+ input wire prog,
43
+
44
+ // Output
45
+ output wire [14:0] out
46
+ );
47
+
48
+ // Nodes definitions
49
+ wire x0, x0a, x0b;
50
+ wire x1, x1a, x1b;
51
+ wire x2, x2a, x2b;
52
+ wire x3, x3a, x3b;
53
+ wire x4, x4a, x4b;
54
+ wire x5, x5a, x5b;
55
+ wire x6, x6a, x6b;
56
+ wire x7, x7a, x7b;
57
+ wire x8, x8a, x8b;
58
+ wire x9, x9a, x9b;
59
+ wire x10, x10a, x10b;
60
+ wire x11, x11a, x11b;
61
+ wire x12, x12a, x12b;
62
+ wire x13, x13a, x13b;
63
+ wire x14, x14a, x14b;
64
+ wire y0;
65
+ wire y1;
66
+ wire y2;
67
+ wire y3;
68
+ wire y4;
69
+ wire y5;
70
+ wire y6;
71
+ wire y7;
72
+ wire y8;
73
+ wire y9;
74
+ wire y10;
75
+ wire y11;
76
+ wire y12;
77
+ wire y13;
78
+ wire y14;
79
+ reg d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14;
80
+
81
+ // Combinational and sequential logic definitions
82
+ assign x0 = x0a ^ x0b;
83
+ assign x1 = x1a ^ x1b;
84
+ assign x2 = x2a ^ x2b;
85
+ assign x3 = x3a ^ x3b;
86
+ assign x4 = x4a ^ x4b;
87
+ assign x5 = x5a ^ x5b;
88
+ assign x6 = x6a ^ x6b;
89
+ assign x7 = x7a ^ x7b;
90
+ assign x8 = x8a ^ x8b;
91
+ assign x9 = x9a ^ x9b;
92
+ assign x10 = x10a ^ x10b;
93
+ assign x11 = x11a ^ x11b;
94
+ assign x12 = x12a ^ x12b;
95
+ assign x13 = x13a ^ x13b;
96
+ assign x14 = x14a ^ x14b;
97
+ assign y1 = x0;
98
+ assign y2 = x1;
99
+ assign y3 = x2;
100
+ assign y4 = x3;
101
+ assign y5 = x4;
102
+ assign y6 = x5;
103
+ assign y7 = x6;
104
+ assign y8 = x7;
105
+ assign y9 = x8;
106
+ assign y10 = x9;
107
+ assign y11 = x10;
108
+ assign y12 = x11;
109
+ assign y13 = x12;
110
+ assign y14 = x13;
111
+ always @(posedge clk)
112
+ if (rst)
113
+ d0 <= rst_val[0];
114
+ else if (prog)
115
+ d0 <= seed[0];
116
+ else if (en)
117
+ d0 <= x14;
118
+ assign y0 = d0;
119
+ assign x0a = y0;
120
+ assign x14a = y0;
121
+ assign x1a = y1;
122
+ always @(posedge clk)
123
+ if (rst)
124
+ d1 <= rst_val[1];
125
+ else if (prog)
126
+ d1 <= seed[1];
127
+ else if (en)
128
+ d1 <= y1;
129
+ assign x0b = d1;
130
+ assign x2a = y2;
131
+ always @(posedge clk)
132
+ if (rst)
133
+ d2 <= rst_val[2];
134
+ else if (prog)
135
+ d2 <= seed[2];
136
+ else if (en)
137
+ d2 <= y2;
138
+ assign x1b = d2;
139
+ assign x3a = y3;
140
+ always @(posedge clk)
141
+ if (rst)
142
+ d3 <= rst_val[3];
143
+ else if (prog)
144
+ d3 <= seed[3];
145
+ else if (en)
146
+ d3 <= y3;
147
+ assign x2b = d3;
148
+ assign x4a = y4;
149
+ always @(posedge clk)
150
+ if (rst)
151
+ d4 <= rst_val[4];
152
+ else if (prog)
153
+ d4 <= seed[4];
154
+ else if (en)
155
+ d4 <= y4;
156
+ assign x3b = d4;
157
+ assign x5a = y5;
158
+ always @(posedge clk)
159
+ if (rst)
160
+ d5 <= rst_val[5];
161
+ else if (prog)
162
+ d5 <= seed[5];
163
+ else if (en)
164
+ d5 <= y5;
165
+ assign x4b = d5;
166
+ assign x6a = y6;
167
+ always @(posedge clk)
168
+ if (rst)
169
+ d6 <= rst_val[6];
170
+ else if (prog)
171
+ d6 <= seed[6];
172
+ else if (en)
173
+ d6 <= y6;
174
+ assign x5b = d6;
175
+ assign x7a = y7;
176
+ always @(posedge clk)
177
+ if (rst)
178
+ d7 <= rst_val[7];
179
+ else if (prog)
180
+ d7 <= seed[7];
181
+ else if (en)
182
+ d7 <= y7;
183
+ assign x6b = d7;
184
+ assign x8a = y8;
185
+ always @(posedge clk)
186
+ if (rst)
187
+ d8 <= rst_val[8];
188
+ else if (prog)
189
+ d8 <= seed[8];
190
+ else if (en)
191
+ d8 <= y8;
192
+ assign x7b = d8;
193
+ assign x9a = y9;
194
+ always @(posedge clk)
195
+ if (rst)
196
+ d9 <= rst_val[9];
197
+ else if (prog)
198
+ d9 <= seed[9];
199
+ else if (en)
200
+ d9 <= y9;
201
+ assign x8b = d9;
202
+ assign x10a = y10;
203
+ always @(posedge clk)
204
+ if (rst)
205
+ d10 <= rst_val[10];
206
+ else if (prog)
207
+ d10 <= seed[10];
208
+ else if (en)
209
+ d10 <= y10;
210
+ assign x9b = d10;
211
+ assign x11a = y11;
212
+ always @(posedge clk)
213
+ if (rst)
214
+ d11 <= rst_val[11];
215
+ else if (prog)
216
+ d11 <= seed[11];
217
+ else if (en)
218
+ d11 <= y11;
219
+ assign x10b = d11;
220
+ assign x12a = y12;
221
+ always @(posedge clk)
222
+ if (rst)
223
+ d12 <= rst_val[12];
224
+ else if (prog)
225
+ d12 <= seed[12];
226
+ else if (en)
227
+ d12 <= y12;
228
+ assign x11b = d12;
229
+ assign x13a = y13;
230
+ always @(posedge clk)
231
+ if (rst)
232
+ d13 <= rst_val[13];
233
+ else if (prog)
234
+ d13 <= seed[13];
235
+ else if (en)
236
+ d13 <= y13;
237
+ assign x12b = d13;
238
+ assign x14b = y14;
239
+ always @(posedge clk)
240
+ if (rst)
241
+ d14 <= rst_val[14];
242
+ else if (prog)
243
+ d14 <= seed[14];
244
+ else if (en)
245
+ d14 <= y14;
246
+ assign x13b = d14;
247
+
248
+ // Output assignment
249
+ assign out = {y14,y13,y12,y11,y10,y9,y8,y7,y6,y5,y4,y3,y2,y1,y0};
250
+
251
+ endmodule
ChFrenkel_ReckOn/src/lfsr/lfsr_noise_neur.v ADDED
@@ -0,0 +1,366 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "lfsr_noise_neur.v" - Unfolded LFSR module for random noise added to the recurrent neuron membrane potentials
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: This module has been automatically generated by a custom Python script applying the unfolding algorithm to
25
+ // arbitrary LFSRs (k pseudo-random outputs generated at every clock cycle, where k is the unfolding factor), see
26
+ // [C. Frenkel, J.D. Legat and D. Bol, "MorphIC: A 65-nm 738k-synapse/mm² quad-core binary-weight digital
27
+ // neuromorphic processor with stochastic spike-driven online learning", IEEE. Trans. on Biomedical Circuits
28
+ // and Systems, vol. 13, no. 5, pp. 999-1010, 2019]
29
+ // for details of the LFSR unfolding procedure.
30
+ //
31
+ //------------------------------------------------------------------------------
32
+
33
+
34
+ module lfsr_noise_neur (
35
+ // Inputs
36
+ input wire clk,
37
+ input wire rst,
38
+ input wire en,
39
+ input wire [16:0] rst_val,
40
+ input wire [16:0] seed,
41
+ input wire prog,
42
+
43
+ // Output
44
+ output wire [31:0] out
45
+ );
46
+
47
+ // Nodes definitions
48
+ wire x0, x0a, x0b;
49
+ wire x1, x1a, x1b;
50
+ wire x2, x2a, x2b;
51
+ wire x3, x3a, x3b;
52
+ wire x4, x4a, x4b;
53
+ wire x5, x5a, x5b;
54
+ wire x6, x6a, x6b;
55
+ wire x7, x7a, x7b;
56
+ wire x8, x8a, x8b;
57
+ wire x9, x9a, x9b;
58
+ wire x10, x10a, x10b;
59
+ wire x11, x11a, x11b;
60
+ wire x12, x12a, x12b;
61
+ wire x13, x13a, x13b;
62
+ wire x14, x14a, x14b;
63
+ wire x15, x15a, x15b;
64
+ wire x16, x16a, x16b;
65
+ wire x17, x17a, x17b;
66
+ wire x18, x18a, x18b;
67
+ wire x19, x19a, x19b;
68
+ wire x20, x20a, x20b;
69
+ wire x21, x21a, x21b;
70
+ wire x22, x22a, x22b;
71
+ wire x23, x23a, x23b;
72
+ wire x24, x24a, x24b;
73
+ wire x25, x25a, x25b;
74
+ wire x26, x26a, x26b;
75
+ wire x27, x27a, x27b;
76
+ wire x28, x28a, x28b;
77
+ wire x29, x29a, x29b;
78
+ wire x30, x30a, x30b;
79
+ wire x31, x31a, x31b;
80
+ wire y0;
81
+ wire y1;
82
+ wire y2;
83
+ wire y3;
84
+ wire y4;
85
+ wire y5;
86
+ wire y6;
87
+ wire y7;
88
+ wire y8;
89
+ wire y9;
90
+ wire y10;
91
+ wire y11;
92
+ wire y12;
93
+ wire y13;
94
+ wire y14;
95
+ wire y15;
96
+ wire y16;
97
+ wire y17;
98
+ wire y18;
99
+ wire y19;
100
+ wire y20;
101
+ wire y21;
102
+ wire y22;
103
+ wire y23;
104
+ wire y24;
105
+ wire y25;
106
+ wire y26;
107
+ wire y27;
108
+ wire y28;
109
+ wire y29;
110
+ wire y30;
111
+ wire y31;
112
+ reg d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16;
113
+
114
+ // Combinational and sequential logic definitions
115
+ assign x0 = x0a ^ x0b;
116
+ assign x1 = x1a ^ x1b;
117
+ assign x2 = x2a ^ x2b;
118
+ assign x3 = x3a ^ x3b;
119
+ assign x4 = x4a ^ x4b;
120
+ assign x5 = x5a ^ x5b;
121
+ assign x6 = x6a ^ x6b;
122
+ assign x7 = x7a ^ x7b;
123
+ assign x8 = x8a ^ x8b;
124
+ assign x9 = x9a ^ x9b;
125
+ assign x10 = x10a ^ x10b;
126
+ assign x11 = x11a ^ x11b;
127
+ assign x12 = x12a ^ x12b;
128
+ assign x13 = x13a ^ x13b;
129
+ assign x14 = x14a ^ x14b;
130
+ assign x15 = x15a ^ x15b;
131
+ assign x16 = x16a ^ x16b;
132
+ assign x17 = x17a ^ x17b;
133
+ assign x18 = x18a ^ x18b;
134
+ assign x19 = x19a ^ x19b;
135
+ assign x20 = x20a ^ x20b;
136
+ assign x21 = x21a ^ x21b;
137
+ assign x22 = x22a ^ x22b;
138
+ assign x23 = x23a ^ x23b;
139
+ assign x24 = x24a ^ x24b;
140
+ assign x25 = x25a ^ x25b;
141
+ assign x26 = x26a ^ x26b;
142
+ assign x27 = x27a ^ x27b;
143
+ assign x28 = x28a ^ x28b;
144
+ assign x29 = x29a ^ x29b;
145
+ assign x30 = x30a ^ x30b;
146
+ assign x31 = x31a ^ x31b;
147
+ assign y3 = x0;
148
+ assign y4 = x1;
149
+ assign y5 = x2;
150
+ assign y6 = x3;
151
+ assign y7 = x4;
152
+ assign y8 = x5;
153
+ assign y9 = x6;
154
+ assign y10 = x7;
155
+ assign y11 = x8;
156
+ assign y12 = x9;
157
+ assign y13 = x10;
158
+ assign y14 = x11;
159
+ assign y15 = x12;
160
+ assign y16 = x13;
161
+ assign y17 = x14;
162
+ assign y18 = x15;
163
+ assign y19 = x16;
164
+ assign y20 = x17;
165
+ assign y21 = x18;
166
+ assign y22 = x19;
167
+ assign y23 = x20;
168
+ assign y24 = x21;
169
+ assign y25 = x22;
170
+ assign y26 = x23;
171
+ assign y27 = x24;
172
+ assign y28 = x25;
173
+ assign y29 = x26;
174
+ assign y30 = x27;
175
+ assign y31 = x28;
176
+ always @(posedge clk)
177
+ if (rst)
178
+ d0 <= rst_val[0];
179
+ else if (prog)
180
+ d0 <= seed[0];
181
+ else if (en)
182
+ d0 <= x29;
183
+ assign y0 = d0;
184
+ always @(posedge clk)
185
+ if (rst)
186
+ d1 <= rst_val[1];
187
+ else if (prog)
188
+ d1 <= seed[1];
189
+ else if (en)
190
+ d1 <= x30;
191
+ assign y1 = d1;
192
+ always @(posedge clk)
193
+ if (rst)
194
+ d2 <= rst_val[2];
195
+ else if (prog)
196
+ d2 <= seed[2];
197
+ else if (en)
198
+ d2 <= x31;
199
+ assign y2 = d2;
200
+ assign x0a = y0;
201
+ assign x14a = y0;
202
+ assign x1a = y1;
203
+ assign x15a = y1;
204
+ assign x2a = y2;
205
+ assign x16a = y2;
206
+ assign x3a = y3;
207
+ assign x17a = y3;
208
+ assign x4a = y4;
209
+ assign x18a = y4;
210
+ assign x5a = y5;
211
+ assign x19a = y5;
212
+ assign x6a = y6;
213
+ assign x20a = y6;
214
+ assign x7a = y7;
215
+ assign x21a = y7;
216
+ assign x8a = y8;
217
+ assign x22a = y8;
218
+ assign x9a = y9;
219
+ assign x23a = y9;
220
+ assign x10a = y10;
221
+ assign x24a = y10;
222
+ assign x11a = y11;
223
+ assign x25a = y11;
224
+ assign x12a = y12;
225
+ assign x26a = y12;
226
+ assign x13a = y13;
227
+ assign x27a = y13;
228
+ assign x14b = y14;
229
+ assign x28a = y14;
230
+ assign x15b = y15;
231
+ assign x29a = y15;
232
+ assign x16b = y16;
233
+ assign x30a = y16;
234
+ assign x17b = y17;
235
+ assign x31a = y17;
236
+ assign x18b = y18;
237
+ always @(posedge clk)
238
+ if (rst)
239
+ d3 <= rst_val[3];
240
+ else if (prog)
241
+ d3 <= seed[3];
242
+ else if (en)
243
+ d3 <= y18;
244
+ assign x0b = d3;
245
+ assign x19b = y19;
246
+ always @(posedge clk)
247
+ if (rst)
248
+ d4 <= rst_val[4];
249
+ else if (prog)
250
+ d4 <= seed[4];
251
+ else if (en)
252
+ d4 <= y19;
253
+ assign x1b = d4;
254
+ assign x20b = y20;
255
+ always @(posedge clk)
256
+ if (rst)
257
+ d5 <= rst_val[5];
258
+ else if (prog)
259
+ d5 <= seed[5];
260
+ else if (en)
261
+ d5 <= y20;
262
+ assign x2b = d5;
263
+ assign x21b = y21;
264
+ always @(posedge clk)
265
+ if (rst)
266
+ d6 <= rst_val[6];
267
+ else if (prog)
268
+ d6 <= seed[6];
269
+ else if (en)
270
+ d6 <= y21;
271
+ assign x3b = d6;
272
+ assign x22b = y22;
273
+ always @(posedge clk)
274
+ if (rst)
275
+ d7 <= rst_val[7];
276
+ else if (prog)
277
+ d7 <= seed[7];
278
+ else if (en)
279
+ d7 <= y22;
280
+ assign x4b = d7;
281
+ assign x23b = y23;
282
+ always @(posedge clk)
283
+ if (rst)
284
+ d8 <= rst_val[8];
285
+ else if (prog)
286
+ d8 <= seed[8];
287
+ else if (en)
288
+ d8 <= y23;
289
+ assign x5b = d8;
290
+ assign x24b = y24;
291
+ always @(posedge clk)
292
+ if (rst)
293
+ d9 <= rst_val[9];
294
+ else if (prog)
295
+ d9 <= seed[9];
296
+ else if (en)
297
+ d9 <= y24;
298
+ assign x6b = d9;
299
+ assign x25b = y25;
300
+ always @(posedge clk)
301
+ if (rst)
302
+ d10 <= rst_val[10];
303
+ else if (prog)
304
+ d10 <= seed[10];
305
+ else if (en)
306
+ d10 <= y25;
307
+ assign x7b = d10;
308
+ assign x26b = y26;
309
+ always @(posedge clk)
310
+ if (rst)
311
+ d11 <= rst_val[11];
312
+ else if (prog)
313
+ d11 <= seed[11];
314
+ else if (en)
315
+ d11 <= y26;
316
+ assign x8b = d11;
317
+ assign x27b = y27;
318
+ always @(posedge clk)
319
+ if (rst)
320
+ d12 <= rst_val[12];
321
+ else if (prog)
322
+ d12 <= seed[12];
323
+ else if (en)
324
+ d12 <= y27;
325
+ assign x9b = d12;
326
+ assign x28b = y28;
327
+ always @(posedge clk)
328
+ if (rst)
329
+ d13 <= rst_val[13];
330
+ else if (prog)
331
+ d13 <= seed[13];
332
+ else if (en)
333
+ d13 <= y28;
334
+ assign x10b = d13;
335
+ assign x29b = y29;
336
+ always @(posedge clk)
337
+ if (rst)
338
+ d14 <= rst_val[14];
339
+ else if (prog)
340
+ d14 <= seed[14];
341
+ else if (en)
342
+ d14 <= y29;
343
+ assign x11b = d14;
344
+ assign x30b = y30;
345
+ always @(posedge clk)
346
+ if (rst)
347
+ d15 <= rst_val[15];
348
+ else if (prog)
349
+ d15 <= seed[15];
350
+ else if (en)
351
+ d15 <= y30;
352
+ assign x12b = d15;
353
+ assign x31b = y31;
354
+ always @(posedge clk)
355
+ if (rst)
356
+ d16 <= rst_val[16];
357
+ else if (prog)
358
+ d16 <= seed[16];
359
+ else if (en)
360
+ d16 <= y31;
361
+ assign x13b = d16;
362
+
363
+ // Output assignment
364
+ assign out = {y31,y30,y29,y28,y27,y26,y25,y24,y23,y22,y21,y20,y19,y18,y17,y16,y15,y14,y13,y12,y11,y10,y9,y8,y7,y6,y5,y4,y3,y2,y1,y0};
365
+
366
+ endmodule
ChFrenkel_ReckOn/src/lfsr/lfsr_oneur_stochround.v ADDED
@@ -0,0 +1,202 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "lfsr_oneur_stochround.v" - Unfolded LFSR module for stochastic rounding on the output neuron membrane potentials
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: This module has been automatically generated by a custom Python script applying the unfolding algorithm to
25
+ // arbitrary LFSRs (k pseudo-random outputs generated at every clock cycle, where k is the unfolding factor), see
26
+ // [C. Frenkel, J.D. Legat and D. Bol, "MorphIC: A 65-nm 738k-synapse/mm² quad-core binary-weight digital
27
+ // neuromorphic processor with stochastic spike-driven online learning", IEEE. Trans. on Biomedical Circuits
28
+ // and Systems, vol. 13, no. 5, pp. 999-1010, 2019]
29
+ // for details of the LFSR unfolding procedure.
30
+ //
31
+ //------------------------------------------------------------------------------
32
+
33
+
34
+ module lfsr_oneur_stochround (
35
+ // Inputs
36
+ input wire clk,
37
+ input wire rst,
38
+ input wire en,
39
+ input wire [14:0] rst_val,
40
+ input wire [14:0] seed,
41
+ input wire prog,
42
+
43
+ // Output
44
+ output wire [6:0] out
45
+ );
46
+
47
+ // Nodes definitions
48
+ wire x0, x0a, x0b;
49
+ wire x1, x1a, x1b;
50
+ wire x2, x2a, x2b;
51
+ wire x3, x3a, x3b;
52
+ wire x4, x4a, x4b;
53
+ wire x5, x5a, x5b;
54
+ wire x6, x6a, x6b;
55
+ wire y0;
56
+ wire y1;
57
+ wire y2;
58
+ wire y3;
59
+ wire y4;
60
+ wire y5;
61
+ wire y6;
62
+ reg d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14;
63
+
64
+ // Combinational and sequential logic definitions
65
+ assign x0 = x0a ^ x0b;
66
+ assign x1 = x1a ^ x1b;
67
+ assign x2 = x2a ^ x2b;
68
+ assign x3 = x3a ^ x3b;
69
+ assign x4 = x4a ^ x4b;
70
+ assign x5 = x5a ^ x5b;
71
+ assign x6 = x6a ^ x6b;
72
+ assign y1 = x0;
73
+ assign y2 = x1;
74
+ assign y3 = x2;
75
+ assign y4 = x3;
76
+ assign y5 = x4;
77
+ assign y6 = x5;
78
+ always @(posedge clk)
79
+ if (rst)
80
+ d0 <= rst_val[0];
81
+ else if (prog)
82
+ d0 <= seed[0];
83
+ else if (en)
84
+ d0 <= x6;
85
+ assign y0 = d0;
86
+ assign x0a = y0;
87
+ always @(posedge clk)
88
+ if (rst)
89
+ d1 <= rst_val[1];
90
+ else if (prog)
91
+ d1 <= seed[1];
92
+ else if (en)
93
+ d1 <= d2;
94
+ assign x0b = d1;
95
+ always @(posedge clk)
96
+ if (rst)
97
+ d2 <= rst_val[2];
98
+ else if (prog)
99
+ d2 <= seed[2];
100
+ else if (en)
101
+ d2 <= y0;
102
+ assign x1a = y1;
103
+ always @(posedge clk)
104
+ if (rst)
105
+ d3 <= rst_val[3];
106
+ else if (prog)
107
+ d3 <= seed[3];
108
+ else if (en)
109
+ d3 <= d4;
110
+ assign x1b = d3;
111
+ always @(posedge clk)
112
+ if (rst)
113
+ d4 <= rst_val[4];
114
+ else if (prog)
115
+ d4 <= seed[4];
116
+ else if (en)
117
+ d4 <= y1;
118
+ assign x2a = y2;
119
+ always @(posedge clk)
120
+ if (rst)
121
+ d5 <= rst_val[5];
122
+ else if (prog)
123
+ d5 <= seed[5];
124
+ else if (en)
125
+ d5 <= d6;
126
+ assign x2b = d5;
127
+ always @(posedge clk)
128
+ if (rst)
129
+ d6 <= rst_val[6];
130
+ else if (prog)
131
+ d6 <= seed[6];
132
+ else if (en)
133
+ d6 <= y2;
134
+ assign x3a = y3;
135
+ always @(posedge clk)
136
+ if (rst)
137
+ d7 <= rst_val[7];
138
+ else if (prog)
139
+ d7 <= seed[7];
140
+ else if (en)
141
+ d7 <= d8;
142
+ assign x3b = d7;
143
+ always @(posedge clk)
144
+ if (rst)
145
+ d8 <= rst_val[8];
146
+ else if (prog)
147
+ d8 <= seed[8];
148
+ else if (en)
149
+ d8 <= y3;
150
+ assign x4a = y4;
151
+ always @(posedge clk)
152
+ if (rst)
153
+ d9 <= rst_val[9];
154
+ else if (prog)
155
+ d9 <= seed[9];
156
+ else if (en)
157
+ d9 <= d10;
158
+ assign x4b = d9;
159
+ always @(posedge clk)
160
+ if (rst)
161
+ d10 <= rst_val[10];
162
+ else if (prog)
163
+ d10 <= seed[10];
164
+ else if (en)
165
+ d10 <= y4;
166
+ assign x5a = y5;
167
+ always @(posedge clk)
168
+ if (rst)
169
+ d11 <= rst_val[11];
170
+ else if (prog)
171
+ d11 <= seed[11];
172
+ else if (en)
173
+ d11 <= d12;
174
+ assign x5b = d11;
175
+ always @(posedge clk)
176
+ if (rst)
177
+ d12 <= rst_val[12];
178
+ else if (prog)
179
+ d12 <= seed[12];
180
+ else if (en)
181
+ d12 <= y5;
182
+ assign x6a = y6;
183
+ always @(posedge clk)
184
+ if (rst)
185
+ d13 <= rst_val[13];
186
+ else if (prog)
187
+ d13 <= seed[13];
188
+ else if (en)
189
+ d13 <= d14;
190
+ assign x6b = d13;
191
+ always @(posedge clk)
192
+ if (rst)
193
+ d14 <= rst_val[14];
194
+ else if (prog)
195
+ d14 <= seed[14];
196
+ else if (en)
197
+ d14 <= y6;
198
+
199
+ // Output assignment
200
+ assign out = {y6,y5,y4,y3,y2,y1,y0};
201
+
202
+ endmodule
ChFrenkel_ReckOn/src/lfsr/lfsr_winp_wrec.v ADDED
@@ -0,0 +1,3302 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "lfsr_winp_wrec.v" - Unfolded LFSR module for stochastic updates in input and recurrent weights
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: This module has been automatically generated by a custom Python script applying the unfolding algorithm to
25
+ // arbitrary LFSRs (k pseudo-random outputs generated at every clock cycle, where k is the unfolding factor), see
26
+ // [C. Frenkel, J.D. Legat and D. Bol, "MorphIC: A 65-nm 738k-synapse/mm² quad-core binary-weight digital
27
+ // neuromorphic processor with stochastic spike-driven online learning", IEEE. Trans. on Biomedical Circuits
28
+ // and Systems, vol. 13, no. 5, pp. 999-1010, 2019]
29
+ // for details of the LFSR unfolding procedure.
30
+ //
31
+ //------------------------------------------------------------------------------
32
+
33
+
34
+ module lfsr_winp_wrec (
35
+ // Inputs
36
+ input wire clk,
37
+ input wire rst,
38
+ input wire en,
39
+ input wire [24:0] rst_val,
40
+ input wire [24:0] seed,
41
+ input wire prog,
42
+
43
+ // Output
44
+ output wire [511:0] out
45
+ );
46
+
47
+ // Nodes definitions
48
+ wire x0, x0a, x0b;
49
+ wire x1, x1a, x1b;
50
+ wire x2, x2a, x2b;
51
+ wire x3, x3a, x3b;
52
+ wire x4, x4a, x4b;
53
+ wire x5, x5a, x5b;
54
+ wire x6, x6a, x6b;
55
+ wire x7, x7a, x7b;
56
+ wire x8, x8a, x8b;
57
+ wire x9, x9a, x9b;
58
+ wire x10, x10a, x10b;
59
+ wire x11, x11a, x11b;
60
+ wire x12, x12a, x12b;
61
+ wire x13, x13a, x13b;
62
+ wire x14, x14a, x14b;
63
+ wire x15, x15a, x15b;
64
+ wire x16, x16a, x16b;
65
+ wire x17, x17a, x17b;
66
+ wire x18, x18a, x18b;
67
+ wire x19, x19a, x19b;
68
+ wire x20, x20a, x20b;
69
+ wire x21, x21a, x21b;
70
+ wire x22, x22a, x22b;
71
+ wire x23, x23a, x23b;
72
+ wire x24, x24a, x24b;
73
+ wire x25, x25a, x25b;
74
+ wire x26, x26a, x26b;
75
+ wire x27, x27a, x27b;
76
+ wire x28, x28a, x28b;
77
+ wire x29, x29a, x29b;
78
+ wire x30, x30a, x30b;
79
+ wire x31, x31a, x31b;
80
+ wire x32, x32a, x32b;
81
+ wire x33, x33a, x33b;
82
+ wire x34, x34a, x34b;
83
+ wire x35, x35a, x35b;
84
+ wire x36, x36a, x36b;
85
+ wire x37, x37a, x37b;
86
+ wire x38, x38a, x38b;
87
+ wire x39, x39a, x39b;
88
+ wire x40, x40a, x40b;
89
+ wire x41, x41a, x41b;
90
+ wire x42, x42a, x42b;
91
+ wire x43, x43a, x43b;
92
+ wire x44, x44a, x44b;
93
+ wire x45, x45a, x45b;
94
+ wire x46, x46a, x46b;
95
+ wire x47, x47a, x47b;
96
+ wire x48, x48a, x48b;
97
+ wire x49, x49a, x49b;
98
+ wire x50, x50a, x50b;
99
+ wire x51, x51a, x51b;
100
+ wire x52, x52a, x52b;
101
+ wire x53, x53a, x53b;
102
+ wire x54, x54a, x54b;
103
+ wire x55, x55a, x55b;
104
+ wire x56, x56a, x56b;
105
+ wire x57, x57a, x57b;
106
+ wire x58, x58a, x58b;
107
+ wire x59, x59a, x59b;
108
+ wire x60, x60a, x60b;
109
+ wire x61, x61a, x61b;
110
+ wire x62, x62a, x62b;
111
+ wire x63, x63a, x63b;
112
+ wire x64, x64a, x64b;
113
+ wire x65, x65a, x65b;
114
+ wire x66, x66a, x66b;
115
+ wire x67, x67a, x67b;
116
+ wire x68, x68a, x68b;
117
+ wire x69, x69a, x69b;
118
+ wire x70, x70a, x70b;
119
+ wire x71, x71a, x71b;
120
+ wire x72, x72a, x72b;
121
+ wire x73, x73a, x73b;
122
+ wire x74, x74a, x74b;
123
+ wire x75, x75a, x75b;
124
+ wire x76, x76a, x76b;
125
+ wire x77, x77a, x77b;
126
+ wire x78, x78a, x78b;
127
+ wire x79, x79a, x79b;
128
+ wire x80, x80a, x80b;
129
+ wire x81, x81a, x81b;
130
+ wire x82, x82a, x82b;
131
+ wire x83, x83a, x83b;
132
+ wire x84, x84a, x84b;
133
+ wire x85, x85a, x85b;
134
+ wire x86, x86a, x86b;
135
+ wire x87, x87a, x87b;
136
+ wire x88, x88a, x88b;
137
+ wire x89, x89a, x89b;
138
+ wire x90, x90a, x90b;
139
+ wire x91, x91a, x91b;
140
+ wire x92, x92a, x92b;
141
+ wire x93, x93a, x93b;
142
+ wire x94, x94a, x94b;
143
+ wire x95, x95a, x95b;
144
+ wire x96, x96a, x96b;
145
+ wire x97, x97a, x97b;
146
+ wire x98, x98a, x98b;
147
+ wire x99, x99a, x99b;
148
+ wire x100, x100a, x100b;
149
+ wire x101, x101a, x101b;
150
+ wire x102, x102a, x102b;
151
+ wire x103, x103a, x103b;
152
+ wire x104, x104a, x104b;
153
+ wire x105, x105a, x105b;
154
+ wire x106, x106a, x106b;
155
+ wire x107, x107a, x107b;
156
+ wire x108, x108a, x108b;
157
+ wire x109, x109a, x109b;
158
+ wire x110, x110a, x110b;
159
+ wire x111, x111a, x111b;
160
+ wire x112, x112a, x112b;
161
+ wire x113, x113a, x113b;
162
+ wire x114, x114a, x114b;
163
+ wire x115, x115a, x115b;
164
+ wire x116, x116a, x116b;
165
+ wire x117, x117a, x117b;
166
+ wire x118, x118a, x118b;
167
+ wire x119, x119a, x119b;
168
+ wire x120, x120a, x120b;
169
+ wire x121, x121a, x121b;
170
+ wire x122, x122a, x122b;
171
+ wire x123, x123a, x123b;
172
+ wire x124, x124a, x124b;
173
+ wire x125, x125a, x125b;
174
+ wire x126, x126a, x126b;
175
+ wire x127, x127a, x127b;
176
+ wire x128, x128a, x128b;
177
+ wire x129, x129a, x129b;
178
+ wire x130, x130a, x130b;
179
+ wire x131, x131a, x131b;
180
+ wire x132, x132a, x132b;
181
+ wire x133, x133a, x133b;
182
+ wire x134, x134a, x134b;
183
+ wire x135, x135a, x135b;
184
+ wire x136, x136a, x136b;
185
+ wire x137, x137a, x137b;
186
+ wire x138, x138a, x138b;
187
+ wire x139, x139a, x139b;
188
+ wire x140, x140a, x140b;
189
+ wire x141, x141a, x141b;
190
+ wire x142, x142a, x142b;
191
+ wire x143, x143a, x143b;
192
+ wire x144, x144a, x144b;
193
+ wire x145, x145a, x145b;
194
+ wire x146, x146a, x146b;
195
+ wire x147, x147a, x147b;
196
+ wire x148, x148a, x148b;
197
+ wire x149, x149a, x149b;
198
+ wire x150, x150a, x150b;
199
+ wire x151, x151a, x151b;
200
+ wire x152, x152a, x152b;
201
+ wire x153, x153a, x153b;
202
+ wire x154, x154a, x154b;
203
+ wire x155, x155a, x155b;
204
+ wire x156, x156a, x156b;
205
+ wire x157, x157a, x157b;
206
+ wire x158, x158a, x158b;
207
+ wire x159, x159a, x159b;
208
+ wire x160, x160a, x160b;
209
+ wire x161, x161a, x161b;
210
+ wire x162, x162a, x162b;
211
+ wire x163, x163a, x163b;
212
+ wire x164, x164a, x164b;
213
+ wire x165, x165a, x165b;
214
+ wire x166, x166a, x166b;
215
+ wire x167, x167a, x167b;
216
+ wire x168, x168a, x168b;
217
+ wire x169, x169a, x169b;
218
+ wire x170, x170a, x170b;
219
+ wire x171, x171a, x171b;
220
+ wire x172, x172a, x172b;
221
+ wire x173, x173a, x173b;
222
+ wire x174, x174a, x174b;
223
+ wire x175, x175a, x175b;
224
+ wire x176, x176a, x176b;
225
+ wire x177, x177a, x177b;
226
+ wire x178, x178a, x178b;
227
+ wire x179, x179a, x179b;
228
+ wire x180, x180a, x180b;
229
+ wire x181, x181a, x181b;
230
+ wire x182, x182a, x182b;
231
+ wire x183, x183a, x183b;
232
+ wire x184, x184a, x184b;
233
+ wire x185, x185a, x185b;
234
+ wire x186, x186a, x186b;
235
+ wire x187, x187a, x187b;
236
+ wire x188, x188a, x188b;
237
+ wire x189, x189a, x189b;
238
+ wire x190, x190a, x190b;
239
+ wire x191, x191a, x191b;
240
+ wire x192, x192a, x192b;
241
+ wire x193, x193a, x193b;
242
+ wire x194, x194a, x194b;
243
+ wire x195, x195a, x195b;
244
+ wire x196, x196a, x196b;
245
+ wire x197, x197a, x197b;
246
+ wire x198, x198a, x198b;
247
+ wire x199, x199a, x199b;
248
+ wire x200, x200a, x200b;
249
+ wire x201, x201a, x201b;
250
+ wire x202, x202a, x202b;
251
+ wire x203, x203a, x203b;
252
+ wire x204, x204a, x204b;
253
+ wire x205, x205a, x205b;
254
+ wire x206, x206a, x206b;
255
+ wire x207, x207a, x207b;
256
+ wire x208, x208a, x208b;
257
+ wire x209, x209a, x209b;
258
+ wire x210, x210a, x210b;
259
+ wire x211, x211a, x211b;
260
+ wire x212, x212a, x212b;
261
+ wire x213, x213a, x213b;
262
+ wire x214, x214a, x214b;
263
+ wire x215, x215a, x215b;
264
+ wire x216, x216a, x216b;
265
+ wire x217, x217a, x217b;
266
+ wire x218, x218a, x218b;
267
+ wire x219, x219a, x219b;
268
+ wire x220, x220a, x220b;
269
+ wire x221, x221a, x221b;
270
+ wire x222, x222a, x222b;
271
+ wire x223, x223a, x223b;
272
+ wire x224, x224a, x224b;
273
+ wire x225, x225a, x225b;
274
+ wire x226, x226a, x226b;
275
+ wire x227, x227a, x227b;
276
+ wire x228, x228a, x228b;
277
+ wire x229, x229a, x229b;
278
+ wire x230, x230a, x230b;
279
+ wire x231, x231a, x231b;
280
+ wire x232, x232a, x232b;
281
+ wire x233, x233a, x233b;
282
+ wire x234, x234a, x234b;
283
+ wire x235, x235a, x235b;
284
+ wire x236, x236a, x236b;
285
+ wire x237, x237a, x237b;
286
+ wire x238, x238a, x238b;
287
+ wire x239, x239a, x239b;
288
+ wire x240, x240a, x240b;
289
+ wire x241, x241a, x241b;
290
+ wire x242, x242a, x242b;
291
+ wire x243, x243a, x243b;
292
+ wire x244, x244a, x244b;
293
+ wire x245, x245a, x245b;
294
+ wire x246, x246a, x246b;
295
+ wire x247, x247a, x247b;
296
+ wire x248, x248a, x248b;
297
+ wire x249, x249a, x249b;
298
+ wire x250, x250a, x250b;
299
+ wire x251, x251a, x251b;
300
+ wire x252, x252a, x252b;
301
+ wire x253, x253a, x253b;
302
+ wire x254, x254a, x254b;
303
+ wire x255, x255a, x255b;
304
+ wire x256, x256a, x256b;
305
+ wire x257, x257a, x257b;
306
+ wire x258, x258a, x258b;
307
+ wire x259, x259a, x259b;
308
+ wire x260, x260a, x260b;
309
+ wire x261, x261a, x261b;
310
+ wire x262, x262a, x262b;
311
+ wire x263, x263a, x263b;
312
+ wire x264, x264a, x264b;
313
+ wire x265, x265a, x265b;
314
+ wire x266, x266a, x266b;
315
+ wire x267, x267a, x267b;
316
+ wire x268, x268a, x268b;
317
+ wire x269, x269a, x269b;
318
+ wire x270, x270a, x270b;
319
+ wire x271, x271a, x271b;
320
+ wire x272, x272a, x272b;
321
+ wire x273, x273a, x273b;
322
+ wire x274, x274a, x274b;
323
+ wire x275, x275a, x275b;
324
+ wire x276, x276a, x276b;
325
+ wire x277, x277a, x277b;
326
+ wire x278, x278a, x278b;
327
+ wire x279, x279a, x279b;
328
+ wire x280, x280a, x280b;
329
+ wire x281, x281a, x281b;
330
+ wire x282, x282a, x282b;
331
+ wire x283, x283a, x283b;
332
+ wire x284, x284a, x284b;
333
+ wire x285, x285a, x285b;
334
+ wire x286, x286a, x286b;
335
+ wire x287, x287a, x287b;
336
+ wire x288, x288a, x288b;
337
+ wire x289, x289a, x289b;
338
+ wire x290, x290a, x290b;
339
+ wire x291, x291a, x291b;
340
+ wire x292, x292a, x292b;
341
+ wire x293, x293a, x293b;
342
+ wire x294, x294a, x294b;
343
+ wire x295, x295a, x295b;
344
+ wire x296, x296a, x296b;
345
+ wire x297, x297a, x297b;
346
+ wire x298, x298a, x298b;
347
+ wire x299, x299a, x299b;
348
+ wire x300, x300a, x300b;
349
+ wire x301, x301a, x301b;
350
+ wire x302, x302a, x302b;
351
+ wire x303, x303a, x303b;
352
+ wire x304, x304a, x304b;
353
+ wire x305, x305a, x305b;
354
+ wire x306, x306a, x306b;
355
+ wire x307, x307a, x307b;
356
+ wire x308, x308a, x308b;
357
+ wire x309, x309a, x309b;
358
+ wire x310, x310a, x310b;
359
+ wire x311, x311a, x311b;
360
+ wire x312, x312a, x312b;
361
+ wire x313, x313a, x313b;
362
+ wire x314, x314a, x314b;
363
+ wire x315, x315a, x315b;
364
+ wire x316, x316a, x316b;
365
+ wire x317, x317a, x317b;
366
+ wire x318, x318a, x318b;
367
+ wire x319, x319a, x319b;
368
+ wire x320, x320a, x320b;
369
+ wire x321, x321a, x321b;
370
+ wire x322, x322a, x322b;
371
+ wire x323, x323a, x323b;
372
+ wire x324, x324a, x324b;
373
+ wire x325, x325a, x325b;
374
+ wire x326, x326a, x326b;
375
+ wire x327, x327a, x327b;
376
+ wire x328, x328a, x328b;
377
+ wire x329, x329a, x329b;
378
+ wire x330, x330a, x330b;
379
+ wire x331, x331a, x331b;
380
+ wire x332, x332a, x332b;
381
+ wire x333, x333a, x333b;
382
+ wire x334, x334a, x334b;
383
+ wire x335, x335a, x335b;
384
+ wire x336, x336a, x336b;
385
+ wire x337, x337a, x337b;
386
+ wire x338, x338a, x338b;
387
+ wire x339, x339a, x339b;
388
+ wire x340, x340a, x340b;
389
+ wire x341, x341a, x341b;
390
+ wire x342, x342a, x342b;
391
+ wire x343, x343a, x343b;
392
+ wire x344, x344a, x344b;
393
+ wire x345, x345a, x345b;
394
+ wire x346, x346a, x346b;
395
+ wire x347, x347a, x347b;
396
+ wire x348, x348a, x348b;
397
+ wire x349, x349a, x349b;
398
+ wire x350, x350a, x350b;
399
+ wire x351, x351a, x351b;
400
+ wire x352, x352a, x352b;
401
+ wire x353, x353a, x353b;
402
+ wire x354, x354a, x354b;
403
+ wire x355, x355a, x355b;
404
+ wire x356, x356a, x356b;
405
+ wire x357, x357a, x357b;
406
+ wire x358, x358a, x358b;
407
+ wire x359, x359a, x359b;
408
+ wire x360, x360a, x360b;
409
+ wire x361, x361a, x361b;
410
+ wire x362, x362a, x362b;
411
+ wire x363, x363a, x363b;
412
+ wire x364, x364a, x364b;
413
+ wire x365, x365a, x365b;
414
+ wire x366, x366a, x366b;
415
+ wire x367, x367a, x367b;
416
+ wire x368, x368a, x368b;
417
+ wire x369, x369a, x369b;
418
+ wire x370, x370a, x370b;
419
+ wire x371, x371a, x371b;
420
+ wire x372, x372a, x372b;
421
+ wire x373, x373a, x373b;
422
+ wire x374, x374a, x374b;
423
+ wire x375, x375a, x375b;
424
+ wire x376, x376a, x376b;
425
+ wire x377, x377a, x377b;
426
+ wire x378, x378a, x378b;
427
+ wire x379, x379a, x379b;
428
+ wire x380, x380a, x380b;
429
+ wire x381, x381a, x381b;
430
+ wire x382, x382a, x382b;
431
+ wire x383, x383a, x383b;
432
+ wire x384, x384a, x384b;
433
+ wire x385, x385a, x385b;
434
+ wire x386, x386a, x386b;
435
+ wire x387, x387a, x387b;
436
+ wire x388, x388a, x388b;
437
+ wire x389, x389a, x389b;
438
+ wire x390, x390a, x390b;
439
+ wire x391, x391a, x391b;
440
+ wire x392, x392a, x392b;
441
+ wire x393, x393a, x393b;
442
+ wire x394, x394a, x394b;
443
+ wire x395, x395a, x395b;
444
+ wire x396, x396a, x396b;
445
+ wire x397, x397a, x397b;
446
+ wire x398, x398a, x398b;
447
+ wire x399, x399a, x399b;
448
+ wire x400, x400a, x400b;
449
+ wire x401, x401a, x401b;
450
+ wire x402, x402a, x402b;
451
+ wire x403, x403a, x403b;
452
+ wire x404, x404a, x404b;
453
+ wire x405, x405a, x405b;
454
+ wire x406, x406a, x406b;
455
+ wire x407, x407a, x407b;
456
+ wire x408, x408a, x408b;
457
+ wire x409, x409a, x409b;
458
+ wire x410, x410a, x410b;
459
+ wire x411, x411a, x411b;
460
+ wire x412, x412a, x412b;
461
+ wire x413, x413a, x413b;
462
+ wire x414, x414a, x414b;
463
+ wire x415, x415a, x415b;
464
+ wire x416, x416a, x416b;
465
+ wire x417, x417a, x417b;
466
+ wire x418, x418a, x418b;
467
+ wire x419, x419a, x419b;
468
+ wire x420, x420a, x420b;
469
+ wire x421, x421a, x421b;
470
+ wire x422, x422a, x422b;
471
+ wire x423, x423a, x423b;
472
+ wire x424, x424a, x424b;
473
+ wire x425, x425a, x425b;
474
+ wire x426, x426a, x426b;
475
+ wire x427, x427a, x427b;
476
+ wire x428, x428a, x428b;
477
+ wire x429, x429a, x429b;
478
+ wire x430, x430a, x430b;
479
+ wire x431, x431a, x431b;
480
+ wire x432, x432a, x432b;
481
+ wire x433, x433a, x433b;
482
+ wire x434, x434a, x434b;
483
+ wire x435, x435a, x435b;
484
+ wire x436, x436a, x436b;
485
+ wire x437, x437a, x437b;
486
+ wire x438, x438a, x438b;
487
+ wire x439, x439a, x439b;
488
+ wire x440, x440a, x440b;
489
+ wire x441, x441a, x441b;
490
+ wire x442, x442a, x442b;
491
+ wire x443, x443a, x443b;
492
+ wire x444, x444a, x444b;
493
+ wire x445, x445a, x445b;
494
+ wire x446, x446a, x446b;
495
+ wire x447, x447a, x447b;
496
+ wire x448, x448a, x448b;
497
+ wire x449, x449a, x449b;
498
+ wire x450, x450a, x450b;
499
+ wire x451, x451a, x451b;
500
+ wire x452, x452a, x452b;
501
+ wire x453, x453a, x453b;
502
+ wire x454, x454a, x454b;
503
+ wire x455, x455a, x455b;
504
+ wire x456, x456a, x456b;
505
+ wire x457, x457a, x457b;
506
+ wire x458, x458a, x458b;
507
+ wire x459, x459a, x459b;
508
+ wire x460, x460a, x460b;
509
+ wire x461, x461a, x461b;
510
+ wire x462, x462a, x462b;
511
+ wire x463, x463a, x463b;
512
+ wire x464, x464a, x464b;
513
+ wire x465, x465a, x465b;
514
+ wire x466, x466a, x466b;
515
+ wire x467, x467a, x467b;
516
+ wire x468, x468a, x468b;
517
+ wire x469, x469a, x469b;
518
+ wire x470, x470a, x470b;
519
+ wire x471, x471a, x471b;
520
+ wire x472, x472a, x472b;
521
+ wire x473, x473a, x473b;
522
+ wire x474, x474a, x474b;
523
+ wire x475, x475a, x475b;
524
+ wire x476, x476a, x476b;
525
+ wire x477, x477a, x477b;
526
+ wire x478, x478a, x478b;
527
+ wire x479, x479a, x479b;
528
+ wire x480, x480a, x480b;
529
+ wire x481, x481a, x481b;
530
+ wire x482, x482a, x482b;
531
+ wire x483, x483a, x483b;
532
+ wire x484, x484a, x484b;
533
+ wire x485, x485a, x485b;
534
+ wire x486, x486a, x486b;
535
+ wire x487, x487a, x487b;
536
+ wire x488, x488a, x488b;
537
+ wire x489, x489a, x489b;
538
+ wire x490, x490a, x490b;
539
+ wire x491, x491a, x491b;
540
+ wire x492, x492a, x492b;
541
+ wire x493, x493a, x493b;
542
+ wire x494, x494a, x494b;
543
+ wire x495, x495a, x495b;
544
+ wire x496, x496a, x496b;
545
+ wire x497, x497a, x497b;
546
+ wire x498, x498a, x498b;
547
+ wire x499, x499a, x499b;
548
+ wire x500, x500a, x500b;
549
+ wire x501, x501a, x501b;
550
+ wire x502, x502a, x502b;
551
+ wire x503, x503a, x503b;
552
+ wire x504, x504a, x504b;
553
+ wire x505, x505a, x505b;
554
+ wire x506, x506a, x506b;
555
+ wire x507, x507a, x507b;
556
+ wire x508, x508a, x508b;
557
+ wire x509, x509a, x509b;
558
+ wire x510, x510a, x510b;
559
+ wire x511, x511a, x511b;
560
+ wire y0;
561
+ wire y1;
562
+ wire y2;
563
+ wire y3;
564
+ wire y4;
565
+ wire y5;
566
+ wire y6;
567
+ wire y7;
568
+ wire y8;
569
+ wire y9;
570
+ wire y10;
571
+ wire y11;
572
+ wire y12;
573
+ wire y13;
574
+ wire y14;
575
+ wire y15;
576
+ wire y16;
577
+ wire y17;
578
+ wire y18;
579
+ wire y19;
580
+ wire y20;
581
+ wire y21;
582
+ wire y22;
583
+ wire y23;
584
+ wire y24;
585
+ wire y25;
586
+ wire y26;
587
+ wire y27;
588
+ wire y28;
589
+ wire y29;
590
+ wire y30;
591
+ wire y31;
592
+ wire y32;
593
+ wire y33;
594
+ wire y34;
595
+ wire y35;
596
+ wire y36;
597
+ wire y37;
598
+ wire y38;
599
+ wire y39;
600
+ wire y40;
601
+ wire y41;
602
+ wire y42;
603
+ wire y43;
604
+ wire y44;
605
+ wire y45;
606
+ wire y46;
607
+ wire y47;
608
+ wire y48;
609
+ wire y49;
610
+ wire y50;
611
+ wire y51;
612
+ wire y52;
613
+ wire y53;
614
+ wire y54;
615
+ wire y55;
616
+ wire y56;
617
+ wire y57;
618
+ wire y58;
619
+ wire y59;
620
+ wire y60;
621
+ wire y61;
622
+ wire y62;
623
+ wire y63;
624
+ wire y64;
625
+ wire y65;
626
+ wire y66;
627
+ wire y67;
628
+ wire y68;
629
+ wire y69;
630
+ wire y70;
631
+ wire y71;
632
+ wire y72;
633
+ wire y73;
634
+ wire y74;
635
+ wire y75;
636
+ wire y76;
637
+ wire y77;
638
+ wire y78;
639
+ wire y79;
640
+ wire y80;
641
+ wire y81;
642
+ wire y82;
643
+ wire y83;
644
+ wire y84;
645
+ wire y85;
646
+ wire y86;
647
+ wire y87;
648
+ wire y88;
649
+ wire y89;
650
+ wire y90;
651
+ wire y91;
652
+ wire y92;
653
+ wire y93;
654
+ wire y94;
655
+ wire y95;
656
+ wire y96;
657
+ wire y97;
658
+ wire y98;
659
+ wire y99;
660
+ wire y100;
661
+ wire y101;
662
+ wire y102;
663
+ wire y103;
664
+ wire y104;
665
+ wire y105;
666
+ wire y106;
667
+ wire y107;
668
+ wire y108;
669
+ wire y109;
670
+ wire y110;
671
+ wire y111;
672
+ wire y112;
673
+ wire y113;
674
+ wire y114;
675
+ wire y115;
676
+ wire y116;
677
+ wire y117;
678
+ wire y118;
679
+ wire y119;
680
+ wire y120;
681
+ wire y121;
682
+ wire y122;
683
+ wire y123;
684
+ wire y124;
685
+ wire y125;
686
+ wire y126;
687
+ wire y127;
688
+ wire y128;
689
+ wire y129;
690
+ wire y130;
691
+ wire y131;
692
+ wire y132;
693
+ wire y133;
694
+ wire y134;
695
+ wire y135;
696
+ wire y136;
697
+ wire y137;
698
+ wire y138;
699
+ wire y139;
700
+ wire y140;
701
+ wire y141;
702
+ wire y142;
703
+ wire y143;
704
+ wire y144;
705
+ wire y145;
706
+ wire y146;
707
+ wire y147;
708
+ wire y148;
709
+ wire y149;
710
+ wire y150;
711
+ wire y151;
712
+ wire y152;
713
+ wire y153;
714
+ wire y154;
715
+ wire y155;
716
+ wire y156;
717
+ wire y157;
718
+ wire y158;
719
+ wire y159;
720
+ wire y160;
721
+ wire y161;
722
+ wire y162;
723
+ wire y163;
724
+ wire y164;
725
+ wire y165;
726
+ wire y166;
727
+ wire y167;
728
+ wire y168;
729
+ wire y169;
730
+ wire y170;
731
+ wire y171;
732
+ wire y172;
733
+ wire y173;
734
+ wire y174;
735
+ wire y175;
736
+ wire y176;
737
+ wire y177;
738
+ wire y178;
739
+ wire y179;
740
+ wire y180;
741
+ wire y181;
742
+ wire y182;
743
+ wire y183;
744
+ wire y184;
745
+ wire y185;
746
+ wire y186;
747
+ wire y187;
748
+ wire y188;
749
+ wire y189;
750
+ wire y190;
751
+ wire y191;
752
+ wire y192;
753
+ wire y193;
754
+ wire y194;
755
+ wire y195;
756
+ wire y196;
757
+ wire y197;
758
+ wire y198;
759
+ wire y199;
760
+ wire y200;
761
+ wire y201;
762
+ wire y202;
763
+ wire y203;
764
+ wire y204;
765
+ wire y205;
766
+ wire y206;
767
+ wire y207;
768
+ wire y208;
769
+ wire y209;
770
+ wire y210;
771
+ wire y211;
772
+ wire y212;
773
+ wire y213;
774
+ wire y214;
775
+ wire y215;
776
+ wire y216;
777
+ wire y217;
778
+ wire y218;
779
+ wire y219;
780
+ wire y220;
781
+ wire y221;
782
+ wire y222;
783
+ wire y223;
784
+ wire y224;
785
+ wire y225;
786
+ wire y226;
787
+ wire y227;
788
+ wire y228;
789
+ wire y229;
790
+ wire y230;
791
+ wire y231;
792
+ wire y232;
793
+ wire y233;
794
+ wire y234;
795
+ wire y235;
796
+ wire y236;
797
+ wire y237;
798
+ wire y238;
799
+ wire y239;
800
+ wire y240;
801
+ wire y241;
802
+ wire y242;
803
+ wire y243;
804
+ wire y244;
805
+ wire y245;
806
+ wire y246;
807
+ wire y247;
808
+ wire y248;
809
+ wire y249;
810
+ wire y250;
811
+ wire y251;
812
+ wire y252;
813
+ wire y253;
814
+ wire y254;
815
+ wire y255;
816
+ wire y256;
817
+ wire y257;
818
+ wire y258;
819
+ wire y259;
820
+ wire y260;
821
+ wire y261;
822
+ wire y262;
823
+ wire y263;
824
+ wire y264;
825
+ wire y265;
826
+ wire y266;
827
+ wire y267;
828
+ wire y268;
829
+ wire y269;
830
+ wire y270;
831
+ wire y271;
832
+ wire y272;
833
+ wire y273;
834
+ wire y274;
835
+ wire y275;
836
+ wire y276;
837
+ wire y277;
838
+ wire y278;
839
+ wire y279;
840
+ wire y280;
841
+ wire y281;
842
+ wire y282;
843
+ wire y283;
844
+ wire y284;
845
+ wire y285;
846
+ wire y286;
847
+ wire y287;
848
+ wire y288;
849
+ wire y289;
850
+ wire y290;
851
+ wire y291;
852
+ wire y292;
853
+ wire y293;
854
+ wire y294;
855
+ wire y295;
856
+ wire y296;
857
+ wire y297;
858
+ wire y298;
859
+ wire y299;
860
+ wire y300;
861
+ wire y301;
862
+ wire y302;
863
+ wire y303;
864
+ wire y304;
865
+ wire y305;
866
+ wire y306;
867
+ wire y307;
868
+ wire y308;
869
+ wire y309;
870
+ wire y310;
871
+ wire y311;
872
+ wire y312;
873
+ wire y313;
874
+ wire y314;
875
+ wire y315;
876
+ wire y316;
877
+ wire y317;
878
+ wire y318;
879
+ wire y319;
880
+ wire y320;
881
+ wire y321;
882
+ wire y322;
883
+ wire y323;
884
+ wire y324;
885
+ wire y325;
886
+ wire y326;
887
+ wire y327;
888
+ wire y328;
889
+ wire y329;
890
+ wire y330;
891
+ wire y331;
892
+ wire y332;
893
+ wire y333;
894
+ wire y334;
895
+ wire y335;
896
+ wire y336;
897
+ wire y337;
898
+ wire y338;
899
+ wire y339;
900
+ wire y340;
901
+ wire y341;
902
+ wire y342;
903
+ wire y343;
904
+ wire y344;
905
+ wire y345;
906
+ wire y346;
907
+ wire y347;
908
+ wire y348;
909
+ wire y349;
910
+ wire y350;
911
+ wire y351;
912
+ wire y352;
913
+ wire y353;
914
+ wire y354;
915
+ wire y355;
916
+ wire y356;
917
+ wire y357;
918
+ wire y358;
919
+ wire y359;
920
+ wire y360;
921
+ wire y361;
922
+ wire y362;
923
+ wire y363;
924
+ wire y364;
925
+ wire y365;
926
+ wire y366;
927
+ wire y367;
928
+ wire y368;
929
+ wire y369;
930
+ wire y370;
931
+ wire y371;
932
+ wire y372;
933
+ wire y373;
934
+ wire y374;
935
+ wire y375;
936
+ wire y376;
937
+ wire y377;
938
+ wire y378;
939
+ wire y379;
940
+ wire y380;
941
+ wire y381;
942
+ wire y382;
943
+ wire y383;
944
+ wire y384;
945
+ wire y385;
946
+ wire y386;
947
+ wire y387;
948
+ wire y388;
949
+ wire y389;
950
+ wire y390;
951
+ wire y391;
952
+ wire y392;
953
+ wire y393;
954
+ wire y394;
955
+ wire y395;
956
+ wire y396;
957
+ wire y397;
958
+ wire y398;
959
+ wire y399;
960
+ wire y400;
961
+ wire y401;
962
+ wire y402;
963
+ wire y403;
964
+ wire y404;
965
+ wire y405;
966
+ wire y406;
967
+ wire y407;
968
+ wire y408;
969
+ wire y409;
970
+ wire y410;
971
+ wire y411;
972
+ wire y412;
973
+ wire y413;
974
+ wire y414;
975
+ wire y415;
976
+ wire y416;
977
+ wire y417;
978
+ wire y418;
979
+ wire y419;
980
+ wire y420;
981
+ wire y421;
982
+ wire y422;
983
+ wire y423;
984
+ wire y424;
985
+ wire y425;
986
+ wire y426;
987
+ wire y427;
988
+ wire y428;
989
+ wire y429;
990
+ wire y430;
991
+ wire y431;
992
+ wire y432;
993
+ wire y433;
994
+ wire y434;
995
+ wire y435;
996
+ wire y436;
997
+ wire y437;
998
+ wire y438;
999
+ wire y439;
1000
+ wire y440;
1001
+ wire y441;
1002
+ wire y442;
1003
+ wire y443;
1004
+ wire y444;
1005
+ wire y445;
1006
+ wire y446;
1007
+ wire y447;
1008
+ wire y448;
1009
+ wire y449;
1010
+ wire y450;
1011
+ wire y451;
1012
+ wire y452;
1013
+ wire y453;
1014
+ wire y454;
1015
+ wire y455;
1016
+ wire y456;
1017
+ wire y457;
1018
+ wire y458;
1019
+ wire y459;
1020
+ wire y460;
1021
+ wire y461;
1022
+ wire y462;
1023
+ wire y463;
1024
+ wire y464;
1025
+ wire y465;
1026
+ wire y466;
1027
+ wire y467;
1028
+ wire y468;
1029
+ wire y469;
1030
+ wire y470;
1031
+ wire y471;
1032
+ wire y472;
1033
+ wire y473;
1034
+ wire y474;
1035
+ wire y475;
1036
+ wire y476;
1037
+ wire y477;
1038
+ wire y478;
1039
+ wire y479;
1040
+ wire y480;
1041
+ wire y481;
1042
+ wire y482;
1043
+ wire y483;
1044
+ wire y484;
1045
+ wire y485;
1046
+ wire y486;
1047
+ wire y487;
1048
+ wire y488;
1049
+ wire y489;
1050
+ wire y490;
1051
+ wire y491;
1052
+ wire y492;
1053
+ wire y493;
1054
+ wire y494;
1055
+ wire y495;
1056
+ wire y496;
1057
+ wire y497;
1058
+ wire y498;
1059
+ wire y499;
1060
+ wire y500;
1061
+ wire y501;
1062
+ wire y502;
1063
+ wire y503;
1064
+ wire y504;
1065
+ wire y505;
1066
+ wire y506;
1067
+ wire y507;
1068
+ wire y508;
1069
+ wire y509;
1070
+ wire y510;
1071
+ wire y511;
1072
+ reg d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21, d22, d23, d24;
1073
+
1074
+ // Combinational and sequential logic definitions
1075
+ assign x0 = x0a ^ x0b;
1076
+ assign x1 = x1a ^ x1b;
1077
+ assign x2 = x2a ^ x2b;
1078
+ assign x3 = x3a ^ x3b;
1079
+ assign x4 = x4a ^ x4b;
1080
+ assign x5 = x5a ^ x5b;
1081
+ assign x6 = x6a ^ x6b;
1082
+ assign x7 = x7a ^ x7b;
1083
+ assign x8 = x8a ^ x8b;
1084
+ assign x9 = x9a ^ x9b;
1085
+ assign x10 = x10a ^ x10b;
1086
+ assign x11 = x11a ^ x11b;
1087
+ assign x12 = x12a ^ x12b;
1088
+ assign x13 = x13a ^ x13b;
1089
+ assign x14 = x14a ^ x14b;
1090
+ assign x15 = x15a ^ x15b;
1091
+ assign x16 = x16a ^ x16b;
1092
+ assign x17 = x17a ^ x17b;
1093
+ assign x18 = x18a ^ x18b;
1094
+ assign x19 = x19a ^ x19b;
1095
+ assign x20 = x20a ^ x20b;
1096
+ assign x21 = x21a ^ x21b;
1097
+ assign x22 = x22a ^ x22b;
1098
+ assign x23 = x23a ^ x23b;
1099
+ assign x24 = x24a ^ x24b;
1100
+ assign x25 = x25a ^ x25b;
1101
+ assign x26 = x26a ^ x26b;
1102
+ assign x27 = x27a ^ x27b;
1103
+ assign x28 = x28a ^ x28b;
1104
+ assign x29 = x29a ^ x29b;
1105
+ assign x30 = x30a ^ x30b;
1106
+ assign x31 = x31a ^ x31b;
1107
+ assign x32 = x32a ^ x32b;
1108
+ assign x33 = x33a ^ x33b;
1109
+ assign x34 = x34a ^ x34b;
1110
+ assign x35 = x35a ^ x35b;
1111
+ assign x36 = x36a ^ x36b;
1112
+ assign x37 = x37a ^ x37b;
1113
+ assign x38 = x38a ^ x38b;
1114
+ assign x39 = x39a ^ x39b;
1115
+ assign x40 = x40a ^ x40b;
1116
+ assign x41 = x41a ^ x41b;
1117
+ assign x42 = x42a ^ x42b;
1118
+ assign x43 = x43a ^ x43b;
1119
+ assign x44 = x44a ^ x44b;
1120
+ assign x45 = x45a ^ x45b;
1121
+ assign x46 = x46a ^ x46b;
1122
+ assign x47 = x47a ^ x47b;
1123
+ assign x48 = x48a ^ x48b;
1124
+ assign x49 = x49a ^ x49b;
1125
+ assign x50 = x50a ^ x50b;
1126
+ assign x51 = x51a ^ x51b;
1127
+ assign x52 = x52a ^ x52b;
1128
+ assign x53 = x53a ^ x53b;
1129
+ assign x54 = x54a ^ x54b;
1130
+ assign x55 = x55a ^ x55b;
1131
+ assign x56 = x56a ^ x56b;
1132
+ assign x57 = x57a ^ x57b;
1133
+ assign x58 = x58a ^ x58b;
1134
+ assign x59 = x59a ^ x59b;
1135
+ assign x60 = x60a ^ x60b;
1136
+ assign x61 = x61a ^ x61b;
1137
+ assign x62 = x62a ^ x62b;
1138
+ assign x63 = x63a ^ x63b;
1139
+ assign x64 = x64a ^ x64b;
1140
+ assign x65 = x65a ^ x65b;
1141
+ assign x66 = x66a ^ x66b;
1142
+ assign x67 = x67a ^ x67b;
1143
+ assign x68 = x68a ^ x68b;
1144
+ assign x69 = x69a ^ x69b;
1145
+ assign x70 = x70a ^ x70b;
1146
+ assign x71 = x71a ^ x71b;
1147
+ assign x72 = x72a ^ x72b;
1148
+ assign x73 = x73a ^ x73b;
1149
+ assign x74 = x74a ^ x74b;
1150
+ assign x75 = x75a ^ x75b;
1151
+ assign x76 = x76a ^ x76b;
1152
+ assign x77 = x77a ^ x77b;
1153
+ assign x78 = x78a ^ x78b;
1154
+ assign x79 = x79a ^ x79b;
1155
+ assign x80 = x80a ^ x80b;
1156
+ assign x81 = x81a ^ x81b;
1157
+ assign x82 = x82a ^ x82b;
1158
+ assign x83 = x83a ^ x83b;
1159
+ assign x84 = x84a ^ x84b;
1160
+ assign x85 = x85a ^ x85b;
1161
+ assign x86 = x86a ^ x86b;
1162
+ assign x87 = x87a ^ x87b;
1163
+ assign x88 = x88a ^ x88b;
1164
+ assign x89 = x89a ^ x89b;
1165
+ assign x90 = x90a ^ x90b;
1166
+ assign x91 = x91a ^ x91b;
1167
+ assign x92 = x92a ^ x92b;
1168
+ assign x93 = x93a ^ x93b;
1169
+ assign x94 = x94a ^ x94b;
1170
+ assign x95 = x95a ^ x95b;
1171
+ assign x96 = x96a ^ x96b;
1172
+ assign x97 = x97a ^ x97b;
1173
+ assign x98 = x98a ^ x98b;
1174
+ assign x99 = x99a ^ x99b;
1175
+ assign x100 = x100a ^ x100b;
1176
+ assign x101 = x101a ^ x101b;
1177
+ assign x102 = x102a ^ x102b;
1178
+ assign x103 = x103a ^ x103b;
1179
+ assign x104 = x104a ^ x104b;
1180
+ assign x105 = x105a ^ x105b;
1181
+ assign x106 = x106a ^ x106b;
1182
+ assign x107 = x107a ^ x107b;
1183
+ assign x108 = x108a ^ x108b;
1184
+ assign x109 = x109a ^ x109b;
1185
+ assign x110 = x110a ^ x110b;
1186
+ assign x111 = x111a ^ x111b;
1187
+ assign x112 = x112a ^ x112b;
1188
+ assign x113 = x113a ^ x113b;
1189
+ assign x114 = x114a ^ x114b;
1190
+ assign x115 = x115a ^ x115b;
1191
+ assign x116 = x116a ^ x116b;
1192
+ assign x117 = x117a ^ x117b;
1193
+ assign x118 = x118a ^ x118b;
1194
+ assign x119 = x119a ^ x119b;
1195
+ assign x120 = x120a ^ x120b;
1196
+ assign x121 = x121a ^ x121b;
1197
+ assign x122 = x122a ^ x122b;
1198
+ assign x123 = x123a ^ x123b;
1199
+ assign x124 = x124a ^ x124b;
1200
+ assign x125 = x125a ^ x125b;
1201
+ assign x126 = x126a ^ x126b;
1202
+ assign x127 = x127a ^ x127b;
1203
+ assign x128 = x128a ^ x128b;
1204
+ assign x129 = x129a ^ x129b;
1205
+ assign x130 = x130a ^ x130b;
1206
+ assign x131 = x131a ^ x131b;
1207
+ assign x132 = x132a ^ x132b;
1208
+ assign x133 = x133a ^ x133b;
1209
+ assign x134 = x134a ^ x134b;
1210
+ assign x135 = x135a ^ x135b;
1211
+ assign x136 = x136a ^ x136b;
1212
+ assign x137 = x137a ^ x137b;
1213
+ assign x138 = x138a ^ x138b;
1214
+ assign x139 = x139a ^ x139b;
1215
+ assign x140 = x140a ^ x140b;
1216
+ assign x141 = x141a ^ x141b;
1217
+ assign x142 = x142a ^ x142b;
1218
+ assign x143 = x143a ^ x143b;
1219
+ assign x144 = x144a ^ x144b;
1220
+ assign x145 = x145a ^ x145b;
1221
+ assign x146 = x146a ^ x146b;
1222
+ assign x147 = x147a ^ x147b;
1223
+ assign x148 = x148a ^ x148b;
1224
+ assign x149 = x149a ^ x149b;
1225
+ assign x150 = x150a ^ x150b;
1226
+ assign x151 = x151a ^ x151b;
1227
+ assign x152 = x152a ^ x152b;
1228
+ assign x153 = x153a ^ x153b;
1229
+ assign x154 = x154a ^ x154b;
1230
+ assign x155 = x155a ^ x155b;
1231
+ assign x156 = x156a ^ x156b;
1232
+ assign x157 = x157a ^ x157b;
1233
+ assign x158 = x158a ^ x158b;
1234
+ assign x159 = x159a ^ x159b;
1235
+ assign x160 = x160a ^ x160b;
1236
+ assign x161 = x161a ^ x161b;
1237
+ assign x162 = x162a ^ x162b;
1238
+ assign x163 = x163a ^ x163b;
1239
+ assign x164 = x164a ^ x164b;
1240
+ assign x165 = x165a ^ x165b;
1241
+ assign x166 = x166a ^ x166b;
1242
+ assign x167 = x167a ^ x167b;
1243
+ assign x168 = x168a ^ x168b;
1244
+ assign x169 = x169a ^ x169b;
1245
+ assign x170 = x170a ^ x170b;
1246
+ assign x171 = x171a ^ x171b;
1247
+ assign x172 = x172a ^ x172b;
1248
+ assign x173 = x173a ^ x173b;
1249
+ assign x174 = x174a ^ x174b;
1250
+ assign x175 = x175a ^ x175b;
1251
+ assign x176 = x176a ^ x176b;
1252
+ assign x177 = x177a ^ x177b;
1253
+ assign x178 = x178a ^ x178b;
1254
+ assign x179 = x179a ^ x179b;
1255
+ assign x180 = x180a ^ x180b;
1256
+ assign x181 = x181a ^ x181b;
1257
+ assign x182 = x182a ^ x182b;
1258
+ assign x183 = x183a ^ x183b;
1259
+ assign x184 = x184a ^ x184b;
1260
+ assign x185 = x185a ^ x185b;
1261
+ assign x186 = x186a ^ x186b;
1262
+ assign x187 = x187a ^ x187b;
1263
+ assign x188 = x188a ^ x188b;
1264
+ assign x189 = x189a ^ x189b;
1265
+ assign x190 = x190a ^ x190b;
1266
+ assign x191 = x191a ^ x191b;
1267
+ assign x192 = x192a ^ x192b;
1268
+ assign x193 = x193a ^ x193b;
1269
+ assign x194 = x194a ^ x194b;
1270
+ assign x195 = x195a ^ x195b;
1271
+ assign x196 = x196a ^ x196b;
1272
+ assign x197 = x197a ^ x197b;
1273
+ assign x198 = x198a ^ x198b;
1274
+ assign x199 = x199a ^ x199b;
1275
+ assign x200 = x200a ^ x200b;
1276
+ assign x201 = x201a ^ x201b;
1277
+ assign x202 = x202a ^ x202b;
1278
+ assign x203 = x203a ^ x203b;
1279
+ assign x204 = x204a ^ x204b;
1280
+ assign x205 = x205a ^ x205b;
1281
+ assign x206 = x206a ^ x206b;
1282
+ assign x207 = x207a ^ x207b;
1283
+ assign x208 = x208a ^ x208b;
1284
+ assign x209 = x209a ^ x209b;
1285
+ assign x210 = x210a ^ x210b;
1286
+ assign x211 = x211a ^ x211b;
1287
+ assign x212 = x212a ^ x212b;
1288
+ assign x213 = x213a ^ x213b;
1289
+ assign x214 = x214a ^ x214b;
1290
+ assign x215 = x215a ^ x215b;
1291
+ assign x216 = x216a ^ x216b;
1292
+ assign x217 = x217a ^ x217b;
1293
+ assign x218 = x218a ^ x218b;
1294
+ assign x219 = x219a ^ x219b;
1295
+ assign x220 = x220a ^ x220b;
1296
+ assign x221 = x221a ^ x221b;
1297
+ assign x222 = x222a ^ x222b;
1298
+ assign x223 = x223a ^ x223b;
1299
+ assign x224 = x224a ^ x224b;
1300
+ assign x225 = x225a ^ x225b;
1301
+ assign x226 = x226a ^ x226b;
1302
+ assign x227 = x227a ^ x227b;
1303
+ assign x228 = x228a ^ x228b;
1304
+ assign x229 = x229a ^ x229b;
1305
+ assign x230 = x230a ^ x230b;
1306
+ assign x231 = x231a ^ x231b;
1307
+ assign x232 = x232a ^ x232b;
1308
+ assign x233 = x233a ^ x233b;
1309
+ assign x234 = x234a ^ x234b;
1310
+ assign x235 = x235a ^ x235b;
1311
+ assign x236 = x236a ^ x236b;
1312
+ assign x237 = x237a ^ x237b;
1313
+ assign x238 = x238a ^ x238b;
1314
+ assign x239 = x239a ^ x239b;
1315
+ assign x240 = x240a ^ x240b;
1316
+ assign x241 = x241a ^ x241b;
1317
+ assign x242 = x242a ^ x242b;
1318
+ assign x243 = x243a ^ x243b;
1319
+ assign x244 = x244a ^ x244b;
1320
+ assign x245 = x245a ^ x245b;
1321
+ assign x246 = x246a ^ x246b;
1322
+ assign x247 = x247a ^ x247b;
1323
+ assign x248 = x248a ^ x248b;
1324
+ assign x249 = x249a ^ x249b;
1325
+ assign x250 = x250a ^ x250b;
1326
+ assign x251 = x251a ^ x251b;
1327
+ assign x252 = x252a ^ x252b;
1328
+ assign x253 = x253a ^ x253b;
1329
+ assign x254 = x254a ^ x254b;
1330
+ assign x255 = x255a ^ x255b;
1331
+ assign x256 = x256a ^ x256b;
1332
+ assign x257 = x257a ^ x257b;
1333
+ assign x258 = x258a ^ x258b;
1334
+ assign x259 = x259a ^ x259b;
1335
+ assign x260 = x260a ^ x260b;
1336
+ assign x261 = x261a ^ x261b;
1337
+ assign x262 = x262a ^ x262b;
1338
+ assign x263 = x263a ^ x263b;
1339
+ assign x264 = x264a ^ x264b;
1340
+ assign x265 = x265a ^ x265b;
1341
+ assign x266 = x266a ^ x266b;
1342
+ assign x267 = x267a ^ x267b;
1343
+ assign x268 = x268a ^ x268b;
1344
+ assign x269 = x269a ^ x269b;
1345
+ assign x270 = x270a ^ x270b;
1346
+ assign x271 = x271a ^ x271b;
1347
+ assign x272 = x272a ^ x272b;
1348
+ assign x273 = x273a ^ x273b;
1349
+ assign x274 = x274a ^ x274b;
1350
+ assign x275 = x275a ^ x275b;
1351
+ assign x276 = x276a ^ x276b;
1352
+ assign x277 = x277a ^ x277b;
1353
+ assign x278 = x278a ^ x278b;
1354
+ assign x279 = x279a ^ x279b;
1355
+ assign x280 = x280a ^ x280b;
1356
+ assign x281 = x281a ^ x281b;
1357
+ assign x282 = x282a ^ x282b;
1358
+ assign x283 = x283a ^ x283b;
1359
+ assign x284 = x284a ^ x284b;
1360
+ assign x285 = x285a ^ x285b;
1361
+ assign x286 = x286a ^ x286b;
1362
+ assign x287 = x287a ^ x287b;
1363
+ assign x288 = x288a ^ x288b;
1364
+ assign x289 = x289a ^ x289b;
1365
+ assign x290 = x290a ^ x290b;
1366
+ assign x291 = x291a ^ x291b;
1367
+ assign x292 = x292a ^ x292b;
1368
+ assign x293 = x293a ^ x293b;
1369
+ assign x294 = x294a ^ x294b;
1370
+ assign x295 = x295a ^ x295b;
1371
+ assign x296 = x296a ^ x296b;
1372
+ assign x297 = x297a ^ x297b;
1373
+ assign x298 = x298a ^ x298b;
1374
+ assign x299 = x299a ^ x299b;
1375
+ assign x300 = x300a ^ x300b;
1376
+ assign x301 = x301a ^ x301b;
1377
+ assign x302 = x302a ^ x302b;
1378
+ assign x303 = x303a ^ x303b;
1379
+ assign x304 = x304a ^ x304b;
1380
+ assign x305 = x305a ^ x305b;
1381
+ assign x306 = x306a ^ x306b;
1382
+ assign x307 = x307a ^ x307b;
1383
+ assign x308 = x308a ^ x308b;
1384
+ assign x309 = x309a ^ x309b;
1385
+ assign x310 = x310a ^ x310b;
1386
+ assign x311 = x311a ^ x311b;
1387
+ assign x312 = x312a ^ x312b;
1388
+ assign x313 = x313a ^ x313b;
1389
+ assign x314 = x314a ^ x314b;
1390
+ assign x315 = x315a ^ x315b;
1391
+ assign x316 = x316a ^ x316b;
1392
+ assign x317 = x317a ^ x317b;
1393
+ assign x318 = x318a ^ x318b;
1394
+ assign x319 = x319a ^ x319b;
1395
+ assign x320 = x320a ^ x320b;
1396
+ assign x321 = x321a ^ x321b;
1397
+ assign x322 = x322a ^ x322b;
1398
+ assign x323 = x323a ^ x323b;
1399
+ assign x324 = x324a ^ x324b;
1400
+ assign x325 = x325a ^ x325b;
1401
+ assign x326 = x326a ^ x326b;
1402
+ assign x327 = x327a ^ x327b;
1403
+ assign x328 = x328a ^ x328b;
1404
+ assign x329 = x329a ^ x329b;
1405
+ assign x330 = x330a ^ x330b;
1406
+ assign x331 = x331a ^ x331b;
1407
+ assign x332 = x332a ^ x332b;
1408
+ assign x333 = x333a ^ x333b;
1409
+ assign x334 = x334a ^ x334b;
1410
+ assign x335 = x335a ^ x335b;
1411
+ assign x336 = x336a ^ x336b;
1412
+ assign x337 = x337a ^ x337b;
1413
+ assign x338 = x338a ^ x338b;
1414
+ assign x339 = x339a ^ x339b;
1415
+ assign x340 = x340a ^ x340b;
1416
+ assign x341 = x341a ^ x341b;
1417
+ assign x342 = x342a ^ x342b;
1418
+ assign x343 = x343a ^ x343b;
1419
+ assign x344 = x344a ^ x344b;
1420
+ assign x345 = x345a ^ x345b;
1421
+ assign x346 = x346a ^ x346b;
1422
+ assign x347 = x347a ^ x347b;
1423
+ assign x348 = x348a ^ x348b;
1424
+ assign x349 = x349a ^ x349b;
1425
+ assign x350 = x350a ^ x350b;
1426
+ assign x351 = x351a ^ x351b;
1427
+ assign x352 = x352a ^ x352b;
1428
+ assign x353 = x353a ^ x353b;
1429
+ assign x354 = x354a ^ x354b;
1430
+ assign x355 = x355a ^ x355b;
1431
+ assign x356 = x356a ^ x356b;
1432
+ assign x357 = x357a ^ x357b;
1433
+ assign x358 = x358a ^ x358b;
1434
+ assign x359 = x359a ^ x359b;
1435
+ assign x360 = x360a ^ x360b;
1436
+ assign x361 = x361a ^ x361b;
1437
+ assign x362 = x362a ^ x362b;
1438
+ assign x363 = x363a ^ x363b;
1439
+ assign x364 = x364a ^ x364b;
1440
+ assign x365 = x365a ^ x365b;
1441
+ assign x366 = x366a ^ x366b;
1442
+ assign x367 = x367a ^ x367b;
1443
+ assign x368 = x368a ^ x368b;
1444
+ assign x369 = x369a ^ x369b;
1445
+ assign x370 = x370a ^ x370b;
1446
+ assign x371 = x371a ^ x371b;
1447
+ assign x372 = x372a ^ x372b;
1448
+ assign x373 = x373a ^ x373b;
1449
+ assign x374 = x374a ^ x374b;
1450
+ assign x375 = x375a ^ x375b;
1451
+ assign x376 = x376a ^ x376b;
1452
+ assign x377 = x377a ^ x377b;
1453
+ assign x378 = x378a ^ x378b;
1454
+ assign x379 = x379a ^ x379b;
1455
+ assign x380 = x380a ^ x380b;
1456
+ assign x381 = x381a ^ x381b;
1457
+ assign x382 = x382a ^ x382b;
1458
+ assign x383 = x383a ^ x383b;
1459
+ assign x384 = x384a ^ x384b;
1460
+ assign x385 = x385a ^ x385b;
1461
+ assign x386 = x386a ^ x386b;
1462
+ assign x387 = x387a ^ x387b;
1463
+ assign x388 = x388a ^ x388b;
1464
+ assign x389 = x389a ^ x389b;
1465
+ assign x390 = x390a ^ x390b;
1466
+ assign x391 = x391a ^ x391b;
1467
+ assign x392 = x392a ^ x392b;
1468
+ assign x393 = x393a ^ x393b;
1469
+ assign x394 = x394a ^ x394b;
1470
+ assign x395 = x395a ^ x395b;
1471
+ assign x396 = x396a ^ x396b;
1472
+ assign x397 = x397a ^ x397b;
1473
+ assign x398 = x398a ^ x398b;
1474
+ assign x399 = x399a ^ x399b;
1475
+ assign x400 = x400a ^ x400b;
1476
+ assign x401 = x401a ^ x401b;
1477
+ assign x402 = x402a ^ x402b;
1478
+ assign x403 = x403a ^ x403b;
1479
+ assign x404 = x404a ^ x404b;
1480
+ assign x405 = x405a ^ x405b;
1481
+ assign x406 = x406a ^ x406b;
1482
+ assign x407 = x407a ^ x407b;
1483
+ assign x408 = x408a ^ x408b;
1484
+ assign x409 = x409a ^ x409b;
1485
+ assign x410 = x410a ^ x410b;
1486
+ assign x411 = x411a ^ x411b;
1487
+ assign x412 = x412a ^ x412b;
1488
+ assign x413 = x413a ^ x413b;
1489
+ assign x414 = x414a ^ x414b;
1490
+ assign x415 = x415a ^ x415b;
1491
+ assign x416 = x416a ^ x416b;
1492
+ assign x417 = x417a ^ x417b;
1493
+ assign x418 = x418a ^ x418b;
1494
+ assign x419 = x419a ^ x419b;
1495
+ assign x420 = x420a ^ x420b;
1496
+ assign x421 = x421a ^ x421b;
1497
+ assign x422 = x422a ^ x422b;
1498
+ assign x423 = x423a ^ x423b;
1499
+ assign x424 = x424a ^ x424b;
1500
+ assign x425 = x425a ^ x425b;
1501
+ assign x426 = x426a ^ x426b;
1502
+ assign x427 = x427a ^ x427b;
1503
+ assign x428 = x428a ^ x428b;
1504
+ assign x429 = x429a ^ x429b;
1505
+ assign x430 = x430a ^ x430b;
1506
+ assign x431 = x431a ^ x431b;
1507
+ assign x432 = x432a ^ x432b;
1508
+ assign x433 = x433a ^ x433b;
1509
+ assign x434 = x434a ^ x434b;
1510
+ assign x435 = x435a ^ x435b;
1511
+ assign x436 = x436a ^ x436b;
1512
+ assign x437 = x437a ^ x437b;
1513
+ assign x438 = x438a ^ x438b;
1514
+ assign x439 = x439a ^ x439b;
1515
+ assign x440 = x440a ^ x440b;
1516
+ assign x441 = x441a ^ x441b;
1517
+ assign x442 = x442a ^ x442b;
1518
+ assign x443 = x443a ^ x443b;
1519
+ assign x444 = x444a ^ x444b;
1520
+ assign x445 = x445a ^ x445b;
1521
+ assign x446 = x446a ^ x446b;
1522
+ assign x447 = x447a ^ x447b;
1523
+ assign x448 = x448a ^ x448b;
1524
+ assign x449 = x449a ^ x449b;
1525
+ assign x450 = x450a ^ x450b;
1526
+ assign x451 = x451a ^ x451b;
1527
+ assign x452 = x452a ^ x452b;
1528
+ assign x453 = x453a ^ x453b;
1529
+ assign x454 = x454a ^ x454b;
1530
+ assign x455 = x455a ^ x455b;
1531
+ assign x456 = x456a ^ x456b;
1532
+ assign x457 = x457a ^ x457b;
1533
+ assign x458 = x458a ^ x458b;
1534
+ assign x459 = x459a ^ x459b;
1535
+ assign x460 = x460a ^ x460b;
1536
+ assign x461 = x461a ^ x461b;
1537
+ assign x462 = x462a ^ x462b;
1538
+ assign x463 = x463a ^ x463b;
1539
+ assign x464 = x464a ^ x464b;
1540
+ assign x465 = x465a ^ x465b;
1541
+ assign x466 = x466a ^ x466b;
1542
+ assign x467 = x467a ^ x467b;
1543
+ assign x468 = x468a ^ x468b;
1544
+ assign x469 = x469a ^ x469b;
1545
+ assign x470 = x470a ^ x470b;
1546
+ assign x471 = x471a ^ x471b;
1547
+ assign x472 = x472a ^ x472b;
1548
+ assign x473 = x473a ^ x473b;
1549
+ assign x474 = x474a ^ x474b;
1550
+ assign x475 = x475a ^ x475b;
1551
+ assign x476 = x476a ^ x476b;
1552
+ assign x477 = x477a ^ x477b;
1553
+ assign x478 = x478a ^ x478b;
1554
+ assign x479 = x479a ^ x479b;
1555
+ assign x480 = x480a ^ x480b;
1556
+ assign x481 = x481a ^ x481b;
1557
+ assign x482 = x482a ^ x482b;
1558
+ assign x483 = x483a ^ x483b;
1559
+ assign x484 = x484a ^ x484b;
1560
+ assign x485 = x485a ^ x485b;
1561
+ assign x486 = x486a ^ x486b;
1562
+ assign x487 = x487a ^ x487b;
1563
+ assign x488 = x488a ^ x488b;
1564
+ assign x489 = x489a ^ x489b;
1565
+ assign x490 = x490a ^ x490b;
1566
+ assign x491 = x491a ^ x491b;
1567
+ assign x492 = x492a ^ x492b;
1568
+ assign x493 = x493a ^ x493b;
1569
+ assign x494 = x494a ^ x494b;
1570
+ assign x495 = x495a ^ x495b;
1571
+ assign x496 = x496a ^ x496b;
1572
+ assign x497 = x497a ^ x497b;
1573
+ assign x498 = x498a ^ x498b;
1574
+ assign x499 = x499a ^ x499b;
1575
+ assign x500 = x500a ^ x500b;
1576
+ assign x501 = x501a ^ x501b;
1577
+ assign x502 = x502a ^ x502b;
1578
+ assign x503 = x503a ^ x503b;
1579
+ assign x504 = x504a ^ x504b;
1580
+ assign x505 = x505a ^ x505b;
1581
+ assign x506 = x506a ^ x506b;
1582
+ assign x507 = x507a ^ x507b;
1583
+ assign x508 = x508a ^ x508b;
1584
+ assign x509 = x509a ^ x509b;
1585
+ assign x510 = x510a ^ x510b;
1586
+ assign x511 = x511a ^ x511b;
1587
+ assign y3 = x0;
1588
+ assign y4 = x1;
1589
+ assign y5 = x2;
1590
+ assign y6 = x3;
1591
+ assign y7 = x4;
1592
+ assign y8 = x5;
1593
+ assign y9 = x6;
1594
+ assign y10 = x7;
1595
+ assign y11 = x8;
1596
+ assign y12 = x9;
1597
+ assign y13 = x10;
1598
+ assign y14 = x11;
1599
+ assign y15 = x12;
1600
+ assign y16 = x13;
1601
+ assign y17 = x14;
1602
+ assign y18 = x15;
1603
+ assign y19 = x16;
1604
+ assign y20 = x17;
1605
+ assign y21 = x18;
1606
+ assign y22 = x19;
1607
+ assign y23 = x20;
1608
+ assign y24 = x21;
1609
+ assign y25 = x22;
1610
+ assign y26 = x23;
1611
+ assign y27 = x24;
1612
+ assign y28 = x25;
1613
+ assign y29 = x26;
1614
+ assign y30 = x27;
1615
+ assign y31 = x28;
1616
+ assign y32 = x29;
1617
+ assign y33 = x30;
1618
+ assign y34 = x31;
1619
+ assign y35 = x32;
1620
+ assign y36 = x33;
1621
+ assign y37 = x34;
1622
+ assign y38 = x35;
1623
+ assign y39 = x36;
1624
+ assign y40 = x37;
1625
+ assign y41 = x38;
1626
+ assign y42 = x39;
1627
+ assign y43 = x40;
1628
+ assign y44 = x41;
1629
+ assign y45 = x42;
1630
+ assign y46 = x43;
1631
+ assign y47 = x44;
1632
+ assign y48 = x45;
1633
+ assign y49 = x46;
1634
+ assign y50 = x47;
1635
+ assign y51 = x48;
1636
+ assign y52 = x49;
1637
+ assign y53 = x50;
1638
+ assign y54 = x51;
1639
+ assign y55 = x52;
1640
+ assign y56 = x53;
1641
+ assign y57 = x54;
1642
+ assign y58 = x55;
1643
+ assign y59 = x56;
1644
+ assign y60 = x57;
1645
+ assign y61 = x58;
1646
+ assign y62 = x59;
1647
+ assign y63 = x60;
1648
+ assign y64 = x61;
1649
+ assign y65 = x62;
1650
+ assign y66 = x63;
1651
+ assign y67 = x64;
1652
+ assign y68 = x65;
1653
+ assign y69 = x66;
1654
+ assign y70 = x67;
1655
+ assign y71 = x68;
1656
+ assign y72 = x69;
1657
+ assign y73 = x70;
1658
+ assign y74 = x71;
1659
+ assign y75 = x72;
1660
+ assign y76 = x73;
1661
+ assign y77 = x74;
1662
+ assign y78 = x75;
1663
+ assign y79 = x76;
1664
+ assign y80 = x77;
1665
+ assign y81 = x78;
1666
+ assign y82 = x79;
1667
+ assign y83 = x80;
1668
+ assign y84 = x81;
1669
+ assign y85 = x82;
1670
+ assign y86 = x83;
1671
+ assign y87 = x84;
1672
+ assign y88 = x85;
1673
+ assign y89 = x86;
1674
+ assign y90 = x87;
1675
+ assign y91 = x88;
1676
+ assign y92 = x89;
1677
+ assign y93 = x90;
1678
+ assign y94 = x91;
1679
+ assign y95 = x92;
1680
+ assign y96 = x93;
1681
+ assign y97 = x94;
1682
+ assign y98 = x95;
1683
+ assign y99 = x96;
1684
+ assign y100 = x97;
1685
+ assign y101 = x98;
1686
+ assign y102 = x99;
1687
+ assign y103 = x100;
1688
+ assign y104 = x101;
1689
+ assign y105 = x102;
1690
+ assign y106 = x103;
1691
+ assign y107 = x104;
1692
+ assign y108 = x105;
1693
+ assign y109 = x106;
1694
+ assign y110 = x107;
1695
+ assign y111 = x108;
1696
+ assign y112 = x109;
1697
+ assign y113 = x110;
1698
+ assign y114 = x111;
1699
+ assign y115 = x112;
1700
+ assign y116 = x113;
1701
+ assign y117 = x114;
1702
+ assign y118 = x115;
1703
+ assign y119 = x116;
1704
+ assign y120 = x117;
1705
+ assign y121 = x118;
1706
+ assign y122 = x119;
1707
+ assign y123 = x120;
1708
+ assign y124 = x121;
1709
+ assign y125 = x122;
1710
+ assign y126 = x123;
1711
+ assign y127 = x124;
1712
+ assign y128 = x125;
1713
+ assign y129 = x126;
1714
+ assign y130 = x127;
1715
+ assign y131 = x128;
1716
+ assign y132 = x129;
1717
+ assign y133 = x130;
1718
+ assign y134 = x131;
1719
+ assign y135 = x132;
1720
+ assign y136 = x133;
1721
+ assign y137 = x134;
1722
+ assign y138 = x135;
1723
+ assign y139 = x136;
1724
+ assign y140 = x137;
1725
+ assign y141 = x138;
1726
+ assign y142 = x139;
1727
+ assign y143 = x140;
1728
+ assign y144 = x141;
1729
+ assign y145 = x142;
1730
+ assign y146 = x143;
1731
+ assign y147 = x144;
1732
+ assign y148 = x145;
1733
+ assign y149 = x146;
1734
+ assign y150 = x147;
1735
+ assign y151 = x148;
1736
+ assign y152 = x149;
1737
+ assign y153 = x150;
1738
+ assign y154 = x151;
1739
+ assign y155 = x152;
1740
+ assign y156 = x153;
1741
+ assign y157 = x154;
1742
+ assign y158 = x155;
1743
+ assign y159 = x156;
1744
+ assign y160 = x157;
1745
+ assign y161 = x158;
1746
+ assign y162 = x159;
1747
+ assign y163 = x160;
1748
+ assign y164 = x161;
1749
+ assign y165 = x162;
1750
+ assign y166 = x163;
1751
+ assign y167 = x164;
1752
+ assign y168 = x165;
1753
+ assign y169 = x166;
1754
+ assign y170 = x167;
1755
+ assign y171 = x168;
1756
+ assign y172 = x169;
1757
+ assign y173 = x170;
1758
+ assign y174 = x171;
1759
+ assign y175 = x172;
1760
+ assign y176 = x173;
1761
+ assign y177 = x174;
1762
+ assign y178 = x175;
1763
+ assign y179 = x176;
1764
+ assign y180 = x177;
1765
+ assign y181 = x178;
1766
+ assign y182 = x179;
1767
+ assign y183 = x180;
1768
+ assign y184 = x181;
1769
+ assign y185 = x182;
1770
+ assign y186 = x183;
1771
+ assign y187 = x184;
1772
+ assign y188 = x185;
1773
+ assign y189 = x186;
1774
+ assign y190 = x187;
1775
+ assign y191 = x188;
1776
+ assign y192 = x189;
1777
+ assign y193 = x190;
1778
+ assign y194 = x191;
1779
+ assign y195 = x192;
1780
+ assign y196 = x193;
1781
+ assign y197 = x194;
1782
+ assign y198 = x195;
1783
+ assign y199 = x196;
1784
+ assign y200 = x197;
1785
+ assign y201 = x198;
1786
+ assign y202 = x199;
1787
+ assign y203 = x200;
1788
+ assign y204 = x201;
1789
+ assign y205 = x202;
1790
+ assign y206 = x203;
1791
+ assign y207 = x204;
1792
+ assign y208 = x205;
1793
+ assign y209 = x206;
1794
+ assign y210 = x207;
1795
+ assign y211 = x208;
1796
+ assign y212 = x209;
1797
+ assign y213 = x210;
1798
+ assign y214 = x211;
1799
+ assign y215 = x212;
1800
+ assign y216 = x213;
1801
+ assign y217 = x214;
1802
+ assign y218 = x215;
1803
+ assign y219 = x216;
1804
+ assign y220 = x217;
1805
+ assign y221 = x218;
1806
+ assign y222 = x219;
1807
+ assign y223 = x220;
1808
+ assign y224 = x221;
1809
+ assign y225 = x222;
1810
+ assign y226 = x223;
1811
+ assign y227 = x224;
1812
+ assign y228 = x225;
1813
+ assign y229 = x226;
1814
+ assign y230 = x227;
1815
+ assign y231 = x228;
1816
+ assign y232 = x229;
1817
+ assign y233 = x230;
1818
+ assign y234 = x231;
1819
+ assign y235 = x232;
1820
+ assign y236 = x233;
1821
+ assign y237 = x234;
1822
+ assign y238 = x235;
1823
+ assign y239 = x236;
1824
+ assign y240 = x237;
1825
+ assign y241 = x238;
1826
+ assign y242 = x239;
1827
+ assign y243 = x240;
1828
+ assign y244 = x241;
1829
+ assign y245 = x242;
1830
+ assign y246 = x243;
1831
+ assign y247 = x244;
1832
+ assign y248 = x245;
1833
+ assign y249 = x246;
1834
+ assign y250 = x247;
1835
+ assign y251 = x248;
1836
+ assign y252 = x249;
1837
+ assign y253 = x250;
1838
+ assign y254 = x251;
1839
+ assign y255 = x252;
1840
+ assign y256 = x253;
1841
+ assign y257 = x254;
1842
+ assign y258 = x255;
1843
+ assign y259 = x256;
1844
+ assign y260 = x257;
1845
+ assign y261 = x258;
1846
+ assign y262 = x259;
1847
+ assign y263 = x260;
1848
+ assign y264 = x261;
1849
+ assign y265 = x262;
1850
+ assign y266 = x263;
1851
+ assign y267 = x264;
1852
+ assign y268 = x265;
1853
+ assign y269 = x266;
1854
+ assign y270 = x267;
1855
+ assign y271 = x268;
1856
+ assign y272 = x269;
1857
+ assign y273 = x270;
1858
+ assign y274 = x271;
1859
+ assign y275 = x272;
1860
+ assign y276 = x273;
1861
+ assign y277 = x274;
1862
+ assign y278 = x275;
1863
+ assign y279 = x276;
1864
+ assign y280 = x277;
1865
+ assign y281 = x278;
1866
+ assign y282 = x279;
1867
+ assign y283 = x280;
1868
+ assign y284 = x281;
1869
+ assign y285 = x282;
1870
+ assign y286 = x283;
1871
+ assign y287 = x284;
1872
+ assign y288 = x285;
1873
+ assign y289 = x286;
1874
+ assign y290 = x287;
1875
+ assign y291 = x288;
1876
+ assign y292 = x289;
1877
+ assign y293 = x290;
1878
+ assign y294 = x291;
1879
+ assign y295 = x292;
1880
+ assign y296 = x293;
1881
+ assign y297 = x294;
1882
+ assign y298 = x295;
1883
+ assign y299 = x296;
1884
+ assign y300 = x297;
1885
+ assign y301 = x298;
1886
+ assign y302 = x299;
1887
+ assign y303 = x300;
1888
+ assign y304 = x301;
1889
+ assign y305 = x302;
1890
+ assign y306 = x303;
1891
+ assign y307 = x304;
1892
+ assign y308 = x305;
1893
+ assign y309 = x306;
1894
+ assign y310 = x307;
1895
+ assign y311 = x308;
1896
+ assign y312 = x309;
1897
+ assign y313 = x310;
1898
+ assign y314 = x311;
1899
+ assign y315 = x312;
1900
+ assign y316 = x313;
1901
+ assign y317 = x314;
1902
+ assign y318 = x315;
1903
+ assign y319 = x316;
1904
+ assign y320 = x317;
1905
+ assign y321 = x318;
1906
+ assign y322 = x319;
1907
+ assign y323 = x320;
1908
+ assign y324 = x321;
1909
+ assign y325 = x322;
1910
+ assign y326 = x323;
1911
+ assign y327 = x324;
1912
+ assign y328 = x325;
1913
+ assign y329 = x326;
1914
+ assign y330 = x327;
1915
+ assign y331 = x328;
1916
+ assign y332 = x329;
1917
+ assign y333 = x330;
1918
+ assign y334 = x331;
1919
+ assign y335 = x332;
1920
+ assign y336 = x333;
1921
+ assign y337 = x334;
1922
+ assign y338 = x335;
1923
+ assign y339 = x336;
1924
+ assign y340 = x337;
1925
+ assign y341 = x338;
1926
+ assign y342 = x339;
1927
+ assign y343 = x340;
1928
+ assign y344 = x341;
1929
+ assign y345 = x342;
1930
+ assign y346 = x343;
1931
+ assign y347 = x344;
1932
+ assign y348 = x345;
1933
+ assign y349 = x346;
1934
+ assign y350 = x347;
1935
+ assign y351 = x348;
1936
+ assign y352 = x349;
1937
+ assign y353 = x350;
1938
+ assign y354 = x351;
1939
+ assign y355 = x352;
1940
+ assign y356 = x353;
1941
+ assign y357 = x354;
1942
+ assign y358 = x355;
1943
+ assign y359 = x356;
1944
+ assign y360 = x357;
1945
+ assign y361 = x358;
1946
+ assign y362 = x359;
1947
+ assign y363 = x360;
1948
+ assign y364 = x361;
1949
+ assign y365 = x362;
1950
+ assign y366 = x363;
1951
+ assign y367 = x364;
1952
+ assign y368 = x365;
1953
+ assign y369 = x366;
1954
+ assign y370 = x367;
1955
+ assign y371 = x368;
1956
+ assign y372 = x369;
1957
+ assign y373 = x370;
1958
+ assign y374 = x371;
1959
+ assign y375 = x372;
1960
+ assign y376 = x373;
1961
+ assign y377 = x374;
1962
+ assign y378 = x375;
1963
+ assign y379 = x376;
1964
+ assign y380 = x377;
1965
+ assign y381 = x378;
1966
+ assign y382 = x379;
1967
+ assign y383 = x380;
1968
+ assign y384 = x381;
1969
+ assign y385 = x382;
1970
+ assign y386 = x383;
1971
+ assign y387 = x384;
1972
+ assign y388 = x385;
1973
+ assign y389 = x386;
1974
+ assign y390 = x387;
1975
+ assign y391 = x388;
1976
+ assign y392 = x389;
1977
+ assign y393 = x390;
1978
+ assign y394 = x391;
1979
+ assign y395 = x392;
1980
+ assign y396 = x393;
1981
+ assign y397 = x394;
1982
+ assign y398 = x395;
1983
+ assign y399 = x396;
1984
+ assign y400 = x397;
1985
+ assign y401 = x398;
1986
+ assign y402 = x399;
1987
+ assign y403 = x400;
1988
+ assign y404 = x401;
1989
+ assign y405 = x402;
1990
+ assign y406 = x403;
1991
+ assign y407 = x404;
1992
+ assign y408 = x405;
1993
+ assign y409 = x406;
1994
+ assign y410 = x407;
1995
+ assign y411 = x408;
1996
+ assign y412 = x409;
1997
+ assign y413 = x410;
1998
+ assign y414 = x411;
1999
+ assign y415 = x412;
2000
+ assign y416 = x413;
2001
+ assign y417 = x414;
2002
+ assign y418 = x415;
2003
+ assign y419 = x416;
2004
+ assign y420 = x417;
2005
+ assign y421 = x418;
2006
+ assign y422 = x419;
2007
+ assign y423 = x420;
2008
+ assign y424 = x421;
2009
+ assign y425 = x422;
2010
+ assign y426 = x423;
2011
+ assign y427 = x424;
2012
+ assign y428 = x425;
2013
+ assign y429 = x426;
2014
+ assign y430 = x427;
2015
+ assign y431 = x428;
2016
+ assign y432 = x429;
2017
+ assign y433 = x430;
2018
+ assign y434 = x431;
2019
+ assign y435 = x432;
2020
+ assign y436 = x433;
2021
+ assign y437 = x434;
2022
+ assign y438 = x435;
2023
+ assign y439 = x436;
2024
+ assign y440 = x437;
2025
+ assign y441 = x438;
2026
+ assign y442 = x439;
2027
+ assign y443 = x440;
2028
+ assign y444 = x441;
2029
+ assign y445 = x442;
2030
+ assign y446 = x443;
2031
+ assign y447 = x444;
2032
+ assign y448 = x445;
2033
+ assign y449 = x446;
2034
+ assign y450 = x447;
2035
+ assign y451 = x448;
2036
+ assign y452 = x449;
2037
+ assign y453 = x450;
2038
+ assign y454 = x451;
2039
+ assign y455 = x452;
2040
+ assign y456 = x453;
2041
+ assign y457 = x454;
2042
+ assign y458 = x455;
2043
+ assign y459 = x456;
2044
+ assign y460 = x457;
2045
+ assign y461 = x458;
2046
+ assign y462 = x459;
2047
+ assign y463 = x460;
2048
+ assign y464 = x461;
2049
+ assign y465 = x462;
2050
+ assign y466 = x463;
2051
+ assign y467 = x464;
2052
+ assign y468 = x465;
2053
+ assign y469 = x466;
2054
+ assign y470 = x467;
2055
+ assign y471 = x468;
2056
+ assign y472 = x469;
2057
+ assign y473 = x470;
2058
+ assign y474 = x471;
2059
+ assign y475 = x472;
2060
+ assign y476 = x473;
2061
+ assign y477 = x474;
2062
+ assign y478 = x475;
2063
+ assign y479 = x476;
2064
+ assign y480 = x477;
2065
+ assign y481 = x478;
2066
+ assign y482 = x479;
2067
+ assign y483 = x480;
2068
+ assign y484 = x481;
2069
+ assign y485 = x482;
2070
+ assign y486 = x483;
2071
+ assign y487 = x484;
2072
+ assign y488 = x485;
2073
+ assign y489 = x486;
2074
+ assign y490 = x487;
2075
+ assign y491 = x488;
2076
+ assign y492 = x489;
2077
+ assign y493 = x490;
2078
+ assign y494 = x491;
2079
+ assign y495 = x492;
2080
+ assign y496 = x493;
2081
+ assign y497 = x494;
2082
+ assign y498 = x495;
2083
+ assign y499 = x496;
2084
+ assign y500 = x497;
2085
+ assign y501 = x498;
2086
+ assign y502 = x499;
2087
+ assign y503 = x500;
2088
+ assign y504 = x501;
2089
+ assign y505 = x502;
2090
+ assign y506 = x503;
2091
+ assign y507 = x504;
2092
+ assign y508 = x505;
2093
+ assign y509 = x506;
2094
+ assign y510 = x507;
2095
+ assign y511 = x508;
2096
+ always @(posedge clk)
2097
+ if (rst)
2098
+ d0 <= rst_val[0];
2099
+ else if (prog)
2100
+ d0 <= seed[0];
2101
+ else if (en)
2102
+ d0 <= x509;
2103
+ assign y0 = d0;
2104
+ always @(posedge clk)
2105
+ if (rst)
2106
+ d1 <= rst_val[1];
2107
+ else if (prog)
2108
+ d1 <= seed[1];
2109
+ else if (en)
2110
+ d1 <= x510;
2111
+ assign y1 = d1;
2112
+ always @(posedge clk)
2113
+ if (rst)
2114
+ d2 <= rst_val[2];
2115
+ else if (prog)
2116
+ d2 <= seed[2];
2117
+ else if (en)
2118
+ d2 <= x511;
2119
+ assign y2 = d2;
2120
+ assign x0a = y0;
2121
+ assign x22a = y0;
2122
+ assign x1a = y1;
2123
+ assign x23a = y1;
2124
+ assign x2a = y2;
2125
+ assign x24a = y2;
2126
+ assign x3a = y3;
2127
+ assign x25a = y3;
2128
+ assign x4a = y4;
2129
+ assign x26a = y4;
2130
+ assign x5a = y5;
2131
+ assign x27a = y5;
2132
+ assign x6a = y6;
2133
+ assign x28a = y6;
2134
+ assign x7a = y7;
2135
+ assign x29a = y7;
2136
+ assign x8a = y8;
2137
+ assign x30a = y8;
2138
+ assign x9a = y9;
2139
+ assign x31a = y9;
2140
+ assign x10a = y10;
2141
+ assign x32a = y10;
2142
+ assign x11a = y11;
2143
+ assign x33a = y11;
2144
+ assign x12a = y12;
2145
+ assign x34a = y12;
2146
+ assign x13a = y13;
2147
+ assign x35a = y13;
2148
+ assign x14a = y14;
2149
+ assign x36a = y14;
2150
+ assign x15a = y15;
2151
+ assign x37a = y15;
2152
+ assign x16a = y16;
2153
+ assign x38a = y16;
2154
+ assign x17a = y17;
2155
+ assign x39a = y17;
2156
+ assign x18a = y18;
2157
+ assign x40a = y18;
2158
+ assign x19a = y19;
2159
+ assign x41a = y19;
2160
+ assign x20a = y20;
2161
+ assign x42a = y20;
2162
+ assign x21a = y21;
2163
+ assign x43a = y21;
2164
+ assign x22b = y22;
2165
+ assign x44a = y22;
2166
+ assign x23b = y23;
2167
+ assign x45a = y23;
2168
+ assign x24b = y24;
2169
+ assign x46a = y24;
2170
+ assign x25b = y25;
2171
+ assign x47a = y25;
2172
+ assign x26b = y26;
2173
+ assign x48a = y26;
2174
+ assign x27b = y27;
2175
+ assign x49a = y27;
2176
+ assign x28b = y28;
2177
+ assign x50a = y28;
2178
+ assign x29b = y29;
2179
+ assign x51a = y29;
2180
+ assign x30b = y30;
2181
+ assign x52a = y30;
2182
+ assign x31b = y31;
2183
+ assign x53a = y31;
2184
+ assign x32b = y32;
2185
+ assign x54a = y32;
2186
+ assign x33b = y33;
2187
+ assign x55a = y33;
2188
+ assign x34b = y34;
2189
+ assign x56a = y34;
2190
+ assign x35b = y35;
2191
+ assign x57a = y35;
2192
+ assign x36b = y36;
2193
+ assign x58a = y36;
2194
+ assign x37b = y37;
2195
+ assign x59a = y37;
2196
+ assign x38b = y38;
2197
+ assign x60a = y38;
2198
+ assign x39b = y39;
2199
+ assign x61a = y39;
2200
+ assign x40b = y40;
2201
+ assign x62a = y40;
2202
+ assign x41b = y41;
2203
+ assign x63a = y41;
2204
+ assign x42b = y42;
2205
+ assign x64a = y42;
2206
+ assign x43b = y43;
2207
+ assign x65a = y43;
2208
+ assign x44b = y44;
2209
+ assign x66a = y44;
2210
+ assign x45b = y45;
2211
+ assign x67a = y45;
2212
+ assign x46b = y46;
2213
+ assign x68a = y46;
2214
+ assign x47b = y47;
2215
+ assign x69a = y47;
2216
+ assign x48b = y48;
2217
+ assign x70a = y48;
2218
+ assign x49b = y49;
2219
+ assign x71a = y49;
2220
+ assign x50b = y50;
2221
+ assign x72a = y50;
2222
+ assign x51b = y51;
2223
+ assign x73a = y51;
2224
+ assign x52b = y52;
2225
+ assign x74a = y52;
2226
+ assign x53b = y53;
2227
+ assign x75a = y53;
2228
+ assign x54b = y54;
2229
+ assign x76a = y54;
2230
+ assign x55b = y55;
2231
+ assign x77a = y55;
2232
+ assign x56b = y56;
2233
+ assign x78a = y56;
2234
+ assign x57b = y57;
2235
+ assign x79a = y57;
2236
+ assign x58b = y58;
2237
+ assign x80a = y58;
2238
+ assign x59b = y59;
2239
+ assign x81a = y59;
2240
+ assign x60b = y60;
2241
+ assign x82a = y60;
2242
+ assign x61b = y61;
2243
+ assign x83a = y61;
2244
+ assign x62b = y62;
2245
+ assign x84a = y62;
2246
+ assign x63b = y63;
2247
+ assign x85a = y63;
2248
+ assign x64b = y64;
2249
+ assign x86a = y64;
2250
+ assign x65b = y65;
2251
+ assign x87a = y65;
2252
+ assign x66b = y66;
2253
+ assign x88a = y66;
2254
+ assign x67b = y67;
2255
+ assign x89a = y67;
2256
+ assign x68b = y68;
2257
+ assign x90a = y68;
2258
+ assign x69b = y69;
2259
+ assign x91a = y69;
2260
+ assign x70b = y70;
2261
+ assign x92a = y70;
2262
+ assign x71b = y71;
2263
+ assign x93a = y71;
2264
+ assign x72b = y72;
2265
+ assign x94a = y72;
2266
+ assign x73b = y73;
2267
+ assign x95a = y73;
2268
+ assign x74b = y74;
2269
+ assign x96a = y74;
2270
+ assign x75b = y75;
2271
+ assign x97a = y75;
2272
+ assign x76b = y76;
2273
+ assign x98a = y76;
2274
+ assign x77b = y77;
2275
+ assign x99a = y77;
2276
+ assign x78b = y78;
2277
+ assign x100a = y78;
2278
+ assign x79b = y79;
2279
+ assign x101a = y79;
2280
+ assign x80b = y80;
2281
+ assign x102a = y80;
2282
+ assign x81b = y81;
2283
+ assign x103a = y81;
2284
+ assign x82b = y82;
2285
+ assign x104a = y82;
2286
+ assign x83b = y83;
2287
+ assign x105a = y83;
2288
+ assign x84b = y84;
2289
+ assign x106a = y84;
2290
+ assign x85b = y85;
2291
+ assign x107a = y85;
2292
+ assign x86b = y86;
2293
+ assign x108a = y86;
2294
+ assign x87b = y87;
2295
+ assign x109a = y87;
2296
+ assign x88b = y88;
2297
+ assign x110a = y88;
2298
+ assign x89b = y89;
2299
+ assign x111a = y89;
2300
+ assign x90b = y90;
2301
+ assign x112a = y90;
2302
+ assign x91b = y91;
2303
+ assign x113a = y91;
2304
+ assign x92b = y92;
2305
+ assign x114a = y92;
2306
+ assign x93b = y93;
2307
+ assign x115a = y93;
2308
+ assign x94b = y94;
2309
+ assign x116a = y94;
2310
+ assign x95b = y95;
2311
+ assign x117a = y95;
2312
+ assign x96b = y96;
2313
+ assign x118a = y96;
2314
+ assign x97b = y97;
2315
+ assign x119a = y97;
2316
+ assign x98b = y98;
2317
+ assign x120a = y98;
2318
+ assign x99b = y99;
2319
+ assign x121a = y99;
2320
+ assign x100b = y100;
2321
+ assign x122a = y100;
2322
+ assign x101b = y101;
2323
+ assign x123a = y101;
2324
+ assign x102b = y102;
2325
+ assign x124a = y102;
2326
+ assign x103b = y103;
2327
+ assign x125a = y103;
2328
+ assign x104b = y104;
2329
+ assign x126a = y104;
2330
+ assign x105b = y105;
2331
+ assign x127a = y105;
2332
+ assign x106b = y106;
2333
+ assign x128a = y106;
2334
+ assign x107b = y107;
2335
+ assign x129a = y107;
2336
+ assign x108b = y108;
2337
+ assign x130a = y108;
2338
+ assign x109b = y109;
2339
+ assign x131a = y109;
2340
+ assign x110b = y110;
2341
+ assign x132a = y110;
2342
+ assign x111b = y111;
2343
+ assign x133a = y111;
2344
+ assign x112b = y112;
2345
+ assign x134a = y112;
2346
+ assign x113b = y113;
2347
+ assign x135a = y113;
2348
+ assign x114b = y114;
2349
+ assign x136a = y114;
2350
+ assign x115b = y115;
2351
+ assign x137a = y115;
2352
+ assign x116b = y116;
2353
+ assign x138a = y116;
2354
+ assign x117b = y117;
2355
+ assign x139a = y117;
2356
+ assign x118b = y118;
2357
+ assign x140a = y118;
2358
+ assign x119b = y119;
2359
+ assign x141a = y119;
2360
+ assign x120b = y120;
2361
+ assign x142a = y120;
2362
+ assign x121b = y121;
2363
+ assign x143a = y121;
2364
+ assign x122b = y122;
2365
+ assign x144a = y122;
2366
+ assign x123b = y123;
2367
+ assign x145a = y123;
2368
+ assign x124b = y124;
2369
+ assign x146a = y124;
2370
+ assign x125b = y125;
2371
+ assign x147a = y125;
2372
+ assign x126b = y126;
2373
+ assign x148a = y126;
2374
+ assign x127b = y127;
2375
+ assign x149a = y127;
2376
+ assign x128b = y128;
2377
+ assign x150a = y128;
2378
+ assign x129b = y129;
2379
+ assign x151a = y129;
2380
+ assign x130b = y130;
2381
+ assign x152a = y130;
2382
+ assign x131b = y131;
2383
+ assign x153a = y131;
2384
+ assign x132b = y132;
2385
+ assign x154a = y132;
2386
+ assign x133b = y133;
2387
+ assign x155a = y133;
2388
+ assign x134b = y134;
2389
+ assign x156a = y134;
2390
+ assign x135b = y135;
2391
+ assign x157a = y135;
2392
+ assign x136b = y136;
2393
+ assign x158a = y136;
2394
+ assign x137b = y137;
2395
+ assign x159a = y137;
2396
+ assign x138b = y138;
2397
+ assign x160a = y138;
2398
+ assign x139b = y139;
2399
+ assign x161a = y139;
2400
+ assign x140b = y140;
2401
+ assign x162a = y140;
2402
+ assign x141b = y141;
2403
+ assign x163a = y141;
2404
+ assign x142b = y142;
2405
+ assign x164a = y142;
2406
+ assign x143b = y143;
2407
+ assign x165a = y143;
2408
+ assign x144b = y144;
2409
+ assign x166a = y144;
2410
+ assign x145b = y145;
2411
+ assign x167a = y145;
2412
+ assign x146b = y146;
2413
+ assign x168a = y146;
2414
+ assign x147b = y147;
2415
+ assign x169a = y147;
2416
+ assign x148b = y148;
2417
+ assign x170a = y148;
2418
+ assign x149b = y149;
2419
+ assign x171a = y149;
2420
+ assign x150b = y150;
2421
+ assign x172a = y150;
2422
+ assign x151b = y151;
2423
+ assign x173a = y151;
2424
+ assign x152b = y152;
2425
+ assign x174a = y152;
2426
+ assign x153b = y153;
2427
+ assign x175a = y153;
2428
+ assign x154b = y154;
2429
+ assign x176a = y154;
2430
+ assign x155b = y155;
2431
+ assign x177a = y155;
2432
+ assign x156b = y156;
2433
+ assign x178a = y156;
2434
+ assign x157b = y157;
2435
+ assign x179a = y157;
2436
+ assign x158b = y158;
2437
+ assign x180a = y158;
2438
+ assign x159b = y159;
2439
+ assign x181a = y159;
2440
+ assign x160b = y160;
2441
+ assign x182a = y160;
2442
+ assign x161b = y161;
2443
+ assign x183a = y161;
2444
+ assign x162b = y162;
2445
+ assign x184a = y162;
2446
+ assign x163b = y163;
2447
+ assign x185a = y163;
2448
+ assign x164b = y164;
2449
+ assign x186a = y164;
2450
+ assign x165b = y165;
2451
+ assign x187a = y165;
2452
+ assign x166b = y166;
2453
+ assign x188a = y166;
2454
+ assign x167b = y167;
2455
+ assign x189a = y167;
2456
+ assign x168b = y168;
2457
+ assign x190a = y168;
2458
+ assign x169b = y169;
2459
+ assign x191a = y169;
2460
+ assign x170b = y170;
2461
+ assign x192a = y170;
2462
+ assign x171b = y171;
2463
+ assign x193a = y171;
2464
+ assign x172b = y172;
2465
+ assign x194a = y172;
2466
+ assign x173b = y173;
2467
+ assign x195a = y173;
2468
+ assign x174b = y174;
2469
+ assign x196a = y174;
2470
+ assign x175b = y175;
2471
+ assign x197a = y175;
2472
+ assign x176b = y176;
2473
+ assign x198a = y176;
2474
+ assign x177b = y177;
2475
+ assign x199a = y177;
2476
+ assign x178b = y178;
2477
+ assign x200a = y178;
2478
+ assign x179b = y179;
2479
+ assign x201a = y179;
2480
+ assign x180b = y180;
2481
+ assign x202a = y180;
2482
+ assign x181b = y181;
2483
+ assign x203a = y181;
2484
+ assign x182b = y182;
2485
+ assign x204a = y182;
2486
+ assign x183b = y183;
2487
+ assign x205a = y183;
2488
+ assign x184b = y184;
2489
+ assign x206a = y184;
2490
+ assign x185b = y185;
2491
+ assign x207a = y185;
2492
+ assign x186b = y186;
2493
+ assign x208a = y186;
2494
+ assign x187b = y187;
2495
+ assign x209a = y187;
2496
+ assign x188b = y188;
2497
+ assign x210a = y188;
2498
+ assign x189b = y189;
2499
+ assign x211a = y189;
2500
+ assign x190b = y190;
2501
+ assign x212a = y190;
2502
+ assign x191b = y191;
2503
+ assign x213a = y191;
2504
+ assign x192b = y192;
2505
+ assign x214a = y192;
2506
+ assign x193b = y193;
2507
+ assign x215a = y193;
2508
+ assign x194b = y194;
2509
+ assign x216a = y194;
2510
+ assign x195b = y195;
2511
+ assign x217a = y195;
2512
+ assign x196b = y196;
2513
+ assign x218a = y196;
2514
+ assign x197b = y197;
2515
+ assign x219a = y197;
2516
+ assign x198b = y198;
2517
+ assign x220a = y198;
2518
+ assign x199b = y199;
2519
+ assign x221a = y199;
2520
+ assign x200b = y200;
2521
+ assign x222a = y200;
2522
+ assign x201b = y201;
2523
+ assign x223a = y201;
2524
+ assign x202b = y202;
2525
+ assign x224a = y202;
2526
+ assign x203b = y203;
2527
+ assign x225a = y203;
2528
+ assign x204b = y204;
2529
+ assign x226a = y204;
2530
+ assign x205b = y205;
2531
+ assign x227a = y205;
2532
+ assign x206b = y206;
2533
+ assign x228a = y206;
2534
+ assign x207b = y207;
2535
+ assign x229a = y207;
2536
+ assign x208b = y208;
2537
+ assign x230a = y208;
2538
+ assign x209b = y209;
2539
+ assign x231a = y209;
2540
+ assign x210b = y210;
2541
+ assign x232a = y210;
2542
+ assign x211b = y211;
2543
+ assign x233a = y211;
2544
+ assign x212b = y212;
2545
+ assign x234a = y212;
2546
+ assign x213b = y213;
2547
+ assign x235a = y213;
2548
+ assign x214b = y214;
2549
+ assign x236a = y214;
2550
+ assign x215b = y215;
2551
+ assign x237a = y215;
2552
+ assign x216b = y216;
2553
+ assign x238a = y216;
2554
+ assign x217b = y217;
2555
+ assign x239a = y217;
2556
+ assign x218b = y218;
2557
+ assign x240a = y218;
2558
+ assign x219b = y219;
2559
+ assign x241a = y219;
2560
+ assign x220b = y220;
2561
+ assign x242a = y220;
2562
+ assign x221b = y221;
2563
+ assign x243a = y221;
2564
+ assign x222b = y222;
2565
+ assign x244a = y222;
2566
+ assign x223b = y223;
2567
+ assign x245a = y223;
2568
+ assign x224b = y224;
2569
+ assign x246a = y224;
2570
+ assign x225b = y225;
2571
+ assign x247a = y225;
2572
+ assign x226b = y226;
2573
+ assign x248a = y226;
2574
+ assign x227b = y227;
2575
+ assign x249a = y227;
2576
+ assign x228b = y228;
2577
+ assign x250a = y228;
2578
+ assign x229b = y229;
2579
+ assign x251a = y229;
2580
+ assign x230b = y230;
2581
+ assign x252a = y230;
2582
+ assign x231b = y231;
2583
+ assign x253a = y231;
2584
+ assign x232b = y232;
2585
+ assign x254a = y232;
2586
+ assign x233b = y233;
2587
+ assign x255a = y233;
2588
+ assign x234b = y234;
2589
+ assign x256a = y234;
2590
+ assign x235b = y235;
2591
+ assign x257a = y235;
2592
+ assign x236b = y236;
2593
+ assign x258a = y236;
2594
+ assign x237b = y237;
2595
+ assign x259a = y237;
2596
+ assign x238b = y238;
2597
+ assign x260a = y238;
2598
+ assign x239b = y239;
2599
+ assign x261a = y239;
2600
+ assign x240b = y240;
2601
+ assign x262a = y240;
2602
+ assign x241b = y241;
2603
+ assign x263a = y241;
2604
+ assign x242b = y242;
2605
+ assign x264a = y242;
2606
+ assign x243b = y243;
2607
+ assign x265a = y243;
2608
+ assign x244b = y244;
2609
+ assign x266a = y244;
2610
+ assign x245b = y245;
2611
+ assign x267a = y245;
2612
+ assign x246b = y246;
2613
+ assign x268a = y246;
2614
+ assign x247b = y247;
2615
+ assign x269a = y247;
2616
+ assign x248b = y248;
2617
+ assign x270a = y248;
2618
+ assign x249b = y249;
2619
+ assign x271a = y249;
2620
+ assign x250b = y250;
2621
+ assign x272a = y250;
2622
+ assign x251b = y251;
2623
+ assign x273a = y251;
2624
+ assign x252b = y252;
2625
+ assign x274a = y252;
2626
+ assign x253b = y253;
2627
+ assign x275a = y253;
2628
+ assign x254b = y254;
2629
+ assign x276a = y254;
2630
+ assign x255b = y255;
2631
+ assign x277a = y255;
2632
+ assign x256b = y256;
2633
+ assign x278a = y256;
2634
+ assign x257b = y257;
2635
+ assign x279a = y257;
2636
+ assign x258b = y258;
2637
+ assign x280a = y258;
2638
+ assign x259b = y259;
2639
+ assign x281a = y259;
2640
+ assign x260b = y260;
2641
+ assign x282a = y260;
2642
+ assign x261b = y261;
2643
+ assign x283a = y261;
2644
+ assign x262b = y262;
2645
+ assign x284a = y262;
2646
+ assign x263b = y263;
2647
+ assign x285a = y263;
2648
+ assign x264b = y264;
2649
+ assign x286a = y264;
2650
+ assign x265b = y265;
2651
+ assign x287a = y265;
2652
+ assign x266b = y266;
2653
+ assign x288a = y266;
2654
+ assign x267b = y267;
2655
+ assign x289a = y267;
2656
+ assign x268b = y268;
2657
+ assign x290a = y268;
2658
+ assign x269b = y269;
2659
+ assign x291a = y269;
2660
+ assign x270b = y270;
2661
+ assign x292a = y270;
2662
+ assign x271b = y271;
2663
+ assign x293a = y271;
2664
+ assign x272b = y272;
2665
+ assign x294a = y272;
2666
+ assign x273b = y273;
2667
+ assign x295a = y273;
2668
+ assign x274b = y274;
2669
+ assign x296a = y274;
2670
+ assign x275b = y275;
2671
+ assign x297a = y275;
2672
+ assign x276b = y276;
2673
+ assign x298a = y276;
2674
+ assign x277b = y277;
2675
+ assign x299a = y277;
2676
+ assign x278b = y278;
2677
+ assign x300a = y278;
2678
+ assign x279b = y279;
2679
+ assign x301a = y279;
2680
+ assign x280b = y280;
2681
+ assign x302a = y280;
2682
+ assign x281b = y281;
2683
+ assign x303a = y281;
2684
+ assign x282b = y282;
2685
+ assign x304a = y282;
2686
+ assign x283b = y283;
2687
+ assign x305a = y283;
2688
+ assign x284b = y284;
2689
+ assign x306a = y284;
2690
+ assign x285b = y285;
2691
+ assign x307a = y285;
2692
+ assign x286b = y286;
2693
+ assign x308a = y286;
2694
+ assign x287b = y287;
2695
+ assign x309a = y287;
2696
+ assign x288b = y288;
2697
+ assign x310a = y288;
2698
+ assign x289b = y289;
2699
+ assign x311a = y289;
2700
+ assign x290b = y290;
2701
+ assign x312a = y290;
2702
+ assign x291b = y291;
2703
+ assign x313a = y291;
2704
+ assign x292b = y292;
2705
+ assign x314a = y292;
2706
+ assign x293b = y293;
2707
+ assign x315a = y293;
2708
+ assign x294b = y294;
2709
+ assign x316a = y294;
2710
+ assign x295b = y295;
2711
+ assign x317a = y295;
2712
+ assign x296b = y296;
2713
+ assign x318a = y296;
2714
+ assign x297b = y297;
2715
+ assign x319a = y297;
2716
+ assign x298b = y298;
2717
+ assign x320a = y298;
2718
+ assign x299b = y299;
2719
+ assign x321a = y299;
2720
+ assign x300b = y300;
2721
+ assign x322a = y300;
2722
+ assign x301b = y301;
2723
+ assign x323a = y301;
2724
+ assign x302b = y302;
2725
+ assign x324a = y302;
2726
+ assign x303b = y303;
2727
+ assign x325a = y303;
2728
+ assign x304b = y304;
2729
+ assign x326a = y304;
2730
+ assign x305b = y305;
2731
+ assign x327a = y305;
2732
+ assign x306b = y306;
2733
+ assign x328a = y306;
2734
+ assign x307b = y307;
2735
+ assign x329a = y307;
2736
+ assign x308b = y308;
2737
+ assign x330a = y308;
2738
+ assign x309b = y309;
2739
+ assign x331a = y309;
2740
+ assign x310b = y310;
2741
+ assign x332a = y310;
2742
+ assign x311b = y311;
2743
+ assign x333a = y311;
2744
+ assign x312b = y312;
2745
+ assign x334a = y312;
2746
+ assign x313b = y313;
2747
+ assign x335a = y313;
2748
+ assign x314b = y314;
2749
+ assign x336a = y314;
2750
+ assign x315b = y315;
2751
+ assign x337a = y315;
2752
+ assign x316b = y316;
2753
+ assign x338a = y316;
2754
+ assign x317b = y317;
2755
+ assign x339a = y317;
2756
+ assign x318b = y318;
2757
+ assign x340a = y318;
2758
+ assign x319b = y319;
2759
+ assign x341a = y319;
2760
+ assign x320b = y320;
2761
+ assign x342a = y320;
2762
+ assign x321b = y321;
2763
+ assign x343a = y321;
2764
+ assign x322b = y322;
2765
+ assign x344a = y322;
2766
+ assign x323b = y323;
2767
+ assign x345a = y323;
2768
+ assign x324b = y324;
2769
+ assign x346a = y324;
2770
+ assign x325b = y325;
2771
+ assign x347a = y325;
2772
+ assign x326b = y326;
2773
+ assign x348a = y326;
2774
+ assign x327b = y327;
2775
+ assign x349a = y327;
2776
+ assign x328b = y328;
2777
+ assign x350a = y328;
2778
+ assign x329b = y329;
2779
+ assign x351a = y329;
2780
+ assign x330b = y330;
2781
+ assign x352a = y330;
2782
+ assign x331b = y331;
2783
+ assign x353a = y331;
2784
+ assign x332b = y332;
2785
+ assign x354a = y332;
2786
+ assign x333b = y333;
2787
+ assign x355a = y333;
2788
+ assign x334b = y334;
2789
+ assign x356a = y334;
2790
+ assign x335b = y335;
2791
+ assign x357a = y335;
2792
+ assign x336b = y336;
2793
+ assign x358a = y336;
2794
+ assign x337b = y337;
2795
+ assign x359a = y337;
2796
+ assign x338b = y338;
2797
+ assign x360a = y338;
2798
+ assign x339b = y339;
2799
+ assign x361a = y339;
2800
+ assign x340b = y340;
2801
+ assign x362a = y340;
2802
+ assign x341b = y341;
2803
+ assign x363a = y341;
2804
+ assign x342b = y342;
2805
+ assign x364a = y342;
2806
+ assign x343b = y343;
2807
+ assign x365a = y343;
2808
+ assign x344b = y344;
2809
+ assign x366a = y344;
2810
+ assign x345b = y345;
2811
+ assign x367a = y345;
2812
+ assign x346b = y346;
2813
+ assign x368a = y346;
2814
+ assign x347b = y347;
2815
+ assign x369a = y347;
2816
+ assign x348b = y348;
2817
+ assign x370a = y348;
2818
+ assign x349b = y349;
2819
+ assign x371a = y349;
2820
+ assign x350b = y350;
2821
+ assign x372a = y350;
2822
+ assign x351b = y351;
2823
+ assign x373a = y351;
2824
+ assign x352b = y352;
2825
+ assign x374a = y352;
2826
+ assign x353b = y353;
2827
+ assign x375a = y353;
2828
+ assign x354b = y354;
2829
+ assign x376a = y354;
2830
+ assign x355b = y355;
2831
+ assign x377a = y355;
2832
+ assign x356b = y356;
2833
+ assign x378a = y356;
2834
+ assign x357b = y357;
2835
+ assign x379a = y357;
2836
+ assign x358b = y358;
2837
+ assign x380a = y358;
2838
+ assign x359b = y359;
2839
+ assign x381a = y359;
2840
+ assign x360b = y360;
2841
+ assign x382a = y360;
2842
+ assign x361b = y361;
2843
+ assign x383a = y361;
2844
+ assign x362b = y362;
2845
+ assign x384a = y362;
2846
+ assign x363b = y363;
2847
+ assign x385a = y363;
2848
+ assign x364b = y364;
2849
+ assign x386a = y364;
2850
+ assign x365b = y365;
2851
+ assign x387a = y365;
2852
+ assign x366b = y366;
2853
+ assign x388a = y366;
2854
+ assign x367b = y367;
2855
+ assign x389a = y367;
2856
+ assign x368b = y368;
2857
+ assign x390a = y368;
2858
+ assign x369b = y369;
2859
+ assign x391a = y369;
2860
+ assign x370b = y370;
2861
+ assign x392a = y370;
2862
+ assign x371b = y371;
2863
+ assign x393a = y371;
2864
+ assign x372b = y372;
2865
+ assign x394a = y372;
2866
+ assign x373b = y373;
2867
+ assign x395a = y373;
2868
+ assign x374b = y374;
2869
+ assign x396a = y374;
2870
+ assign x375b = y375;
2871
+ assign x397a = y375;
2872
+ assign x376b = y376;
2873
+ assign x398a = y376;
2874
+ assign x377b = y377;
2875
+ assign x399a = y377;
2876
+ assign x378b = y378;
2877
+ assign x400a = y378;
2878
+ assign x379b = y379;
2879
+ assign x401a = y379;
2880
+ assign x380b = y380;
2881
+ assign x402a = y380;
2882
+ assign x381b = y381;
2883
+ assign x403a = y381;
2884
+ assign x382b = y382;
2885
+ assign x404a = y382;
2886
+ assign x383b = y383;
2887
+ assign x405a = y383;
2888
+ assign x384b = y384;
2889
+ assign x406a = y384;
2890
+ assign x385b = y385;
2891
+ assign x407a = y385;
2892
+ assign x386b = y386;
2893
+ assign x408a = y386;
2894
+ assign x387b = y387;
2895
+ assign x409a = y387;
2896
+ assign x388b = y388;
2897
+ assign x410a = y388;
2898
+ assign x389b = y389;
2899
+ assign x411a = y389;
2900
+ assign x390b = y390;
2901
+ assign x412a = y390;
2902
+ assign x391b = y391;
2903
+ assign x413a = y391;
2904
+ assign x392b = y392;
2905
+ assign x414a = y392;
2906
+ assign x393b = y393;
2907
+ assign x415a = y393;
2908
+ assign x394b = y394;
2909
+ assign x416a = y394;
2910
+ assign x395b = y395;
2911
+ assign x417a = y395;
2912
+ assign x396b = y396;
2913
+ assign x418a = y396;
2914
+ assign x397b = y397;
2915
+ assign x419a = y397;
2916
+ assign x398b = y398;
2917
+ assign x420a = y398;
2918
+ assign x399b = y399;
2919
+ assign x421a = y399;
2920
+ assign x400b = y400;
2921
+ assign x422a = y400;
2922
+ assign x401b = y401;
2923
+ assign x423a = y401;
2924
+ assign x402b = y402;
2925
+ assign x424a = y402;
2926
+ assign x403b = y403;
2927
+ assign x425a = y403;
2928
+ assign x404b = y404;
2929
+ assign x426a = y404;
2930
+ assign x405b = y405;
2931
+ assign x427a = y405;
2932
+ assign x406b = y406;
2933
+ assign x428a = y406;
2934
+ assign x407b = y407;
2935
+ assign x429a = y407;
2936
+ assign x408b = y408;
2937
+ assign x430a = y408;
2938
+ assign x409b = y409;
2939
+ assign x431a = y409;
2940
+ assign x410b = y410;
2941
+ assign x432a = y410;
2942
+ assign x411b = y411;
2943
+ assign x433a = y411;
2944
+ assign x412b = y412;
2945
+ assign x434a = y412;
2946
+ assign x413b = y413;
2947
+ assign x435a = y413;
2948
+ assign x414b = y414;
2949
+ assign x436a = y414;
2950
+ assign x415b = y415;
2951
+ assign x437a = y415;
2952
+ assign x416b = y416;
2953
+ assign x438a = y416;
2954
+ assign x417b = y417;
2955
+ assign x439a = y417;
2956
+ assign x418b = y418;
2957
+ assign x440a = y418;
2958
+ assign x419b = y419;
2959
+ assign x441a = y419;
2960
+ assign x420b = y420;
2961
+ assign x442a = y420;
2962
+ assign x421b = y421;
2963
+ assign x443a = y421;
2964
+ assign x422b = y422;
2965
+ assign x444a = y422;
2966
+ assign x423b = y423;
2967
+ assign x445a = y423;
2968
+ assign x424b = y424;
2969
+ assign x446a = y424;
2970
+ assign x425b = y425;
2971
+ assign x447a = y425;
2972
+ assign x426b = y426;
2973
+ assign x448a = y426;
2974
+ assign x427b = y427;
2975
+ assign x449a = y427;
2976
+ assign x428b = y428;
2977
+ assign x450a = y428;
2978
+ assign x429b = y429;
2979
+ assign x451a = y429;
2980
+ assign x430b = y430;
2981
+ assign x452a = y430;
2982
+ assign x431b = y431;
2983
+ assign x453a = y431;
2984
+ assign x432b = y432;
2985
+ assign x454a = y432;
2986
+ assign x433b = y433;
2987
+ assign x455a = y433;
2988
+ assign x434b = y434;
2989
+ assign x456a = y434;
2990
+ assign x435b = y435;
2991
+ assign x457a = y435;
2992
+ assign x436b = y436;
2993
+ assign x458a = y436;
2994
+ assign x437b = y437;
2995
+ assign x459a = y437;
2996
+ assign x438b = y438;
2997
+ assign x460a = y438;
2998
+ assign x439b = y439;
2999
+ assign x461a = y439;
3000
+ assign x440b = y440;
3001
+ assign x462a = y440;
3002
+ assign x441b = y441;
3003
+ assign x463a = y441;
3004
+ assign x442b = y442;
3005
+ assign x464a = y442;
3006
+ assign x443b = y443;
3007
+ assign x465a = y443;
3008
+ assign x444b = y444;
3009
+ assign x466a = y444;
3010
+ assign x445b = y445;
3011
+ assign x467a = y445;
3012
+ assign x446b = y446;
3013
+ assign x468a = y446;
3014
+ assign x447b = y447;
3015
+ assign x469a = y447;
3016
+ assign x448b = y448;
3017
+ assign x470a = y448;
3018
+ assign x449b = y449;
3019
+ assign x471a = y449;
3020
+ assign x450b = y450;
3021
+ assign x472a = y450;
3022
+ assign x451b = y451;
3023
+ assign x473a = y451;
3024
+ assign x452b = y452;
3025
+ assign x474a = y452;
3026
+ assign x453b = y453;
3027
+ assign x475a = y453;
3028
+ assign x454b = y454;
3029
+ assign x476a = y454;
3030
+ assign x455b = y455;
3031
+ assign x477a = y455;
3032
+ assign x456b = y456;
3033
+ assign x478a = y456;
3034
+ assign x457b = y457;
3035
+ assign x479a = y457;
3036
+ assign x458b = y458;
3037
+ assign x480a = y458;
3038
+ assign x459b = y459;
3039
+ assign x481a = y459;
3040
+ assign x460b = y460;
3041
+ assign x482a = y460;
3042
+ assign x461b = y461;
3043
+ assign x483a = y461;
3044
+ assign x462b = y462;
3045
+ assign x484a = y462;
3046
+ assign x463b = y463;
3047
+ assign x485a = y463;
3048
+ assign x464b = y464;
3049
+ assign x486a = y464;
3050
+ assign x465b = y465;
3051
+ assign x487a = y465;
3052
+ assign x466b = y466;
3053
+ assign x488a = y466;
3054
+ assign x467b = y467;
3055
+ assign x489a = y467;
3056
+ assign x468b = y468;
3057
+ assign x490a = y468;
3058
+ assign x469b = y469;
3059
+ assign x491a = y469;
3060
+ assign x470b = y470;
3061
+ assign x492a = y470;
3062
+ assign x471b = y471;
3063
+ assign x493a = y471;
3064
+ assign x472b = y472;
3065
+ assign x494a = y472;
3066
+ assign x473b = y473;
3067
+ assign x495a = y473;
3068
+ assign x474b = y474;
3069
+ assign x496a = y474;
3070
+ assign x475b = y475;
3071
+ assign x497a = y475;
3072
+ assign x476b = y476;
3073
+ assign x498a = y476;
3074
+ assign x477b = y477;
3075
+ assign x499a = y477;
3076
+ assign x478b = y478;
3077
+ assign x500a = y478;
3078
+ assign x479b = y479;
3079
+ assign x501a = y479;
3080
+ assign x480b = y480;
3081
+ assign x502a = y480;
3082
+ assign x481b = y481;
3083
+ assign x503a = y481;
3084
+ assign x482b = y482;
3085
+ assign x504a = y482;
3086
+ assign x483b = y483;
3087
+ assign x505a = y483;
3088
+ assign x484b = y484;
3089
+ assign x506a = y484;
3090
+ assign x485b = y485;
3091
+ assign x507a = y485;
3092
+ assign x486b = y486;
3093
+ assign x508a = y486;
3094
+ assign x487b = y487;
3095
+ assign x509a = y487;
3096
+ assign x488b = y488;
3097
+ assign x510a = y488;
3098
+ assign x489b = y489;
3099
+ assign x511a = y489;
3100
+ assign x490b = y490;
3101
+ always @(posedge clk)
3102
+ if (rst)
3103
+ d3 <= rst_val[3];
3104
+ else if (prog)
3105
+ d3 <= seed[3];
3106
+ else if (en)
3107
+ d3 <= y490;
3108
+ assign x0b = d3;
3109
+ assign x491b = y491;
3110
+ always @(posedge clk)
3111
+ if (rst)
3112
+ d4 <= rst_val[4];
3113
+ else if (prog)
3114
+ d4 <= seed[4];
3115
+ else if (en)
3116
+ d4 <= y491;
3117
+ assign x1b = d4;
3118
+ assign x492b = y492;
3119
+ always @(posedge clk)
3120
+ if (rst)
3121
+ d5 <= rst_val[5];
3122
+ else if (prog)
3123
+ d5 <= seed[5];
3124
+ else if (en)
3125
+ d5 <= y492;
3126
+ assign x2b = d5;
3127
+ assign x493b = y493;
3128
+ always @(posedge clk)
3129
+ if (rst)
3130
+ d6 <= rst_val[6];
3131
+ else if (prog)
3132
+ d6 <= seed[6];
3133
+ else if (en)
3134
+ d6 <= y493;
3135
+ assign x3b = d6;
3136
+ assign x494b = y494;
3137
+ always @(posedge clk)
3138
+ if (rst)
3139
+ d7 <= rst_val[7];
3140
+ else if (prog)
3141
+ d7 <= seed[7];
3142
+ else if (en)
3143
+ d7 <= y494;
3144
+ assign x4b = d7;
3145
+ assign x495b = y495;
3146
+ always @(posedge clk)
3147
+ if (rst)
3148
+ d8 <= rst_val[8];
3149
+ else if (prog)
3150
+ d8 <= seed[8];
3151
+ else if (en)
3152
+ d8 <= y495;
3153
+ assign x5b = d8;
3154
+ assign x496b = y496;
3155
+ always @(posedge clk)
3156
+ if (rst)
3157
+ d9 <= rst_val[9];
3158
+ else if (prog)
3159
+ d9 <= seed[9];
3160
+ else if (en)
3161
+ d9 <= y496;
3162
+ assign x6b = d9;
3163
+ assign x497b = y497;
3164
+ always @(posedge clk)
3165
+ if (rst)
3166
+ d10 <= rst_val[10];
3167
+ else if (prog)
3168
+ d10 <= seed[10];
3169
+ else if (en)
3170
+ d10 <= y497;
3171
+ assign x7b = d10;
3172
+ assign x498b = y498;
3173
+ always @(posedge clk)
3174
+ if (rst)
3175
+ d11 <= rst_val[11];
3176
+ else if (prog)
3177
+ d11 <= seed[11];
3178
+ else if (en)
3179
+ d11 <= y498;
3180
+ assign x8b = d11;
3181
+ assign x499b = y499;
3182
+ always @(posedge clk)
3183
+ if (rst)
3184
+ d12 <= rst_val[12];
3185
+ else if (prog)
3186
+ d12 <= seed[12];
3187
+ else if (en)
3188
+ d12 <= y499;
3189
+ assign x9b = d12;
3190
+ assign x500b = y500;
3191
+ always @(posedge clk)
3192
+ if (rst)
3193
+ d13 <= rst_val[13];
3194
+ else if (prog)
3195
+ d13 <= seed[13];
3196
+ else if (en)
3197
+ d13 <= y500;
3198
+ assign x10b = d13;
3199
+ assign x501b = y501;
3200
+ always @(posedge clk)
3201
+ if (rst)
3202
+ d14 <= rst_val[14];
3203
+ else if (prog)
3204
+ d14 <= seed[14];
3205
+ else if (en)
3206
+ d14 <= y501;
3207
+ assign x11b = d14;
3208
+ assign x502b = y502;
3209
+ always @(posedge clk)
3210
+ if (rst)
3211
+ d15 <= rst_val[15];
3212
+ else if (prog)
3213
+ d15 <= seed[15];
3214
+ else if (en)
3215
+ d15 <= y502;
3216
+ assign x12b = d15;
3217
+ assign x503b = y503;
3218
+ always @(posedge clk)
3219
+ if (rst)
3220
+ d16 <= rst_val[16];
3221
+ else if (prog)
3222
+ d16 <= seed[16];
3223
+ else if (en)
3224
+ d16 <= y503;
3225
+ assign x13b = d16;
3226
+ assign x504b = y504;
3227
+ always @(posedge clk)
3228
+ if (rst)
3229
+ d17 <= rst_val[17];
3230
+ else if (prog)
3231
+ d17 <= seed[17];
3232
+ else if (en)
3233
+ d17 <= y504;
3234
+ assign x14b = d17;
3235
+ assign x505b = y505;
3236
+ always @(posedge clk)
3237
+ if (rst)
3238
+ d18 <= rst_val[18];
3239
+ else if (prog)
3240
+ d18 <= seed[18];
3241
+ else if (en)
3242
+ d18 <= y505;
3243
+ assign x15b = d18;
3244
+ assign x506b = y506;
3245
+ always @(posedge clk)
3246
+ if (rst)
3247
+ d19 <= rst_val[19];
3248
+ else if (prog)
3249
+ d19 <= seed[19];
3250
+ else if (en)
3251
+ d19 <= y506;
3252
+ assign x16b = d19;
3253
+ assign x507b = y507;
3254
+ always @(posedge clk)
3255
+ if (rst)
3256
+ d20 <= rst_val[20];
3257
+ else if (prog)
3258
+ d20 <= seed[20];
3259
+ else if (en)
3260
+ d20 <= y507;
3261
+ assign x17b = d20;
3262
+ assign x508b = y508;
3263
+ always @(posedge clk)
3264
+ if (rst)
3265
+ d21 <= rst_val[21];
3266
+ else if (prog)
3267
+ d21 <= seed[21];
3268
+ else if (en)
3269
+ d21 <= y508;
3270
+ assign x18b = d21;
3271
+ assign x509b = y509;
3272
+ always @(posedge clk)
3273
+ if (rst)
3274
+ d22 <= rst_val[22];
3275
+ else if (prog)
3276
+ d22 <= seed[22];
3277
+ else if (en)
3278
+ d22 <= y509;
3279
+ assign x19b = d22;
3280
+ assign x510b = y510;
3281
+ always @(posedge clk)
3282
+ if (rst)
3283
+ d23 <= rst_val[23];
3284
+ else if (prog)
3285
+ d23 <= seed[23];
3286
+ else if (en)
3287
+ d23 <= y510;
3288
+ assign x20b = d23;
3289
+ assign x511b = y511;
3290
+ always @(posedge clk)
3291
+ if (rst)
3292
+ d24 <= rst_val[24];
3293
+ else if (prog)
3294
+ d24 <= seed[24];
3295
+ else if (en)
3296
+ d24 <= y511;
3297
+ assign x21b = d24;
3298
+
3299
+ // Output assignment
3300
+ assign out = {y511,y510,y509,y508,y507,y506,y505,y504,y503,y502,y501,y500,y499,y498,y497,y496,y495,y494,y493,y492,y491,y490,y489,y488,y487,y486,y485,y484,y483,y482,y481,y480,y479,y478,y477,y476,y475,y474,y473,y472,y471,y470,y469,y468,y467,y466,y465,y464,y463,y462,y461,y460,y459,y458,y457,y456,y455,y454,y453,y452,y451,y450,y449,y448,y447,y446,y445,y444,y443,y442,y441,y440,y439,y438,y437,y436,y435,y434,y433,y432,y431,y430,y429,y428,y427,y426,y425,y424,y423,y422,y421,y420,y419,y418,y417,y416,y415,y414,y413,y412,y411,y410,y409,y408,y407,y406,y405,y404,y403,y402,y401,y400,y399,y398,y397,y396,y395,y394,y393,y392,y391,y390,y389,y388,y387,y386,y385,y384,y383,y382,y381,y380,y379,y378,y377,y376,y375,y374,y373,y372,y371,y370,y369,y368,y367,y366,y365,y364,y363,y362,y361,y360,y359,y358,y357,y356,y355,y354,y353,y352,y351,y350,y349,y348,y347,y346,y345,y344,y343,y342,y341,y340,y339,y338,y337,y336,y335,y334,y333,y332,y331,y330,y329,y328,y327,y326,y325,y324,y323,y322,y321,y320,y319,y318,y317,y316,y315,y314,y313,y312,y311,y310,y309,y308,y307,y306,y305,y304,y303,y302,y301,y300,y299,y298,y297,y296,y295,y294,y293,y292,y291,y290,y289,y288,y287,y286,y285,y284,y283,y282,y281,y280,y279,y278,y277,y276,y275,y274,y273,y272,y271,y270,y269,y268,y267,y266,y265,y264,y263,y262,y261,y260,y259,y258,y257,y256,y255,y254,y253,y252,y251,y250,y249,y248,y247,y246,y245,y244,y243,y242,y241,y240,y239,y238,y237,y236,y235,y234,y233,y232,y231,y230,y229,y228,y227,y226,y225,y224,y223,y222,y221,y220,y219,y218,y217,y216,y215,y214,y213,y212,y211,y210,y209,y208,y207,y206,y205,y204,y203,y202,y201,y200,y199,y198,y197,y196,y195,y194,y193,y192,y191,y190,y189,y188,y187,y186,y185,y184,y183,y182,y181,y180,y179,y178,y177,y176,y175,y174,y173,y172,y171,y170,y169,y168,y167,y166,y165,y164,y163,y162,y161,y160,y159,y158,y157,y156,y155,y154,y153,y152,y151,y150,y149,y148,y147,y146,y145,y144,y143,y142,y141,y140,y139,y138,y137,y136,y135,y134,y133,y132,y131,y130,y129,y128,y127,y126,y125,y124,y123,y122,y121,y120,y119,y118,y117,y116,y115,y114,y113,y112,y111,y110,y109,y108,y107,y106,y105,y104,y103,y102,y101,y100,y99,y98,y97,y96,y95,y94,y93,y92,y91,y90,y89,y88,y87,y86,y85,y84,y83,y82,y81,y80,y79,y78,y77,y76,y75,y74,y73,y72,y71,y70,y69,y68,y67,y66,y65,y64,y63,y62,y61,y60,y59,y58,y57,y56,y55,y54,y53,y52,y51,y50,y49,y48,y47,y46,y45,y44,y43,y42,y41,y40,y39,y38,y37,y36,y35,y34,y33,y32,y31,y30,y29,y28,y27,y26,y25,y24,y23,y22,y21,y20,y19,y18,y17,y16,y15,y14,y13,y12,y11,y10,y9,y8,y7,y6,y5,y4,y3,y2,y1,y0};
3301
+
3302
+ endmodule
ChFrenkel_ReckOn/src/lfsr/lfsr_wout.v ADDED
@@ -0,0 +1,2897 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "lfsr_wout.v" - Unfolded LFSR module for stochastic updates in output weights
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: This module has been automatically generated by a custom Python script applying the unfolding algorithm to
25
+ // arbitrary LFSRs (k pseudo-random outputs generated at every clock cycle, where k is the unfolding factor), see
26
+ // [C. Frenkel, J.D. Legat and D. Bol, "MorphIC: A 65-nm 738k-synapse/mm² quad-core binary-weight digital
27
+ // neuromorphic processor with stochastic spike-driven online learning", IEEE. Trans. on Biomedical Circuits
28
+ // and Systems, vol. 13, no. 5, pp. 999-1010, 2019]
29
+ // for details of the LFSR unfolding procedure.
30
+ //
31
+ //------------------------------------------------------------------------------
32
+
33
+
34
+ module lfsr_wout (
35
+ // Inputs
36
+ input wire clk,
37
+ input wire rst,
38
+ input wire en,
39
+ input wire [21:0] rst_val,
40
+ input wire [21:0] seed,
41
+ input wire prog,
42
+
43
+ // Output
44
+ output wire [447:0] out
45
+ );
46
+
47
+ // Nodes definitions
48
+ wire x0, x0a, x0b;
49
+ wire x1, x1a, x1b;
50
+ wire x2, x2a, x2b;
51
+ wire x3, x3a, x3b;
52
+ wire x4, x4a, x4b;
53
+ wire x5, x5a, x5b;
54
+ wire x6, x6a, x6b;
55
+ wire x7, x7a, x7b;
56
+ wire x8, x8a, x8b;
57
+ wire x9, x9a, x9b;
58
+ wire x10, x10a, x10b;
59
+ wire x11, x11a, x11b;
60
+ wire x12, x12a, x12b;
61
+ wire x13, x13a, x13b;
62
+ wire x14, x14a, x14b;
63
+ wire x15, x15a, x15b;
64
+ wire x16, x16a, x16b;
65
+ wire x17, x17a, x17b;
66
+ wire x18, x18a, x18b;
67
+ wire x19, x19a, x19b;
68
+ wire x20, x20a, x20b;
69
+ wire x21, x21a, x21b;
70
+ wire x22, x22a, x22b;
71
+ wire x23, x23a, x23b;
72
+ wire x24, x24a, x24b;
73
+ wire x25, x25a, x25b;
74
+ wire x26, x26a, x26b;
75
+ wire x27, x27a, x27b;
76
+ wire x28, x28a, x28b;
77
+ wire x29, x29a, x29b;
78
+ wire x30, x30a, x30b;
79
+ wire x31, x31a, x31b;
80
+ wire x32, x32a, x32b;
81
+ wire x33, x33a, x33b;
82
+ wire x34, x34a, x34b;
83
+ wire x35, x35a, x35b;
84
+ wire x36, x36a, x36b;
85
+ wire x37, x37a, x37b;
86
+ wire x38, x38a, x38b;
87
+ wire x39, x39a, x39b;
88
+ wire x40, x40a, x40b;
89
+ wire x41, x41a, x41b;
90
+ wire x42, x42a, x42b;
91
+ wire x43, x43a, x43b;
92
+ wire x44, x44a, x44b;
93
+ wire x45, x45a, x45b;
94
+ wire x46, x46a, x46b;
95
+ wire x47, x47a, x47b;
96
+ wire x48, x48a, x48b;
97
+ wire x49, x49a, x49b;
98
+ wire x50, x50a, x50b;
99
+ wire x51, x51a, x51b;
100
+ wire x52, x52a, x52b;
101
+ wire x53, x53a, x53b;
102
+ wire x54, x54a, x54b;
103
+ wire x55, x55a, x55b;
104
+ wire x56, x56a, x56b;
105
+ wire x57, x57a, x57b;
106
+ wire x58, x58a, x58b;
107
+ wire x59, x59a, x59b;
108
+ wire x60, x60a, x60b;
109
+ wire x61, x61a, x61b;
110
+ wire x62, x62a, x62b;
111
+ wire x63, x63a, x63b;
112
+ wire x64, x64a, x64b;
113
+ wire x65, x65a, x65b;
114
+ wire x66, x66a, x66b;
115
+ wire x67, x67a, x67b;
116
+ wire x68, x68a, x68b;
117
+ wire x69, x69a, x69b;
118
+ wire x70, x70a, x70b;
119
+ wire x71, x71a, x71b;
120
+ wire x72, x72a, x72b;
121
+ wire x73, x73a, x73b;
122
+ wire x74, x74a, x74b;
123
+ wire x75, x75a, x75b;
124
+ wire x76, x76a, x76b;
125
+ wire x77, x77a, x77b;
126
+ wire x78, x78a, x78b;
127
+ wire x79, x79a, x79b;
128
+ wire x80, x80a, x80b;
129
+ wire x81, x81a, x81b;
130
+ wire x82, x82a, x82b;
131
+ wire x83, x83a, x83b;
132
+ wire x84, x84a, x84b;
133
+ wire x85, x85a, x85b;
134
+ wire x86, x86a, x86b;
135
+ wire x87, x87a, x87b;
136
+ wire x88, x88a, x88b;
137
+ wire x89, x89a, x89b;
138
+ wire x90, x90a, x90b;
139
+ wire x91, x91a, x91b;
140
+ wire x92, x92a, x92b;
141
+ wire x93, x93a, x93b;
142
+ wire x94, x94a, x94b;
143
+ wire x95, x95a, x95b;
144
+ wire x96, x96a, x96b;
145
+ wire x97, x97a, x97b;
146
+ wire x98, x98a, x98b;
147
+ wire x99, x99a, x99b;
148
+ wire x100, x100a, x100b;
149
+ wire x101, x101a, x101b;
150
+ wire x102, x102a, x102b;
151
+ wire x103, x103a, x103b;
152
+ wire x104, x104a, x104b;
153
+ wire x105, x105a, x105b;
154
+ wire x106, x106a, x106b;
155
+ wire x107, x107a, x107b;
156
+ wire x108, x108a, x108b;
157
+ wire x109, x109a, x109b;
158
+ wire x110, x110a, x110b;
159
+ wire x111, x111a, x111b;
160
+ wire x112, x112a, x112b;
161
+ wire x113, x113a, x113b;
162
+ wire x114, x114a, x114b;
163
+ wire x115, x115a, x115b;
164
+ wire x116, x116a, x116b;
165
+ wire x117, x117a, x117b;
166
+ wire x118, x118a, x118b;
167
+ wire x119, x119a, x119b;
168
+ wire x120, x120a, x120b;
169
+ wire x121, x121a, x121b;
170
+ wire x122, x122a, x122b;
171
+ wire x123, x123a, x123b;
172
+ wire x124, x124a, x124b;
173
+ wire x125, x125a, x125b;
174
+ wire x126, x126a, x126b;
175
+ wire x127, x127a, x127b;
176
+ wire x128, x128a, x128b;
177
+ wire x129, x129a, x129b;
178
+ wire x130, x130a, x130b;
179
+ wire x131, x131a, x131b;
180
+ wire x132, x132a, x132b;
181
+ wire x133, x133a, x133b;
182
+ wire x134, x134a, x134b;
183
+ wire x135, x135a, x135b;
184
+ wire x136, x136a, x136b;
185
+ wire x137, x137a, x137b;
186
+ wire x138, x138a, x138b;
187
+ wire x139, x139a, x139b;
188
+ wire x140, x140a, x140b;
189
+ wire x141, x141a, x141b;
190
+ wire x142, x142a, x142b;
191
+ wire x143, x143a, x143b;
192
+ wire x144, x144a, x144b;
193
+ wire x145, x145a, x145b;
194
+ wire x146, x146a, x146b;
195
+ wire x147, x147a, x147b;
196
+ wire x148, x148a, x148b;
197
+ wire x149, x149a, x149b;
198
+ wire x150, x150a, x150b;
199
+ wire x151, x151a, x151b;
200
+ wire x152, x152a, x152b;
201
+ wire x153, x153a, x153b;
202
+ wire x154, x154a, x154b;
203
+ wire x155, x155a, x155b;
204
+ wire x156, x156a, x156b;
205
+ wire x157, x157a, x157b;
206
+ wire x158, x158a, x158b;
207
+ wire x159, x159a, x159b;
208
+ wire x160, x160a, x160b;
209
+ wire x161, x161a, x161b;
210
+ wire x162, x162a, x162b;
211
+ wire x163, x163a, x163b;
212
+ wire x164, x164a, x164b;
213
+ wire x165, x165a, x165b;
214
+ wire x166, x166a, x166b;
215
+ wire x167, x167a, x167b;
216
+ wire x168, x168a, x168b;
217
+ wire x169, x169a, x169b;
218
+ wire x170, x170a, x170b;
219
+ wire x171, x171a, x171b;
220
+ wire x172, x172a, x172b;
221
+ wire x173, x173a, x173b;
222
+ wire x174, x174a, x174b;
223
+ wire x175, x175a, x175b;
224
+ wire x176, x176a, x176b;
225
+ wire x177, x177a, x177b;
226
+ wire x178, x178a, x178b;
227
+ wire x179, x179a, x179b;
228
+ wire x180, x180a, x180b;
229
+ wire x181, x181a, x181b;
230
+ wire x182, x182a, x182b;
231
+ wire x183, x183a, x183b;
232
+ wire x184, x184a, x184b;
233
+ wire x185, x185a, x185b;
234
+ wire x186, x186a, x186b;
235
+ wire x187, x187a, x187b;
236
+ wire x188, x188a, x188b;
237
+ wire x189, x189a, x189b;
238
+ wire x190, x190a, x190b;
239
+ wire x191, x191a, x191b;
240
+ wire x192, x192a, x192b;
241
+ wire x193, x193a, x193b;
242
+ wire x194, x194a, x194b;
243
+ wire x195, x195a, x195b;
244
+ wire x196, x196a, x196b;
245
+ wire x197, x197a, x197b;
246
+ wire x198, x198a, x198b;
247
+ wire x199, x199a, x199b;
248
+ wire x200, x200a, x200b;
249
+ wire x201, x201a, x201b;
250
+ wire x202, x202a, x202b;
251
+ wire x203, x203a, x203b;
252
+ wire x204, x204a, x204b;
253
+ wire x205, x205a, x205b;
254
+ wire x206, x206a, x206b;
255
+ wire x207, x207a, x207b;
256
+ wire x208, x208a, x208b;
257
+ wire x209, x209a, x209b;
258
+ wire x210, x210a, x210b;
259
+ wire x211, x211a, x211b;
260
+ wire x212, x212a, x212b;
261
+ wire x213, x213a, x213b;
262
+ wire x214, x214a, x214b;
263
+ wire x215, x215a, x215b;
264
+ wire x216, x216a, x216b;
265
+ wire x217, x217a, x217b;
266
+ wire x218, x218a, x218b;
267
+ wire x219, x219a, x219b;
268
+ wire x220, x220a, x220b;
269
+ wire x221, x221a, x221b;
270
+ wire x222, x222a, x222b;
271
+ wire x223, x223a, x223b;
272
+ wire x224, x224a, x224b;
273
+ wire x225, x225a, x225b;
274
+ wire x226, x226a, x226b;
275
+ wire x227, x227a, x227b;
276
+ wire x228, x228a, x228b;
277
+ wire x229, x229a, x229b;
278
+ wire x230, x230a, x230b;
279
+ wire x231, x231a, x231b;
280
+ wire x232, x232a, x232b;
281
+ wire x233, x233a, x233b;
282
+ wire x234, x234a, x234b;
283
+ wire x235, x235a, x235b;
284
+ wire x236, x236a, x236b;
285
+ wire x237, x237a, x237b;
286
+ wire x238, x238a, x238b;
287
+ wire x239, x239a, x239b;
288
+ wire x240, x240a, x240b;
289
+ wire x241, x241a, x241b;
290
+ wire x242, x242a, x242b;
291
+ wire x243, x243a, x243b;
292
+ wire x244, x244a, x244b;
293
+ wire x245, x245a, x245b;
294
+ wire x246, x246a, x246b;
295
+ wire x247, x247a, x247b;
296
+ wire x248, x248a, x248b;
297
+ wire x249, x249a, x249b;
298
+ wire x250, x250a, x250b;
299
+ wire x251, x251a, x251b;
300
+ wire x252, x252a, x252b;
301
+ wire x253, x253a, x253b;
302
+ wire x254, x254a, x254b;
303
+ wire x255, x255a, x255b;
304
+ wire x256, x256a, x256b;
305
+ wire x257, x257a, x257b;
306
+ wire x258, x258a, x258b;
307
+ wire x259, x259a, x259b;
308
+ wire x260, x260a, x260b;
309
+ wire x261, x261a, x261b;
310
+ wire x262, x262a, x262b;
311
+ wire x263, x263a, x263b;
312
+ wire x264, x264a, x264b;
313
+ wire x265, x265a, x265b;
314
+ wire x266, x266a, x266b;
315
+ wire x267, x267a, x267b;
316
+ wire x268, x268a, x268b;
317
+ wire x269, x269a, x269b;
318
+ wire x270, x270a, x270b;
319
+ wire x271, x271a, x271b;
320
+ wire x272, x272a, x272b;
321
+ wire x273, x273a, x273b;
322
+ wire x274, x274a, x274b;
323
+ wire x275, x275a, x275b;
324
+ wire x276, x276a, x276b;
325
+ wire x277, x277a, x277b;
326
+ wire x278, x278a, x278b;
327
+ wire x279, x279a, x279b;
328
+ wire x280, x280a, x280b;
329
+ wire x281, x281a, x281b;
330
+ wire x282, x282a, x282b;
331
+ wire x283, x283a, x283b;
332
+ wire x284, x284a, x284b;
333
+ wire x285, x285a, x285b;
334
+ wire x286, x286a, x286b;
335
+ wire x287, x287a, x287b;
336
+ wire x288, x288a, x288b;
337
+ wire x289, x289a, x289b;
338
+ wire x290, x290a, x290b;
339
+ wire x291, x291a, x291b;
340
+ wire x292, x292a, x292b;
341
+ wire x293, x293a, x293b;
342
+ wire x294, x294a, x294b;
343
+ wire x295, x295a, x295b;
344
+ wire x296, x296a, x296b;
345
+ wire x297, x297a, x297b;
346
+ wire x298, x298a, x298b;
347
+ wire x299, x299a, x299b;
348
+ wire x300, x300a, x300b;
349
+ wire x301, x301a, x301b;
350
+ wire x302, x302a, x302b;
351
+ wire x303, x303a, x303b;
352
+ wire x304, x304a, x304b;
353
+ wire x305, x305a, x305b;
354
+ wire x306, x306a, x306b;
355
+ wire x307, x307a, x307b;
356
+ wire x308, x308a, x308b;
357
+ wire x309, x309a, x309b;
358
+ wire x310, x310a, x310b;
359
+ wire x311, x311a, x311b;
360
+ wire x312, x312a, x312b;
361
+ wire x313, x313a, x313b;
362
+ wire x314, x314a, x314b;
363
+ wire x315, x315a, x315b;
364
+ wire x316, x316a, x316b;
365
+ wire x317, x317a, x317b;
366
+ wire x318, x318a, x318b;
367
+ wire x319, x319a, x319b;
368
+ wire x320, x320a, x320b;
369
+ wire x321, x321a, x321b;
370
+ wire x322, x322a, x322b;
371
+ wire x323, x323a, x323b;
372
+ wire x324, x324a, x324b;
373
+ wire x325, x325a, x325b;
374
+ wire x326, x326a, x326b;
375
+ wire x327, x327a, x327b;
376
+ wire x328, x328a, x328b;
377
+ wire x329, x329a, x329b;
378
+ wire x330, x330a, x330b;
379
+ wire x331, x331a, x331b;
380
+ wire x332, x332a, x332b;
381
+ wire x333, x333a, x333b;
382
+ wire x334, x334a, x334b;
383
+ wire x335, x335a, x335b;
384
+ wire x336, x336a, x336b;
385
+ wire x337, x337a, x337b;
386
+ wire x338, x338a, x338b;
387
+ wire x339, x339a, x339b;
388
+ wire x340, x340a, x340b;
389
+ wire x341, x341a, x341b;
390
+ wire x342, x342a, x342b;
391
+ wire x343, x343a, x343b;
392
+ wire x344, x344a, x344b;
393
+ wire x345, x345a, x345b;
394
+ wire x346, x346a, x346b;
395
+ wire x347, x347a, x347b;
396
+ wire x348, x348a, x348b;
397
+ wire x349, x349a, x349b;
398
+ wire x350, x350a, x350b;
399
+ wire x351, x351a, x351b;
400
+ wire x352, x352a, x352b;
401
+ wire x353, x353a, x353b;
402
+ wire x354, x354a, x354b;
403
+ wire x355, x355a, x355b;
404
+ wire x356, x356a, x356b;
405
+ wire x357, x357a, x357b;
406
+ wire x358, x358a, x358b;
407
+ wire x359, x359a, x359b;
408
+ wire x360, x360a, x360b;
409
+ wire x361, x361a, x361b;
410
+ wire x362, x362a, x362b;
411
+ wire x363, x363a, x363b;
412
+ wire x364, x364a, x364b;
413
+ wire x365, x365a, x365b;
414
+ wire x366, x366a, x366b;
415
+ wire x367, x367a, x367b;
416
+ wire x368, x368a, x368b;
417
+ wire x369, x369a, x369b;
418
+ wire x370, x370a, x370b;
419
+ wire x371, x371a, x371b;
420
+ wire x372, x372a, x372b;
421
+ wire x373, x373a, x373b;
422
+ wire x374, x374a, x374b;
423
+ wire x375, x375a, x375b;
424
+ wire x376, x376a, x376b;
425
+ wire x377, x377a, x377b;
426
+ wire x378, x378a, x378b;
427
+ wire x379, x379a, x379b;
428
+ wire x380, x380a, x380b;
429
+ wire x381, x381a, x381b;
430
+ wire x382, x382a, x382b;
431
+ wire x383, x383a, x383b;
432
+ wire x384, x384a, x384b;
433
+ wire x385, x385a, x385b;
434
+ wire x386, x386a, x386b;
435
+ wire x387, x387a, x387b;
436
+ wire x388, x388a, x388b;
437
+ wire x389, x389a, x389b;
438
+ wire x390, x390a, x390b;
439
+ wire x391, x391a, x391b;
440
+ wire x392, x392a, x392b;
441
+ wire x393, x393a, x393b;
442
+ wire x394, x394a, x394b;
443
+ wire x395, x395a, x395b;
444
+ wire x396, x396a, x396b;
445
+ wire x397, x397a, x397b;
446
+ wire x398, x398a, x398b;
447
+ wire x399, x399a, x399b;
448
+ wire x400, x400a, x400b;
449
+ wire x401, x401a, x401b;
450
+ wire x402, x402a, x402b;
451
+ wire x403, x403a, x403b;
452
+ wire x404, x404a, x404b;
453
+ wire x405, x405a, x405b;
454
+ wire x406, x406a, x406b;
455
+ wire x407, x407a, x407b;
456
+ wire x408, x408a, x408b;
457
+ wire x409, x409a, x409b;
458
+ wire x410, x410a, x410b;
459
+ wire x411, x411a, x411b;
460
+ wire x412, x412a, x412b;
461
+ wire x413, x413a, x413b;
462
+ wire x414, x414a, x414b;
463
+ wire x415, x415a, x415b;
464
+ wire x416, x416a, x416b;
465
+ wire x417, x417a, x417b;
466
+ wire x418, x418a, x418b;
467
+ wire x419, x419a, x419b;
468
+ wire x420, x420a, x420b;
469
+ wire x421, x421a, x421b;
470
+ wire x422, x422a, x422b;
471
+ wire x423, x423a, x423b;
472
+ wire x424, x424a, x424b;
473
+ wire x425, x425a, x425b;
474
+ wire x426, x426a, x426b;
475
+ wire x427, x427a, x427b;
476
+ wire x428, x428a, x428b;
477
+ wire x429, x429a, x429b;
478
+ wire x430, x430a, x430b;
479
+ wire x431, x431a, x431b;
480
+ wire x432, x432a, x432b;
481
+ wire x433, x433a, x433b;
482
+ wire x434, x434a, x434b;
483
+ wire x435, x435a, x435b;
484
+ wire x436, x436a, x436b;
485
+ wire x437, x437a, x437b;
486
+ wire x438, x438a, x438b;
487
+ wire x439, x439a, x439b;
488
+ wire x440, x440a, x440b;
489
+ wire x441, x441a, x441b;
490
+ wire x442, x442a, x442b;
491
+ wire x443, x443a, x443b;
492
+ wire x444, x444a, x444b;
493
+ wire x445, x445a, x445b;
494
+ wire x446, x446a, x446b;
495
+ wire x447, x447a, x447b;
496
+ wire y0;
497
+ wire y1;
498
+ wire y2;
499
+ wire y3;
500
+ wire y4;
501
+ wire y5;
502
+ wire y6;
503
+ wire y7;
504
+ wire y8;
505
+ wire y9;
506
+ wire y10;
507
+ wire y11;
508
+ wire y12;
509
+ wire y13;
510
+ wire y14;
511
+ wire y15;
512
+ wire y16;
513
+ wire y17;
514
+ wire y18;
515
+ wire y19;
516
+ wire y20;
517
+ wire y21;
518
+ wire y22;
519
+ wire y23;
520
+ wire y24;
521
+ wire y25;
522
+ wire y26;
523
+ wire y27;
524
+ wire y28;
525
+ wire y29;
526
+ wire y30;
527
+ wire y31;
528
+ wire y32;
529
+ wire y33;
530
+ wire y34;
531
+ wire y35;
532
+ wire y36;
533
+ wire y37;
534
+ wire y38;
535
+ wire y39;
536
+ wire y40;
537
+ wire y41;
538
+ wire y42;
539
+ wire y43;
540
+ wire y44;
541
+ wire y45;
542
+ wire y46;
543
+ wire y47;
544
+ wire y48;
545
+ wire y49;
546
+ wire y50;
547
+ wire y51;
548
+ wire y52;
549
+ wire y53;
550
+ wire y54;
551
+ wire y55;
552
+ wire y56;
553
+ wire y57;
554
+ wire y58;
555
+ wire y59;
556
+ wire y60;
557
+ wire y61;
558
+ wire y62;
559
+ wire y63;
560
+ wire y64;
561
+ wire y65;
562
+ wire y66;
563
+ wire y67;
564
+ wire y68;
565
+ wire y69;
566
+ wire y70;
567
+ wire y71;
568
+ wire y72;
569
+ wire y73;
570
+ wire y74;
571
+ wire y75;
572
+ wire y76;
573
+ wire y77;
574
+ wire y78;
575
+ wire y79;
576
+ wire y80;
577
+ wire y81;
578
+ wire y82;
579
+ wire y83;
580
+ wire y84;
581
+ wire y85;
582
+ wire y86;
583
+ wire y87;
584
+ wire y88;
585
+ wire y89;
586
+ wire y90;
587
+ wire y91;
588
+ wire y92;
589
+ wire y93;
590
+ wire y94;
591
+ wire y95;
592
+ wire y96;
593
+ wire y97;
594
+ wire y98;
595
+ wire y99;
596
+ wire y100;
597
+ wire y101;
598
+ wire y102;
599
+ wire y103;
600
+ wire y104;
601
+ wire y105;
602
+ wire y106;
603
+ wire y107;
604
+ wire y108;
605
+ wire y109;
606
+ wire y110;
607
+ wire y111;
608
+ wire y112;
609
+ wire y113;
610
+ wire y114;
611
+ wire y115;
612
+ wire y116;
613
+ wire y117;
614
+ wire y118;
615
+ wire y119;
616
+ wire y120;
617
+ wire y121;
618
+ wire y122;
619
+ wire y123;
620
+ wire y124;
621
+ wire y125;
622
+ wire y126;
623
+ wire y127;
624
+ wire y128;
625
+ wire y129;
626
+ wire y130;
627
+ wire y131;
628
+ wire y132;
629
+ wire y133;
630
+ wire y134;
631
+ wire y135;
632
+ wire y136;
633
+ wire y137;
634
+ wire y138;
635
+ wire y139;
636
+ wire y140;
637
+ wire y141;
638
+ wire y142;
639
+ wire y143;
640
+ wire y144;
641
+ wire y145;
642
+ wire y146;
643
+ wire y147;
644
+ wire y148;
645
+ wire y149;
646
+ wire y150;
647
+ wire y151;
648
+ wire y152;
649
+ wire y153;
650
+ wire y154;
651
+ wire y155;
652
+ wire y156;
653
+ wire y157;
654
+ wire y158;
655
+ wire y159;
656
+ wire y160;
657
+ wire y161;
658
+ wire y162;
659
+ wire y163;
660
+ wire y164;
661
+ wire y165;
662
+ wire y166;
663
+ wire y167;
664
+ wire y168;
665
+ wire y169;
666
+ wire y170;
667
+ wire y171;
668
+ wire y172;
669
+ wire y173;
670
+ wire y174;
671
+ wire y175;
672
+ wire y176;
673
+ wire y177;
674
+ wire y178;
675
+ wire y179;
676
+ wire y180;
677
+ wire y181;
678
+ wire y182;
679
+ wire y183;
680
+ wire y184;
681
+ wire y185;
682
+ wire y186;
683
+ wire y187;
684
+ wire y188;
685
+ wire y189;
686
+ wire y190;
687
+ wire y191;
688
+ wire y192;
689
+ wire y193;
690
+ wire y194;
691
+ wire y195;
692
+ wire y196;
693
+ wire y197;
694
+ wire y198;
695
+ wire y199;
696
+ wire y200;
697
+ wire y201;
698
+ wire y202;
699
+ wire y203;
700
+ wire y204;
701
+ wire y205;
702
+ wire y206;
703
+ wire y207;
704
+ wire y208;
705
+ wire y209;
706
+ wire y210;
707
+ wire y211;
708
+ wire y212;
709
+ wire y213;
710
+ wire y214;
711
+ wire y215;
712
+ wire y216;
713
+ wire y217;
714
+ wire y218;
715
+ wire y219;
716
+ wire y220;
717
+ wire y221;
718
+ wire y222;
719
+ wire y223;
720
+ wire y224;
721
+ wire y225;
722
+ wire y226;
723
+ wire y227;
724
+ wire y228;
725
+ wire y229;
726
+ wire y230;
727
+ wire y231;
728
+ wire y232;
729
+ wire y233;
730
+ wire y234;
731
+ wire y235;
732
+ wire y236;
733
+ wire y237;
734
+ wire y238;
735
+ wire y239;
736
+ wire y240;
737
+ wire y241;
738
+ wire y242;
739
+ wire y243;
740
+ wire y244;
741
+ wire y245;
742
+ wire y246;
743
+ wire y247;
744
+ wire y248;
745
+ wire y249;
746
+ wire y250;
747
+ wire y251;
748
+ wire y252;
749
+ wire y253;
750
+ wire y254;
751
+ wire y255;
752
+ wire y256;
753
+ wire y257;
754
+ wire y258;
755
+ wire y259;
756
+ wire y260;
757
+ wire y261;
758
+ wire y262;
759
+ wire y263;
760
+ wire y264;
761
+ wire y265;
762
+ wire y266;
763
+ wire y267;
764
+ wire y268;
765
+ wire y269;
766
+ wire y270;
767
+ wire y271;
768
+ wire y272;
769
+ wire y273;
770
+ wire y274;
771
+ wire y275;
772
+ wire y276;
773
+ wire y277;
774
+ wire y278;
775
+ wire y279;
776
+ wire y280;
777
+ wire y281;
778
+ wire y282;
779
+ wire y283;
780
+ wire y284;
781
+ wire y285;
782
+ wire y286;
783
+ wire y287;
784
+ wire y288;
785
+ wire y289;
786
+ wire y290;
787
+ wire y291;
788
+ wire y292;
789
+ wire y293;
790
+ wire y294;
791
+ wire y295;
792
+ wire y296;
793
+ wire y297;
794
+ wire y298;
795
+ wire y299;
796
+ wire y300;
797
+ wire y301;
798
+ wire y302;
799
+ wire y303;
800
+ wire y304;
801
+ wire y305;
802
+ wire y306;
803
+ wire y307;
804
+ wire y308;
805
+ wire y309;
806
+ wire y310;
807
+ wire y311;
808
+ wire y312;
809
+ wire y313;
810
+ wire y314;
811
+ wire y315;
812
+ wire y316;
813
+ wire y317;
814
+ wire y318;
815
+ wire y319;
816
+ wire y320;
817
+ wire y321;
818
+ wire y322;
819
+ wire y323;
820
+ wire y324;
821
+ wire y325;
822
+ wire y326;
823
+ wire y327;
824
+ wire y328;
825
+ wire y329;
826
+ wire y330;
827
+ wire y331;
828
+ wire y332;
829
+ wire y333;
830
+ wire y334;
831
+ wire y335;
832
+ wire y336;
833
+ wire y337;
834
+ wire y338;
835
+ wire y339;
836
+ wire y340;
837
+ wire y341;
838
+ wire y342;
839
+ wire y343;
840
+ wire y344;
841
+ wire y345;
842
+ wire y346;
843
+ wire y347;
844
+ wire y348;
845
+ wire y349;
846
+ wire y350;
847
+ wire y351;
848
+ wire y352;
849
+ wire y353;
850
+ wire y354;
851
+ wire y355;
852
+ wire y356;
853
+ wire y357;
854
+ wire y358;
855
+ wire y359;
856
+ wire y360;
857
+ wire y361;
858
+ wire y362;
859
+ wire y363;
860
+ wire y364;
861
+ wire y365;
862
+ wire y366;
863
+ wire y367;
864
+ wire y368;
865
+ wire y369;
866
+ wire y370;
867
+ wire y371;
868
+ wire y372;
869
+ wire y373;
870
+ wire y374;
871
+ wire y375;
872
+ wire y376;
873
+ wire y377;
874
+ wire y378;
875
+ wire y379;
876
+ wire y380;
877
+ wire y381;
878
+ wire y382;
879
+ wire y383;
880
+ wire y384;
881
+ wire y385;
882
+ wire y386;
883
+ wire y387;
884
+ wire y388;
885
+ wire y389;
886
+ wire y390;
887
+ wire y391;
888
+ wire y392;
889
+ wire y393;
890
+ wire y394;
891
+ wire y395;
892
+ wire y396;
893
+ wire y397;
894
+ wire y398;
895
+ wire y399;
896
+ wire y400;
897
+ wire y401;
898
+ wire y402;
899
+ wire y403;
900
+ wire y404;
901
+ wire y405;
902
+ wire y406;
903
+ wire y407;
904
+ wire y408;
905
+ wire y409;
906
+ wire y410;
907
+ wire y411;
908
+ wire y412;
909
+ wire y413;
910
+ wire y414;
911
+ wire y415;
912
+ wire y416;
913
+ wire y417;
914
+ wire y418;
915
+ wire y419;
916
+ wire y420;
917
+ wire y421;
918
+ wire y422;
919
+ wire y423;
920
+ wire y424;
921
+ wire y425;
922
+ wire y426;
923
+ wire y427;
924
+ wire y428;
925
+ wire y429;
926
+ wire y430;
927
+ wire y431;
928
+ wire y432;
929
+ wire y433;
930
+ wire y434;
931
+ wire y435;
932
+ wire y436;
933
+ wire y437;
934
+ wire y438;
935
+ wire y439;
936
+ wire y440;
937
+ wire y441;
938
+ wire y442;
939
+ wire y443;
940
+ wire y444;
941
+ wire y445;
942
+ wire y446;
943
+ wire y447;
944
+ reg d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18, d19, d20, d21;
945
+
946
+ // Combinational and sequential logic definitions
947
+ assign x0 = x0a ^ x0b;
948
+ assign x1 = x1a ^ x1b;
949
+ assign x2 = x2a ^ x2b;
950
+ assign x3 = x3a ^ x3b;
951
+ assign x4 = x4a ^ x4b;
952
+ assign x5 = x5a ^ x5b;
953
+ assign x6 = x6a ^ x6b;
954
+ assign x7 = x7a ^ x7b;
955
+ assign x8 = x8a ^ x8b;
956
+ assign x9 = x9a ^ x9b;
957
+ assign x10 = x10a ^ x10b;
958
+ assign x11 = x11a ^ x11b;
959
+ assign x12 = x12a ^ x12b;
960
+ assign x13 = x13a ^ x13b;
961
+ assign x14 = x14a ^ x14b;
962
+ assign x15 = x15a ^ x15b;
963
+ assign x16 = x16a ^ x16b;
964
+ assign x17 = x17a ^ x17b;
965
+ assign x18 = x18a ^ x18b;
966
+ assign x19 = x19a ^ x19b;
967
+ assign x20 = x20a ^ x20b;
968
+ assign x21 = x21a ^ x21b;
969
+ assign x22 = x22a ^ x22b;
970
+ assign x23 = x23a ^ x23b;
971
+ assign x24 = x24a ^ x24b;
972
+ assign x25 = x25a ^ x25b;
973
+ assign x26 = x26a ^ x26b;
974
+ assign x27 = x27a ^ x27b;
975
+ assign x28 = x28a ^ x28b;
976
+ assign x29 = x29a ^ x29b;
977
+ assign x30 = x30a ^ x30b;
978
+ assign x31 = x31a ^ x31b;
979
+ assign x32 = x32a ^ x32b;
980
+ assign x33 = x33a ^ x33b;
981
+ assign x34 = x34a ^ x34b;
982
+ assign x35 = x35a ^ x35b;
983
+ assign x36 = x36a ^ x36b;
984
+ assign x37 = x37a ^ x37b;
985
+ assign x38 = x38a ^ x38b;
986
+ assign x39 = x39a ^ x39b;
987
+ assign x40 = x40a ^ x40b;
988
+ assign x41 = x41a ^ x41b;
989
+ assign x42 = x42a ^ x42b;
990
+ assign x43 = x43a ^ x43b;
991
+ assign x44 = x44a ^ x44b;
992
+ assign x45 = x45a ^ x45b;
993
+ assign x46 = x46a ^ x46b;
994
+ assign x47 = x47a ^ x47b;
995
+ assign x48 = x48a ^ x48b;
996
+ assign x49 = x49a ^ x49b;
997
+ assign x50 = x50a ^ x50b;
998
+ assign x51 = x51a ^ x51b;
999
+ assign x52 = x52a ^ x52b;
1000
+ assign x53 = x53a ^ x53b;
1001
+ assign x54 = x54a ^ x54b;
1002
+ assign x55 = x55a ^ x55b;
1003
+ assign x56 = x56a ^ x56b;
1004
+ assign x57 = x57a ^ x57b;
1005
+ assign x58 = x58a ^ x58b;
1006
+ assign x59 = x59a ^ x59b;
1007
+ assign x60 = x60a ^ x60b;
1008
+ assign x61 = x61a ^ x61b;
1009
+ assign x62 = x62a ^ x62b;
1010
+ assign x63 = x63a ^ x63b;
1011
+ assign x64 = x64a ^ x64b;
1012
+ assign x65 = x65a ^ x65b;
1013
+ assign x66 = x66a ^ x66b;
1014
+ assign x67 = x67a ^ x67b;
1015
+ assign x68 = x68a ^ x68b;
1016
+ assign x69 = x69a ^ x69b;
1017
+ assign x70 = x70a ^ x70b;
1018
+ assign x71 = x71a ^ x71b;
1019
+ assign x72 = x72a ^ x72b;
1020
+ assign x73 = x73a ^ x73b;
1021
+ assign x74 = x74a ^ x74b;
1022
+ assign x75 = x75a ^ x75b;
1023
+ assign x76 = x76a ^ x76b;
1024
+ assign x77 = x77a ^ x77b;
1025
+ assign x78 = x78a ^ x78b;
1026
+ assign x79 = x79a ^ x79b;
1027
+ assign x80 = x80a ^ x80b;
1028
+ assign x81 = x81a ^ x81b;
1029
+ assign x82 = x82a ^ x82b;
1030
+ assign x83 = x83a ^ x83b;
1031
+ assign x84 = x84a ^ x84b;
1032
+ assign x85 = x85a ^ x85b;
1033
+ assign x86 = x86a ^ x86b;
1034
+ assign x87 = x87a ^ x87b;
1035
+ assign x88 = x88a ^ x88b;
1036
+ assign x89 = x89a ^ x89b;
1037
+ assign x90 = x90a ^ x90b;
1038
+ assign x91 = x91a ^ x91b;
1039
+ assign x92 = x92a ^ x92b;
1040
+ assign x93 = x93a ^ x93b;
1041
+ assign x94 = x94a ^ x94b;
1042
+ assign x95 = x95a ^ x95b;
1043
+ assign x96 = x96a ^ x96b;
1044
+ assign x97 = x97a ^ x97b;
1045
+ assign x98 = x98a ^ x98b;
1046
+ assign x99 = x99a ^ x99b;
1047
+ assign x100 = x100a ^ x100b;
1048
+ assign x101 = x101a ^ x101b;
1049
+ assign x102 = x102a ^ x102b;
1050
+ assign x103 = x103a ^ x103b;
1051
+ assign x104 = x104a ^ x104b;
1052
+ assign x105 = x105a ^ x105b;
1053
+ assign x106 = x106a ^ x106b;
1054
+ assign x107 = x107a ^ x107b;
1055
+ assign x108 = x108a ^ x108b;
1056
+ assign x109 = x109a ^ x109b;
1057
+ assign x110 = x110a ^ x110b;
1058
+ assign x111 = x111a ^ x111b;
1059
+ assign x112 = x112a ^ x112b;
1060
+ assign x113 = x113a ^ x113b;
1061
+ assign x114 = x114a ^ x114b;
1062
+ assign x115 = x115a ^ x115b;
1063
+ assign x116 = x116a ^ x116b;
1064
+ assign x117 = x117a ^ x117b;
1065
+ assign x118 = x118a ^ x118b;
1066
+ assign x119 = x119a ^ x119b;
1067
+ assign x120 = x120a ^ x120b;
1068
+ assign x121 = x121a ^ x121b;
1069
+ assign x122 = x122a ^ x122b;
1070
+ assign x123 = x123a ^ x123b;
1071
+ assign x124 = x124a ^ x124b;
1072
+ assign x125 = x125a ^ x125b;
1073
+ assign x126 = x126a ^ x126b;
1074
+ assign x127 = x127a ^ x127b;
1075
+ assign x128 = x128a ^ x128b;
1076
+ assign x129 = x129a ^ x129b;
1077
+ assign x130 = x130a ^ x130b;
1078
+ assign x131 = x131a ^ x131b;
1079
+ assign x132 = x132a ^ x132b;
1080
+ assign x133 = x133a ^ x133b;
1081
+ assign x134 = x134a ^ x134b;
1082
+ assign x135 = x135a ^ x135b;
1083
+ assign x136 = x136a ^ x136b;
1084
+ assign x137 = x137a ^ x137b;
1085
+ assign x138 = x138a ^ x138b;
1086
+ assign x139 = x139a ^ x139b;
1087
+ assign x140 = x140a ^ x140b;
1088
+ assign x141 = x141a ^ x141b;
1089
+ assign x142 = x142a ^ x142b;
1090
+ assign x143 = x143a ^ x143b;
1091
+ assign x144 = x144a ^ x144b;
1092
+ assign x145 = x145a ^ x145b;
1093
+ assign x146 = x146a ^ x146b;
1094
+ assign x147 = x147a ^ x147b;
1095
+ assign x148 = x148a ^ x148b;
1096
+ assign x149 = x149a ^ x149b;
1097
+ assign x150 = x150a ^ x150b;
1098
+ assign x151 = x151a ^ x151b;
1099
+ assign x152 = x152a ^ x152b;
1100
+ assign x153 = x153a ^ x153b;
1101
+ assign x154 = x154a ^ x154b;
1102
+ assign x155 = x155a ^ x155b;
1103
+ assign x156 = x156a ^ x156b;
1104
+ assign x157 = x157a ^ x157b;
1105
+ assign x158 = x158a ^ x158b;
1106
+ assign x159 = x159a ^ x159b;
1107
+ assign x160 = x160a ^ x160b;
1108
+ assign x161 = x161a ^ x161b;
1109
+ assign x162 = x162a ^ x162b;
1110
+ assign x163 = x163a ^ x163b;
1111
+ assign x164 = x164a ^ x164b;
1112
+ assign x165 = x165a ^ x165b;
1113
+ assign x166 = x166a ^ x166b;
1114
+ assign x167 = x167a ^ x167b;
1115
+ assign x168 = x168a ^ x168b;
1116
+ assign x169 = x169a ^ x169b;
1117
+ assign x170 = x170a ^ x170b;
1118
+ assign x171 = x171a ^ x171b;
1119
+ assign x172 = x172a ^ x172b;
1120
+ assign x173 = x173a ^ x173b;
1121
+ assign x174 = x174a ^ x174b;
1122
+ assign x175 = x175a ^ x175b;
1123
+ assign x176 = x176a ^ x176b;
1124
+ assign x177 = x177a ^ x177b;
1125
+ assign x178 = x178a ^ x178b;
1126
+ assign x179 = x179a ^ x179b;
1127
+ assign x180 = x180a ^ x180b;
1128
+ assign x181 = x181a ^ x181b;
1129
+ assign x182 = x182a ^ x182b;
1130
+ assign x183 = x183a ^ x183b;
1131
+ assign x184 = x184a ^ x184b;
1132
+ assign x185 = x185a ^ x185b;
1133
+ assign x186 = x186a ^ x186b;
1134
+ assign x187 = x187a ^ x187b;
1135
+ assign x188 = x188a ^ x188b;
1136
+ assign x189 = x189a ^ x189b;
1137
+ assign x190 = x190a ^ x190b;
1138
+ assign x191 = x191a ^ x191b;
1139
+ assign x192 = x192a ^ x192b;
1140
+ assign x193 = x193a ^ x193b;
1141
+ assign x194 = x194a ^ x194b;
1142
+ assign x195 = x195a ^ x195b;
1143
+ assign x196 = x196a ^ x196b;
1144
+ assign x197 = x197a ^ x197b;
1145
+ assign x198 = x198a ^ x198b;
1146
+ assign x199 = x199a ^ x199b;
1147
+ assign x200 = x200a ^ x200b;
1148
+ assign x201 = x201a ^ x201b;
1149
+ assign x202 = x202a ^ x202b;
1150
+ assign x203 = x203a ^ x203b;
1151
+ assign x204 = x204a ^ x204b;
1152
+ assign x205 = x205a ^ x205b;
1153
+ assign x206 = x206a ^ x206b;
1154
+ assign x207 = x207a ^ x207b;
1155
+ assign x208 = x208a ^ x208b;
1156
+ assign x209 = x209a ^ x209b;
1157
+ assign x210 = x210a ^ x210b;
1158
+ assign x211 = x211a ^ x211b;
1159
+ assign x212 = x212a ^ x212b;
1160
+ assign x213 = x213a ^ x213b;
1161
+ assign x214 = x214a ^ x214b;
1162
+ assign x215 = x215a ^ x215b;
1163
+ assign x216 = x216a ^ x216b;
1164
+ assign x217 = x217a ^ x217b;
1165
+ assign x218 = x218a ^ x218b;
1166
+ assign x219 = x219a ^ x219b;
1167
+ assign x220 = x220a ^ x220b;
1168
+ assign x221 = x221a ^ x221b;
1169
+ assign x222 = x222a ^ x222b;
1170
+ assign x223 = x223a ^ x223b;
1171
+ assign x224 = x224a ^ x224b;
1172
+ assign x225 = x225a ^ x225b;
1173
+ assign x226 = x226a ^ x226b;
1174
+ assign x227 = x227a ^ x227b;
1175
+ assign x228 = x228a ^ x228b;
1176
+ assign x229 = x229a ^ x229b;
1177
+ assign x230 = x230a ^ x230b;
1178
+ assign x231 = x231a ^ x231b;
1179
+ assign x232 = x232a ^ x232b;
1180
+ assign x233 = x233a ^ x233b;
1181
+ assign x234 = x234a ^ x234b;
1182
+ assign x235 = x235a ^ x235b;
1183
+ assign x236 = x236a ^ x236b;
1184
+ assign x237 = x237a ^ x237b;
1185
+ assign x238 = x238a ^ x238b;
1186
+ assign x239 = x239a ^ x239b;
1187
+ assign x240 = x240a ^ x240b;
1188
+ assign x241 = x241a ^ x241b;
1189
+ assign x242 = x242a ^ x242b;
1190
+ assign x243 = x243a ^ x243b;
1191
+ assign x244 = x244a ^ x244b;
1192
+ assign x245 = x245a ^ x245b;
1193
+ assign x246 = x246a ^ x246b;
1194
+ assign x247 = x247a ^ x247b;
1195
+ assign x248 = x248a ^ x248b;
1196
+ assign x249 = x249a ^ x249b;
1197
+ assign x250 = x250a ^ x250b;
1198
+ assign x251 = x251a ^ x251b;
1199
+ assign x252 = x252a ^ x252b;
1200
+ assign x253 = x253a ^ x253b;
1201
+ assign x254 = x254a ^ x254b;
1202
+ assign x255 = x255a ^ x255b;
1203
+ assign x256 = x256a ^ x256b;
1204
+ assign x257 = x257a ^ x257b;
1205
+ assign x258 = x258a ^ x258b;
1206
+ assign x259 = x259a ^ x259b;
1207
+ assign x260 = x260a ^ x260b;
1208
+ assign x261 = x261a ^ x261b;
1209
+ assign x262 = x262a ^ x262b;
1210
+ assign x263 = x263a ^ x263b;
1211
+ assign x264 = x264a ^ x264b;
1212
+ assign x265 = x265a ^ x265b;
1213
+ assign x266 = x266a ^ x266b;
1214
+ assign x267 = x267a ^ x267b;
1215
+ assign x268 = x268a ^ x268b;
1216
+ assign x269 = x269a ^ x269b;
1217
+ assign x270 = x270a ^ x270b;
1218
+ assign x271 = x271a ^ x271b;
1219
+ assign x272 = x272a ^ x272b;
1220
+ assign x273 = x273a ^ x273b;
1221
+ assign x274 = x274a ^ x274b;
1222
+ assign x275 = x275a ^ x275b;
1223
+ assign x276 = x276a ^ x276b;
1224
+ assign x277 = x277a ^ x277b;
1225
+ assign x278 = x278a ^ x278b;
1226
+ assign x279 = x279a ^ x279b;
1227
+ assign x280 = x280a ^ x280b;
1228
+ assign x281 = x281a ^ x281b;
1229
+ assign x282 = x282a ^ x282b;
1230
+ assign x283 = x283a ^ x283b;
1231
+ assign x284 = x284a ^ x284b;
1232
+ assign x285 = x285a ^ x285b;
1233
+ assign x286 = x286a ^ x286b;
1234
+ assign x287 = x287a ^ x287b;
1235
+ assign x288 = x288a ^ x288b;
1236
+ assign x289 = x289a ^ x289b;
1237
+ assign x290 = x290a ^ x290b;
1238
+ assign x291 = x291a ^ x291b;
1239
+ assign x292 = x292a ^ x292b;
1240
+ assign x293 = x293a ^ x293b;
1241
+ assign x294 = x294a ^ x294b;
1242
+ assign x295 = x295a ^ x295b;
1243
+ assign x296 = x296a ^ x296b;
1244
+ assign x297 = x297a ^ x297b;
1245
+ assign x298 = x298a ^ x298b;
1246
+ assign x299 = x299a ^ x299b;
1247
+ assign x300 = x300a ^ x300b;
1248
+ assign x301 = x301a ^ x301b;
1249
+ assign x302 = x302a ^ x302b;
1250
+ assign x303 = x303a ^ x303b;
1251
+ assign x304 = x304a ^ x304b;
1252
+ assign x305 = x305a ^ x305b;
1253
+ assign x306 = x306a ^ x306b;
1254
+ assign x307 = x307a ^ x307b;
1255
+ assign x308 = x308a ^ x308b;
1256
+ assign x309 = x309a ^ x309b;
1257
+ assign x310 = x310a ^ x310b;
1258
+ assign x311 = x311a ^ x311b;
1259
+ assign x312 = x312a ^ x312b;
1260
+ assign x313 = x313a ^ x313b;
1261
+ assign x314 = x314a ^ x314b;
1262
+ assign x315 = x315a ^ x315b;
1263
+ assign x316 = x316a ^ x316b;
1264
+ assign x317 = x317a ^ x317b;
1265
+ assign x318 = x318a ^ x318b;
1266
+ assign x319 = x319a ^ x319b;
1267
+ assign x320 = x320a ^ x320b;
1268
+ assign x321 = x321a ^ x321b;
1269
+ assign x322 = x322a ^ x322b;
1270
+ assign x323 = x323a ^ x323b;
1271
+ assign x324 = x324a ^ x324b;
1272
+ assign x325 = x325a ^ x325b;
1273
+ assign x326 = x326a ^ x326b;
1274
+ assign x327 = x327a ^ x327b;
1275
+ assign x328 = x328a ^ x328b;
1276
+ assign x329 = x329a ^ x329b;
1277
+ assign x330 = x330a ^ x330b;
1278
+ assign x331 = x331a ^ x331b;
1279
+ assign x332 = x332a ^ x332b;
1280
+ assign x333 = x333a ^ x333b;
1281
+ assign x334 = x334a ^ x334b;
1282
+ assign x335 = x335a ^ x335b;
1283
+ assign x336 = x336a ^ x336b;
1284
+ assign x337 = x337a ^ x337b;
1285
+ assign x338 = x338a ^ x338b;
1286
+ assign x339 = x339a ^ x339b;
1287
+ assign x340 = x340a ^ x340b;
1288
+ assign x341 = x341a ^ x341b;
1289
+ assign x342 = x342a ^ x342b;
1290
+ assign x343 = x343a ^ x343b;
1291
+ assign x344 = x344a ^ x344b;
1292
+ assign x345 = x345a ^ x345b;
1293
+ assign x346 = x346a ^ x346b;
1294
+ assign x347 = x347a ^ x347b;
1295
+ assign x348 = x348a ^ x348b;
1296
+ assign x349 = x349a ^ x349b;
1297
+ assign x350 = x350a ^ x350b;
1298
+ assign x351 = x351a ^ x351b;
1299
+ assign x352 = x352a ^ x352b;
1300
+ assign x353 = x353a ^ x353b;
1301
+ assign x354 = x354a ^ x354b;
1302
+ assign x355 = x355a ^ x355b;
1303
+ assign x356 = x356a ^ x356b;
1304
+ assign x357 = x357a ^ x357b;
1305
+ assign x358 = x358a ^ x358b;
1306
+ assign x359 = x359a ^ x359b;
1307
+ assign x360 = x360a ^ x360b;
1308
+ assign x361 = x361a ^ x361b;
1309
+ assign x362 = x362a ^ x362b;
1310
+ assign x363 = x363a ^ x363b;
1311
+ assign x364 = x364a ^ x364b;
1312
+ assign x365 = x365a ^ x365b;
1313
+ assign x366 = x366a ^ x366b;
1314
+ assign x367 = x367a ^ x367b;
1315
+ assign x368 = x368a ^ x368b;
1316
+ assign x369 = x369a ^ x369b;
1317
+ assign x370 = x370a ^ x370b;
1318
+ assign x371 = x371a ^ x371b;
1319
+ assign x372 = x372a ^ x372b;
1320
+ assign x373 = x373a ^ x373b;
1321
+ assign x374 = x374a ^ x374b;
1322
+ assign x375 = x375a ^ x375b;
1323
+ assign x376 = x376a ^ x376b;
1324
+ assign x377 = x377a ^ x377b;
1325
+ assign x378 = x378a ^ x378b;
1326
+ assign x379 = x379a ^ x379b;
1327
+ assign x380 = x380a ^ x380b;
1328
+ assign x381 = x381a ^ x381b;
1329
+ assign x382 = x382a ^ x382b;
1330
+ assign x383 = x383a ^ x383b;
1331
+ assign x384 = x384a ^ x384b;
1332
+ assign x385 = x385a ^ x385b;
1333
+ assign x386 = x386a ^ x386b;
1334
+ assign x387 = x387a ^ x387b;
1335
+ assign x388 = x388a ^ x388b;
1336
+ assign x389 = x389a ^ x389b;
1337
+ assign x390 = x390a ^ x390b;
1338
+ assign x391 = x391a ^ x391b;
1339
+ assign x392 = x392a ^ x392b;
1340
+ assign x393 = x393a ^ x393b;
1341
+ assign x394 = x394a ^ x394b;
1342
+ assign x395 = x395a ^ x395b;
1343
+ assign x396 = x396a ^ x396b;
1344
+ assign x397 = x397a ^ x397b;
1345
+ assign x398 = x398a ^ x398b;
1346
+ assign x399 = x399a ^ x399b;
1347
+ assign x400 = x400a ^ x400b;
1348
+ assign x401 = x401a ^ x401b;
1349
+ assign x402 = x402a ^ x402b;
1350
+ assign x403 = x403a ^ x403b;
1351
+ assign x404 = x404a ^ x404b;
1352
+ assign x405 = x405a ^ x405b;
1353
+ assign x406 = x406a ^ x406b;
1354
+ assign x407 = x407a ^ x407b;
1355
+ assign x408 = x408a ^ x408b;
1356
+ assign x409 = x409a ^ x409b;
1357
+ assign x410 = x410a ^ x410b;
1358
+ assign x411 = x411a ^ x411b;
1359
+ assign x412 = x412a ^ x412b;
1360
+ assign x413 = x413a ^ x413b;
1361
+ assign x414 = x414a ^ x414b;
1362
+ assign x415 = x415a ^ x415b;
1363
+ assign x416 = x416a ^ x416b;
1364
+ assign x417 = x417a ^ x417b;
1365
+ assign x418 = x418a ^ x418b;
1366
+ assign x419 = x419a ^ x419b;
1367
+ assign x420 = x420a ^ x420b;
1368
+ assign x421 = x421a ^ x421b;
1369
+ assign x422 = x422a ^ x422b;
1370
+ assign x423 = x423a ^ x423b;
1371
+ assign x424 = x424a ^ x424b;
1372
+ assign x425 = x425a ^ x425b;
1373
+ assign x426 = x426a ^ x426b;
1374
+ assign x427 = x427a ^ x427b;
1375
+ assign x428 = x428a ^ x428b;
1376
+ assign x429 = x429a ^ x429b;
1377
+ assign x430 = x430a ^ x430b;
1378
+ assign x431 = x431a ^ x431b;
1379
+ assign x432 = x432a ^ x432b;
1380
+ assign x433 = x433a ^ x433b;
1381
+ assign x434 = x434a ^ x434b;
1382
+ assign x435 = x435a ^ x435b;
1383
+ assign x436 = x436a ^ x436b;
1384
+ assign x437 = x437a ^ x437b;
1385
+ assign x438 = x438a ^ x438b;
1386
+ assign x439 = x439a ^ x439b;
1387
+ assign x440 = x440a ^ x440b;
1388
+ assign x441 = x441a ^ x441b;
1389
+ assign x442 = x442a ^ x442b;
1390
+ assign x443 = x443a ^ x443b;
1391
+ assign x444 = x444a ^ x444b;
1392
+ assign x445 = x445a ^ x445b;
1393
+ assign x446 = x446a ^ x446b;
1394
+ assign x447 = x447a ^ x447b;
1395
+ assign y1 = x0;
1396
+ assign y2 = x1;
1397
+ assign y3 = x2;
1398
+ assign y4 = x3;
1399
+ assign y5 = x4;
1400
+ assign y6 = x5;
1401
+ assign y7 = x6;
1402
+ assign y8 = x7;
1403
+ assign y9 = x8;
1404
+ assign y10 = x9;
1405
+ assign y11 = x10;
1406
+ assign y12 = x11;
1407
+ assign y13 = x12;
1408
+ assign y14 = x13;
1409
+ assign y15 = x14;
1410
+ assign y16 = x15;
1411
+ assign y17 = x16;
1412
+ assign y18 = x17;
1413
+ assign y19 = x18;
1414
+ assign y20 = x19;
1415
+ assign y21 = x20;
1416
+ assign y22 = x21;
1417
+ assign y23 = x22;
1418
+ assign y24 = x23;
1419
+ assign y25 = x24;
1420
+ assign y26 = x25;
1421
+ assign y27 = x26;
1422
+ assign y28 = x27;
1423
+ assign y29 = x28;
1424
+ assign y30 = x29;
1425
+ assign y31 = x30;
1426
+ assign y32 = x31;
1427
+ assign y33 = x32;
1428
+ assign y34 = x33;
1429
+ assign y35 = x34;
1430
+ assign y36 = x35;
1431
+ assign y37 = x36;
1432
+ assign y38 = x37;
1433
+ assign y39 = x38;
1434
+ assign y40 = x39;
1435
+ assign y41 = x40;
1436
+ assign y42 = x41;
1437
+ assign y43 = x42;
1438
+ assign y44 = x43;
1439
+ assign y45 = x44;
1440
+ assign y46 = x45;
1441
+ assign y47 = x46;
1442
+ assign y48 = x47;
1443
+ assign y49 = x48;
1444
+ assign y50 = x49;
1445
+ assign y51 = x50;
1446
+ assign y52 = x51;
1447
+ assign y53 = x52;
1448
+ assign y54 = x53;
1449
+ assign y55 = x54;
1450
+ assign y56 = x55;
1451
+ assign y57 = x56;
1452
+ assign y58 = x57;
1453
+ assign y59 = x58;
1454
+ assign y60 = x59;
1455
+ assign y61 = x60;
1456
+ assign y62 = x61;
1457
+ assign y63 = x62;
1458
+ assign y64 = x63;
1459
+ assign y65 = x64;
1460
+ assign y66 = x65;
1461
+ assign y67 = x66;
1462
+ assign y68 = x67;
1463
+ assign y69 = x68;
1464
+ assign y70 = x69;
1465
+ assign y71 = x70;
1466
+ assign y72 = x71;
1467
+ assign y73 = x72;
1468
+ assign y74 = x73;
1469
+ assign y75 = x74;
1470
+ assign y76 = x75;
1471
+ assign y77 = x76;
1472
+ assign y78 = x77;
1473
+ assign y79 = x78;
1474
+ assign y80 = x79;
1475
+ assign y81 = x80;
1476
+ assign y82 = x81;
1477
+ assign y83 = x82;
1478
+ assign y84 = x83;
1479
+ assign y85 = x84;
1480
+ assign y86 = x85;
1481
+ assign y87 = x86;
1482
+ assign y88 = x87;
1483
+ assign y89 = x88;
1484
+ assign y90 = x89;
1485
+ assign y91 = x90;
1486
+ assign y92 = x91;
1487
+ assign y93 = x92;
1488
+ assign y94 = x93;
1489
+ assign y95 = x94;
1490
+ assign y96 = x95;
1491
+ assign y97 = x96;
1492
+ assign y98 = x97;
1493
+ assign y99 = x98;
1494
+ assign y100 = x99;
1495
+ assign y101 = x100;
1496
+ assign y102 = x101;
1497
+ assign y103 = x102;
1498
+ assign y104 = x103;
1499
+ assign y105 = x104;
1500
+ assign y106 = x105;
1501
+ assign y107 = x106;
1502
+ assign y108 = x107;
1503
+ assign y109 = x108;
1504
+ assign y110 = x109;
1505
+ assign y111 = x110;
1506
+ assign y112 = x111;
1507
+ assign y113 = x112;
1508
+ assign y114 = x113;
1509
+ assign y115 = x114;
1510
+ assign y116 = x115;
1511
+ assign y117 = x116;
1512
+ assign y118 = x117;
1513
+ assign y119 = x118;
1514
+ assign y120 = x119;
1515
+ assign y121 = x120;
1516
+ assign y122 = x121;
1517
+ assign y123 = x122;
1518
+ assign y124 = x123;
1519
+ assign y125 = x124;
1520
+ assign y126 = x125;
1521
+ assign y127 = x126;
1522
+ assign y128 = x127;
1523
+ assign y129 = x128;
1524
+ assign y130 = x129;
1525
+ assign y131 = x130;
1526
+ assign y132 = x131;
1527
+ assign y133 = x132;
1528
+ assign y134 = x133;
1529
+ assign y135 = x134;
1530
+ assign y136 = x135;
1531
+ assign y137 = x136;
1532
+ assign y138 = x137;
1533
+ assign y139 = x138;
1534
+ assign y140 = x139;
1535
+ assign y141 = x140;
1536
+ assign y142 = x141;
1537
+ assign y143 = x142;
1538
+ assign y144 = x143;
1539
+ assign y145 = x144;
1540
+ assign y146 = x145;
1541
+ assign y147 = x146;
1542
+ assign y148 = x147;
1543
+ assign y149 = x148;
1544
+ assign y150 = x149;
1545
+ assign y151 = x150;
1546
+ assign y152 = x151;
1547
+ assign y153 = x152;
1548
+ assign y154 = x153;
1549
+ assign y155 = x154;
1550
+ assign y156 = x155;
1551
+ assign y157 = x156;
1552
+ assign y158 = x157;
1553
+ assign y159 = x158;
1554
+ assign y160 = x159;
1555
+ assign y161 = x160;
1556
+ assign y162 = x161;
1557
+ assign y163 = x162;
1558
+ assign y164 = x163;
1559
+ assign y165 = x164;
1560
+ assign y166 = x165;
1561
+ assign y167 = x166;
1562
+ assign y168 = x167;
1563
+ assign y169 = x168;
1564
+ assign y170 = x169;
1565
+ assign y171 = x170;
1566
+ assign y172 = x171;
1567
+ assign y173 = x172;
1568
+ assign y174 = x173;
1569
+ assign y175 = x174;
1570
+ assign y176 = x175;
1571
+ assign y177 = x176;
1572
+ assign y178 = x177;
1573
+ assign y179 = x178;
1574
+ assign y180 = x179;
1575
+ assign y181 = x180;
1576
+ assign y182 = x181;
1577
+ assign y183 = x182;
1578
+ assign y184 = x183;
1579
+ assign y185 = x184;
1580
+ assign y186 = x185;
1581
+ assign y187 = x186;
1582
+ assign y188 = x187;
1583
+ assign y189 = x188;
1584
+ assign y190 = x189;
1585
+ assign y191 = x190;
1586
+ assign y192 = x191;
1587
+ assign y193 = x192;
1588
+ assign y194 = x193;
1589
+ assign y195 = x194;
1590
+ assign y196 = x195;
1591
+ assign y197 = x196;
1592
+ assign y198 = x197;
1593
+ assign y199 = x198;
1594
+ assign y200 = x199;
1595
+ assign y201 = x200;
1596
+ assign y202 = x201;
1597
+ assign y203 = x202;
1598
+ assign y204 = x203;
1599
+ assign y205 = x204;
1600
+ assign y206 = x205;
1601
+ assign y207 = x206;
1602
+ assign y208 = x207;
1603
+ assign y209 = x208;
1604
+ assign y210 = x209;
1605
+ assign y211 = x210;
1606
+ assign y212 = x211;
1607
+ assign y213 = x212;
1608
+ assign y214 = x213;
1609
+ assign y215 = x214;
1610
+ assign y216 = x215;
1611
+ assign y217 = x216;
1612
+ assign y218 = x217;
1613
+ assign y219 = x218;
1614
+ assign y220 = x219;
1615
+ assign y221 = x220;
1616
+ assign y222 = x221;
1617
+ assign y223 = x222;
1618
+ assign y224 = x223;
1619
+ assign y225 = x224;
1620
+ assign y226 = x225;
1621
+ assign y227 = x226;
1622
+ assign y228 = x227;
1623
+ assign y229 = x228;
1624
+ assign y230 = x229;
1625
+ assign y231 = x230;
1626
+ assign y232 = x231;
1627
+ assign y233 = x232;
1628
+ assign y234 = x233;
1629
+ assign y235 = x234;
1630
+ assign y236 = x235;
1631
+ assign y237 = x236;
1632
+ assign y238 = x237;
1633
+ assign y239 = x238;
1634
+ assign y240 = x239;
1635
+ assign y241 = x240;
1636
+ assign y242 = x241;
1637
+ assign y243 = x242;
1638
+ assign y244 = x243;
1639
+ assign y245 = x244;
1640
+ assign y246 = x245;
1641
+ assign y247 = x246;
1642
+ assign y248 = x247;
1643
+ assign y249 = x248;
1644
+ assign y250 = x249;
1645
+ assign y251 = x250;
1646
+ assign y252 = x251;
1647
+ assign y253 = x252;
1648
+ assign y254 = x253;
1649
+ assign y255 = x254;
1650
+ assign y256 = x255;
1651
+ assign y257 = x256;
1652
+ assign y258 = x257;
1653
+ assign y259 = x258;
1654
+ assign y260 = x259;
1655
+ assign y261 = x260;
1656
+ assign y262 = x261;
1657
+ assign y263 = x262;
1658
+ assign y264 = x263;
1659
+ assign y265 = x264;
1660
+ assign y266 = x265;
1661
+ assign y267 = x266;
1662
+ assign y268 = x267;
1663
+ assign y269 = x268;
1664
+ assign y270 = x269;
1665
+ assign y271 = x270;
1666
+ assign y272 = x271;
1667
+ assign y273 = x272;
1668
+ assign y274 = x273;
1669
+ assign y275 = x274;
1670
+ assign y276 = x275;
1671
+ assign y277 = x276;
1672
+ assign y278 = x277;
1673
+ assign y279 = x278;
1674
+ assign y280 = x279;
1675
+ assign y281 = x280;
1676
+ assign y282 = x281;
1677
+ assign y283 = x282;
1678
+ assign y284 = x283;
1679
+ assign y285 = x284;
1680
+ assign y286 = x285;
1681
+ assign y287 = x286;
1682
+ assign y288 = x287;
1683
+ assign y289 = x288;
1684
+ assign y290 = x289;
1685
+ assign y291 = x290;
1686
+ assign y292 = x291;
1687
+ assign y293 = x292;
1688
+ assign y294 = x293;
1689
+ assign y295 = x294;
1690
+ assign y296 = x295;
1691
+ assign y297 = x296;
1692
+ assign y298 = x297;
1693
+ assign y299 = x298;
1694
+ assign y300 = x299;
1695
+ assign y301 = x300;
1696
+ assign y302 = x301;
1697
+ assign y303 = x302;
1698
+ assign y304 = x303;
1699
+ assign y305 = x304;
1700
+ assign y306 = x305;
1701
+ assign y307 = x306;
1702
+ assign y308 = x307;
1703
+ assign y309 = x308;
1704
+ assign y310 = x309;
1705
+ assign y311 = x310;
1706
+ assign y312 = x311;
1707
+ assign y313 = x312;
1708
+ assign y314 = x313;
1709
+ assign y315 = x314;
1710
+ assign y316 = x315;
1711
+ assign y317 = x316;
1712
+ assign y318 = x317;
1713
+ assign y319 = x318;
1714
+ assign y320 = x319;
1715
+ assign y321 = x320;
1716
+ assign y322 = x321;
1717
+ assign y323 = x322;
1718
+ assign y324 = x323;
1719
+ assign y325 = x324;
1720
+ assign y326 = x325;
1721
+ assign y327 = x326;
1722
+ assign y328 = x327;
1723
+ assign y329 = x328;
1724
+ assign y330 = x329;
1725
+ assign y331 = x330;
1726
+ assign y332 = x331;
1727
+ assign y333 = x332;
1728
+ assign y334 = x333;
1729
+ assign y335 = x334;
1730
+ assign y336 = x335;
1731
+ assign y337 = x336;
1732
+ assign y338 = x337;
1733
+ assign y339 = x338;
1734
+ assign y340 = x339;
1735
+ assign y341 = x340;
1736
+ assign y342 = x341;
1737
+ assign y343 = x342;
1738
+ assign y344 = x343;
1739
+ assign y345 = x344;
1740
+ assign y346 = x345;
1741
+ assign y347 = x346;
1742
+ assign y348 = x347;
1743
+ assign y349 = x348;
1744
+ assign y350 = x349;
1745
+ assign y351 = x350;
1746
+ assign y352 = x351;
1747
+ assign y353 = x352;
1748
+ assign y354 = x353;
1749
+ assign y355 = x354;
1750
+ assign y356 = x355;
1751
+ assign y357 = x356;
1752
+ assign y358 = x357;
1753
+ assign y359 = x358;
1754
+ assign y360 = x359;
1755
+ assign y361 = x360;
1756
+ assign y362 = x361;
1757
+ assign y363 = x362;
1758
+ assign y364 = x363;
1759
+ assign y365 = x364;
1760
+ assign y366 = x365;
1761
+ assign y367 = x366;
1762
+ assign y368 = x367;
1763
+ assign y369 = x368;
1764
+ assign y370 = x369;
1765
+ assign y371 = x370;
1766
+ assign y372 = x371;
1767
+ assign y373 = x372;
1768
+ assign y374 = x373;
1769
+ assign y375 = x374;
1770
+ assign y376 = x375;
1771
+ assign y377 = x376;
1772
+ assign y378 = x377;
1773
+ assign y379 = x378;
1774
+ assign y380 = x379;
1775
+ assign y381 = x380;
1776
+ assign y382 = x381;
1777
+ assign y383 = x382;
1778
+ assign y384 = x383;
1779
+ assign y385 = x384;
1780
+ assign y386 = x385;
1781
+ assign y387 = x386;
1782
+ assign y388 = x387;
1783
+ assign y389 = x388;
1784
+ assign y390 = x389;
1785
+ assign y391 = x390;
1786
+ assign y392 = x391;
1787
+ assign y393 = x392;
1788
+ assign y394 = x393;
1789
+ assign y395 = x394;
1790
+ assign y396 = x395;
1791
+ assign y397 = x396;
1792
+ assign y398 = x397;
1793
+ assign y399 = x398;
1794
+ assign y400 = x399;
1795
+ assign y401 = x400;
1796
+ assign y402 = x401;
1797
+ assign y403 = x402;
1798
+ assign y404 = x403;
1799
+ assign y405 = x404;
1800
+ assign y406 = x405;
1801
+ assign y407 = x406;
1802
+ assign y408 = x407;
1803
+ assign y409 = x408;
1804
+ assign y410 = x409;
1805
+ assign y411 = x410;
1806
+ assign y412 = x411;
1807
+ assign y413 = x412;
1808
+ assign y414 = x413;
1809
+ assign y415 = x414;
1810
+ assign y416 = x415;
1811
+ assign y417 = x416;
1812
+ assign y418 = x417;
1813
+ assign y419 = x418;
1814
+ assign y420 = x419;
1815
+ assign y421 = x420;
1816
+ assign y422 = x421;
1817
+ assign y423 = x422;
1818
+ assign y424 = x423;
1819
+ assign y425 = x424;
1820
+ assign y426 = x425;
1821
+ assign y427 = x426;
1822
+ assign y428 = x427;
1823
+ assign y429 = x428;
1824
+ assign y430 = x429;
1825
+ assign y431 = x430;
1826
+ assign y432 = x431;
1827
+ assign y433 = x432;
1828
+ assign y434 = x433;
1829
+ assign y435 = x434;
1830
+ assign y436 = x435;
1831
+ assign y437 = x436;
1832
+ assign y438 = x437;
1833
+ assign y439 = x438;
1834
+ assign y440 = x439;
1835
+ assign y441 = x440;
1836
+ assign y442 = x441;
1837
+ assign y443 = x442;
1838
+ assign y444 = x443;
1839
+ assign y445 = x444;
1840
+ assign y446 = x445;
1841
+ assign y447 = x446;
1842
+ always @(posedge clk)
1843
+ if (rst)
1844
+ d0 <= rst_val[0];
1845
+ else if (prog)
1846
+ d0 <= seed[0];
1847
+ else if (en)
1848
+ d0 <= x447;
1849
+ assign y0 = d0;
1850
+ assign x0a = y0;
1851
+ assign x21a = y0;
1852
+ assign x1a = y1;
1853
+ assign x22a = y1;
1854
+ assign x2a = y2;
1855
+ assign x23a = y2;
1856
+ assign x3a = y3;
1857
+ assign x24a = y3;
1858
+ assign x4a = y4;
1859
+ assign x25a = y4;
1860
+ assign x5a = y5;
1861
+ assign x26a = y5;
1862
+ assign x6a = y6;
1863
+ assign x27a = y6;
1864
+ assign x7a = y7;
1865
+ assign x28a = y7;
1866
+ assign x8a = y8;
1867
+ assign x29a = y8;
1868
+ assign x9a = y9;
1869
+ assign x30a = y9;
1870
+ assign x10a = y10;
1871
+ assign x31a = y10;
1872
+ assign x11a = y11;
1873
+ assign x32a = y11;
1874
+ assign x12a = y12;
1875
+ assign x33a = y12;
1876
+ assign x13a = y13;
1877
+ assign x34a = y13;
1878
+ assign x14a = y14;
1879
+ assign x35a = y14;
1880
+ assign x15a = y15;
1881
+ assign x36a = y15;
1882
+ assign x16a = y16;
1883
+ assign x37a = y16;
1884
+ assign x17a = y17;
1885
+ assign x38a = y17;
1886
+ assign x18a = y18;
1887
+ assign x39a = y18;
1888
+ assign x19a = y19;
1889
+ assign x40a = y19;
1890
+ assign x20a = y20;
1891
+ assign x41a = y20;
1892
+ assign x21b = y21;
1893
+ assign x42a = y21;
1894
+ assign x22b = y22;
1895
+ assign x43a = y22;
1896
+ assign x23b = y23;
1897
+ assign x44a = y23;
1898
+ assign x24b = y24;
1899
+ assign x45a = y24;
1900
+ assign x25b = y25;
1901
+ assign x46a = y25;
1902
+ assign x26b = y26;
1903
+ assign x47a = y26;
1904
+ assign x27b = y27;
1905
+ assign x48a = y27;
1906
+ assign x28b = y28;
1907
+ assign x49a = y28;
1908
+ assign x29b = y29;
1909
+ assign x50a = y29;
1910
+ assign x30b = y30;
1911
+ assign x51a = y30;
1912
+ assign x31b = y31;
1913
+ assign x52a = y31;
1914
+ assign x32b = y32;
1915
+ assign x53a = y32;
1916
+ assign x33b = y33;
1917
+ assign x54a = y33;
1918
+ assign x34b = y34;
1919
+ assign x55a = y34;
1920
+ assign x35b = y35;
1921
+ assign x56a = y35;
1922
+ assign x36b = y36;
1923
+ assign x57a = y36;
1924
+ assign x37b = y37;
1925
+ assign x58a = y37;
1926
+ assign x38b = y38;
1927
+ assign x59a = y38;
1928
+ assign x39b = y39;
1929
+ assign x60a = y39;
1930
+ assign x40b = y40;
1931
+ assign x61a = y40;
1932
+ assign x41b = y41;
1933
+ assign x62a = y41;
1934
+ assign x42b = y42;
1935
+ assign x63a = y42;
1936
+ assign x43b = y43;
1937
+ assign x64a = y43;
1938
+ assign x44b = y44;
1939
+ assign x65a = y44;
1940
+ assign x45b = y45;
1941
+ assign x66a = y45;
1942
+ assign x46b = y46;
1943
+ assign x67a = y46;
1944
+ assign x47b = y47;
1945
+ assign x68a = y47;
1946
+ assign x48b = y48;
1947
+ assign x69a = y48;
1948
+ assign x49b = y49;
1949
+ assign x70a = y49;
1950
+ assign x50b = y50;
1951
+ assign x71a = y50;
1952
+ assign x51b = y51;
1953
+ assign x72a = y51;
1954
+ assign x52b = y52;
1955
+ assign x73a = y52;
1956
+ assign x53b = y53;
1957
+ assign x74a = y53;
1958
+ assign x54b = y54;
1959
+ assign x75a = y54;
1960
+ assign x55b = y55;
1961
+ assign x76a = y55;
1962
+ assign x56b = y56;
1963
+ assign x77a = y56;
1964
+ assign x57b = y57;
1965
+ assign x78a = y57;
1966
+ assign x58b = y58;
1967
+ assign x79a = y58;
1968
+ assign x59b = y59;
1969
+ assign x80a = y59;
1970
+ assign x60b = y60;
1971
+ assign x81a = y60;
1972
+ assign x61b = y61;
1973
+ assign x82a = y61;
1974
+ assign x62b = y62;
1975
+ assign x83a = y62;
1976
+ assign x63b = y63;
1977
+ assign x84a = y63;
1978
+ assign x64b = y64;
1979
+ assign x85a = y64;
1980
+ assign x65b = y65;
1981
+ assign x86a = y65;
1982
+ assign x66b = y66;
1983
+ assign x87a = y66;
1984
+ assign x67b = y67;
1985
+ assign x88a = y67;
1986
+ assign x68b = y68;
1987
+ assign x89a = y68;
1988
+ assign x69b = y69;
1989
+ assign x90a = y69;
1990
+ assign x70b = y70;
1991
+ assign x91a = y70;
1992
+ assign x71b = y71;
1993
+ assign x92a = y71;
1994
+ assign x72b = y72;
1995
+ assign x93a = y72;
1996
+ assign x73b = y73;
1997
+ assign x94a = y73;
1998
+ assign x74b = y74;
1999
+ assign x95a = y74;
2000
+ assign x75b = y75;
2001
+ assign x96a = y75;
2002
+ assign x76b = y76;
2003
+ assign x97a = y76;
2004
+ assign x77b = y77;
2005
+ assign x98a = y77;
2006
+ assign x78b = y78;
2007
+ assign x99a = y78;
2008
+ assign x79b = y79;
2009
+ assign x100a = y79;
2010
+ assign x80b = y80;
2011
+ assign x101a = y80;
2012
+ assign x81b = y81;
2013
+ assign x102a = y81;
2014
+ assign x82b = y82;
2015
+ assign x103a = y82;
2016
+ assign x83b = y83;
2017
+ assign x104a = y83;
2018
+ assign x84b = y84;
2019
+ assign x105a = y84;
2020
+ assign x85b = y85;
2021
+ assign x106a = y85;
2022
+ assign x86b = y86;
2023
+ assign x107a = y86;
2024
+ assign x87b = y87;
2025
+ assign x108a = y87;
2026
+ assign x88b = y88;
2027
+ assign x109a = y88;
2028
+ assign x89b = y89;
2029
+ assign x110a = y89;
2030
+ assign x90b = y90;
2031
+ assign x111a = y90;
2032
+ assign x91b = y91;
2033
+ assign x112a = y91;
2034
+ assign x92b = y92;
2035
+ assign x113a = y92;
2036
+ assign x93b = y93;
2037
+ assign x114a = y93;
2038
+ assign x94b = y94;
2039
+ assign x115a = y94;
2040
+ assign x95b = y95;
2041
+ assign x116a = y95;
2042
+ assign x96b = y96;
2043
+ assign x117a = y96;
2044
+ assign x97b = y97;
2045
+ assign x118a = y97;
2046
+ assign x98b = y98;
2047
+ assign x119a = y98;
2048
+ assign x99b = y99;
2049
+ assign x120a = y99;
2050
+ assign x100b = y100;
2051
+ assign x121a = y100;
2052
+ assign x101b = y101;
2053
+ assign x122a = y101;
2054
+ assign x102b = y102;
2055
+ assign x123a = y102;
2056
+ assign x103b = y103;
2057
+ assign x124a = y103;
2058
+ assign x104b = y104;
2059
+ assign x125a = y104;
2060
+ assign x105b = y105;
2061
+ assign x126a = y105;
2062
+ assign x106b = y106;
2063
+ assign x127a = y106;
2064
+ assign x107b = y107;
2065
+ assign x128a = y107;
2066
+ assign x108b = y108;
2067
+ assign x129a = y108;
2068
+ assign x109b = y109;
2069
+ assign x130a = y109;
2070
+ assign x110b = y110;
2071
+ assign x131a = y110;
2072
+ assign x111b = y111;
2073
+ assign x132a = y111;
2074
+ assign x112b = y112;
2075
+ assign x133a = y112;
2076
+ assign x113b = y113;
2077
+ assign x134a = y113;
2078
+ assign x114b = y114;
2079
+ assign x135a = y114;
2080
+ assign x115b = y115;
2081
+ assign x136a = y115;
2082
+ assign x116b = y116;
2083
+ assign x137a = y116;
2084
+ assign x117b = y117;
2085
+ assign x138a = y117;
2086
+ assign x118b = y118;
2087
+ assign x139a = y118;
2088
+ assign x119b = y119;
2089
+ assign x140a = y119;
2090
+ assign x120b = y120;
2091
+ assign x141a = y120;
2092
+ assign x121b = y121;
2093
+ assign x142a = y121;
2094
+ assign x122b = y122;
2095
+ assign x143a = y122;
2096
+ assign x123b = y123;
2097
+ assign x144a = y123;
2098
+ assign x124b = y124;
2099
+ assign x145a = y124;
2100
+ assign x125b = y125;
2101
+ assign x146a = y125;
2102
+ assign x126b = y126;
2103
+ assign x147a = y126;
2104
+ assign x127b = y127;
2105
+ assign x148a = y127;
2106
+ assign x128b = y128;
2107
+ assign x149a = y128;
2108
+ assign x129b = y129;
2109
+ assign x150a = y129;
2110
+ assign x130b = y130;
2111
+ assign x151a = y130;
2112
+ assign x131b = y131;
2113
+ assign x152a = y131;
2114
+ assign x132b = y132;
2115
+ assign x153a = y132;
2116
+ assign x133b = y133;
2117
+ assign x154a = y133;
2118
+ assign x134b = y134;
2119
+ assign x155a = y134;
2120
+ assign x135b = y135;
2121
+ assign x156a = y135;
2122
+ assign x136b = y136;
2123
+ assign x157a = y136;
2124
+ assign x137b = y137;
2125
+ assign x158a = y137;
2126
+ assign x138b = y138;
2127
+ assign x159a = y138;
2128
+ assign x139b = y139;
2129
+ assign x160a = y139;
2130
+ assign x140b = y140;
2131
+ assign x161a = y140;
2132
+ assign x141b = y141;
2133
+ assign x162a = y141;
2134
+ assign x142b = y142;
2135
+ assign x163a = y142;
2136
+ assign x143b = y143;
2137
+ assign x164a = y143;
2138
+ assign x144b = y144;
2139
+ assign x165a = y144;
2140
+ assign x145b = y145;
2141
+ assign x166a = y145;
2142
+ assign x146b = y146;
2143
+ assign x167a = y146;
2144
+ assign x147b = y147;
2145
+ assign x168a = y147;
2146
+ assign x148b = y148;
2147
+ assign x169a = y148;
2148
+ assign x149b = y149;
2149
+ assign x170a = y149;
2150
+ assign x150b = y150;
2151
+ assign x171a = y150;
2152
+ assign x151b = y151;
2153
+ assign x172a = y151;
2154
+ assign x152b = y152;
2155
+ assign x173a = y152;
2156
+ assign x153b = y153;
2157
+ assign x174a = y153;
2158
+ assign x154b = y154;
2159
+ assign x175a = y154;
2160
+ assign x155b = y155;
2161
+ assign x176a = y155;
2162
+ assign x156b = y156;
2163
+ assign x177a = y156;
2164
+ assign x157b = y157;
2165
+ assign x178a = y157;
2166
+ assign x158b = y158;
2167
+ assign x179a = y158;
2168
+ assign x159b = y159;
2169
+ assign x180a = y159;
2170
+ assign x160b = y160;
2171
+ assign x181a = y160;
2172
+ assign x161b = y161;
2173
+ assign x182a = y161;
2174
+ assign x162b = y162;
2175
+ assign x183a = y162;
2176
+ assign x163b = y163;
2177
+ assign x184a = y163;
2178
+ assign x164b = y164;
2179
+ assign x185a = y164;
2180
+ assign x165b = y165;
2181
+ assign x186a = y165;
2182
+ assign x166b = y166;
2183
+ assign x187a = y166;
2184
+ assign x167b = y167;
2185
+ assign x188a = y167;
2186
+ assign x168b = y168;
2187
+ assign x189a = y168;
2188
+ assign x169b = y169;
2189
+ assign x190a = y169;
2190
+ assign x170b = y170;
2191
+ assign x191a = y170;
2192
+ assign x171b = y171;
2193
+ assign x192a = y171;
2194
+ assign x172b = y172;
2195
+ assign x193a = y172;
2196
+ assign x173b = y173;
2197
+ assign x194a = y173;
2198
+ assign x174b = y174;
2199
+ assign x195a = y174;
2200
+ assign x175b = y175;
2201
+ assign x196a = y175;
2202
+ assign x176b = y176;
2203
+ assign x197a = y176;
2204
+ assign x177b = y177;
2205
+ assign x198a = y177;
2206
+ assign x178b = y178;
2207
+ assign x199a = y178;
2208
+ assign x179b = y179;
2209
+ assign x200a = y179;
2210
+ assign x180b = y180;
2211
+ assign x201a = y180;
2212
+ assign x181b = y181;
2213
+ assign x202a = y181;
2214
+ assign x182b = y182;
2215
+ assign x203a = y182;
2216
+ assign x183b = y183;
2217
+ assign x204a = y183;
2218
+ assign x184b = y184;
2219
+ assign x205a = y184;
2220
+ assign x185b = y185;
2221
+ assign x206a = y185;
2222
+ assign x186b = y186;
2223
+ assign x207a = y186;
2224
+ assign x187b = y187;
2225
+ assign x208a = y187;
2226
+ assign x188b = y188;
2227
+ assign x209a = y188;
2228
+ assign x189b = y189;
2229
+ assign x210a = y189;
2230
+ assign x190b = y190;
2231
+ assign x211a = y190;
2232
+ assign x191b = y191;
2233
+ assign x212a = y191;
2234
+ assign x192b = y192;
2235
+ assign x213a = y192;
2236
+ assign x193b = y193;
2237
+ assign x214a = y193;
2238
+ assign x194b = y194;
2239
+ assign x215a = y194;
2240
+ assign x195b = y195;
2241
+ assign x216a = y195;
2242
+ assign x196b = y196;
2243
+ assign x217a = y196;
2244
+ assign x197b = y197;
2245
+ assign x218a = y197;
2246
+ assign x198b = y198;
2247
+ assign x219a = y198;
2248
+ assign x199b = y199;
2249
+ assign x220a = y199;
2250
+ assign x200b = y200;
2251
+ assign x221a = y200;
2252
+ assign x201b = y201;
2253
+ assign x222a = y201;
2254
+ assign x202b = y202;
2255
+ assign x223a = y202;
2256
+ assign x203b = y203;
2257
+ assign x224a = y203;
2258
+ assign x204b = y204;
2259
+ assign x225a = y204;
2260
+ assign x205b = y205;
2261
+ assign x226a = y205;
2262
+ assign x206b = y206;
2263
+ assign x227a = y206;
2264
+ assign x207b = y207;
2265
+ assign x228a = y207;
2266
+ assign x208b = y208;
2267
+ assign x229a = y208;
2268
+ assign x209b = y209;
2269
+ assign x230a = y209;
2270
+ assign x210b = y210;
2271
+ assign x231a = y210;
2272
+ assign x211b = y211;
2273
+ assign x232a = y211;
2274
+ assign x212b = y212;
2275
+ assign x233a = y212;
2276
+ assign x213b = y213;
2277
+ assign x234a = y213;
2278
+ assign x214b = y214;
2279
+ assign x235a = y214;
2280
+ assign x215b = y215;
2281
+ assign x236a = y215;
2282
+ assign x216b = y216;
2283
+ assign x237a = y216;
2284
+ assign x217b = y217;
2285
+ assign x238a = y217;
2286
+ assign x218b = y218;
2287
+ assign x239a = y218;
2288
+ assign x219b = y219;
2289
+ assign x240a = y219;
2290
+ assign x220b = y220;
2291
+ assign x241a = y220;
2292
+ assign x221b = y221;
2293
+ assign x242a = y221;
2294
+ assign x222b = y222;
2295
+ assign x243a = y222;
2296
+ assign x223b = y223;
2297
+ assign x244a = y223;
2298
+ assign x224b = y224;
2299
+ assign x245a = y224;
2300
+ assign x225b = y225;
2301
+ assign x246a = y225;
2302
+ assign x226b = y226;
2303
+ assign x247a = y226;
2304
+ assign x227b = y227;
2305
+ assign x248a = y227;
2306
+ assign x228b = y228;
2307
+ assign x249a = y228;
2308
+ assign x229b = y229;
2309
+ assign x250a = y229;
2310
+ assign x230b = y230;
2311
+ assign x251a = y230;
2312
+ assign x231b = y231;
2313
+ assign x252a = y231;
2314
+ assign x232b = y232;
2315
+ assign x253a = y232;
2316
+ assign x233b = y233;
2317
+ assign x254a = y233;
2318
+ assign x234b = y234;
2319
+ assign x255a = y234;
2320
+ assign x235b = y235;
2321
+ assign x256a = y235;
2322
+ assign x236b = y236;
2323
+ assign x257a = y236;
2324
+ assign x237b = y237;
2325
+ assign x258a = y237;
2326
+ assign x238b = y238;
2327
+ assign x259a = y238;
2328
+ assign x239b = y239;
2329
+ assign x260a = y239;
2330
+ assign x240b = y240;
2331
+ assign x261a = y240;
2332
+ assign x241b = y241;
2333
+ assign x262a = y241;
2334
+ assign x242b = y242;
2335
+ assign x263a = y242;
2336
+ assign x243b = y243;
2337
+ assign x264a = y243;
2338
+ assign x244b = y244;
2339
+ assign x265a = y244;
2340
+ assign x245b = y245;
2341
+ assign x266a = y245;
2342
+ assign x246b = y246;
2343
+ assign x267a = y246;
2344
+ assign x247b = y247;
2345
+ assign x268a = y247;
2346
+ assign x248b = y248;
2347
+ assign x269a = y248;
2348
+ assign x249b = y249;
2349
+ assign x270a = y249;
2350
+ assign x250b = y250;
2351
+ assign x271a = y250;
2352
+ assign x251b = y251;
2353
+ assign x272a = y251;
2354
+ assign x252b = y252;
2355
+ assign x273a = y252;
2356
+ assign x253b = y253;
2357
+ assign x274a = y253;
2358
+ assign x254b = y254;
2359
+ assign x275a = y254;
2360
+ assign x255b = y255;
2361
+ assign x276a = y255;
2362
+ assign x256b = y256;
2363
+ assign x277a = y256;
2364
+ assign x257b = y257;
2365
+ assign x278a = y257;
2366
+ assign x258b = y258;
2367
+ assign x279a = y258;
2368
+ assign x259b = y259;
2369
+ assign x280a = y259;
2370
+ assign x260b = y260;
2371
+ assign x281a = y260;
2372
+ assign x261b = y261;
2373
+ assign x282a = y261;
2374
+ assign x262b = y262;
2375
+ assign x283a = y262;
2376
+ assign x263b = y263;
2377
+ assign x284a = y263;
2378
+ assign x264b = y264;
2379
+ assign x285a = y264;
2380
+ assign x265b = y265;
2381
+ assign x286a = y265;
2382
+ assign x266b = y266;
2383
+ assign x287a = y266;
2384
+ assign x267b = y267;
2385
+ assign x288a = y267;
2386
+ assign x268b = y268;
2387
+ assign x289a = y268;
2388
+ assign x269b = y269;
2389
+ assign x290a = y269;
2390
+ assign x270b = y270;
2391
+ assign x291a = y270;
2392
+ assign x271b = y271;
2393
+ assign x292a = y271;
2394
+ assign x272b = y272;
2395
+ assign x293a = y272;
2396
+ assign x273b = y273;
2397
+ assign x294a = y273;
2398
+ assign x274b = y274;
2399
+ assign x295a = y274;
2400
+ assign x275b = y275;
2401
+ assign x296a = y275;
2402
+ assign x276b = y276;
2403
+ assign x297a = y276;
2404
+ assign x277b = y277;
2405
+ assign x298a = y277;
2406
+ assign x278b = y278;
2407
+ assign x299a = y278;
2408
+ assign x279b = y279;
2409
+ assign x300a = y279;
2410
+ assign x280b = y280;
2411
+ assign x301a = y280;
2412
+ assign x281b = y281;
2413
+ assign x302a = y281;
2414
+ assign x282b = y282;
2415
+ assign x303a = y282;
2416
+ assign x283b = y283;
2417
+ assign x304a = y283;
2418
+ assign x284b = y284;
2419
+ assign x305a = y284;
2420
+ assign x285b = y285;
2421
+ assign x306a = y285;
2422
+ assign x286b = y286;
2423
+ assign x307a = y286;
2424
+ assign x287b = y287;
2425
+ assign x308a = y287;
2426
+ assign x288b = y288;
2427
+ assign x309a = y288;
2428
+ assign x289b = y289;
2429
+ assign x310a = y289;
2430
+ assign x290b = y290;
2431
+ assign x311a = y290;
2432
+ assign x291b = y291;
2433
+ assign x312a = y291;
2434
+ assign x292b = y292;
2435
+ assign x313a = y292;
2436
+ assign x293b = y293;
2437
+ assign x314a = y293;
2438
+ assign x294b = y294;
2439
+ assign x315a = y294;
2440
+ assign x295b = y295;
2441
+ assign x316a = y295;
2442
+ assign x296b = y296;
2443
+ assign x317a = y296;
2444
+ assign x297b = y297;
2445
+ assign x318a = y297;
2446
+ assign x298b = y298;
2447
+ assign x319a = y298;
2448
+ assign x299b = y299;
2449
+ assign x320a = y299;
2450
+ assign x300b = y300;
2451
+ assign x321a = y300;
2452
+ assign x301b = y301;
2453
+ assign x322a = y301;
2454
+ assign x302b = y302;
2455
+ assign x323a = y302;
2456
+ assign x303b = y303;
2457
+ assign x324a = y303;
2458
+ assign x304b = y304;
2459
+ assign x325a = y304;
2460
+ assign x305b = y305;
2461
+ assign x326a = y305;
2462
+ assign x306b = y306;
2463
+ assign x327a = y306;
2464
+ assign x307b = y307;
2465
+ assign x328a = y307;
2466
+ assign x308b = y308;
2467
+ assign x329a = y308;
2468
+ assign x309b = y309;
2469
+ assign x330a = y309;
2470
+ assign x310b = y310;
2471
+ assign x331a = y310;
2472
+ assign x311b = y311;
2473
+ assign x332a = y311;
2474
+ assign x312b = y312;
2475
+ assign x333a = y312;
2476
+ assign x313b = y313;
2477
+ assign x334a = y313;
2478
+ assign x314b = y314;
2479
+ assign x335a = y314;
2480
+ assign x315b = y315;
2481
+ assign x336a = y315;
2482
+ assign x316b = y316;
2483
+ assign x337a = y316;
2484
+ assign x317b = y317;
2485
+ assign x338a = y317;
2486
+ assign x318b = y318;
2487
+ assign x339a = y318;
2488
+ assign x319b = y319;
2489
+ assign x340a = y319;
2490
+ assign x320b = y320;
2491
+ assign x341a = y320;
2492
+ assign x321b = y321;
2493
+ assign x342a = y321;
2494
+ assign x322b = y322;
2495
+ assign x343a = y322;
2496
+ assign x323b = y323;
2497
+ assign x344a = y323;
2498
+ assign x324b = y324;
2499
+ assign x345a = y324;
2500
+ assign x325b = y325;
2501
+ assign x346a = y325;
2502
+ assign x326b = y326;
2503
+ assign x347a = y326;
2504
+ assign x327b = y327;
2505
+ assign x348a = y327;
2506
+ assign x328b = y328;
2507
+ assign x349a = y328;
2508
+ assign x329b = y329;
2509
+ assign x350a = y329;
2510
+ assign x330b = y330;
2511
+ assign x351a = y330;
2512
+ assign x331b = y331;
2513
+ assign x352a = y331;
2514
+ assign x332b = y332;
2515
+ assign x353a = y332;
2516
+ assign x333b = y333;
2517
+ assign x354a = y333;
2518
+ assign x334b = y334;
2519
+ assign x355a = y334;
2520
+ assign x335b = y335;
2521
+ assign x356a = y335;
2522
+ assign x336b = y336;
2523
+ assign x357a = y336;
2524
+ assign x337b = y337;
2525
+ assign x358a = y337;
2526
+ assign x338b = y338;
2527
+ assign x359a = y338;
2528
+ assign x339b = y339;
2529
+ assign x360a = y339;
2530
+ assign x340b = y340;
2531
+ assign x361a = y340;
2532
+ assign x341b = y341;
2533
+ assign x362a = y341;
2534
+ assign x342b = y342;
2535
+ assign x363a = y342;
2536
+ assign x343b = y343;
2537
+ assign x364a = y343;
2538
+ assign x344b = y344;
2539
+ assign x365a = y344;
2540
+ assign x345b = y345;
2541
+ assign x366a = y345;
2542
+ assign x346b = y346;
2543
+ assign x367a = y346;
2544
+ assign x347b = y347;
2545
+ assign x368a = y347;
2546
+ assign x348b = y348;
2547
+ assign x369a = y348;
2548
+ assign x349b = y349;
2549
+ assign x370a = y349;
2550
+ assign x350b = y350;
2551
+ assign x371a = y350;
2552
+ assign x351b = y351;
2553
+ assign x372a = y351;
2554
+ assign x352b = y352;
2555
+ assign x373a = y352;
2556
+ assign x353b = y353;
2557
+ assign x374a = y353;
2558
+ assign x354b = y354;
2559
+ assign x375a = y354;
2560
+ assign x355b = y355;
2561
+ assign x376a = y355;
2562
+ assign x356b = y356;
2563
+ assign x377a = y356;
2564
+ assign x357b = y357;
2565
+ assign x378a = y357;
2566
+ assign x358b = y358;
2567
+ assign x379a = y358;
2568
+ assign x359b = y359;
2569
+ assign x380a = y359;
2570
+ assign x360b = y360;
2571
+ assign x381a = y360;
2572
+ assign x361b = y361;
2573
+ assign x382a = y361;
2574
+ assign x362b = y362;
2575
+ assign x383a = y362;
2576
+ assign x363b = y363;
2577
+ assign x384a = y363;
2578
+ assign x364b = y364;
2579
+ assign x385a = y364;
2580
+ assign x365b = y365;
2581
+ assign x386a = y365;
2582
+ assign x366b = y366;
2583
+ assign x387a = y366;
2584
+ assign x367b = y367;
2585
+ assign x388a = y367;
2586
+ assign x368b = y368;
2587
+ assign x389a = y368;
2588
+ assign x369b = y369;
2589
+ assign x390a = y369;
2590
+ assign x370b = y370;
2591
+ assign x391a = y370;
2592
+ assign x371b = y371;
2593
+ assign x392a = y371;
2594
+ assign x372b = y372;
2595
+ assign x393a = y372;
2596
+ assign x373b = y373;
2597
+ assign x394a = y373;
2598
+ assign x374b = y374;
2599
+ assign x395a = y374;
2600
+ assign x375b = y375;
2601
+ assign x396a = y375;
2602
+ assign x376b = y376;
2603
+ assign x397a = y376;
2604
+ assign x377b = y377;
2605
+ assign x398a = y377;
2606
+ assign x378b = y378;
2607
+ assign x399a = y378;
2608
+ assign x379b = y379;
2609
+ assign x400a = y379;
2610
+ assign x380b = y380;
2611
+ assign x401a = y380;
2612
+ assign x381b = y381;
2613
+ assign x402a = y381;
2614
+ assign x382b = y382;
2615
+ assign x403a = y382;
2616
+ assign x383b = y383;
2617
+ assign x404a = y383;
2618
+ assign x384b = y384;
2619
+ assign x405a = y384;
2620
+ assign x385b = y385;
2621
+ assign x406a = y385;
2622
+ assign x386b = y386;
2623
+ assign x407a = y386;
2624
+ assign x387b = y387;
2625
+ assign x408a = y387;
2626
+ assign x388b = y388;
2627
+ assign x409a = y388;
2628
+ assign x389b = y389;
2629
+ assign x410a = y389;
2630
+ assign x390b = y390;
2631
+ assign x411a = y390;
2632
+ assign x391b = y391;
2633
+ assign x412a = y391;
2634
+ assign x392b = y392;
2635
+ assign x413a = y392;
2636
+ assign x393b = y393;
2637
+ assign x414a = y393;
2638
+ assign x394b = y394;
2639
+ assign x415a = y394;
2640
+ assign x395b = y395;
2641
+ assign x416a = y395;
2642
+ assign x396b = y396;
2643
+ assign x417a = y396;
2644
+ assign x397b = y397;
2645
+ assign x418a = y397;
2646
+ assign x398b = y398;
2647
+ assign x419a = y398;
2648
+ assign x399b = y399;
2649
+ assign x420a = y399;
2650
+ assign x400b = y400;
2651
+ assign x421a = y400;
2652
+ assign x401b = y401;
2653
+ assign x422a = y401;
2654
+ assign x402b = y402;
2655
+ assign x423a = y402;
2656
+ assign x403b = y403;
2657
+ assign x424a = y403;
2658
+ assign x404b = y404;
2659
+ assign x425a = y404;
2660
+ assign x405b = y405;
2661
+ assign x426a = y405;
2662
+ assign x406b = y406;
2663
+ assign x427a = y406;
2664
+ assign x407b = y407;
2665
+ assign x428a = y407;
2666
+ assign x408b = y408;
2667
+ assign x429a = y408;
2668
+ assign x409b = y409;
2669
+ assign x430a = y409;
2670
+ assign x410b = y410;
2671
+ assign x431a = y410;
2672
+ assign x411b = y411;
2673
+ assign x432a = y411;
2674
+ assign x412b = y412;
2675
+ assign x433a = y412;
2676
+ assign x413b = y413;
2677
+ assign x434a = y413;
2678
+ assign x414b = y414;
2679
+ assign x435a = y414;
2680
+ assign x415b = y415;
2681
+ assign x436a = y415;
2682
+ assign x416b = y416;
2683
+ assign x437a = y416;
2684
+ assign x417b = y417;
2685
+ assign x438a = y417;
2686
+ assign x418b = y418;
2687
+ assign x439a = y418;
2688
+ assign x419b = y419;
2689
+ assign x440a = y419;
2690
+ assign x420b = y420;
2691
+ assign x441a = y420;
2692
+ assign x421b = y421;
2693
+ assign x442a = y421;
2694
+ assign x422b = y422;
2695
+ assign x443a = y422;
2696
+ assign x423b = y423;
2697
+ assign x444a = y423;
2698
+ assign x424b = y424;
2699
+ assign x445a = y424;
2700
+ assign x425b = y425;
2701
+ assign x446a = y425;
2702
+ assign x426b = y426;
2703
+ assign x447a = y426;
2704
+ assign x427b = y427;
2705
+ always @(posedge clk)
2706
+ if (rst)
2707
+ d1 <= rst_val[1];
2708
+ else if (prog)
2709
+ d1 <= seed[1];
2710
+ else if (en)
2711
+ d1 <= y427;
2712
+ assign x0b = d1;
2713
+ assign x428b = y428;
2714
+ always @(posedge clk)
2715
+ if (rst)
2716
+ d2 <= rst_val[2];
2717
+ else if (prog)
2718
+ d2 <= seed[2];
2719
+ else if (en)
2720
+ d2 <= y428;
2721
+ assign x1b = d2;
2722
+ assign x429b = y429;
2723
+ always @(posedge clk)
2724
+ if (rst)
2725
+ d3 <= rst_val[3];
2726
+ else if (prog)
2727
+ d3 <= seed[3];
2728
+ else if (en)
2729
+ d3 <= y429;
2730
+ assign x2b = d3;
2731
+ assign x430b = y430;
2732
+ always @(posedge clk)
2733
+ if (rst)
2734
+ d4 <= rst_val[4];
2735
+ else if (prog)
2736
+ d4 <= seed[4];
2737
+ else if (en)
2738
+ d4 <= y430;
2739
+ assign x3b = d4;
2740
+ assign x431b = y431;
2741
+ always @(posedge clk)
2742
+ if (rst)
2743
+ d5 <= rst_val[5];
2744
+ else if (prog)
2745
+ d5 <= seed[5];
2746
+ else if (en)
2747
+ d5 <= y431;
2748
+ assign x4b = d5;
2749
+ assign x432b = y432;
2750
+ always @(posedge clk)
2751
+ if (rst)
2752
+ d6 <= rst_val[6];
2753
+ else if (prog)
2754
+ d6 <= seed[6];
2755
+ else if (en)
2756
+ d6 <= y432;
2757
+ assign x5b = d6;
2758
+ assign x433b = y433;
2759
+ always @(posedge clk)
2760
+ if (rst)
2761
+ d7 <= rst_val[7];
2762
+ else if (prog)
2763
+ d7 <= seed[7];
2764
+ else if (en)
2765
+ d7 <= y433;
2766
+ assign x6b = d7;
2767
+ assign x434b = y434;
2768
+ always @(posedge clk)
2769
+ if (rst)
2770
+ d8 <= rst_val[8];
2771
+ else if (prog)
2772
+ d8 <= seed[8];
2773
+ else if (en)
2774
+ d8 <= y434;
2775
+ assign x7b = d8;
2776
+ assign x435b = y435;
2777
+ always @(posedge clk)
2778
+ if (rst)
2779
+ d9 <= rst_val[9];
2780
+ else if (prog)
2781
+ d9 <= seed[9];
2782
+ else if (en)
2783
+ d9 <= y435;
2784
+ assign x8b = d9;
2785
+ assign x436b = y436;
2786
+ always @(posedge clk)
2787
+ if (rst)
2788
+ d10 <= rst_val[10];
2789
+ else if (prog)
2790
+ d10 <= seed[10];
2791
+ else if (en)
2792
+ d10 <= y436;
2793
+ assign x9b = d10;
2794
+ assign x437b = y437;
2795
+ always @(posedge clk)
2796
+ if (rst)
2797
+ d11 <= rst_val[11];
2798
+ else if (prog)
2799
+ d11 <= seed[11];
2800
+ else if (en)
2801
+ d11 <= y437;
2802
+ assign x10b = d11;
2803
+ assign x438b = y438;
2804
+ always @(posedge clk)
2805
+ if (rst)
2806
+ d12 <= rst_val[12];
2807
+ else if (prog)
2808
+ d12 <= seed[12];
2809
+ else if (en)
2810
+ d12 <= y438;
2811
+ assign x11b = d12;
2812
+ assign x439b = y439;
2813
+ always @(posedge clk)
2814
+ if (rst)
2815
+ d13 <= rst_val[13];
2816
+ else if (prog)
2817
+ d13 <= seed[13];
2818
+ else if (en)
2819
+ d13 <= y439;
2820
+ assign x12b = d13;
2821
+ assign x440b = y440;
2822
+ always @(posedge clk)
2823
+ if (rst)
2824
+ d14 <= rst_val[14];
2825
+ else if (prog)
2826
+ d14 <= seed[14];
2827
+ else if (en)
2828
+ d14 <= y440;
2829
+ assign x13b = d14;
2830
+ assign x441b = y441;
2831
+ always @(posedge clk)
2832
+ if (rst)
2833
+ d15 <= rst_val[15];
2834
+ else if (prog)
2835
+ d15 <= seed[15];
2836
+ else if (en)
2837
+ d15 <= y441;
2838
+ assign x14b = d15;
2839
+ assign x442b = y442;
2840
+ always @(posedge clk)
2841
+ if (rst)
2842
+ d16 <= rst_val[16];
2843
+ else if (prog)
2844
+ d16 <= seed[16];
2845
+ else if (en)
2846
+ d16 <= y442;
2847
+ assign x15b = d16;
2848
+ assign x443b = y443;
2849
+ always @(posedge clk)
2850
+ if (rst)
2851
+ d17 <= rst_val[17];
2852
+ else if (prog)
2853
+ d17 <= seed[17];
2854
+ else if (en)
2855
+ d17 <= y443;
2856
+ assign x16b = d17;
2857
+ assign x444b = y444;
2858
+ always @(posedge clk)
2859
+ if (rst)
2860
+ d18 <= rst_val[18];
2861
+ else if (prog)
2862
+ d18 <= seed[18];
2863
+ else if (en)
2864
+ d18 <= y444;
2865
+ assign x17b = d18;
2866
+ assign x445b = y445;
2867
+ always @(posedge clk)
2868
+ if (rst)
2869
+ d19 <= rst_val[19];
2870
+ else if (prog)
2871
+ d19 <= seed[19];
2872
+ else if (en)
2873
+ d19 <= y445;
2874
+ assign x18b = d19;
2875
+ assign x446b = y446;
2876
+ always @(posedge clk)
2877
+ if (rst)
2878
+ d20 <= rst_val[20];
2879
+ else if (prog)
2880
+ d20 <= seed[20];
2881
+ else if (en)
2882
+ d20 <= y446;
2883
+ assign x19b = d20;
2884
+ assign x447b = y447;
2885
+ always @(posedge clk)
2886
+ if (rst)
2887
+ d21 <= rst_val[21];
2888
+ else if (prog)
2889
+ d21 <= seed[21];
2890
+ else if (en)
2891
+ d21 <= y447;
2892
+ assign x20b = d21;
2893
+
2894
+ // Output assignment
2895
+ assign out = {y447,y446,y445,y444,y443,y442,y441,y440,y439,y438,y437,y436,y435,y434,y433,y432,y431,y430,y429,y428,y427,y426,y425,y424,y423,y422,y421,y420,y419,y418,y417,y416,y415,y414,y413,y412,y411,y410,y409,y408,y407,y406,y405,y404,y403,y402,y401,y400,y399,y398,y397,y396,y395,y394,y393,y392,y391,y390,y389,y388,y387,y386,y385,y384,y383,y382,y381,y380,y379,y378,y377,y376,y375,y374,y373,y372,y371,y370,y369,y368,y367,y366,y365,y364,y363,y362,y361,y360,y359,y358,y357,y356,y355,y354,y353,y352,y351,y350,y349,y348,y347,y346,y345,y344,y343,y342,y341,y340,y339,y338,y337,y336,y335,y334,y333,y332,y331,y330,y329,y328,y327,y326,y325,y324,y323,y322,y321,y320,y319,y318,y317,y316,y315,y314,y313,y312,y311,y310,y309,y308,y307,y306,y305,y304,y303,y302,y301,y300,y299,y298,y297,y296,y295,y294,y293,y292,y291,y290,y289,y288,y287,y286,y285,y284,y283,y282,y281,y280,y279,y278,y277,y276,y275,y274,y273,y272,y271,y270,y269,y268,y267,y266,y265,y264,y263,y262,y261,y260,y259,y258,y257,y256,y255,y254,y253,y252,y251,y250,y249,y248,y247,y246,y245,y244,y243,y242,y241,y240,y239,y238,y237,y236,y235,y234,y233,y232,y231,y230,y229,y228,y227,y226,y225,y224,y223,y222,y221,y220,y219,y218,y217,y216,y215,y214,y213,y212,y211,y210,y209,y208,y207,y206,y205,y204,y203,y202,y201,y200,y199,y198,y197,y196,y195,y194,y193,y192,y191,y190,y189,y188,y187,y186,y185,y184,y183,y182,y181,y180,y179,y178,y177,y176,y175,y174,y173,y172,y171,y170,y169,y168,y167,y166,y165,y164,y163,y162,y161,y160,y159,y158,y157,y156,y155,y154,y153,y152,y151,y150,y149,y148,y147,y146,y145,y144,y143,y142,y141,y140,y139,y138,y137,y136,y135,y134,y133,y132,y131,y130,y129,y128,y127,y126,y125,y124,y123,y122,y121,y120,y119,y118,y117,y116,y115,y114,y113,y112,y111,y110,y109,y108,y107,y106,y105,y104,y103,y102,y101,y100,y99,y98,y97,y96,y95,y94,y93,y92,y91,y90,y89,y88,y87,y86,y85,y84,y83,y82,y81,y80,y79,y78,y77,y76,y75,y74,y73,y72,y71,y70,y69,y68,y67,y66,y65,y64,y63,y62,y61,y60,y59,y58,y57,y56,y55,y54,y53,y52,y51,y50,y49,y48,y47,y46,y45,y44,y43,y42,y41,y40,y39,y38,y37,y36,y35,y34,y33,y32,y31,y30,y29,y28,y27,y26,y25,y24,y23,y22,y21,y20,y19,y18,y17,y16,y15,y14,y13,y12,y11,y10,y9,y8,y7,y6,y5,y4,y3,y2,y1,y0};
2896
+
2897
+ endmodule
ChFrenkel_ReckOn/src/reckon.v ADDED
@@ -0,0 +1,472 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "reckon.v" - Toplevel file
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: Unpublished parts were removed. Padring (made of technology-specific cells) has been removed from the toplevel.
25
+ //
26
+ //------------------------------------------------------------------------------
27
+
28
+
29
+ `define EXT_CLK_ONLY 1
30
+
31
+ module reckon #(
32
+ parameter N = 256,
33
+ parameter M = 8
34
+ )(
35
+ // Global inputs -------------------------------
36
+ input wire CLK_EXT,
37
+ input wire CLK_INT_EN,
38
+ input wire RST,
39
+
40
+ // SPI slave -------------------------------
41
+ input wire SCK,
42
+ input wire MOSI,
43
+ output wire MISO,
44
+
45
+ // Input bus and control inputs ------------------
46
+ input wire [M-1:0] AERIN_ADDR,
47
+ input wire AERIN_REQ,
48
+ output wire AERIN_ACK,
49
+ input wire AERIN_TAR_EN,
50
+ input wire SAMPLE,
51
+ input wire TIME_TICK,
52
+ input wire TARGET_VALID,
53
+ input wire INFER_ACC,
54
+
55
+ // Output bus and control outputs ----------------
56
+ output wire SPI_RDY,
57
+ output wire TIMING_ERROR_RDY,
58
+ output wire OUT_REQ,
59
+ input wire OUT_ACK,
60
+ output wire [ 7:0] OUT_DATA
61
+ );
62
+
63
+ //----------------------------------------------------------------------------------
64
+ // Internal regs and wires
65
+ //----------------------------------------------------------------------------------
66
+
67
+ // Reset and clock
68
+ wire CLK, CLK_INT;
69
+ wire CLK_INT_MON;
70
+ reg RST_sync_int, RST_sync;
71
+ reg SPI_EN_CONF_sync_int, SPI_EN_CONF_sync;
72
+
73
+ // SPI
74
+ wire MISO_int;
75
+ wire REQ_TAR;
76
+ wire [ 15:0] SPI_ADDR;
77
+ wire [ 31:0] SPI_DATA;
78
+ wire SPI_EN_CONF;
79
+ wire [ 31:0] SRNN_READBACK;
80
+ // Toplevel
81
+ wire [ 8:0] SPI_RO_STAGE_SEL;
82
+ wire SPI_GET_CLKINT_OUT;
83
+ wire SPI_GET_TAR_REQ_OUT;
84
+ // Control
85
+ wire SPI_RST_MODE;
86
+ wire [ 2:0] SPI_DO_EPROP;
87
+ wire SPI_LOCAL_TICK;
88
+ wire SPI_ERROR_HALT;
89
+ wire [ 2:0] SPI_FP_LOC_WINP;
90
+ wire [ 2:0] SPI_FP_LOC_WREC;
91
+ wire [ 2:0] SPI_FP_LOC_WOUT;
92
+ wire [ 2:0] SPI_FP_LOC_TINP;
93
+ wire [ 2:0] SPI_FP_LOC_TREC;
94
+ wire [ 2:0] SPI_FP_LOC_TOUT;
95
+ wire [ 3:0] SPI_LEARN_SIG_SCALE;
96
+ wire [ 2:0] SPI_REGUL_MODE;
97
+ wire [ 1:0] SPI_REGUL_W;
98
+ wire SPI_EN_STOCH_ROUND;
99
+ wire [ 7:0] SPI_SRAM_SPEEDMODE;
100
+ wire SPI_TIMING_MODE;
101
+ wire SPI_REGRESSION;
102
+ wire SPI_SINGLE_LABEL;
103
+ wire SPI_NO_OUT_ACT;
104
+ wire SPI_SEND_PER_TIMESTEP;
105
+ wire SPI_SEND_LABEL_ONLY;
106
+ wire SPI_NOISE_EN;
107
+ wire SPI_FORCE_TRACES;
108
+ // Network
109
+ wire [ 31:0] SPI_CYCLES_PER_TICK;
110
+ wire [ 127:0] SPI_ALPHA_CONF;
111
+ wire [ 7:0] SPI_KAPPA;
112
+ wire signed [ 15:0] SPI_THR_H_0;
113
+ wire signed [ 15:0] SPI_THR_H_1;
114
+ wire signed [ 15:0] SPI_THR_H_2;
115
+ wire signed [ 15:0] SPI_THR_H_3;
116
+ wire signed [ 4:0] SPI_H_0;
117
+ wire signed [ 4:0] SPI_H_1;
118
+ wire signed [ 4:0] SPI_H_2;
119
+ wire signed [ 4:0] SPI_H_3;
120
+ wire signed [ 4:0] SPI_H_4;
121
+ wire [ 4:0] SPI_LR_R_WINP;
122
+ wire [ 4:0] SPI_LR_P_WINP;
123
+ wire [ 4:0] SPI_LR_R_WREC;
124
+ wire [ 4:0] SPI_LR_P_WREC;
125
+ wire [ 4:0] SPI_LR_R_WOUT;
126
+ wire [ 4:0] SPI_LR_P_WOUT;
127
+ wire [ 24:0] SPI_SEED_INP;
128
+ wire [ 24:0] SPI_SEED_REC;
129
+ wire [ 21:0] SPI_SEED_OUT;
130
+ wire [ 29:0] SPI_SEED_STRND_NEUR;
131
+ wire [ 14:0] SPI_SEED_STRND_ONEUR;
132
+ wire [ 29:0] SPI_SEED_STRND_TINP;
133
+ wire [ 29:0] SPI_SEED_STRND_TREC;
134
+ wire [ 29:0] SPI_SEED_STRND_TOUT;
135
+ wire [ 16:0] SPI_SEED_NOISE_NEUR;
136
+ wire [ M-1:0] SPI_NUM_INP_NEUR;
137
+ wire [ M-1:0] SPI_NUM_REC_NEUR;
138
+ wire [ 3:0] SPI_NUM_OUT_NEUR;
139
+ wire [ 11:0] SPI_REGUL_F0;
140
+ wire [ 4:0] SPI_REGUL_K_INP_R;
141
+ wire [ 4:0] SPI_REGUL_K_INP_P;
142
+ wire [ 4:0] SPI_REGUL_K_REC_R;
143
+ wire [ 4:0] SPI_REGUL_K_REC_P;
144
+ wire [ 4:0] SPI_REGUL_K_MUL;
145
+ wire [ 3:0] SPI_NOISE_STR;
146
+ // Programming triggers
147
+ wire PROG_NEUR;
148
+ wire PROG_ONEUR;
149
+ wire PROG_WINP;
150
+ wire PROG_WREC;
151
+ wire PROG_WOUT;
152
+ wire PROG_SEED_INP;
153
+ wire PROG_SEED_REC;
154
+ wire PROG_SEED_OUT;
155
+ wire PROG_SEED_STRND_NEUR;
156
+ wire PROG_SEED_STRND_ONEUR;
157
+ wire PROG_SEED_STRND_TINP;
158
+ wire PROG_SEED_STRND_TREC;
159
+ wire PROG_SEED_STRND_TOUT;
160
+ wire PROG_SEED_NOISE_NEUR;
161
+ wire READ_NEUR;
162
+ wire READ_ONEUR;
163
+ wire READ_WINP;
164
+ wire READ_WREC;
165
+ wire READ_WOUT;
166
+
167
+
168
+ //----------------------------------------------------------------------------------
169
+ // Reset (with double sync barrier)
170
+ //----------------------------------------------------------------------------------
171
+
172
+ always @(posedge CLK) begin
173
+ RST_sync_int <= RST;
174
+ RST_sync <= RST_sync_int;
175
+ end
176
+
177
+
178
+ //----------------------------------------------------------------------------------
179
+ // Clock generator (optional)
180
+ //----------------------------------------------------------------------------------
181
+
182
+
183
+
184
+ `ifdef EXT_CLK_ONLY
185
+ assign CLK_INT = 1'b0;
186
+ assign CLK_INT_div = 1'b0;
187
+ `else
188
+
189
+ // //
190
+ // Dummy clk gen and div instantiations go here //
191
+ // Implementations to be provided separately //
192
+ // (technology-specific cells/macros have been removed) //
193
+ // //
194
+ clock_generator clock_generator_0 (
195
+ .EN(CLK_INT_EN),
196
+ .STAGE_SEL(SPI_RO_STAGE_SEL),
197
+ .OUT(CLK_INT)
198
+ );
199
+ assign CLK_INT_MON = CLK_INT & SPI_GET_CLKINT_OUT;
200
+ clock_divider clock_divider_0 (
201
+ .RST(RST),
202
+ .CLK(CLK_INT_MON),
203
+ .CLK_DIV(CLK_INT_div)
204
+ );
205
+ // //
206
+ // //
207
+
208
+ `endif
209
+
210
+ clk_or clk_or_0 (
211
+ .CLK_EXT(CLK_EXT),
212
+ .CLK_INT(CLK_INT),
213
+ .CLK(CLK)
214
+ );
215
+
216
+ assign MISO = MISO_int | (SPI_GET_CLKINT_OUT & CLK_INT_div) | (SPI_GET_TAR_REQ_OUT & REQ_TAR); // Monitor the divided clock on the MISO pin
217
+
218
+
219
+ //----------------------------------------------------------------------------------
220
+ // SPI + parameter bank + clock int/ext handling
221
+ //----------------------------------------------------------------------------------
222
+
223
+ spi_slave #(
224
+ .N(N),
225
+ .M(M)
226
+ ) spi_slave_0 (
227
+ // Global inputs -------------------------
228
+ .RST_async(RST),
229
+
230
+ // SPI slave interface -------------------
231
+ .SCK(SCK),
232
+ .MISO(MISO_int),
233
+ .MOSI(MOSI),
234
+
235
+ // Global output -------------------------
236
+ .SPI_ADDR(SPI_ADDR),
237
+ .SPI_DATA(SPI_DATA),
238
+ .SPI_EN_CONF(SPI_EN_CONF),
239
+
240
+ // Parameter outputs ---------------------
241
+ // Toplevel
242
+ .SPI_RO_STAGE_SEL(SPI_RO_STAGE_SEL),
243
+ .SPI_GET_CLKINT_OUT(SPI_GET_CLKINT_OUT),
244
+ .SPI_GET_TAR_REQ_OUT(SPI_GET_TAR_REQ_OUT),
245
+ // Control
246
+ .SPI_RST_MODE(SPI_RST_MODE),
247
+ .SPI_DO_EPROP(SPI_DO_EPROP),
248
+ .SPI_LOCAL_TICK(SPI_LOCAL_TICK),
249
+ .SPI_ERROR_HALT(SPI_ERROR_HALT),
250
+ .SPI_FP_LOC_WINP(SPI_FP_LOC_WINP),
251
+ .SPI_FP_LOC_WREC(SPI_FP_LOC_WREC),
252
+ .SPI_FP_LOC_WOUT(SPI_FP_LOC_WOUT),
253
+ .SPI_FP_LOC_TINP(SPI_FP_LOC_TINP),
254
+ .SPI_FP_LOC_TREC(SPI_FP_LOC_TREC),
255
+ .SPI_FP_LOC_TOUT(SPI_FP_LOC_TOUT),
256
+ .SPI_LEARN_SIG_SCALE(SPI_LEARN_SIG_SCALE),
257
+ .SPI_REGUL_MODE(SPI_REGUL_MODE),
258
+ .SPI_REGUL_W(SPI_REGUL_W),
259
+ .SPI_EN_STOCH_ROUND(SPI_EN_STOCH_ROUND),
260
+ .SPI_SRAM_SPEEDMODE(SPI_SRAM_SPEEDMODE),
261
+ .SPI_TIMING_MODE(SPI_TIMING_MODE),
262
+ .SPI_REGRESSION(SPI_REGRESSION),
263
+ .SPI_SINGLE_LABEL(SPI_SINGLE_LABEL),
264
+ .SPI_NO_OUT_ACT(SPI_NO_OUT_ACT),
265
+ .SPI_SEND_PER_TIMESTEP(SPI_SEND_PER_TIMESTEP),
266
+ .SPI_SEND_LABEL_ONLY(SPI_SEND_LABEL_ONLY),
267
+ .SPI_NOISE_EN(SPI_NOISE_EN),
268
+ .SPI_FORCE_TRACES(SPI_FORCE_TRACES),
269
+ // Network
270
+ .SPI_CYCLES_PER_TICK(SPI_CYCLES_PER_TICK),
271
+ .SPI_ALPHA_CONF(SPI_ALPHA_CONF),
272
+ .SPI_KAPPA(SPI_KAPPA),
273
+ .SPI_THR_H_0(SPI_THR_H_0),
274
+ .SPI_THR_H_1(SPI_THR_H_1),
275
+ .SPI_THR_H_2(SPI_THR_H_2),
276
+ .SPI_THR_H_3(SPI_THR_H_3),
277
+ .SPI_H_0(SPI_H_0),
278
+ .SPI_H_1(SPI_H_1),
279
+ .SPI_H_2(SPI_H_2),
280
+ .SPI_H_3(SPI_H_3),
281
+ .SPI_H_4(SPI_H_4),
282
+ .SPI_LR_R_WINP(SPI_LR_R_WINP),
283
+ .SPI_LR_P_WINP(SPI_LR_P_WINP),
284
+ .SPI_LR_R_WREC(SPI_LR_R_WREC),
285
+ .SPI_LR_P_WREC(SPI_LR_P_WREC),
286
+ .SPI_LR_R_WOUT(SPI_LR_R_WOUT),
287
+ .SPI_LR_P_WOUT(SPI_LR_P_WOUT),
288
+ .SPI_SEED_INP(SPI_SEED_INP),
289
+ .SPI_SEED_REC(SPI_SEED_REC),
290
+ .SPI_SEED_OUT(SPI_SEED_OUT),
291
+ .SPI_SEED_STRND_NEUR(SPI_SEED_STRND_NEUR),
292
+ .SPI_SEED_STRND_ONEUR(SPI_SEED_STRND_ONEUR),
293
+ .SPI_SEED_STRND_TINP(SPI_SEED_STRND_TINP),
294
+ .SPI_SEED_STRND_TREC(SPI_SEED_STRND_TREC),
295
+ .SPI_SEED_STRND_TOUT(SPI_SEED_STRND_TOUT),
296
+ .SPI_SEED_NOISE_NEUR(SPI_SEED_NOISE_NEUR),
297
+ .SPI_NUM_INP_NEUR(SPI_NUM_INP_NEUR),
298
+ .SPI_NUM_REC_NEUR(SPI_NUM_REC_NEUR),
299
+ .SPI_NUM_OUT_NEUR(SPI_NUM_OUT_NEUR),
300
+ .SPI_REGUL_F0(SPI_REGUL_F0),
301
+ .SPI_REGUL_K_INP_R(SPI_REGUL_K_INP_R),
302
+ .SPI_REGUL_K_INP_P(SPI_REGUL_K_INP_P),
303
+ .SPI_REGUL_K_REC_R(SPI_REGUL_K_REC_R),
304
+ .SPI_REGUL_K_REC_P(SPI_REGUL_K_REC_P),
305
+ .SPI_REGUL_K_MUL(SPI_REGUL_K_MUL),
306
+ .SPI_NOISE_STR(SPI_NOISE_STR),
307
+ // Programming triggers
308
+ .PROG_NEUR(PROG_NEUR),
309
+ .PROG_ONEUR(PROG_ONEUR),
310
+ .PROG_WINP(PROG_WINP),
311
+ .PROG_WREC(PROG_WREC),
312
+ .PROG_WOUT(PROG_WOUT),
313
+ .PROG_SEED_INP(PROG_SEED_INP),
314
+ .PROG_SEED_REC(PROG_SEED_REC),
315
+ .PROG_SEED_OUT(PROG_SEED_OUT),
316
+ .PROG_SEED_STRND_NEUR(PROG_SEED_STRND_NEUR),
317
+ .PROG_SEED_STRND_ONEUR(PROG_SEED_STRND_ONEUR),
318
+ .PROG_SEED_STRND_TINP(PROG_SEED_STRND_TINP),
319
+ .PROG_SEED_STRND_TREC(PROG_SEED_STRND_TREC),
320
+ .PROG_SEED_STRND_TOUT(PROG_SEED_STRND_TOUT),
321
+ .PROG_SEED_NOISE_NEUR(PROG_SEED_NOISE_NEUR),
322
+ .READ_NEUR(READ_NEUR),
323
+ .READ_ONEUR(READ_ONEUR),
324
+ .READ_WINP(READ_WINP),
325
+ .READ_WREC(READ_WREC),
326
+ .READ_WOUT(READ_WOUT),
327
+
328
+ // Inputs from SRNN ----------------------
329
+ .SRNN_READBACK(SRNN_READBACK)
330
+ );
331
+
332
+
333
+ //----------------------------------------------------------------------------------
334
+ // Spiking recurrent neural network core
335
+ //----------------------------------------------------------------------------------
336
+
337
+ srnn #(
338
+ .N(N),
339
+ .M(M)
340
+ ) srnn_0 (
341
+ // Global inputs ------------------------------------
342
+ .CLK(CLK),
343
+ .RST(RST_sync),
344
+
345
+ // Parameters -----------------------------------------
346
+ // Control
347
+ .SPI_RST_MODE(SPI_RST_MODE),
348
+ .SPI_DO_EPROP(SPI_DO_EPROP),
349
+ .SPI_LOCAL_TICK(SPI_LOCAL_TICK),
350
+ .SPI_ERROR_HALT(SPI_ERROR_HALT),
351
+ .SPI_FP_LOC_WINP(SPI_FP_LOC_WINP),
352
+ .SPI_FP_LOC_WREC(SPI_FP_LOC_WREC),
353
+ .SPI_FP_LOC_WOUT(SPI_FP_LOC_WOUT),
354
+ .SPI_FP_LOC_TINP(SPI_FP_LOC_TINP),
355
+ .SPI_FP_LOC_TREC(SPI_FP_LOC_TREC),
356
+ .SPI_FP_LOC_TOUT(SPI_FP_LOC_TOUT),
357
+ .SPI_LEARN_SIG_SCALE(SPI_LEARN_SIG_SCALE),
358
+ .SPI_REGUL_MODE(SPI_REGUL_MODE),
359
+ .SPI_REGUL_W(SPI_REGUL_W),
360
+ .SPI_EN_STOCH_ROUND(SPI_EN_STOCH_ROUND),
361
+ .SPI_SRAM_SPEEDMODE(SPI_SRAM_SPEEDMODE),
362
+ .SPI_TIMING_MODE(SPI_TIMING_MODE),
363
+ .SPI_REGRESSION(SPI_REGRESSION),
364
+ .SPI_SINGLE_LABEL(SPI_SINGLE_LABEL),
365
+ .SPI_NO_OUT_ACT(SPI_NO_OUT_ACT),
366
+ .SPI_SEND_PER_TIMESTEP(SPI_SEND_PER_TIMESTEP),
367
+ .SPI_SEND_LABEL_ONLY(SPI_SEND_LABEL_ONLY),
368
+ .SPI_NOISE_EN(SPI_NOISE_EN),
369
+ .SPI_FORCE_TRACES(SPI_FORCE_TRACES),
370
+ // Network
371
+ .SPI_CYCLES_PER_TICK(SPI_CYCLES_PER_TICK),
372
+ .SPI_ALPHA_CONF(SPI_ALPHA_CONF),
373
+ .SPI_KAPPA(SPI_KAPPA),
374
+ .SPI_THR_H_0(SPI_THR_H_0),
375
+ .SPI_THR_H_1(SPI_THR_H_1),
376
+ .SPI_THR_H_2(SPI_THR_H_2),
377
+ .SPI_THR_H_3(SPI_THR_H_3),
378
+ .SPI_H_0(SPI_H_0),
379
+ .SPI_H_1(SPI_H_1),
380
+ .SPI_H_2(SPI_H_2),
381
+ .SPI_H_3(SPI_H_3),
382
+ .SPI_H_4(SPI_H_4),
383
+ .SPI_LR_R_WINP(SPI_LR_R_WINP),
384
+ .SPI_LR_P_WINP(SPI_LR_P_WINP),
385
+ .SPI_LR_R_WREC(SPI_LR_R_WREC),
386
+ .SPI_LR_P_WREC(SPI_LR_P_WREC),
387
+ .SPI_LR_R_WOUT(SPI_LR_R_WOUT),
388
+ .SPI_LR_P_WOUT(SPI_LR_P_WOUT),
389
+ .SPI_SEED_INP(SPI_SEED_INP),
390
+ .SPI_SEED_REC(SPI_SEED_REC),
391
+ .SPI_SEED_OUT(SPI_SEED_OUT),
392
+ .SPI_SEED_STRND_NEUR(SPI_SEED_STRND_NEUR),
393
+ .SPI_SEED_STRND_ONEUR(SPI_SEED_STRND_ONEUR),
394
+ .SPI_SEED_STRND_TINP(SPI_SEED_STRND_TINP),
395
+ .SPI_SEED_STRND_TREC(SPI_SEED_STRND_TREC),
396
+ .SPI_SEED_STRND_TOUT(SPI_SEED_STRND_TOUT),
397
+ .SPI_SEED_NOISE_NEUR(SPI_SEED_NOISE_NEUR),
398
+ .SPI_NUM_INP_NEUR(SPI_NUM_INP_NEUR),
399
+ .SPI_NUM_REC_NEUR(SPI_NUM_REC_NEUR),
400
+ .SPI_NUM_OUT_NEUR(SPI_NUM_OUT_NEUR),
401
+ .SPI_REGUL_F0(SPI_REGUL_F0),
402
+ .SPI_REGUL_K_INP_R(SPI_REGUL_K_INP_R),
403
+ .SPI_REGUL_K_INP_P(SPI_REGUL_K_INP_P),
404
+ .SPI_REGUL_K_REC_R(SPI_REGUL_K_REC_R),
405
+ .SPI_REGUL_K_REC_P(SPI_REGUL_K_REC_P),
406
+ .SPI_REGUL_K_MUL(SPI_REGUL_K_MUL),
407
+ .SPI_NOISE_STR(SPI_NOISE_STR),
408
+
409
+ // Inputs from SPI slave ------------------------------
410
+ .SPI_ADDR(SPI_ADDR),
411
+ .SPI_DATA(SPI_DATA),
412
+ .SPI_EN_CONF(SPI_EN_CONF),
413
+ .PROG_NEUR(PROG_NEUR),
414
+ .PROG_ONEUR(PROG_ONEUR),
415
+ .PROG_WINP(PROG_WINP),
416
+ .PROG_WREC(PROG_WREC),
417
+ .PROG_WOUT(PROG_WOUT),
418
+ .PROG_SEED_INP(PROG_SEED_INP),
419
+ .PROG_SEED_REC(PROG_SEED_REC),
420
+ .PROG_SEED_OUT(PROG_SEED_OUT),
421
+ .PROG_SEED_STRND_NEUR(PROG_SEED_STRND_NEUR),
422
+ .PROG_SEED_STRND_ONEUR(PROG_SEED_STRND_ONEUR),
423
+ .PROG_SEED_STRND_TINP(PROG_SEED_STRND_TINP),
424
+ .PROG_SEED_STRND_TREC(PROG_SEED_STRND_TREC),
425
+ .PROG_SEED_STRND_TOUT(PROG_SEED_STRND_TOUT),
426
+ .PROG_SEED_NOISE_NEUR(PROG_SEED_NOISE_NEUR),
427
+ .READ_NEUR(READ_NEUR),
428
+ .READ_ONEUR(READ_ONEUR),
429
+ .READ_WINP(READ_WINP),
430
+ .READ_WREC(READ_WREC),
431
+ .READ_WOUT(READ_WOUT),
432
+
433
+ // Outputs to SPI slave --------------------------------
434
+ .SRNN_READBACK(SRNN_READBACK),
435
+
436
+ // Core inputs -----------------------------
437
+ .AERIN_ADDR(AERIN_ADDR),
438
+ .AERIN_REQ(AERIN_REQ),
439
+ .AERIN_ACK(AERIN_ACK),
440
+ .AERIN_TAR_EN(AERIN_TAR_EN),
441
+ .TARGET_VALID(TARGET_VALID),
442
+ .INFER_ACC(INFER_ACC),
443
+ .SAMPLE(SAMPLE),
444
+ .TIME_TICK(TIME_TICK),
445
+
446
+ // Core outputs ------------------------------
447
+ .SPI_RDY(SPI_RDY),
448
+ .TIMING_ERROR_RDY(TIMING_ERROR_RDY),
449
+
450
+ // Output bus ------------------------------
451
+ .REQ_TAR(REQ_TAR),
452
+ .OUT_REQ(OUT_REQ),
453
+ .OUT_ACK(OUT_ACK),
454
+ .OUT_DATA(OUT_DATA)
455
+ );
456
+
457
+
458
+ endmodule
459
+
460
+
461
+ // Separate clock OR module for easier SDC constraints definition
462
+ module clk_or (
463
+ // Inputs
464
+ input wire CLK_EXT,
465
+ input wire CLK_INT,
466
+ // Outputs
467
+ output wire CLK
468
+ );
469
+
470
+ assign CLK = CLK_EXT | CLK_INT;
471
+
472
+ endmodule
ChFrenkel_ReckOn/src/spi_slave.v ADDED
@@ -0,0 +1,631 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "spi_slave.v" - 32-bit SPI slave bus
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: SPI doc and address space as follows:
25
+ //
26
+ // 32-bit SPI shift register (falling edge)
27
+ // Address organization: {[R/Wb][Code<2:0>][NumWrites<11:0>][StartAddr<15:0>]} - Total 32 bits (supports max 2047 reads at a time!)
28
+ // If code==cfg:
29
+ // Addr<15:0>: config register address
30
+ // If code==neur (each pair of hidden neurons occupy a single 128-bit word in memory):
31
+ // If Addr<9>==0 (SRAM programming):
32
+ // Addr<8:2>: SRAM address
33
+ // Addr<1:0>: word 32-bit chunk address
34
+ // If Addr<9>==1 (reserved registers programming for debug purposes):
35
+ // Addr<7:0>: neuron index
36
+ // If code==neur_out (each output neuron occupies a 16-bit membrane potential, register-file-based storage):
37
+ // Addr<3:0>: output neuron index
38
+ // If code==inp_weights (each weight occupies single byte, SRAM words are 128-bit):
39
+ // Addr<13:2>: SRAM address
40
+ // Addr< 1:0>: word 32-bit chunk address
41
+ // If code==rec_weights (each weight occupies single byte, SRAM words are 128-bit):
42
+ // Addr<13:2>: SRAM address
43
+ // Addr< 1:0>: word 32-bit chunk address
44
+ // If code==out_weights (each weight occupies a single byte, 8-bit register storage):
45
+ // Addr<10:2>: SRAM address
46
+ // Addr< 1:0>: word 32-bit chunk address
47
+ // Data organization: {[Data<31:0>]} - Total 32 bits
48
+ // Data<31:0> contains 32-bit data received from SPI, not all bits of which may be used
49
+ // Codes : 3'b000: cfg (not readable)
50
+ // 3'b001: neur
51
+ // 3'b010: neur_out
52
+ // 3'b011: inp_weights
53
+ // 3'b100: rec_weights
54
+ // 3'b101: out_weights
55
+ //
56
+ //------------------------------------------------------------------------------
57
+
58
+
59
+
60
+ module spi_slave #(
61
+ parameter N = 256,
62
+ parameter M = 8
63
+ )(
64
+
65
+ // Global inputs -------------------------
66
+ input wire RST_async,
67
+
68
+ // SPI slave interface -------------------
69
+ input wire SCK,
70
+ output wire MISO,
71
+ input wire MOSI,
72
+
73
+ // Global output -------------------------
74
+ output reg [ 15:0] SPI_ADDR,
75
+ output reg [ 31:0] SPI_DATA,
76
+ output reg SPI_EN_CONF,
77
+
78
+ // Parameter outputs ---------------------
79
+ // Toplevel
80
+ output reg [ 8:0] SPI_RO_STAGE_SEL,
81
+ output reg SPI_GET_CLKINT_OUT,
82
+ output reg SPI_GET_TAR_REQ_OUT,
83
+ // Control
84
+ output reg SPI_RST_MODE,
85
+ output reg [ 2:0] SPI_DO_EPROP,
86
+ output reg SPI_LOCAL_TICK,
87
+ output reg SPI_ERROR_HALT,
88
+ output reg [ 2:0] SPI_FP_LOC_WINP,
89
+ output reg [ 2:0] SPI_FP_LOC_WREC,
90
+ output reg [ 2:0] SPI_FP_LOC_WOUT,
91
+ output reg [ 2:0] SPI_FP_LOC_TINP,
92
+ output reg [ 2:0] SPI_FP_LOC_TREC,
93
+ output reg [ 2:0] SPI_FP_LOC_TOUT,
94
+ output reg [ 3:0] SPI_LEARN_SIG_SCALE,
95
+ output reg [ 2:0] SPI_REGUL_MODE,
96
+ output reg [ 1:0] SPI_REGUL_W,
97
+ output reg SPI_EN_STOCH_ROUND,
98
+ output reg [ 7:0] SPI_SRAM_SPEEDMODE,
99
+ output reg SPI_TIMING_MODE,
100
+ output reg SPI_REGRESSION,
101
+ output reg SPI_SINGLE_LABEL,
102
+ output reg SPI_NO_OUT_ACT,
103
+ output reg SPI_SEND_PER_TIMESTEP,
104
+ output reg SPI_SEND_LABEL_ONLY,
105
+ output reg SPI_NOISE_EN,
106
+ output reg SPI_FORCE_TRACES,
107
+ // Network
108
+ output reg [ 31:0] SPI_CYCLES_PER_TICK,
109
+ output reg [ 127:0] SPI_ALPHA_CONF,
110
+ output reg [ 7:0] SPI_KAPPA,
111
+ output reg signed [ 15:0] SPI_THR_H_0,
112
+ output reg signed [ 15:0] SPI_THR_H_1,
113
+ output reg signed [ 15:0] SPI_THR_H_2,
114
+ output reg signed [ 15:0] SPI_THR_H_3,
115
+ output reg signed [ 4:0] SPI_H_0,
116
+ output reg signed [ 4:0] SPI_H_1,
117
+ output reg signed [ 4:0] SPI_H_2,
118
+ output reg signed [ 4:0] SPI_H_3,
119
+ output reg signed [ 4:0] SPI_H_4,
120
+ output reg [ 4:0] SPI_LR_R_WINP,
121
+ output reg [ 4:0] SPI_LR_P_WINP,
122
+ output reg [ 4:0] SPI_LR_R_WREC,
123
+ output reg [ 4:0] SPI_LR_P_WREC,
124
+ output reg [ 4:0] SPI_LR_R_WOUT,
125
+ output reg [ 4:0] SPI_LR_P_WOUT,
126
+ output reg [ 24:0] SPI_SEED_INP,
127
+ output reg [ 24:0] SPI_SEED_REC,
128
+ output reg [ 21:0] SPI_SEED_OUT,
129
+ output reg [ 29:0] SPI_SEED_STRND_NEUR,
130
+ output reg [ 14:0] SPI_SEED_STRND_ONEUR,
131
+ output reg [ 29:0] SPI_SEED_STRND_TINP,
132
+ output reg [ 29:0] SPI_SEED_STRND_TREC,
133
+ output reg [ 29:0] SPI_SEED_STRND_TOUT,
134
+ output reg [ 16:0] SPI_SEED_NOISE_NEUR,
135
+ output reg [ M-1:0] SPI_NUM_INP_NEUR,
136
+ output reg [ M-1:0] SPI_NUM_REC_NEUR,
137
+ output reg [ 3:0] SPI_NUM_OUT_NEUR,
138
+ output reg [ 11:0] SPI_REGUL_F0,
139
+ output reg [ 4:0] SPI_REGUL_K_INP_R,
140
+ output reg [ 4:0] SPI_REGUL_K_INP_P,
141
+ output reg [ 4:0] SPI_REGUL_K_REC_R,
142
+ output reg [ 4:0] SPI_REGUL_K_REC_P,
143
+ output reg [ 4:0] SPI_REGUL_K_MUL,
144
+ output reg [ 3:0] SPI_NOISE_STR,
145
+ // Programming triggers
146
+ output reg PROG_NEUR,
147
+ output reg PROG_ONEUR,
148
+ output reg PROG_WINP,
149
+ output reg PROG_WREC,
150
+ output reg PROG_WOUT,
151
+ output reg PROG_SEED_INP,
152
+ output reg PROG_SEED_REC,
153
+ output reg PROG_SEED_OUT,
154
+ output reg PROG_SEED_STRND_NEUR,
155
+ output reg PROG_SEED_STRND_ONEUR,
156
+ output reg PROG_SEED_STRND_TINP,
157
+ output reg PROG_SEED_STRND_TREC,
158
+ output reg PROG_SEED_STRND_TOUT,
159
+ output reg PROG_SEED_NOISE_NEUR,
160
+ output reg READ_NEUR,
161
+ output reg READ_ONEUR,
162
+ output reg READ_WINP,
163
+ output reg READ_WREC,
164
+ output reg READ_WOUT,
165
+
166
+ // Inputs from SRNN ------------------------
167
+ input wire [ 31:0] SRNN_READBACK
168
+ );
169
+
170
+ //----------------------------------------------------------------------------------
171
+ // REG & WIRES :
172
+ //----------------------------------------------------------------------------------
173
+
174
+ reg [16:0] spi_cnt;
175
+
176
+ reg [31:0] spi_shift_reg_out, spi_shift_reg_in;
177
+ reg [31:0] spi_addr;
178
+ wire [11:0] num_write;
179
+
180
+ genvar i;
181
+
182
+
183
+ //----------------------------------------------------------------------------------
184
+ // SPI circuitry
185
+ //----------------------------------------------------------------------------------
186
+
187
+ // SPI counter
188
+ always @(negedge SCK, posedge RST_async)
189
+ if (RST_async) spi_cnt <= 17'd0;
190
+ else if (&spi_cnt[4:0] && (spi_cnt[16:5] >= num_write)) spi_cnt <= 17'd0;
191
+ else spi_cnt <= spi_cnt + 17'd1;
192
+ assign num_write = (spi_cnt == 17'd31) ? spi_shift_reg_in[27:16] : spi_addr[27:16];
193
+
194
+ always @(negedge SCK, posedge RST_async)
195
+ if (RST_async) spi_addr <= 32'd0;
196
+ else if (spi_cnt == 17'd31) spi_addr <= spi_shift_reg_in[31:0];
197
+
198
+ always @(posedge SCK)
199
+ spi_shift_reg_in <= {spi_shift_reg_in[30:0], MOSI};
200
+
201
+ always @(negedge SCK, posedge RST_async)
202
+ if (RST_async) begin
203
+ spi_shift_reg_out <= 32'b0;
204
+ PROG_NEUR <= 1'b0;
205
+ PROG_ONEUR <= 1'b0;
206
+ PROG_WINP <= 1'b0;
207
+ PROG_WREC <= 1'b0;
208
+ PROG_WOUT <= 1'b0;
209
+ PROG_SEED_INP <= 1'b0;
210
+ PROG_SEED_REC <= 1'b0;
211
+ PROG_SEED_OUT <= 1'b0;
212
+ PROG_SEED_STRND_NEUR <= 1'b0;
213
+ PROG_SEED_STRND_ONEUR <= 1'b0;
214
+ PROG_SEED_STRND_TINP <= 1'b0;
215
+ PROG_SEED_STRND_TREC <= 1'b0;
216
+ PROG_SEED_STRND_TOUT <= 1'b0;
217
+ PROG_SEED_NOISE_NEUR <= 1'b0;
218
+ READ_NEUR <= 1'b0;
219
+ READ_ONEUR <= 1'b0;
220
+ READ_WINP <= 1'b0;
221
+ READ_WREC <= 1'b0;
222
+ READ_WOUT <= 1'b0;
223
+ end else if (!spi_addr[31] && &spi_cnt[4:0] && |spi_cnt[16:5]) begin
224
+ spi_shift_reg_out <= 32'b0;
225
+ PROG_NEUR <= (spi_addr[30:28] == 3'b001);
226
+ PROG_ONEUR <= (spi_addr[30:28] == 3'b010);
227
+ PROG_WINP <= (spi_addr[30:28] == 3'b011);
228
+ PROG_WREC <= (spi_addr[30:28] == 3'b100);
229
+ PROG_WOUT <= (spi_addr[30:28] == 3'b101);
230
+ PROG_SEED_INP <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd85));
231
+ PROG_SEED_REC <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd86));
232
+ PROG_SEED_OUT <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd87));
233
+ PROG_SEED_STRND_NEUR <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd88));
234
+ PROG_SEED_STRND_ONEUR <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd89));
235
+ PROG_SEED_STRND_TINP <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd90));
236
+ PROG_SEED_STRND_TREC <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd91));
237
+ PROG_SEED_STRND_TOUT <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd92));
238
+ PROG_SEED_NOISE_NEUR <= ((spi_addr[30:28] == 3'b000) && (spi_addr[15:0] == 16'd93));
239
+ SPI_ADDR <= spi_addr[15:0] + {4'b0,spi_cnt[16:5]} - 16'd1;
240
+ SPI_DATA <= spi_shift_reg_in;
241
+ end else if ( spi_shift_reg_in[31] && (spi_cnt == 17'd31)) begin
242
+ spi_shift_reg_out <= {spi_shift_reg_out[30:0], 1'b0};
243
+ READ_NEUR <= (spi_shift_reg_in[30:28] == 3'b001);
244
+ READ_ONEUR <= (spi_shift_reg_in[30:28] == 3'b010);
245
+ READ_WINP <= (spi_shift_reg_in[30:28] == 3'b011);
246
+ READ_WREC <= (spi_shift_reg_in[30:28] == 3'b100);
247
+ READ_WOUT <= (spi_shift_reg_in[30:28] == 3'b101);
248
+ SPI_ADDR <= spi_shift_reg_in[15:0];
249
+ end else if ( spi_addr[31] && &spi_cnt[4:0] && |spi_cnt[16:5] && (spi_cnt[16:5] < num_write)) begin
250
+ spi_shift_reg_out <= {spi_shift_reg_out[30:0], 1'b0};
251
+ READ_NEUR <= (spi_addr[30:28] == 3'b001);
252
+ READ_ONEUR <= (spi_addr[30:28] == 3'b010);
253
+ READ_WINP <= (spi_addr[30:28] == 3'b011);
254
+ READ_WREC <= (spi_addr[30:28] == 3'b100);
255
+ READ_WOUT <= (spi_addr[30:28] == 3'b101);
256
+ SPI_ADDR <= spi_addr[15:0] + {4'b0,spi_cnt[16:5]};
257
+ end else if ( spi_addr[31] && ~|spi_cnt[4:0] && |spi_cnt[16:5]) begin
258
+ spi_shift_reg_out <= SRNN_READBACK << 1;
259
+ READ_NEUR <= 1'b0;
260
+ READ_ONEUR <= 1'b0;
261
+ READ_WINP <= 1'b0;
262
+ READ_WREC <= 1'b0;
263
+ READ_WOUT <= 1'b0;
264
+ PROG_NEUR <= 1'b0;
265
+ PROG_ONEUR <= 1'b0;
266
+ PROG_WINP <= 1'b0;
267
+ PROG_WREC <= 1'b0;
268
+ PROG_WOUT <= 1'b0;
269
+ PROG_SEED_INP <= 1'b0;
270
+ PROG_SEED_REC <= 1'b0;
271
+ PROG_SEED_OUT <= 1'b0;
272
+ PROG_SEED_STRND_NEUR <= 1'b0;
273
+ PROG_SEED_STRND_ONEUR <= 1'b0;
274
+ PROG_SEED_STRND_TINP <= 1'b0;
275
+ PROG_SEED_STRND_TREC <= 1'b0;
276
+ PROG_SEED_STRND_TOUT <= 1'b0;
277
+ PROG_SEED_NOISE_NEUR <= 1'b0;
278
+ end else if (spi_cnt[4:0] == 5'd0) begin
279
+ PROG_NEUR <= 1'b0;
280
+ PROG_ONEUR <= 1'b0;
281
+ PROG_WINP <= 1'b0;
282
+ PROG_WREC <= 1'b0;
283
+ PROG_WOUT <= 1'b0;
284
+ PROG_SEED_INP <= 1'b0;
285
+ PROG_SEED_REC <= 1'b0;
286
+ PROG_SEED_OUT <= 1'b0;
287
+ PROG_SEED_STRND_NEUR <= 1'b0;
288
+ PROG_SEED_STRND_ONEUR <= 1'b0;
289
+ PROG_SEED_STRND_TINP <= 1'b0;
290
+ PROG_SEED_STRND_TREC <= 1'b0;
291
+ PROG_SEED_STRND_TOUT <= 1'b0;
292
+ PROG_SEED_NOISE_NEUR <= 1'b0;
293
+ end else begin
294
+ spi_shift_reg_out <= {spi_shift_reg_out[30:0], 1'b0};
295
+ end
296
+
297
+ // SPI MISO
298
+ assign MISO = (spi_addr[31] && ~|spi_cnt[4:0] && |spi_cnt[16:5]) ? SRNN_READBACK[31] : spi_shift_reg_out[31];
299
+
300
+
301
+ //----------------------------------------------------------------------------------
302
+ // Output config. registers
303
+ //----------------------------------------------------------------------------------
304
+
305
+
306
+ // Toplevel
307
+
308
+ //SPI_EN_CONF - 1 bit - address 0
309
+ always @(posedge SCK, posedge RST_async)
310
+ if (RST_async) SPI_EN_CONF <= 1'b1;
311
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd0 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_EN_CONF <= MOSI;
312
+
313
+ //SPI_RO_STAGE_SEL - 9 bits - address 1
314
+ always @(posedge SCK, posedge RST_async)
315
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd1 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_RO_STAGE_SEL <= {spi_shift_reg_in[7:0], MOSI};
316
+
317
+ //SPI_GET_CLKINT_OUT - 1 bit - address 2
318
+ always @(posedge SCK, posedge RST_async)
319
+ if (RST_async) SPI_GET_CLKINT_OUT <= 1'b0;
320
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd2 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_GET_CLKINT_OUT <= MOSI;
321
+
322
+ //SPI_GET_TAR_REQ_OUT - 1 bit - address 3
323
+ always @(posedge SCK, posedge RST_async)
324
+ if (RST_async) SPI_GET_TAR_REQ_OUT <= 1'b1;
325
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd3 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_GET_TAR_REQ_OUT <= MOSI;
326
+
327
+ /* *
328
+ * Some address room for other params if necessary *
329
+ * */
330
+
331
+
332
+ // Control
333
+
334
+ //SPI_RST_MODE - 1 bit - address 8
335
+ always @(posedge SCK, posedge RST_async)
336
+ if (RST_async) SPI_RST_MODE <= 1'b0;
337
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd8 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_RST_MODE <= MOSI;
338
+
339
+ //SPI_DO_EPROP - 3 bits - address 9
340
+ always @(posedge SCK, posedge RST_async)
341
+ if (RST_async) SPI_DO_EPROP <= 3'b111;
342
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd9 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_DO_EPROP <= {spi_shift_reg_in[1:0], MOSI};
343
+
344
+ //SPI_LOCAL_TICK - 1 bit - address 10
345
+ always @(posedge SCK, posedge RST_async)
346
+ if (RST_async) SPI_LOCAL_TICK <= 1'b0;
347
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd10) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LOCAL_TICK <= MOSI;
348
+
349
+ //SPI_ERROR_HALT - 1 bits - address 11
350
+ always @(posedge SCK, posedge RST_async)
351
+ if (RST_async) SPI_ERROR_HALT <= 1'b1;
352
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd11) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_ERROR_HALT <= MOSI;
353
+
354
+ //SPI_FP_LOC_WINP - 3 bits - address 12
355
+ always @(posedge SCK, posedge RST_async)
356
+ if (RST_async) SPI_FP_LOC_WINP <= 3'b000;
357
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd12) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FP_LOC_WINP <= {spi_shift_reg_in[1:0], MOSI};
358
+
359
+ //SPI_FP_LOC_WREC - 3 bits - address 13
360
+ always @(posedge SCK, posedge RST_async)
361
+ if (RST_async) SPI_FP_LOC_WREC <= 3'b000;
362
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd13) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FP_LOC_WREC <= {spi_shift_reg_in[1:0], MOSI};
363
+
364
+ //SPI_FP_LOC_WOUT - 3 bits - address 14
365
+ always @(posedge SCK, posedge RST_async)
366
+ if (RST_async) SPI_FP_LOC_WOUT <= 3'b000;
367
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd14) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FP_LOC_WOUT <= {spi_shift_reg_in[1:0], MOSI};
368
+
369
+ //SPI_FP_LOC_TINP - 3 bits - address 15
370
+ always @(posedge SCK, posedge RST_async)
371
+ if (RST_async) SPI_FP_LOC_TINP <= 3'b000;
372
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd15) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FP_LOC_TINP <= {spi_shift_reg_in[1:0], MOSI};
373
+
374
+ //SPI_FP_LOC_TREC - 3 bits - address 16
375
+ always @(posedge SCK, posedge RST_async)
376
+ if (RST_async) SPI_FP_LOC_TREC <= 3'b000;
377
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd16) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FP_LOC_TREC <= {spi_shift_reg_in[1:0], MOSI};
378
+
379
+ //SPI_FP_LOC_TOUT - 3 bits - address 17
380
+ always @(posedge SCK, posedge RST_async)
381
+ if (RST_async) SPI_FP_LOC_TOUT <= 3'b000;
382
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd17) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FP_LOC_TOUT <= {spi_shift_reg_in[1:0], MOSI};
383
+
384
+ //SPI_LEARN_SIG_SCALE - 4 bits - address 18
385
+ always @(posedge SCK, posedge RST_async)
386
+ if (RST_async) SPI_LEARN_SIG_SCALE <= 4'b0000;
387
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd18) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LEARN_SIG_SCALE <= {spi_shift_reg_in[2:0], MOSI};
388
+
389
+ //SPI_REGUL_MODE - 3 bits - address 19
390
+ always @(posedge SCK, posedge RST_async)
391
+ if (RST_async) SPI_REGUL_MODE <= 3'b000;
392
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd19) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_MODE <= {spi_shift_reg_in[1:0], MOSI};
393
+
394
+ //SPI_REGUL_W - 2 bits - address 20
395
+ always @(posedge SCK, posedge RST_async)
396
+ if (RST_async) SPI_REGUL_W <= 2'b00;
397
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd20) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_W <= {spi_shift_reg_in[0], MOSI};
398
+
399
+ //SPI_EN_STOCH_ROUND - 1 bit - address 21
400
+ always @(posedge SCK, posedge RST_async)
401
+ if (RST_async) SPI_EN_STOCH_ROUND <= 1'b0;
402
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd21) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_EN_STOCH_ROUND <= MOSI;
403
+
404
+ //SPI_SRAM_SPEEDMODE - 8 bits - address 22
405
+ always @(posedge SCK, posedge RST_async)
406
+ if (RST_async) SPI_SRAM_SPEEDMODE <= 8'h00;
407
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd22) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SRAM_SPEEDMODE <= {spi_shift_reg_in[6:0], MOSI};
408
+
409
+ //SPI_TIMING_MODE - 1 bit - address 23
410
+ always @(posedge SCK, posedge RST_async)
411
+ if (RST_async) SPI_TIMING_MODE <= 1'b0;
412
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd23) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_TIMING_MODE <= MOSI;
413
+
414
+ //Config register at address 24 removed (unpublished block)
415
+
416
+ //SPI_REGRESSION - 1 bit - address 25
417
+ always @(posedge SCK, posedge RST_async)
418
+ if (RST_async) SPI_REGRESSION <= 1'b0;
419
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd25) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGRESSION <= MOSI;
420
+
421
+ //SPI_SINGLE_LABEL - 1 bit - address 26
422
+ always @(posedge SCK, posedge RST_async)
423
+ if (RST_async) SPI_SINGLE_LABEL <= 1'b1;
424
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd26) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SINGLE_LABEL <= MOSI;
425
+
426
+ //SPI_NO_OUT_ACT - 1 bit - address 27
427
+ always @(posedge SCK, posedge RST_async)
428
+ if (RST_async) SPI_NO_OUT_ACT <= 1'b0;
429
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd27) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_NO_OUT_ACT <= MOSI;
430
+
431
+ //Config register at address 28 removed (unpublished block)
432
+
433
+ //Config register at address 29 removed (unpublished block)
434
+
435
+ //SPI_SEND_PER_TIMESTEP - 1 bit - address 30
436
+ always @(posedge SCK, posedge RST_async)
437
+ if (RST_async) SPI_SEND_PER_TIMESTEP <= 1'b0;
438
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd30) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEND_PER_TIMESTEP <= MOSI;
439
+
440
+ //SPI_SEND_LABEL_ONLY - 1 bit - address 31
441
+ always @(posedge SCK, posedge RST_async)
442
+ if (RST_async) SPI_SEND_LABEL_ONLY <= 1'b1;
443
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd31) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEND_LABEL_ONLY <= MOSI;
444
+
445
+ //SPI_NOISE_EN - 1 bit - address 32
446
+ always @(posedge SCK, posedge RST_async)
447
+ if (RST_async) SPI_NOISE_EN <= 1'b0;
448
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd32) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_NOISE_EN <= MOSI;
449
+
450
+ //SPI_FORCE_TRACES - 1 bit - address 33
451
+ always @(posedge SCK, posedge RST_async)
452
+ if (RST_async) SPI_FORCE_TRACES <= 1'b0;
453
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd33) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_FORCE_TRACES <= MOSI;
454
+
455
+ //Config register at address 34 removed (unpublished block)
456
+
457
+
458
+ /* *
459
+ * Some address room for other params if necessary *
460
+ * */
461
+
462
+
463
+ // Network
464
+
465
+ //SPI_CYCLES_PER_TICK - 32 bits - address 64
466
+ always @(posedge SCK)
467
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd64 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_CYCLES_PER_TICK <= {spi_shift_reg_in[30:0], MOSI};
468
+
469
+ //SPI_ALPHA_CONF - 128 bits - addresses 65-68
470
+ generate
471
+ for (i=0; i<4; i=i+1) begin
472
+ always @(posedge SCK, posedge RST_async)
473
+ if (RST_async) SPI_ALPHA_CONF[32*i+31:32*i] <= 32'h00000000;
474
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == (16'd65+i)) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_ALPHA_CONF[32*i+31:32*i] <= {spi_shift_reg_in[30:0], MOSI};
475
+ end
476
+ endgenerate
477
+
478
+ //SPI_KAPPA - 8 bits - address 69
479
+ always @(posedge SCK, posedge RST_async)
480
+ if (RST_async) SPI_KAPPA <= 8'b01111010;
481
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd69 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_KAPPA <= {spi_shift_reg_in[6:0], MOSI};
482
+
483
+ //SPI_THR_H_0 - 16 bits - address 70
484
+ always @(posedge SCK)
485
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd70 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_THR_H_0 <= {spi_shift_reg_in[14:0], MOSI};
486
+
487
+ //SPI_THR_H_1 - 16 bits - address 71
488
+ always @(posedge SCK)
489
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd71 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_THR_H_1 <= {spi_shift_reg_in[14:0], MOSI};
490
+
491
+ //SPI_THR_H_2 - 16 bits - address 72
492
+ always @(posedge SCK)
493
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd72 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_THR_H_2 <= {spi_shift_reg_in[14:0], MOSI};
494
+
495
+ //SPI_THR_H_3 - 16 bits - address 73
496
+ always @(posedge SCK)
497
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd73 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_THR_H_3 <= {spi_shift_reg_in[14:0], MOSI};
498
+
499
+ //SPI_H_0 - 5 bits - address 74
500
+ always @(posedge SCK)
501
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd74 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_H_0 <= {spi_shift_reg_in[3:0], MOSI};
502
+
503
+ //SPI_H_1 - 5 bits - address 75
504
+ always @(posedge SCK)
505
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd75 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_H_1 <= {spi_shift_reg_in[3:0], MOSI};
506
+
507
+ //SPI_H_2 - 5 bits - address 76
508
+ always @(posedge SCK)
509
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd76 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_H_2 <= {spi_shift_reg_in[3:0], MOSI};
510
+
511
+ //SPI_H_3 - 5 bits - address 77
512
+ always @(posedge SCK)
513
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd77 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_H_3 <= {spi_shift_reg_in[3:0], MOSI};
514
+
515
+ //SPI_H_4 - 5 bits - address 78
516
+ always @(posedge SCK)
517
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd78 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_H_4 <= {spi_shift_reg_in[3:0], MOSI};
518
+
519
+ //SPI_LR_R_WINP - 5 bits - address 79
520
+ always @(posedge SCK)
521
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd79 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LR_R_WINP <= {spi_shift_reg_in[3:0], MOSI};
522
+
523
+ //SPI_LR_P_WINP - 5 bits - address 80
524
+ always @(posedge SCK)
525
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd80 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LR_P_WINP <= {spi_shift_reg_in[3:0], MOSI};
526
+
527
+ //SPI_LR_R_WREC - 5 bits - address 81
528
+ always @(posedge SCK)
529
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd81 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LR_R_WREC <= {spi_shift_reg_in[3:0], MOSI};
530
+
531
+ //SPI_LR_P_WREC - 5 bits - address 82
532
+ always @(posedge SCK)
533
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd82 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LR_P_WREC <= {spi_shift_reg_in[3:0], MOSI};
534
+
535
+ //SPI_LR_R_WOUT - 5 bits - address 83
536
+ always @(posedge SCK)
537
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd83 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LR_R_WOUT <= {spi_shift_reg_in[3:0], MOSI};
538
+
539
+ //SPI_LR_P_WOUT - 5 bits - address 84
540
+ always @(posedge SCK)
541
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd84 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_LR_P_WOUT <= {spi_shift_reg_in[3:0], MOSI};
542
+
543
+ //SPI_SEED_INP - 25 bits - address 85
544
+ always @(posedge SCK)
545
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd85 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_INP <= {spi_shift_reg_in[23:0], MOSI};
546
+
547
+ //SPI_SEED_REC - 25 bits - address 86
548
+ always @(posedge SCK)
549
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd86 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_REC <= {spi_shift_reg_in[23:0], MOSI};
550
+
551
+ //SPI_SEED_OUT - 22 bits - address 87
552
+ always @(posedge SCK)
553
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd87 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_OUT <= {spi_shift_reg_in[20:0], MOSI};
554
+
555
+ //SPI_SEED_STRND_NEUR - 30 bits - address 88
556
+ always @(posedge SCK)
557
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd88 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_STRND_NEUR <= {spi_shift_reg_in[28:0], MOSI};
558
+
559
+ //SPI_SEED_STRND_ONEUR - 15 bits - address 89
560
+ always @(posedge SCK)
561
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd89 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_STRND_ONEUR <= {spi_shift_reg_in[13:0], MOSI};
562
+
563
+ //SPI_SEED_STRND_TINP - 30 bits - address 90
564
+ always @(posedge SCK)
565
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd90 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_STRND_TINP <= {spi_shift_reg_in[28:0], MOSI};
566
+
567
+ //SPI_SEED_STRND_TREC - 30 bits - address 91
568
+ always @(posedge SCK)
569
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd91 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_STRND_TREC <= {spi_shift_reg_in[28:0], MOSI};
570
+
571
+ //SPI_SEED_STRND_TOUT - 30 bits - address 92
572
+ always @(posedge SCK)
573
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd92 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_STRND_TOUT <= {spi_shift_reg_in[28:0], MOSI};
574
+
575
+ //SPI_SEED_NOISE_NEUR - 17 bits - address 93
576
+ always @(posedge SCK)
577
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd93 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_SEED_NOISE_NEUR <= {spi_shift_reg_in[15:0], MOSI};
578
+
579
+ //SPI_NUM_INP_NEUR - M bits - address 94
580
+ always @(posedge SCK, posedge RST_async)
581
+ if (RST_async) SPI_NUM_INP_NEUR <= {M{1'b1}};
582
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd94 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_NUM_INP_NEUR <= {spi_shift_reg_in[M-2:0], MOSI};
583
+
584
+ //SPI_NUM_REC_NEUR - M bits - address 95
585
+ always @(posedge SCK, posedge RST_async)
586
+ if (RST_async) SPI_NUM_REC_NEUR <= {M{1'b1}};
587
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd95 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_NUM_REC_NEUR <= {spi_shift_reg_in[M-2:0], MOSI};
588
+
589
+ //SPI_NUM_OUT_NEUR - 4 bits - address 96
590
+ always @(posedge SCK, posedge RST_async)
591
+ if (RST_async) SPI_NUM_OUT_NEUR <= 4'hF;
592
+ else if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd96 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_NUM_OUT_NEUR <= {spi_shift_reg_in[2:0], MOSI};
593
+
594
+ //Config register at address 97 removed (unpublished block)
595
+
596
+ //SPI_REGUL_F0 - 12 bits - address 98
597
+ always @(posedge SCK)
598
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd98 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_F0 <= {spi_shift_reg_in[10:0], MOSI};
599
+
600
+ //SPI_REGUL_K_INP_R - 5 bits - address 99
601
+ always @(posedge SCK)
602
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd99 ) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_K_INP_R <= {spi_shift_reg_in[3:0], MOSI};
603
+
604
+ //SPI_REGUL_K_INP_P - 5 bits - address 100
605
+ always @(posedge SCK)
606
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd100) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_K_INP_P <= {spi_shift_reg_in[3:0], MOSI};
607
+
608
+ //SPI_REGUL_K_REC_R - 5 bits - address 101
609
+ always @(posedge SCK)
610
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd101) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_K_REC_R <= {spi_shift_reg_in[3:0], MOSI};
611
+
612
+ //SPI_REGUL_K_REC_P - 5 bits - address 102
613
+ always @(posedge SCK)
614
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd102) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_K_REC_P <= {spi_shift_reg_in[3:0], MOSI};
615
+
616
+ //SPI_REGUL_K_MUL - 5 bits - address 103
617
+ always @(posedge SCK)
618
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd103) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_REGUL_K_MUL <= {spi_shift_reg_in[3:0], MOSI};
619
+
620
+ //SPI_NOISE_STR - 4 bits - address 104
621
+ always @(posedge SCK)
622
+ if (~|spi_addr[31:28] && (spi_addr[15:0] == 16'd104) && &spi_cnt[4:0] && |spi_cnt[16:5]) SPI_NOISE_STR <= {spi_shift_reg_in[2:0], MOSI};
623
+
624
+
625
+ /* *
626
+ * Some address room for other params if necessary *
627
+ * */
628
+
629
+
630
+
631
+ endmodule
ChFrenkel_ReckOn/src/srnn.v ADDED
@@ -0,0 +1,1605 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "srnn.v" - Spiking recurrent neural network core, including learning based on modified e-prop
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: -
25
+ //
26
+ //------------------------------------------------------------------------------
27
+
28
+
29
+
30
+ `define SRAM_BEHAV 1
31
+
32
+ module srnn #(
33
+ parameter N = 256,
34
+ parameter M = 8
35
+ )(
36
+ // Global inputs -------------------------------------
37
+ input wire CLK,
38
+ input wire RST,
39
+
40
+ // Parameters ------------------------------------------
41
+ // Control
42
+ input wire SPI_RST_MODE,
43
+ input wire [ 2:0] SPI_DO_EPROP,
44
+ input wire SPI_LOCAL_TICK,
45
+ input wire SPI_ERROR_HALT,
46
+ input wire [ 2:0] SPI_FP_LOC_WINP,
47
+ input wire [ 2:0] SPI_FP_LOC_WREC,
48
+ input wire [ 2:0] SPI_FP_LOC_WOUT,
49
+ input wire [ 2:0] SPI_FP_LOC_TINP,
50
+ input wire [ 2:0] SPI_FP_LOC_TREC,
51
+ input wire [ 2:0] SPI_FP_LOC_TOUT,
52
+ input wire [ 3:0] SPI_LEARN_SIG_SCALE,
53
+ input wire [ 2:0] SPI_REGUL_MODE,
54
+ input wire [ 1:0] SPI_REGUL_W,
55
+ input wire SPI_EN_STOCH_ROUND,
56
+ input wire [ 7:0] SPI_SRAM_SPEEDMODE,
57
+ input wire SPI_TIMING_MODE,
58
+ input wire SPI_REGRESSION,
59
+ input wire SPI_SINGLE_LABEL,
60
+ input wire SPI_NO_OUT_ACT,
61
+ input wire SPI_SEND_PER_TIMESTEP,
62
+ input wire SPI_SEND_LABEL_ONLY,
63
+ input wire SPI_NOISE_EN,
64
+ input wire SPI_FORCE_TRACES,
65
+ // Network
66
+ input wire [ 31:0] SPI_CYCLES_PER_TICK,
67
+ input wire [ 127:0] SPI_ALPHA_CONF,
68
+ input wire [ 7:0] SPI_KAPPA,
69
+ input wire signed [ 15:0] SPI_THR_H_0,
70
+ input wire signed [ 15:0] SPI_THR_H_1,
71
+ input wire signed [ 15:0] SPI_THR_H_2,
72
+ input wire signed [ 15:0] SPI_THR_H_3,
73
+ input wire signed [ 4:0] SPI_H_0,
74
+ input wire signed [ 4:0] SPI_H_1,
75
+ input wire signed [ 4:0] SPI_H_2,
76
+ input wire signed [ 4:0] SPI_H_3,
77
+ input wire signed [ 4:0] SPI_H_4,
78
+ input wire [ 4:0] SPI_LR_R_WINP,
79
+ input wire [ 4:0] SPI_LR_P_WINP,
80
+ input wire [ 4:0] SPI_LR_R_WREC,
81
+ input wire [ 4:0] SPI_LR_P_WREC,
82
+ input wire [ 4:0] SPI_LR_R_WOUT,
83
+ input wire [ 4:0] SPI_LR_P_WOUT,
84
+ input wire [ 24:0] SPI_SEED_INP,
85
+ input wire [ 24:0] SPI_SEED_REC,
86
+ input wire [ 21:0] SPI_SEED_OUT,
87
+ input wire [ 29:0] SPI_SEED_STRND_NEUR,
88
+ input wire [ 14:0] SPI_SEED_STRND_ONEUR,
89
+ input wire [ 29:0] SPI_SEED_STRND_TINP,
90
+ input wire [ 29:0] SPI_SEED_STRND_TREC,
91
+ input wire [ 29:0] SPI_SEED_STRND_TOUT,
92
+ input wire [ 16:0] SPI_SEED_NOISE_NEUR,
93
+ input wire [ M-1:0] SPI_NUM_INP_NEUR,
94
+ input wire [ M-1:0] SPI_NUM_REC_NEUR,
95
+ input wire [ 3:0] SPI_NUM_OUT_NEUR,
96
+ input wire [ 11:0] SPI_REGUL_F0,
97
+ input wire [ 4:0] SPI_REGUL_K_INP_R,
98
+ input wire [ 4:0] SPI_REGUL_K_INP_P,
99
+ input wire [ 4:0] SPI_REGUL_K_REC_R,
100
+ input wire [ 4:0] SPI_REGUL_K_REC_P,
101
+ input wire [ 4:0] SPI_REGUL_K_MUL,
102
+ input wire [ 3:0] SPI_NOISE_STR,
103
+
104
+ // Inputs from SPI slave -------------------------------
105
+ input wire [ 15:0] SPI_ADDR,
106
+ input wire [ 31:0] SPI_DATA,
107
+ input wire SPI_EN_CONF, //already synchronized
108
+ input wire PROG_NEUR,
109
+ input wire PROG_ONEUR,
110
+ input wire PROG_WINP,
111
+ input wire PROG_WREC,
112
+ input wire PROG_WOUT,
113
+ input wire PROG_SEED_INP,
114
+ input wire PROG_SEED_REC,
115
+ input wire PROG_SEED_OUT,
116
+ input wire PROG_SEED_STRND_NEUR,
117
+ input wire PROG_SEED_STRND_ONEUR,
118
+ input wire PROG_SEED_STRND_TINP,
119
+ input wire PROG_SEED_STRND_TREC,
120
+ input wire PROG_SEED_STRND_TOUT,
121
+ input wire PROG_SEED_NOISE_NEUR,
122
+ input wire READ_NEUR,
123
+ input wire READ_ONEUR,
124
+ input wire READ_WINP,
125
+ input wire READ_WREC,
126
+ input wire READ_WOUT,
127
+
128
+ // Outputs to SPI slave --------------------------------
129
+ output reg [ 31:0] SRNN_READBACK,
130
+
131
+ // Core inputs -----------------------------------------
132
+ input wire [ M-1:0] AERIN_ADDR,
133
+ input wire AERIN_REQ,
134
+ output reg AERIN_ACK,
135
+ input wire AERIN_TAR_EN,
136
+ input wire TARGET_VALID,
137
+ input wire INFER_ACC,
138
+ input wire SAMPLE,
139
+ input wire TIME_TICK,
140
+
141
+ // Core outputs ----------------------------------------
142
+ output wire SPI_RDY,
143
+ output wire TIMING_ERROR_RDY,
144
+
145
+ // Core inouts -----------------------------------------
146
+ output wire REQ_TAR,
147
+ output reg OUT_REQ,
148
+ input wire OUT_ACK,
149
+ output reg [ 7:0] OUT_DATA
150
+ );
151
+
152
+ //----------------------------------------------------------------------------------
153
+ // PARAMETERS
154
+ //----------------------------------------------------------------------------------
155
+
156
+ // FSM states (states associated to unpublished blocks have been removed)
157
+ localparam IDLE = 4'd0;
158
+ localparam PROP = 4'd1;
159
+ localparam STEP = 4'd2;
160
+ localparam SDONE = 4'd3;
161
+ localparam GET_TAR = 4'd4;
162
+ localparam CONFIG = 4'd5;
163
+ localparam EPROP = 4'd6;
164
+ localparam SEND = 4'd7;
165
+
166
+ localparam WAIT = 2'd0;
167
+ localparam CNT = 2'd1;
168
+ localparam EVT = 2'd2;
169
+ localparam SUPP = 2'd3;
170
+
171
+
172
+ //----------------------------------------------------------------------------------
173
+ // Internal regs and wires
174
+ //----------------------------------------------------------------------------------
175
+
176
+ // Sync barriers
177
+ reg AERIN_REQ_sync_int , AERIN_REQ_sync ;
178
+ reg SAMPLE_sync_int , SAMPLE_sync ;
179
+ reg TARGET_VALID_sync_int , TARGET_VALID_sync ;
180
+ reg INFER_ACC_sync_int , INFER_ACC_sync ;
181
+ reg TIME_TICK_sync_int , TIME_TICK_sync , TIME_TICK_del ;
182
+ reg PROG_NEUR_sync_int , PROG_NEUR_sync , PROG_NEUR_del ;
183
+ reg PROG_ONEUR_sync_int , PROG_ONEUR_sync , PROG_ONEUR_del ;
184
+ reg PROG_WINP_sync_int , PROG_WINP_sync , PROG_WINP_del ;
185
+ reg PROG_WREC_sync_int , PROG_WREC_sync , PROG_WREC_del ;
186
+ reg PROG_WOUT_sync_int , PROG_WOUT_sync , PROG_WOUT_del ;
187
+ reg PROG_SEED_INP_sync_int , PROG_SEED_INP_sync , PROG_SEED_INP_del ;
188
+ reg PROG_SEED_REC_sync_int , PROG_SEED_REC_sync , PROG_SEED_REC_del ;
189
+ reg PROG_SEED_OUT_sync_int , PROG_SEED_OUT_sync , PROG_SEED_OUT_del ;
190
+ reg PROG_SEED_STRND_NEUR_sync_int , PROG_SEED_STRND_NEUR_sync , PROG_SEED_STRND_NEUR_del ;
191
+ reg PROG_SEED_STRND_ONEUR_sync_int, PROG_SEED_STRND_ONEUR_sync, PROG_SEED_STRND_ONEUR_del;
192
+ reg PROG_SEED_STRND_TINP_sync_int , PROG_SEED_STRND_TINP_sync , PROG_SEED_STRND_TINP_del ;
193
+ reg PROG_SEED_STRND_TREC_sync_int , PROG_SEED_STRND_TREC_sync , PROG_SEED_STRND_TREC_del ;
194
+ reg PROG_SEED_STRND_TOUT_sync_int , PROG_SEED_STRND_TOUT_sync , PROG_SEED_STRND_TOUT_del ;
195
+ reg PROG_SEED_NOISE_NEUR_sync_int , PROG_SEED_NOISE_NEUR_sync , PROG_SEED_NOISE_NEUR_del ;
196
+ reg READ_NEUR_sync_int , READ_NEUR_sync ;
197
+ reg READ_ONEUR_sync_int , READ_ONEUR_sync ;
198
+ reg READ_WINP_sync_int , READ_WINP_sync ;
199
+ reg READ_WREC_sync_int , READ_WREC_sync ;
200
+ reg READ_WOUT_sync_int , READ_WOUT_sync ;
201
+ reg OUT_ACK_sync_int , OUT_ACK_sync ;
202
+ wire TIME_TICK_new ;
203
+ wire PROG_NEUR_new ;
204
+ wire PROG_ONEUR_new ;
205
+ wire PROG_WINP_new ;
206
+ wire PROG_WREC_new ;
207
+ wire PROG_WOUT_new ;
208
+ wire PROG_SEED_INP_new ;
209
+ wire PROG_SEED_REC_new ;
210
+ wire PROG_SEED_OUT_new ;
211
+ wire PROG_SEED_STRND_NEUR_new ;
212
+ wire PROG_SEED_STRND_ONEUR_new ;
213
+ wire PROG_SEED_STRND_TINP_new ;
214
+ wire PROG_SEED_STRND_TREC_new ;
215
+ wire PROG_SEED_STRND_TOUT_new ;
216
+ wire PROG_SEED_NOISE_NEUR_new ;
217
+ wire [M-1:0] SPI_NUM_NEUR, SPI_NUM_RECOUT ;
218
+ reg TIMING_ERROR ;
219
+
220
+
221
+ // I/O
222
+ // Receiving events
223
+ wire aerin_new;
224
+ reg [N-1:0] inp_events;
225
+ reg [N-1:0] inp_events_next;
226
+ // Receiving targets
227
+ reg signed [15:0] reg_tar [15:0];
228
+ reg [ 3:0] class_label ;
229
+ reg got_label ;
230
+ wire target_new ;
231
+ wire target_done ;
232
+ reg [ 4:0] target_cnt ;
233
+ // Sending classification results
234
+ wire send_done;
235
+ reg [4:0] send_cnt;
236
+ wire [4:0] send_num;
237
+
238
+
239
+ // Global controller
240
+ reg [ 3:0] state, nextstate;
241
+ wire time_tick;
242
+ reg [ 31:0] tick_cnt;
243
+ reg [M-1:0] neur_step_cnt;
244
+
245
+
246
+ // eprop handling
247
+ reg [ 3:0] e_post_msb;
248
+ reg [ 4:0] e_post_lsb;
249
+ reg [ M:0] e_pre;
250
+ wire [M-1:0] e_post;
251
+ reg buf16_post;
252
+ wire skip_update_winp;
253
+ wire skip_update_wrec;
254
+ wire skip_update_wout;
255
+ wire eprop_done;
256
+
257
+ wire [M-2:0] neur_addr_eprop;
258
+ wire neur_cs_eprop;
259
+ reg neur_cs_eprop_del;
260
+ wire winp_cs_eprop , wrec_cs_eprop , wout_cs_eprop ;
261
+ wire winp_we_eprop , wrec_we_eprop , wout_we_eprop ;
262
+ wire [M+3:0] winp_addr_eprop , wrec_addr_eprop ;
263
+ wire [M :0] wout_addr_eprop ;
264
+ wire [127:0] winp_data_i_eprop, wrec_data_i_eprop, wrec_data_i_eprop_temp, wout_data_i_eprop;
265
+ wire [127:0] winp_mask_eprop , wrec_mask_eprop , wout_mask_eprop ;
266
+
267
+ reg signed [27:0] neur_learn_sigs_psum [15:0];
268
+ wire signed [43:0] neur_learn_sigs_temp1;
269
+ wire signed [15:0] neur_learn_sigs_temp2;
270
+ reg signed [15:0] learning_signals [15:0];
271
+ wire signed [15:0] neur_u_eprop;
272
+ wire [11:0] trace_rec_reg, trace_rec_reg_f0;
273
+ wire [11:0] trace_inp_eprop, trace_rec_eprop;
274
+ wire [ 9:0] trace_out_eprop;
275
+ wire signed [ 4:0] update_h;
276
+ reg signed [ 4:0] neur_h [15:0];
277
+ reg [11:0] trace_reg [15:0];
278
+ wire trace_reg_zero;
279
+
280
+ wire do_update_winp;
281
+ wire do_update_wrec;
282
+ wire do_update_wregi;
283
+ wire do_update_wregr;
284
+ wire do_update_wout;
285
+ wire [511:0] winp_rand;
286
+ wire [511:0] wrec_rand;
287
+ wire [447:0] wout_rand;
288
+
289
+ wire winp_en [15:0];
290
+ wire wrec_en [15:0];
291
+ wire signed [ 31:0] prob_winp [15:0];
292
+ wire signed [ 31:0] prob_wrec [15:0];
293
+ wire signed [ 31:0] prob_winp_e [15:0];
294
+ wire signed [ 31:0] prob_wrec_e [15:0];
295
+ wire signed [ 31:0] prob_wregi [15:0];
296
+ wire signed [ 31:0] prob_wregr [15:0];
297
+ wire [ 11:0] prob_wregm [15:0];
298
+ wire signed [ 5:0] prob_wregs [15:0];
299
+ wire signed [ 36:0] prob_winp_k [15:0];
300
+ wire signed [ 36:0] prob_wrec_k [15:0];
301
+ wire signed [ 31:0] prob_winp_s [15:0];
302
+ wire signed [ 31:0] prob_wrec_s [15:0];
303
+ wire signed [ 27:0] prob_wout [15:0];
304
+
305
+
306
+ // Event controller
307
+ reg [ 1:0] state_evt, nextstate_evt;
308
+ wire inp_event;
309
+ wire inp_evt_trace, rec_evt_trace, out_evt_trace;
310
+ wire winp_cs_ctrl, wrec_cs_ctrl, wout_cs_ctrl;
311
+ wire [M+3:0] winp_addr_ctrl, wrec_addr_ctrl;
312
+ wire [M :0] wout_addr_ctrl;
313
+ wire supp_cond;
314
+ reg wout_cs_del;
315
+ reg supp_cycle;
316
+ reg [M-1:0] neur128x2_cnt;
317
+ reg [M-1:0] neur256_cnt;
318
+
319
+
320
+ // Neuron array and updates
321
+ wire neur_cs_ctrl, neur_we_ctrl;
322
+ wire [M-2:0] neur_addr_ctrl;
323
+ reg [127:0] neur_data_i_ctrl, neur_mask_ctrl;
324
+ reg signed [ 15:0] neur_u [1:0];
325
+ reg [ 11:0] trace_inp [1:0];
326
+ reg [ 11:0] trace_rec [1:0];
327
+ reg [ 9:0] trace_out [1:0];
328
+ wire [ 3:0] alpha_msb;
329
+ wire [ 15:0] alpha;
330
+ wire signed [ 16:0] alpha_s;
331
+ wire signed [ 15:0] thr;
332
+ wire [127:0] shift_winp;
333
+ wire [127:0] shift_wrec;
334
+ wire [ 31:0] neur_noise_rand;
335
+
336
+ reg signed [ 15:0] update_winp [1:0];
337
+ reg signed [ 15:0] update_wrec [1:0];
338
+ reg signed [ 15:0] update_wt [1:0];
339
+ reg signed [ 15:0] update_w [1:0];
340
+ reg signed [ 15:0] update_u [1:0];
341
+ reg ovfl_p [1:0];
342
+ reg ovfl_n [1:0];
343
+ reg signed [ 15:0] neur_u_next [1:0];
344
+
345
+ wire [ 14:0] neur_u_leak_rand [1:0];
346
+ reg signed [ 31:0] neur_u_leak [1:0];
347
+ reg signed [ 15:0] neur_u_stoc [1:0];
348
+ reg signed [ 15:0] neur_u_lkst [1:0];
349
+ reg neur_u_spk [1:0];
350
+ reg signed [ 15:0] neur_u_step [1:0];
351
+
352
+ reg [N-1:0] neur_z;
353
+ reg [N-1:0] neur_dirty;
354
+
355
+ wire [ 6:0] oneur_u_leak_rand;
356
+ reg signed [ 15:0] update_wout [15:0];
357
+ reg signed [ 15:0] update_out [15:0];
358
+ reg ovfl_out_p [15:0];
359
+ reg ovfl_out_n [15:0];
360
+ reg signed [ 15:0] oneur_out_next [15:0];
361
+ wire signed [ 23:0] oneur_u_leak;
362
+ wire signed [ 15:0] oneur_u_stoc, oneur_u_lkst;
363
+ reg signed [ 15:0] oneur_u [ 15:0];
364
+ wire signed [ 15:0] oneur_err [15:0];
365
+
366
+ wire [ 14:0] trace_inp_rand [1:0];
367
+ wire [ 14:0] trace_rec_rand [1:0];
368
+ wire [ 6:0] trace_out_rand [1:0];
369
+ reg [ 11:0] trace_inp_inc [1:0];
370
+ reg [ 27:0] trace_inp_step [1:0];
371
+ reg [ 11:0] trace_inp_stoc [1:0];
372
+ reg [ 11:0] trace_inp_lkst [1:0];
373
+ reg [ 11:0] trace_inp_next [1:0];
374
+ reg [ 11:0] trace_rec_inc [1:0];
375
+ reg [ 27:0] trace_rec_step [1:0];
376
+ reg [ 11:0] trace_rec_stoc [1:0];
377
+ reg [ 11:0] trace_rec_lkst [1:0];
378
+ reg [ 11:0] trace_rec_next [1:0];
379
+ reg [ 9:0] trace_out_inc [1:0];
380
+ reg [ 17:0] trace_out_step [1:0];
381
+ reg [ 9:0] trace_out_stoc [1:0];
382
+ reg [ 9:0] trace_out_lkst [1:0];
383
+ reg [ 9:0] trace_out_next [1:0];
384
+
385
+
386
+ // Winner computation
387
+ reg [ 3:0] label_winner [15:0];
388
+ reg signed [15:0] neur_winner [15:0];
389
+ reg [15:0] cnt_winner [15:0];
390
+ reg [15:0] aer_winner [15:0];
391
+ reg [ 3:0] send_winner [15:0];
392
+
393
+
394
+ // Readback
395
+ wire [127:0] neur_data_o_shift;
396
+ wire [127:0] winp_data_o_shift;
397
+ wire [127:0] wrec_data_o_shift;
398
+ wire [127:0] wout_data_o_shift;
399
+
400
+
401
+ // SRAMs
402
+ wire neur_cs;
403
+ wire neur_we;
404
+ wire [M-2:0] neur_addr;
405
+ wire [127:0] neur_data_i;
406
+ wire [127:0] neur_mask;
407
+ wire [127:0] neur_data_o;
408
+ wire winp_cs , wrec_cs , wout_cs ;
409
+ wire winp_we , wrec_we , wout_we ;
410
+ wire [M+3:0] winp_addr , wrec_addr ;
411
+ wire [M :0] wout_addr ;
412
+ wire [127:0] winp_data_i, wrec_data_i, wout_data_i;
413
+ wire [127:0] winp_mask , wrec_mask , wout_mask ;
414
+ wire [127:0] winp_data_o, wrec_data_o, wout_data_o;
415
+
416
+
417
+ // Other ariables for logic generation
418
+ genvar i, j, k, n;
419
+ integer kk;
420
+
421
+
422
+ //----------------------------------------------------------------------------------
423
+ // Sync barriers
424
+ //----------------------------------------------------------------------------------
425
+
426
+ always @(posedge CLK, posedge RST) begin
427
+ if (RST) begin
428
+ TARGET_VALID_sync_int <= 1'b0;
429
+ TARGET_VALID_sync <= 1'b0;
430
+ end else if (|SPI_DO_EPROP) begin
431
+ TARGET_VALID_sync_int <= TARGET_VALID;
432
+ TARGET_VALID_sync <= TARGET_VALID_sync_int;
433
+ end
434
+ end
435
+
436
+ always @(posedge CLK, posedge RST) begin
437
+ if (RST) begin
438
+ AERIN_REQ_sync_int <= 1'b0;
439
+ AERIN_REQ_sync <= 1'b0;
440
+ SAMPLE_sync_int <= 1'b0;
441
+ SAMPLE_sync <= 1'b0;
442
+ INFER_ACC_sync_int <= 1'b0;
443
+ INFER_ACC_sync <= 1'b0;
444
+ OUT_ACK_sync_int <= 1'b0;
445
+ OUT_ACK_sync <= 1'b0;
446
+ end else begin
447
+ AERIN_REQ_sync_int <= AERIN_REQ;
448
+ AERIN_REQ_sync <= AERIN_REQ_sync_int;
449
+ SAMPLE_sync_int <= SAMPLE;
450
+ SAMPLE_sync <= SAMPLE_sync_int;
451
+ INFER_ACC_sync_int <= INFER_ACC;
452
+ INFER_ACC_sync <= INFER_ACC_sync_int;
453
+ OUT_ACK_sync_int <= OUT_ACK;
454
+ OUT_ACK_sync <= OUT_ACK_sync_int;
455
+ end
456
+ end
457
+
458
+ always @(posedge CLK, posedge RST) begin
459
+ if (RST) begin
460
+ PROG_NEUR_sync_int <= 1'b0;
461
+ PROG_NEUR_sync <= 1'b0;
462
+ PROG_NEUR_del <= 1'b0;
463
+ PROG_ONEUR_sync_int <= 1'b0;
464
+ PROG_ONEUR_sync <= 1'b0;
465
+ PROG_ONEUR_del <= 1'b0;
466
+ PROG_WINP_sync_int <= 1'b0;
467
+ PROG_WINP_sync <= 1'b0;
468
+ PROG_WINP_del <= 1'b0;
469
+ PROG_WREC_sync_int <= 1'b0;
470
+ PROG_WREC_sync <= 1'b0;
471
+ PROG_WREC_del <= 1'b0;
472
+ PROG_WOUT_sync_int <= 1'b0;
473
+ PROG_WOUT_sync <= 1'b0;
474
+ PROG_WOUT_del <= 1'b0;
475
+ PROG_SEED_INP_sync_int <= 1'b0;
476
+ PROG_SEED_INP_sync <= 1'b0;
477
+ PROG_SEED_INP_del <= 1'b0;
478
+ PROG_SEED_REC_sync_int <= 1'b0;
479
+ PROG_SEED_REC_sync <= 1'b0;
480
+ PROG_SEED_REC_del <= 1'b0;
481
+ PROG_SEED_OUT_sync_int <= 1'b0;
482
+ PROG_SEED_OUT_sync <= 1'b0;
483
+ PROG_SEED_OUT_del <= 1'b0;
484
+ PROG_SEED_STRND_NEUR_sync_int <= 1'b0;
485
+ PROG_SEED_STRND_NEUR_sync <= 1'b0;
486
+ PROG_SEED_STRND_NEUR_del <= 1'b0;
487
+ PROG_SEED_STRND_ONEUR_sync_int <= 1'b0;
488
+ PROG_SEED_STRND_ONEUR_sync <= 1'b0;
489
+ PROG_SEED_STRND_ONEUR_del <= 1'b0;
490
+ PROG_SEED_STRND_TINP_sync_int <= 1'b0;
491
+ PROG_SEED_STRND_TINP_sync <= 1'b0;
492
+ PROG_SEED_STRND_TINP_del <= 1'b0;
493
+ PROG_SEED_STRND_TREC_sync_int <= 1'b0;
494
+ PROG_SEED_STRND_TREC_sync <= 1'b0;
495
+ PROG_SEED_STRND_TREC_del <= 1'b0;
496
+ PROG_SEED_STRND_TOUT_sync_int <= 1'b0;
497
+ PROG_SEED_STRND_TOUT_sync <= 1'b0;
498
+ PROG_SEED_STRND_TOUT_del <= 1'b0;
499
+ PROG_SEED_NOISE_NEUR_sync_int <= 1'b0;
500
+ PROG_SEED_NOISE_NEUR_sync <= 1'b0;
501
+ PROG_SEED_NOISE_NEUR_del <= 1'b0;
502
+ READ_NEUR_sync_int <= 1'b0;
503
+ READ_NEUR_sync <= 1'b0;
504
+ READ_ONEUR_sync_int <= 1'b0;
505
+ READ_ONEUR_sync <= 1'b0;
506
+ READ_WINP_sync_int <= 1'b0;
507
+ READ_WINP_sync <= 1'b0;
508
+ READ_WREC_sync_int <= 1'b0;
509
+ READ_WREC_sync <= 1'b0;
510
+ READ_WOUT_sync_int <= 1'b0;
511
+ READ_WOUT_sync <= 1'b0;
512
+ end else if (SPI_EN_CONF) begin
513
+ PROG_NEUR_sync_int <= PROG_NEUR;
514
+ PROG_NEUR_sync <= PROG_NEUR_sync_int;
515
+ PROG_NEUR_del <= PROG_NEUR_sync;
516
+ PROG_ONEUR_sync_int <= PROG_ONEUR;
517
+ PROG_ONEUR_sync <= PROG_ONEUR_sync_int;
518
+ PROG_ONEUR_del <= PROG_ONEUR_sync;
519
+ PROG_WINP_sync_int <= PROG_WINP;
520
+ PROG_WINP_sync <= PROG_WINP_sync_int;
521
+ PROG_WINP_del <= PROG_WINP_sync;
522
+ PROG_WREC_sync_int <= PROG_WREC;
523
+ PROG_WREC_sync <= PROG_WREC_sync_int;
524
+ PROG_WREC_del <= PROG_WREC_sync;
525
+ PROG_WOUT_sync_int <= PROG_WOUT;
526
+ PROG_WOUT_sync <= PROG_WOUT_sync_int;
527
+ PROG_WOUT_del <= PROG_WOUT_sync;
528
+ PROG_SEED_INP_sync_int <= PROG_SEED_INP;
529
+ PROG_SEED_INP_sync <= PROG_SEED_INP_sync_int;
530
+ PROG_SEED_INP_del <= PROG_SEED_INP_sync;
531
+ PROG_SEED_REC_sync_int <= PROG_SEED_REC;
532
+ PROG_SEED_REC_sync <= PROG_SEED_REC_sync_int;
533
+ PROG_SEED_REC_del <= PROG_SEED_REC_sync;
534
+ PROG_SEED_OUT_sync_int <= PROG_SEED_OUT;
535
+ PROG_SEED_OUT_sync <= PROG_SEED_OUT_sync_int;
536
+ PROG_SEED_OUT_del <= PROG_SEED_OUT_sync;
537
+ PROG_SEED_STRND_NEUR_sync_int <= PROG_SEED_STRND_NEUR;
538
+ PROG_SEED_STRND_NEUR_sync <= PROG_SEED_STRND_NEUR_sync_int;
539
+ PROG_SEED_STRND_NEUR_del <= PROG_SEED_STRND_NEUR_sync;
540
+ PROG_SEED_STRND_ONEUR_sync_int <= PROG_SEED_STRND_ONEUR;
541
+ PROG_SEED_STRND_ONEUR_sync <= PROG_SEED_STRND_ONEUR_sync_int;
542
+ PROG_SEED_STRND_ONEUR_del <= PROG_SEED_STRND_ONEUR_sync;
543
+ PROG_SEED_STRND_TINP_sync_int <= PROG_SEED_STRND_TINP;
544
+ PROG_SEED_STRND_TINP_sync <= PROG_SEED_STRND_TINP_sync_int;
545
+ PROG_SEED_STRND_TINP_del <= PROG_SEED_STRND_TINP_sync;
546
+ PROG_SEED_STRND_TREC_sync_int <= PROG_SEED_STRND_TREC;
547
+ PROG_SEED_STRND_TREC_sync <= PROG_SEED_STRND_TREC_sync_int;
548
+ PROG_SEED_STRND_TREC_del <= PROG_SEED_STRND_TREC_sync;
549
+ PROG_SEED_STRND_TOUT_sync_int <= PROG_SEED_STRND_TOUT;
550
+ PROG_SEED_STRND_TOUT_sync <= PROG_SEED_STRND_TOUT_sync_int;
551
+ PROG_SEED_STRND_TOUT_del <= PROG_SEED_STRND_TOUT_sync;
552
+ PROG_SEED_NOISE_NEUR_sync_int <= PROG_SEED_NOISE_NEUR;
553
+ PROG_SEED_NOISE_NEUR_sync <= PROG_SEED_NOISE_NEUR_sync_int;
554
+ PROG_SEED_NOISE_NEUR_del <= PROG_SEED_NOISE_NEUR_sync;
555
+ READ_NEUR_sync_int <= READ_NEUR;
556
+ READ_NEUR_sync <= READ_NEUR_sync_int;
557
+ READ_ONEUR_sync_int <= READ_ONEUR;
558
+ READ_ONEUR_sync <= READ_ONEUR_sync_int;
559
+ READ_WINP_sync_int <= READ_WINP;
560
+ READ_WINP_sync <= READ_WINP_sync_int;
561
+ READ_WREC_sync_int <= READ_WREC;
562
+ READ_WREC_sync <= READ_WREC_sync_int;
563
+ READ_WOUT_sync_int <= READ_WOUT;
564
+ READ_WOUT_sync <= READ_WOUT_sync_int;
565
+ end
566
+ end
567
+
568
+ always @(posedge CLK, posedge RST) begin
569
+ if (RST) begin
570
+ TIME_TICK_sync_int <= 1'b0;
571
+ TIME_TICK_sync <= 1'b0;
572
+ TIME_TICK_del <= 1'b0;
573
+ end else if (!SPI_LOCAL_TICK) begin
574
+ TIME_TICK_sync_int <= TIME_TICK;
575
+ TIME_TICK_sync <= TIME_TICK_sync_int;
576
+ TIME_TICK_del <= TIME_TICK_sync;
577
+ end
578
+ end
579
+
580
+ assign TIME_TICK_new = TIME_TICK_sync & ~TIME_TICK_del;
581
+ assign PROG_NEUR_new = PROG_NEUR_sync & ~PROG_NEUR_del;
582
+ assign PROG_ONEUR_new = PROG_ONEUR_sync & ~PROG_ONEUR_del;
583
+ assign PROG_WINP_new = PROG_WINP_sync & ~PROG_WINP_del;
584
+ assign PROG_WREC_new = PROG_WREC_sync & ~PROG_WREC_del;
585
+ assign PROG_WOUT_new = PROG_WOUT_sync & ~PROG_WOUT_del;
586
+ assign PROG_SEED_INP_new = PROG_SEED_INP_sync & ~PROG_SEED_INP_del;
587
+ assign PROG_SEED_REC_new = PROG_SEED_REC_sync & ~PROG_SEED_REC_del;
588
+ assign PROG_SEED_OUT_new = PROG_SEED_OUT_sync & ~PROG_SEED_OUT_del;
589
+ assign PROG_SEED_STRND_NEUR_new = PROG_SEED_STRND_NEUR_sync & ~PROG_SEED_STRND_NEUR_del;
590
+ assign PROG_SEED_STRND_ONEUR_new = PROG_SEED_STRND_ONEUR_sync & ~PROG_SEED_STRND_ONEUR_del;
591
+ assign PROG_SEED_STRND_TINP_new = PROG_SEED_STRND_TINP_sync & ~PROG_SEED_STRND_TINP_del;
592
+ assign PROG_SEED_STRND_TREC_new = PROG_SEED_STRND_TREC_sync & ~PROG_SEED_STRND_TREC_del;
593
+ assign PROG_SEED_STRND_TOUT_new = PROG_SEED_STRND_TOUT_sync & ~PROG_SEED_STRND_TOUT_del;
594
+ assign PROG_SEED_NOISE_NEUR_new = PROG_SEED_NOISE_NEUR_sync & ~PROG_SEED_NOISE_NEUR_del;
595
+
596
+ assign SPI_NUM_NEUR = (SPI_NUM_REC_NEUR > SPI_NUM_INP_NEUR) ? SPI_NUM_REC_NEUR : SPI_NUM_INP_NEUR;
597
+ assign SPI_NUM_RECOUT = ((SPI_NUM_REC_NEUR > SPI_NUM_OUT_NEUR ) && (SPI_NUM_REC_NEUR > SPI_NUM_INP_NEUR)) ? SPI_NUM_REC_NEUR : ((SPI_NUM_INP_NEUR > SPI_NUM_OUT_NEUR) ? SPI_NUM_INP_NEUR : SPI_NUM_OUT_NEUR);
598
+ assign TIMING_ERROR_RDY = SPI_TIMING_MODE ? TIMING_ERROR : ((state == IDLE) | ((state == PROP) & (state_evt == WAIT) & (nextstate_evt == WAIT)));
599
+
600
+
601
+ //----------------------------------------------------------------------------------
602
+ // Receiving events
603
+ //----------------------------------------------------------------------------------
604
+
605
+ assign aerin_new = ~AERIN_ACK & ~AERIN_TAR_EN & AERIN_REQ_sync;
606
+
607
+ always @(posedge CLK, posedge RST)
608
+ if (RST)
609
+ AERIN_ACK <= 1'b0;
610
+ else if (aerin_new | target_new)
611
+ AERIN_ACK <= 1'b1;
612
+ else if (AERIN_ACK && !AERIN_REQ_sync)
613
+ AERIN_ACK <= 1'b0;
614
+
615
+
616
+ generate
617
+ for (i=0; i<N; i=i+1)
618
+ always @(posedge CLK)
619
+ if (RST || ((state != IDLE) && (nextstate == IDLE))) begin
620
+ inp_events[i] <= 1'b0;
621
+ inp_events_next[i] <= 1'b0;
622
+ end else if (time_tick) begin
623
+ inp_events[i] <= inp_events_next[i];
624
+ inp_events_next[i] <= 1'b0;
625
+ end else if (aerin_new && (i == AERIN_ADDR)) begin
626
+ inp_events_next[i] <= 1'b1;
627
+ end else if (neur_cs_ctrl && neur_we_ctrl && ((state_evt == EVT) || (state_evt == SUPP)) && ((nextstate_evt == CNT) || (nextstate_evt == WAIT)) && (i[7:0] == neur256_cnt)) begin
628
+ inp_events[i] <= 1'b0;
629
+ end
630
+ endgenerate
631
+
632
+
633
+ //----------------------------------------------------------------------------------
634
+ // Receiving targets (for both classification and regression)
635
+ //----------------------------------------------------------------------------------
636
+
637
+ assign target_new = ~AERIN_ACK & AERIN_TAR_EN & AERIN_REQ_sync;
638
+ assign target_done = target_new & (~SPI_REGRESSION | ((target_cnt[4:1] == SPI_NUM_OUT_NEUR) & target_cnt[0]));
639
+ assign REQ_TAR = (state == GET_TAR);
640
+
641
+ always @(posedge CLK)
642
+ if (state == IDLE)
643
+ target_cnt <= 5'b0;
644
+ else if ((state == GET_TAR) && (nextstate != GET_TAR))
645
+ target_cnt <= 5'b0;
646
+ else if (target_new)
647
+ target_cnt <= target_cnt + 5'b1;
648
+
649
+ // Regression
650
+ generate
651
+ for (i=0; i<16; i=i+1) begin
652
+ always @(posedge CLK)
653
+ if (SPI_REGRESSION && target_new && (i == target_cnt[4:1]))
654
+ if (target_cnt[0])
655
+ reg_tar[i][15:8] <= AERIN_ADDR;
656
+ else
657
+ reg_tar[i][ 7:0] <= AERIN_ADDR;
658
+ end
659
+ endgenerate
660
+
661
+ // Classification
662
+ always @(posedge CLK)
663
+ if (!SPI_REGRESSION && target_new)
664
+ class_label <= AERIN_ADDR[3:0];
665
+ always @(posedge CLK)
666
+ if (state == IDLE)
667
+ got_label <= 1'b0;
668
+ else if (!SPI_REGRESSION && target_new)
669
+ got_label <= 1'b1;
670
+
671
+
672
+ //----------------------------------------------------------------------------------
673
+ // Sending classification results
674
+ //----------------------------------------------------------------------------------
675
+
676
+ assign send_done = OUT_ACK_sync & OUT_REQ & (send_cnt == send_num);
677
+ assign send_num = SPI_SEND_LABEL_ONLY ? 5'd0 : {SPI_NUM_OUT_NEUR,1'b1};
678
+
679
+ always @(posedge CLK)
680
+ if (state == IDLE) begin
681
+ OUT_REQ <= 1'b0;
682
+ OUT_DATA <= 8'b0;
683
+ send_cnt <= 'd0;
684
+ end else if ((state == SEND) && (nextstate != SEND)) begin
685
+ OUT_REQ <= 1'b0;
686
+ send_cnt <= 'd0;
687
+ end else if ((state == SEND) && (send_cnt <= send_num))
688
+ if (!OUT_ACK_sync && !OUT_REQ) begin
689
+ OUT_REQ <= 1'b1;
690
+ OUT_DATA <= SPI_SEND_LABEL_ONLY ? {4'b0,send_winner[15]} : (send_cnt[0] ? oneur_u[send_cnt[4:1]][15:8] : oneur_u[send_cnt[4:1]][7:0]);
691
+ end else if ( OUT_ACK_sync && OUT_REQ) begin
692
+ OUT_REQ <= 1'b0;
693
+ send_cnt <= send_cnt + 'd1;
694
+ end
695
+
696
+
697
+ //----------------------------------------------------------------------------------
698
+ // Global controller (FSM, timestep-driven)
699
+ //----------------------------------------------------------------------------------
700
+
701
+ // State register
702
+ always @(posedge CLK, posedge RST)
703
+ begin
704
+ if (RST) state <= IDLE;
705
+ else if (SPI_ERROR_HALT && TIMING_ERROR) state <= IDLE;
706
+ else state <= nextstate;
707
+ end
708
+
709
+ // Next state logic
710
+ always @(*)
711
+ case(state)
712
+ IDLE : if (SAMPLE_sync && time_tick) nextstate = PROP;
713
+ else nextstate = IDLE;
714
+ PROP : if (time_tick) nextstate = STEP;
715
+ else nextstate = PROP;
716
+ STEP : if (neur_step_cnt == SPI_NUM_RECOUT) nextstate = SDONE;
717
+ else nextstate = STEP;
718
+ SDONE : if (!SAMPLE_sync) nextstate = SEND;
719
+ else if (SPI_EN_CONF) nextstate = CONFIG;
720
+ else if (|SPI_DO_EPROP && (TARGET_VALID_sync || &SPI_REGUL_MODE[2:1]))
721
+ if (!(SPI_SINGLE_LABEL && got_label)) nextstate = GET_TAR;
722
+ else nextstate = EPROP;
723
+ else if (SPI_SEND_PER_TIMESTEP) nextstate = SEND;
724
+ else nextstate = PROP;
725
+ GET_TAR: if (target_done) nextstate = EPROP;
726
+ else nextstate = GET_TAR;
727
+ CONFIG : if (!SPI_EN_CONF)
728
+ if (|SPI_DO_EPROP && (TARGET_VALID_sync || &SPI_REGUL_MODE[2:1]))
729
+ if (!(SPI_SINGLE_LABEL && got_label)) nextstate = GET_TAR;
730
+ else nextstate = EPROP;
731
+ else if (SPI_SEND_PER_TIMESTEP) nextstate = SEND;
732
+ else nextstate = PROP;
733
+ else nextstate = CONFIG;
734
+ EPROP : if (eprop_done && SPI_SEND_PER_TIMESTEP) nextstate = SEND;
735
+ else if (eprop_done && SAMPLE_sync) nextstate = PROP;
736
+ else nextstate = EPROP;
737
+ SEND : if (send_done && SPI_SEND_PER_TIMESTEP && SAMPLE_sync) nextstate = PROP;
738
+ else if (send_done) nextstate = IDLE;
739
+ else nextstate = SEND;
740
+ default: nextstate = IDLE;
741
+ endcase
742
+
743
+ // SPI readyness
744
+ assign SPI_RDY = (state == CONFIG);
745
+
746
+ // Time handling
747
+ always @(posedge CLK)
748
+ if (SPI_LOCAL_TICK && (state != IDLE) && (tick_cnt != SPI_CYCLES_PER_TICK)) tick_cnt <= tick_cnt + 32'd1;
749
+ else tick_cnt <= 32'd1;
750
+ assign time_tick = SPI_LOCAL_TICK ? (tick_cnt == SPI_CYCLES_PER_TICK) : TIME_TICK_new;
751
+
752
+ // Step handling
753
+ always @(posedge CLK)
754
+ if (nextstate != STEP)
755
+ neur_step_cnt <= 'd0;
756
+ else if (state == STEP)
757
+ neur_step_cnt <= neur_step_cnt + 'd1;
758
+
759
+ // Timing error
760
+ always @(posedge CLK, posedge RST)
761
+ if (RST) TIMING_ERROR <= 1'b0;
762
+ else if (time_tick && ( ((state != IDLE) && (state != PROP)) || ((state == PROP) && (state_evt != WAIT)) ) ) TIMING_ERROR <= 1'b1;
763
+
764
+
765
+
766
+ // ----------------------------------------------------- e-prop handling --------------------------------------------------------------
767
+
768
+ always @(posedge CLK)
769
+ if ((state != EPROP) && (nextstate == EPROP)) begin
770
+ e_pre <= 'd0;
771
+ e_post_msb <= 'd0;
772
+ e_post_lsb <= 'd0;
773
+ buf16_post <= 1'b1;
774
+ end else if (state == EPROP) begin
775
+ if (buf16_post) begin
776
+ e_post_lsb <= e_post_lsb + 'd1;
777
+ e_post_msb <= ((SPI_DO_EPROP == 3'b100) & &e_post_lsb) ? (e_post_msb + 'd1) : e_post_msb;
778
+ buf16_post <= (SPI_DO_EPROP == 3'b100) | ~&e_post_lsb;
779
+ end else begin
780
+ e_pre <= ((e_pre[M:1] == SPI_NUM_NEUR) & e_pre[0]) ? 'd0 : (e_pre + 'd1);
781
+ e_post_msb <= ((e_pre[M:1] == SPI_NUM_NEUR) & e_pre[0]) ? (e_post_msb + 'd1) : e_post_msb;
782
+ buf16_post <= ((e_pre[M:1] == SPI_NUM_NEUR) & e_pre[0]);
783
+ end
784
+ end
785
+ always @(posedge CLK)
786
+ if (state == EPROP)
787
+ neur_cs_eprop_del <= (neur_cs_eprop & buf16_post);
788
+ else
789
+ neur_cs_eprop_del <= 1'b0;
790
+ assign eprop_done = (SPI_DO_EPROP == 3'b100) ? ((e_post_msb == SPI_NUM_REC_NEUR[M-1:4]) & (e_post_lsb[4:1] == SPI_NUM_REC_NEUR[3:0]) & e_post_lsb[0])
791
+ : ((e_post_msb == SPI_NUM_REC_NEUR[M-1:4]) & (e_pre[M:1] == SPI_NUM_NEUR) & e_pre[0]);
792
+ assign skip_update_winp = e_pre[0] & ~|(trace_inp[e_pre[1]] >> SPI_FP_LOC_TINP) & trace_reg_zero;
793
+ assign skip_update_wrec = e_pre[0] & ~|(trace_rec[e_pre[1]] >> SPI_FP_LOC_TREC) & trace_reg_zero;
794
+ assign skip_update_wout = ~|(trace_out[e_post_lsb[1]] >> SPI_FP_LOC_TOUT) & e_post_lsb[0];
795
+ assign e_post = {e_post_msb,e_post_lsb[4:1]};
796
+
797
+ // Output logic
798
+ // Neur
799
+ assign neur_cs_eprop = (state == EPROP) & (buf16_post ? ((e_post <= SPI_NUM_NEUR) & TARGET_VALID_sync & ~|e_post_lsb[1:0])
800
+ : ((e_pre[M:1] <= SPI_NUM_NEUR) & TARGET_VALID_sync & ~|e_pre[1:0]));
801
+ assign neur_addr_eprop = buf16_post ? e_post[M-1:1] : e_pre[M:2];
802
+ // Wout
803
+ assign wout_cs_eprop = (state == EPROP) & buf16_post & ~skip_update_wout & (e_post <= SPI_NUM_REC_NEUR) & TARGET_VALID_sync & |SPI_DO_EPROP;
804
+ assign wout_we_eprop = e_post_lsb[0] & wout_cs_eprop & SPI_DO_EPROP[2];
805
+ assign wout_addr_eprop = {1'b0, e_post};
806
+ // Winp, Wrec
807
+ assign winp_cs_eprop = (state == EPROP) & ~buf16_post & ~skip_update_winp & (e_pre[M:1] <= SPI_NUM_INP_NEUR) & (TARGET_VALID_sync | (&SPI_REGUL_MODE[2:1] & SPI_REGUL_W[0])) & SPI_DO_EPROP[0];
808
+ assign wrec_cs_eprop = (state == EPROP) & ~buf16_post & ~skip_update_wrec & (e_pre[M:1] <= SPI_NUM_REC_NEUR) & (TARGET_VALID_sync | (&SPI_REGUL_MODE[2:1] & SPI_REGUL_W[1])) & SPI_DO_EPROP[1];
809
+ assign winp_we_eprop = e_pre[0] & winp_cs_eprop;
810
+ assign wrec_we_eprop = e_pre[0] & wrec_cs_eprop;
811
+ assign winp_addr_eprop = {e_pre[M:1],e_post_msb};
812
+ assign wrec_addr_eprop = {e_pre[M:1],e_post_msb};
813
+
814
+ // Learning signals (of post-synaptic neurons)
815
+ always @(*)
816
+ if (e_post_lsb[0] & |SPI_DO_EPROP[1:0]) begin
817
+ neur_learn_sigs_psum[0] = (oneur_err[0]*$signed(wout_data_o[7:0]));
818
+ for (kk=1; kk<16; kk=kk+1)
819
+ neur_learn_sigs_psum[kk] = (kk > SPI_NUM_OUT_NEUR) ? neur_learn_sigs_psum[kk-1] : ((oneur_err[kk]*$signed(wout_data_o[kk*8+:8])) + neur_learn_sigs_psum[kk-1]);
820
+ end else
821
+ for (kk=0; kk<16; kk=kk+1)
822
+ neur_learn_sigs_psum[kk] = 28'h0000000;
823
+ assign neur_learn_sigs_temp1 = {{16{neur_learn_sigs_psum[15][27]}},neur_learn_sigs_psum[15]} << SPI_LEARN_SIG_SCALE;
824
+ assign neur_learn_sigs_temp2 = (neur_learn_sigs_temp1[43:27] != {17{neur_learn_sigs_psum[15][27]}}) ? (neur_learn_sigs_psum[15][27] ? $signed(16'h8000) : $signed(16'h7FFF)) : $signed(neur_learn_sigs_temp1[27:12]);
825
+ generate
826
+ for (i=0; i<16; i=i+1) begin
827
+ always @(posedge CLK)
828
+ if ((state == EPROP) && (i == e_post_lsb[4:1]) && e_post_lsb[0])
829
+ learning_signals[i] <= (e_post <= SPI_NUM_REC_NEUR) ? neur_learn_sigs_temp2 : $signed(16'd0);
830
+ end
831
+ endgenerate
832
+
833
+ // Pseudo-derivatives and regularization traces (of post-synaptic neurons)
834
+ assign neur_u_eprop = e_post[0] ? neur_u[1] : neur_u[0];
835
+ assign trace_rec_reg = e_post[0] ? trace_rec[1] : trace_rec[0];
836
+ assign trace_rec_reg_f0 = (trace_rec_reg >> SPI_FP_LOC_TREC) - SPI_REGUL_F0;
837
+ assign trace_inp_eprop = (e_pre[1] ? trace_inp[1] : trace_inp[0]) >> SPI_FP_LOC_TINP;
838
+ assign trace_rec_eprop = (e_pre[1] ? trace_rec[1] : trace_rec[0]) >> SPI_FP_LOC_TREC;
839
+ assign trace_out_eprop = (e_post[0] ? trace_out[1] : trace_out[0]) >> SPI_FP_LOC_TOUT;
840
+ assign update_h = ((state == EPROP) && buf16_post) ? ((neur_u_eprop < SPI_THR_H_0) ? SPI_H_0
841
+ : ((neur_u_eprop < SPI_THR_H_1) ? SPI_H_1
842
+ : ((neur_u_eprop < SPI_THR_H_2) ? SPI_H_2
843
+ : ((neur_u_eprop < SPI_THR_H_3) ? SPI_H_3
844
+ : SPI_H_4))))
845
+ : $signed(5'd0);
846
+ generate
847
+ for (n=0; n<16; n=n+1) begin
848
+ always @(posedge CLK)
849
+ if (e_post_lsb[0] && (n == e_post_lsb[4:1]))
850
+ neur_h[n] <= update_h;
851
+ always @(posedge CLK)
852
+ if (e_post_lsb[0] && (n == e_post_lsb[4:1]) && |SPI_REGUL_MODE)
853
+ trace_reg[n] <= (trace_rec_reg_f0 > (trace_rec_reg >> SPI_FP_LOC_TREC)) ? 12'd0 : trace_rec_reg_f0;
854
+ end
855
+ endgenerate
856
+ assign trace_reg_zero = ~|SPI_REGUL_MODE ? 1'b1 : ~(|trace_reg[ 0] | |trace_reg[ 1] | |trace_reg[ 2] | |trace_reg[ 3] |
857
+ |trace_reg[ 4] | |trace_reg[ 5] | |trace_reg[ 6] | |trace_reg[ 7] |
858
+ |trace_reg[ 8] | |trace_reg[ 9] | |trace_reg[10] | |trace_reg[11] |
859
+ |trace_reg[12] | |trace_reg[13] | |trace_reg[14] | |trace_reg[15]);
860
+
861
+ // Input/Recurrent weight update
862
+ assign do_update_winp = winp_we_eprop & TARGET_VALID_sync;
863
+ assign do_update_wrec = wrec_we_eprop & TARGET_VALID_sync;
864
+ assign do_update_wregi = winp_we_eprop & |SPI_REGUL_MODE & SPI_REGUL_W[0];
865
+ assign do_update_wregr = wrec_we_eprop & |SPI_REGUL_MODE & SPI_REGUL_W[1];
866
+ lfsr_winp_wrec lfsr_winp_0 (
867
+ .clk(CLK),
868
+ .rst(RST),
869
+ .en(winp_we_eprop),
870
+ .rst_val(25'h1),
871
+ .seed(SPI_SEED_INP),
872
+ .prog(PROG_SEED_INP_new),
873
+ .out(winp_rand)
874
+ );
875
+ lfsr_winp_wrec lfsr_wrec_0 (
876
+ .clk(CLK),
877
+ .rst(RST),
878
+ .en(wrec_we_eprop),
879
+ .rst_val(25'h0424242),
880
+ .seed(SPI_SEED_REC),
881
+ .prog(PROG_SEED_REC_new),
882
+ .out(wrec_rand)
883
+ );
884
+
885
+ generate
886
+ for (n=0; n<16; n=n+1) begin
887
+ assign winp_en[n] = do_update_winp & |neur_h[n];
888
+ assign wrec_en[n] = do_update_wrec & |neur_h[n];
889
+
890
+ assign prob_winp_e[n] = winp_en[n] ? (learning_signals[n] * $signed({1'b0,trace_inp_eprop}) * neur_h[n]) : $signed(32'd0);
891
+ assign prob_wrec_e[n] = wrec_en[n] ? (learning_signals[n] * $signed({1'b0,trace_rec_eprop}) * neur_h[n]) : $signed(32'd0);
892
+
893
+ assign prob_wregi[n] = (SPI_REGUL_MODE[1] & SPI_REGUL_W[0]) ? (($signed({20'b0,trace_reg[n]}) << SPI_REGUL_K_INP_P) >> SPI_REGUL_K_INP_R) : $signed(32'd0);
894
+ assign prob_wregr[n] = (SPI_REGUL_MODE[1] & SPI_REGUL_W[1]) ? (($signed({20'b0,trace_reg[n]}) << SPI_REGUL_K_REC_P) >> SPI_REGUL_K_REC_R) : $signed(32'd0);
895
+ assign prob_wregm[n] = (SPI_REGUL_MODE[0] & |SPI_REGUL_W ) ? (trace_reg[n] >> SPI_REGUL_K_MUL) : 12'd0;
896
+ assign prob_wregs[n] = (~SPI_REGUL_MODE[0] || ~|SPI_REGUL_W) ? $signed(6'd16) : ((|prob_wregm[n][11:4]) ? $signed(6'd0) : ($signed(6'd16) - $signed({2'b0,prob_wregm[n][3:0]})));
897
+
898
+ assign prob_winp_k[n] = prob_winp_e[n][31] ? (prob_winp_e[n] * $signed(6'd16)) : (prob_winp_e[n] * prob_wregs[n]);
899
+ assign prob_wrec_k[n] = prob_wrec_e[n][31] ? (prob_wrec_e[n] * $signed(6'd16)) : (prob_wrec_e[n] * prob_wregs[n]);
900
+
901
+ assign prob_winp_s[n] = $signed(prob_winp_k[n][35:4]) - prob_wregi[n];
902
+ assign prob_winp[n] = (~prob_winp_s[n][31] & prob_winp_k[n][31]) ? $signed(32'h80000000) : prob_winp_s[n];
903
+ assign prob_wrec_s[n] = $signed(prob_wrec_k[n][35:4]) - prob_wregr[n];
904
+ assign prob_wrec[n] = (~prob_wrec_s[n][31] & prob_wrec_k[n][31]) ? $signed(32'h80000000) : prob_wrec_s[n];
905
+
906
+ stoch_update #(
907
+ .WIDTH_IN(32),
908
+ .LR_IN(5)
909
+ ) stoch_update_winp (
910
+ .prob(prob_winp[n]),
911
+ .w_in(winp_data_o[8*n+7:8*n]),
912
+ .en(winp_en[n] | do_update_wregi),
913
+ .lr_r(SPI_LR_R_WINP),
914
+ .lr_p(SPI_LR_P_WINP),
915
+ .rnd(winp_rand[32*n+31:32*n]),
916
+ .w_out(winp_data_i_eprop[8*n+7:8*n]),
917
+ .mask(winp_mask_eprop[8*n+7:8*n])
918
+ );
919
+ stoch_update #(
920
+ .WIDTH_IN(32),
921
+ .LR_IN(5)
922
+ ) stoch_update_wrec (
923
+ .prob(prob_wrec[n]),
924
+ .w_in(wrec_data_o[8*n+7:8*n]),
925
+ .en(wrec_en[n] | do_update_wregr),
926
+ .lr_r(SPI_LR_R_WREC),
927
+ .lr_p(SPI_LR_P_WREC),
928
+ .rnd(wrec_rand[32*n+31:32*n]),
929
+ .w_out(wrec_data_i_eprop_temp[8*n+7:8*n]),
930
+ .mask(wrec_mask_eprop[8*n+7:8*n])
931
+ );
932
+ assign wrec_data_i_eprop[8*n+7:8*n] = ((wrec_addr_eprop[11:8] == wrec_addr_eprop[3:0]) && (n == wrec_addr_eprop[7:4])) ? 8'h00 : wrec_data_i_eprop_temp[8*n+7:8*n];
933
+ end
934
+ endgenerate
935
+
936
+ // Output weight update
937
+ assign do_update_wout = wout_we_eprop;
938
+ lfsr_wout lfsr_wout_0 (
939
+ .clk(CLK),
940
+ .rst(RST),
941
+ .en(do_update_wout),
942
+ .rst_val(22'h1),
943
+ .seed(SPI_SEED_OUT),
944
+ .prog(PROG_SEED_OUT_new),
945
+ .out(wout_rand)
946
+ );
947
+ generate
948
+ for (k=0; k<16; k=k+1) begin
949
+ assign prob_wout[k] = do_update_wout ? (oneur_err[k] * $signed({1'b0,trace_out_eprop})) : $signed(28'd0);
950
+ stoch_update #(
951
+ .WIDTH_IN(28),
952
+ .LR_IN(5)
953
+ ) stoch_update_wout (
954
+ .prob(prob_wout[k]),
955
+ .w_in(wout_data_o[8*k+7:8*k]),
956
+ .en(do_update_wout),
957
+ .lr_r(SPI_LR_R_WOUT),
958
+ .lr_p(SPI_LR_P_WOUT),
959
+ .rnd(wout_rand[28*k+27:28*k]),
960
+ .w_out(wout_data_i_eprop[8*k+7:8*k]),
961
+ .mask(wout_mask_eprop[8*k+7:8*k])
962
+ );
963
+ end
964
+ endgenerate
965
+
966
+
967
+ //----------------------------------------------------------------------------------
968
+ // Event controller (FSM, input-driven)
969
+ //----------------------------------------------------------------------------------
970
+
971
+ // State register
972
+ always @(posedge CLK, posedge RST)
973
+ begin
974
+ if (RST) state_evt <= WAIT;
975
+ else state_evt <= nextstate_evt;
976
+ end
977
+
978
+ // Next state logic
979
+ always @(*)
980
+ case(state_evt)
981
+ WAIT : if ((state != PROP) && (nextstate == PROP)) nextstate_evt = CNT;
982
+ else nextstate_evt = WAIT;
983
+ CNT : if (neur_z[neur256_cnt] || inp_event) nextstate_evt = EVT;
984
+ else if (neur256_cnt == SPI_NUM_NEUR) nextstate_evt = WAIT;
985
+ else nextstate_evt = CNT;
986
+ EVT : if ((neur128x2_cnt[M-1:1] == SPI_NUM_REC_NEUR[M-1:1]) && neur128x2_cnt[0] && (neur256_cnt == SPI_NUM_NEUR))
987
+ if (supp_cond) nextstate_evt = SUPP;
988
+ else nextstate_evt = WAIT;
989
+ else if ((neur128x2_cnt[M-1:1] == SPI_NUM_REC_NEUR[M-1:1]) && neur128x2_cnt[0])
990
+ if (supp_cond) nextstate_evt = SUPP;
991
+ else nextstate_evt = CNT;
992
+ else nextstate_evt = EVT;
993
+ SUPP : if (supp_cycle && (neur256_cnt == SPI_NUM_NEUR)) nextstate_evt = WAIT;
994
+ else if (supp_cycle) nextstate_evt = CNT;
995
+ else nextstate_evt = SUPP;
996
+ default: nextstate_evt = WAIT;
997
+ endcase
998
+
999
+
1000
+ // Output logic
1001
+ assign inp_event = inp_events[neur256_cnt];
1002
+ assign inp_evt_trace = ((state_evt == EVT) || (state_evt == SUPP)) & inp_event & (neur_addr_ctrl == neur256_cnt[M-1:1]) & (SPI_DO_EPROP[0] | SPI_FORCE_TRACES);
1003
+ assign rec_evt_trace = (state_evt == EVT) & neur_z[neur256_cnt] & (neur_addr_ctrl == neur256_cnt[M-1:1]) & (SPI_DO_EPROP[1] | SPI_FORCE_TRACES);
1004
+ assign out_evt_trace = (state_evt == EVT) & neur_z[neur256_cnt] & (neur_addr_ctrl == neur256_cnt[M-1:1]) & (SPI_DO_EPROP[2] | SPI_FORCE_TRACES);
1005
+ assign winp_cs_ctrl = (state_evt == EVT) & ~|neur128x2_cnt[3:0] & inp_event;
1006
+ assign wrec_cs_ctrl = (state_evt == EVT) & ~|neur128x2_cnt[3:0] & neur_z[neur256_cnt];
1007
+ assign winp_addr_ctrl = {neur256_cnt,neur128x2_cnt[M-1:4]};
1008
+ assign wrec_addr_ctrl = {neur256_cnt,neur128x2_cnt[M-1:4]};
1009
+ assign wout_cs_ctrl = (state_evt == CNT) & (nextstate_evt == EVT) & neur_z[neur256_cnt];
1010
+ assign wout_addr_ctrl = {1'b0,neur256_cnt};
1011
+ assign supp_cond = inp_event & (neur256_cnt > SPI_NUM_REC_NEUR) & (SPI_DO_EPROP[0] | SPI_FORCE_TRACES);
1012
+ always @(posedge CLK)
1013
+ wout_cs_del <= wout_cs_ctrl;
1014
+ always @(posedge CLK)
1015
+ supp_cycle <= (state_evt == SUPP);
1016
+
1017
+ // Control
1018
+ always @(posedge CLK)
1019
+ if (nextstate_evt != EVT)
1020
+ neur128x2_cnt <= 'd0;
1021
+ else if (state_evt == EVT)
1022
+ neur128x2_cnt <= neur128x2_cnt + 'd1;
1023
+ always @(posedge CLK)
1024
+ if (state_evt == WAIT)
1025
+ neur256_cnt <= 'd0;
1026
+ else if (nextstate_evt == CNT)
1027
+ neur256_cnt <= neur256_cnt + 'd1;
1028
+
1029
+
1030
+ //----------------------------------------------------------------------------------
1031
+ // Neuron array and update computation
1032
+ //----------------------------------------------------------------------------------
1033
+
1034
+ assign neur_cs_ctrl = (state_evt == EVT) | (state_evt == SUPP) | (state == STEP);
1035
+ assign neur_we_ctrl = neur128x2_cnt[0] | supp_cycle | neur_step_cnt[0];
1036
+ assign neur_addr_ctrl = (state_evt == EVT) ? neur128x2_cnt[M-1:1] : ((state_evt == SUPP) ? neur256_cnt[M-1:1] : neur_step_cnt[M-1:1]);
1037
+
1038
+ generate
1039
+ for (n=0; n<2; n=n+1)
1040
+ always @(*) begin
1041
+ // Input encoding
1042
+ neur_data_i_ctrl[50*n+15:50*n+ 0] = (state_evt == EVT) ? neur_u_next[n][15:0] : neur_u_step[n][15:0]; // Membrane potential
1043
+ neur_mask_ctrl[ 50*n+15:50*n+ 0] = {16{neur_we_ctrl & ~supp_cycle}};
1044
+ neur_data_i_ctrl[50*n+27:50*n+16] = trace_inp_next[n]; // Input traces
1045
+ neur_mask_ctrl[ 50*n+27:50*n+16] = {12{neur_we_ctrl & ( ((inp_evt_trace & (n[0] == neur256_cnt[0])) | !neur_dirty[(neur_addr_ctrl << 1)+n])
1046
+ | neur_step_cnt[0])}};
1047
+ neur_data_i_ctrl[50*n+39:50*n+28] = trace_rec_next[n]; // Recurrent traces
1048
+ neur_mask_ctrl[ 50*n+39:50*n+28] = {12{neur_we_ctrl & ( ((rec_evt_trace & (n[0] == neur256_cnt[0])) | !neur_dirty[(neur_addr_ctrl << 1)+n])
1049
+ | neur_step_cnt[0])}};
1050
+ neur_data_i_ctrl[50*n+49:50*n+40] = trace_out_next[n]; // Output traces
1051
+ neur_mask_ctrl[ 50*n+49:50*n+40] = {10{neur_we_ctrl & ( ((out_evt_trace & (n[0] == neur256_cnt[0])) | !neur_dirty[(neur_addr_ctrl << 1)+n])
1052
+ | neur_step_cnt[0])}};
1053
+
1054
+ neur_data_i_ctrl[14*n+113:14*n+100] = 14'b0;
1055
+ neur_mask_ctrl[ 14*n+113:14*n+100] = 14'b0;
1056
+ // Output decoding
1057
+ neur_u[n] = neur_dirty[(neur_addr_ctrl << 1)+n] ? $signed(neur_data_o[50*n+15:50*n+ 0]) : $signed(16'd0);
1058
+ trace_inp[n] = neur_dirty[(neur_addr_ctrl << 1)+n] ? neur_data_o[50*n+27:50*n+16] : 12'd0 ;
1059
+ trace_rec[n] = neur_dirty[(neur_addr_ctrl << 1)+n] ? neur_data_o[50*n+39:50*n+28] : 12'd0 ;
1060
+ trace_out[n] = neur_dirty[(neur_addr_ctrl << 1)+n] ? neur_data_o[50*n+49:50*n+40] : 10'd0 ;
1061
+ end
1062
+ endgenerate
1063
+ assign alpha_msb = SPI_ALPHA_CONF[neur_addr_ctrl] ? 4'h8 : 4'h7;
1064
+ assign alpha = { alpha_msb,neur_data_o[127:116]} ;
1065
+ assign alpha_s = $signed({1'b0,alpha_msb,neur_data_o[127:116]});
1066
+ assign thr = $signed(neur_data_o[115:100]);
1067
+
1068
+
1069
+ // Hidden neurons
1070
+ assign shift_winp = winp_data_o >> ({4'b0,neur128x2_cnt[3:1]}<<4);
1071
+ assign shift_wrec = wrec_data_o >> ({4'b0,neur128x2_cnt[3:1]}<<4);
1072
+ lfsr_noise_neur lfsr_noise_neur (
1073
+ .clk(CLK),
1074
+ .rst(RST),
1075
+ .en(SPI_NOISE_EN & (state == PROP) & neur128x2_cnt[0]),
1076
+ .rst_val(17'h1F0F1),
1077
+ .seed(SPI_SEED_NOISE_NEUR),
1078
+ .prog(PROG_SEED_NOISE_NEUR_new),
1079
+ .out(neur_noise_rand)
1080
+ );
1081
+ generate
1082
+ for (n=0; n<2; n=n+1) begin
1083
+ always @(*) begin
1084
+ update_winp[n] = (neur128x2_cnt[0] && inp_event ) ? ($signed({{8{shift_winp[n*8+7]}},shift_winp[n*8+7:n*8]})<<SPI_FP_LOC_WINP) : $signed(16'd0);
1085
+ update_wrec[n] = (neur128x2_cnt[0] && neur_z[neur256_cnt]) ? ($signed({{8{shift_wrec[n*8+7]}},shift_wrec[n*8+7:n*8]})<<SPI_FP_LOC_WREC) : $signed(16'd0);
1086
+ update_wt[n] = update_wrec[n] + update_winp[n];
1087
+ update_w[n] = ( update_wt[n][15] & ~update_wrec[n][15] & ~update_winp[n][15]) ? $signed(16'h7FFF) :
1088
+ ((~update_wt[n][15] & update_wrec[n][15] & update_winp[n][15]) ? $signed(16'h8000) :
1089
+ update_wt[n]);
1090
+ update_u[n] = neur_u[n] + update_w[n] + (SPI_NOISE_EN ? ($signed(neur_noise_rand[n*16+15:n*16]) >>> SPI_NOISE_STR) : $signed(16'd0));
1091
+ ovfl_p[n] = ~neur_u[n][15] & ~update_w[n][15] & update_u[n][15];
1092
+ ovfl_n[n] = neur_u[n][15] & update_w[n][15] & ~update_u[n][15];
1093
+ neur_u_next[n] = ovfl_p[n] ? $signed(16'h7FFF) : (ovfl_n[n] ? $signed(16'h8000) : update_u[n]);
1094
+ end
1095
+ lfsr_neur_stochround lfsr_strnd_neur_u (
1096
+ .clk(CLK),
1097
+ .rst(RST),
1098
+ .en(SPI_EN_STOCH_ROUND & (state == STEP) & neur_step_cnt[0] & (alpha != 16'h8000)),
1099
+ .rst_val(n ? 15'h70F0 : 15'h1234),
1100
+ .seed(SPI_SEED_STRND_NEUR[15*n+14:15*n]),
1101
+ .prog(PROG_SEED_STRND_NEUR_new),
1102
+ .out(neur_u_leak_rand[n])
1103
+ );
1104
+ always @(*) begin
1105
+ neur_u_leak[n] = ((state == STEP) && neur_step_cnt[0]) ? (neur_u[n]*alpha_s) : $signed(32'd0);
1106
+ neur_u_stoc[n] = (SPI_EN_STOCH_ROUND && (alpha != 16'h8000) && (neur_u_leak[n][14:0] >= neur_u_leak_rand[n]) && |neur_u_leak[n][30:15]) ? $signed(16'd1) : $signed(16'd0); //more cropped ones --> more probability to increment (for both pos. and neg.)
1107
+ neur_u_lkst[n] = $signed(neur_u_leak[n][30:15]) + neur_u_stoc[n];
1108
+ neur_u_spk[n] = ((state == STEP) && neur_step_cnt[0]) & (neur_u[n] >= thr);
1109
+ neur_u_step[n] = ((state == STEP) && neur_step_cnt[0]) ? (neur_u_spk[n] ? (SPI_RST_MODE ? $signed(16'd0) : (neur_u_lkst[n]-thr)) : neur_u_lkst[n]) : $signed(16'd0);
1110
+ end
1111
+ end
1112
+ endgenerate
1113
+ generate
1114
+ for (j=0; j<N; j=j+1) begin
1115
+ always @(posedge CLK)
1116
+ if (RST || ((state != IDLE) && (nextstate == IDLE)))
1117
+ neur_z[j] <= 1'b0;
1118
+ else if (PROG_NEUR_new && SPI_ADDR[9] && (j == SPI_ADDR[M-1:0]))
1119
+ neur_z[j] <= SPI_DATA[0];
1120
+ else if ((state == STEP) && (j[M-1:1] == neur_step_cnt[M-1:1]))
1121
+ neur_z[j] <= neur_u_spk[j[0]];
1122
+ else if (neur_cs_ctrl && neur_we_ctrl && ((state_evt == EVT) || (state_evt == SUPP)) && ((nextstate_evt == CNT) || (nextstate_evt == WAIT)) && (j[7:0] == neur256_cnt))
1123
+ neur_z[j] <= 1'b0;
1124
+ always @(posedge CLK)
1125
+ if (RST || ((state != IDLE) && (nextstate == IDLE)))
1126
+ neur_dirty[j] <= 1'b0;
1127
+ else if (PROG_NEUR_new && SPI_ADDR[9] && (j == SPI_ADDR[M-1:0]))
1128
+ neur_dirty[j] <= SPI_DATA[1];
1129
+ else if (neur_cs && neur_we && (j[M-1:1] == neur_addr))
1130
+ neur_dirty[j] <= 1'b1;
1131
+ end
1132
+ endgenerate
1133
+
1134
+
1135
+ // Output neurons
1136
+ lfsr_oneur_stochround lfsr_strnd_oneur_u (
1137
+ .clk(CLK),
1138
+ .rst(RST),
1139
+ .en(SPI_EN_STOCH_ROUND & (state == STEP) & (SPI_KAPPA != 8'h80) & ~|neur_step_cnt[M-1:4]),
1140
+ .rst_val(15'h7ABA),
1141
+ .seed(SPI_SEED_STRND_ONEUR),
1142
+ .prog(PROG_SEED_STRND_ONEUR_new),
1143
+ .out(oneur_u_leak_rand)
1144
+ );
1145
+ generate
1146
+ for (k=0; k<16; k=k+1)
1147
+ always @(*) begin
1148
+ update_wout[k] = wout_cs_del ? ($signed({{8{wout_data_o[k*8+7]}},wout_data_o[k*8+7:k*8]})<<SPI_FP_LOC_WOUT) : $signed(16'd0);
1149
+ update_out[k] = oneur_u[k] + update_wout[k];
1150
+ ovfl_out_p[k] = ~oneur_u[k][15] & ~update_wout[k][15] & update_out[k][15];
1151
+ ovfl_out_n[k] = oneur_u[k][15] & update_wout[k][15] & ~update_out[k][15];
1152
+ oneur_out_next[k] = ovfl_out_p[k] ? $signed(16'h7FFF) : (ovfl_out_n[k] ? $signed(16'h8000) : update_out[k]);
1153
+ end
1154
+ endgenerate
1155
+ assign oneur_u_leak = ((state == STEP) && ~|neur_step_cnt[M-1:4]) ? (oneur_u[neur_step_cnt[3:0]]*$signed({1'b0,SPI_KAPPA})) : $signed(24'd0);
1156
+ assign oneur_u_stoc = (SPI_EN_STOCH_ROUND && (SPI_KAPPA != 8'h80) && (oneur_u_leak[6:0] >= oneur_u_leak_rand) && |oneur_u_leak[22:7]) ? $signed(16'd1) : $signed(16'd0); //more cropped ones --> more probability to increment (for both pos. and neg.)
1157
+ assign oneur_u_lkst = $signed(oneur_u_leak[22:7]) + oneur_u_stoc;
1158
+ generate
1159
+ for (k=0; k<16; k=k+1)
1160
+ always @(posedge CLK)
1161
+ if (RST || ((state != IDLE) && (nextstate == IDLE)))
1162
+ oneur_u[k] <= $signed(16'd0);
1163
+ else if (PROG_ONEUR_new && (k == SPI_ADDR[3:0]))
1164
+ oneur_u[k] <= SPI_DATA[15:0];
1165
+ else if (k <= SPI_NUM_OUT_NEUR)
1166
+ if (wout_cs_del)
1167
+ oneur_u[k] <= oneur_out_next[k];
1168
+ else if ((state == STEP) && (k == neur_step_cnt[3:0]) && ~|neur_step_cnt[M-1:4])
1169
+ oneur_u[k] <= oneur_u_lkst;
1170
+ endgenerate
1171
+
1172
+
1173
+ // Hardsigmoid activation function and error computation if e-prop is enabled
1174
+ generate
1175
+ for (k=0; k<16; k=k+1)
1176
+ output_act_err output_act_err (
1177
+ .en(|SPI_DO_EPROP & TARGET_VALID_sync & (k <= SPI_NUM_OUT_NEUR)),
1178
+ .regr(SPI_REGRESSION),
1179
+ .act(~SPI_NO_OUT_ACT),
1180
+ .label(class_label==k[3:0]),
1181
+ .target(reg_tar[k]),
1182
+ .vo(oneur_u[k]),
1183
+ .e(oneur_err[k])
1184
+ );
1185
+ endgenerate
1186
+
1187
+
1188
+ // Input, recurrent and output trace update
1189
+ generate
1190
+ for (n=0; n<2; n=n+1) begin
1191
+ lfsr_neur_stochround lfsr_strnd_tinp (
1192
+ .clk(CLK),
1193
+ .rst(RST),
1194
+ .en(SPI_EN_STOCH_ROUND & (state == STEP) & neur_step_cnt[0]),
1195
+ .rst_val(n ? 15'h7FCF : 15'h1348),
1196
+ .seed(SPI_SEED_STRND_TINP[15*n+14:15*n]),
1197
+ .prog(PROG_SEED_STRND_TINP_new),
1198
+ .out(trace_inp_rand[n])
1199
+ );
1200
+ lfsr_neur_stochround lfsr_strnd_trec (
1201
+ .clk(CLK),
1202
+ .rst(RST),
1203
+ .en(SPI_EN_STOCH_ROUND & (state == STEP) & neur_step_cnt[0]),
1204
+ .rst_val(n ? 15'h7BEA : 15'h4321),
1205
+ .seed(SPI_SEED_STRND_TREC[15*n+14:15*n]),
1206
+ .prog(PROG_SEED_STRND_TREC_new),
1207
+ .out(trace_rec_rand[n])
1208
+ );
1209
+ lfsr_oneur_stochround lfsr_strnd_tout (
1210
+ .clk(CLK),
1211
+ .rst(RST),
1212
+ .en(SPI_EN_STOCH_ROUND & (state == STEP) & neur_step_cnt[0]),
1213
+ .rst_val(n ? 15'h7EF0 : 15'h3FF3),
1214
+ .seed(SPI_SEED_STRND_TOUT[15*n+14:15*n]),
1215
+ .prog(PROG_SEED_STRND_TOUT_new),
1216
+ .out(trace_out_rand[n])
1217
+ );
1218
+ always @(*) begin
1219
+ trace_inp_inc[n] = (inp_evt_trace & (n[0] == neur256_cnt[0])) ? (trace_inp[n] + (12'd8 << SPI_FP_LOC_TINP)) : 12'b0;
1220
+ trace_inp_step[n] = (state == STEP) ? (trace_inp[n]*alpha) : 28'b0;
1221
+ trace_inp_stoc[n] = (SPI_EN_STOCH_ROUND && (alpha != 16'h8000) && (trace_inp_step[n][14:0] >= trace_inp_rand[n]) && |trace_inp_step[n][26:15]) ? 12'd1 : 12'd0; //more cropped ones --> more probability to increment (for both pos. and neg.)
1222
+ trace_inp_lkst[n] = trace_inp_step[n][26:15] + trace_inp_stoc[n];
1223
+ trace_inp_next[n] = (inp_evt_trace & (n[0] == neur256_cnt[0])) ? ((trace_inp_inc[n] < trace_inp[n]) ? 12'hFFF : trace_inp_inc[n])
1224
+ : ((state == STEP) ? trace_inp_lkst[n] : trace_inp[n]);
1225
+ trace_rec_inc[n] = (rec_evt_trace & (n[0] == neur256_cnt[0])) ? (trace_rec[n] + (12'd8 << SPI_FP_LOC_TREC)) : 12'b0;
1226
+ trace_rec_step[n] = (state == STEP) ? (trace_rec[n]*alpha) : 28'b0;
1227
+ trace_rec_stoc[n] = (SPI_EN_STOCH_ROUND && (alpha != 16'h8000) && (trace_rec_step[n][14:0] >= trace_rec_rand[n]) && |trace_rec_step[n][26:15]) ? 12'd1 : 12'd0; //more cropped ones --> more probability to increment (for both pos. and neg.)
1228
+ trace_rec_lkst[n] = trace_rec_step[n][26:15] + trace_rec_stoc[n];
1229
+ trace_rec_next[n] = (rec_evt_trace & (n[0] == neur256_cnt[0])) ? ((trace_rec_inc[n] < trace_rec[n]) ? 12'hFFF : trace_rec_inc[n])
1230
+ : ((state == STEP) ? trace_rec_lkst[n] : trace_rec[n]);
1231
+ trace_out_inc[n] = (out_evt_trace & (n[0] == neur256_cnt[0])) ? (trace_out[n] + (10'd2 << SPI_FP_LOC_TOUT)) : 10'b0;
1232
+ trace_out_step[n] = (state == STEP) ? (trace_out[n]*SPI_KAPPA) : 18'b0;
1233
+ trace_out_stoc[n] = (SPI_EN_STOCH_ROUND && (SPI_KAPPA != 8'h80) && (trace_out_step[n][6:0] >= trace_out_rand[n]) && |trace_out_step[n][16:7]) ? 10'd1 : 10'd0; //more cropped ones --> more probability to increment (for both pos. and neg.)
1234
+ trace_out_lkst[n] = trace_out_step[n][16:7] + trace_out_stoc[n];
1235
+ trace_out_next[n] = (out_evt_trace & (n[0] == neur256_cnt[0])) ? ((trace_out_inc[n] < trace_out[n]) ? 10'h3FF : trace_out_inc[n])
1236
+ : ((state == STEP) ? trace_out_lkst[n] : trace_out[n]);
1237
+ end
1238
+ end
1239
+ endgenerate
1240
+
1241
+
1242
+ //----------------------------------------------------------------------------------
1243
+ // SRAMs
1244
+ //----------------------------------------------------------------------------------
1245
+
1246
+ // Neuron SRAM
1247
+ SRAM_128x128_wrapper neurons (
1248
+ // Global inputs
1249
+ .CK (CLK),
1250
+ .SM (SPI_SRAM_SPEEDMODE[7:6]),
1251
+ // Control and data inputs
1252
+ .CS (neur_cs),
1253
+ .WE (neur_we),
1254
+ .A (neur_addr),
1255
+ .D (neur_data_i),
1256
+ .M (neur_mask),
1257
+ // Data output
1258
+ .Q (neur_data_o)
1259
+ );
1260
+ assign neur_cs = PROG_NEUR_new ? 1'b1 : (READ_NEUR_sync ? 1'b1 : ((state==EPROP) ? neur_cs_eprop : neur_cs_ctrl ));
1261
+ assign neur_we = PROG_NEUR_new ? 1'b1 : (READ_NEUR_sync ? 1'b0 : neur_we_ctrl );
1262
+ assign neur_addr = PROG_NEUR_new ? SPI_ADDR[ 8:2] : (READ_NEUR_sync ? SPI_ADDR[ 8:2] : ((state==EPROP) ? neur_addr_eprop : neur_addr_ctrl ));
1263
+ assign neur_data_i = PROG_NEUR_new ? ({96'b0,SPI_DATA[31:0]} << ({5'b0,SPI_ADDR[1:0]}<<5)) : neur_data_i_ctrl ;
1264
+ assign neur_mask = PROG_NEUR_new ? ({96'b0,32'hFFFFFFFF } << ({5'b0,SPI_ADDR[1:0]}<<5)) : neur_mask_ctrl ;
1265
+
1266
+ // Input weights SRAM
1267
+ SRAM_4096x128_wrapper weights_inp (
1268
+ // Global inputs
1269
+ .CK (CLK),
1270
+ .SM (SPI_SRAM_SPEEDMODE[5:4]),
1271
+ // Control and data inputs
1272
+ .CS (winp_cs),
1273
+ .WE (winp_we),
1274
+ .A (winp_addr),
1275
+ .D (winp_data_i),
1276
+ .M (winp_mask),
1277
+ // Data output
1278
+ .Q (winp_data_o)
1279
+ );
1280
+ assign winp_cs = PROG_WINP_new ? 1'b1 : (READ_WINP_sync ? 1'b1 : ((state==EPROP) ? winp_cs_eprop : winp_cs_ctrl ));
1281
+ assign winp_we = PROG_WINP_new ? 1'b1 : (READ_WINP_sync ? 1'b0 : winp_we_eprop );
1282
+ assign winp_addr = PROG_WINP_new ? SPI_ADDR[13:2] : (READ_WINP_sync ? SPI_ADDR[13:2] : ((state==EPROP) ? winp_addr_eprop : winp_addr_ctrl ));
1283
+ assign winp_data_i = PROG_WINP_new ? ({96'b0,SPI_DATA[31:0]} << ({5'b0,SPI_ADDR[1:0]} << 5)) : winp_data_i_eprop ;
1284
+ assign winp_mask = PROG_WINP_new ? ({96'b0,32'hFFFFFFFF } << ({5'b0,SPI_ADDR[1:0]} << 5)) : winp_mask_eprop ;
1285
+
1286
+ // Recurrent weights SRAM
1287
+ SRAM_4096x128_wrapper weights_rec (
1288
+ // Global inputs
1289
+ .CK (CLK),
1290
+ .SM (SPI_SRAM_SPEEDMODE[3:2]),
1291
+ // Control and data inputs
1292
+ .CS (wrec_cs),
1293
+ .WE (wrec_we),
1294
+ .A (wrec_addr),
1295
+ .D (wrec_data_i),
1296
+ .M (wrec_mask),
1297
+ // Data output
1298
+ .Q (wrec_data_o)
1299
+ );
1300
+ assign wrec_cs = PROG_WREC_new ? 1'b1 : (READ_WREC_sync ? 1'b1 : ((state==EPROP) ? wrec_cs_eprop : wrec_cs_ctrl ));
1301
+ assign wrec_we = PROG_WREC_new ? 1'b1 : (READ_WREC_sync ? 1'b0 : wrec_we_eprop );
1302
+ assign wrec_addr = PROG_WREC_new ? SPI_ADDR[13:2] : (READ_WREC_sync ? SPI_ADDR[13:2] : ((state==EPROP) ? wrec_addr_eprop : wrec_addr_ctrl ));
1303
+ assign wrec_data_i = PROG_WREC_new ? ({96'b0,SPI_DATA[31:0]} << ({5'b0,SPI_ADDR[1:0]} << 5)) : wrec_data_i_eprop ;
1304
+ assign wrec_mask = PROG_WREC_new ? ({96'b0,32'hFFFFFFFF } << ({5'b0,SPI_ADDR[1:0]} << 5)) : wrec_mask_eprop ;
1305
+
1306
+ // Output weights SRAM
1307
+ SRAM_512x128_wrapper weights_out (
1308
+ // Global inputs
1309
+ .CK (CLK),
1310
+ .SM (SPI_SRAM_SPEEDMODE[1:0]),
1311
+ // Control and data inputs
1312
+ .CS (wout_cs),
1313
+ .WE (wout_we),
1314
+ .A (wout_addr),
1315
+ .D (wout_data_i),
1316
+ .M (wout_mask),
1317
+ // Data output
1318
+ .Q (wout_data_o)
1319
+ );
1320
+ assign wout_cs = PROG_WOUT_new ? 1'b1 : (READ_WOUT_sync ? 1'b1 : ((state==EPROP) ? wout_cs_eprop : wout_cs_ctrl ));
1321
+ assign wout_we = PROG_WOUT_new ? 1'b1 : (READ_WOUT_sync ? 1'b0 : wout_we_eprop );
1322
+ assign wout_addr = PROG_WOUT_new ? SPI_ADDR[10:2] : (READ_WOUT_sync ? SPI_ADDR[10:2] : ((state==EPROP) ? wout_addr_eprop : wout_addr_ctrl ));
1323
+ assign wout_data_i = PROG_WOUT_new ? ({96'b0,SPI_DATA[31:0]} << ({5'b0,SPI_ADDR[1:0]}<<5)) : wout_data_i_eprop ;
1324
+ assign wout_mask = PROG_WOUT_new ? ({96'b0,32'hFFFFFFFF } << ({5'b0,SPI_ADDR[1:0]}<<5)) : wout_mask_eprop ;
1325
+
1326
+
1327
+ //----------------------------------------------------------------------------------
1328
+ // Winner computation
1329
+ //----------------------------------------------------------------------------------
1330
+
1331
+ // Identifying winner neuron
1332
+ always @(*) begin
1333
+ if (!SPI_REGRESSION && INFER_ACC_sync && (state == SDONE)) begin
1334
+ neur_winner[0] = oneur_u[0];
1335
+ label_winner[0] = 4'd0;
1336
+ for (kk=1; kk<16; kk=kk+1)
1337
+ if ((kk <= SPI_NUM_OUT_NEUR) && (oneur_u[kk] > neur_winner[kk-1])) begin
1338
+ neur_winner[kk] = oneur_u[kk];
1339
+ label_winner[kk] = kk[3:0];
1340
+ end else begin
1341
+ neur_winner[kk] = neur_winner[kk-1];
1342
+ label_winner[kk] = label_winner[kk-1];
1343
+ end
1344
+ end else begin
1345
+ for (kk=0; kk<16; kk=kk+1) begin
1346
+ neur_winner[kk] = 16'b0;
1347
+ label_winner[kk] = 4'b0;
1348
+ end
1349
+ end
1350
+ end
1351
+ generate
1352
+ for (k=0; k<16; k=k+1)
1353
+ always @(posedge CLK)
1354
+ if (state == IDLE)
1355
+ cnt_winner[k] <= 16'b0;
1356
+ else if ((k <= SPI_NUM_OUT_NEUR) && INFER_ACC_sync && (state == SDONE) && (k[3:0] == label_winner[15]))
1357
+ cnt_winner[k] <= cnt_winner[k] + 16'd1;
1358
+ endgenerate
1359
+ always @(*) begin
1360
+ if (!SPI_REGRESSION && (state==SEND)) begin
1361
+ aer_winner[0] = cnt_winner[0];
1362
+ send_winner[0] = 4'd0;
1363
+ for (kk=1; kk<16; kk=kk+1)
1364
+ if ((kk <= SPI_NUM_OUT_NEUR) && (cnt_winner[kk] > aer_winner[kk-1])) begin
1365
+ aer_winner[kk] = cnt_winner[kk];
1366
+ send_winner[kk] = kk[3:0];
1367
+ end else begin
1368
+ aer_winner[kk] = aer_winner[kk-1];
1369
+ send_winner[kk] = send_winner[kk-1];
1370
+ end
1371
+ end else begin
1372
+ for (kk=0; kk<16; kk=kk+1) begin
1373
+ aer_winner[kk] = 16'b0;
1374
+ send_winner[kk] = 4'b0;
1375
+ end
1376
+ end
1377
+ end
1378
+
1379
+
1380
+ //----------------------------------------------------------------------------------
1381
+ // Readback
1382
+ //----------------------------------------------------------------------------------
1383
+
1384
+ assign winp_data_o_shift = winp_data_o >> ({5'b0,SPI_ADDR[1:0]}<<5);
1385
+ assign wrec_data_o_shift = wrec_data_o >> ({5'b0,SPI_ADDR[1:0]}<<5);
1386
+ assign wout_data_o_shift = wout_data_o >> ({5'b0,SPI_ADDR[1:0]}<<5);
1387
+ assign neur_data_o_shift = neur_data_o >> ({5'b0,SPI_ADDR[1:0]}<<5);
1388
+
1389
+ always @(posedge CLK)
1390
+ if (READ_NEUR_sync)
1391
+ SRNN_READBACK <= neur_data_o_shift[31:0];
1392
+ else if (READ_ONEUR_sync)
1393
+ SRNN_READBACK <= {16'd0,oneur_u[SPI_ADDR[3:0]]};
1394
+ else if (READ_WINP_sync)
1395
+ SRNN_READBACK <= winp_data_o_shift[31:0];
1396
+ else if (READ_WREC_sync)
1397
+ SRNN_READBACK <= wrec_data_o_shift[31:0];
1398
+ else if (READ_WOUT_sync)
1399
+ SRNN_READBACK <= wout_data_o_shift[31:0];
1400
+
1401
+
1402
+ endmodule
1403
+
1404
+
1405
+
1406
+
1407
+ module SRAM_4096x128_wrapper (
1408
+
1409
+ // Global inputs
1410
+ input CK, // Clock (synchronous read/write)
1411
+ input [ 1:0] SM, // Speed mode
1412
+
1413
+ // Control and data inputs
1414
+ input CS, // Chip select (active high)
1415
+ input WE, // Write enable (active high)
1416
+ input [ 11:0] A, // Address bus
1417
+ input [127:0] D, // Data input bus (write)
1418
+ input [127:0] M, // Mask bus (write, 1=overwrite)
1419
+
1420
+ // Data output
1421
+ output [127:0] Q // Data output bus (read)
1422
+ );
1423
+
1424
+ `ifdef SRAM_BEHAV
1425
+ // Simple behavioral code for simulation, to be replaced by a 4096-word 128-bit SRAM macro
1426
+ // or Block RAM (BRAM) memory with the same format for FPGA implementations.
1427
+ reg [127:0] SRAM[4095:0];
1428
+ reg [127:0] Qr;
1429
+ always @(posedge CK) begin
1430
+ Qr <= CS ? SRAM[A] : Qr;
1431
+ if (CS & WE) SRAM[A] <= (D & M) | (SRAM[A] & ~M);
1432
+ end
1433
+ assign Q = Qr;
1434
+ `else
1435
+
1436
+ // //
1437
+ // SRAM macro instantiation goes here //
1438
+ // (technology-specific cells/macros have been removed) //
1439
+ // //
1440
+
1441
+ `endif
1442
+
1443
+ endmodule
1444
+
1445
+ module SRAM_512x128_wrapper (
1446
+
1447
+ // Global inputs
1448
+ input CK, // Clock (synchronous read/write)
1449
+ input [ 1:0] SM, // Speed mode
1450
+
1451
+ // Control and data inputs
1452
+ input CS, // Chip select (active high)
1453
+ input WE, // Write enable (active high)
1454
+ input [ 8:0] A, // Address bus
1455
+ input [127:0] D, // Data input bus (write)
1456
+ input [127:0] M, // Mask bus (write, 1=overwrite)
1457
+
1458
+ // Data output
1459
+ output [127:0] Q // Data output bus (read)
1460
+ );
1461
+
1462
+ `ifdef SRAM_BEHAV
1463
+ // Simple behavioral code for simulation, to be replaced by a 512-word 128-bit SRAM macro
1464
+ // or Block RAM (BRAM) memory with the same format for FPGA implementations.
1465
+ reg [127:0] SRAM[511:0];
1466
+ reg [127:0] Qr;
1467
+ always @(posedge CK) begin
1468
+ Qr <= CS ? SRAM[A] : Qr;
1469
+ if (CS & WE) SRAM[A] <= (D & M) | (SRAM[A] & ~M);
1470
+ end
1471
+ assign Q = Qr;
1472
+ `else
1473
+
1474
+ // //
1475
+ // SRAM macro instantiation goes here //
1476
+ // (technology-specific cells/macros have been removed) //
1477
+ // //
1478
+
1479
+ `endif
1480
+
1481
+ endmodule
1482
+
1483
+ module SRAM_128x128_wrapper (
1484
+
1485
+ // Global inputs
1486
+ input CK, // Clock (synchronous read/write)
1487
+ input [ 1:0] SM, // Speed mode
1488
+
1489
+ // Control and data inputs
1490
+ input CS, // Chip select (active high)
1491
+ input WE, // Write enable (active high)
1492
+ input [ 6:0] A, // Address bus
1493
+ input [127:0] D, // Data input bus (write)
1494
+ input [127:0] M, // Mask bus (write, 1=overwrite)
1495
+
1496
+ // Data output
1497
+ output [127:0] Q // Data output bus (read)
1498
+ );
1499
+
1500
+ `ifdef SRAM_BEHAV
1501
+ // Simple behavioral code for simulation, to be replaced by a 128-word 128-bit SRAM macro
1502
+ // or Block RAM (BRAM) memory with the same format for FPGA implementations.
1503
+ reg [127:0] SRAM[127:0];
1504
+ reg [127:0] Qr;
1505
+ always @(posedge CK) begin
1506
+ Qr <= CS ? SRAM[A] : Qr;
1507
+ if (CS & WE) SRAM[A] <= (D & M) | (SRAM[A] & ~M);
1508
+ end
1509
+ assign Q = Qr;
1510
+ `else
1511
+
1512
+ // //
1513
+ // SRAM macro instantiation goes here //
1514
+ // (technology-specific cells/macros have been removed) //
1515
+ // //
1516
+
1517
+ `endif
1518
+
1519
+ endmodule
1520
+
1521
+
1522
+ module output_act_err (
1523
+ input wire en,
1524
+ input wire regr,
1525
+ input wire act,
1526
+ input wire label,
1527
+ input wire signed [15:0] target,
1528
+ input wire signed [15:0] vo,
1529
+ output wire signed [15:0] e
1530
+ );
1531
+ reg signed [15:0] yt;
1532
+ reg signed [15:0] y;
1533
+ wire signed [15:0] e_temp;
1534
+ wire ovfl_p, ovfl_n;
1535
+
1536
+ // Output
1537
+ always @(*)
1538
+ if (en)
1539
+ if (act)
1540
+ if (vo > $signed( 16'd2047))
1541
+ y = $signed(16'd2048);
1542
+ else if (vo < $signed(-16'd2048))
1543
+ y = $signed(16'd0);
1544
+ else
1545
+ y = $signed((vo + $signed(16'd2048)) >>> 1);
1546
+ else
1547
+ y = vo;
1548
+ else
1549
+ y = $signed(16'd0);
1550
+
1551
+ // Target
1552
+ always @(*)
1553
+ if (en)
1554
+ if (regr) // Regression
1555
+ yt = target;
1556
+ else // Classification
1557
+ yt = label ? $signed(16'd2048) : $signed(16'd0);
1558
+ else
1559
+ yt = $signed(16'd0);
1560
+
1561
+ // Error
1562
+ assign e_temp = yt - y;
1563
+ assign ovfl_p = ~yt[15] & y[15] & e_temp[15];
1564
+ assign ovfl_n = yt[15] & ~y[15] & ~e_temp[15];
1565
+ assign e = ovfl_p ? $signed(16'h7FFF) : (ovfl_n ? $signed(16'h8000) : e_temp);
1566
+
1567
+ endmodule
1568
+
1569
+
1570
+ module stoch_update #(
1571
+ parameter WIDTH_IN = 16,
1572
+ parameter LR_IN = 4
1573
+ )(
1574
+ input wire signed [WIDTH_IN-1:0] prob,
1575
+ input wire signed [ 7:0] w_in,
1576
+ input wire en,
1577
+ input wire [ LR_IN-1:0] lr_r,
1578
+ input wire [ LR_IN-1:0] lr_p,
1579
+ input wire [WIDTH_IN-1:0] rnd,
1580
+ output wire signed [ 7:0] w_out,
1581
+ output wire [ 7:0] mask
1582
+ );
1583
+ wire prob_0, prob_m, prob_ovfl;
1584
+ wire update;
1585
+ wire overflow;
1586
+ wire no_change;
1587
+ wire signed [ 7:0] w_updated;
1588
+ wire [WIDTH_IN-1:0] prob_abs, prob_tot;
1589
+ wire [WIDTH_IN+(1<<LR_IN)-1:0] prob_lrp;
1590
+
1591
+ assign prob_0 = (prob == 'd0) | ~en;
1592
+ assign prob_m = (~|prob[WIDTH_IN-2:0] & prob[WIDTH_IN-1]);
1593
+ assign prob_abs = prob_0 ? 'd0 : (prob[WIDTH_IN-1] ? {$signed(~prob)+$signed('d1)} : prob);
1594
+ assign prob_lrp = {{(1<<LR_IN){1'b0}},prob_abs} << lr_p;
1595
+ assign prob_ovfl = |prob_lrp[WIDTH_IN+(1<<LR_IN)-1:WIDTH_IN];
1596
+ assign prob_tot = (prob_ovfl ? {WIDTH_IN{1'b1}} : prob_lrp[WIDTH_IN-1:0]) >> lr_r;
1597
+ assign update = prob_m | (prob_tot >= rnd);
1598
+
1599
+ assign no_change = prob_0 | ~update;
1600
+ assign w_updated = prob[WIDTH_IN-1] ? (w_in - $signed(8'd1)) : (w_in + $signed(8'd1));
1601
+ assign overflow = (w_in[7] & ~w_updated[7] & prob[WIDTH_IN-1]) | (~w_in[7] & w_updated[7] & ~prob[WIDTH_IN-1]);
1602
+ assign w_out = (no_change | overflow) ? w_in : w_updated;
1603
+ assign mask = {8{~no_change}};
1604
+
1605
+ endmodule
ChFrenkel_ReckOn/src/tbench.h ADDED
@@ -0,0 +1,96 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "tbench.h" - Testbench header with SPI parameters for fast-convergence delayed-supervision navigation task
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: -
25
+ //
26
+ //------------------------------------------------------------------------------
27
+
28
+ `define CLK_HALF_PERIOD 10
29
+ `define SCK_HALF_PERIOD 50
30
+
31
+ `define EPOCHS 10
32
+
33
+ `define SPI_RO_STAGE_SEL 9'b0
34
+ `define SPI_GET_CLKINT_OUT 1'b0
35
+
36
+ `define SPI_RST_MODE 1'b0
37
+ `define SPI_DO_EPROP 3'b000
38
+ `define SPI_LOCAL_TICK 1'b0
39
+ `define SPI_ERROR_HALT 1'b1
40
+ `define SPI_FP_LOC_WINP 3'b011
41
+ `define SPI_FP_LOC_WREC 3'b011
42
+ `define SPI_FP_LOC_WOUT 3'b011
43
+ `define SPI_FP_LOC_TINP 3'b011
44
+ `define SPI_FP_LOC_TREC 3'b100
45
+ `define SPI_FP_LOC_TOUT 3'b110
46
+ `define SPI_LEARN_SIG_SCALE 4'b0101
47
+ `define SPI_REGUL_MODE 3'b010
48
+ `define SPI_REGUL_W 2'b11
49
+ `define SPI_EN_STOCH_ROUND 1'b1
50
+ `define SPI_SRAM_SPEEDMODE 8'b00000000
51
+ `define SPI_TIMING_MODE 1'b0
52
+ `define SPI_REGRESSION 1'b0
53
+ `define SPI_SINGLE_LABEL 1'b1
54
+ `define SPI_NO_OUT_ACT 1'b0
55
+ `define SPI_SEND_PER_TIMESTEP 1'b0
56
+ `define SPI_SEND_LABEL_ONLY 1'b1
57
+ `define SPI_NOISE_EN 1'b0
58
+ `define SPI_FORCE_TRACES 1'b0
59
+
60
+ `define SPI_CYCLES_PER_TICK 32'b0
61
+ `define SPI_ALPHA_CONF 128'h0
62
+ `define SPI_KAPPA 8'h79
63
+ `define SPI_THR_H_0 $signed(16'd205)
64
+ `define SPI_THR_H_1 $signed(16'd205)
65
+ `define SPI_THR_H_2 $signed(16'd205)
66
+ `define SPI_THR_H_3 $signed(16'd205)
67
+ `define SPI_H_0 $signed(5'd0)
68
+ `define SPI_H_1 $signed(5'd0)
69
+ `define SPI_H_2 $signed(5'd0)
70
+ `define SPI_H_3 $signed(5'd0)
71
+ `define SPI_H_4 $signed(5'd1)
72
+ `define SPI_LR_R_WINP 5'b0
73
+ `define SPI_LR_P_WINP 5'd8
74
+ `define SPI_LR_R_WREC 5'b0
75
+ `define SPI_LR_P_WREC 5'd8
76
+ `define SPI_LR_R_WOUT 5'b0
77
+ `define SPI_LR_P_WOUT 5'd14
78
+ `define SPI_SEED_INP 25'hF0F0
79
+ `define SPI_SEED_REC 25'hF1F1
80
+ `define SPI_SEED_OUT 22'hF2F2
81
+ `define SPI_SEED_STRND_NEUR 30'h3F3FF3F3
82
+ `define SPI_SEED_STRND_ONEUR 15'hF4F4
83
+ `define SPI_SEED_STRND_TINP 30'h3F5FF5F5
84
+ `define SPI_SEED_STRND_TREC 30'h3F6FF6F6
85
+ `define SPI_SEED_STRND_TOUT 30'h3F7FF7F7
86
+ `define SPI_SEED_NOISE_NEUR 17'h00FF0
87
+ `define SPI_NUM_INP_NEUR 8'd39
88
+ `define SPI_NUM_REC_NEUR 8'd99
89
+ `define SPI_NUM_OUT_NEUR 4'd1
90
+ `define SPI_REGUL_F0 12'd160
91
+ `define SPI_REGUL_K_INP_R 5'b0
92
+ `define SPI_REGUL_K_INP_P 5'd10
93
+ `define SPI_REGUL_K_REC_R 5'b0
94
+ `define SPI_REGUL_K_REC_P 5'd10
95
+ `define SPI_REGUL_K_MUL 5'd0
96
+ `define SPI_NOISE_STR 4'b0000
ChFrenkel_ReckOn/src/tbench.sv ADDED
@@ -0,0 +1,662 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // Copyright (C) 2020-2022 University of Zurich
2
+ // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
3
+ //
4
+ // Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file except in compliance
5
+ // with the License, or, at your option, the Apache License version 2.0. You may obtain a copy of the License at
6
+ // https://solderpad.org/licenses/SHL-2.1/
7
+ //
8
+ // Unless required by applicable law or agreed to in writing, any work distributed under the License is distributed on
9
+ // an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the
10
+ // specific language governing permissions and limitations under the License.
11
+ //
12
+ //------------------------------------------------------------------------------
13
+ //
14
+ // "tbench.sv" - SystemVerilog testbench including delayed-supervision navigation task implementation
15
+ //
16
+ // Project: ReckOn - Spiking RECurrent neural network processor enabling ON-chip learning over second-long timescales
17
+ //
18
+ // Author: C. Frenkel, Institute of Neuroinformatics, University of Zurich and ETH Zurich
19
+ //
20
+ // Cite/paper: [C. Frenkel and G. Indiveri, "ReckOn: A 28nm sub-mm² task-agnostic spiking recurrent neural network
21
+ // processor enabling on-chip learning over second-long timescales," IEEE International Solid-State
22
+ // Circuits Conference (ISSCC), 2022]
23
+ //
24
+ // Comments: -
25
+ //
26
+ //------------------------------------------------------------------------------
27
+
28
+ `define N 256
29
+ `define M 8
30
+
31
+ `include "tbench.h"
32
+
33
+ `define PATH_TO_INIT_INP_WEIGHTS `"../src/data/init_rand_weights_inp_cueAcc.dat`"
34
+ `define PATH_TO_INIT_REC_WEIGHTS `"../src/data/init_rand_weights_rec_cueAcc.dat`"
35
+ `define PATH_TO_INIT_OUT_WEIGHTS `"../src/data/init_rand_weights_out_cueAcc.dat`"
36
+ `define PATH_TO_TRAIN_SET `"../src/data/dataset_cueAcc_train.dat`"
37
+ `define PATH_TO_TEST_SET `"../src/data/dataset_cueAcc_test.dat`"
38
+
39
+
40
+ module tbench ();
41
+
42
+ /***************************
43
+ SIGNAL DEFINITIONS
44
+ ***************************/
45
+
46
+ // Global inputs -------------------------------
47
+ logic CLK;
48
+ logic CLK_INT_EN;
49
+ logic RST;
50
+
51
+ // SPI slave -------------------------------
52
+ logic SCK;
53
+ logic MOSI;
54
+ logic MISO;
55
+
56
+ // Input bus and control inputs ------------------
57
+ logic [`M-1:0] AERIN_ADDR;
58
+ logic AERIN_REQ;
59
+ logic AERIN_ACK;
60
+ logic AERIN_TAR_EN;
61
+ logic TARGET_VALID;
62
+ logic INFER_ACC;
63
+ logic SAMPLE;
64
+ logic TIME_TICK;
65
+
66
+ // Output bus and control outputs ----------------
67
+ logic SPI_RDY;
68
+ logic TIMING_ERROR_RDY;
69
+ logic OUT_REQ;
70
+ logic OUT_ACK;
71
+ logic [ 7:0] OUT_DATA;
72
+
73
+ // Other testbench signals -----------------------
74
+ logic rst_done, SPI_param_checked, SRNN_initialized_rdy, do_clk_ext;
75
+ logic [ 127:0] prog_val128;
76
+ logic [ 31:0] prog_val32;
77
+ integer e, i, j, k;
78
+
79
+ int fd;
80
+ integer test;
81
+ int status, weight;
82
+ int correct;
83
+ int len;
84
+ int curr_sample;
85
+ int curr_tick;
86
+ int evt_neur, evt_time, evt_target;
87
+ int inference;
88
+
89
+ integer N, M;
90
+ string path_to_init_inp_weights = `PATH_TO_INIT_INP_WEIGHTS;
91
+ string path_to_init_rec_weights = `PATH_TO_INIT_REC_WEIGHTS;
92
+ string path_to_init_out_weights = `PATH_TO_INIT_OUT_WEIGHTS;
93
+ string path_to_train_set = `PATH_TO_TRAIN_SET;
94
+ string path_to_test_set = `PATH_TO_TEST_SET;
95
+
96
+
97
+ /***************************
98
+ CLK
99
+ ***************************/
100
+
101
+ initial begin
102
+ CLK = 1'b0;
103
+ wait_ns(2);
104
+ forever begin
105
+ wait_ns(`CLK_HALF_PERIOD);
106
+ if (do_clk_ext)
107
+ CLK = ~CLK;
108
+ else if (CLK)
109
+ CLK = 1'b0;
110
+ end
111
+ end
112
+
113
+ /***************************
114
+ RST
115
+ ***************************/
116
+
117
+ initial begin
118
+ N = `N;
119
+ M = `M;
120
+ rst_done = 1'b0;
121
+ SPI_param_checked = 1'b0;
122
+ do_clk_ext = 1'b1;
123
+ RST = 1'b0;
124
+ wait_ns(50);
125
+ RST = 1'b1;
126
+ wait_ns(50);
127
+ RST = 1'b0;
128
+ wait_ns(50);
129
+ rst_done = 1'b1;
130
+ end
131
+
132
+
133
+ /***************************
134
+ Other initializations
135
+ ***************************/
136
+
137
+ initial begin
138
+ CLK_INT_EN = 1'b0;
139
+ SCK = 1'b0;
140
+ MOSI = 1'b0;
141
+ AERIN_ADDR = 'd0;
142
+ AERIN_REQ = 1'b0;
143
+ AERIN_TAR_EN = 1'd0;
144
+ TARGET_VALID = 1'b0;
145
+ INFER_ACC = 1'b0;
146
+ SAMPLE = 1'b0;
147
+ TIME_TICK = 1'b0;
148
+ OUT_ACK = 1'b0;
149
+ end
150
+
151
+
152
+ /***************************
153
+ STIMULI
154
+ ***************************/
155
+
156
+ initial begin
157
+
158
+ // Waiting for reset
159
+ while(!rst_done) wait_ns(10);
160
+
161
+ /*****************************************************************************************************************************************************************************************************************
162
+ PROGRAMMING THE CONTROL REGISTERS AND NEURON PARAMETERS THROUGH 32-bit SPI
163
+ *****************************************************************************************************************************************************************************************************************/
164
+
165
+ $display("----- Programming SNN parameters...");
166
+ fork begin
167
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd0 }), .data(1 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_EN_CONF
168
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd1 }), .data(`SPI_RO_STAGE_SEL ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_RO_STAGE_SEL
169
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd2 }), .data(`SPI_GET_CLKINT_OUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_GET_CLKINT_OUT
170
+
171
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd8 }), .data(`SPI_RST_MODE ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_RST_MODE
172
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd9 }), .data(`SPI_DO_EPROP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_DO_EPROP
173
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd10 }), .data(`SPI_LOCAL_TICK ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LOCAL_TICK
174
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd11 }), .data(`SPI_ERROR_HALT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_ERROR_HALT
175
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd12 }), .data(`SPI_FP_LOC_WINP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FP_LOC_WINP
176
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd13 }), .data(`SPI_FP_LOC_WREC ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FP_LOC_WREC
177
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd14 }), .data(`SPI_FP_LOC_WOUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FP_LOC_WOUT
178
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd15 }), .data(`SPI_FP_LOC_TINP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FP_LOC_TINP
179
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd16 }), .data(`SPI_FP_LOC_TREC ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FP_LOC_TREC
180
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd17 }), .data(`SPI_FP_LOC_TOUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FP_LOC_TOUT
181
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd18 }), .data(`SPI_LEARN_SIG_SCALE ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LEARN_SIG_SCALE
182
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd19 }), .data(`SPI_REGUL_MODE ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_MODE
183
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd20 }), .data(`SPI_REGUL_W ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_W
184
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd21 }), .data(`SPI_EN_STOCH_ROUND ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_EN_STOCH_ROUND
185
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd22 }), .data(`SPI_SRAM_SPEEDMODE ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SRAM_SPEEDMODE
186
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd23 }), .data(`SPI_TIMING_MODE ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_TIMING_MODE
187
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd25 }), .data(`SPI_REGRESSION ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGRESSION
188
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd26 }), .data(`SPI_SINGLE_LABEL ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SINGLE_LABEL
189
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd27 }), .data(`SPI_NO_OUT_ACT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_NO_OUT_ACT
190
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd30 }), .data(`SPI_SEND_PER_TIMESTEP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEND_PER_TIMESTEP
191
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd31 }), .data(`SPI_SEND_LABEL_ONLY ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEND_LABEL_ONLY
192
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd32 }), .data(`SPI_NOISE_EN ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_NOISE_EN
193
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd33 }), .data(`SPI_FORCE_TRACES ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_FORCE_TRACES
194
+
195
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd64 }), .data(`SPI_CYCLES_PER_TICK ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_CYCLES_PER_TICK
196
+ for (i=0; i<4; i=i+1) begin
197
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd65+i[1:0]}), .data((`SPI_ALPHA_CONF>>(32*i))), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_ALPHA
198
+ end
199
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd69 }), .data(`SPI_KAPPA ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_KAPPA
200
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd70 }), .data(`SPI_THR_H_0 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_THR_H_0
201
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd71 }), .data(`SPI_THR_H_1 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_THR_H_1
202
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd72 }), .data(`SPI_THR_H_2 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_THR_H_2
203
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd73 }), .data(`SPI_THR_H_3 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_THR_H_3
204
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd74 }), .data(`SPI_H_0 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_H_0
205
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd75 }), .data(`SPI_H_1 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_H_1
206
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd76 }), .data(`SPI_H_2 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_H_2
207
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd77 }), .data(`SPI_H_3 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_H_3
208
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd78 }), .data(`SPI_H_4 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_H_4
209
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd79 }), .data(`SPI_LR_R_WINP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LR_R_WINP
210
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd80 }), .data(`SPI_LR_P_WINP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LR_P_WINP
211
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd81 }), .data(`SPI_LR_R_WREC ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LR_R_WREC
212
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd82 }), .data(`SPI_LR_P_WREC ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LR_P_WREC
213
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd83 }), .data(`SPI_LR_R_WOUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LR_R_WOUT
214
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd84 }), .data(`SPI_LR_P_WOUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_LR_P_WOUT
215
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd85 }), .data(`SPI_SEED_INP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_INP
216
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd86 }), .data(`SPI_SEED_REC ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_REC
217
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd87 }), .data(`SPI_SEED_OUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_OUT
218
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd88 }), .data(`SPI_SEED_STRND_NEUR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_STRND_NEUR
219
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd89 }), .data(`SPI_SEED_STRND_ONEUR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_STRND_ONEUR
220
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd90 }), .data(`SPI_SEED_STRND_TINP ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_STRND_TINP
221
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd91 }), .data(`SPI_SEED_STRND_TREC ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_STRND_TREC
222
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd92 }), .data(`SPI_SEED_STRND_TOUT ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_STRND_TOUT
223
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd93 }), .data(`SPI_SEED_NOISE_NEUR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_SEED_NOISE_NEUR
224
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd94 }), .data(`SPI_NUM_INP_NEUR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_NUM_INP_NEUR
225
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd95 }), .data(`SPI_NUM_REC_NEUR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_NUM_REC_NEUR
226
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd96 }), .data(`SPI_NUM_OUT_NEUR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_NUM_OUT_NEUR
227
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd98 }), .data(`SPI_REGUL_F0 ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_F0
228
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd99 }), .data(`SPI_REGUL_K_INP_R ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_K_INP_R
229
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd100}), .data(`SPI_REGUL_K_INP_P ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_K_INP_P
230
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd101}), .data(`SPI_REGUL_K_REC_R ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_K_REC_R
231
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd102}), .data(`SPI_REGUL_K_REC_P ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_K_REC_P
232
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd103}), .data(`SPI_REGUL_K_MUL ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_REGUL_K_MUL
233
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd104}), .data(`SPI_NOISE_STR ), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //SPI_NOISE_STR
234
+ end join
235
+
236
+
237
+ /*****************************************************************************************************************************************************************************************************************
238
+ VERIFYING THE NEURON PARAMETERS
239
+ *****************************************************************************************************************************************************************************************************************/
240
+
241
+ $display("----- Starting verification of programmed SNN parameters");
242
+ assert(srnn_0.spi_slave_0.SPI_EN_CONF == 1'b1 ) else $fatal(0, "SPI_EN_CONF parameter not correct.");
243
+ assert(srnn_0.spi_slave_0.SPI_RO_STAGE_SEL == `SPI_RO_STAGE_SEL ) else $fatal(0, "SPI_RO_STAGE_SEL parameter not correct.");
244
+ assert(srnn_0.spi_slave_0.SPI_GET_CLKINT_OUT == `SPI_GET_CLKINT_OUT ) else $fatal(0, "SPI_GET_CLKINT_OUT parameter not correct.");
245
+ assert(srnn_0.srnn_0.SPI_RST_MODE == `SPI_RST_MODE ) else $fatal(0, "SPI_RST_MODE parameter not correct.");
246
+ assert(srnn_0.srnn_0.SPI_DO_EPROP == `SPI_DO_EPROP ) else $fatal(0, "SPI_DO_EPROP parameter not correct.");
247
+ assert(srnn_0.srnn_0.SPI_LOCAL_TICK == `SPI_LOCAL_TICK ) else $fatal(0, "SPI_LOCAL_TICK parameter not correct.");
248
+ assert(srnn_0.srnn_0.SPI_ERROR_HALT == `SPI_ERROR_HALT ) else $fatal(0, "SPI_ERROR_HALT parameter not correct.");
249
+ assert(srnn_0.srnn_0.SPI_FP_LOC_WINP == `SPI_FP_LOC_WINP ) else $fatal(0, "SPI_FP_LOC_WINP parameter not correct.");
250
+ assert(srnn_0.srnn_0.SPI_FP_LOC_WREC == `SPI_FP_LOC_WREC ) else $fatal(0, "SPI_FP_LOC_WREC parameter not correct.");
251
+ assert(srnn_0.srnn_0.SPI_FP_LOC_WOUT == `SPI_FP_LOC_WOUT ) else $fatal(0, "SPI_FP_LOC_WOUT parameter not correct.");
252
+ assert(srnn_0.srnn_0.SPI_FP_LOC_TINP == `SPI_FP_LOC_TINP ) else $fatal(0, "SPI_FP_LOC_TINP parameter not correct.");
253
+ assert(srnn_0.srnn_0.SPI_FP_LOC_TREC == `SPI_FP_LOC_TREC ) else $fatal(0, "SPI_FP_LOC_TREC parameter not correct.");
254
+ assert(srnn_0.srnn_0.SPI_FP_LOC_TOUT == `SPI_FP_LOC_TOUT ) else $fatal(0, "SPI_FP_LOC_TOUT parameter not correct.");
255
+ assert(srnn_0.srnn_0.SPI_LEARN_SIG_SCALE == `SPI_LEARN_SIG_SCALE ) else $fatal(0, "SPI_LEARN_SIG_SCALE parameter not correct.");
256
+ assert(srnn_0.srnn_0.SPI_REGUL_MODE == `SPI_REGUL_MODE ) else $fatal(0, "SPI_REGUL_MODE parameter not correct.");
257
+ assert(srnn_0.srnn_0.SPI_REGUL_W == `SPI_REGUL_W ) else $fatal(0, "SPI_REGUL_W parameter not correct.");
258
+ assert(srnn_0.srnn_0.SPI_EN_STOCH_ROUND == `SPI_EN_STOCH_ROUND ) else $fatal(0, "SPI_EN_STOCH_ROUND parameter not correct.");
259
+ assert(srnn_0.srnn_0.SPI_SRAM_SPEEDMODE == `SPI_SRAM_SPEEDMODE ) else $fatal(0, "SPI_SRAM_SPEEDMODE parameter not correct.");
260
+ assert(srnn_0.srnn_0.SPI_TIMING_MODE == `SPI_TIMING_MODE ) else $fatal(0, "SPI_TIMING_MODE parameter not correct.");
261
+ assert(srnn_0.srnn_0.SPI_REGRESSION == `SPI_REGRESSION ) else $fatal(0, "SPI_REGRESSION parameter not correct.");
262
+ assert(srnn_0.srnn_0.SPI_SINGLE_LABEL == `SPI_SINGLE_LABEL ) else $fatal(0, "SPI_SINGLE_LABEL parameter not correct.");
263
+ assert(srnn_0.srnn_0.SPI_NO_OUT_ACT == `SPI_NO_OUT_ACT ) else $fatal(0, "SPI_NO_OUT_ACT parameter not correct.");
264
+ assert(srnn_0.srnn_0.SPI_SEND_PER_TIMESTEP == `SPI_SEND_PER_TIMESTEP ) else $fatal(0, "SPI_SEND_PER_TIMESTEP parameter not correct.");
265
+ assert(srnn_0.srnn_0.SPI_SEND_LABEL_ONLY == `SPI_SEND_LABEL_ONLY ) else $fatal(0, "SPI_SEND_LABEL_ONLY parameter not correct.");
266
+ assert(srnn_0.srnn_0.SPI_NOISE_EN == `SPI_NOISE_EN ) else $fatal(0, "SPI_NOISE_EN parameter not correct.");
267
+ assert(srnn_0.srnn_0.SPI_FORCE_TRACES == `SPI_FORCE_TRACES ) else $fatal(0, "SPI_FORCE_TRACES parameter not correct.");
268
+
269
+ assert(srnn_0.srnn_0.SPI_CYCLES_PER_TICK == `SPI_CYCLES_PER_TICK ) else $fatal(0, "SPI_CYCLES_PER_TICK parameter not correct.");
270
+ assert(srnn_0.srnn_0.SPI_ALPHA_CONF == `SPI_ALPHA_CONF ) else $fatal(0, "SPI_ALPHA_CONF parameter not correct.");
271
+ assert(srnn_0.srnn_0.SPI_KAPPA == `SPI_KAPPA ) else $fatal(0, "SPI_KAPPA parameter not correct.");
272
+ assert(srnn_0.srnn_0.SPI_THR_H_0 == `SPI_THR_H_0 ) else $fatal(0, "SPI_THR_H_0 parameter not correct.");
273
+ assert(srnn_0.srnn_0.SPI_THR_H_1 == `SPI_THR_H_1 ) else $fatal(0, "SPI_THR_H_1 parameter not correct.");
274
+ assert(srnn_0.srnn_0.SPI_THR_H_2 == `SPI_THR_H_2 ) else $fatal(0, "SPI_THR_H_2 parameter not correct.");
275
+ assert(srnn_0.srnn_0.SPI_THR_H_3 == `SPI_THR_H_3 ) else $fatal(0, "SPI_THR_H_3 parameter not correct.");
276
+ assert(srnn_0.srnn_0.SPI_H_0 == `SPI_H_0 ) else $fatal(0, "SPI_H_0 parameter not correct.");
277
+ assert(srnn_0.srnn_0.SPI_H_1 == `SPI_H_1 ) else $fatal(0, "SPI_H_1 parameter not correct.");
278
+ assert(srnn_0.srnn_0.SPI_H_2 == `SPI_H_2 ) else $fatal(0, "SPI_H_2 parameter not correct.");
279
+ assert(srnn_0.srnn_0.SPI_H_3 == `SPI_H_3 ) else $fatal(0, "SPI_H_3 parameter not correct.");
280
+ assert(srnn_0.srnn_0.SPI_H_4 == `SPI_H_4 ) else $fatal(0, "SPI_H_4 parameter not correct.");
281
+ assert(srnn_0.srnn_0.SPI_LR_R_WINP == `SPI_LR_R_WINP ) else $fatal(0, "SPI_LR_R_WINP parameter not correct.");
282
+ assert(srnn_0.srnn_0.SPI_LR_P_WINP == `SPI_LR_P_WINP ) else $fatal(0, "SPI_LR_P_WINP parameter not correct.");
283
+ assert(srnn_0.srnn_0.SPI_LR_R_WREC == `SPI_LR_R_WREC ) else $fatal(0, "SPI_LR_R_WREC parameter not correct.");
284
+ assert(srnn_0.srnn_0.SPI_LR_P_WREC == `SPI_LR_P_WREC ) else $fatal(0, "SPI_LR_P_WREC parameter not correct.");
285
+ assert(srnn_0.srnn_0.SPI_LR_R_WOUT == `SPI_LR_R_WOUT ) else $fatal(0, "SPI_LR_R_WOUT parameter not correct.");
286
+ assert(srnn_0.srnn_0.SPI_LR_P_WOUT == `SPI_LR_P_WOUT ) else $fatal(0, "SPI_LR_P_WOUT parameter not correct.");
287
+ assert(srnn_0.srnn_0.SPI_SEED_INP == `SPI_SEED_INP ) else $fatal(0, "SPI_SEED_INP parameter not correct.");
288
+ assert(srnn_0.srnn_0.SPI_SEED_REC == `SPI_SEED_REC ) else $fatal(0, "SPI_SEED_REC parameter not correct.");
289
+ assert(srnn_0.srnn_0.SPI_SEED_OUT == `SPI_SEED_OUT ) else $fatal(0, "SPI_SEED_OUT parameter not correct.");
290
+ assert(srnn_0.srnn_0.SPI_SEED_STRND_NEUR == `SPI_SEED_STRND_NEUR ) else $fatal(0, "SPI_SEED_STRND_NEUR parameter not correct.");
291
+ assert(srnn_0.srnn_0.SPI_SEED_STRND_ONEUR == `SPI_SEED_STRND_ONEUR ) else $fatal(0, "SPI_SEED_STRND_ONEUR parameter not correct.");
292
+ assert(srnn_0.srnn_0.SPI_SEED_STRND_TINP == `SPI_SEED_STRND_TINP ) else $fatal(0, "SPI_SEED_STRND_TINP parameter not correct.");
293
+ assert(srnn_0.srnn_0.SPI_SEED_STRND_TREC == `SPI_SEED_STRND_TREC ) else $fatal(0, "SPI_SEED_STRND_TREC parameter not correct.");
294
+ assert(srnn_0.srnn_0.SPI_SEED_STRND_TOUT == `SPI_SEED_STRND_TOUT ) else $fatal(0, "SPI_SEED_STRND_TOUT parameter not correct.");
295
+ assert(srnn_0.srnn_0.SPI_SEED_NOISE_NEUR == `SPI_SEED_NOISE_NEUR ) else $fatal(0, "SPI_SEED_NOISE_NEUR parameter not correct.");
296
+ assert(srnn_0.srnn_0.SPI_NUM_INP_NEUR == `SPI_NUM_INP_NEUR ) else $fatal(0, "SPI_NUM_INP_NEUR parameter not correct.");
297
+ assert(srnn_0.srnn_0.SPI_NUM_REC_NEUR == `SPI_NUM_REC_NEUR ) else $fatal(0, "SPI_NUM_REC_NEUR parameter not correct.");
298
+ assert(srnn_0.srnn_0.SPI_NUM_OUT_NEUR == `SPI_NUM_OUT_NEUR ) else $fatal(0, "SPI_NUM_OUT_NEUR parameter not correct.");
299
+ assert(srnn_0.srnn_0.SPI_REGUL_F0 == `SPI_REGUL_F0 ) else $fatal(0, "SPI_REGUL_F0 parameter not correct.");
300
+ assert(srnn_0.srnn_0.SPI_REGUL_K_INP_R == `SPI_REGUL_K_INP_R ) else $fatal(0, "SPI_REGUL_K_INP_R parameter not correct.");
301
+ assert(srnn_0.srnn_0.SPI_REGUL_K_INP_P == `SPI_REGUL_K_INP_P ) else $fatal(0, "SPI_REGUL_K_INP_P parameter not correct.");
302
+ assert(srnn_0.srnn_0.SPI_REGUL_K_REC_R == `SPI_REGUL_K_REC_R ) else $fatal(0, "SPI_REGUL_K_REC_R parameter not correct.");
303
+ assert(srnn_0.srnn_0.SPI_REGUL_K_REC_P == `SPI_REGUL_K_REC_P ) else $fatal(0, "SPI_REGUL_K_REC_P parameter not correct.");
304
+ assert(srnn_0.srnn_0.SPI_REGUL_K_MUL == `SPI_REGUL_K_MUL ) else $fatal(0, "SPI_REGUL_K_MUL parameter not correct.");
305
+ assert(srnn_0.srnn_0.SPI_NOISE_STR == `SPI_NOISE_STR ) else $fatal(0, "SPI_NOISE_STR parameter not correct.");
306
+
307
+ $display("----- Done verification of programmed SNN parameters.");
308
+ spi_send (.addr({1'b0,3'b000,12'd1,16'd0}), .data(0), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); //Disable SPI_EN_CONF
309
+
310
+ wait_ns(1000);
311
+
312
+
313
+ /*****************************************************************************************************************************************************************************************************************
314
+ FAST DELAYED-SUPERVISION NAVIGATION E-PROP BENCHMARKING
315
+ *****************************************************************************************************************************************************************************************************************/
316
+
317
+ // Enter programming phase
318
+ spi_send (.addr({1'b0,3'h0,12'd1,16'd0}), .data(1), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Enable SPI_EN_CONF
319
+
320
+ $display("----- Starting delayed-supervision navigation benchmarking (e-prop enabled on random weights)...");
321
+ $display(" Initializing input weights (with SPI)...");
322
+ fd = $fopen(path_to_init_inp_weights,"r");
323
+ fork begin
324
+ for (i=0; i<40; i=i+1) begin
325
+ spi_half_w(.data({1'b0,3'h3,12'd25,{2'b0,i[7:0],6'd0}}), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Header of a multi-write transaction starting at postsynaptic address 0 of pre-synaptic neuron i (25 32-bit writes = 100 post-synaptic weights)
326
+ for (j=0; j<25; j=j+1) begin
327
+ prog_val32 = 32'b0;
328
+ for (k=0; k<4; k=k+1) begin
329
+ status = $fscanf(fd,"%d",weight);
330
+ assert(status == 1) else $fatal(0, "A problem occured while processing input weights file.");
331
+ prog_val32 = prog_val32 | ({24'b0,weight[7:0]} << (8*k));
332
+ end
333
+ spi_half_w(.data(prog_val32), .MISO(MISO), .MOSI(MOSI), .SCK(SCK));
334
+ end
335
+ end
336
+ end join
337
+ $fclose(fd);
338
+ $display(" Initializing recurrent weights (with SPI)...");
339
+ fd = $fopen(path_to_init_rec_weights,"r");
340
+ fork begin
341
+ for (i=0; i<100; i=i+1) begin
342
+ spi_half_w(.data({1'b0,3'h4,12'd25,{2'b0,i[7:0],6'd0}}), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Header of a multi-write transaction starting at postsynaptic address 0 of pre-synaptic neuron i (25 32-bit writes = 100 post-synaptic weights)
343
+ for (j=0; j<25; j=j+1) begin
344
+ prog_val32 = 32'b0;
345
+ for (k=0; k<4; k=k+1) begin
346
+ status = $fscanf(fd,"%d",weight);
347
+ assert(status == 1) else $fatal(0, "A problem occured while processing recurrent weights file.");
348
+ prog_val32 = prog_val32 | ({24'b0,weight[7:0]} << (8*k));
349
+ end
350
+ spi_half_w(.data(prog_val32), .MISO(MISO), .MOSI(MOSI), .SCK(SCK));
351
+ end
352
+ end
353
+ end join
354
+ $fclose(fd);
355
+ $display(" Initializing output weights (with SPI)...");
356
+ fd = $fopen(path_to_init_out_weights,"r");
357
+ fork begin
358
+ for (i=0; i<100; i=i+1) begin
359
+ prog_val32 = 32'b0;
360
+ for (k=0; k<2; k=k+1) begin
361
+ status = $fscanf(fd,"%d",weight);
362
+ assert(status == 1) else $fatal(0, "A problem occured while processing output weights file.");
363
+ prog_val32 = prog_val32 | ({24'b0,weight[7:0]} << (8*k));
364
+ end
365
+ spi_send (.addr({1'b0,3'h5,12'd1,{6'b0,i[7:0],2'b0}}), .data(prog_val32), .MISO(MISO), .MOSI(MOSI), .SCK(SCK));
366
+ end
367
+ end join
368
+ $fclose(fd);
369
+ wait_ns(1000);
370
+
371
+ $display(" Initializing neurons (with SPI)...");
372
+ fork begin
373
+ prog_val128 = {12'hFEF,16'd614,{2{10'b0,12'b0,12'b0,16'b0}}};
374
+ spi_half_w(.data({1'b0,3'h1,12'd400,16'd0}), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Header of a multi-write transaction starting at address 0 of neurons
375
+ for (i=0; i<100; i=i+1) begin
376
+ for (j=0; j<4; j=j+1) begin
377
+ prog_val32 = prog_val128[j*32+:32];
378
+ spi_half_w(.data(prog_val32), .MISO(MISO), .MOSI(MOSI), .SCK(SCK));
379
+ end
380
+ end
381
+ spi_send (.addr({1'b0,3'h0,12'd1,16'd0}), .data(0), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Disable SPI_EN_CONF
382
+ end join
383
+ wait_ns(1000);
384
+
385
+
386
+ $display(" Start training for %d epochs...", `EPOCHS);
387
+ for (e=0; e<`EPOCHS; e++) begin // For a given number of epochs
388
+
389
+ $display(" --- Epoch %d:", e+1);
390
+ for (test=0; test<=1; test++) begin
391
+
392
+ correct = 0;
393
+ fork begin
394
+ spi_send (.addr({1'b0,3'h0,12'd1,16'd0}), .data(1), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Enable SPI_EN_CONF
395
+ if (test) begin // Test
396
+ spi_send (.addr({1'b0,3'h0,12'd1,16'd9}), .data(3'b000), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // SPI_DO_EPROP all disabled
397
+ fd = $fopen(path_to_test_set,"r");
398
+ end else begin // Train
399
+ spi_send (.addr({1'b0,3'h0,12'd1,16'd9}), .data(3'b111), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // SPI_DO_EPROP all enabled
400
+ fd = $fopen(path_to_train_set,"r");
401
+ end
402
+ spi_send (.addr({1'b0,3'h0,12'd1,16'd0}), .data(0), .MISO(MISO), .MOSI(MOSI), .SCK(SCK)); // Disable SPI_EN_CONF
403
+ end join
404
+ status = $fscanf(fd,"%d",len);
405
+ assert (status == 1) else $fatal(0, "A problem occured while reading the header of the delayed-supervision navigation dataset.");
406
+ wait_ns(1000);
407
+
408
+ for (curr_sample=0; curr_sample<len; curr_sample=curr_sample+1) begin
409
+ curr_tick = 0;
410
+ SAMPLE = 1'b1;
411
+ wait_ns(100);
412
+ while (1) begin
413
+ status = $fscanf(fd, "%d, %d", evt_neur, evt_time);
414
+ assert(status == 2) else $fatal(0, "A problem occured while reading an event from the dataset.");
415
+ if (evt_neur == -2) begin // Target start mark
416
+ evt_target = evt_time;
417
+ while (curr_tick < 2100) begin
418
+ TIME_TICK = 1'b1;
419
+ wait_ns(100);
420
+ TIME_TICK = 1'b0;
421
+ curr_tick = curr_tick + 1;
422
+ @(posedge TIMING_ERROR_RDY);
423
+ wait_ns(100);
424
+ end
425
+ if (!test) begin
426
+ AERIN_TAR_EN = 1'b1;
427
+ aer_send(.addr_in(evt_target[7:0]), .addr_out(AERIN_ADDR), .ack(AERIN_ACK), .req(AERIN_REQ));
428
+ wait_ns(200);
429
+ AERIN_TAR_EN = 1'b0;
430
+ wait_ns(100);
431
+ TARGET_VALID = 1'b1;
432
+ end
433
+ INFER_ACC = 1'b1;
434
+ wait_ns(100);
435
+ status = $fscanf(fd, "%d, %d", evt_neur, evt_time);
436
+ assert(status == 2) else $fatal(0, "A problem occured while reading an event post-target from the dataset.");
437
+ end
438
+ while (curr_tick < evt_time) begin
439
+ if (curr_tick == 2249) begin
440
+ SAMPLE = 1'b0;
441
+ wait_ns(100);
442
+ end
443
+ TIME_TICK = 1'b1;
444
+ wait_ns(100);
445
+ TIME_TICK = 1'b0;
446
+
447
+ if (curr_tick == 2249)
448
+ break;
449
+ curr_tick = curr_tick + 1;
450
+ @(posedge TIMING_ERROR_RDY);
451
+ wait_ns(100);
452
+
453
+ end if (evt_neur == -1)
454
+ break;
455
+ aer_send(.addr_in(evt_neur[7:0]), .addr_out(AERIN_ADDR), .ack(AERIN_ACK), .req(AERIN_REQ));
456
+ wait_ns(100);
457
+ end
458
+
459
+ while (!OUT_REQ)
460
+ wait_ns(100);
461
+ inference = OUT_DATA[3:0];
462
+ if (inference == evt_target[3:0])
463
+ correct = correct + 1;
464
+ $display(" Sample %2d: inference is %2d, label is %2d", curr_sample, inference, evt_target);
465
+ OUT_ACK = 1'b1;
466
+ while (OUT_REQ)
467
+ wait_ns(100);
468
+ OUT_ACK = 1'b0;
469
+ wait_ns(1000);
470
+ TARGET_VALID = 1'b0;
471
+ INFER_ACC = 1'b0;
472
+ wait_ns(1000);
473
+ end
474
+ $fclose(fd);
475
+ if (test)
476
+ $display(" Score on test set is %0d/%0d (%d percents)!", correct, len, 100*correct/len);
477
+ else
478
+ $display(" Score while training is %0d/%0d (%d percents)!", correct, len, 100*correct/len);
479
+ end
480
+ end
481
+
482
+ $display("----- Ending delayed-supervision navigation benchmarking.");
483
+
484
+
485
+ /***************************
486
+ Properly ending simulation
487
+ ***************************/
488
+
489
+ wait_ns(10000);
490
+ $finish;
491
+
492
+ end
493
+
494
+
495
+ /***************************
496
+ SNN INSTANTIATION
497
+ ***************************/
498
+
499
+ reckon srnn_0 (
500
+ // Global inputs -------------------------------
501
+ .CLK_EXT(CLK),
502
+ .CLK_INT_EN(CLK_INT_EN),
503
+ .RST(RST),
504
+
505
+ // SPI slave -------------------------------
506
+ .SCK(SCK),
507
+ .MOSI(MOSI),
508
+ .MISO(MISO),
509
+
510
+ // Input bus and control inputs ------------------
511
+ .AERIN_ADDR(AERIN_ADDR),
512
+ .AERIN_REQ(AERIN_REQ),
513
+ .AERIN_ACK(AERIN_ACK),
514
+ .AERIN_TAR_EN(AERIN_TAR_EN),
515
+ .SAMPLE(SAMPLE),
516
+ .TIME_TICK(TIME_TICK),
517
+ .TARGET_VALID(TARGET_VALID),
518
+ .INFER_ACC(INFER_ACC),
519
+
520
+ // Output bus and control outputs ----------------
521
+ .SPI_RDY(SPI_RDY),
522
+ .TIMING_ERROR_RDY(TIMING_ERROR_RDY),
523
+ .OUT_REQ(OUT_REQ),
524
+ .OUT_ACK(OUT_ACK),
525
+ .OUT_DATA(OUT_DATA)
526
+ );
527
+
528
+
529
+ /***********************************************************************
530
+ TASK IMPLEMENTATIONS
531
+ ************************************************************************/
532
+
533
+ /***************************
534
+ SIMPLE TIME-HANDLING TASKS
535
+ ***************************/
536
+
537
+ // Based on a correct definition of the simulator timescale at 1ns/1ps.
538
+ task wait_ns;
539
+ input tics_ns;
540
+ integer tics_ns;
541
+ #tics_ns;
542
+ endtask
543
+
544
+ /***************************
545
+ AER send event
546
+ ***************************/
547
+
548
+ task automatic aer_send (
549
+ input logic [`M-1:0] addr_in,
550
+ ref logic [`M-1:0] addr_out,
551
+ ref logic ack,
552
+ ref logic req
553
+ );
554
+ while (ack) wait_ns(1);
555
+ addr_out = addr_in;
556
+ wait_ns(1);
557
+ req = 1'b1;
558
+ while (!ack) wait_ns(1);
559
+ wait_ns(1);
560
+ req = 1'b0;
561
+ endtask
562
+
563
+ /***************************
564
+ SPI half transaction (for multi-R/W)
565
+ ***************************/
566
+
567
+ task automatic spi_half_w (
568
+ input logic [31:0] data,
569
+ input logic MISO, // not used
570
+ ref logic MOSI,
571
+ ref logic SCK
572
+ );
573
+ integer i;
574
+
575
+ for (i=0; i<32; i=i+1) begin
576
+ MOSI = data[31-i];
577
+ wait_ns(`SCK_HALF_PERIOD);
578
+ SCK = 1'b1;
579
+ wait_ns(`SCK_HALF_PERIOD);
580
+ SCK = 1'b0;
581
+ end
582
+ endtask
583
+
584
+ task automatic spi_half_r (
585
+ output logic [31:0] data,
586
+ ref logic MISO,
587
+ ref logic MOSI,
588
+ ref logic SCK
589
+ );
590
+ integer i;
591
+
592
+ for (i=0; i<32; i=i+1) begin
593
+ wait_ns(`SCK_HALF_PERIOD);
594
+ data = {data[30:0],MISO};
595
+ SCK = 1'b1;
596
+ wait_ns(`SCK_HALF_PERIOD);
597
+ SCK = 1'b0;
598
+ end
599
+ endtask
600
+
601
+ /***************************
602
+ SPI send data
603
+ ***************************/
604
+
605
+ task automatic spi_send (
606
+ input logic [31:0] addr,
607
+ input logic [31:0] data,
608
+ input logic MISO, // not used
609
+ ref logic MOSI,
610
+ ref logic SCK
611
+ );
612
+ integer i;
613
+
614
+ for (i=0; i<32; i=i+1) begin
615
+ MOSI = addr[31-i];
616
+ wait_ns(`SCK_HALF_PERIOD);
617
+ SCK = 1'b1;
618
+ wait_ns(`SCK_HALF_PERIOD);
619
+ SCK = 1'b0;
620
+ end
621
+ for (i=0; i<32; i=i+1) begin
622
+ MOSI = data[31-i];
623
+ wait_ns(`SCK_HALF_PERIOD);
624
+ SCK = 1'b1;
625
+ wait_ns(`SCK_HALF_PERIOD);
626
+ SCK = 1'b0;
627
+ end
628
+ endtask
629
+
630
+ /***************************
631
+ SPI read data
632
+ ***************************/
633
+
634
+ task automatic spi_read (
635
+ input logic [31:0] addr,
636
+ output logic [31:0] data,
637
+ ref logic MISO,
638
+ ref logic MOSI,
639
+ ref logic SCK
640
+ );
641
+ integer i;
642
+
643
+ for (i=0; i<32; i=i+1) begin
644
+ MOSI = addr[31-i];
645
+ wait_ns(`SCK_HALF_PERIOD);
646
+ SCK = 1'b1;
647
+ wait_ns(`SCK_HALF_PERIOD);
648
+ SCK = 1'b0;
649
+ end
650
+ for (i=0; i<32; i=i+1) begin
651
+ wait_ns(`SCK_HALF_PERIOD);
652
+ data = {data[30:0],MISO};
653
+ SCK = 1'b1;
654
+ wait_ns(`SCK_HALF_PERIOD);
655
+ SCK = 1'b0;
656
+ end
657
+ endtask
658
+
659
+
660
+ endmodule
661
+
662
+