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| LX_DEPENDENCIES = ["icestorm", "yosys", "nextpnr-ice40"] |
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| |
| import os,os.path,shutil,sys,subprocess |
| sys.path.insert(0, os.path.dirname(__file__)) |
| import lxbuildenv |
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|
| from migen import * |
| from migen.genlib.resetsync import AsyncResetSynchronizer |
|
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| from litex.soc.integration.soc_core import SoCCore |
| from litex.soc.integration.builder import Builder |
| from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage |
|
|
| from litex_boards.targets.fomu import BaseSoC, add_dfu_suffix |
|
|
| from valentyusb.usbcore import io as usbio |
| from valentyusb.usbcore.cpu import dummyusb |
|
|
| import argparse |
|
|
| def main(): |
| parser = argparse.ArgumentParser( |
| description="Build Fomu Main Gateware") |
| parser.add_argument( |
| "--seed", default=0, help="seed to use in nextpnr" |
| ) |
| parser.add_argument( |
| "--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr" |
| ) |
| parser.add_argument( |
| "--board", choices=["evt", "pvt", "hacker"], required=True, |
| help="build for a particular hardware board" |
| ) |
| args = parser.parse_args() |
|
|
| soc = BaseSoC(args.board, pnr_seed=args.seed, pnr_placer=args.placer, usb_bridge=True) |
|
|
| builder = Builder(soc, |
| output_dir="build", csr_csv="build/csr.csv", |
| compile_software=False) |
| vns = builder.build() |
| soc.do_exit(vns) |
| add_dfu_suffix(os.path.join('build', 'gateware', 'fomu_{}.bin'.format(args.board))) |
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|
|
| if __name__ == "__main__": |
| main() |
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