| module sys_pll_56_25 ( |
| input wire inclk0, |
| input wire areset, |
| output wire c0, |
| output wire locked |
| ); |
|
|
| wire [4:0] clk_bus; |
| wire [1:0] inclk_bus = {1'b0, inclk0}; |
|
|
| altpll altpll_component ( |
| .areset(areset), |
| .inclk(inclk_bus), |
| .clk(clk_bus), |
| .locked(locked), |
| .activeclock(), |
| .clkbad(), |
| .clkena({6{1'b1}}), |
| .clkloss(), |
| .enable0(), |
| .enable1(), |
| .extclk(), |
| .extclkena({4{1'b1}}), |
| .fbin(1'b1), |
| .fbmimicbidir(), |
| .fbout(), |
| .fref(), |
| .icdrclk(), |
| .pfdena(1'b1), |
| .phasecounterselect({4{1'b1}}), |
| .phasedone(), |
| .phasestep(1'b1), |
| .phaseupdown(1'b1), |
| .pllena(1'b1), |
| .scanaclr(1'b0), |
| .scanclk(1'b0), |
| .scanclkena(1'b1), |
| .scandata(1'b0), |
| .scandataout(), |
| .scandone(), |
| .scanread(1'b0), |
| .scanwrite(1'b0), |
| .sclkout0(), |
| .sclkout1(), |
| .vcooverrange(), |
| .vcounderrange() |
| ); |
|
|
| defparam |
| altpll_component.bandwidth_type = "AUTO", |
| altpll_component.clk0_divide_by = 8, |
| altpll_component.clk0_duty_cycle = 50, |
| altpll_component.clk0_multiply_by = 9, |
| altpll_component.clk0_phase_shift = "0", |
| altpll_component.compensate_clock = "CLK0", |
| altpll_component.inclk0_input_frequency = 20000, |
| altpll_component.intended_device_family = "Cyclone V", |
| altpll_component.operation_mode = "NORMAL", |
| altpll_component.pll_type = "AUTO", |
| altpll_component.port_activeclock = "PORT_UNUSED", |
| altpll_component.port_areset = "PORT_USED", |
| altpll_component.port_clkbad0 = "PORT_UNUSED", |
| altpll_component.port_clkbad1 = "PORT_UNUSED", |
| altpll_component.port_clkloss = "PORT_UNUSED", |
| altpll_component.port_clkswitch = "PORT_UNUSED", |
| altpll_component.port_configupdate = "PORT_UNUSED", |
| altpll_component.port_fbin = "PORT_UNUSED", |
| altpll_component.port_inclk0 = "PORT_USED", |
| altpll_component.port_inclk1 = "PORT_UNUSED", |
| altpll_component.port_locked = "PORT_USED", |
| altpll_component.port_pfdena = "PORT_UNUSED", |
| altpll_component.port_phasecounterselect = "PORT_UNUSED", |
| altpll_component.port_phasedone = "PORT_UNUSED", |
| altpll_component.port_phasestep = "PORT_UNUSED", |
| altpll_component.port_phaseupdown = "PORT_UNUSED", |
| altpll_component.port_pllena = "PORT_UNUSED", |
| altpll_component.port_scanaclr = "PORT_UNUSED", |
| altpll_component.port_scanclk = "PORT_UNUSED", |
| altpll_component.port_scanclkena = "PORT_UNUSED", |
| altpll_component.port_scandata = "PORT_UNUSED", |
| altpll_component.port_scandataout = "PORT_UNUSED", |
| altpll_component.port_scandone = "PORT_UNUSED", |
| altpll_component.port_scanread = "PORT_UNUSED", |
| altpll_component.port_scanwrite = "PORT_UNUSED"; |
|
|
| assign c0 = clk_bus[0]; |
|
|
| endmodule |
|
|
