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verilog_data-2 / The-OpenROAD-Project_OpenROAD-flow-scripts /flow /scripts /synth_metrics.tcl

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Add Batch 2 with 10 repos

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	utl::set_metrics_stage "synth__{}"
	source $::env(SCRIPTS_DIR)/load.tcl
	load_design 1_2_yosys.v 1_synth.sdc

	report_metrics 1 "Post synthesis" false false