THU-DSP-LAB_ventus-gpgpu-verilog/FPGA_test/ventus_fpga.tcl

#*****************************************************************************************
# Vivado (TM) v2019.1 (64-bit)
#
# ventus_fpga.tcl: Tcl script for re-creating project 'ventus_gpgputest_verilogtcl'
#
# Generated by Vivado on Thu Feb 13 16:55:07 +0800 2025
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (ventus_fpga.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    "E:/FPGA/ventus/ventus/ventus_gpgputest_verilogtcl/ventus_gpgputest_verilogtcl.srcs/sources_1/bd/config_mb/hdl/config_mb_wrapper.v"
#    "E:/FPGA/ventus/ventus/ventus_gpgputest_verilogtcl/ventus_gpgputest_verilogtcl.srcs/constrs_1/new/pin_config.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/define/define.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/GPGPU_top.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Listbuffer.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Listbuffer_no_push_opc_put_source.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/MSHR.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Scheduler.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/SourceA.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/addrcalculate.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/allocator_neo.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/alu.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/aluexe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/array_multiplier.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4lite_2_cta.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/shared_memory/bankconflict_arb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/banked_store.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/bin2one.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/booth.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/branch_back.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/simt_stack/branch_join_stack.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/byte_extract.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cam_allocator.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cam_allocator_neo.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cluster_to_l2_arb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/collector_unit.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/csr/csrexe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/csr/csrfile.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/cta2warp.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta_interface.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cta_scheduler.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cu_handler.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/dcache_control.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/dcache_wshr.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/decodeUnit.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/directory_test.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/dis_controller.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/dualportSRAM.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fadd_pipe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fadd_pipe_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fadd_s1.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fadd_s2.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/far_path.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fcmp.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fcmp_core.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fcmp_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fifo.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fifo_with_count.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fifo_with_flush.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/find_first.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fixed_pri_arb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fma.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fma_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fmul_pipe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fmul_pipe_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s1.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s2.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s3.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fp_to_int.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fp_to_int_core.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fp_to_int_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fpmv.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fpmv_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpuexe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/full_adder.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/gen_data_map_per_byte.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/gen_data_map_same_word.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/gen_imm.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/get_data_access_banken.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/get_entry_status.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/get_entry_status_req.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/get_entry_status_rsp.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/get_setid.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/gpu_interface.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer/ibuffer.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer2issue.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/inflight_wg_buffer.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/input_fifo.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/input_reverse.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/inst_demux.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/instruction_cache.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/int_div.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/int_to_fp_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp_postnorm.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp_prenorm.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/issue.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_dcache.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/l1_mshr.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache_arb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2_distribute.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/lru_matrix.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/lsu2wb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/lsu_exe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/lza.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/mshr_icache.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/mshr_reg.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/mult_32.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/naivemultiplier.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/near_path.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/one2bin.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operand_arbiter.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/pc_align.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/pc_control.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/pipe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/pop_cnt.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/prefer_select.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/ram.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/resource_table.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/resource_table_group.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/round_robin_arb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/rounding.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/rsp_arb.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/scalar_fpu.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/scalar_fpu_no_ctrl.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/scalar_regfile_bank.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/scoreboard.v"
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#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/shift_right_jam.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/shiftboard.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/simt_stack/simt_stack.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sinkA.v"
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#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm2cluster_arb.v"
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#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/sram_template.v"
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#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo.v"
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#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true_with_count.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_useSRAM.v"
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#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tensor_core_exe.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tensor_core_fp32.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/throttling_engine.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/top_resource_table.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu_top.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/vector_regfile_bank.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/vfpu.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul_top.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/wallace_adder_18.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/warp_scheduler.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/wf_done_interface_single.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/wg_resource_table_neo.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/wg_slot_id_convert_opt.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/writeback.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter_top.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_cut.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/cf_math_pkg.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/defs_div_sqrt_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/control_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/crossbar.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/div_sqrt_top_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_top.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/iteration_div_sqrt_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/lzc.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/norm_div_sqrt_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/nrbd_nrsc_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operandcollector_top.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/preprocess_mvp.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register_flushable.sv"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_adpater.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/define/undefine.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/mshr_backup.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/clz.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/clz_49.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_flow_true.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true_has_flush.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_with_incount_useSRAM.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu_v2.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/vfpu_v2.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul_v2.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/lru_matrix.v"
#    "E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/sm_wrapper_backup.v"
#
#*****************************************************************************************

# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "E:/FPGA/ventus/ventus/relative"

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

# Set the project name
set _xil_proj_name_ "ventus_gpgputest_verilogtcl"

# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set _xil_proj_name_ $::user_project_name
}

variable script_file
set script_file "ventus_fpga.tcl"

# Help information for this script
proc print_help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < $::argc} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
      "--help"         { print_help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"

# Create project
create_project ${_xil_proj_name_} "E:/FPGA/ventus/ventus/ventus_gpgputest_verilogtcl" -part xcvu37p-fsvh2892-2L-e

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Set project properties
set obj [current_project]
set_property -name "board_part" -value "xilinx.com:vcu128:part0:1.0" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
set_property -name "dsa.board_id" -value "vcu128" -objects $obj
set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
set_property -name "dsa.emu_dir" -value "emu" -objects $obj
set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
set_property -name "dsa.flash_size" -value "1024" -objects $obj
set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
set_property -name "dsa.host_interface" -value "pcie" -objects $obj
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
set_property -name "dsa.vendor" -value "xilinx" -objects $obj
set_property -name "dsa.version" -value "0.0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/define/define.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/GPGPU_top.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Listbuffer.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Listbuffer_no_push_opc_put_source.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/MSHR.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Scheduler.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/SourceA.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/addrcalculate.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/allocator_neo.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/alu.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/aluexe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/array_multiplier.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4lite_2_cta.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/shared_memory/bankconflict_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/banked_store.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/bin2one.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/booth.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/branch_back.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/simt_stack/branch_join_stack.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/byte_extract.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cam_allocator.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cam_allocator_neo.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cluster_to_l2_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/collector_unit.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/csr/csrexe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/csr/csrfile.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/cta2warp.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta_interface.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cta_scheduler.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cu_handler.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/dcache_control.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/dcache_wshr.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/decodeUnit.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/directory_test.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/dis_controller.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/dualportSRAM.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fadd_pipe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fadd_pipe_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fadd_s1.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fadd_s2.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/far_path.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fcmp.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fcmp_core.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fcmp_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/fifo.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/fifo_with_count.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/fifo_with_flush.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/find_first.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/fixed_pri_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fma.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fma_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fmul_pipe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fmul_pipe_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s1.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s2.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s3.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fp_to_int.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fp_to_int_core.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fp_to_int_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fpmv.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fpmv_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpuexe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/full_adder.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/gen_data_map_per_byte.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/gen_data_map_same_word.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/gen_imm.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/get_data_access_banken.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/get_entry_status.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/get_entry_status_req.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/get_entry_status_rsp.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/get_setid.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/gpu_interface.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer/ibuffer.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer2issue.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/inflight_wg_buffer.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/input_fifo.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/input_reverse.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/inst_demux.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/instruction_cache.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/int_div.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/int_to_fp_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp_postnorm.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp_prenorm.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/issue.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_dcache.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/l1_mshr.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2_distribute.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/lru_matrix.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/lsu2wb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/lsu_exe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/lza.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/mshr_icache.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/mshr_reg.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/mult_32.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/naivemultiplier.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/near_path.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/one2bin.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operand_arbiter.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/pc_align.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/pc_control.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/pipe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/pop_cnt.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/prefer_select.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/ram.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/resource_table.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/resource_table_group.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/round_robin_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/rounding.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/rsp_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/scalar_fpu.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/scalar_fpu_no_ctrl.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/scalar_regfile_bank.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/scoreboard.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/sfu_exe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/shared_memory/sharemem.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/shift_right_jam.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/shiftboard.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/simt_stack/simt_stack.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sinkA.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sinkD.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer/slowdown.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm2cluster_arb.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/sm_wrapper.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sourceD.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/sram_template.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/sram_template_l1d_tag.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_hasflush_true.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_hasflush_true_no_empty_full.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true_with_count.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_useSRAM.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_useSRAM_with_count.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/tag_access_icache.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/tag_access/tag_access_top_v2.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/tag_access/tag_checker.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/tag_checker_icache.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tc_add_pipe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tc_dot_product.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tc_mul_pipe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tensor_core_exe.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tensor_core_fp32.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/throttling_engine.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/top_resource_table.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu_top.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/vector_regfile_bank.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/vfpu.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul_top.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/wallace_adder_18.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/warp_scheduler.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/wf_done_interface_single.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/wg_resource_table_neo.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/wg_slot_id_convert_opt.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/writeback.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter_top.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_cut.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/cf_math_pkg.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/defs_div_sqrt_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/control_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/crossbar.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/div_sqrt_top_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_top.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/iteration_div_sqrt_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/lzc.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/norm_div_sqrt_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/nrbd_nrsc_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operandcollector_top.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/preprocess_mvp.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register_flushable.sv"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_adpater.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/define/undefine.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/mshr_backup.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/clz.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/clz_49.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_flow_true.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true_has_flush.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_with_incount_useSRAM.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu_v2.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/vfpu_v2.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul_v2.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/lru_matrix.v"] \
 [file normalize "${origin_dir}/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/sm_wrapper_backup.v"] \
]
add_files -norecurse -fileset $obj $files

# Import local files from the original project
set files [list \
 [file normalize "${origin_dir}/ventus_gpgputest_verilogtcl.srcs/sources_1/bd/config_mb/hdl/config_mb_wrapper.v" ]\
]
set imported_files [import_files -fileset sources_1 $files]

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../ventus-gpgpu-verilog-main/src/define/define.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter_top.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_cut.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/cf_math_pkg.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/defs_div_sqrt_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/control_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/crossbar.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/div_sqrt_top_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_top.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/iteration_div_sqrt_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/lzc.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/norm_div_sqrt_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/nrbd_nrsc_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operandcollector_top.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/preprocess_mvp.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register_flushable.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/define/undefine.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog Header" -objects $file_obj
set_property -name "is_global_include" -value "1" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/lru_matrix.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_enabled" -value "0" -objects $file_obj

set file "$origin_dir/../ventus-gpgpu-verilog-main/src/gpgpu_top/sm/sm_wrapper_backup.v"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "is_enabled" -value "0" -objects $file_obj


# Set 'sources_1' fileset file properties for local files
# None

# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "config_mb_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/ventus_gpgputest_verilogtcl.srcs/constrs_1/new/pin_config.xdc"]"
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "new/pin_config.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "target_constrs_file" -value "[get_files *new/pin_config.xdc]" -objects $obj
set_property -name "target_ucf" -value "[get_files *new/pin_config.xdc]" -objects $obj

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "mshr_backup" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj

# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Empty (no sources present)

# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]


# Adding sources referenced in BDs, if not already added
if { [get_files define.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/define/define.v
}
if { [get_files undefine.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/define/undefine.v
}
if { [get_files GPGPU_top.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/GPGPU_top.v
}
if { [get_files Listbuffer.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Listbuffer.v
}
if { [get_files Listbuffer_no_push_opc_put_source.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Listbuffer_no_push_opc_put_source.v
}
if { [get_files MSHR.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/MSHR.v
}
if { [get_files Scheduler.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/Scheduler.v
}
if { [get_files SourceA.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/SourceA.v
}
if { [get_files addrcalculate.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/addrcalculate.v
}
if { [get_files allocator_neo.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/allocator_neo.v
}
if { [get_files alu.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/alu.v
}
if { [get_files aluexe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/aluexe.v
}
if { [get_files array_multiplier.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/array_multiplier.v
}
if { [get_files axi4lite_2_cta.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4lite_2_cta.v
}
if { [get_files bankconflict_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/shared_memory/bankconflict_arb.v
}
if { [get_files banked_store.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/banked_store.v
}
if { [get_files bin2one.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/bin2one.v
}
if { [get_files booth.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/booth.v
}
if { [get_files branch_back.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/branch_back.v
}
if { [get_files branch_join_stack.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/simt_stack/branch_join_stack.v
}
if { [get_files byte_extract.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/byte_extract.v
}
if { [get_files cam_allocator.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cam_allocator.v
}
if { [get_files cam_allocator_neo.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cam_allocator_neo.v
}
if { [get_files cluster_to_l2_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cluster_to_l2_arb.v
}
if { [get_files collector_unit.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/collector_unit.v
}
if { [get_files csrexe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/csr/csrexe.v
}
if { [get_files csrfile.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/csr/csrfile.v
}
if { [get_files cta2warp.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/cta2warp.v
}
if { [get_files cta_interface.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta_interface.v
}
if { [get_files cta_scheduler.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cta_scheduler.v
}
if { [get_files cu_handler.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/cu_handler.v
}
if { [get_files dcache_control.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/dcache_control.v
}
if { [get_files dcache_wshr.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/dcache_wshr.v
}
if { [get_files decodeUnit.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/decodeUnit.v
}
if { [get_files directory_test.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/directory_test.v
}
if { [get_files dis_controller.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/dis_controller.v
}
if { [get_files dualportSRAM.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/dualportSRAM.v
}
if { [get_files fadd_pipe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fadd_pipe.v
}
if { [get_files fadd_pipe_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fadd_pipe_no_ctrl.v
}
if { [get_files fadd_s1.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fadd_s1.v
}
if { [get_files fadd_s2.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fadd_s2.v
}
if { [get_files far_path.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/far_path.v
}
if { [get_files fcmp.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fcmp.v
}
if { [get_files fcmp_core.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fcmp_core.v
}
if { [get_files fcmp_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fcmp_no_ctrl.v
}
if { [get_files fifo.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fifo.v
}
if { [get_files fifo_with_count.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fifo_with_count.v
}
if { [get_files fifo_with_flush.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fifo_with_flush.v
}
if { [get_files find_first.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/find_first.v
}
if { [get_files fixed_pri_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/fixed_pri_arb.v
}
if { [get_files fma.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fma.v
}
if { [get_files fma_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fma_no_ctrl.v
}
if { [get_files fmul_pipe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fmul_pipe.v
}
if { [get_files fmul_pipe_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fmul_pipe_no_ctrl.v
}
if { [get_files fmul_s1.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s1.v
}
if { [get_files fmul_s2.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s2.v
}
if { [get_files fmul_s3.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/fmul_s3.v
}
if { [get_files fp_to_int.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fp_to_int.v
}
if { [get_files fp_to_int_core.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fp_to_int_core.v
}
if { [get_files fp_to_int_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fp_to_int_no_ctrl.v
}
if { [get_files fpmv.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/fpmv.v
}
if { [get_files fpmv_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/fpmv_no_ctrl.v
}
if { [get_files fpuexe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpuexe.v
}
if { [get_files full_adder.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/full_adder.v
}
if { [get_files gen_data_map_per_byte.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/gen_data_map_per_byte.v
}
if { [get_files gen_data_map_same_word.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/gen_data_map_same_word.v
}
if { [get_files gen_imm.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/gen_imm.v
}
if { [get_files get_data_access_banken.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/get_data_access_banken.v
}
if { [get_files get_entry_status.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/get_entry_status.v
}
if { [get_files get_entry_status_req.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/get_entry_status_req.v
}
if { [get_files get_entry_status_rsp.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/get_entry_status_rsp.v
}
if { [get_files get_setid.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/get_setid.v
}
if { [get_files gpu_interface.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/gpu_interface.v
}
if { [get_files ibuffer.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer/ibuffer.v
}
if { [get_files ibuffer2issue.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer2issue.v
}
if { [get_files inflight_wg_buffer.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/inflight_wg_buffer.v
}
if { [get_files input_fifo.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/input_fifo.v
}
if { [get_files input_reverse.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/input_reverse.v
}
if { [get_files inst_demux.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/inst_demux.v
}
if { [get_files instruction_cache.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/instruction_cache.v
}
if { [get_files int_div.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/int_div.v
}
if { [get_files int_to_fp.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp.v
}
if { [get_files int_to_fp_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/int_to_fp_no_ctrl.v
}
if { [get_files int_to_fp_postnorm.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp_postnorm.v
}
if { [get_files int_to_fp_prenorm.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/int_to_fp_prenorm.v
}
if { [get_files issue.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/issue.v
}
if { [get_files l1_dcache.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_dcache.v
}
if { [get_files l1_mshr.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/l1_mshr/l1_mshr.v
}
if { [get_files l1cache_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache_arb.v
}
if { [get_files l2_distribute.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2_distribute.v
}
if { [get_files lru_matrix.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/lru_matrix.v
}
if { [get_files lsu2wb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/lsu2wb.v
}
if { [get_files lsu_exe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/lsu_exe.v
}
if { [get_files lza.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/lza.v
}
if { [get_files mshr_icache.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/mshr_icache.v
}
if { [get_files mshr_reg.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/mshr_reg.v
}
if { [get_files mult_32.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/mult_32.v
}
if { [get_files naivemultiplier.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/naivemultiplier.v
}
if { [get_files near_path.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/near_path.v
}
if { [get_files one2bin.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/one2bin.v
}
if { [get_files operand_arbiter.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operand_arbiter.v
}
if { [get_files pc_align.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/pc_align.v
}
if { [get_files pc_control.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/pc_control.v
}
if { [get_files pipe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/pipe.v
}
if { [get_files pop_cnt.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/pop_cnt.v
}
if { [get_files prefer_select.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/prefer_select.v
}
if { [get_files ram.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/ram.v
}
if { [get_files resource_table.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/resource_table.v
}
if { [get_files resource_table_group.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/resource_table_group.v
}
if { [get_files round_robin_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/round_robin_arb.v
}
if { [get_files rounding.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/rounding.v
}
if { [get_files rsp_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/rsp_arb.v
}
if { [get_files scalar_fpu.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/scalar_fpu.v
}
if { [get_files scalar_fpu_no_ctrl.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu_no_ctrl/scalar_fpu_no_ctrl.v
}
if { [get_files scalar_regfile_bank.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/scalar_regfile_bank.v
}
if { [get_files scoreboard.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/scoreboard.v
}
if { [get_files sfu_exe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/sfu_exe.v
}
if { [get_files sharemem.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/shared_memory/sharemem.v
}
if { [get_files shift_right_jam.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/fpu/common_cells/shift_right_jam.v
}
if { [get_files shiftboard.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/lsu/shiftboard.v
}
if { [get_files simt_stack.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/simt_stack/simt_stack.v
}
if { [get_files sinkA.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sinkA.v
}
if { [get_files sinkD.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sinkD.v
}
if { [get_files slowdown.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/ibuffer/slowdown.v
}
if { [get_files sm2cluster_arb.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm2cluster_arb.v
}
if { [get_files sm_wrapper.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/sm_wrapper.v
}
if { [get_files sourceD.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/l2cache/sourceD.v
}
if { [get_files sram_template.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/sram_template.v
}
if { [get_files sram_template_l1d_tag.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/common/sram_template_l1d_tag.v
}
if { [get_files stream_fifo.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo.v
}
if { [get_files stream_fifo_hasflush_true.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_hasflush_true.v
}
if { [get_files stream_fifo_hasflush_true_no_empty_full.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_hasflush_true_no_empty_full.v
}
if { [get_files stream_fifo_pipe_true.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true.v
}
if { [get_files stream_fifo_pipe_true_with_count.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_pipe_true_with_count.v
}
if { [get_files stream_fifo_useSRAM.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_useSRAM.v
}
if { [get_files stream_fifo_useSRAM_with_count.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/common_cell/stream_fifo_useSRAM_with_count.v
}
if { [get_files tag_access_icache.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/tag_access_icache.v
}
if { [get_files tag_access_top_v2.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/tag_access/tag_access_top_v2.v
}
if { [get_files tag_checker.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/dcache/tag_access/tag_checker.v
}
if { [get_files tag_checker_icache.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/l1cache/icache/tag_checker_icache.v
}
if { [get_files tc_add_pipe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tc_add_pipe.v
}
if { [get_files tc_dot_product.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tc_dot_product.v
}
if { [get_files tc_mul_pipe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tc_mul_pipe.v
}
if { [get_files tensor_core_exe.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tensor_core_exe.v
}
if { [get_files tensor_core_fp32.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/tensor/tensor_core_fp32.v
}
if { [get_files throttling_engine.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/throttling_engine.v
}
if { [get_files top_resource_table.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/top_resource_table.v
}
if { [get_files valu.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu.v
}
if { [get_files valu_top.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/valu/valu_top.v
}
if { [get_files vector_regfile_bank.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/vector_regfile_bank.v
}
if { [get_files vfpu.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/fpu/vfpu.v
}
if { [get_files vmul.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul.v
}
if { [get_files vmul_top.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/vmul_top.v
}
if { [get_files wallace_adder_18.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/vmul/wallace_adder_18.v
}
if { [get_files warp_scheduler.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/warp_scheduler/warp_scheduler.v
}
if { [get_files wf_done_interface_single.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/wf_done_interface_single.v
}
if { [get_files wg_resource_table_neo.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/wg_resource_table_neo.v
}
if { [get_files wg_slot_id_convert_opt.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/cta_top/cta/wg_slot_id_convert_opt.v
}
if { [get_files writeback.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/writeback.v
}
if { [get_files axi4_adapter.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter.sv
}
if { [get_files axi4_adapter_top.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_adapter_top.sv
}
if { [get_files axi4_cut.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/axi4_cut.sv
}
if { [get_files cf_math_pkg.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/cf_math_pkg.sv
}
if { [get_files defs_div_sqrt_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/defs_div_sqrt_mvp.sv
}
if { [get_files control_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/control_mvp.sv
}
if { [get_files crossbar.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/crossbar.sv
}
if { [get_files div_sqrt_top_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/div_sqrt_top_mvp.sv
}
if { [get_files gpgpu_axi_top.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_top.sv
}
if { [get_files iteration_div_sqrt_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/iteration_div_sqrt_mvp.sv
}
if { [get_files lzc.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/lzc.sv
}
if { [get_files norm_div_sqrt_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/norm_div_sqrt_mvp.sv
}
if { [get_files nrbd_nrsc_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/nrbd_nrsc_mvp.sv
}
if { [get_files operandcollector_top.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/operand_collector/operandcollector_top.sv
}
if { [get_files preprocess_mvp.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/sm/pipeline/sfu_v2/float_div_mvp/preprocess_mvp.sv
}
if { [get_files spill_register.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register.sv
}
if { [get_files spill_register_flushable.sv] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/axi4_adapter/spill_register_flushable.sv
}
if { [get_files gpgpu_axi_adpater.v] == "" } {
  import_files -quiet -fileset sources_1 E:/FPGA/ventus/ventus/ventus-gpgpu-verilog-main/src/gpgpu_top/gpgpu_axi_adpater.v
}


# Proc to create BD config_mb
proc cr_bd_config_mb { parentCell } {
# The design that will be created by this Tcl proc contains the following 
# module references:
# gpgpu_axi_adapter_top



  # CHANGE DESIGN NAME HERE
  set design_name config_mb

  common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

  create_bd_design $design_name

  set bCheckIPsPassed 1
  ##################################################################
  # CHECK IPs
  ##################################################################
  set bCheckIPs 1
  if { $bCheckIPs == 1 } {
     set list_check_ips "\ 
  xilinx.com:ip:axi_bram_ctrl:4.1\
  xilinx.com:ip:axi_cdma:4.1\
  xilinx.com:ip:axi_gpio:2.0\
  xilinx.com:ip:smartconnect:1.0\
  xilinx.com:ip:axi_uartlite:2.0\
  xilinx.com:ip:blk_mem_gen:8.4\
  xilinx.com:ip:clk_wiz:6.0\
  xilinx.com:ip:ddr4:2.2\
  xilinx.com:ip:mdm:3.2\
  xilinx.com:ip:microblaze:11.0\
  xilinx.com:ip:proc_sys_reset:5.0\
  xilinx.com:ip:system_ila:1.1\
  xilinx.com:ip:lmb_bram_if_cntlr:4.0\
  xilinx.com:ip:lmb_v10:3.0\
  "

   set list_ips_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

   foreach ip_vlnv $list_check_ips {
      set ip_obj [get_ipdefs -all $ip_vlnv]
      if { $ip_obj eq "" } {
         lappend list_ips_missing $ip_vlnv
      }
   }

   if { $list_ips_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
      set bCheckIPsPassed 0
   }

  }

  ##################################################################
  # CHECK Modules
  ##################################################################
  set bCheckModules 1
  if { $bCheckModules == 1 } {
     set list_check_mods "\ 
  gpgpu_axi_adapter_top\
  "

   set list_mods_missing ""
   common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."

   foreach mod_vlnv $list_check_mods {
      if { [can_resolve_reference $mod_vlnv] == 0 } {
         lappend list_mods_missing $mod_vlnv
      }
   }

   if { $list_mods_missing ne "" } {
      catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
      common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
      set bCheckIPsPassed 0
   }
}

  if { $bCheckIPsPassed != 1 } {
    common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
    return 3
  }

  
# Hierarchical cell: microblaze_0_local_memory
proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } {

  variable script_folder

  if { $parentCell eq "" || $nameHier eq "" } {
     catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"}
     return
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj

  # Create cell and set as current instance
  set hier_obj [create_bd_cell -type hier $nameHier]
  current_bd_instance $hier_obj

  # Create interface pins
  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB

  create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB


  # Create pins
  create_bd_pin -dir I LMB_CLK
  create_bd_pin -dir I SYS_Rst

  # Create instance: blk_mem_gen_0, and set properties
  set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
  set_property -dict [ list \
   CONFIG.Enable_B {Use_ENB_Pin} \
   CONFIG.Memory_Type {True_Dual_Port_RAM} \
   CONFIG.Port_B_Clock {100} \
   CONFIG.Port_B_Enable_Rate {100} \
   CONFIG.Port_B_Write_Rate {50} \
   CONFIG.Use_RSTB_Pin {true} \
 ] $blk_mem_gen_0

  # Create instance: lmb_bram_if_cntlr_0, and set properties
  set lmb_bram_if_cntlr_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 lmb_bram_if_cntlr_0 ]

  # Create instance: lmb_bram_if_cntlr_1, and set properties
  set lmb_bram_if_cntlr_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 lmb_bram_if_cntlr_1 ]

  # Create instance: lmb_v10_0, and set properties
  set lmb_v10_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 lmb_v10_0 ]

  # Create instance: lmb_v10_1, and set properties
  set lmb_v10_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 lmb_v10_1 ]

  # Create interface connections
  connect_bd_intf_net -intf_net Conn [get_bd_intf_pins lmb_bram_if_cntlr_0/SLMB] [get_bd_intf_pins lmb_v10_0/LMB_Sl_0]
  connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins lmb_bram_if_cntlr_1/SLMB] [get_bd_intf_pins lmb_v10_1/LMB_Sl_0]
  connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins ILMB] [get_bd_intf_pins lmb_v10_1/LMB_M]
  connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins DLMB] [get_bd_intf_pins lmb_v10_0/LMB_M]
  connect_bd_intf_net -intf_net lmb_bram_if_cntlr_0_BRAM_PORT [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA] [get_bd_intf_pins lmb_bram_if_cntlr_0/BRAM_PORT]
  connect_bd_intf_net -intf_net lmb_bram_if_cntlr_1_BRAM_PORT [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTB] [get_bd_intf_pins lmb_bram_if_cntlr_1/BRAM_PORT]

  # Create port connections
  connect_bd_net -net LMB_CLK_1 [get_bd_pins LMB_CLK] [get_bd_pins lmb_bram_if_cntlr_0/LMB_Clk] [get_bd_pins lmb_bram_if_cntlr_1/LMB_Clk] [get_bd_pins lmb_v10_0/LMB_Clk] [get_bd_pins lmb_v10_1/LMB_Clk]
  connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins lmb_bram_if_cntlr_0/LMB_Rst] [get_bd_pins lmb_bram_if_cntlr_1/LMB_Rst] [get_bd_pins lmb_v10_0/SYS_Rst] [get_bd_pins lmb_v10_1/SYS_Rst]

  # Restore current instance
  current_bd_instance $oldCurInst
}
  variable script_folder

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports
  set ddr4_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram ]

  set default_100mhz_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_100mhz_clk ]
  set_property -dict [ list \
   CONFIG.FREQ_HZ {100000000} \
   ] $default_100mhz_clk

  set led_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_8bits ]

  set rs232_uart_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart_0 ]


  # Create ports
  set reset_0 [ create_bd_port -dir I -type rst reset_0 ]
  set_property -dict [ list \
   CONFIG.POLARITY {ACTIVE_HIGH} \
 ] $reset_0

  # Create instance: axi_bram_ctrl_0, and set properties
  set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]

  # Create instance: axi_cdma_0, and set properties
  set axi_cdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_cdma:4.1 axi_cdma_0 ]
  set_property -dict [ list \
   CONFIG.C_INCLUDE_SF {1} \
   CONFIG.C_INCLUDE_SG {0} \
 ] $axi_cdma_0

  # Create instance: axi_gpio_0, and set properties
  set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
  set_property -dict [ list \
   CONFIG.C_GPIO_WIDTH {8} \
 ] $axi_gpio_0

  # Create instance: axi_smc, and set properties
  set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
  set_property -dict [ list \
   CONFIG.NUM_CLKS {2} \
   CONFIG.NUM_MI {2} \
   CONFIG.NUM_SI {5} \
 ] $axi_smc

  # Create instance: axi_uartlite_0, and set properties
  set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
  set_property -dict [ list \
   CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
 ] $axi_uartlite_0

  # Create instance: blk_mem_gen_0, and set properties
  set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
  set_property -dict [ list \
   CONFIG.Enable_B {Use_ENB_Pin} \
   CONFIG.Memory_Type {True_Dual_Port_RAM} \
   CONFIG.Port_B_Clock {100} \
   CONFIG.Port_B_Enable_Rate {100} \
   CONFIG.Port_B_Write_Rate {50} \
   CONFIG.Use_RSTB_Pin {true} \
 ] $blk_mem_gen_0

  # Create instance: clk_wiz_0, and set properties
  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
  set_property -dict [ list \
   CONFIG.CLKIN1_JITTER_PS {30.000} \
   CONFIG.CLKIN1_UI_JITTER {30.000} \
   CONFIG.CLKIN2_JITTER_PS {100.000} \
   CONFIG.CLKIN2_UI_JITTER {100.000} \
   CONFIG.CLKOUT1_JITTER {274.534} \
   CONFIG.CLKOUT1_PHASE_ERROR {416.311} \
   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000} \
   CONFIG.JITTER_OPTIONS {PS} \
   CONFIG.MMCM_CLKFBOUT_MULT_F {100.000} \
   CONFIG.MMCM_CLKIN1_PERIOD {3.001} \
   CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
   CONFIG.MMCM_CLKOUT0_DIVIDE_F {21.500} \
   CONFIG.MMCM_DIVCLK_DIVIDE {31} \
   CONFIG.MMCM_REF_JITTER2 {0.010} \
   CONFIG.USE_LOCKED {false} \
   CONFIG.USE_RESET {false} \
 ] $clk_wiz_0

  # Create instance: ddr4_0, and set properties
  set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
  set_property -dict [ list \
   CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
   CONFIG.C0.BANK_GROUP_WIDTH {1} \
   CONFIG.C0.CS_WIDTH {2} \
   CONFIG.C0.DDR4_AxiAddressWidth {32} \
   CONFIG.C0.DDR4_AxiDataWidth {512} \
   CONFIG.C0.DDR4_CLKFBOUT_MULT {10} \
   CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
   CONFIG.C0.DDR4_Clamshell {true} \
   CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
   CONFIG.C0.DDR4_DataWidth {72} \
   CONFIG.C0.DDR4_Ecc {true} \
   CONFIG.C0.DDR4_InputClockPeriod {10000} \
   CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
   CONFIG.C0_CLOCK_BOARD_INTERFACE {default_100mhz_clk} \
   CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \
 ] $ddr4_0

  # Create instance: gpgpu_axi_adapter_top_0, and set properties
  set block_name gpgpu_axi_adapter_top
  set block_cell_name gpgpu_axi_adapter_top_0
  if { [catch {set gpgpu_axi_adapter_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $gpgpu_axi_adapter_top_0 eq "" } {
     catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: mdm_1, and set properties
  set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ]

  # Create instance: microblaze_0, and set properties
  set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 microblaze_0 ]
  set_property -dict [ list \
   CONFIG.C_DEBUG_ENABLED {1} \
   CONFIG.C_D_AXI {1} \
   CONFIG.C_D_LMB {1} \
   CONFIG.C_I_LMB {1} \
   CONFIG.C_USE_DCACHE {1} \
   CONFIG.C_USE_ICACHE {1} \
 ] $microblaze_0

  # Create instance: microblaze_0_axi_periph, and set properties
  set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ]
  set_property -dict [ list \
   CONFIG.NUM_MI {6} \
 ] $microblaze_0_axi_periph

  # Create instance: microblaze_0_local_memory
  create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory

  # Create instance: rst_ddr4_0_100M, and set properties
  set rst_ddr4_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4_0_100M ]

  # Create instance: rst_ddr4_0_333M, and set properties
  set rst_ddr4_0_333M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4_0_333M ]

  # Create instance: system_ila_0, and set properties
  set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_0 ]
  set_property -dict [ list \
   CONFIG.C_BRAM_CNT {6} \
   CONFIG.C_MON_TYPE {INTERFACE} \
   CONFIG.C_NUM_MONITOR_SLOTS {3} \
   CONFIG.C_NUM_OF_PROBES {1} \
   CONFIG.C_SLOT_0_APC_EN {0} \
   CONFIG.C_SLOT_0_AXI_AR_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_AR_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_AW_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_AW_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_B_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_B_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_R_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_R_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_W_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_W_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
   CONFIG.C_SLOT_1_APC_EN {0} \
   CONFIG.C_SLOT_1_AXI_AR_SEL_DATA {1} \
   CONFIG.C_SLOT_1_AXI_AR_SEL_TRIG {1} \
   CONFIG.C_SLOT_1_AXI_AW_SEL_DATA {1} \
   CONFIG.C_SLOT_1_AXI_AW_SEL_TRIG {1} \
   CONFIG.C_SLOT_1_AXI_B_SEL_DATA {1} \
   CONFIG.C_SLOT_1_AXI_B_SEL_TRIG {1} \
   CONFIG.C_SLOT_1_AXI_R_SEL_DATA {1} \
   CONFIG.C_SLOT_1_AXI_R_SEL_TRIG {1} \
   CONFIG.C_SLOT_1_AXI_W_SEL_DATA {1} \
   CONFIG.C_SLOT_1_AXI_W_SEL_TRIG {1} \
   CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
   CONFIG.C_SLOT_1_TYPE {0} \
   CONFIG.C_SLOT_2_APC_EN {0} \
   CONFIG.C_SLOT_2_AXI_AR_SEL_DATA {1} \
   CONFIG.C_SLOT_2_AXI_AR_SEL_TRIG {1} \
   CONFIG.C_SLOT_2_AXI_AW_SEL_DATA {1} \
   CONFIG.C_SLOT_2_AXI_AW_SEL_TRIG {1} \
   CONFIG.C_SLOT_2_AXI_B_SEL_DATA {1} \
   CONFIG.C_SLOT_2_AXI_B_SEL_TRIG {1} \
   CONFIG.C_SLOT_2_AXI_R_SEL_DATA {1} \
   CONFIG.C_SLOT_2_AXI_R_SEL_TRIG {1} \
   CONFIG.C_SLOT_2_AXI_W_SEL_DATA {1} \
   CONFIG.C_SLOT_2_AXI_W_SEL_TRIG {1} \
   CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
   CONFIG.C_SLOT_2_TYPE {0} \
   CONFIG.C_SLOT_3_APC_EN {0} \
   CONFIG.C_SLOT_3_AXI_AR_SEL_DATA {1} \
   CONFIG.C_SLOT_3_AXI_AR_SEL_TRIG {1} \
   CONFIG.C_SLOT_3_AXI_AW_SEL_DATA {1} \
   CONFIG.C_SLOT_3_AXI_AW_SEL_TRIG {1} \
   CONFIG.C_SLOT_3_AXI_B_SEL_DATA {1} \
   CONFIG.C_SLOT_3_AXI_B_SEL_TRIG {1} \
   CONFIG.C_SLOT_3_AXI_R_SEL_DATA {1} \
   CONFIG.C_SLOT_3_AXI_R_SEL_TRIG {1} \
   CONFIG.C_SLOT_3_AXI_W_SEL_DATA {1} \
   CONFIG.C_SLOT_3_AXI_W_SEL_TRIG {1} \
   CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
 ] $system_ila_0

  # Create instance: system_ila_1, and set properties
  set system_ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.1 system_ila_1 ]
  set_property -dict [ list \
   CONFIG.C_MON_TYPE {INTERFACE} \
   CONFIG.C_NUM_MONITOR_SLOTS {1} \
   CONFIG.C_SLOT_0_APC_EN {0} \
   CONFIG.C_SLOT_0_AXI_AR_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_AR_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_AW_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_AW_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_B_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_B_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_R_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_R_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_AXI_W_SEL_DATA {1} \
   CONFIG.C_SLOT_0_AXI_W_SEL_TRIG {1} \
   CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:aximm_rtl:1.0} \
 ] $system_ila_1

  # Create interface connections
  connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
  connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTB]
  connect_bd_intf_net -intf_net axi_cdma_0_M_AXI [get_bd_intf_pins axi_cdma_0/M_AXI] [get_bd_intf_pins axi_smc/S02_AXI]
  connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports led_8bits] [get_bd_intf_pins axi_gpio_0/GPIO]
  connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI]
connect_bd_intf_net -intf_net [get_bd_intf_nets axi_smc_M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] [get_bd_intf_pins system_ila_1/SLOT_0_AXI]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets axi_smc_M00_AXI]
  connect_bd_intf_net -intf_net axi_smc_M01_AXI [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] [get_bd_intf_pins axi_smc/M01_AXI]
  connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports rs232_uart_0] [get_bd_intf_pins axi_uartlite_0/UART]
connect_bd_intf_net -intf_net axi_wrapper_0_0_m_axi [get_bd_intf_pins axi_smc/S03_AXI] [get_bd_intf_pins system_ila_0/SLOT_1_AXI]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets axi_wrapper_0_0_m_axi]
  connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram] [get_bd_intf_pins ddr4_0/C0_DDR4]
  connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK]
  connect_bd_intf_net -intf_net gpgpu_axi_adapter_top_0_m_axi [get_bd_intf_pins axi_smc/S04_AXI] [get_bd_intf_pins gpgpu_axi_adapter_top_0/m_axi]
  connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC]
  connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC]
  connect_bd_intf_net -intf_net microblaze_0_axi_dp [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI]
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_cdma_0/S_AXI_LITE] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI]
connect_bd_intf_net -intf_net [get_bd_intf_nets microblaze_0_axi_periph_M00_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] [get_bd_intf_pins system_ila_0/SLOT_0_AXI]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets microblaze_0_axi_periph_M00_AXI]
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI]
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI]
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI]
connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] [get_bd_intf_pins system_ila_0/SLOT_2_AXI]
  set_property HDL_ATTRIBUTE.DEBUG {true} [get_bd_intf_nets microblaze_0_axi_periph_M04_AXI]
  connect_bd_intf_net -intf_net microblaze_0_axi_periph_M05_AXI [get_bd_intf_pins gpgpu_axi_adapter_top_0/s_axilite] [get_bd_intf_pins microblaze_0_axi_periph/M05_AXI]
  connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG]
  connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB]
  connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB]

  # Create port connections
  connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_cdma_0/m_axi_aclk] [get_bd_pins axi_cdma_0/s_axi_lite_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins gpgpu_axi_adapter_top_0/clk] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/M05_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_CLK] [get_bd_pins rst_ddr4_0_100M/slowest_sync_clk] [get_bd_pins system_ila_0/clk]
  connect_bd_net -net ddr4_0_c0_ddr4_ui_clk1 [get_bd_pins axi_smc/aclk1] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins rst_ddr4_0_333M/slowest_sync_clk] [get_bd_pins system_ila_1/clk]
  connect_bd_net -net mdm_1_Debug_SYS_Rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_ddr4_0_100M/mb_debug_sys_rst]
  connect_bd_net -net reset_0_1 [get_bd_ports reset_0] [get_bd_pins ddr4_0/sys_rst] [get_bd_pins rst_ddr4_0_100M/ext_reset_in] [get_bd_pins rst_ddr4_0_333M/ext_reset_in]
  connect_bd_net -net rst_ddr4_0_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_ddr4_0_100M/bus_struct_reset]
  connect_bd_net -net rst_ddr4_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_ddr4_0_100M/mb_reset]
  connect_bd_net -net rst_ddr4_0_100M_peripheral_aresetn [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_cdma_0/s_axi_lite_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins gpgpu_axi_adapter_top_0/rst_n] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/M05_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ddr4_0_100M/peripheral_aresetn] [get_bd_pins system_ila_0/resetn]
  connect_bd_net -net rst_ddr4_0_333M_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins rst_ddr4_0_333M/peripheral_aresetn] [get_bd_pins system_ila_1/resetn]

  # Create address segments
  create_bd_addr_seg -range 0x00200000 -offset 0x70000000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
  create_bd_addr_seg -range 0x80000000 -offset 0x80000000 [get_bd_addr_spaces axi_cdma_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK
  create_bd_addr_seg -range 0x00200000 -offset 0x70000000 [get_bd_addr_spaces gpgpu_axi_adapter_top_0/m_axi] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
  create_bd_addr_seg -range 0x80000000 -offset 0x80000000 [get_bd_addr_spaces gpgpu_axi_adapter_top_0/m_axi] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK
  create_bd_addr_seg -range 0x00200000 -offset 0x70000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
  create_bd_addr_seg -range 0x00200000 -offset 0x70000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] SEG_axi_bram_ctrl_0_Mem0
  create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_cdma_0/S_AXI_LITE/Reg] SEG_axi_cdma_0_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
  create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg
  create_bd_addr_seg -range 0x80000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK
  create_bd_addr_seg -range 0x80000000 -offset 0x80000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK
  create_bd_addr_seg -range 0x00100000 -offset 0x41300000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] SEG_ddr4_0_C0_REG
  create_bd_addr_seg -range 0x20000000 -offset 0x20000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs gpgpu_axi_adapter_top_0/s_axilite/reg0] SEG_gpgpu_axi_adapter_top_0_reg0
  create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/lmb_bram_if_cntlr_0/SLMB/Mem] SEG_lmb_bram_if_cntlr_0_Mem
  create_bd_addr_seg -range 0x00010000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/lmb_bram_if_cntlr_1/SLMB/Mem] SEG_lmb_bram_if_cntlr_1_Mem

  # Perform GUI Layout
  regenerate_bd_layout -layout_string {
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.0.19  2019-03-26 bk=1.5019 VDI=41 GEI=35 GUI=JA:9.0 non-TLS
#  -string -flagsOSRD
preplace port ddr4_sdram -pg 1 -lvl 8 -x 3000 -y 260 -defaultsOSRD
preplace port default_100mhz_clk -pg 1 -lvl 0 -x -40 -y 440 -defaultsOSRD
preplace port led_8bits -pg 1 -lvl 8 -x 3000 -y 740 -defaultsOSRD
preplace port rs232_uart_0 -pg 1 -lvl 8 -x 3000 -y 590 -defaultsOSRD
preplace port reset_0 -pg 1 -lvl 0 -x -40 -y 750 -defaultsOSRD
preplace inst microblaze_0_local_memory -pg 1 -lvl 4 -x 1580 -y 660 -defaultsOSRD
preplace inst gpgpu_axi_adapter_top_0 -pg 1 -lvl 5 -x 1960 -y 450 -defaultsOSRD
preplace inst axi_cdma_0 -pg 1 -lvl 5 -x 1960 -y 160 -defaultsOSRD
preplace inst mdm_1 -pg 1 -lvl 2 -x 670 -y 540 -defaultsOSRD
preplace inst microblaze_0 -pg 1 -lvl 3 -x 1120 -y 540 -defaultsOSRD
preplace inst microblaze_0_axi_periph -pg 1 -lvl 4 -x 1580 -y 220 -defaultsOSRD
preplace inst system_ila_0 -pg 1 -lvl 6 -x 2340 -y 190 -defaultsOSRD
preplace inst system_ila_1 -pg 1 -lvl 7 -x 2790 -y 140 -defaultsOSRD
preplace inst axi_gpio_0 -pg 1 -lvl 7 -x 2790 -y 740 -defaultsOSRD
preplace inst axi_smc -pg 1 -lvl 6 -x 2340 -y 430 -defaultsOSRD
preplace inst axi_uartlite_0 -pg 1 -lvl 7 -x 2790 -y 600 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 360 -y 690 -defaultsOSRD
preplace inst ddr4_0 -pg 1 -lvl 7 -x 2790 -y 330 -defaultsOSRD
preplace inst rst_ddr4_0_100M -pg 1 -lvl 2 -x 670 -y 730 -defaultsOSRD
preplace inst rst_ddr4_0_333M -pg 1 -lvl 3 -x 1120 -y 890 -defaultsOSRD
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 5 -x 1960 -y 690 -defaultsOSRD
preplace inst blk_mem_gen_0 -pg 1 -lvl 6 -x 2340 -y 710 -defaultsOSRD
preplace netloc ddr4_0_c0_ddr4_ui_clk 1 1 6 460 630 880 640 1430 0 1750 310 2160 600 2540
preplace netloc ddr4_0_c0_ddr4_ui_clk1 1 0 8 -20 840 NJ 840 860 280 1400 -40 NJ -40 2150 70 2550 60 2980
preplace netloc mdm_1_Debug_SYS_Rst 1 1 2 470 620 840
preplace netloc reset_0_1 1 0 7 NJ 750 460 830 880 650 1370J 570 NJ 570 NJ 570 2550
preplace netloc rst_ddr4_0_100M_bus_struct_reset 1 2 2 NJ 710 1430
preplace netloc rst_ddr4_0_100M_mb_reset 1 2 1 870 570n
preplace netloc rst_ddr4_0_100M_peripheral_aresetn 1 2 5 850J 440 1370 -10 1760 300 2130 610 2480
preplace netloc rst_ddr4_0_333M_peripheral_aresetn 1 3 4 1410 -20 NJ -20 NJ -20 2530
preplace netloc axi_smc_M00_AXI 1 6 1 2520 120n
preplace netloc ddr4_0_C0_DDR4 1 7 1 NJ 260
preplace netloc microblaze_0_ilmb_1 1 3 1 1390 520n
preplace netloc microblaze_0_axi_periph_M05_AXI 1 4 1 1740 270n
preplace netloc microblaze_0_axi_periph_M03_AXI 1 4 3 1770 280 2140J 300 2500J
preplace netloc microblaze_0_axi_periph_M01_AXI 1 4 3 1730 60 NJ 60 2510J
preplace netloc axi_gpio_0_GPIO 1 7 1 NJ 740
preplace netloc microblaze_0_debug 1 2 1 N 530
preplace netloc gpgpu_axi_adapter_top_0_m_axi 1 5 1 N 440
preplace netloc microblaze_0_M_AXI_DC 1 3 3 1360J -30 NJ -30 2170
preplace netloc microblaze_0_axi_periph_M00_AXI 1 4 2 1740 70 2130
preplace netloc axi_wrapper_0_0_m_axi 1 5 1 2180 170n
preplace netloc microblaze_0_M_AXI_IC 1 3 3 1420J 440 1780J 370 2110
preplace netloc microblaze_0_axi_periph_M02_AXI 1 4 3 1780 290 NJ 290 2490J
preplace netloc axi_cdma_0_M_AXI 1 5 1 2120 150n
preplace netloc microblaze_0_axi_periph_M04_AXI 1 4 2 NJ 250 2110
preplace netloc microblaze_0_axi_dp 1 3 1 1380 60n
preplace netloc microblaze_0_dlmb_1 1 3 1 1400 500n
preplace netloc default_100mhz_clk_1 1 0 7 -20J -50 NJ -50 NJ -50 NJ -50 NJ -50 NJ -50 2540J
preplace netloc axi_uartlite_0_UART 1 7 1 NJ 590
preplace netloc axi_smc_M01_AXI 1 4 3 1780 590 NJ 590 2480
preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 5 1 2120 700n
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 5 1 2160 680n
levelinfo -pg 1 -40 360 670 1120 1580 1960 2340 2790 3000
pagesize -pg 1 -db -bbox -sgen -220 -260 3140 990
"
}

  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
  close_bd_design $design_name 
}
# End of cr_bd_config_mb()
cr_bd_config_mb ""
set_property REGISTERED_WITH_MANAGER "1" [get_files config_mb.bd ] 
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files config_mb.bd ] 

# Create 'synth_gpgpu' run (if not found)
if {[string equal [get_runs -quiet synth_gpgpu] ""]} {
    create_run -name synth_gpgpu -part xcvu37p-fsvh2892-2L-e -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_gpgpu]
  set_property flow "Vivado Synthesis 2019" [get_runs synth_gpgpu]
}
set obj [get_runs synth_gpgpu]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Synthesis Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'synth_gpgpu_synth_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs synth_gpgpu] synth_gpgpu_synth_report_utilization_0] "" ] } {
  create_report_config -report_name synth_gpgpu_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_gpgpu
}
set obj [get_report_configs -of_objects [get_runs synth_gpgpu] synth_gpgpu_synth_report_utilization_0]
if { $obj != "" } {

}
set obj [get_runs synth_gpgpu]
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj

# set the current synth run
current_run -synthesis [get_runs synth_gpgpu]

# Create 'impl_2' run (if not found)
if {[string equal [get_runs -quiet impl_2] ""]} {
    create_run -name impl_2 -part xcvu37p-fsvh2892-2L-e -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_gpgpu
} else {
  set_property strategy "Vivado Implementation Defaults" [get_runs impl_2]
  set_property flow "Vivado Implementation 2019" [get_runs impl_2]
}
set obj [get_runs impl_2]
set_property set_report_strategy_name 1 $obj
set_property report_strategy {Vivado Implementation Default Reports} $obj
set_property set_report_strategy_name 0 $obj
# Create 'impl_2_init_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_init_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_init_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_opt_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_drc_0] "" ] } {
  create_report_config -report_name impl_2_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_drc_0]
if { $obj != "" } {

}
# Create 'impl_2_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_place_report_io_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_io_0] "" ] } {
  create_report_config -report_name impl_2_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_io_0]
if { $obj != "" } {

}
# Create 'impl_2_place_report_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_utilization_0] "" ] } {
  create_report_config -report_name impl_2_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_utilization_0]
if { $obj != "" } {

}
# Create 'impl_2_place_report_control_sets_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_control_sets_0] "" ] } {
  create_report_config -report_name impl_2_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_control_sets_0]
if { $obj != "" } {
set_property -name "options.verbose" -value "1" -objects $obj

}
# Create 'impl_2_place_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_2_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj

}
# Create 'impl_2_place_report_incremental_reuse_1' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_1] "" ] } {
  create_report_config -report_name impl_2_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_incremental_reuse_1]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj

}
# Create 'impl_2_place_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_place_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_post_place_power_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_post_place_power_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_post_place_power_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "is_enabled" -value "0" -objects $obj
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_route_report_drc_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_drc_0] "" ] } {
  create_report_config -report_name impl_2_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_drc_0]
if { $obj != "" } {

}
# Create 'impl_2_route_report_methodology_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_methodology_0] "" ] } {
  create_report_config -report_name impl_2_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_methodology_0]
if { $obj != "" } {

}
# Create 'impl_2_route_report_power_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_power_0] "" ] } {
  create_report_config -report_name impl_2_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_power_0]
if { $obj != "" } {

}
# Create 'impl_2_route_report_route_status_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_route_status_0] "" ] } {
  create_report_config -report_name impl_2_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_route_status_0]
if { $obj != "" } {

}
# Create 'impl_2_route_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj

}
# Create 'impl_2_route_report_incremental_reuse_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_incremental_reuse_0] "" ] } {
  create_report_config -report_name impl_2_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_incremental_reuse_0]
if { $obj != "" } {

}
# Create 'impl_2_route_report_clock_utilization_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_clock_utilization_0] "" ] } {
  create_report_config -report_name impl_2_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_clock_utilization_0]
if { $obj != "" } {

}
# Create 'impl_2_route_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_2_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_route_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
# Create 'impl_2_post_route_phys_opt_report_timing_summary_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_timing_summary_0] "" ] } {
  create_report_config -report_name impl_2_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_timing_summary_0]
if { $obj != "" } {
set_property -name "options.max_paths" -value "10" -objects $obj
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
# Create 'impl_2_post_route_phys_opt_report_bus_skew_0' report (if not found)
if { [ string equal [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_bus_skew_0] "" ] } {
  create_report_config -report_name impl_2_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_2
}
set obj [get_report_configs -of_objects [get_runs impl_2] impl_2_post_route_phys_opt_report_bus_skew_0]
if { $obj != "" } {
set_property -name "options.warn_on_violation" -value "1" -objects $obj

}
set obj [get_runs impl_2]
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj

# set the current impl run
current_run -implementation [get_runs impl_2]

puts "INFO: Project created:${_xil_proj_name_}"
# Create 'drc_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
create_dashboard_gadget -name {drc_1} -type drc
}
set obj [get_dashboard_gadgets [ list "drc_1" ] ]

# Create 'methodology_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
create_dashboard_gadget -name {methodology_1} -type methodology
}
set obj [get_dashboard_gadgets [ list "methodology_1" ] ]

# Create 'power_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
create_dashboard_gadget -name {power_1} -type power
}
set obj [get_dashboard_gadgets [ list "power_1" ] ]

# Create 'timing_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
create_dashboard_gadget -name {timing_1} -type timing
}
set obj [get_dashboard_gadgets [ list "timing_1" ] ]

# Create 'utilization_1' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
create_dashboard_gadget -name {utilization_1} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
set_property -name "run.step" -value "synth_design" -objects $obj
set_property -name "run.type" -value "synthesis" -objects $obj

# Create 'utilization_2' gadget (if not found)
if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
create_dashboard_gadget -name {utilization_2} -type utilization
}
set obj [get_dashboard_gadgets [ list "utilization_2" ] ]

move_dashboard_gadget -name {utilization_1} -row 0 -col 0
move_dashboard_gadget -name {power_1} -row 1 -col 0
move_dashboard_gadget -name {drc_1} -row 2 -col 0
move_dashboard_gadget -name {timing_1} -row 0 -col 1
move_dashboard_gadget -name {utilization_2} -row 1 -col 1
move_dashboard_gadget -name {methodology_1} -row 2 -col 1