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8dc19e4 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 | // 4-bit modulo 16 binary counter with parallel load, synchronous clear
module ttl_74163 #(parameter WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0)
(
input Clear_bar,
input Load_bar,
input ENT,
input ENP,
input [WIDTH-1:0] D,
input Clk,
output RCO,
output [WIDTH-1:0] Q
);
//------------------------------------------------//
wire RCO_current;
reg [WIDTH-1:0] Q_current;
wire [WIDTH-1:0] Q_next;
assign Q_next = Q_current + 1;
always @(posedge Clk)
begin
if (!Clear_bar)
begin
Q_current <= {WIDTH{1'b0}};
end
else
begin
if (!Load_bar)
begin
Q_current <= D;
end
if (Load_bar && ENT && ENP)
begin
Q_current <= Q_next;
end
end
end
// output
assign RCO_current = ENT && (&Q_current);
//------------------------------------------------//
assign #(DELAY_RISE, DELAY_FALL) RCO = RCO_current;
assign #(DELAY_RISE, DELAY_FALL) Q = Q_current;
endmodule
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