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55acfed | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 | `include "./../Register file/REG_FILE.v"
`include "./../ALU/ALU.v"
module DATAPATH(
input [4:0]read_reg_num1,
input [4:0]read_reg_num2,
input [4:0]write_reg,
input [3:0]alu_control,
input regwrite,
input clock,
input reset,
output zero_flag
);
// Declaring internal wires that carry data
wire [31:0]read_data1;
wire [31:0]read_data2;
wire [31:0]write_data;
// Instantiating the register file
REG_FILE reg_file_module(
read_reg_num1,
read_reg_num2,
write_reg,
write_data,
read_data1,
read_data2,
regwrite,
clock,
reset
);
// Instanting ALU
ALU alu_module(read_data1, read_data2, alu_control, write_data, zero_flag);
endmodule |