File size: 417 Bytes
1893362 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 | module trigger_led
(
input trigger,
input clock,
input reset,
output reg led
);
reg [23:0] counter;
always @(posedge trigger or negedge clock) begin
if (trigger) begin
led <= 1;
counter <= 1_000_000;
end else begin
if (~reset) begin
counter <= 0;
led <= 0;
end else begin
if (counter == 0) begin
led <= 0;
end
counter <= counter - 1;
end
end
end
endmodule
|