File size: 1,520 Bytes
8dc19e4 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 | // Test: Hex buffer/driver (OC)
module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 7;
// DUT inputs
reg [BLOCKS-1:0] A;
// DUT outputs
wire [BLOCKS-1:0] Y;
// DUT
ttl_7407 #(.BLOCKS(BLOCKS), .DELAY_RISE(2), .DELAY_FALL(3)) dut(
.A(A),
.Y(Y)
);
initial
begin
integer i;
$dumpfile("7407-tb.vcd");
$dumpvars;
// all zeroes -> 0
for (i = 0; i < BLOCKS; i++)
A[i] = 1'b0;
#5
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b0, "Test 1");
#0
// single bit change to one causes -> 1, others unchanged
A[1] = 1'b1;
#5
tbassert(Y[0] == 1'b0, "Test 2");
tbassert(Y[1] == 1'b1, "Test 2");
tbassert(Y[2] == 1'b0, "Test 2");
tbassert(Y[3] == 1'b0, "Test 2");
#0
// other bit change to one causes -> 1, others unchanged
A[6] = 1'b1;
#5
tbassert(Y[0] == 1'b0, "Test 3");
tbassert(Y[1] == 1'b1, "Test 3");
tbassert(Y[4] == 1'b0, "Test 3");
tbassert(Y[5] == 1'b0, "Test 3");
tbassert(Y[6] == 1'b1, "Test 3");
#0
// all ones -> 1
for (i = 0; i < BLOCKS; i++)
A[i] = 1'b1;
#5
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b1, "Test 4");
#0
// single bit change to zero causes -> 0, others unchanged
A[3] = 1'b0;
#5
tbassert(Y == 7'b1110111, "Test 5");
#0
// mixed bits causes both -> 0, 1
A = 7'b0101101;
#6
tbassert(Y == 7'b0101101, "Test 6");
tbassert(Y == A, "Test 6");
#0
// all input bits transition from previous
A = 7'b1010010;
#5
tbassert(Y == 7'b1010010, "Test 7");
tbassert(Y == A, "Test 7");
#10
$finish;
end
endmodule
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