File size: 3,590 Bytes
8dc19e4 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | // Test: Quad 2-input NAND gate
module test;
`TBASSERT_METHOD(tbassert)
localparam BLOCKS = 5;
localparam WIDTH_IN = 2;
// DUT inputs
reg [BLOCKS*WIDTH_IN-1:0] A;
// DUT outputs
wire [BLOCKS-1:0] Y;
// DUT
ttl_7400 #(.BLOCKS(BLOCKS), .WIDTH_IN(WIDTH_IN), .DELAY_RISE(5), .DELAY_FALL(3)) dut(
.A_2D(A),
.Y(Y)
);
initial
begin
reg [WIDTH_IN-1:0] Block1;
reg [WIDTH_IN-1:0] Block2;
reg [WIDTH_IN-1:0] Block3;
reg [WIDTH_IN-1:0] Block4;
reg [WIDTH_IN-1:0] Block5;
integer i;
$dumpfile("7400-tb.vcd");
$dumpvars;
// all ones -> 0, enough time for output to fall but not to rise
Block1 = {WIDTH_IN{1'b1}};
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#4
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b0, "Test 1");
#0
// all zeroes -> 1, enough time for output to rise
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = {WIDTH_IN{1'b0}};
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#6
for (i = 0; i < BLOCKS; i++)
tbassert(Y[i] == 1'b1, "Test 2");
#0
// only a single bit causes -> 1
Block1 = 2'b10;
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00001, "Test 3");
#0
// same on the other inputs
Block1 = 2'b01;
Block2 = {WIDTH_IN{1'b1}};
Block3 = {WIDTH_IN{1'b1}};
Block4 = {WIDTH_IN{1'b1}};
Block5 = {WIDTH_IN{1'b1}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b00001, "Test 4");
#0
// only a pair of bits causes -> 0
Block1 = {WIDTH_IN{1'b0}};
Block2 = {WIDTH_IN{1'b0}};
Block3 = 2'b11;
Block4 = {WIDTH_IN{1'b0}};
Block5 = {WIDTH_IN{1'b0}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11011, "Test 5");
#0
// zeroes on either side and all ones causes -> 1
Block1 = 2'b10;
Block2 = 2'b10;
Block3 = 2'b10;
Block4 = 2'b10;
Block5 = 2'b10;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 6");
#0
// same on the other inputs
Block1 = 2'b01;
Block2 = 2'b01;
Block3 = 2'b01;
Block4 = 2'b01;
Block5 = 2'b01;
A = {Block5, Block4, Block3, Block2, Block1};
#10
tbassert(Y == 5'b11111, "Test 7");
#0
// mixed bits causes both -> 0, 1
Block1 = 2'b00;
Block2 = 2'b01;
Block3 = 2'b00;
Block4 = 2'b11;
Block5 = 2'b10;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10111, "Test 8");
#0
// same on the other inputs
Block1 = 2'b00;
Block2 = 2'b10;
Block3 = 2'b00;
Block4 = 2'b11;
Block5 = 2'b01;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b10111, "Test 9");
#0
// all input bits transition from previous
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b11;
Block4 = 2'b00;
Block5 = 2'b10;
A = {Block5, Block4, Block3, Block2, Block1};
#6
tbassert(Y == 5'b11010, "Test 10");
#0
// timing: clear inputs, then must wait for outputs to transition
Block1 = {WIDTH_IN{1'bx}};
Block2 = {WIDTH_IN{1'bx}};
Block3 = {WIDTH_IN{1'bx}};
Block4 = {WIDTH_IN{1'bx}};
Block5 = {WIDTH_IN{1'bx}};
A = {Block5, Block4, Block3, Block2, Block1};
#10
Block1 = 2'b11;
Block2 = 2'b01;
Block3 = 2'b11;
Block4 = 2'b00;
Block5 = 2'b10;
A = {Block5, Block4, Block3, Block2, Block1};
#2
tbassert(Y === 5'bxxxxx, "Test 11");
#4
tbassert(Y == 5'b11010, "Test 11");
#10
$finish;
end
endmodule
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