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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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verilog_data-1
/
SymbioticEDA_riscv-formal
/
tests
/
semantics
14.1 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
8d16be2
verified
6 days ago
.gitignore
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25 Bytes
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
6 days ago
Makefile
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570 Bytes
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
6 days ago
cexformat.py
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3.81 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
6 days ago
makejob.py
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1.45 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
6 days ago
top.sv
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8.25 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
6 days ago
