Hugging Face
Models
Datasets
Spaces
Buckets
new
Docs
Enterprise
Pricing
Website
Tasks
HuggingChat
Collections
Languages
Organizations
Community
Blog
Posts
Daily Papers
Hardware
Learn
Discord
Forum
GitHub
Solutions
Team & Enterprise
Hugging Face PRO
Enterprise Support
Inference Providers
Inference Endpoints
Storage Buckets
Log In
Sign Up
Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
like
0
Dataset card
Files
Files and versions
xet
Community
main
verilog_data-1
/
SymbioticEDA_riscv-formal
/
checks
109 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
8d16be2
verified
4 days ago
genchecks.py
Safe
18.4 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_causal_check.sv
Safe
2.15 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_channel.sv
Safe
3.39 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_cover_check.sv
Safe
3.28 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_csrw_check.sv
Safe
7.01 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_dmem_check.sv
Safe
1.92 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_hang_check.sv
Safe
1.69 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_ill_check.sv
Safe
3.52 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_imem_check.sv
Safe
1.86 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_insn_check.sv
Safe
7.93 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_liveness_check.sv
Safe
1.57 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_macros.py
19.3 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_macros.vh
25.6 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_pc_bwd_check.sv
Safe
2.15 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_pc_fwd_check.sv
Safe
2.15 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_reg_check.sv
Safe
2.55 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_testbench.sv
Safe
2.87 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
rvfi_unique_check.sv
Safe
1.58 kB
Add batch 1 (fguzman82_gateGPT, dtysky_FPGA-Imaging-Library, SymbioticEDA_riscv-formal, ultraembedded_core_ddr3_controller, seldridge_verilog)
4 days ago
