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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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34a77e1
verilog_data-1
/
Evensgn_RISC-V-CPU
/
src
/
cpu
84.1 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
df0a64a
verified
8 days ago
library
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
no use
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
cache.v
Safe
11.5 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
cpu.v
Safe
2.73 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
ctrl.v
Safe
687 Bytes
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
defines.v
Safe
3.52 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
mem_ctrl.v
Safe
6.14 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
reg_ex_mem.v
Safe
1.14 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
reg_id_ex.v
Safe
1.46 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
reg_if_id.v
Safe
564 Bytes
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
reg_mem_wb.v
Safe
723 Bytes
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
reg_pc.v
Safe
941 Bytes
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
regfile.v
Safe
1.12 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
riscv_cpu.v
Safe
9.91 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
simple_ram.v
Safe
1.03 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
stage_ex.v
Safe
3.24 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
stage_id.v
Safe
10.5 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
stage_if.v
Safe
1.69 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
stage_mem.v
Safe
4.49 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
uart_trans.v
Safe
3.86 kB
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
utility.v
Safe
547 Bytes
Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)
8 days ago
