verilog_data-1 / IBM_AccDNN

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History: 1 commit

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Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN)

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bin
Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN) 5 days ago
conf
Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN) 5 days ago
example
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layers
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lib
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sim
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tools
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util
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web
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LICENSE

11.4 kB
Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN) 5 days ago
README.md

11.9 kB
Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN) 5 days ago
chip_define.py

84 Bytes
Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN) 5 days ago
codegen.py

2.64 kB
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freqency.py

2.93 kB
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model.py

42.2 kB
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service.py

7.11 kB
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settings.py

5.75 kB
Add batch 6 (secworks_aes, T-K-233_RISC-V-Single-Cycle-CPU, wuxx_icesugar, nand2mario_nestang, IBM_AccDNN) 5 days ago