{ "name": "fpga-support", "displayName": "Digital IDE", "description": "Design For Digital Development", "publisher": "sterben", "homepage": "https://github.com/Bestduan/Digital-IDE", "version": "0.2.6", "main": "./out/extension", "icon": "images/DIDE.png", "keywords": [ "FPGA Develop Support", "FPGA", "ASIC", "IC", "Digital", "HDL", "Systemverilog", "Verilog", "VHDL", "Vivado", "Xilinx" ], "repository": { "type": "git", "url": "https://github.com/Bestduan/Digital-IDE" }, "bugs": { "url": "https://github.com/Bestduan/Digital-IDE/issues" }, "engines": { "vscode": "^1.42.1" }, "categories": [ "Extension Packs", "Programming Languages", "Snippets" ], "activationEvents": [ "*" ], "contributes": { "configuration": { "title": "DIDE", "properties": { "HDL.linting.vlog.linter": { "scope": "window", "type": "string", "enum": [ "vivado", "modelsim", "iverilog", "verible", "verilator", "default" ], "default": "vivado", "description": "Select the verilog or systemverilog linter." }, "HDL.linting.vhdl.linter": { "scope": "window", "type": "string", "enum": [ "vivado", "modelsim", "ghdl", "default" ], "default": "vivado", "description": "Select the vhdl linter." }, "HDL.linting.runFilePath": { "scope": "window", "type": "string", "default": "", "description": "Simulate tool will be run at the file location for linting. Else it will be run at workspace folder." }, "HDL.linting.ghdl.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add ghdl arguments here. They will be added to ghdl while linting." }, "HDL.linting.iverilog.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add Icarus Verilog arguments here (like macros). They will be added to Icarus Verilog while linting." }, "HDL.linting.vivado.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add Vivado arguments here. They will be added to Vivado while linting." }, "HDL.linting.modelsim.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add Modelsim arguments here. They will be added to Modelsim while linting." }, "HDL.linting.verible.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add verible arguments here. They will be added to verible while linting." }, "HDL.linting.verilator.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add Verilator arguments here (like macros). They will be added to Verilator while linting." }, "HDL.linting.vsg.arguments": { "scope": "window", "type": "string", "default": "", "description": "Add vsg arguments here (like macros). They will be added to vsg while linting." }, "HDL.formatter.vlog.default.style": { "scope": "window", "type": "string", "enum": [ "kr", "ansi", "gnu" ], "default": "kr", "description": "Select the verilog and systemverilog formatter style." }, "HDL.formatter.vlog.default.args": { "scope": "window", "type": "string", "default": "", "description": "Add verilog formatter arguments here (like istyle)." }, "HDL.formatter.vhdl.default.keyword-case": { "description": "Keyword case", "type": "string", "default": "LowerCase", "enum": [ "LowerCase", "UpperCase" ] }, "HDL.formatter.vhdl.default.align-comments": { "description": "Align comments", "type": "boolean", "default": false }, "HDL.formatter.vhdl.default.type-name-case": { "description": "Type name case", "type": "string", "default": "LowerCase", "enum": [ "LowerCase", "UpperCase" ] }, "HDL.formatter.vhdl.default.indentation": { "description": "Indentation", "type": "number", "default": 4 }, "PRJ.file.limit.number": { "scope": "window", "type": "number", "default": 600, "description": "PRJ file limit number" }, "PRJ.file.structure.notice": { "scope": "window", "type": "boolean", "default": true, "description": "notice when change file structure" }, "PRJ.customer.Lib.repo.path": { "scope": "window", "type": "string", "default": "", "description": "set the customer lib_repo_path" }, "PRJ.xilinx.BD.repo.path": { "scope": "window", "type": "string", "default": "", "description": "set the xilinx bd_repo_path" }, "PRJ.xilinx.IP.repo.path": { "scope": "window", "type": "string", "default": "", "description": "set the xilinx ip_repo_path \n e.g. : D:/project/FPGA/.Lib/xIP" }, "SIM.Xilinx.LIB.path": { "scope": "window", "type": "string", "default": "", "description": "set the Xilinx SIM LIB path. \n e.g. : D:/APP/vivado_18_3/Vivado/2018.3/data/verilog/src" }, "TOOL.vivado.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the xilinx install path. \n e.g. : D:/APP/vivado_18_3/Vivado/2018.3/bin/ \n This applies only to WIN For other systems, add it to environment variables" }, "TOOL.modelsim.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the modelsim install path. \n e.g. : D:/APP/modelsim/bin/" }, "TOOL.verilator.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the verilator install path. \n e.g. : D:/APP/verilator/bin/" }, "TOOL.verible.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the verible install path. \n e.g. : D:/APP/verible/bin/" }, "TOOL.ghdl.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the verible install path. \n e.g. : D:/APP/ghdl/bin/" }, "TOOL.vsg.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the vsg install path. \n e.g. : D:/APP/vsg/bin/" }, "TOOL.iverilog.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the iVerilog install path. \n e.g. : D:/APP/iverilog/bin/" }, "TOOL.gtkwave.install.path": { "scope": "window", "type": "string", "default": "", "description": "set the gtkwave install path. \n e.g. : D:/APP/iverilog/gtkwave/bin/" } } }, "viewsContainers": { "activitybar": [ { "id": "TOOL", "title": "DIDE Tool", "icon": "images/svg/DIDE.svg" } ] }, "views": { "TOOL": [ { "id": "TOOL.file_tree", "name": "File" }, { "id": "TOOL.Tool_tree", "name": "Tool" }, { "id": "TOOL.hard_tree", "name": "FPGA Options" }, { "id": "TOOL.soft_tree", "name": "SOFT Options" } ] }, "languages": [ { "id": "tcl", "aliases": [ "TCL", "Xilinx Constraints File", "Synopsis Constraints File" ], "extensions": [ ".tcl", ".sdc", ".xdc", ".fdc" ], "configuration": "./config/tcl.configuration.json" }, { "id": "bd", "extensions": [ ".bd" ] }, { "id": "vhdl", "aliases": [ "VHDL", "vhdl" ], "extensions": [ ".vhd", ".vhdl", ".vho", ".vht" ], "configuration": "./config/vhdl.configuration.json" }, { "id": "verilog", "aliases": [ "Verilog", "verilog" ], "extensions": [ ".v", ".V", ".vh", ".vl" ], "configuration": "./config/vlog.configuration.json" }, { "id": "systemverilog", "aliases": [ "System Verilog", "systemverilog" ], "extensions": [ ".sv", ".SV" ], "configuration": "./config/svlog.configuration.json" }, { "id": "arm", "aliases": [ "ARM", "arm" ], "extensions": [ ".s", ".S", ".asm", ".sx" ], "configuration": "./config/arm.configuration.json" }, { "id": "linkerscript", "aliases": [ "LinkerScript", "linkerscript" ], "extensions": [ ".ld", ".dld" ], "configuration": "./config/link.configuration.json" } ], "jsonValidation": [ { "fileMatch": "property.json", "url": "./property-schema.json" } ], "grammars": [ { "language": "linkerscript", "scopeName": "source.ld", "path": "./syntaxes/link.json" }, { "language": "arm", "scopeName": "source.arm", "path": "./syntaxes/arm.json" }, { "language": "tcl", "scopeName": "source.tcl", "path": "./syntaxes/tcl.json" }, { "language": "vhdl", "scopeName": "source.vhdl", "path": "./syntaxes/vhdl.json" }, { "language": "verilog", "scopeName": "source.verilog", "path": "./syntaxes/vlog.json" }, { "language": "systemverilog", "scopeName": "source.systemverilog", "path": "./syntaxes/svlog.json" } ], "snippets": [ { "language": "tcl", "path": "snippets/tcl.json" }, { "language": "vhdl", "path": "snippets/vhdl.json" }, { "language": "verilog", "path": "snippets/svlog.json" }, { "language": "systemverilog", "path": "snippets/svlog.json" } ], "commands": [ { "command": "FILE.refresh", "title": "Refresh this File List", "icon": "$(refresh)", "category": "FILE" }, { "command": "FILE.expand", "title": "Refresh this File List", "icon": "$(expand-all)", "category": "FILE" }, { "command": "FILE.collapse", "title": "Refresh this File List", "icon": "$(collapse-all)", "category": "FILE" }, { "command": "FILE.openFile", "title": "Open this File", "category": "FILE" }, { "command": "TOOL.Lint", "title": "syntax check", "category": "TOOL" }, { "command": "TOOL.Launch", "title": "launch extension", "category": "TOOL" }, { "command": "TOOL.Gen_Property", "title": "generate property file", "category": "TOOL" }, { "command": "TOOL.Overwrite_InitProperty", "title": "Overwrite the InitPropertyParam", "category": "TOOL" }, { "command": "TOOL.BOOT", "title": "BOOT", "category": "TOOL" }, { "command": "TOOL.Clean", "title": "Clean", "category": "TOOL" }, { "command": "TOOL.SerialPort", "title": "Serial monitor", "category": "TOOL" }, { "command": "TOOL.simulate", "title": "Simulate", "icon": { "light": "images/svg/light/debug.svg", "dark": "images/svg/dark/debug.svg" }, "category": "TOOL" }, { "command": "TOOL.libPick", "title": "import library", "icon": { "light": "images/svg/light/library.svg", "dark": "images/svg/dark/library.svg" }, "category": "TOOL" }, { "command": "TOOL.netlist", "title": "show netlist", "icon": { "light": "images/svg/light/list-tree.svg", "dark": "images/svg/dark/list-tree.svg" }, "category": "TOOL" }, { "command": "TOOL.FSMGraph", "title": "show FSMGraph", "icon": { "light": "images/svg/light/fsm.svg", "dark": "images/svg/dark/fsm.svg" }, "category": "TOOL" }, { "command": "TOOL.vhdl2vlog", "title": "translate vhdl to vlog", "icon": { "light": "images/svg/light/translate.svg", "dark": "images/svg/dark/translate.svg" }, "category": "TOOL" }, { "command": "TOOL.instance", "title": "Instance", "category": "TOOL" }, { "command": "TOOL.testbench", "title": "Testbench", "category": "TOOL" }, { "command": "TOOL.Overwrite_tb", "title": "Overwrite the template of testbench", "category": "TOOL" }, { "command": "TOOL.Generate_template", "title": "generate template file", "category": "TOOL" }, { "command": "TOOL.state_machine.designer", "title": "State machine designer", "category": "TOOL" }, { "command": "TOOL.state_machine.viewer", "title": "State machine viewer", "category": "TOOL" }, { "command": "HARD.Launch", "title": "Launch", "category": "FPGA" }, { "command": "HARD.srcTop", "title": "Set as TOP", "category": "FPGA" }, { "command": "HARD.simTop", "title": "Set as Testbench TOP", "category": "FPGA" }, { "command": "HARD.Refresh", "title": "refresh designed file", "category": "FPGA" }, { "command": "HARD.Simulate", "title": "Run the Simulation", "category": "FPGA" }, { "command": "HARD.Build", "title": "Build the current fpga project", "category": "FPGA" }, { "command": "HARD.Synth", "title": "Synth the current fpga project", "category": "FPGA" }, { "command": "HARD.Impl", "title": "Impl the current fpga project", "category": "FPGA" }, { "command": "HARD.Bit", "title": "Generate the bit file", "category": "FPGA" }, { "command": "HARD.Program", "title": "Download the bit file into the device", "category": "FPGA" }, { "command": "HARD.GUI", "title": "Open the GUI", "category": "FPGA" }, { "command": "HARD.Exit", "title": "Exit the current project", "category": "FPGA" }, { "command": "HARD.Add_dev", "title": "Add devices to the database", "category": "FPGA" }, { "command": "HARD.Delete_dev", "title": "Remove the device from the database", "category": "FPGA" }, { "command": "SOFT.Launch", "title": "Launch", "category": "SOFT" }, { "command": "SOFT.Build", "title": "Build", "category": "SOFT" }, { "command": "SOFT.Download", "title": "Download", "category": "SOFT" }, { "command": "xilinx.Overwrite_bd", "title": "Overwrite the bd_file", "category": "FPGA" }, { "command": "xilinx.Add_bd", "title": "Add a bd_file", "category": "FPGA" }, { "command": "xilinx.Delete_bd", "title": "Delete the bd_file", "category": "FPGA" } ], "keybindings": [ { "command": "HARD.Launch", "key": "Alt+z", "mac": "Alt+z", "when": "editorTextFocus" }, { "command": "TOOL.instance", "key": "Alt+i", "mac": "Alt+i", "when": "editorTextFocus" } ], "menus": { "view/title": [ { "command": "TOOL.libPick", "group": "navigation", "when": "view == TOOL.file_tree" }, { "command": "FILE.refresh", "group": "navigation", "when": "view == TOOL.file_tree" } ], "view/item/context": [ { "command": "TOOL.simulate", "group": "inline", "when": "view == TOOL.file_tree && viewItem == file" }, { "command": "TOOL.netlist", "group": "inline", "when": "view == TOOL.file_tree && viewItem == file" }, { "command": "HARD.srcTop", "group": "navigation@1", "when": "view == TOOL.file_tree && viewItem == file" }, { "command": "HARD.simTop", "group": "navigation@2", "when": "view == TOOL.file_tree && viewItem == file" }, { "command": "TOOL.simulate", "group": "navigation@3", "when": "view == TOOL.file_tree && viewItem == file" } ], "editor/title": [ { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "TOOL.netlist", "group": "navigation" }, { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "TOOL.FSMGraph", "group": "navigation" }, { "when": "resourceLangId == vhdl", "command": "TOOL.vhdl2vlog", "group": "navigation" } ], "editor/context": [ { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "HARD.srcTop", "group": "navigation@1" }, { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "HARD.simTop", "group": "navigation@2" }, { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "TOOL.instance", "group": "navigation@3" }, { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "TOOL.testbench", "group": "navigation@4" }, { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "TOOL.simulate", "group": "navigation@5" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "TOOL.netlist", "group": "navigation@6" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "TOOL.FSMGraph", "group": "navigation@7" }, { "when": "resourceLangId == vhdl", "command": "TOOL.vhdl2vlog", "group": "navigation@8" }, { "when": "editorLangId == bd", "command": "xilinx.Overwrite_bd", "group": "navigation@9" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "TOOL.Lint", "group": "navigation@10" } ], "explorer/context": [ { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "HARD.srcTop", "group": "navigation@5" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "HARD.simTop", "group": "navigation@6" }, { "when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl", "command": "TOOL.testbench", "group": "navigation@7" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "TOOL.simulate", "group": "navigation@8" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "TOOL.netlist", "group": "navigation@9" }, { "when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl", "command": "TOOL.FSMGraph", "group": "navigation@10" }, { "when": "resourceLangId == vhdl", "command": "TOOL.vhdl2vlog", "group": "navigation@11" }, { "when": "editorLangId == bd", "command": "xilinx.Overwrite_bd", "group": "navigation@12" } ] } }, "scripts": { "vscode:prepublish": "webpack --mode production" }, "devDependencies": {}, "dependencies": {} }