xilinx.com user NV_nvdla_wrapper 1.0 m_axi AWID nvdla_core2dbb_aw_awid AWADDR nvdla_core2dbb_aw_awaddr AWLEN nvdla_core2dbb_aw_awlen AWSIZE nvdla_core2dbb_aw_awsize AWBURST m_axi_awburst AWLOCK m_axi_awlock AWCACHE m_axi_awcache AWPROT m_axi_awprot AWQOS m_axi_awqos AWUSER m_axi_awuser AWVALID nvdla_core2dbb_aw_awvalid AWREADY nvdla_core2dbb_aw_awready WDATA nvdla_core2dbb_w_wdata WSTRB nvdla_core2dbb_w_wstrb WLAST nvdla_core2dbb_w_wlast WUSER m_axi_wuser WVALID nvdla_core2dbb_w_wvalid WREADY nvdla_core2dbb_w_wready BID nvdla_core2dbb_b_bid BRESP m_axi_bresp BUSER m_axi_buser BVALID nvdla_core2dbb_b_bvalid BREADY nvdla_core2dbb_b_bready ARID nvdla_core2dbb_ar_arid ARADDR nvdla_core2dbb_ar_araddr ARLEN nvdla_core2dbb_ar_arlen ARSIZE nvdla_core2dbb_ar_arsize ARBURST m_axi_arburst ARLOCK m_axi_arlock ARCACHE m_axi_arcache ARPROT m_axi_arprot ARQOS m_axi_arqos ARUSER m_axi_aruser ARVALID nvdla_core2dbb_ar_arvalid ARREADY nvdla_core2dbb_ar_arready RID nvdla_core2dbb_r_rid RDATA nvdla_core2dbb_r_rdata RRESP m_axi_rresp RLAST nvdla_core2dbb_r_rlast RUSER m_axi_ruser RVALID nvdla_core2dbb_r_rvalid RREADY nvdla_core2dbb_r_rready s_apb PADDR paddr PSEL psel PENABLE penable PWRITE pwrite PWDATA pwdata PREADY pready PRDATA prdata PSLVERR pslverr csb_rstn RST csb_rstn POLARITY ACTIVE_LOW rstn RST rstn POLARITY ACTIVE_LOW core_clk CLK core_clk ASSOCIATED_RESET rstn csb_clk CLK csb_clk ASSOCIATED_RESET csb_rstn dla_intr INTERRUPT dla_intr SENSITIVITY LEVEL_HIGH m_axi 16777216T 64 s_apb reg 0 4096 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog NV_nvdla_wrapper xilinx_anylanguagesynthesis_view_fileset viewChecksum b4683d40 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog NV_nvdla_wrapper xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum b4683d40 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f64a5dae core_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation csb_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation csb_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dla_intr out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_aw_awvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_aw_awready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_aw_awid out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_aw_awlen out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_aw_awsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_aw_awaddr out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_w_wvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_w_wready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_w_wdata out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_w_wstrb out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_w_wlast out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_ar_arvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_ar_arready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_ar_arid out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_ar_arlen out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_ar_arsize out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_ar_araddr out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_b_bvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_b_bready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_b_bid in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_r_rvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_r_rready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation nvdla_core2dbb_r_rid in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_r_rlast in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 nvdla_core2dbb_r_rdata in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_awburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awlock out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awqos out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_awuser out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_wuser out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_bresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_buser in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_arburst out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arlock out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arcache out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arprot out 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_arqos out 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_aruser out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axi_rresp in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 m_axi_ruser in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 psel in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation penable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwrite in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation paddr in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pwdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation prdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation pslverr out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation choice_list_99a1d2b9 LEVEL_HIGH LEVEL_LOW EDGE_RISING EDGE_FALLING choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset src/HLS_cdp_icvt.v verilogSource IMPORTED_FILE src/HLS_cdp_ocvt.v verilogSource IMPORTED_FILE src/MUX2D4.v verilogSource IMPORTED_FILE src/MUX2HDD2.v verilogSource IMPORTED_FILE src/NV_BLKBOX_SINK.v verilogSource IMPORTED_FILE src/NV_BLKBOX_SRC0.v verilogSource IMPORTED_FILE src/NV_CLK_gate_power.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_CALC_int8.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_assembly_buffer.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_assembly_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_calculator.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_delivery_buffer.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_delivery_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_dual_reg.v verilogSource IMPORTED_FILE src/simulate_x_tick.vh verilogSource IMPORTED_FILE true src/NV_NVDLA_CACC_regfile.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_single_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_CVT_cell.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_DC_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_pack.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_sg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_WT_8ATMM_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_WT_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_cvt.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_dc.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_dma_mux.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_dual_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_img.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_regfile.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_shared_buffer.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_single_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_status.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_wt.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_INTP_unit.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_LUT_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_MUL_unit.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_bufferin_tp1.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_cvtin.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_cvtout.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_data_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_intp.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_intpinfo_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_lut.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_mul.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_nan.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_sum.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_sumpd_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_syncfifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_cq.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_lat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_ro_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_WDMA_dat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_dp.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_rdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_wdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_CFGROM_rom.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_active.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_cfg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_mac.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_rt_in.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_rt_out.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_core.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_SG_dat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_SG_wt_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_WL_dec.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_dl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_dual_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_regfile.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_sg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_single_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_wl.v verilogSource IMPORTED_FILE src/NV_NVDLA_DMAIF_rdreq.v verilogSource IMPORTED_FILE src/NV_NVDLA_DMAIF_rdrsp.v verilogSource IMPORTED_FILE src/NV_NVDLA_DMAIF_wr.v verilogSource IMPORTED_FILE src/NV_NVDLA_GLB_CSB_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_GLB_csb.v verilogSource IMPORTED_FILE src/NV_NVDLA_GLB_ic.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_saturate.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_shiftleftsu.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_shiftrightsatsu.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_shiftrightsu.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_CSB_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_IG_arb.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_IG_bpt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_IG_cvt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_define.vh verilogSource IMPORTED_FILE true src/NV_NVDLA_MCIF_READ_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_IG_arb.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_IG_bpt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_IG_cvt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_cq.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_csb.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_read.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_write.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_cal1d.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_cal2d.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_preproc.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_unit1d.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_cq.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_lat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_ro_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_WDMA_DAT_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_WDMA_cmd.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_WDMA_dat.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_core.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_nan.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_rdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_wdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_BRDMA_cq_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_BRDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_CORE_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_CORE_pack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_CORE_unpack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_C_int.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_alu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_mul.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_relu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_trt.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_c.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_prelu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_relu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_sync2data.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_x1_int.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_x2_int.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_cmd.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_din.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_dout.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_cq_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_NRDMA_cq_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_NRDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_EG_ro.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_dmaif.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_pack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_unpack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_DAT_in.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_DAT_out.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_cmd.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_dat.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_intr.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_brdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_cmux.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_core.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_mrdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_nrdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_rdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_wdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_XXIF_libs.v verilogSource IMPORTED_FILE src/NV_NVDLA_apb2csb.v verilogSource IMPORTED_FILE src/NV_NVDLA_cacc.v verilogSource IMPORTED_FILE src/NV_NVDLA_cbuf.v verilogSource IMPORTED_FILE src/NV_NVDLA_cdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_cdp.v verilogSource IMPORTED_FILE src/NV_NVDLA_cfgrom.v verilogSource IMPORTED_FILE src/NV_NVDLA_cmac.v verilogSource IMPORTED_FILE src/NV_NVDLA_core_reset.v verilogSource IMPORTED_FILE src/NV_NVDLA_csb_master.v verilogSource IMPORTED_FILE src/NV_NVDLA_csc.v verilogSource IMPORTED_FILE src/NV_NVDLA_glb.v verilogSource IMPORTED_FILE src/NV_NVDLA_mcif.v verilogSource IMPORTED_FILE src/NV_HWACC_NVDLA_tick_defines.vh verilogSource IMPORTED_FILE true src/NV_NVDLA_partition_a.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_c.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_m.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_o.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_p.v verilogSource IMPORTED_FILE src/NV_NVDLA_pdp.v verilogSource IMPORTED_FILE src/NV_NVDLA_reset.v verilogSource IMPORTED_FILE src/NV_NVDLA_sdp.v verilogSource IMPORTED_FILE src/NV_NVDLA_sync3d.v verilogSource IMPORTED_FILE src/NV_NVDLA_sync3d_c.v verilogSource IMPORTED_FILE src/NV_NVDLA_sync3d_s.v verilogSource IMPORTED_FILE src/NV_nvdla.v verilogSource IMPORTED_FILE src/OR2D1.v verilogSource IMPORTED_FILE src/int_sum_block_tp1.v verilogSource IMPORTED_FILE src/nv_ram_rws_128x18.v verilogSource IMPORTED_FILE src/nv_ram_rws_16x256.v verilogSource IMPORTED_FILE src/nv_ram_rws_16x272.v verilogSource IMPORTED_FILE src/nv_ram_rws_16x64.v verilogSource IMPORTED_FILE src/nv_ram_rws_256x3.v verilogSource IMPORTED_FILE src/nv_ram_rws_256x64.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_128x11.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_128x6.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_16x14.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_16x16.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_16x65.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_8x65.v verilogSource IMPORTED_FILE src/nv_ram_rwst_256x8.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_20x4.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_60x21.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_80x17.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_80x9.v verilogSource IMPORTED_FILE src/oneHotClk_async_read_clock.v verilogSource IMPORTED_FILE src/oneHotClk_async_write_clock.v verilogSource IMPORTED_FILE src/p_SSYNC2DO_C_PP.v verilogSource IMPORTED_FILE src/p_SSYNC3DO.v verilogSource IMPORTED_FILE src/p_SSYNC3DO_C_PPP.v verilogSource IMPORTED_FILE src/p_SSYNC3DO_S_PPP.v verilogSource IMPORTED_FILE src/p_STRICTSYNC3DOTM_C_PPP.v verilogSource IMPORTED_FILE src/sync3d.v verilogSource IMPORTED_FILE src/sync3d_c_ppp.v verilogSource IMPORTED_FILE src/sync3d_s_ppp.v verilogSource IMPORTED_FILE src/sync_reset.v verilogSource IMPORTED_FILE src/NV_nvdla_wrapper.v verilogSource CHECKSUM_a644eadc IMPORTED_FILE xilinx_anylanguagebehavioralsimulation_view_fileset src/HLS_cdp_icvt.v verilogSource IMPORTED_FILE src/HLS_cdp_ocvt.v verilogSource IMPORTED_FILE src/MUX2D4.v verilogSource IMPORTED_FILE src/MUX2HDD2.v verilogSource IMPORTED_FILE src/NV_BLKBOX_SINK.v verilogSource IMPORTED_FILE src/NV_BLKBOX_SRC0.v verilogSource IMPORTED_FILE src/NV_CLK_gate_power.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_CALC_int8.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_assembly_buffer.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_assembly_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_calculator.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_delivery_buffer.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_delivery_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_dual_reg.v verilogSource IMPORTED_FILE src/simulate_x_tick.vh verilogSource IMPORTED_FILE true src/NV_NVDLA_CACC_regfile.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_single_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CACC_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_CVT_cell.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_DC_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_pack.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_sg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_WT_8ATMM_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_WT_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_cvt.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_dc.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_dma_mux.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_dual_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_img.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_regfile.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_shared_buffer.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_single_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_status.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDMA_wt.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_INTP_unit.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_LUT_ctrl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_MUL_unit.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_bufferin_tp1.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_cvtin.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_cvtout.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_data_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_intp.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_intpinfo_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_lut.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_mul.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_nan.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_sum.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_sumpd_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_DP_syncfifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_cq.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_lat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_RDMA_ro_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_WDMA_dat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_dp.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_rdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CDP_wdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_CFGROM_rom.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_active.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_cfg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_mac.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_rt_in.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_rt_out.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_CORE_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_core.v verilogSource IMPORTED_FILE src/NV_NVDLA_CMAC_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_SG_dat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_SG_wt_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_WL_dec.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_dl.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_dual_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_regfile.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_sg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_single_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_CSC_wl.v verilogSource IMPORTED_FILE src/NV_NVDLA_DMAIF_rdreq.v verilogSource IMPORTED_FILE src/NV_NVDLA_DMAIF_rdrsp.v verilogSource IMPORTED_FILE src/NV_NVDLA_DMAIF_wr.v verilogSource IMPORTED_FILE src/NV_NVDLA_GLB_CSB_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_GLB_csb.v verilogSource IMPORTED_FILE src/NV_NVDLA_GLB_ic.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_saturate.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_shiftleftsu.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_shiftrightsatsu.v verilogSource IMPORTED_FILE src/NV_NVDLA_HLS_shiftrightsu.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_CSB_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_IG_arb.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_IG_bpt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_IG_cvt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_define.vh verilogSource IMPORTED_FILE true src/NV_NVDLA_MCIF_READ_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_READ_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_IG_arb.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_IG_bpt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_IG_cvt.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_cq.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_WRITE_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_csb.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_read.v verilogSource IMPORTED_FILE src/NV_NVDLA_MCIF_write.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_cal1d.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_cal2d.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_preproc.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_CORE_unit1d.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_cq.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_lat_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_RDMA_ro_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_WDMA_DAT_fifo.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_WDMA_cmd.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_WDMA_dat.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_core.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_nan.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_rdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_slcg.v verilogSource IMPORTED_FILE src/NV_NVDLA_PDP_wdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_BRDMA_cq_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_BRDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_CORE_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_CORE_pack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_CORE_unpack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_C_int.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_alu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_mul.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_relu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_X_int_trt.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_c.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_prelu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_relu.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_sync2data.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_x1_int.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_HLS_x2_int.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_cmd.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_din.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_dout.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_cq_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_MRDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_NRDMA_cq_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_NRDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_EG_ro.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_dmaif.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_eg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_ig.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_pack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_RDMA_unpack.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_REG_dual.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_REG_single.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_DAT_in.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_DAT_out.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_cmd.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_dat.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_gate.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_WDMA_intr.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_brdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_cmux.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_core.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_mrdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_nrdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_rdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_reg.v verilogSource IMPORTED_FILE src/NV_NVDLA_SDP_wdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_XXIF_libs.v verilogSource IMPORTED_FILE src/NV_NVDLA_apb2csb.v verilogSource IMPORTED_FILE src/NV_NVDLA_cacc.v verilogSource IMPORTED_FILE src/NV_NVDLA_cbuf.v verilogSource IMPORTED_FILE src/NV_NVDLA_cdma.v verilogSource IMPORTED_FILE src/NV_NVDLA_cdp.v verilogSource IMPORTED_FILE src/NV_NVDLA_cfgrom.v verilogSource IMPORTED_FILE src/NV_NVDLA_cmac.v verilogSource IMPORTED_FILE src/NV_NVDLA_core_reset.v verilogSource IMPORTED_FILE src/NV_NVDLA_csb_master.v verilogSource IMPORTED_FILE src/NV_NVDLA_csc.v verilogSource IMPORTED_FILE src/NV_NVDLA_glb.v verilogSource IMPORTED_FILE src/NV_NVDLA_mcif.v verilogSource IMPORTED_FILE src/NV_HWACC_NVDLA_tick_defines.vh verilogSource IMPORTED_FILE true src/NV_NVDLA_partition_a.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_c.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_m.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_o.v verilogSource IMPORTED_FILE src/NV_NVDLA_partition_p.v verilogSource IMPORTED_FILE src/NV_NVDLA_pdp.v verilogSource IMPORTED_FILE src/NV_NVDLA_reset.v verilogSource IMPORTED_FILE src/NV_NVDLA_sdp.v verilogSource IMPORTED_FILE src/NV_NVDLA_sync3d.v verilogSource IMPORTED_FILE src/NV_NVDLA_sync3d_c.v verilogSource IMPORTED_FILE src/NV_NVDLA_sync3d_s.v verilogSource IMPORTED_FILE src/NV_nvdla.v verilogSource IMPORTED_FILE src/OR2D1.v verilogSource IMPORTED_FILE src/int_sum_block_tp1.v verilogSource IMPORTED_FILE src/nv_ram_rws_128x18.v verilogSource IMPORTED_FILE src/nv_ram_rws_16x256.v verilogSource IMPORTED_FILE src/nv_ram_rws_16x272.v verilogSource IMPORTED_FILE src/nv_ram_rws_16x64.v verilogSource IMPORTED_FILE src/nv_ram_rws_256x3.v verilogSource IMPORTED_FILE src/nv_ram_rws_256x64.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_128x11.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_128x6.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_16x14.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_16x16.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_16x65.v verilogSource IMPORTED_FILE src/nv_ram_rwsp_8x65.v verilogSource IMPORTED_FILE src/nv_ram_rwst_256x8.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_20x4.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_60x21.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_80x17.v verilogSource IMPORTED_FILE src/nv_ram_rwsthp_80x9.v verilogSource IMPORTED_FILE src/oneHotClk_async_read_clock.v verilogSource IMPORTED_FILE src/oneHotClk_async_write_clock.v verilogSource IMPORTED_FILE src/p_SSYNC2DO_C_PP.v verilogSource IMPORTED_FILE src/p_SSYNC3DO.v verilogSource IMPORTED_FILE src/p_SSYNC3DO_C_PPP.v verilogSource IMPORTED_FILE src/p_SSYNC3DO_S_PPP.v verilogSource IMPORTED_FILE src/p_STRICTSYNC3DOTM_C_PPP.v verilogSource IMPORTED_FILE src/sync3d.v verilogSource IMPORTED_FILE src/sync3d_c_ppp.v verilogSource IMPORTED_FILE src/sync3d_s_ppp.v verilogSource IMPORTED_FILE src/sync_reset.v verilogSource IMPORTED_FILE src/NV_nvdla_wrapper.v verilogSource IMPORTED_FILE xilinx_xpgui_view_fileset xgui/NV_nvdla_wrapper_v1_0.tcl tclSource CHECKSUM_f64a5dae XGUI_VERSION_2 NV_nvdla_wrapper_v1_0 Component_Name NV_nvdla_wrapper_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM kintexuplus kintexu /UserIP NV_nvdla_wrapper_v1_0 package_project 2 2021-07-23T10:43:29Z c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP c:/Users/tjwan/Desktop/ZYNQ-NVDLA/IP 2019.1