ALL_ULTIMATE_LOGIC := \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/io_bus_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/io_bus_splitter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/io_bus_bridge2.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/io_bus_arbiter_pri.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/io_dummy.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/mem_bus_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/mem_bus_arbiter_pri.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/mem_bus_arbiter_pri_32.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/mem_to_mem32.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/dma_bus_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/dma_bus_arbiter_pri.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/slot_bus_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/io_to_dma_bridge.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/slot_to_io_bridge.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/busses/vhdl_source/endianness_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/sync_fifo/vhdl_source/sync_fifo.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/srl_fifo/vhdl_source/srl_fifo-xilinx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/stack/vhdl_source/distributed_stack.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/pulse_stretch/vhdl_source/pulse_stretch.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/oc_pusher/vhdl_source/oc_pusher.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/synchroniser/vhdl_source/synchroniser.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/synchroniser/vhdl_source/synchronizer_gzw.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/synchroniser/vhdl_source/level_synchronizer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/synchroniser/vhdl_source/pulse_synchronizer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/async_fifo/vhdl_source/gray_code_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/async_fifo/vhdl_source/async_fifo_ft.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/spram.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram_io.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/spram.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/pseudo_dpram_8x32.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/pseudo_dpram_8x32-xilinx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/pseudo_dpram_8x16.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/pseudo_dpram_8x16-xilinx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram_8x16.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram_8x16-xilinx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram_8x32.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram_8x32-xilinx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/video/vhdl_source/char_generator_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/video/vhdl_source/char_generator_rom_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/video/vhdl_source/char_generator_rom.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/video/vhdl_source/char_generator_regs.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/video/vhdl_source/char_generator_slave.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/video/vhdl_source/char_generator_peripheral.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/clock/vhdl_source/real_time_clock.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/clock/vhdl_source/fractional_div.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/nano_cpu/vhdl_source/nano_cpu_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/nano_cpu/vhdl_source/nano_alu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/nano_cpu/vhdl_source/nano_cpu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/nano_cpu/vhdl_source/nano.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/free_queue/vhdl_source/block_bus_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/ip/free_queue/vhdl_source/free_queue.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/acia/vhdl_source/acia6551_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/acia/vhdl_source/acia6551.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/audio_select/vhdl_source/audio_select.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/tx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/rx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/tx_dma.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/rx_dma.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/uart_dma.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/slip_encoder.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/slip_decoder.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/uart_lite/vhdl_source/uart_peripheral_io.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sigma_delta_dac/vhdl_source/sigma_delta_dac.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sigma_delta_dac/vhdl_source/noise_generator.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sigma_delta_dac/vhdl_source/high_pass.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sigma_delta_dac/vhdl_source/my_math_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/spi/vhdl_source/spi.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/spi/vhdl_source/spi_peripheral_io.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v5.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/spike_filter/vhdl_source/spike_filter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/rmii/vhdl_source/rmii_transceiver.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/rmii/vhdl_source/crc32.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/rmii/vhdl_source/eth_filter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/rmii/vhdl_source/eth_transmit.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/rmii/vhdl_source/packet_generator.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/rmii/vhdl_source/ethernet_interface.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_debug.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/data_crc.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/timer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/host_sequencer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/nano_minimal_io.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/token_crc.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/token_crc_19.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/token_crc_check.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/ulpi_bus.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/ulpi_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/ulpi_rx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/ulpi_tx.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_cmd_nano.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_cmd_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_host_nano.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_host_interface.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/bridge_to_mem_ctrl.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/mem_addr_counter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/mem_remain_counter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_memory_ctrl.vhd \ vhdl,work,$(ULTIMATE_FPGA)/altera/align_read_to_bram.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/usb2/vhdl_source/usb_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/itu/vhdl_source/itu_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/itu/vhdl_source/itu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/icap/vhdl_source/icap_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/icap/vhdl_source/icap-spartan.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/iec_interface/vhdl_source/iec_processor.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/iec_interface/vhdl_source/iec_processor_io.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/c2n_playback/vhdl_source/c2n_playback_io.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/c2n_playback/vhdl_source/tape_speed_control.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/c2n_record/vhdl_source/c2n_record.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/command_interface/vhdl_source/command_if_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/command_interface/vhdl_source/command_protocol.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/command_interface/vhdl_source/command_interface.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/copper/vhdl_source/copper_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/copper/vhdl_source/copper_regs.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/copper/vhdl_source/copper_engine.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/copper/vhdl_source/copper.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sampler/vhdl_source/sampler_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sampler/vhdl_source/sampler_accu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sampler/vhdl_source/sampler_regs.vhd \ vhdl,work,$(ULTIMATE_FPGA)/io/sampler/vhdl_source/sampler.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_debug_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_trace.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/Q_table.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/adsr_multi.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/mult_acc.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/oscillator.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_ctrl.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_filter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_mixer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_regs.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/wave_map.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_top.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_io_regs_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_io_regs.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_mapper.vhd \ vhdl,work,$(ULTIMATE_FPGA)/sid6581/vhdl_source/sid_peripheral.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/pkg_6502_defs.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/pkg_6502_decode.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/shifter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/implied.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/bit_cpx_cpy.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/alu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/proc_registers.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/proc_interrupt.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/proc_control.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/data_oper.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/proc_core.vhd \ vhdl,work,$(ULTIMATE_FPGA)/6502n/vhdl_source/cpu6502.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/cia_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/cia_registers.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/cia_timer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/floppy_stream.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/floppy_mem.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/floppy_param_mem.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/floppy.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/floppy_sound.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/via6522.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/cpu_part_1541.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/drive_registers.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/c1541_drive.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/c1541_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/c1541_timing.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/mm_drive.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/mm_drive_cpu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/wd177x.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/stepper.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/gcr2bin.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/bin2gcr.vhd \ vhdl,work,$(ULTIMATE_FPGA)/1541/vhdl_source/gcr_codec.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/mblite_wrapper.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/mem32k.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/mem16k.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/mem4k.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/config_pkg.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/std/std_Pkg.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/std/dsram.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/std/sram.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/std/sram_4en.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/core_Pkg.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/decode.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/execute.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/fetch.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/gprf.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/mem.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/core.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/core_address_decoder.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/core_wb_adapter.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/mblite/hw/core/core_wb.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/ip/memory/vhdl_source/dpram_sc.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/dm_simple.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/dm_with_invalidate.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/dmem_arbiter.vhd \ vhdl,mblite,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/cached_mblite.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cpu_unit/vhdl_source/dmem_splitter.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/cart_slot_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/cart_slot_registers.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/slot_timing.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/slot_slave.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/slot_trace.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/slot_master_v4.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/slot_server_v4.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/freezer.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/all_carts_v5.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/reu_pkg.vhd \ vhdl,work,$(ULTIMATE_FPGA)/cart_slot/vhdl_source/reu.vhd \ vhdl,work,$(ULTIMATE_FPGA)/devices/vhdl_source/microwire_eeprom.vhd \ vhdl,work,$(ULTIMATE_FPGA)/fpga_top/ultimate_fpga/vhdl_source/s3e_clockgen.vhd \ vhdl,work,$(ULTIMATE_FPGA)/fpga_top/ultimate_fpga/vhdl_source/s3a_clockgen.vhd \ vhdl,work,$(ULTIMATE_FPGA)/fpga_top/ultimate_fpga/vhdl_source/ultimate_logic_32.vhd \