Add batch 2 (openasic-org_xkISP, JOKOSAHS_DMA-Pcileech, lawrie_fpga_pio, nukeykt_Nuked-MD-FPGA, vipinkmenon_neuralNetwork)

JOKOSAHS_DMA-Pcileech/README.md

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+## **💡 Current Status**
+
+The **network card firmware** has been patched by **ACE** and is no longer functional in its original state.  
+The purpose of open-sourcing this firmware is to **accelerate learning** and provide insights into this project.  
+
+By sharing this resource, we aim to foster a deeper understanding and enable developers to explore and innovate further.  
+Remember, this is for educational and research purposes—let's build a better community together!  
+
+## **🔧 Focus Areas**
+
+Our primary focus is on **media cards**, **sound cards**, and **hard drives**.  
+Due to the nature of these devices, we have decided **not to open-source them**.  
+
+If you are interested in discussing these technologies or joining our community, feel free to connect with us on **Discord**:  
+
+
+## ⚠️ About TLP Interrupts
+
+The TLP interrupt mechanism requires proper echoing with the computer motherboard. This project was developed specifically for **ASUS motherboards**, ensuring compatibility. However, many individuals who have **stolen this project** fail to adapt the kernel interrupts for other systems. As a result, users might experience issues such as **blue screens** or other errors due to these unaddressed compatibility problems. These individuals often mislead users into switching to specific motherboards instead of resolving the underlying issues, highlighting their lack of technical expertise.
+
+While **network card firmware technology is outdated**, some developers continue to sell it at **high prices**, exploiting users who may not know better. Our decision to open-source this technology has disrupted many fraudulent developers, leading to retaliation instead of constructive improvements on their part. We believe that true developers should focus on **learning, innovating**, and solving compatibility challenges rather than deceiving customers or charging unreasonable fees.
+
+## ⚠️ Important Update on Network Card Firmware
+
+ACE has now marked all **Intel** and **Realtek** series network cards. In the future, **network card firmware** will be fully detected. Scammers who are exploiting our open-source technology will soon be exposed.
+
+### Why We Open-Sourced This Project
+The primary purpose of open-sourcing this project was to **counter the exploitation of our work**. By making the technology publicly available, we ensure that **malicious users** cannot hide behind our creations and resell them unlawfully.
+
+We will continue to monitor and update the firmware to stay ahead of these attempts.
+
+Thank you for your continued support.
+
+**Purpose of Open Source**: Following a leak by a customer, the firmware became widely distributed and resold. To address this, it has been made public. 
+
+Note that once exposed, anti-cheat systems will likely detect the firmware's space, which may limit its future usability.
+
+We are not working with any developers and any mention of us is false!
+
+## Caution Against Scammers
+
+Currently, there are many fake users cloning this open-source library and using our information to deceive others. 
+
+**Devices for Full Emulation**: Killer series network cards.
+
+**New Update**: We have modified a new IP core to support the detection of Delta games.
+
+**Want to share your insights or seek assistance?** 
+
+> ⚠️ **Note to Malicious Attackers and Troublemakers**  
+> Please refrain from joining our group. We do not welcome individuals who intend to misuse our free resources for resale purposes. Such members will be removed from the community
+
+### Open Access to Network Card DMA Firmware
+ACE has recently restricted many RTL-type devices, including network card DMA firmware. Importantly, this technology has become **publicly accessible**, allowing anyone with basic technical knowledge to quickly learn and create it. As a result, prices for these firmware solutions remain relatively affordable, generally within the **100-180 USD** range. This applies to both Killer cards and other models, so prices should not vary significantly.
+
+### Recognizing False Claims and High-Price Tactics
+Some individuals may attempt to mislead new players by claiming that open-source network card devices, often with additional modifications, are exclusive "internal" products. They may also assert that their versions are unique or private. 
+
+- **Unique Firmware:** ACE is likely to soon gather data on all such devices. Each firmware version requires unique encoding, ensuring distinct versions for each user.
+- **Open and Accessible Technology:** With the right emulation skills, anyone can achieve stability and reliability in these devices. 
+There is no "private" firmware—only **thousands of lines of code** accessible to those who seek it.
+
+
+### Scam Alert
+If you’ve paid **300 USD** for network card emulation firmware, there’s a strong chance you’ve been overcharged, as this technology is now widely accessible.
+
+**Devices for Full Emulation**: Killer series network cards.
+

JOKOSAHS_DMA-Pcileech/pcie_7x

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+

JOKOSAHS_DMA-Pcileech/src/75immt.xdc

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+set_property PACKAGE_PIN V20  [get_ports ft601_be[0]]
+set_property PACKAGE_PIN V19  [get_ports ft601_be[1]]
+set_property PACKAGE_PIN W20  [get_ports ft601_be[2]]
+set_property PACKAGE_PIN AB20 [get_ports ft601_be[3]]
+set_property PACKAGE_PIN H20  [get_ports ft601_data[0]]
+set_property PACKAGE_PIN H22  [get_ports ft601_data[1]]
+set_property PACKAGE_PIN J21  [get_ports ft601_data[2]]
+set_property PACKAGE_PIN J22  [get_ports ft601_data[3]]
+set_property PACKAGE_PIN K21  [get_ports ft601_data[4]]
+set_property PACKAGE_PIN K22  [get_ports ft601_data[5]]
+set_property PACKAGE_PIN L21  [get_ports ft601_data[6]]
+set_property PACKAGE_PIN N18  [get_ports ft601_data[7]]
+set_property PACKAGE_PIN M18  [get_ports ft601_data[8]]
+set_property PACKAGE_PIN L20  [get_ports ft601_data[9]]
+set_property PACKAGE_PIN L19  [get_ports ft601_data[10]]
+set_property PACKAGE_PIN M20  [get_ports ft601_data[11]]
+set_property PACKAGE_PIN M22  [get_ports ft601_data[12]]
+set_property PACKAGE_PIN M21  [get_ports ft601_data[13]]
+set_property PACKAGE_PIN N22  [get_ports ft601_data[14]]
+set_property PACKAGE_PIN N20  [get_ports ft601_data[15]]
+set_property PACKAGE_PIN P15  [get_ports ft601_data[16]]
+set_property PACKAGE_PIN T21  [get_ports ft601_data[17]]
+set_property PACKAGE_PIN R16  [get_ports ft601_data[18]]
+# OLD  ft601_data[19]
+set_property PACKAGE_PIN T20  [get_ports ft601_data[19]]
+
+set_property PACKAGE_PIN U17  [get_ports ft601_data[20]]
+set_property PACKAGE_PIN U20  [get_ports ft601_data[21]]
+set_property PACKAGE_PIN U21  [get_ports ft601_data[22]]
+set_property PACKAGE_PIN V22  [get_ports ft601_data[23]]
+set_property PACKAGE_PIN W22  [get_ports ft601_data[24]]
+set_property PACKAGE_PIN W21  [get_ports ft601_data[25]]
+set_property PACKAGE_PIN Y22  [get_ports ft601_data[26]]
+set_property PACKAGE_PIN Y21  [get_ports ft601_data[27]]
+set_property PACKAGE_PIN AB22 [get_ports ft601_data[28]]
+set_property PACKAGE_PIN AA21 [get_ports ft601_data[29]]
+set_property PACKAGE_PIN AB21 [get_ports ft601_data[30]]
+set_property PACKAGE_PIN AA20 [get_ports ft601_data[31]]
+set_property PACKAGE_PIN W17  [get_ports ft601_oe_n]
+set_property PACKAGE_PIN P16  [get_ports ft601_rd_n]
+set_property PACKAGE_PIN AA18 [get_ports ft601_rxf_n]
+set_property PACKAGE_PIN AB18 [get_ports ft601_siwu_n]
+set_property PACKAGE_PIN AA19 [get_ports ft601_txe_n]
+set_property PACKAGE_PIN W19  [get_ports ft601_wr_n]
+set_property PACKAGE_PIN N13  [get_ports ft601_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+
+set_property PACKAGE_PIN G21 [get_ports user_ld1_n]
+set_property PACKAGE_PIN G22 [get_ports user_ld2_n]
+set_property PACKAGE_PIN F19 [get_ports user_sw1_n]
+set_property PACKAGE_PIN F20 [get_ports user_sw2_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1_n user_ld2_n user_sw1_n user_sw2_n}]
+
+# SYSCLK
+set_property PACKAGE_PIN J19 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk]
+
+# FT601 CLK
+create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk]
+set_property PACKAGE_PIN K18 [get_ports ft601_clk]
+
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n]
+
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/txo_dout_reg[*]]
+
+set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/oe_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_false_path -from [get_pins {tickcount64_reg[*]/C}]
+set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
+
+#PCIe signals
+set_property PACKAGE_PIN A13 [get_ports pcie_present]
+set_property PACKAGE_PIN C13 [get_ports pcie_perst_n]
+set_property PACKAGE_PIN B13 [get_ports pcie_wake_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_present]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n]
+
+set_property PACKAGE_PIN C9 [get_ports {pcie_rx_n[0]}]
+set_property PACKAGE_PIN D9 [get_ports {pcie_rx_p[0]}]
+set_property PACKAGE_PIN C7 [get_ports {pcie_tx_n[0]}]
+set_property PACKAGE_PIN D7 [get_ports {pcie_tx_p[0]}]
+
+set_property PACKAGE_PIN E10 [get_ports pcie_clk_n]
+set_property PACKAGE_PIN F10 [get_ports pcie_clk_p]
+
+create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p]
+
+set_property CFGBVS Vcco [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

JOKOSAHS_DMA-Pcileech/src/pcileech_captain_75T.xdc

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+set_property PACKAGE_PIN V20  [get_ports ft601_be[0]]
+set_property PACKAGE_PIN V19  [get_ports ft601_be[1]]
+set_property PACKAGE_PIN W20  [get_ports ft601_be[2]]
+set_property PACKAGE_PIN AB20 [get_ports ft601_be[3]]
+set_property PACKAGE_PIN H20  [get_ports ft601_data[0]]
+set_property PACKAGE_PIN H22  [get_ports ft601_data[1]]
+set_property PACKAGE_PIN J21  [get_ports ft601_data[2]]
+set_property PACKAGE_PIN J22  [get_ports ft601_data[3]]
+set_property PACKAGE_PIN K21  [get_ports ft601_data[4]]
+set_property PACKAGE_PIN K22  [get_ports ft601_data[5]]
+set_property PACKAGE_PIN L21  [get_ports ft601_data[6]]
+set_property PACKAGE_PIN N18  [get_ports ft601_data[7]]
+set_property PACKAGE_PIN M18  [get_ports ft601_data[8]]
+set_property PACKAGE_PIN L20  [get_ports ft601_data[9]]
+set_property PACKAGE_PIN L19  [get_ports ft601_data[10]]
+set_property PACKAGE_PIN M20  [get_ports ft601_data[11]]
+set_property PACKAGE_PIN M22  [get_ports ft601_data[12]]
+set_property PACKAGE_PIN M21  [get_ports ft601_data[13]]
+set_property PACKAGE_PIN N22  [get_ports ft601_data[14]]
+set_property PACKAGE_PIN N20  [get_ports ft601_data[15]]
+set_property PACKAGE_PIN P15  [get_ports ft601_data[16]]
+set_property PACKAGE_PIN T21  [get_ports ft601_data[17]]
+set_property PACKAGE_PIN R16  [get_ports ft601_data[18]]
+# OLD  ft601_data[19]
+set_property PACKAGE_PIN T20  [get_ports ft601_data[19]]
+# NEW  ft601_data[19]
+# set_property PACKAGE_PIN T18  [get_ports ft601_data[19]]
+set_property PACKAGE_PIN U17  [get_ports ft601_data[20]]
+set_property PACKAGE_PIN U20  [get_ports ft601_data[21]]
+set_property PACKAGE_PIN U21  [get_ports ft601_data[22]]
+set_property PACKAGE_PIN V22  [get_ports ft601_data[23]]
+set_property PACKAGE_PIN W22  [get_ports ft601_data[24]]
+set_property PACKAGE_PIN W21  [get_ports ft601_data[25]]
+set_property PACKAGE_PIN Y22  [get_ports ft601_data[26]]
+set_property PACKAGE_PIN Y21  [get_ports ft601_data[27]]
+set_property PACKAGE_PIN AB22 [get_ports ft601_data[28]]
+set_property PACKAGE_PIN AA21 [get_ports ft601_data[29]]
+set_property PACKAGE_PIN AB21 [get_ports ft601_data[30]]
+set_property PACKAGE_PIN AA20 [get_ports ft601_data[31]]
+set_property PACKAGE_PIN W17  [get_ports ft601_oe_n]
+set_property PACKAGE_PIN P16  [get_ports ft601_rd_n]
+set_property PACKAGE_PIN AA18 [get_ports ft601_rxf_n]
+set_property PACKAGE_PIN AB18 [get_ports ft601_siwu_n]
+set_property PACKAGE_PIN AA19 [get_ports ft601_txe_n]
+set_property PACKAGE_PIN W19  [get_ports ft601_wr_n]
+set_property PACKAGE_PIN N13  [get_ports ft601_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+
+set_property PACKAGE_PIN G21 [get_ports user_ld1_n]
+set_property PACKAGE_PIN G22 [get_ports user_ld2_n]
+set_property PACKAGE_PIN F19 [get_ports user_sw1_n]
+set_property PACKAGE_PIN F20 [get_ports user_sw2_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1_n user_ld2_n user_sw1_n user_sw2_n}]
+
+# SYSCLK
+set_property PACKAGE_PIN J19 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk]
+
+# FT601 CLK
+create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk]
+set_property PACKAGE_PIN K18 [get_ports ft601_clk]
+
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n]
+
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]]
+
+set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_false_path -from [get_pins {tickcount64_reg[*]/C}]
+set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
+
+#PCIe signals
+set_property PACKAGE_PIN A13 [get_ports pcie_present]
+set_property PACKAGE_PIN C13 [get_ports pcie_perst_n]
+set_property PACKAGE_PIN B13 [get_ports pcie_wake_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_present]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n]
+
+set_property PACKAGE_PIN C9 [get_ports {pcie_rx_n[0]}]
+set_property PACKAGE_PIN D9 [get_ports {pcie_rx_p[0]}]
+set_property PACKAGE_PIN C7 [get_ports {pcie_tx_n[0]}]
+set_property PACKAGE_PIN D7 [get_ports {pcie_tx_p[0]}]
+
+set_property PACKAGE_PIN E10 [get_ports pcie_clk_n]
+set_property PACKAGE_PIN F10 [get_ports pcie_clk_p]
+
+create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p]
+
+set_property CFGBVS Vcco [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

JOKOSAHS_DMA-Pcileech/src/pcileech_com.sv

@@ -0,0 +1,248 @@
+//
+// PCILeech Buffered Communication Core for either:
+//   - FT601 USB3.
+//   - FPGA RMII ETHERNET.
+//
+//
+// (c) Ulf Frisk, 2019-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+//`define ENABLE_ETH
+`define ENABLE_FT601
+
+module pcileech_com (
+    // SYS
+    input               clk,                // 100MHz SYSTEM CLK
+    input               clk_com,            // COMMUNICATION CORE CLK
+    input               rst,
+    output              led_state_txdata,
+    input               led_state_invert,
+
+    // TO/FROM FIFO
+    IfComToFifo.mp_com  dfifo,
+
+`ifdef ENABLE_FT601
+    // FT601
+    inout   [31:0]      ft601_data,
+    output  [3:0]       ft601_be,
+    input               ft601_rxf_n,
+    input               ft601_txe_n,
+    output              ft601_wr_n,
+    output              ft601_siwu_n,
+    output              ft601_rd_n,
+    output              ft601_oe_n
+`endif /* ENABLE_FT601 */    
+`ifdef ENABLE_ETH
+    // ETH
+    output              eth_clk50,
+    output              eth_rst_n,
+    input   [1:0]       eth_rx_data,
+    input               eth_crs_dv,
+    output              eth_tx_en,
+    output  [1:0]       eth_tx_data,
+    output              eth_mdc,
+    inout               eth_mdio,
+    input               eth_rx_err,
+    input   [31:0]      eth_cfg_static_addr,
+    input               eth_cfg_static_force,
+    input   [15:0]      eth_cfg_port,
+    output              eth_led_state_red,
+    output              eth_led_state_green
+`endif /* ENABLE_ETH */
+    );
+
+    // ----------------------------------------------------------------------------
+    // COMMUNICATION CORE INITIAL ON-BOARD DEFAULT RX-DATA
+    // Sometimes there is a need to perform actions - such as setting DRP-related
+    // values before the PCIe core is brought online. This is possible by specify
+    // "virtual" COM-core initial transmitted values below.
+    // ----------------------------------------------------------------------------
+    
+    bit [63:0] initial_rx [5] = '{
+            // Modify data below to set own actions - examples:
+            // - send some initial TLP on core startup.
+            // - set initial VID/PID if PCIe core has been modified.
+            // - write to DRP memory space to alter the core.
+            // replace / expand on dummy values below - for syntax of each 64-bit word
+            // please consult sources and also device_fpga.c in the LeechCore project.
+            64'h00000000_00000000,
+            64'h00000000_00000000,
+            64'h00000000_00000000,
+            64'h00000000_00000000,
+
+            // Bring the PCIe core online from initial hot-reset state. This is done by
+            // setting control bit in PCIleech FIFO CMD register. This should ideally be
+            // done after DRP&Config actions are completed - but before sending PCIe TLPs.
+            64'h00000003_80182377
+        };
+        
+    time tickcount64 = 0;
+    always @ ( posedge clk )
+        tickcount64 <= rst ? 0 : tickcount64 + 1;
+        
+    time tickcount64_com = 0;
+    always @ ( posedge clk_com )
+        tickcount64_com <= rst ? 0 : tickcount64_com + 1;
+            
+    wire        initial_rx_valid    = ~rst & (tickcount64 >= 16) & (tickcount64 < $size(initial_rx) + 16);
+    wire [63:0] initial_rx_data     = initial_rx_valid ? initial_rx[tickcount64 - 16] : 64'h0;
+    
+    // ----------------------------------------------------------------------------
+    // COMMUNICATION CORE RX DATA BELOW:
+    // 1: convert 32-bit signal into 64-bit signal using logic.
+    // 2: change clock domain from clk_com to clk using a very shallow fifo.
+    //    due to previous 32->64 conversion this will be fine if: 2*clk_com < clk. 
+    // ----------------------------------------------------------------------------
+    
+    wire [31:0] com_rx_data32;
+    wire        com_rx_valid32;
+    reg [63:0]  com_rx_data64;
+    reg [1:0]   com_rx_valid64_dw;
+    wire        com_rx_valid64 = com_rx_valid64_dw[0] & com_rx_valid64_dw[1];
+    wire [63:0] com_rx_dout;
+    wire        com_rx_valid;
+   
+    always @ ( posedge clk_com )
+        if ( rst | (~com_rx_valid32 & com_rx_valid64_dw[0] & com_rx_valid64_dw[1]) )
+            com_rx_valid64_dw <= 2'b00;
+        else if ( com_rx_valid32 && (com_rx_data32 == 32'h66665555) && (com_rx_data64[31:0] == 32'h66665555) )
+            // resync logic to allow the host to send resync data that will
+            // allow bitstream to sync to proper 32->64-bit sequence in case
+            // it should have happen to get out of sync at startup/shutdown.
+            com_rx_valid64_dw <= 2'b00;
+        else if ( com_rx_valid32 )
+            begin
+                com_rx_data64 <= (com_rx_data64 << 32) | com_rx_data32;
+                com_rx_valid64_dw <= (com_rx_valid64_dw == 2'b01) ? 2'b11 : 2'b01;
+            end
+    
+    fifo_64_64_clk2_comrx i_fifo_64_64_clk2_comrx(
+        .rst            ( rst | (tickcount64_com<2) ),
+        .wr_clk         ( clk_com                   ),
+        .rd_clk         ( clk                       ),
+        .din            ( com_rx_data64             ),
+        .wr_en          ( com_rx_valid64            ),
+        .rd_en          ( 1'b1                      ),
+        .dout           ( com_rx_dout               ),
+        .full           (                           ),
+        .empty          (                           ),
+        .valid          ( com_rx_valid              )
+    );
+    
+    assign dfifo.com_dout = initial_rx_valid ? initial_rx_data : com_rx_dout;
+    assign dfifo.com_dout_valid = initial_rx_valid | com_rx_valid;
+    
+    // ----------------------------------------------------------------------------
+    // COMMUNICATION CORE TX DATA BELOW:
+    // ----------------------------------------------------------------------------
+       
+    wire [31:0] core_din;
+    wire        core_din_empty;
+    wire        core_din_wr_en;
+    wire        core_din_ready;
+    
+    wire [31:0] com_tx_data;
+    wire        com_tx_wr_en;
+    wire        com_tx_almost_full;
+    wire        com_tx_prog_full;
+    wire        com_tx_prog_empty;
+    
+    wire        out_buffer1_almost_full;
+
+    assign dfifo.com_din_ready  = ~out_buffer1_almost_full;
+    assign led_state_txdata     = com_tx_prog_full ^ led_state_invert;
+    
+    fifo_32_32_clk1_comtx i_fifo_32_32_clk2_comtx(
+        .clk            ( clk_com                   ),
+        .srst           ( rst                       ),
+        .din            ( com_tx_data               ),
+        .wr_en          ( com_tx_wr_en              ),
+        .rd_en          ( core_din_ready            ),
+        .dout           ( core_din                  ),
+        .full           (                           ),
+        .almost_full    ( com_tx_almost_full        ),
+        .empty          ( core_din_empty            ),
+        .prog_empty     ( com_tx_prog_empty         ),  // threshold = 3
+        .prog_full      ( com_tx_prog_full          ),  // threshold = 6
+        .valid          ( core_din_wr_en            )
+    );
+    fifo_256_32_clk2_comtx i_fifo_256_32_clk2_comtx(
+        .rd_clk         ( clk_com                   ),
+        .wr_clk         ( clk                       ),
+        .rst            ( rst                       ),
+        .din            ( dfifo.com_din             ),
+        .wr_en          ( dfifo.com_din_wr_en       ),
+        .rd_en          ( ~com_tx_almost_full       ),
+        .dout           ( com_tx_data               ),
+        .full           (                           ),
+        .almost_full    ( out_buffer1_almost_full   ),
+        .empty          (                           ),
+        .valid          ( com_tx_wr_en              )
+    );
+
+    // ----------------------------------------------------
+    // FT601 USB3 BELOW:
+    // ----------------------------------------------------
+`ifdef ENABLE_FT601
+    
+    pcileech_ft601 i_pcileech_ft601(
+        // SYS
+        .clk                ( clk_com               ),
+        .rst                ( rst                   ),
+        // TO/FROM FT601 PADS
+        .FT601_DATA         ( ft601_data            ),
+        .FT601_BE           ( ft601_be              ),
+        .FT601_TXE_N        ( ft601_txe_n           ),
+        .FT601_RXF_N        ( ft601_rxf_n           ),
+        .FT601_SIWU_N       ( ft601_siwu_n          ),
+        .FT601_WR_N         ( ft601_wr_n            ),
+        .FT601_RD_N         ( ft601_rd_n            ),
+        .FT601_OE_N         ( ft601_oe_n            ),
+        // TO/FROM FIFO
+        .dout               ( com_rx_data32         ),  // -> [31:0]
+        .dout_valid         ( com_rx_valid32        ),  // ->        
+        .din                ( core_din              ),  // <- [31:0]
+        .din_wr_en          ( core_din_wr_en        ),  // <-
+        .din_req_data       ( core_din_ready        )   // ->
+    );
+`endif /* ENABLE_FT601 */
+
+    // ----------------------------------------------------
+    // UDP Ethernet Below:
+    // ----------------------------------------------------
+`ifdef ENABLE_ETH
+
+    pcileech_eth i_pcileech_eth(
+        // SYS
+        .clk                ( clk_com               ),
+        .rst                ( rst                   ),
+        // MAC/RMII
+        .eth_clk50          ( eth_clk50             ),
+        .eth_rst_n          ( eth_rst_n             ),
+        .eth_crs_dv         ( eth_crs_dv            ),
+        .eth_rx_data        ( eth_rx_data           ),
+        .eth_rx_err         ( eth_rx_err            ),
+        .eth_tx_en          ( eth_tx_en             ),
+        .eth_tx_data        ( eth_tx_data           ),
+        .eth_mdc            ( eth_mdc               ),
+        .eth_mdio           ( eth_mdio              ),
+        // CFG
+        .cfg_static_addr    ( eth_cfg_static_addr   ),  // <- [31:0]
+        .cfg_static_force   ( eth_cfg_static_force  ),  // <-
+        .cfg_port           ( eth_cfg_port          ),  // <- [15:0]
+        // State and Activity LEDs
+        .led_state_red      ( eth_led_state_red     ),  // ->
+        .led_state_green    ( eth_led_state_green   ),  // ->
+        // TO/FROM FIFO
+        .dout               ( com_rx_data32         ),  // -> [31:0]
+        .dout_valid         ( com_rx_valid32        ),  // ->
+        .din                ( core_din              ),  // <- [31:0]
+        .din_empty          ( core_din_empty        ),  // <-
+        .din_wr_en          ( core_din_wr_en        ),  // <-
+        .din_ready          ( core_din_ready        )   // ->       
+    );
+`endif /* ENABLE_ETH */
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_enigma_x1.xdc

@@ -0,0 +1,115 @@
+set_property PACKAGE_PIN V20  [get_ports ft601_be[0]]
+set_property PACKAGE_PIN V19  [get_ports ft601_be[1]]
+set_property PACKAGE_PIN W20  [get_ports ft601_be[2]]
+set_property PACKAGE_PIN AB20 [get_ports ft601_be[3]]
+set_property PACKAGE_PIN H20  [get_ports ft601_data[0]]
+set_property PACKAGE_PIN H22  [get_ports ft601_data[1]]
+set_property PACKAGE_PIN J21  [get_ports ft601_data[2]]
+set_property PACKAGE_PIN J22  [get_ports ft601_data[3]]
+set_property PACKAGE_PIN K21  [get_ports ft601_data[4]]
+set_property PACKAGE_PIN K22  [get_ports ft601_data[5]]
+set_property PACKAGE_PIN L21  [get_ports ft601_data[6]]
+set_property PACKAGE_PIN N18  [get_ports ft601_data[7]]
+set_property PACKAGE_PIN M18  [get_ports ft601_data[8]]
+set_property PACKAGE_PIN L20  [get_ports ft601_data[9]]
+set_property PACKAGE_PIN L19  [get_ports ft601_data[10]]
+set_property PACKAGE_PIN M20  [get_ports ft601_data[11]]
+set_property PACKAGE_PIN M22  [get_ports ft601_data[12]]
+set_property PACKAGE_PIN M21  [get_ports ft601_data[13]]
+set_property PACKAGE_PIN N22  [get_ports ft601_data[14]]
+set_property PACKAGE_PIN N20  [get_ports ft601_data[15]]
+set_property PACKAGE_PIN P15  [get_ports ft601_data[16]]
+set_property PACKAGE_PIN T21  [get_ports ft601_data[17]]
+set_property PACKAGE_PIN R16  [get_ports ft601_data[18]]
+# OLD  ft601_data[19]
+#set_property PACKAGE_PIN T20  [get_ports ft601_data[19]]
+# NEW  ft601_data[19]
+set_property PACKAGE_PIN T18  [get_ports ft601_data[19]]
+set_property PACKAGE_PIN U17  [get_ports ft601_data[20]]
+set_property PACKAGE_PIN U20  [get_ports ft601_data[21]]
+set_property PACKAGE_PIN U21  [get_ports ft601_data[22]]
+set_property PACKAGE_PIN V22  [get_ports ft601_data[23]]
+set_property PACKAGE_PIN W22  [get_ports ft601_data[24]]
+set_property PACKAGE_PIN W21  [get_ports ft601_data[25]]
+set_property PACKAGE_PIN Y22  [get_ports ft601_data[26]]
+set_property PACKAGE_PIN Y21  [get_ports ft601_data[27]]
+set_property PACKAGE_PIN AB22 [get_ports ft601_data[28]]
+set_property PACKAGE_PIN AA21 [get_ports ft601_data[29]]
+set_property PACKAGE_PIN AB21 [get_ports ft601_data[30]]
+set_property PACKAGE_PIN AA20 [get_ports ft601_data[31]]
+set_property PACKAGE_PIN W17  [get_ports ft601_oe_n]
+set_property PACKAGE_PIN P16  [get_ports ft601_rd_n]
+set_property PACKAGE_PIN AA18 [get_ports ft601_rxf_n]
+set_property PACKAGE_PIN AB18 [get_ports ft601_siwu_n]
+set_property PACKAGE_PIN AA19 [get_ports ft601_txe_n]
+set_property PACKAGE_PIN W19  [get_ports ft601_wr_n]
+set_property PACKAGE_PIN N13  [get_ports ft601_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+
+set_property PACKAGE_PIN G21 [get_ports user_ld1_n]
+set_property PACKAGE_PIN G22 [get_ports user_ld2_n]
+set_property PACKAGE_PIN F19 [get_ports user_sw1_n]
+set_property PACKAGE_PIN F20 [get_ports user_sw2_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1_n user_ld2_n user_sw1_n user_sw2_n}]
+
+# SYSCLK
+set_property PACKAGE_PIN J19 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk]
+
+# FT601 CLK
+create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk]
+set_property PACKAGE_PIN K18 [get_ports ft601_clk]
+
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n]
+
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]]
+
+set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_false_path -from [get_pins {tickcount64_reg[*]/C}]
+set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
+
+#PCIe signals
+set_property PACKAGE_PIN A13 [get_ports pcie_present]
+set_property PACKAGE_PIN C13 [get_ports pcie_perst_n]
+set_property PACKAGE_PIN B13 [get_ports pcie_wake_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_present]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n]
+
+set_property PACKAGE_PIN C9 [get_ports {pcie_rx_n[0]}]
+set_property PACKAGE_PIN D9 [get_ports {pcie_rx_p[0]}]
+set_property PACKAGE_PIN C7 [get_ports {pcie_tx_n[0]}]
+set_property PACKAGE_PIN D7 [get_ports {pcie_tx_p[0]}]
+
+set_property PACKAGE_PIN E10 [get_ports pcie_clk_n]
+set_property PACKAGE_PIN F10 [get_ports pcie_clk_p]
+
+create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p]
+
+set_property CFGBVS Vcco [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

JOKOSAHS_DMA-Pcileech/src/pcileech_enigma_x1_top.sv

@@ -0,0 +1,166 @@
+//
+// PCILeech FPGA.
+//
+// Top module for the Enigma X1 Artix-7 board.
+//
+// (c) Ulf Frisk, 2019-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_enigma_x1_top #(
+    // DEVICE IDs as follows:
+    // 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer, 5 = NeTV2
+    parameter       PARAM_DEVICE_ID = 9,
+    parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
+    parameter       PARAM_VERSION_NUMBER_MINOR = 13,
+    parameter       PARAM_CUSTOM_VALUE = 32'hffffffff
+) (
+    // SYS
+    input           clk,
+    input           ft601_clk,
+    
+    // SYSTEM LEDs and BUTTONs
+    output          user_ld1_n,
+    output          user_ld2_n,
+    input           user_sw1_n,
+    input           user_sw2_n,
+    
+    // PCI-E FABRIC
+    output  [0:0]   pcie_tx_p,
+    output  [0:0]   pcie_tx_n,
+    input   [0:0]   pcie_rx_p,
+    input   [0:0]   pcie_rx_n,
+    input           pcie_clk_p,
+    input           pcie_clk_n,
+    input           pcie_present,
+    input           pcie_perst_n,
+    output reg      pcie_wake_n = 1'b1,
+    
+    // TO/FROM FT601 PADS
+    output          ft601_rst_n,
+    
+    inout   [31:0]  ft601_data,
+    output  [3:0]   ft601_be,
+    input           ft601_rxf_n,
+    input           ft601_txe_n,
+    output          ft601_wr_n,
+    output          ft601_siwu_n,
+    output          ft601_rd_n,
+    output          ft601_oe_n
+    );
+    
+    // SYS
+    wire            rst;
+    
+    // FIFO CTL <--> COM CTL
+    wire [63:0]     com_dout;
+    wire            com_dout_valid;
+    wire [255:0]    com_din;
+    wire            com_din_wr_en;
+    wire            com_din_ready;
+    wire            led_com;
+    wire            led_pcie;
+    
+    // FIFO CTL <--> COM CTL
+    IfComToFifo     dcom_fifo();
+	
+    // FIFO CTL <--> PCIe
+    IfPCIeFifoCfg   dcfg();
+    IfPCIeFifoTlp   dtlp();
+    IfPCIeFifoCore  dpcie();
+    IfShadow2Fifo   dshadow2fifo();
+	
+    // ----------------------------------------------------
+    // TickCount64 CLK
+    // ----------------------------------------------------
+
+    time tickcount64 = 0;
+    time tickcount64_reload = 0;
+    always @ ( posedge clk ) begin
+        tickcount64         <= user_sw2_n ? (tickcount64 + 1) : 0;
+        tickcount64_reload  <= user_sw2_n ? 0 : (tickcount64_reload + 1);
+    end
+
+    assign rst = ~user_sw2_n || ((tickcount64 < 64) ? 1'b1 : 1'b0);
+    assign ft601_rst_n = ~rst;
+    wire led_pwronblink = ~user_sw1_n ^ (tickcount64[24] & (tickcount64[63:27] == 0));
+    
+    OBUF led_ld1_obuf(.O(user_ld1_n), .I(~led_pcie));
+    OBUF led_ld2_obuf(.O(user_ld2_n), .I(~led_com));
+    
+    // ----------------------------------------------------
+    // BUFFERED COMMUNICATION DEVICE (FT601)
+    // ----------------------------------------------------
+    
+    pcileech_com i_pcileech_com (
+        // SYS
+        .clk                ( clk                   ),
+        .clk_com            ( ft601_clk             ),
+        .rst                ( rst                   ),
+        .led_state_txdata   ( led_com               ),  // ->
+        .led_state_invert   ( led_pwronblink        ),  // <-
+        // FIFO CTL <--> COM CTL
+        .dfifo              ( dcom_fifo.mp_com      ),
+        // TO/FROM FT601 PADS
+        .ft601_data         ( ft601_data            ),  // <> [31:0]
+        .ft601_be           ( ft601_be              ),  // -> [3:0]
+        .ft601_txe_n        ( ft601_txe_n           ),  // <-
+        .ft601_rxf_n        ( ft601_rxf_n           ),  // <-
+        .ft601_siwu_n       ( ft601_siwu_n          ),  // ->
+        .ft601_wr_n         ( ft601_wr_n            ),  // ->
+        .ft601_rd_n         ( ft601_rd_n            ),  // ->
+        .ft601_oe_n         ( ft601_oe_n            )   // ->
+    );
+    
+    // ----------------------------------------------------
+    // FIFO CTL
+    // ----------------------------------------------------
+    
+    pcileech_fifo #(
+        .PARAM_DEVICE_ID            ( PARAM_DEVICE_ID               ),
+        .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR    ),
+        .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR    ),
+        .PARAM_CUSTOM_VALUE         ( PARAM_CUSTOM_VALUE            )
+    ) i_pcileech_fifo (
+        .clk                ( clk                   ),
+        .rst                ( rst                   ),
+        .rst_cfg_reload     ( (tickcount64_reload > 500000000) ? 1'b1 : 1'b0 ),     // config reload after 5s button press
+        .pcie_present       ( pcie_present          ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // FIFO CTL <--> COM CTL
+        .dcom               ( dcom_fifo.mp_fifo     ),
+        // FIFO CTL <--> PCIe
+        .dcfg               ( dcfg.mp_fifo          ),
+        .dtlp               ( dtlp.mp_fifo          ),
+        .dpcie              ( dpcie.mp_fifo         ),
+        .dshadow2fifo       ( dshadow2fifo.fifo     )
+    );
+    
+    // ----------------------------------------------------
+    // PCIe
+    // ----------------------------------------------------
+    
+    pcileech_pcie_a7 i_pcileech_pcie_a7(
+        .clk_sys            ( clk                   ),
+        .rst                ( rst                   ),
+        // PCIe fabric
+        .pcie_tx_p          ( pcie_tx_p             ),
+        .pcie_tx_n          ( pcie_tx_n             ),
+        .pcie_rx_p          ( pcie_rx_p             ),
+        .pcie_rx_n          ( pcie_rx_n             ),
+        .pcie_clk_p         ( pcie_clk_p            ),
+        .pcie_clk_n         ( pcie_clk_n            ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // State and Activity LEDs
+        .led_state          ( led_pcie              ),
+        // FIFO CTL <--> PCIe
+        .dfifo_cfg          ( dcfg.mp_pcie          ),
+        .dfifo_tlp          ( dtlp.mp_pcie          ),
+        .dfifo_pcie         ( dpcie.mp_pcie         ),
+        .dshadow2fifo       ( dshadow2fifo.shadow   )
+    );
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_fifo.sv

@@ -0,0 +1,458 @@
+//
+// PCILeech FPGA.
+//
+// FIFO network / control.
+//
+// (c) Ulf Frisk, 2017-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+// Special thanks to: Dmytro Oleksiuk @d_olex
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+`define ENABLE_STARTUPE2
+
+module pcileech_fifo #(
+    parameter               PARAM_DEVICE_ID = 0,
+    parameter               PARAM_VERSION_NUMBER_MAJOR = 0,
+    parameter               PARAM_VERSION_NUMBER_MINOR = 0,
+    parameter               PARAM_CUSTOM_VALUE = 0
+) (
+    input                   clk,
+    input                   rst,
+    input                   rst_cfg_reload,
+    
+    input                   pcie_present,
+    input                   pcie_perst_n,
+    
+    IfComToFifo.mp_fifo     dcom,
+    
+    IfPCIeFifoCfg.mp_fifo   dcfg,
+    IfPCIeFifoTlp.mp_fifo   dtlp,
+    IfPCIeFifoCore.mp_fifo  dpcie,
+    IfShadow2Fifo.fifo      dshadow2fifo
+    );
+      
+    // ----------------------------------------------------
+    // TickCount64
+    // ----------------------------------------------------
+    
+    time tickcount64 = 0;
+    always @ ( posedge clk )
+        tickcount64 <= tickcount64 + 1;
+   
+    // ----------------------------------------------------------------------------
+    // RX FROM USB/FT601/FT245 BELOW:
+    // ----------------------------------------------------------------------------
+    // Incoming data received from FT601 is converted from 32-bit to 64-bit.
+    // This always happen regardless whether receiving FIFOs are full or not.
+    // The actual data contains a MAGIC which tells which receiving FIFO should
+    // accept the data. Receiving TYPEs are: PCIe TLP, PCIe CFG, Loopback, Command.
+    //
+    //         /--> PCIe TLP (32-bit)
+    //         |
+    // FT601 --+--> PCIe CFG (64-bit)
+    //         |
+    //         +--> LOOPBACK (32-bit)
+    //         |
+    //         \--> COMMAND  (64-bit)
+    //
+            
+    // ----------------------------------------------------------
+    // Route 64-bit incoming FT601 data to correct receiver below:
+    // ----------------------------------------------------------
+    `define CHECK_MAGIC     (dcom.com_dout[7:0] == 8'h77)
+    `define CHECK_TYPE_TLP  (dcom.com_dout[9:8] == 2'b00)
+    `define CHECK_TYPE_CFG  (dcom.com_dout[9:8] == 2'b01)
+    `define CHECK_TYPE_LOOP (dcom.com_dout[9:8] == 2'b10)
+    `define CHECK_TYPE_CMD  (dcom.com_dout[9:8] == 2'b11)
+    
+    assign   dtlp.tx_valid = dcom.com_dout_valid & `CHECK_MAGIC & `CHECK_TYPE_TLP;
+    assign   dcfg.tx_valid = dcom.com_dout_valid & `CHECK_MAGIC & `CHECK_TYPE_CFG;
+    wire     _loop_rx_wren = dcom.com_dout_valid & `CHECK_MAGIC & `CHECK_TYPE_LOOP;
+    wire     _cmd_rx_wren  = dcom.com_dout_valid & `CHECK_MAGIC & `CHECK_TYPE_CMD;
+    
+    // Incoming TLPs are forwarded to PCIe core logic.
+    assign dtlp.tx_data = dcom.com_dout[63:32];
+    assign dtlp.tx_last = dcom.com_dout[10];
+    // Incoming CFGs are forwarded to PCIe core logic.
+    assign dcfg.tx_data = dcom.com_dout;
+
+    // ----------------------------------------------------------------------------
+    // TX TO USB/FT601/FT245 BELOW:
+    // ----------------------------------------------------------------------------
+    //
+    //                                         MULTIPLEXER
+    //                                         ===========
+    //                                         1st priority
+    // PCIe TLP ->(32-bit) --------------------->--\
+    //                                         2nd |    /-----------------------------------------\
+    // PCIe CFG ->(32-bit)---------------------->--+--> | 256-> BUFFER FIFO (NATIVE OR DRAM) ->32 | -> FT601
+    //                                             |    \-----------------------------------------/
+    //            /--------------------------\ 3rd |
+    // FT601   -> | 34->  Loopback FIFO ->34 | ->--/
+    //            \--------------------------/     | 
+    //                                             |
+    //            /--------------------------\ 4th |
+    // COMMAND -> | 34->  Command FIFO  ->34 | ->--/
+    //            \--------------------------/
+    //
+   
+    // ----------------------------------------------------------
+    // LOOPBACK FIFO:
+    // ----------------------------------------------------------
+    wire [33:0]       _loop_dout;
+    wire              _loop_valid;
+    wire              _loop_rd_en;
+    fifo_34_34 i_fifo_loop_tx(
+        .clk            ( clk                       ),
+        .srst           ( rst                       ),
+        .rd_en          ( _loop_rd_en               ),
+        .dout           ( _loop_dout                ),
+        .din            ( {dcom.com_dout[11:10], dcom.com_dout[63:32]} ),
+        .wr_en          ( _loop_rx_wren             ),
+        .full           (                           ),
+        .almost_full    (                           ),
+        .empty          (                           ),
+        .valid          ( _loop_valid               )
+    );
+   
+    // ----------------------------------------------------------
+    // COMMAND FIFO:
+    // ----------------------------------------------------------
+    wire [33:0]       _cmd_tx_dout;
+    wire              _cmd_tx_valid;
+    wire              _cmd_tx_rd_en;
+    wire              _cmd_tx_almost_full;
+    reg               _cmd_tx_wr_en;
+    reg [33:0]        _cmd_tx_din;
+    fifo_34_34 i_fifo_cmd_tx(
+        .clk            ( clk                       ),
+        .srst           ( rst                       ),
+        .rd_en          ( _cmd_tx_rd_en             ),
+        .dout           ( _cmd_tx_dout              ),
+        .din            ( _cmd_tx_din               ),
+        .wr_en          ( _cmd_tx_wr_en             ),
+        .full           (                           ),
+        .almost_full    ( _cmd_tx_almost_full       ),
+        .empty          (                           ),
+        .valid          ( _cmd_tx_valid             )
+    );
+
+    // ----------------------------------------------------------
+    // MULTIPLEXER
+    // ----------------------------------------------------------
+    pcileech_mux i_pcileech_mux(
+        .clk            ( clk                           ),
+        .rst            ( rst                           ),
+        // output
+        .dout           ( dcom.com_din                  ),
+        .valid          ( dcom.com_din_wr_en            ),
+        .rd_en          ( dcom.com_din_ready            ),
+        // LOOPBACK:
+        .p0_din         ( _loop_dout[31:0]              ),
+        .p0_tag         ( 2'b10                         ),
+        .p0_ctx         ( _loop_dout[33:32]             ),
+        .p0_wr_en       ( _loop_valid                   ),
+        .p0_req_data    ( _loop_rd_en                   ),
+        // COMMAND:
+        .p1_din         ( _cmd_tx_dout[31:0]            ),
+        .p1_tag         ( 2'b11                         ),
+        .p1_ctx         ( _cmd_tx_dout[33:32]           ),
+        .p1_wr_en       ( _cmd_tx_valid                 ),
+        .p1_req_data    ( _cmd_tx_rd_en                 ),
+        // PCIe CFG
+        .p2_din         ( dcfg.rx_data                  ),
+        .p2_tag         ( 2'b01                         ),
+        .p2_ctx         ( 2'b00                         ),
+        .p2_wr_en       ( dcfg.rx_valid                 ),
+        .p2_req_data    ( dcfg.rx_rd_en                 ),
+        // PCIe TLP #1
+        .p3_din         ( dtlp.rx_data[0]               ),
+        .p3_tag         ( 2'b00                         ),
+        .p3_ctx         ( {dtlp.rx_first[0], dtlp.rx_last[0]} ),
+        .p3_wr_en       ( dtlp.rx_valid[0]              ),
+        .p3_req_data    ( dtlp.rx_rd_en                 ),
+        // PCIe TLP #2
+        .p4_din         ( dtlp.rx_data[1]               ),
+        .p4_tag         ( 2'b00                         ),
+        .p4_ctx         ( {dtlp.rx_first[1], dtlp.rx_last[1]} ),
+        .p4_wr_en       ( dtlp.rx_valid[1]              ),
+        .p4_req_data    (                               ),
+        // PCIe TLP #3
+        .p5_din         ( dtlp.rx_data[2]               ),
+        .p5_tag         ( 2'b00                         ),
+        .p5_ctx         ( {dtlp.rx_first[2], dtlp.rx_last[2]} ),
+        .p5_wr_en       ( dtlp.rx_valid[2]              ),
+        .p5_req_data    ( dtlp.rx_rd_en                 ),
+        // PCIe TLP #4
+        .p6_din         ( dtlp.rx_data[3]               ),
+        .p6_tag         ( 2'b00                         ),
+        .p6_ctx         ( {dtlp.rx_first[3], dtlp.rx_last[3]} ),
+        .p6_wr_en       ( dtlp.rx_valid[3]              ),
+        .p6_req_data    (                               ),
+        // P7
+        .p7_din         ( 32'h00000000                  ),
+        .p7_tag         ( 2'b11                         ),
+        .p7_ctx         ( 2'b00                         ),
+        .p7_wr_en       ( 1'b0                          ),
+        .p7_req_data    (                               )
+    );
+   
+    // ------------------------------------------------------------------------
+    // COMMAND / CONTROL FIFO: REGISTER FILE: COMMON
+    // ------------------------------------------------------------------------
+    
+    localparam          RWPOS_WAIT_COMPLETE         = 18;   // WAIT FOR DRP COMPLETION
+    localparam          RWPOS_DRP_RD_EN             = 20;
+    localparam          RWPOS_DRP_WR_EN             = 21;
+    localparam          RWPOS_GLOBAL_SYSTEM_RESET   = 31;
+    
+    wire    [319:0]     ro;
+    reg     [239:0]     rw;
+    
+    // special non-user accessible registers 
+    reg     [79:0]      _pcie_core_config = { 4'hf, 1'b1, 1'b1, 1'b0, 1'b0, 8'h02, 16'h0666, 16'h10EE, 16'h0007, 16'h10EE };
+    time                _cmd_timer_inactivity_base;
+    reg                 rwi_drp_rd_en;
+    reg                 rwi_drp_wr_en;
+    reg     [15:0]      rwi_drp_data;
+    
+    // ------------------------------------------------------------------------
+    // COMMAND / CONTROL FIFO: REGISTER FILE: READ-ONLY LAYOUT/SPECIFICATION
+    // ------------------------------------------------------------------------
+    
+    // MAGIC
+    assign ro[15:0]     = 16'hab89;                     // +000: MAGIC
+    // SPECIAL
+    assign ro[19:16]    = 0;                            // +002: SPECIAL
+    assign ro[20]       = rwi_drp_rd_en;                //
+    assign ro[21]       = rwi_drp_wr_en;                //
+    assign ro[31:22]    = 0;                            //
+    // SIZEOF / BYTECOUNT [little-endian]
+    assign ro[63:32]    = $bits(ro) >> 3;               // +004: SIZEOF / BYTECOUNT [little-endian]
+    // ID: VERSION & DEVICE
+    assign ro[71:64]    = PARAM_VERSION_NUMBER_MAJOR;   // +008: VERSION MAJOR
+    assign ro[79:72]    = PARAM_VERSION_NUMBER_MINOR;   // +009: VERSION MINOR
+    assign ro[87:80]    = PARAM_DEVICE_ID;              // +00A: DEVICE ID
+    assign ro[127:88]   = 0;                            // +00B: SLACK
+    // UPTIME (tickcount64*100MHz)
+    assign ro[191:128]   = tickcount64;                 // +010: UPTIME (tickcount64*100MHz)
+    // INACTIVITY TIMER
+    assign ro[255:192]  = _cmd_timer_inactivity_base;   // +018: INACTIVITY TIMER
+    // PCIe DRP 
+    assign ro[271:256]  = rwi_drp_data;                 // +020: DRP: pcie_drp_do
+    // PCIe
+    assign ro[272]      = pcie_present;                 // +022: PCIe PRSNT#
+    assign ro[273]      = pcie_perst_n;                 //       PCIe PERST#
+    assign ro[287:274]  = 0;                            //       SLACK
+    // CUSTOM_VALUE
+    assign ro[319:288]  = PARAM_CUSTOM_VALUE;           // +024: CUSTOM VALUE
+    // +028
+    
+    // ------------------------------------------------------------------------
+    // INITIALIZATION/RESET BLOCK _AND_
+    // COMMAND / CONTROL FIFO: REGISTER FILE: READ-WRITE LAYOUT/SPECIFICATION
+    // ------------------------------------------------------------------------
+    
+    task pcileech_fifo_ctl_initialvalues;               // task is non automatic
+        begin
+            _cmd_tx_wr_en  <= 1'b0;
+               
+            // MAGIC
+            rw[15:0]    <= 16'hefcd;                    // +000: MAGIC
+            // SPECIAL
+            rw[16]      <= 0;                           // +002: enable inactivity timer
+            rw[17]      <= 0;                           //       enable send count
+            rw[18]      <= 1;                           //       WAIT FOR PCIe DRP RD/WR COMPLETION BEFORE ACCEPT NEW FIFO READ/WRITES
+            rw[19]      <= 0;                           //       SLACK
+            rw[20]      <= 0;                           //       DRP RD EN
+            rw[21]      <= 0;                           //       DRP WR EN
+            rw[30:22]   <= 0;                           //       RESERVED FUTURE
+            rw[31]      <= 0;                           //       global system reset (GSR) via STARTUPE2 primitive
+            // SIZEOF / BYTECOUNT [little-endian]
+            rw[63:32]   <= $bits(rw) >> 3;              // +004: bytecount [little endian]
+            // CMD INACTIVITY TIMER TRIGGER VALUE
+            rw[95:64]   <= 0;                           // +008: cmd_inactivity_timer (ticks) [little-endian]
+            // CMD SEND COUNT
+            rw[127:96]  <= 0;                           // +00C: cmd_send_count [little-endian]
+            // PCIE INITIAL CONFIG (SPECIAL BITSTREAM)
+            // NB! "initial" CLK0 values may also be changed in: '_pcie_core_config = {...};' [important on PCIeScreamer].
+            rw[143:128] <= 16'h10EE;                    // +010: CFG_SUBSYS_VEND_ID (NOT IMPLEMENTED)
+            rw[159:144] <= 16'h0007;                    // +012: CFG_SUBSYS_ID      (NOT IMPLEMENTED)
+            rw[175:160] <= 16'h10EE;                    // +014: CFG_VEND_ID        (NOT IMPLEMENTED)
+            rw[191:176] <= 16'h0666;                    // +016: CFG_DEV_ID         (NOT IMPLEMENTED)
+            rw[199:192] <= 8'h02;                       // +018: CFG_REV_ID         (NOT IMPLEMENTED)
+            rw[200]     <= 1'b1;                        // +019: PCIE CORE RESET
+            rw[201]     <= 1'b0;                        //       PCIE SUBSYSTEM RESET
+            rw[202]     <= 1'b1;                        //       CFGTLP PROCESSING ENABLE
+            rw[203]     <= 1'b1;                        //       CFGTLP ZERO DATA
+            rw[204]     <= 1'b1;                        //       CFGTLP FILTER TLP FROM USER
+            rw[205]     <= 1'b1;                        //       PCIE BAR PIO ON-BOARD PROCESSING ENABLE
+            rw[206]     <= 1'b0;                        //       CFGTLP PCIE WRITE ENABLE
+            rw[207]     <= 1'b1;                        //       TLP FILTER FROM USER: EXCEPT: Cpl,CplD and CfgRd/CfgWr (handled by rw[204])
+            // PCIe DRP, PRSNT#, PERST#
+            rw[208+:16] <= 0;                           // +01A: DRP: pcie_drp_di
+            rw[224+:9]  <= 0;                           // +01C: DRP: pcie_drp_addr
+            rw[233+:7]  <= 0;                           //       SLACK
+            // 01E -  
+             
+        end
+    endtask
+    
+    wire                _cmd_timer_inactivity_enable    = rw[16];
+    wire    [31:0]      _cmd_timer_inactivity_ticks     = rw[95:64];
+    wire    [15:0]      _cmd_send_count_dword           = rw[63:32];
+    wire                _cmd_send_count_enable          = rw[17] & (_cmd_send_count_dword != 16'h0000);
+    
+    always @ ( posedge clk )
+         _pcie_core_config <= rw[207:128];
+    assign dpcie.pcie_rst_core                          = _pcie_core_config[72];
+    assign dpcie.pcie_rst_subsys                        = _pcie_core_config[73];
+    assign dshadow2fifo.cfgtlp_en                       = _pcie_core_config[74];
+    assign dshadow2fifo.cfgtlp_zero                     = _pcie_core_config[75];
+    assign dshadow2fifo.cfgtlp_filter                   = _pcie_core_config[76];
+    assign dshadow2fifo.bar_en                          = _pcie_core_config[77];
+    assign dshadow2fifo.cfgtlp_wren                     = _pcie_core_config[78];
+    assign dshadow2fifo.alltlp_filter                   = _pcie_core_config[79];
+    assign dpcie.drp_en                                 = rw[RWPOS_DRP_WR_EN] | rw[RWPOS_DRP_RD_EN];
+    assign dpcie.drp_we                                 = rw[RWPOS_DRP_WR_EN];
+    assign dpcie.drp_addr                               = rw[224+:9];
+    assign dpcie.drp_di                                 = rw[208+:16];
+    
+    // ------------------------------------------------------------------------
+    // COMMAND / CONTROL FIFO: STATE MACHINE / LOGIC FOR READ/WRITE AND OTHER HOUSEKEEPING TASKS
+    // ------------------------------------------------------------------------
+ 
+    wire [63:0] cmd_rx_dout;
+    wire        cmd_rx_valid;
+    wire        cmd_rx_rd_en_drp = rwi_drp_rd_en | rwi_drp_wr_en | rw[RWPOS_DRP_RD_EN] | rw[RWPOS_DRP_WR_EN];
+    wire        cmd_rx_rd_en = tickcount64[1] & ( ~rw[RWPOS_WAIT_COMPLETE] | ~cmd_rx_rd_en_drp);
+    
+    fifo_64_64_clk1_fifocmd i_fifo_cmd_rx(
+        .clk            ( clk                       ),
+        .srst           ( rst                       ),
+        .rd_en          ( cmd_rx_rd_en              ),
+        .dout           ( cmd_rx_dout               ),
+        .din            ( dcom.com_dout             ),
+        .wr_en          ( _cmd_rx_wren              ),
+        .full           (                           ),
+        .empty          (                           ),
+        .valid          ( cmd_rx_valid              )
+    );
+    
+    integer i_write;
+    wire [15:0] in_cmd_address_byte = cmd_rx_dout[31:16];
+    wire [17:0] in_cmd_address_bit  = {in_cmd_address_byte[14:0], 3'b000};
+    wire [15:0] in_cmd_value        = {cmd_rx_dout[48+:8], cmd_rx_dout[56+:8]};
+    wire [15:0] in_cmd_mask         = {cmd_rx_dout[32+:8], cmd_rx_dout[40+:8]};
+    wire        f_rw                = in_cmd_address_byte[15];
+    wire        f_shadowcfgspace    = in_cmd_address_byte[14];
+    wire [15:0] in_cmd_data_in      = (in_cmd_address_bit < (f_rw ? $bits(rw) : $bits(ro))) ? (f_rw ? rw[in_cmd_address_bit+:16] : ro[in_cmd_address_bit+:16]) : 16'h0000;
+    wire        in_cmd_read         = cmd_rx_valid & cmd_rx_dout[12] & ~f_shadowcfgspace;
+    wire        in_cmd_write        = cmd_rx_valid & cmd_rx_dout[13] & ~f_shadowcfgspace & f_rw;
+    assign dshadow2fifo.rx_rden     = cmd_rx_valid & cmd_rx_dout[12] &  f_shadowcfgspace;
+    assign dshadow2fifo.rx_wren     = cmd_rx_valid & cmd_rx_dout[13] &  f_shadowcfgspace & f_rw;
+    assign dshadow2fifo.rx_be       = {(in_cmd_mask[7:0] > 0 ? ~in_cmd_address_byte[1] : 1'b0), (in_cmd_mask[15:8] > 0 ? ~in_cmd_address_byte[1] : 1'b0), (in_cmd_mask[7:0] > 0 ? in_cmd_address_byte[1] : 1'b0), (in_cmd_mask[15:8] > 0 ? in_cmd_address_byte[1] : 1'b0)};
+    assign dshadow2fifo.rx_addr     = in_cmd_address_byte[11:2];
+    assign dshadow2fifo.rx_addr_lo  = in_cmd_address_byte[1];
+    assign dshadow2fifo.rx_data     = {in_cmd_value[7:0], in_cmd_value[15:8], in_cmd_value[7:0], in_cmd_value[15:8]};
+    
+    initial pcileech_fifo_ctl_initialvalues();
+    
+    always @ ( posedge clk )
+        if ( rst )
+            pcileech_fifo_ctl_initialvalues();
+        else
+            begin
+                // SHADOW CONFIG SPACE RESPONSE
+                if ( dshadow2fifo.tx_valid )
+                    begin
+                        _cmd_tx_wr_en       <= 1'b1;
+                        _cmd_tx_din[31:16]  <= {4'b1100, dshadow2fifo.tx_addr, dshadow2fifo.tx_addr_lo, 1'b0};
+                        _cmd_tx_din[15:0]   <= dshadow2fifo.tx_addr_lo ? dshadow2fifo.tx_data[15:0] : dshadow2fifo.tx_data[31:16];                        
+                    end
+                // READ config
+                else if ( in_cmd_read )
+                    begin
+                        _cmd_tx_wr_en       <= 1'b1;
+                        _cmd_tx_din[31:16]  <= in_cmd_address_byte;
+                        _cmd_tx_din[15:0]   <= {in_cmd_data_in[7:0], in_cmd_data_in[15:8]};
+                    end
+                // SEND COUNT ACTION
+                else if ( ~_cmd_tx_almost_full & ~in_cmd_write & _cmd_send_count_enable )
+                    begin
+                        _cmd_tx_wr_en       <= 1'b1;
+                        _cmd_tx_din[31:16]  <= 16'hfffe;
+                        _cmd_tx_din[15:0]   <= _cmd_send_count_dword;
+                        rw[63:32]           <= _cmd_send_count_dword - 1;
+                    end
+                // INACTIVITY TIMER ACTION
+                else if ( ~_cmd_tx_almost_full & ~in_cmd_write & _cmd_timer_inactivity_enable & (_cmd_timer_inactivity_ticks + _cmd_timer_inactivity_base < tickcount64) )
+                    begin
+                        _cmd_tx_wr_en       <= 1'b1;
+                        _cmd_tx_din[31:16]  <= 16'hffff;
+                        _cmd_tx_din[15:0]   <= 16'hcede;
+                        rw[16]              <= 1'b0;
+                    end
+                else
+                    _cmd_tx_wr_en <= 1'b0;
+
+                // WRITE config
+                if ( tickcount64 < 8 )
+                    pcileech_fifo_ctl_initialvalues();
+                else if ( in_cmd_write )
+                    for ( i_write = 0; i_write < 16; i_write = i_write + 1 )
+                        begin
+                            if ( in_cmd_mask[i_write] )
+                                rw[in_cmd_address_bit+i_write] <= in_cmd_value[i_write];
+                        end
+
+                // UPDATE INACTIVITY TIMER BASE
+                if ( dcom.com_din_wr_en | ~dcom.com_din_ready )
+                    _cmd_timer_inactivity_base <= tickcount64;  
+                    
+                // DRP READ/WRITE                        
+                if ( dpcie.drp_rdy )
+                    begin
+                        rwi_drp_rd_en   <= 1'b0;
+                        rwi_drp_wr_en   <= 1'b0;
+                        rwi_drp_data    <= dpcie.drp_do;
+                    end
+                else if ( rw[RWPOS_DRP_RD_EN] | rw[RWPOS_DRP_WR_EN] )
+                    begin
+                        rw[RWPOS_DRP_RD_EN] <= 1'b0;
+                        rw[RWPOS_DRP_WR_EN] <= 1'b0;
+                        rwi_drp_rd_en <= rwi_drp_rd_en | rw[RWPOS_DRP_RD_EN];
+                        rwi_drp_wr_en <= rwi_drp_wr_en | rw[RWPOS_DRP_WR_EN];
+                    end      
+            
+            end
+
+    // ----------------------------------------------------
+    // GLOBAL SYSTEM RESET:  ( provided via STARTUPE2 primitive )
+    // ----------------------------------------------------
+`ifdef ENABLE_STARTUPE2
+
+    STARTUPE2 #(
+      .PROG_USR         ( "FALSE"           ),
+      .SIM_CCLK_FREQ    ( 0.0               )
+    ) i_STARTUPE2 (
+      .CFGCLK           (                   ), // ->
+      .CFGMCLK          (                   ), // ->
+      .EOS              (                   ), // ->
+      .PREQ             (                   ), // ->
+      .CLK              ( clk               ), // <-
+      .GSR              ( rw[RWPOS_GLOBAL_SYSTEM_RESET] | rst_cfg_reload ), // <- GLOBAL SYSTEM RESET
+      .GTS              ( 1'b0              ), // <-
+      .KEYCLEARB        ( 1'b0              ), // <-
+      .PACK             ( 1'b0              ), // <-
+      .USRCCLKO         ( 1'b0              ), // <-
+      .USRCCLKTS        ( 1'b0              ), // <-
+      .USRDONEO         ( 1'b1              ), // <-
+      .USRDONETS        ( 1'b1              )  // <-
+    );
+`endif /* ENABLE_STARTUPE2 */
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_ft601.sv

@@ -0,0 +1,181 @@
+//
+// PCILeech FPGA.
+//
+// FT601 / FT245 controller module (v4).
+//
+// (c) Ulf Frisk, 2017-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+
+module pcileech_ft601(
+    input               clk,
+    input               rst,
+    // TO/FROM PADS
+    output [3:0]        FT601_BE,
+    inout [31:0]        FT601_DATA,
+    input               FT601_RXF_N,
+    input               FT601_TXE_N,
+    output bit          FT601_OE_N,
+    output bit          FT601_RD_N,
+    output bit          FT601_WR_N,
+    output bit          FT601_SIWU_N,
+    // TO/FROM FIFO
+    output bit [31:0]   dout,
+    output bit          dout_valid,
+    input [31:0]        din,
+    input               din_wr_en,
+    output              din_req_data
+    );
+    
+    initial begin
+        FT601_OE_N   <= 1'b1;
+        FT601_RD_N   <= 1'b1;
+        FT601_WR_N   <= 1'b1;
+        FT601_SIWU_N <= 1'b1;
+        dout_valid   <= 1'b0;
+        dout         <= 32'h00000000;
+    end
+
+    `define S_FT601_IDLE         4'h0
+    `define S_FT601_RX_WAIT1     4'h2
+    `define S_FT601_RX_WAIT2     4'h3
+    `define S_FT601_RX_WAIT3     4'h4
+    `define S_FT601_RX_ACTIVE    4'h5
+    `define S_FT601_RX_COOLDOWN1 4'h6
+    `define S_FT601_RX_COOLDOWN2 4'h7
+    `define S_FT601_TX_WAIT1     4'h8
+    `define S_FT601_TX_WAIT2     4'h9
+    `define S_FT601_TX_ACTIVE    4'ha
+    `define S_FT601_TX_COOLDOWN1 4'hb
+    `define S_FT601_TX_COOLDOWN2 4'hc
+
+                        bit [31:0]      FT601_DATA_OUT[5];
+    (* KEEP = "TRUE" *) wire            FWD;
+    (* KEEP = "TRUE" *) bit             OE                  = 1'b1;
+    (* KEEP = "TRUE" *) bit [3:0]       data_cooldown_count = 0;
+    (* KEEP = "TRUE" *) bit [2:0]       data_queue_count    = 0;     
+    (* KEEP = "TRUE" *) bit [3:0]       state               = `S_FT601_IDLE;
+
+
+
+    // -------------------------------------------------------------------------
+    // FT245 RX / DATA INPUT BELOW:
+    // -------------------------------------------------------------------------
+
+    always @ ( posedge clk )
+        begin
+            dout_valid      <= !rst && !FT601_RXF_N && (state == `S_FT601_RX_ACTIVE);
+            dout[7:0]       <= FT601_DATA[31:24];
+            dout[15:8]      <= FT601_DATA[23:16];
+            dout[23:16]     <= FT601_DATA[15:8];
+            dout[31:24]     <= FT601_DATA[7:0];
+        end
+
+
+
+    // -------------------------------------------------------------------------
+    // FT245 TX / DATA OUTPUT BELOW:
+    // -------------------------------------------------------------------------        
+
+    assign FT601_BE     = OE ? 4'b1111 : 4'bzzzz;
+    assign FT601_DATA   = OE ? {FT601_DATA_OUT[0][7:0], FT601_DATA_OUT[0][15:8], FT601_DATA_OUT[0][23:16], FT601_DATA_OUT[0][31:24]} : 32'hzzzzzzzz;
+    assign din_req_data = !rst && (data_queue_count == 2) || (data_queue_count == 3);
+    assign FWD          = !rst && !FT601_TXE_N && (data_queue_count != 0) && (state == `S_FT601_TX_ACTIVE);
+
+    always @ ( posedge clk ) begin
+        if ( rst || (data_cooldown_count == 4'hf) ) begin
+            data_cooldown_count <= 0;
+            data_queue_count    <= 5;
+            FT601_DATA_OUT[0]   <= 32'h66665555;
+            FT601_DATA_OUT[1]   <= 32'h66665555;
+            FT601_DATA_OUT[2]   <= 32'h66665555;
+            FT601_DATA_OUT[3]   <= 32'h66665555;
+            FT601_DATA_OUT[4]   <= 32'h66665555;
+        end
+        else begin
+            data_cooldown_count <= (data_queue_count == 0) ? (data_cooldown_count + 1) : 0;
+            data_queue_count    <= data_queue_count + (din_wr_en ? 3'b001 : 3'b000) - (FWD ? 3'b001 : 3'b000);
+            if ( FWD ) begin
+                if ( data_queue_count > 1 ) begin
+                    FT601_DATA_OUT[0] <= FT601_DATA_OUT[1];
+                end
+                if ( data_queue_count > 2 ) begin
+                    FT601_DATA_OUT[1] <= FT601_DATA_OUT[2];
+                end
+                if ( data_queue_count > 3 ) begin
+                    FT601_DATA_OUT[2] <= FT601_DATA_OUT[3];
+                end
+                if ( data_queue_count > 4 ) begin
+                    FT601_DATA_OUT[3] <= FT601_DATA_OUT[4];
+                end
+            end
+            if ( din_wr_en ) begin
+                FT601_DATA_OUT[data_queue_count - (FWD ? 3'b001 : 3'b000)] <= din;
+            end
+        end
+    end
+
+
+
+    // -------------------------------------------------------------------------
+    // FT245 main control below:
+    // -------------------------------------------------------------------------
+
+    always @ ( posedge clk )
+        begin
+            OE          <=  (rst || FT601_RXF_N || ((state != `S_FT601_RX_ACTIVE) && (state != `S_FT601_RX_WAIT3) && (state != `S_FT601_RX_WAIT2) && (state != `S_FT601_RX_COOLDOWN1) && (state != `S_FT601_RX_COOLDOWN2)));
+            FT601_OE_N  <=  (rst || FT601_RXF_N || ((state != `S_FT601_RX_ACTIVE) && (state != `S_FT601_RX_WAIT3) && (state != `S_FT601_RX_WAIT2)));
+            FT601_RD_N  <=  (rst || FT601_RXF_N || ((state != `S_FT601_RX_ACTIVE) && (state != `S_FT601_RX_WAIT3)));
+            FT601_WR_N  <=  !(!rst && !FT601_TXE_N && ((state == `S_FT601_TX_WAIT2) || ((state == `S_FT601_TX_ACTIVE) && (din_wr_en || (data_queue_count > 1)))));
+        end
+
+    always @ ( posedge clk )
+        if ( rst )
+            begin
+                state <= `S_FT601_IDLE;
+            end
+        else case ( state )
+            // ----------------------------------------------------------------
+            // IDLE STATE:
+            // RX are prioritized above TX in case both options are available. 
+            // ----------------------------------------------------------------
+            `S_FT601_IDLE:
+                if ( !FT601_RXF_N )
+                    state <= `S_FT601_RX_WAIT1;
+                else if ( !FT601_TXE_N && (data_queue_count > 0) )
+                    state <= `S_FT601_TX_WAIT1;
+            // ----------------------------------------------------------------
+            // RX DATA FROM THE FT601:
+            // The receiver FIFO is assumed to always be non-full.
+            // If receiver FIFO is full data will still be received but lost.
+            // ----------------------------------------------------------------
+            `S_FT601_RX_WAIT1:
+                state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_WAIT2;
+            `S_FT601_RX_WAIT2:
+                state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_WAIT3;
+            `S_FT601_RX_WAIT3:
+                state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_ACTIVE;
+            `S_FT601_RX_ACTIVE:
+                state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_ACTIVE;
+            `S_FT601_RX_COOLDOWN1:
+                state <= `S_FT601_RX_COOLDOWN2;
+            `S_FT601_RX_COOLDOWN2:
+                state <= `S_FT601_IDLE;
+            // ----------------------------------------------------------------
+            // TX DATA TO THE FT601:
+            // ----------------------------------------------------------------
+            `S_FT601_TX_WAIT1:
+                state <= FT601_TXE_N ? `S_FT601_TX_COOLDOWN1 : `S_FT601_TX_WAIT2;
+            `S_FT601_TX_WAIT2:
+                state <= FT601_TXE_N ? `S_FT601_TX_COOLDOWN1 : `S_FT601_TX_ACTIVE;
+            `S_FT601_TX_ACTIVE:
+                state <= (FT601_TXE_N || (!din_wr_en && (data_queue_count <= 1))) ? `S_FT601_TX_COOLDOWN1 : `S_FT601_TX_ACTIVE;
+            `S_FT601_TX_COOLDOWN1:
+                state <= `S_FT601_TX_COOLDOWN2;
+            `S_FT601_TX_COOLDOWN2:
+                state   <= `S_FT601_IDLE;
+        endcase
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_header.svh

@@ -0,0 +1,336 @@
+//
+// PCILeech FPGA.
+//
+// SystemVerilog Header File for PCILeech FPGA projects.
+//
+// (c) Ulf Frisk, 2019-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`ifndef _pcileech_header_svh_
+`define _pcileech_header_svh_
+
+`define _bs16(v)   {{v}[7:0], {v}[15:8]}
+`define _bs32(v)   {{v}[7:0], {v}[15:8], {v}[23:16], {v}[31:24]}
+
+// ------------------------------------------------------------------------
+// Interface connecting COM to FIFO module.
+// ------------------------------------------------------------------------
+interface IfComToFifo;
+    wire [63:0]     com_dout;
+    wire            com_dout_valid;
+    wire [255:0]    com_din;
+    wire            com_din_wr_en;
+    wire            com_din_ready;
+
+    modport mp_com (
+        output com_dout, com_dout_valid, com_din_ready,
+        input com_din, com_din_wr_en
+    );
+
+    modport mp_fifo (
+        input com_dout, com_dout_valid, com_din_ready,
+        output com_din, com_din_wr_en
+    );
+endinterface
+
+// ------------------------------------------------------------------------
+// Interface connecting PCIe to PCIe CFG module.
+// ------------------------------------------------------------------------
+interface IfPCIeSignals;
+    // ------------------------------------------------------------------------
+    // VALUES FROM PCIe TO module.
+    // ------------------------------------------------------------------------
+    wire    [7:0]       cfg_bus_number;
+    wire    [4:0]       cfg_device_number;
+    wire    [2:0]       cfg_function_number;
+    
+    wire    [15:0]      cfg_command;
+    wire    [31:0]      cfg_mgmt_do;
+    wire                cfg_mgmt_rd_wr_done;
+    
+    wire    [2:0]       pl_initial_link_width;
+    wire                pl_phy_lnk_up;
+    wire    [1:0]       pl_lane_reversal_mode;
+    wire                pl_link_gen2_cap;
+    wire                pl_link_partner_gen2_supported;
+    wire                pl_link_upcfg_cap;
+    wire                pl_sel_lnk_rate;
+    wire    [1:0]       pl_sel_lnk_width;
+    wire    [5:0]       pl_ltssm_state;
+    wire    [1:0]       pl_rx_pm_state;
+    wire    [2:0]       pl_tx_pm_state;
+    wire                pl_directed_change_done;
+    wire                pl_received_hot_rst;
+    
+    wire                cfg_aer_rooterr_corr_err_received;
+    wire                cfg_aer_rooterr_corr_err_reporting_en;
+    wire                cfg_aer_rooterr_fatal_err_received;
+    wire                cfg_aer_rooterr_fatal_err_reporting_en;
+    wire                cfg_aer_rooterr_non_fatal_err_received;
+    wire                cfg_aer_rooterr_non_fatal_err_reporting_en;
+    wire                cfg_bridge_serr_en;
+    wire    [15:0]      cfg_dcommand;
+    wire    [15:0]      cfg_dcommand2;
+    wire    [15:0]      cfg_dstatus;
+    wire    [15:0]      cfg_lcommand;
+    wire    [15:0]      cfg_lstatus;
+    wire    [2:0]       cfg_pcie_link_state;
+    wire                cfg_pmcsr_pme_en;
+    wire                cfg_pmcsr_pme_status;
+    wire    [1:0]       cfg_pmcsr_powerstate;
+    wire                cfg_received_func_lvl_rst;
+    wire                cfg_root_control_pme_int_en;
+    wire                cfg_root_control_syserr_corr_err_en;
+    wire                cfg_root_control_syserr_fatal_err_en;
+    wire                cfg_root_control_syserr_non_fatal_err_en;
+    wire                cfg_slot_control_electromech_il_ctl_pulse;
+    wire    [15:0]      cfg_status;
+    wire                cfg_to_turnoff;
+    wire    [5:0]       tx_buf_av;
+    wire                tx_cfg_req;
+    wire                tx_err_drop;
+    wire    [6:0]       cfg_vc_tcvc_map;
+    
+    wire    [2:0]       cfg_interrupt_mmenable;
+    wire                cfg_interrupt_msienable;
+    wire                cfg_interrupt_msixenable;
+    wire                cfg_interrupt_msixfm;
+    wire                cfg_interrupt_rdy;
+    wire    [7:0]       cfg_interrupt_do;
+    
+    // ------------------------------------------------------------------------
+    // VALUES FROM module TO PCIe.
+    // ------------------------------------------------------------------------
+    
+    wire                cfg_mgmt_rd_en;
+    wire                cfg_mgmt_wr_en;
+    
+    wire    [63:0]      cfg_dsn;
+    wire    [31:0]      cfg_mgmt_di;
+    wire    [9:0]       cfg_mgmt_dwaddr;
+    wire    [3:0]       cfg_mgmt_byte_en;
+    wire                cfg_mgmt_wr_readonly;
+    wire                cfg_mgmt_wr_rw1c_as_rw;
+    
+    wire    [1:0]       pl_directed_link_change;
+    wire    [1:0]       pl_directed_link_width;
+    wire                pl_directed_link_auton;
+    wire                pl_directed_link_speed;
+    wire                pl_upstream_prefer_deemph;
+    wire                pl_transmit_hot_rst;
+    wire                pl_downstream_deemph_source;
+    
+    wire    [7:0]       cfg_interrupt_di;
+    wire    [4:0]       cfg_pciecap_interrupt_msgnum;
+    wire                cfg_interrupt_assert;
+    wire                cfg_interrupt;
+    wire                cfg_interrupt_stat;
+    
+    wire    [1:0]       cfg_pm_force_state;
+    wire                cfg_pm_force_state_en;
+    wire                cfg_pm_halt_aspm_l0s;
+    wire                cfg_pm_halt_aspm_l1;
+    wire                cfg_pm_send_pme_to;
+    wire                cfg_pm_wake;
+    wire                cfg_trn_pending;
+    wire                cfg_turnoff_ok;
+    wire                rx_np_ok;
+    wire                rx_np_req;
+    wire                tx_cfg_gnt;
+    
+    modport mpm (
+        input cfg_bus_number, cfg_device_number, cfg_function_number, cfg_command, cfg_mgmt_do, cfg_mgmt_rd_wr_done,
+            pl_initial_link_width, pl_phy_lnk_up, pl_lane_reversal_mode, pl_link_gen2_cap, pl_link_partner_gen2_supported,
+            pl_link_upcfg_cap, pl_sel_lnk_rate, pl_sel_lnk_width, pl_ltssm_state, pl_rx_pm_state,
+            pl_tx_pm_state, pl_directed_change_done, pl_received_hot_rst,
+            cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_fatal_err_received, cfg_aer_rooterr_fatal_err_reporting_en,
+            cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_bridge_serr_en, cfg_dcommand, cfg_dcommand2, cfg_dstatus,
+            cfg_lcommand, cfg_lstatus, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_pme_status, cfg_pmcsr_powerstate, cfg_received_func_lvl_rst, cfg_root_control_pme_int_en,
+            cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_slot_control_electromech_il_ctl_pulse,
+            cfg_status, cfg_to_turnoff, tx_buf_av, tx_cfg_req, tx_err_drop, cfg_vc_tcvc_map,
+            cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_rdy, cfg_interrupt_do,
+            
+        output cfg_mgmt_rd_en, cfg_mgmt_wr_en, cfg_dsn, cfg_mgmt_di, cfg_mgmt_dwaddr, cfg_mgmt_wr_readonly, cfg_mgmt_wr_rw1c_as_rw, cfg_mgmt_byte_en, pl_directed_link_change, pl_directed_link_width, pl_directed_link_auton,
+            pl_directed_link_speed, pl_upstream_prefer_deemph, pl_transmit_hot_rst, pl_downstream_deemph_source,
+            cfg_interrupt_di, cfg_pciecap_interrupt_msgnum, cfg_interrupt_assert, cfg_interrupt, cfg_interrupt_stat, cfg_pm_force_state, cfg_pm_force_state_en, cfg_pm_halt_aspm_l0s,
+            cfg_pm_halt_aspm_l1, cfg_pm_send_pme_to, cfg_pm_wake, cfg_trn_pending, cfg_turnoff_ok, rx_np_ok, rx_np_req, tx_cfg_gnt
+    );
+endinterface
+
+// ------------------------------------------------------------------------
+// Interface PCIe 128-bit RX stream
+// ------------------------------------------------------------------------
+
+interface IfAXIS128;
+    wire [127:0]    tdata;
+    wire [3:0]      tkeepdw;
+    wire            tvalid;
+    wire            tlast;
+    wire [8:0]      tuser;      // [0] = first
+                                // [1] = last
+                                // [8:2] = BAR, 2=BAR0, 3=BAR1, .. 7=BAR5, 8=EXPROM
+    
+    wire            tready;
+    wire            has_data;
+    
+    modport source(
+        input  tready,
+        output tdata, tkeepdw, tvalid, tlast, tuser, has_data
+    );
+    
+    modport sink(
+        output tready,
+        input  tdata, tkeepdw, tvalid, tlast, tuser, has_data
+    );
+    
+    modport source_lite(
+        output tdata, tkeepdw, tvalid, tlast, tuser
+    );
+    
+    modport sink_lite(
+        input  tdata, tkeepdw, tvalid, tlast, tuser
+    );
+endinterface
+
+// ------------------------------------------------------------------------
+// Interface connecting PCIe CFG to FIFO
+// ------------------------------------------------------------------------
+interface IfPCIeFifoCfg;
+    wire    [63:0]      tx_data;
+    wire                tx_valid;
+    wire    [31:0]      rx_data;
+    wire                rx_valid;
+    wire                rx_rd_en;
+
+    modport mp_fifo (
+        output tx_data, tx_valid, rx_rd_en,
+        input rx_data, rx_valid
+    );
+
+    modport mp_pcie (
+        input tx_data, tx_valid, rx_rd_en,
+        output rx_data, rx_valid
+    );
+endinterface
+
+// ------------------------------------------------------------------------
+// Interface connecting PCIe TLP to FIFO
+// ------------------------------------------------------------------------
+interface IfPCIeFifoTlp;
+    wire    [31:0]      tx_data;
+    wire                tx_last;
+    wire                tx_valid;   
+    wire    [31:0]      rx_data[4];
+    wire                rx_first[4];
+    wire                rx_last[4];
+    wire                rx_valid[4];
+    wire                rx_rd_en;
+
+    modport mp_fifo (
+        output tx_data, tx_last, tx_valid, rx_rd_en,
+        input rx_data, rx_first, rx_last, rx_valid
+    );
+
+    modport mp_pcie (
+        input tx_data, tx_last, tx_valid, rx_rd_en,
+        output rx_data, rx_first, rx_last, rx_valid
+    );
+endinterface
+
+// ------------------------------------------------------------------------
+// Interface connecting PCIe CORE config to FIFO
+// ------------------------------------------------------------------------
+interface IfPCIeFifoCore;
+    // PCIe optional config
+    wire                pcie_rst_core;
+    wire                pcie_rst_subsys;
+    // DRP config
+    wire                drp_rdy;
+    wire    [15:0]      drp_do;
+    wire                drp_en;
+    wire                drp_we;
+    wire    [8:0]       drp_addr;
+    wire    [15:0]      drp_di;
+    
+    modport mp_fifo (
+        input drp_rdy, drp_do,
+        output pcie_rst_core, pcie_rst_subsys, drp_en, drp_we, drp_addr, drp_di
+    );
+
+    modport mp_pcie (
+        input pcie_rst_core, pcie_rst_subsys, drp_en, drp_we, drp_addr, drp_di,
+        output drp_rdy, drp_do
+    );
+endinterface
+
+interface IfShadow2Fifo;
+    // SHADOW CONFIGURATION SPACE TO FIFO
+    wire                rx_rden;
+    wire                rx_wren;
+    wire    [3:0]       rx_be;
+    wire    [31:0]      rx_data;
+    wire    [9:0]       rx_addr;
+    wire                rx_addr_lo;
+    wire                tx_valid;
+    wire    [31:0]      tx_data;
+    wire    [9:0]       tx_addr;
+    wire                tx_addr_lo;
+    wire                cfgtlp_wren;
+    wire                cfgtlp_zero;
+    wire                cfgtlp_en;
+    wire                cfgtlp_filter;
+    wire                alltlp_filter;
+    wire                bar_en;
+    
+    modport fifo (
+        output cfgtlp_wren, cfgtlp_zero, rx_rden, rx_wren, rx_be, rx_addr, rx_addr_lo, rx_data, cfgtlp_en, cfgtlp_filter, alltlp_filter, bar_en,
+        input tx_valid, tx_addr, tx_addr_lo, tx_data
+    );
+
+    modport shadow (
+        input cfgtlp_wren, cfgtlp_zero, rx_rden, rx_wren, rx_be, rx_addr, rx_addr_lo, rx_data, cfgtlp_en, cfgtlp_filter, alltlp_filter, bar_en,
+        output tx_valid, tx_addr, tx_addr_lo, tx_data
+    );
+endinterface
+
+// ------------------------------------------------------------------------
+// Interface PCIe AXI RX / TX
+// ------------------------------------------------------------------------
+interface IfPCIeTlpRxTx;
+    wire    [63:0]      data;
+    wire    [7:0]       keep;
+    wire                last;
+    wire    [21:0]      user;
+    wire                valid;
+    wire                ready;
+    
+    modport source (
+        output data, keep, last, user, valid,
+        input ready
+    );
+    
+    modport sink (
+        input data, keep, last, user, valid,
+        output ready
+    );
+endinterface
+
+interface IfPCIeTlpRx128;
+    wire    [127:0]     data;
+    wire    [21:0]      user;
+    wire                valid;
+    wire                ready;
+    
+    modport source (
+        output data, user, valid,
+        input ready
+    );
+    
+    modport sink (
+        input data, user, valid,
+        output ready
+    );
+endinterface
+
+`endif

JOKOSAHS_DMA-Pcileech/src/pcileech_mux.sv

@@ -0,0 +1,175 @@
+//
+// PCILeech FPGA.
+//
+// Merge multiple 32-bit words into a 256-bit word consisting of one (1) 32-bit
+// status word and seven (7) data words. This is done to enable relatively
+// efficient transmission over the FT601 together with some additional info.
+//
+// (c) Ulf Frisk, 2017-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+
+module pcileech_mux(
+    input                clk,
+    input                rst,
+    // output
+    output [255:0]       dout,
+    output               valid,
+    input                rd_en,
+    // port0: input highest priority
+    input  [31:0]        p0_din,
+    input  [1:0]         p0_tag,
+    input  [1:0]         p0_ctx,
+    input                p0_wr_en,
+    output               p0_req_data,
+    // port1:
+    input  [31:0]        p1_din,
+    input  [1:0]         p1_tag,
+    input  [1:0]         p1_ctx,
+    input                p1_wr_en,
+    output               p1_req_data,
+    // port2:
+    input  [31:0]        p2_din,
+    input  [1:0]         p2_tag,
+    input  [1:0]         p2_ctx,
+    input                p2_wr_en,
+    output               p2_req_data,
+    // port3:
+    input  [31:0]        p3_din,
+    input  [1:0]         p3_tag,
+    input  [1:0]         p3_ctx,
+    input                p3_wr_en,
+    output               p3_req_data,
+    // port4:
+    input  [31:0]        p4_din,
+    input  [1:0]         p4_tag,
+    input  [1:0]         p4_ctx,
+    input                p4_wr_en,
+    output               p4_req_data,
+    // port5:
+    input  [31:0]        p5_din,
+    input  [1:0]         p5_tag,
+    input  [1:0]         p5_ctx,
+    input                p5_wr_en,
+    output               p5_req_data,
+    // port6:
+    input  [31:0]        p6_din,
+    input  [1:0]         p6_tag,
+    input  [1:0]         p6_ctx,
+    input                p6_wr_en,
+    output               p6_req_data,
+    // port7:
+    input  [31:0]        p7_din,
+    input  [1:0]         p7_tag,
+    input  [1:0]         p7_ctx,
+    input                p7_wr_en,
+    output               p7_req_data
+    );
+
+    // 'en' is delayed 1CLK so it's in synch with inputs.
+    //      output integrity is handled by extra register.
+    reg en;
+    always @ ( posedge clk )
+        en <= rd_en && !rst;
+
+    assign p0_req_data = rd_en;
+    assign p1_req_data = rd_en;
+    assign p2_req_data = rd_en;
+    assign p3_req_data = rd_en;
+    assign p4_req_data = rd_en;
+    assign p5_req_data = rd_en;
+    assign p6_req_data = rd_en;
+    assign p7_req_data = rd_en;
+
+    reg [31:0]  data_reg[14];
+    reg [3:0]   ctx_reg[14];
+
+    wire        p8_wr_en;
+    reg [3:0]   idx_base;
+    wire [3:0]  p0_idx = idx_base;
+    wire [3:0]  p1_idx = p0_idx + p0_wr_en;
+    wire [3:0]  p2_idx = p1_idx + p1_wr_en;
+    wire [3:0]  p3_idx = p2_idx + p2_wr_en;
+    wire [3:0]  p4_idx = p3_idx + p3_wr_en;
+    wire [3:0]  p5_idx = p4_idx + p4_wr_en;
+    wire [3:0]  p6_idx = p5_idx + p5_wr_en;
+    wire [3:0]  p7_idx = p6_idx + p6_wr_en;
+    wire [3:0]  p8_idx = p7_idx + p7_wr_en;     // idle port
+    wire [3:0] idx_max = p8_idx + p8_wr_en;     // max index
+
+    // P8: INTERNAL "IDLE PORT"
+    reg [3:0]   idle_count;
+    wire [31:0] p8_din = 32'hffffffff;
+    wire [1:0]  p8_tag = 2'b11;
+    wire [1:0]  p8_ctx = 2'b11;
+    assign      p8_wr_en = en && (idx_base > 0) && (idle_count > 7) && (idx_base == p8_idx);
+    
+    
+    
+    // output buffer logic, when rd_en is deasserted the output data must be
+    // buffered not to cause data loss.
+    reg             dout_valid;
+    wire [255:0]    dout_data = { ctx_reg[1], ctx_reg[0], ctx_reg[3], ctx_reg[2], ctx_reg[5], ctx_reg[4], 4'hE, ctx_reg[6], data_reg[0], data_reg[1], data_reg[2], data_reg[3], data_reg[4], data_reg[5], data_reg[6] };
+    reg             dout_buf_valid;
+    reg [255:0]     dout_buf_data;
+    assign valid = rd_en && (dout_buf_valid || dout_valid);
+    assign dout = dout_buf_valid ? dout_buf_data : dout_data;
+    
+    
+    
+    always @ ( posedge clk ) begin
+        if( rst )
+            begin
+                idx_base <= 0;
+                idle_count <= 0;
+                dout_valid <= 0;
+                dout_buf_valid <= 0;
+            end
+        else
+            begin
+                // OUTPUT BUFFER LOGIC:
+                
+                if( en ) begin
+                    dout_buf_valid <= 0;
+                end else if( dout_valid ) begin
+                    dout_buf_data <= dout_data;
+                    dout_buf_valid <= 1;
+                end
+            
+                // OUTPUT VALID:
+                dout_valid <= en && (idx_max >= 7);
+                
+                if( en ) begin
+                    // NEXT INDEX BASE:
+                    idx_base <= idx_max - ((idx_max >= 7) ? 7 : 0);
+                    // IDLE COUNT:
+                    idle_count <= ((idx_base > 0) && (idx_base == p8_idx)) ? (idle_count + 1) : 0;
+                    // DATA/CTX writes into index [0-8]:
+                    if( p0_wr_en ) begin  data_reg[p0_idx] <= p0_din;  ctx_reg[p0_idx] <= {p0_ctx, p0_tag};  end
+                    if( p1_wr_en ) begin  data_reg[p1_idx] <= p1_din;  ctx_reg[p1_idx] <= {p1_ctx, p1_tag};  end
+                    if( p2_wr_en ) begin  data_reg[p2_idx] <= p2_din;  ctx_reg[p2_idx] <= {p2_ctx, p2_tag};  end
+                    if( p3_wr_en ) begin  data_reg[p3_idx] <= p3_din;  ctx_reg[p3_idx] <= {p3_ctx, p3_tag};  end
+                    if( p4_wr_en ) begin  data_reg[p4_idx] <= p4_din;  ctx_reg[p4_idx] <= {p4_ctx, p4_tag};  end
+                    if( p5_wr_en ) begin  data_reg[p5_idx] <= p5_din;  ctx_reg[p5_idx] <= {p5_ctx, p5_tag};  end
+                    if( p6_wr_en ) begin  data_reg[p6_idx] <= p6_din;  ctx_reg[p6_idx] <= {p6_ctx, p6_tag};  end
+                    if( p7_wr_en ) begin  data_reg[p7_idx] <= p7_din;  ctx_reg[p7_idx] <= {p7_ctx, p7_tag};  end
+                    if( p8_wr_en ) begin  data_reg[p8_idx] <= p8_din;  ctx_reg[p8_idx] <= {p8_ctx, p8_tag};  end
+                end
+                
+                if( dout_valid ) begin
+                    // DATA/CTX previous move:
+                    if( idx_base > 0) begin  data_reg[0] <= data_reg[7+0];  ctx_reg[0] <= ctx_reg[7+0];  end
+                    if( idx_base > 1) begin  data_reg[1] <= data_reg[7+1];  ctx_reg[1] <= ctx_reg[7+1];  end
+                    if( idx_base > 2) begin  data_reg[2] <= data_reg[7+2];  ctx_reg[2] <= ctx_reg[7+2];  end
+                    if( idx_base > 3) begin  data_reg[3] <= data_reg[7+3];  ctx_reg[3] <= ctx_reg[7+3];  end
+                    if( idx_base > 4) begin  data_reg[4] <= data_reg[7+4];  ctx_reg[4] <= ctx_reg[7+4];  end
+                    if( idx_base > 5) begin  data_reg[5] <= data_reg[7+5];  ctx_reg[5] <= ctx_reg[7+5];  end
+                    if( idx_base > 6) begin  data_reg[6] <= data_reg[7+6];  ctx_reg[6] <= ctx_reg[7+6];  end
+                end
+                
+
+            end
+    end
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_pcie_a7.sv

@@ -0,0 +1,353 @@
+//
+// PCILeech FPGA.
+//
+// PCIe module for Artix-7.
+//
+// (c) Ulf Frisk, 2018-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_pcie_a7(
+    input                   clk_sys,
+    input                   rst,
+
+    // PCIe fabric
+    output  [0:0]           pcie_tx_p,
+    output  [0:0]           pcie_tx_n,
+    input   [0:0]           pcie_rx_p,
+    input   [0:0]           pcie_rx_n,
+    input                   pcie_clk_p,
+    input                   pcie_clk_n,
+    input                   pcie_perst_n,
+    
+    // State and Activity LEDs
+    output                  led_state,
+    
+    // PCIe <--> FIFOs
+    IfPCIeFifoCfg.mp_pcie   dfifo_cfg,
+    IfPCIeFifoTlp.mp_pcie   dfifo_tlp,
+    IfPCIeFifoCore.mp_pcie  dfifo_pcie,
+    IfShadow2Fifo.shadow    dshadow2fifo
+    );
+       
+    // ----------------------------------------------------------------------------
+    // PCIe DEFINES AND WIRES
+    // ----------------------------------------------------------------------------
+    
+    IfPCIeSignals           ctx();
+    IfPCIeTlpRxTx           tlp_tx();
+    IfPCIeTlpRxTx           tlp_rx();
+    IfAXIS128               tlps_tx();
+    IfAXIS128               tlps_rx();
+    
+    IfAXIS128               tlps_static();       // static tlp transmit from cfg->tlp
+    wire [15:0]             pcie_id;
+    wire                    user_lnk_up;
+    
+    // system interface
+    wire pcie_clk_c;
+    wire clk_pcie;
+    wire rst_pcie_user;
+    wire rst_subsys = rst || rst_pcie_user || dfifo_pcie.pcie_rst_subsys;
+    wire rst_pcie = rst || ~pcie_perst_n || dfifo_pcie.pcie_rst_core;
+       
+    // Buffer for differential system clock
+    IBUFDS_GTE2 refclk_ibuf (.O(pcie_clk_c), .ODIV2(), .I(pcie_clk_p), .CEB(1'b0), .IB(pcie_clk_n));
+    
+    // ----------------------------------------------------
+    // TickCount64 PCIe REFCLK and LED OUTPUT
+    // ----------------------------------------------------
+
+    time tickcount64_pcie_refclk = 0;
+    always @ ( posedge pcie_clk_c )
+        tickcount64_pcie_refclk <= tickcount64_pcie_refclk + 1;
+    assign led_state = user_lnk_up || tickcount64_pcie_refclk[25];
+    
+    // ----------------------------------------------------------------------------
+    // PCIe CFG RX/TX <--> FIFO below
+    // ----------------------------------------------------------------------------
+    wire [31:0] base_address_register;
+    
+    pcileech_pcie_cfg_a7 i_pcileech_pcie_cfg_a7(
+        .rst                        ( rst_subsys                ),
+        .clk_sys                    ( clk_sys                   ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .dfifo                      ( dfifo_cfg                 ),        
+        .ctx                        ( ctx                       ),
+        .tlps_static                ( tlps_static.source        ),
+        .pcie_id                    ( pcie_id                   ),  // -> [15:0]
+        .base_address_register      ( base_address_register     )
+    );
+    
+    // ----------------------------------------------------------------------------
+    // PCIe TLP RX/TX <--> FIFO below
+    // ----------------------------------------------------------------------------
+    
+    pcileech_tlps128_src64 i_pcileech_tlps128_src64(
+        .rst                        ( rst_subsys                ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .tlp_rx                     ( tlp_rx.sink               ),
+        .tlps_out                   ( tlps_rx.source_lite       )
+    );
+    
+    pcileech_pcie_tlp_a7 i_pcileech_pcie_tlp_a7(
+        .rst                        ( rst_subsys                ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .clk_sys                    ( clk_sys                   ),
+        .dfifo                      ( dfifo_tlp                 ),
+        .tlps_tx                    ( tlps_tx.source            ),       
+        .tlps_rx                    ( tlps_rx.sink_lite         ),
+        .tlps_static                ( tlps_static.sink          ),
+        .dshadow2fifo               ( dshadow2fifo              ),
+        .pcie_id                    ( pcie_id                   ),  // <- [15:0]
+        .base_address_register      ( base_address_register     )
+    );
+    
+    pcileech_tlps128_dst64 i_pcileech_tlps128_dst64(
+        .rst                        ( rst                       ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .tlp_tx                     ( tlp_tx.source             ),
+        .tlps_in                    ( tlps_tx.sink              )
+    );
+    
+    // ----------------------------------------------------------------------------
+    // PCIe CORE BELOW
+    // ---------------------------------------------------------------------------- 
+      
+    pcie_7x_0 i_pcie_7x_0 (
+        // pcie_7x_mgt
+        .pci_exp_txp                ( pcie_tx_p                 ),  // ->
+        .pci_exp_txn                ( pcie_tx_n                 ),  // ->
+        .pci_exp_rxp                ( pcie_rx_p                 ),  // <-
+        .pci_exp_rxn                ( pcie_rx_n                 ),  // <-
+        .sys_clk                    ( pcie_clk_c                ),  // <-
+        .sys_rst_n                  ( ~rst_pcie                 ),  // <-
+    
+        // s_axis_tx (transmit data)
+        .s_axis_tx_tdata            ( tlp_tx.data               ),  // <- [63:0]
+        .s_axis_tx_tkeep            ( tlp_tx.keep               ),  // <- [7:0]
+        .s_axis_tx_tlast            ( tlp_tx.last               ),  // <-
+        .s_axis_tx_tready           ( tlp_tx.ready              ),  // ->
+        .s_axis_tx_tuser            ( 4'b0                      ),  // <- [3:0]
+        .s_axis_tx_tvalid           ( tlp_tx.valid              ),  // <-
+    
+        // s_axis_rx (receive data)
+        .m_axis_rx_tdata            ( tlp_rx.data               ),  // -> [63:0]
+        .m_axis_rx_tkeep            ( tlp_rx.keep               ),  // -> [7:0]
+        .m_axis_rx_tlast            ( tlp_rx.last               ),  // -> 
+        .m_axis_rx_tready           ( tlp_rx.ready              ),  // <-
+        .m_axis_rx_tuser            ( tlp_rx.user               ),  // -> [21:0]
+        .m_axis_rx_tvalid           ( tlp_rx.valid              ),  // ->
+    
+        // pcie_cfg_mgmt
+        .cfg_mgmt_dwaddr            ( ctx.cfg_mgmt_dwaddr       ),  // <- [9:0]
+        .cfg_mgmt_byte_en           ( ctx.cfg_mgmt_byte_en      ),  // <- [3:0]
+        .cfg_mgmt_do                ( ctx.cfg_mgmt_do           ),  // -> [31:0]
+        .cfg_mgmt_rd_en             ( ctx.cfg_mgmt_rd_en        ),  // <-
+        .cfg_mgmt_rd_wr_done        ( ctx.cfg_mgmt_rd_wr_done   ),  // ->
+        .cfg_mgmt_wr_readonly       ( ctx.cfg_mgmt_wr_readonly  ),  // <-
+        .cfg_mgmt_wr_rw1c_as_rw     ( ctx.cfg_mgmt_wr_rw1c_as_rw ), // <-
+        .cfg_mgmt_di                ( ctx.cfg_mgmt_di           ),  // <- [31:0]
+        .cfg_mgmt_wr_en             ( ctx.cfg_mgmt_wr_en        ),  // <-
+    
+        // special core config
+        //.pcie_cfg_vend_id           ( dfifo_pcie.pcie_cfg_vend_id       ),  // <- [15:0]
+        //.pcie_cfg_dev_id            ( dfifo_pcie.pcie_cfg_dev_id        ),  // <- [15:0]
+        //.pcie_cfg_rev_id            ( dfifo_pcie.pcie_cfg_rev_id        ),  // <- [7:0]
+        //.pcie_cfg_subsys_vend_id    ( dfifo_pcie.pcie_cfg_subsys_vend_id ), // <- [15:0]
+        //.pcie_cfg_subsys_id         ( dfifo_pcie.pcie_cfg_subsys_id     ),  // <- [15:0]
+    
+        // pcie2_cfg_interrupt
+        .cfg_interrupt_assert       ( ctx.cfg_interrupt_assert          ),  // <-
+        .cfg_interrupt              ( ctx.cfg_interrupt                 ),  // <-
+        .cfg_interrupt_mmenable     ( ctx.cfg_interrupt_mmenable        ),  // -> [2:0]
+        .cfg_interrupt_msienable    ( ctx.cfg_interrupt_msienable       ),  // ->
+        .cfg_interrupt_msixenable   ( ctx.cfg_interrupt_msixenable      ),  // ->
+        .cfg_interrupt_msixfm       ( ctx.cfg_interrupt_msixfm          ),  // ->
+        .cfg_pciecap_interrupt_msgnum ( ctx.cfg_pciecap_interrupt_msgnum ), // <- [4:0]
+        .cfg_interrupt_rdy          ( ctx.cfg_interrupt_rdy             ),  // ->
+        .cfg_interrupt_do           ( ctx.cfg_interrupt_do              ),  // -> [7:0]
+        .cfg_interrupt_stat         ( ctx.cfg_interrupt_stat            ),  // <-
+        .cfg_interrupt_di           ( ctx.cfg_interrupt_di              ),  // <- [7:0]
+        
+        // pcie2_cfg_control
+        .cfg_ds_bus_number          ( ctx.cfg_bus_number                ),  // <- [7:0]
+        .cfg_ds_device_number       ( ctx.cfg_device_number             ),  // <- [4:0]
+        .cfg_ds_function_number     ( ctx.cfg_function_number           ),  // <- [2:0]
+        .cfg_dsn                    ( ctx.cfg_dsn                       ),  // <- [63:0]
+        .cfg_pm_force_state         ( ctx.cfg_pm_force_state            ),  // <- [1:0]
+        .cfg_pm_force_state_en      ( ctx.cfg_pm_force_state_en         ),  // <-
+        .cfg_pm_halt_aspm_l0s       ( ctx.cfg_pm_halt_aspm_l0s          ),  // <-
+        .cfg_pm_halt_aspm_l1        ( ctx.cfg_pm_halt_aspm_l1           ),  // <-
+        .cfg_pm_send_pme_to         ( ctx.cfg_pm_send_pme_to            ),  // <-
+        .cfg_pm_wake                ( ctx.cfg_pm_wake                   ),  // <-
+        .rx_np_ok                   ( ctx.rx_np_ok                      ),  // <-
+        .rx_np_req                  ( ctx.rx_np_req                     ),  // <-
+        .cfg_trn_pending            ( ctx.cfg_trn_pending               ),  // <-
+        .cfg_turnoff_ok             ( ctx.cfg_turnoff_ok                ),  // <-
+        .tx_cfg_gnt                 ( ctx.tx_cfg_gnt                    ),  // <-
+        
+        // pcie2_cfg_status
+        .cfg_command                ( ctx.cfg_command                   ),  // -> [15:0]
+        .cfg_bus_number             ( ctx.cfg_bus_number                ),  // -> [7:0]
+        .cfg_device_number          ( ctx.cfg_device_number             ),  // -> [4:0]
+        .cfg_function_number        ( ctx.cfg_function_number           ),  // -> [2:0]
+        .cfg_root_control_pme_int_en( ctx.cfg_root_control_pme_int_en   ),  // ->
+        .cfg_bridge_serr_en         ( ctx.cfg_bridge_serr_en            ),  // ->
+        .cfg_dcommand               ( ctx.cfg_dcommand                  ),  // -> [15:0]
+        .cfg_dcommand2              ( ctx.cfg_dcommand2                 ),  // -> [15:0]
+        .cfg_dstatus                ( ctx.cfg_dstatus                   ),  // -> [15:0]
+        .cfg_lcommand               ( ctx.cfg_lcommand                  ),  // -> [15:0]
+        .cfg_lstatus                ( ctx.cfg_lstatus                   ),  // -> [15:0]
+        .cfg_pcie_link_state        ( ctx.cfg_pcie_link_state           ),  // -> [2:0]
+        .cfg_pmcsr_pme_en           ( ctx.cfg_pmcsr_pme_en              ),  // ->
+        .cfg_pmcsr_pme_status       ( ctx.cfg_pmcsr_pme_status          ),  // ->
+        .cfg_pmcsr_powerstate       ( ctx.cfg_pmcsr_powerstate          ),  // -> [1:0]
+        .cfg_received_func_lvl_rst  ( ctx.cfg_received_func_lvl_rst     ),  // ->
+        .cfg_status                 ( ctx.cfg_status                    ),  // -> [15:0]
+        .cfg_to_turnoff             ( ctx.cfg_to_turnoff                ),  // ->
+        .tx_buf_av                  ( ctx.tx_buf_av                     ),  // -> [5:0]
+        .tx_cfg_req                 ( ctx.tx_cfg_req                    ),  // ->
+        .tx_err_drop                ( ctx.tx_err_drop                   ),  // ->
+        .cfg_vc_tcvc_map            ( ctx.cfg_vc_tcvc_map               ),  // -> [6:0]
+        .cfg_aer_rooterr_corr_err_received          ( ctx.cfg_aer_rooterr_corr_err_received             ),  // ->
+        .cfg_aer_rooterr_corr_err_reporting_en      ( ctx.cfg_aer_rooterr_corr_err_reporting_en         ),  // ->
+        .cfg_aer_rooterr_fatal_err_received         ( ctx.cfg_aer_rooterr_fatal_err_received            ),  // ->
+        .cfg_aer_rooterr_fatal_err_reporting_en     ( ctx.cfg_aer_rooterr_fatal_err_reporting_en        ),  // ->
+        .cfg_aer_rooterr_non_fatal_err_received     ( ctx.cfg_aer_rooterr_non_fatal_err_received        ),  // ->
+        .cfg_aer_rooterr_non_fatal_err_reporting_en ( ctx.cfg_aer_rooterr_non_fatal_err_reporting_en    ),  // ->
+        .cfg_root_control_syserr_corr_err_en        ( ctx.cfg_root_control_syserr_corr_err_en           ),  // ->
+        .cfg_root_control_syserr_fatal_err_en       ( ctx.cfg_root_control_syserr_fatal_err_en          ),  // ->
+        .cfg_root_control_syserr_non_fatal_err_en   ( ctx.cfg_root_control_syserr_non_fatal_err_en      ),  // ->
+        .cfg_slot_control_electromech_il_ctl_pulse  ( ctx.cfg_slot_control_electromech_il_ctl_pulse     ),  // ->
+        
+        // PCIe core PHY
+        .pl_initial_link_width      ( ctx.pl_initial_link_width         ),  // -> [2:0]
+        .pl_phy_lnk_up              ( ctx.pl_phy_lnk_up                 ),  // ->
+        .pl_lane_reversal_mode      ( ctx.pl_lane_reversal_mode         ),  // -> [1:0]
+        .pl_link_gen2_cap           ( ctx.pl_link_gen2_cap              ),  // ->
+        .pl_link_partner_gen2_supported ( ctx.pl_link_partner_gen2_supported ),  // ->
+        .pl_link_upcfg_cap          ( ctx.pl_link_upcfg_cap             ),  // ->
+        .pl_sel_lnk_rate            ( ctx.pl_sel_lnk_rate               ),  // ->
+        .pl_sel_lnk_width           ( ctx.pl_sel_lnk_width              ),  // -> [1:0]
+        .pl_ltssm_state             ( ctx.pl_ltssm_state                ),  // -> [5:0]
+        .pl_rx_pm_state             ( ctx.pl_rx_pm_state                ),  // -> [1:0]
+        .pl_tx_pm_state             ( ctx.pl_tx_pm_state                ),  // -> [2:0]
+        .pl_directed_change_done    ( ctx.pl_directed_change_done       ),  // ->
+        .pl_received_hot_rst        ( ctx.pl_received_hot_rst           ),  // ->
+        .pl_directed_link_auton     ( ctx.pl_directed_link_auton        ),  // <-
+        .pl_directed_link_change    ( ctx.pl_directed_link_change       ),  // <- [1:0]
+        .pl_directed_link_speed     ( ctx.pl_directed_link_speed        ),  // <-
+        .pl_directed_link_width     ( ctx.pl_directed_link_width        ),  // <- [1:0]
+        .pl_upstream_prefer_deemph  ( ctx.pl_upstream_prefer_deemph     ),  // <-
+        .pl_transmit_hot_rst        ( ctx.pl_transmit_hot_rst           ),  // <-
+        .pl_downstream_deemph_source( ctx.pl_downstream_deemph_source   ),  // <-
+        
+        // DRP - clock domain clk_100 - write should only happen when core is in reset state ...
+        .pcie_drp_clk               ( clk_sys                           ),  // <-
+        .pcie_drp_en                ( dfifo_pcie.drp_en                 ),  // <-
+        .pcie_drp_we                ( dfifo_pcie.drp_we                 ),  // <-
+        .pcie_drp_addr              ( dfifo_pcie.drp_addr               ),  // <- [8:0]
+        .pcie_drp_di                ( dfifo_pcie.drp_di                 ),  // <- [15:0]
+        .pcie_drp_rdy               ( dfifo_pcie.drp_rdy                ),  // ->
+        .pcie_drp_do                ( dfifo_pcie.drp_do                 ),  // -> [15:0]
+    
+        // user interface
+        .user_clk_out               ( clk_pcie                          ),  // ->
+        .user_reset_out             ( rst_pcie_user                     ),  // ->
+        .user_lnk_up                ( user_lnk_up                       ),  // ->
+        .user_app_rdy               (                                   )   // ->
+    );
+
+endmodule
+
+
+// ------------------------------------------------------------------------
+// TLP STREAM SINK:
+// Convert a 128-bit TLP-AXI-STREAM to a 64-bit PCIe core AXI-STREAM.
+// ------------------------------------------------------------------------
+module pcileech_tlps128_dst64(
+    input                   rst,
+    input                   clk_pcie,
+    IfPCIeTlpRxTx.source    tlp_tx,
+    IfAXIS128.sink          tlps_in
+);
+
+    bit [63:0]  d1_tdata;
+    bit         d1_tkeepdw2;
+    bit         d1_tlast;
+    bit         d1_tvalid = 0;
+    
+    assign tlps_in.tready = tlp_tx.ready && !(tlps_in.tvalid && tlps_in.tkeepdw[2]);
+    
+    wire tkeepdw2       = d1_tvalid ? d1_tkeepdw2 : tlps_in.tkeepdw[1];
+    assign tlp_tx.data  = d1_tvalid ? d1_tdata : tlps_in.tdata[63:0];
+    assign tlp_tx.last  = d1_tvalid ? d1_tlast : (tlps_in.tlast && !tlps_in.tkeepdw[2]);
+    assign tlp_tx.keep  = tkeepdw2 ? 8'hff : 8'h0f;
+    assign tlp_tx.valid = d1_tvalid || tlps_in.tvalid;
+    
+    always @ ( posedge clk_pcie ) begin
+        d1_tvalid    <= !rst && tlps_in.tvalid && tlps_in.tkeepdw[2];
+        d1_tdata     <= tlps_in.tdata[127:64];
+        d1_tlast     <= tlps_in.tlast;
+        d1_tkeepdw2  <= tlps_in.tkeepdw[3];
+    end
+
+endmodule
+
+
+// ------------------------------------------------------------------------
+// TLP STREAM SOURCE:
+// Convert a 64-bit PCIe core AXIS to a 128-bit TLP-AXI-STREAM 
+// ------------------------------------------------------------------------
+module pcileech_tlps128_src64(
+    input                   rst,
+    input                   clk_pcie,
+    IfPCIeTlpRxTx.sink      tlp_rx,
+    IfAXIS128.source_lite   tlps_out
+);
+
+    bit [127:0] tdata;
+    bit         first       = 1;
+    bit         tlast       = 0;
+    bit [3:0]   len         = 0;
+    bit [6:0]   bar_hit     = 0;
+    wire        tvalid      = tlast || (len>2);
+    
+    assign tlp_rx.ready     = 1'b1;
+    assign tlps_out.tdata   = tdata;
+    assign tlps_out.tkeepdw = {(len>3), (len>2), (len>1), 1'b1};
+    assign tlps_out.tlast   = tlast;   
+    assign tlps_out.tvalid  = tvalid; 
+    assign tlps_out.tuser[0]    = first;
+    assign tlps_out.tuser[1]    = tlast;
+    assign tlps_out.tuser[8:2]  = bar_hit;
+    
+    wire [3:0]  next_base   = (tlast || tvalid) ? 0 : len;
+    wire [3:0]  next_len    = next_base + 1 + tlp_rx.keep[4];
+
+    always @ ( posedge clk_pcie )
+        if ( rst ) begin
+            first   <= 1;
+            tlast   <= 0;
+            len     <= 0;
+            bar_hit <= 0;
+        end
+        else if ( tlp_rx.valid ) begin
+            tdata[(32*next_base)+:64] <= tlp_rx.data;
+            first   <= tvalid ? tlast : first;
+            tlast   <= tlp_rx.last;
+            len     <= next_len;
+            bar_hit <= tlp_rx.user[8:2];
+        end
+        else if ( tvalid ) begin 
+            first   <= tlast;
+            tlast   <= 0;
+            len     <= 0;
+            bar_hit <= 0;
+        end
+    
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_pcie_a7x4.sv

@@ -0,0 +1,374 @@
+//
+// PCILeech FPGA.
+//
+// PCIe module for Artix-7.
+//
+// (c) Ulf Frisk, 2018-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_pcie_a7x4(
+    input                   clk_sys,
+    input                   rst,
+
+    // PCIe fabric
+    output  [3:0]           pcie_tx_p,
+    output  [3:0]           pcie_tx_n,
+    input   [3:0]           pcie_rx_p,
+    input   [3:0]           pcie_rx_n,
+    input                   pcie_clk_p,
+    input                   pcie_clk_n,
+    input                   pcie_perst_n,
+    
+    // State and Activity LEDs
+    output                  led_state,
+    
+    // PCIe <--> FIFOs
+    IfPCIeFifoCfg.mp_pcie   dfifo_cfg,
+    IfPCIeFifoTlp.mp_pcie   dfifo_tlp,
+    IfPCIeFifoCore.mp_pcie  dfifo_pcie,
+    IfShadow2Fifo.shadow    dshadow2fifo
+    );
+       
+    // ----------------------------------------------------------------------------
+    // PCIe DEFINES AND WIRES
+    // ----------------------------------------------------------------------------
+    
+    IfPCIeSignals           ctx();
+    IfAXIS128               tlp_tx();
+    IfPCIeTlpRx128          tlp_rx();
+    IfAXIS128               tlps_tx();
+    IfAXIS128               tlps_rx();
+    
+    IfAXIS128               tlps_static();       // static tlp transmit from cfg->tlp
+    wire [15:0]             pcie_id;
+    wire                    user_lnk_up;
+    
+    // system interface
+    wire pcie_clk_c;
+    wire clk_pcie;
+    wire rst_pcie_user;
+    wire rst_subsys = rst || rst_pcie_user || dfifo_pcie.pcie_rst_subsys;
+    wire rst_pcie = rst || ~pcie_perst_n || dfifo_pcie.pcie_rst_core;
+       
+    // Buffer for differential system clock
+    IBUFDS_GTE2 refclk_ibuf (.O(pcie_clk_c), .ODIV2(), .I(pcie_clk_p), .CEB(1'b0), .IB(pcie_clk_n));
+    
+    // ----------------------------------------------------
+    // TickCount64 PCIe REFCLK and LED OUTPUT
+    // ----------------------------------------------------
+
+    time tickcount64_pcie_refclk = 0;
+    always @ ( posedge pcie_clk_c )
+        tickcount64_pcie_refclk <= tickcount64_pcie_refclk + 1;
+    assign led_state = user_lnk_up || tickcount64_pcie_refclk[25];
+    
+    // ----------------------------------------------------------------------------
+    // PCIe CFG RX/TX <--> FIFO below
+    // ----------------------------------------------------------------------------
+    wire [31:0] base_address_register;
+    pcileech_pcie_cfg_a7 i_pcileech_pcie_cfg_a7(
+        .rst                        ( rst_subsys                ),
+        .clk_sys                    ( clk_sys                   ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .dfifo                      ( dfifo_cfg                 ),        
+        .ctx                        ( ctx                       ),
+        .tlps_static                ( tlps_static.source        ),
+        .pcie_id                    ( pcie_id                   ),   // -> [15:0]
+        .base_address_register      ( base_address_register     )
+    );
+    
+    // ----------------------------------------------------------------------------
+    // PCIe TLP RX/TX <--> FIFO below
+    // ----------------------------------------------------------------------------
+    
+    pcileech_tlps128_src128 i_pcileech_tlps128_src128(
+        .rst                        ( rst_subsys                ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .tlp_rx                     ( tlp_rx.sink               ),
+        .tlps_out                   ( tlps_rx.source_lite       )
+    );
+    
+    pcileech_pcie_tlp_a7 i_pcileech_pcie_tlp_a7(
+        .rst                        ( rst_subsys                ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .clk_sys                    ( clk_sys                   ),
+        .dfifo                      ( dfifo_tlp                 ),
+        .tlps_tx                    ( tlps_tx.source            ),
+        .tlps_rx                    ( tlps_rx.sink_lite         ),
+        .tlps_static                ( tlps_static.sink          ),
+        .dshadow2fifo               ( dshadow2fifo              ),
+        .pcie_id                    ( pcie_id                   ),   // <- [15:0]
+        .base_address_register      ( base_address_register     )
+    );
+    
+    pcileech_tlps128_dst128 i_pcileech_tlps128_dst128(
+        .rst                        ( rst_subsys                ),
+        .clk_pcie                   ( clk_pcie                  ),
+        .tlps_in                    ( tlps_tx.sink              ),
+        .tlps_out                   ( tlp_tx.source             )
+    );
+    
+    wire [15:0] tlp_tx_tkeep;
+    assign tlp_tx_tkeep[3:0]   = tlp_tx.tkeepdw[0] ? 4'hf : 4'h0;
+    assign tlp_tx_tkeep[7:4]   = tlp_tx.tkeepdw[1] ? 4'hf : 4'h0;
+    assign tlp_tx_tkeep[11:8]  = tlp_tx.tkeepdw[2] ? 4'hf : 4'h0;
+    assign tlp_tx_tkeep[15:12] = tlp_tx.tkeepdw[3] ? 4'hf : 4'h0;
+    
+    // ----------------------------------------------------------------------------
+    // PCIe CORE BELOW
+    // ----------------------------------------------------------------------------
+      
+    pcie_7x_0 i_pcie_7x_0 (
+        // pcie_7x_mgt
+        .pci_exp_txp                ( pcie_tx_p                 ),  // ->
+        .pci_exp_txn                ( pcie_tx_n                 ),  // ->
+        .pci_exp_rxp                ( pcie_rx_p                 ),  // <-
+        .pci_exp_rxn                ( pcie_rx_n                 ),  // <-
+        .sys_clk                    ( pcie_clk_c                ),  // <-
+        .sys_rst_n                  ( ~rst_pcie                 ),  // <-
+
+        // s_axis_tx (transmit data) - 128-bit AXIS
+        .s_axis_tx_tdata            ( tlp_tx.tdata              ),  // <- [127:0]
+        .s_axis_tx_tkeep            ( tlp_tx_tkeep              ),  // <- [15:0]
+        .s_axis_tx_tlast            ( tlp_tx.tlast              ),  // <-
+        .s_axis_tx_tready           ( tlp_tx.tready             ),  // ->
+        .s_axis_tx_tuser            ( 4'b0000                   ),  // <- [3:0]
+        .s_axis_tx_tvalid           ( tlp_tx.tvalid             ),  // <-
+        // s_axis_rx (receive data) - 128-bit AXIS
+        .m_axis_rx_tdata            ( tlp_rx.data               ),  // -> [127:0]
+        .m_axis_rx_tkeep            (                           ),  // -> [15:0]
+        .m_axis_rx_tlast            (                           ),  // -> 
+        .m_axis_rx_tready           ( tlp_rx.ready              ),  // <-
+        .m_axis_rx_tuser            ( tlp_rx.user               ),  // -> [21:0]
+        .m_axis_rx_tvalid           ( tlp_rx.valid              ),  // ->
+    
+        // pcie_cfg_mgmt
+        .cfg_mgmt_dwaddr            ( ctx.cfg_mgmt_dwaddr       ),  // <- [9:0]
+        .cfg_mgmt_byte_en           ( ctx.cfg_mgmt_byte_en      ),  // <- [3:0]
+        .cfg_mgmt_do                ( ctx.cfg_mgmt_do           ),  // -> [31:0]
+        .cfg_mgmt_rd_en             ( ctx.cfg_mgmt_rd_en        ),  // <-
+        .cfg_mgmt_rd_wr_done        ( ctx.cfg_mgmt_rd_wr_done   ),  // ->
+        .cfg_mgmt_wr_readonly       ( ctx.cfg_mgmt_wr_readonly  ),  // <-
+        .cfg_mgmt_wr_rw1c_as_rw     ( ctx.cfg_mgmt_wr_rw1c_as_rw ), // <-
+        .cfg_mgmt_di                ( ctx.cfg_mgmt_di           ),  // <- [31:0]
+        .cfg_mgmt_wr_en             ( ctx.cfg_mgmt_wr_en        ),  // <-
+    
+        // special core config
+        //.pcie_cfg_vend_id           ( dfifo_pcie.pcie_cfg_vend_id       ),  // <- [15:0]
+        //.pcie_cfg_dev_id            ( dfifo_pcie.pcie_cfg_dev_id        ),  // <- [15:0]
+        //.pcie_cfg_rev_id            ( dfifo_pcie.pcie_cfg_rev_id        ),  // <- [7:0]
+        //.pcie_cfg_subsys_vend_id    ( dfifo_pcie.pcie_cfg_subsys_vend_id ), // <- [15:0]
+        //.pcie_cfg_subsys_id         ( dfifo_pcie.pcie_cfg_subsys_id     ),  // <- [15:0]
+    
+        // pcie2_cfg_interrupt
+        .cfg_interrupt_assert       ( ctx.cfg_interrupt_assert          ),  // <-
+        .cfg_interrupt              ( ctx.cfg_interrupt                 ),  // <-
+        .cfg_interrupt_mmenable     ( ctx.cfg_interrupt_mmenable        ),  // -> [2:0]
+        .cfg_interrupt_msienable    ( ctx.cfg_interrupt_msienable       ),  // ->
+        .cfg_interrupt_msixenable   ( ctx.cfg_interrupt_msixenable      ),  // ->
+        .cfg_interrupt_msixfm       ( ctx.cfg_interrupt_msixfm          ),  // ->
+        .cfg_pciecap_interrupt_msgnum ( ctx.cfg_pciecap_interrupt_msgnum ), // <- [4:0]
+        .cfg_interrupt_rdy          ( ctx.cfg_interrupt_rdy             ),  // ->
+        .cfg_interrupt_do           ( ctx.cfg_interrupt_do              ),  // -> [7:0]
+        .cfg_interrupt_stat         ( ctx.cfg_interrupt_stat            ),  // <-
+        .cfg_interrupt_di           ( ctx.cfg_interrupt_di              ),  // <- [7:0]
+        
+        // pcie2_cfg_control
+        .cfg_ds_bus_number          ( ctx.cfg_bus_number                ),  // <- [7:0]
+        .cfg_ds_device_number       ( ctx.cfg_device_number             ),  // <- [4:0]
+        .cfg_ds_function_number     ( ctx.cfg_function_number           ),  // <- [2:0]
+        .cfg_dsn                    ( ctx.cfg_dsn                       ),  // <- [63:0]
+        .cfg_pm_force_state         ( ctx.cfg_pm_force_state            ),  // <- [1:0]
+        .cfg_pm_force_state_en      ( ctx.cfg_pm_force_state_en         ),  // <-
+        .cfg_pm_halt_aspm_l0s       ( ctx.cfg_pm_halt_aspm_l0s          ),  // <-
+        .cfg_pm_halt_aspm_l1        ( ctx.cfg_pm_halt_aspm_l1           ),  // <-
+        .cfg_pm_send_pme_to         ( ctx.cfg_pm_send_pme_to            ),  // <-
+        .cfg_pm_wake                ( ctx.cfg_pm_wake                   ),  // <-
+        .rx_np_ok                   ( ctx.rx_np_ok                      ),  // <-
+        .rx_np_req                  ( ctx.rx_np_req                     ),  // <-
+        .cfg_trn_pending            ( ctx.cfg_trn_pending               ),  // <-
+        .cfg_turnoff_ok             ( ctx.cfg_turnoff_ok                ),  // <-
+        .tx_cfg_gnt                 ( ctx.tx_cfg_gnt                    ),  // <-
+        
+        // pcie2_cfg_status
+        .cfg_command                ( ctx.cfg_command                   ),  // -> [15:0]
+        .cfg_bus_number             ( ctx.cfg_bus_number                ),  // -> [7:0]
+        .cfg_device_number          ( ctx.cfg_device_number             ),  // -> [4:0]
+        .cfg_function_number        ( ctx.cfg_function_number           ),  // -> [2:0]
+        .cfg_root_control_pme_int_en( ctx.cfg_root_control_pme_int_en   ),  // ->
+        .cfg_bridge_serr_en         ( ctx.cfg_bridge_serr_en            ),  // ->
+        .cfg_dcommand               ( ctx.cfg_dcommand                  ),  // -> [15:0]
+        .cfg_dcommand2              ( ctx.cfg_dcommand2                 ),  // -> [15:0]
+        .cfg_dstatus                ( ctx.cfg_dstatus                   ),  // -> [15:0]
+        .cfg_lcommand               ( ctx.cfg_lcommand                  ),  // -> [15:0]
+        .cfg_lstatus                ( ctx.cfg_lstatus                   ),  // -> [15:0]
+        .cfg_pcie_link_state        ( ctx.cfg_pcie_link_state           ),  // -> [2:0]
+        .cfg_pmcsr_pme_en           ( ctx.cfg_pmcsr_pme_en              ),  // ->
+        .cfg_pmcsr_pme_status       ( ctx.cfg_pmcsr_pme_status          ),  // ->
+        .cfg_pmcsr_powerstate       ( ctx.cfg_pmcsr_powerstate          ),  // -> [1:0]
+        .cfg_received_func_lvl_rst  ( ctx.cfg_received_func_lvl_rst     ),  // ->
+        .cfg_status                 ( ctx.cfg_status                    ),  // -> [15:0]
+        .cfg_to_turnoff             ( ctx.cfg_to_turnoff                ),  // ->
+        .tx_buf_av                  ( ctx.tx_buf_av                     ),  // -> [5:0]
+        .tx_cfg_req                 ( ctx.tx_cfg_req                    ),  // ->
+        .tx_err_drop                ( ctx.tx_err_drop                   ),  // ->
+        .cfg_vc_tcvc_map            ( ctx.cfg_vc_tcvc_map               ),  // -> [6:0]
+        .cfg_aer_rooterr_corr_err_received          ( ctx.cfg_aer_rooterr_corr_err_received             ),  // ->
+        .cfg_aer_rooterr_corr_err_reporting_en      ( ctx.cfg_aer_rooterr_corr_err_reporting_en         ),  // ->
+        .cfg_aer_rooterr_fatal_err_received         ( ctx.cfg_aer_rooterr_fatal_err_received            ),  // ->
+        .cfg_aer_rooterr_fatal_err_reporting_en     ( ctx.cfg_aer_rooterr_fatal_err_reporting_en        ),  // ->
+        .cfg_aer_rooterr_non_fatal_err_received     ( ctx.cfg_aer_rooterr_non_fatal_err_received        ),  // ->
+        .cfg_aer_rooterr_non_fatal_err_reporting_en ( ctx.cfg_aer_rooterr_non_fatal_err_reporting_en    ),  // ->
+        .cfg_root_control_syserr_corr_err_en        ( ctx.cfg_root_control_syserr_corr_err_en           ),  // ->
+        .cfg_root_control_syserr_fatal_err_en       ( ctx.cfg_root_control_syserr_fatal_err_en          ),  // ->
+        .cfg_root_control_syserr_non_fatal_err_en   ( ctx.cfg_root_control_syserr_non_fatal_err_en      ),  // ->
+        .cfg_slot_control_electromech_il_ctl_pulse  ( ctx.cfg_slot_control_electromech_il_ctl_pulse     ),  // ->
+        
+        // PCIe core PHY
+        .pl_initial_link_width      ( ctx.pl_initial_link_width         ),  // -> [2:0]
+        .pl_phy_lnk_up              ( ctx.pl_phy_lnk_up                 ),  // ->
+        .pl_lane_reversal_mode      ( ctx.pl_lane_reversal_mode         ),  // -> [1:0]
+        .pl_link_gen2_cap           ( ctx.pl_link_gen2_cap              ),  // ->
+        .pl_link_partner_gen2_supported ( ctx.pl_link_partner_gen2_supported ),  // ->
+        .pl_link_upcfg_cap          ( ctx.pl_link_upcfg_cap             ),  // ->
+        .pl_sel_lnk_rate            ( ctx.pl_sel_lnk_rate               ),  // ->
+        .pl_sel_lnk_width           ( ctx.pl_sel_lnk_width              ),  // -> [1:0]
+        .pl_ltssm_state             ( ctx.pl_ltssm_state                ),  // -> [5:0]
+        .pl_rx_pm_state             ( ctx.pl_rx_pm_state                ),  // -> [1:0]
+        .pl_tx_pm_state             ( ctx.pl_tx_pm_state                ),  // -> [2:0]
+        .pl_directed_change_done    ( ctx.pl_directed_change_done       ),  // ->
+        .pl_received_hot_rst        ( ctx.pl_received_hot_rst           ),  // ->
+        .pl_directed_link_auton     ( ctx.pl_directed_link_auton        ),  // <-
+        .pl_directed_link_change    ( ctx.pl_directed_link_change       ),  // <- [1:0]
+        .pl_directed_link_speed     ( ctx.pl_directed_link_speed        ),  // <-
+        .pl_directed_link_width     ( ctx.pl_directed_link_width        ),  // <- [1:0]
+        .pl_upstream_prefer_deemph  ( ctx.pl_upstream_prefer_deemph     ),  // <-
+        .pl_transmit_hot_rst        ( ctx.pl_transmit_hot_rst           ),  // <-
+        .pl_downstream_deemph_source( ctx.pl_downstream_deemph_source   ),  // <-
+        
+        // DRP - clock domain clk - write should only happen when core is in reset state ...
+        .pcie_drp_clk               ( clk_sys                           ),  // <-
+        .pcie_drp_en                ( dfifo_pcie.drp_en                 ),  // <-
+        .pcie_drp_we                ( dfifo_pcie.drp_we                 ),  // <-
+        .pcie_drp_addr              ( dfifo_pcie.drp_addr               ),  // <- [8:0]
+        .pcie_drp_di                ( dfifo_pcie.drp_di                 ),  // <- [15:0]
+        .pcie_drp_rdy               ( dfifo_pcie.drp_rdy                ),  // ->
+        .pcie_drp_do                ( dfifo_pcie.drp_do                 ),  // -> [15:0]
+    
+        // user interface
+        .user_clk_out               ( clk_pcie                          ),  // ->
+        .user_reset_out             ( rst_pcie_user                     ),  // ->
+        .user_lnk_up                ( user_lnk_up                       ),  // ->
+        .user_app_rdy               (                                   )   // ->
+    );
+
+endmodule
+
+// ------------------------------------------------------------------------
+// TLP STREAM SINK:
+// Convert a 128-bit TLP-AXI-STREAM to a 128-bit PCIe core AXI-STREAM.
+// ------------------------------------------------------------------------
+module pcileech_tlps128_dst128(
+    input                   rst,
+    input                   clk_pcie,
+    IfAXIS128.source        tlps_out,
+    IfAXIS128.sink          tlps_in
+);
+
+    bit [127:0] d_tdata;
+    bit [3:0]   d_tkeepdw;
+    bit         d_tlast;
+    bit         d_tvalid;    
+    always @ ( posedge clk_pcie ) begin
+        if ( rst ) begin
+            d_tvalid    <= 0;
+        end
+        else if ( tlps_in.tvalid ) begin
+            d_tdata     <= tlps_in.tdata;
+            d_tkeepdw   <= tlps_in.tkeepdw;
+            d_tlast     <= tlps_in.tlast;
+            d_tvalid    <= !tlps_out.tready;
+        end
+        else if ( tlps_out.tready ) begin
+            d_tvalid    <= 0;
+        end
+    end
+    
+    assign tlps_in.tready   = tlps_out.tready && !d_tvalid;
+    assign tlps_out.tdata   = d_tvalid ? d_tdata    : tlps_in.tdata;
+    assign tlps_out.tkeepdw = d_tvalid ? d_tkeepdw  : tlps_in.tkeepdw;
+    assign tlps_out.tlast   = d_tvalid ? d_tlast    : tlps_in.tlast;
+    assign tlps_out.tvalid  = d_tvalid || tlps_in.tvalid;
+    
+endmodule
+
+// ------------------------------------------------------------------------
+// TLP STREAM SOURCE:
+// Convert a 128-bit PCIe core AXIS to a 128-bit TLP-AXI-STREAM 
+// ------------------------------------------------------------------------
+module pcileech_tlps128_src128(
+    input                   rst,
+    input                   clk_pcie,
+    IfPCIeTlpRx128.sink     tlp_rx,
+    IfAXIS128.source_lite   tlps_out
+);
+    
+    bit             rxd_ready;
+    wire [127:0]    rxf_data    = tlp_rx.data;
+    wire [21:0]     rxf_user    = tlp_rx.user;
+    wire            rxf_valid   = tlp_rx.valid && rxd_ready;
+    wire            rxf_ready;
+    assign          tlp_rx.ready = rxf_ready;
+    
+    bit             rxd_sof;
+    bit             rxd_eof;
+    bit             rxd_eof_dw;
+    bit [6:0]       rxd_bar_hit;
+    bit [63:0]      rxd_data_qw;
+    bit             rxd_valid;
+    
+    wire [63:0]     rxf_data_qw0    = rxf_data[63:0];
+    wire [63:0]     rxf_data_qw1    = rxf_data[127:64];
+    wire            rxf_sof         = rxf_user[14];
+    wire            rxf_sof_qw      = rxf_user[13];
+    wire            rxf_eof         = rxf_user[21];
+    wire [1:0]      rxf_eof_dw      = rxf_user[20:19];
+    wire [6:0]      rxf_bar_hit     = rxf_user[8:2];
+    
+    wire [3:0]      rx_keep_dw; 
+    
+    assign rxf_ready = !(rxd_valid && rxf_eof && (rxf_eof_dw >= 2)) || !rxf_valid;
+    
+    assign tlps_out.tdata       = rxd_valid ? {rxf_data_qw0, rxd_data_qw} : {rxf_data_qw1, rxf_data_qw0};
+    assign tlps_out.tuser[0]    = rxd_valid ? rxd_sof : (rxf_sof && !rxf_sof_qw);                       // tfirst
+    assign tlps_out.tuser[1]    = rxd_valid ? (rxd_eof || (rxf_eof && (rxf_eof_dw <= 1))) : rxf_eof;    // tlast
+    assign tlps_out.tuser[8:2]  = rxd_valid ? rxd_bar_hit : rxf_bar_hit;
+    assign tlps_out.tlast       = tlps_out.tuser[1];
+    assign tlps_out.tvalid      = rxd_valid || (rxf_valid && rxf_eof) || (rxf_valid && !(rxf_sof && rxf_sof_qw)); 
+    
+    assign tlps_out.tkeepdw[0]  = rxd_valid || rxf_valid;
+    assign tlps_out.tkeepdw[1]  = rxd_valid ? (!rxd_eof || rxd_eof_dw) :
+                                              (!rxf_eof || (rxf_eof_dw >= 1));
+    assign tlps_out.tkeepdw[2]  = rxd_valid ? (!rxd_eof && rxf_valid) :
+                                              (!rxf_eof || (rxf_eof_dw >= 2));
+    assign tlps_out.tkeepdw[3]  = rxd_valid ? (!rxd_eof && rxf_valid && (!rxf_eof || (rxf_eof_dw >= 1))) :
+                                              (!rxf_eof || (rxf_eof_dw >= 3));
+                                              
+    wire rxf_rxd_valid_next = !rst && rxf_valid && (rxd_valid ? ((!rxf_sof && !rxf_eof) || (rxf_sof && rxf_sof_qw) || (rxf_eof && (rxf_eof_dw >= 2))) :
+                                                                (rxf_sof && rxf_sof_qw));
+    
+    always @ ( posedge clk_pcie ) begin
+        rxd_ready   <= rxf_ready;
+        rxd_bar_hit <= rxf_bar_hit;
+        rxd_data_qw <= rxf_data_qw1;
+        rxd_sof     <= rxf_sof && rxf_sof_qw;
+        rxd_eof     <= rxf_eof && (rxf_eof_dw >= 2);
+        rxd_eof_dw  <= (rxf_eof_dw == 3);
+        rxd_valid   <= rxf_rxd_valid_next;
+    end
+    
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_pcie_cfg_a7.sv

@@ -0,0 +1,447 @@
+//
+// PCILeech FPGA.
+//
+// PCIe configuration module - CFG handling for Artix-7.
+//
+// (c) Ulf Frisk, 2018-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_pcie_cfg_a7(
+    input                   rst,
+    input                   clk_sys,
+    input                   clk_pcie,
+    IfPCIeFifoCfg.mp_pcie   dfifo,
+    IfPCIeSignals.mpm       ctx,
+    IfAXIS128.source        tlps_static,
+    output [15:0]           pcie_id,
+    output wire [31:0]      base_address_register
+    );
+
+    // ----------------------------------------------------
+    // TickCount64
+    // ----------------------------------------------------
+    
+    time tickcount64 = 0;
+    always @ ( posedge clk_pcie )
+        tickcount64 <= tickcount64 + 1;
+    
+    // ----------------------------------------------------------------------------
+    // Convert received CFG data from FT601 to PCIe clock domain
+    // FIFO depth: 512 / 64-bits
+    // ----------------------------------------------------------------------------
+    reg             in_rden;
+    wire [63:0]     in_dout;
+    wire            in_empty;
+    wire            in_valid;
+    
+    reg [63:0]      in_data64;
+    wire [31:0]     in_data32   = in_data64[63:32];
+    wire [15:0]     in_data16   = in_data64[31:16];
+    wire [3:0]      in_type     = in_data64[15:12];
+	
+    fifo_64_64 i_fifo_pcie_cfg_tx(
+        .rst            ( rst                   ),
+        .wr_clk         ( clk_sys               ),
+        .rd_clk         ( clk_pcie              ),
+        .din            ( dfifo.tx_data         ),
+        .wr_en          ( dfifo.tx_valid        ),
+        .rd_en          ( in_rden               ),
+        .dout           ( in_dout               ),
+        .full           (                       ),
+        .empty          ( in_empty              ),
+        .valid          ( in_valid              )
+    );
+    
+    // ------------------------------------------------------------------------
+    // Convert received CFG from PCIe core and transmit onwards to FT601
+    // FIFO depth: 512 / 64-bits.
+    // ------------------------------------------------------------------------
+    reg             out_wren;
+    reg [31:0]      out_data;
+    wire            pcie_cfg_rx_almost_full;
+    
+    fifo_32_32_clk2 i_fifo_pcie_cfg_rx(
+        .rst            ( rst                   ),
+        .wr_clk         ( clk_pcie              ),
+        .rd_clk         ( clk_sys               ),
+        .din            ( out_data              ),
+        .wr_en          ( out_wren              ),
+        .rd_en          ( dfifo.rx_rd_en        ),
+        .dout           ( dfifo.rx_data         ),
+        .full           (                       ),
+        .almost_full    ( pcie_cfg_rx_almost_full ),
+        .empty          (                       ),
+        .valid          ( dfifo.rx_valid        )
+    );
+    
+    // ------------------------------------------------------------------------
+    // REGISTER FILE: COMMON
+    // ------------------------------------------------------------------------
+    
+    wire    [383:0]     ro;
+    reg     [703:0]     rw;
+    
+    // special non-user accessible registers 
+    reg                 rwi_cfg_mgmt_rd_en;
+    reg                 rwi_cfg_mgmt_wr_en;
+    reg                 rwi_cfgrd_valid;
+    reg     [9:0]       rwi_cfgrd_addr;
+    reg     [3:0]       rwi_cfgrd_byte_en;
+    reg     [31:0]      rwi_cfgrd_data;
+    reg                 rwi_tlp_static_valid;
+    reg                 rwi_tlp_static_2nd;
+    reg                 rwi_tlp_static_has_data;
+    reg     [31:0]      rwi_count_cfgspace_status_cl;
+    bit     [31:0]      base_address_register_reg;
+   
+    // ------------------------------------------------------------------------
+    // REGISTER FILE: READ-ONLY LAYOUT/SPECIFICATION
+    // ------------------------------------------------------------------------
+     
+    // MAGIC
+    assign base_address_register = base_address_register_reg;
+    assign ro[15:0]     = 16'h2301;                     // +000: MAGIC
+    // SPECIAL
+    assign ro[16]       = ctx.cfg_mgmt_rd_en;           // +002: SPECIAL
+    assign ro[17]       = ctx.cfg_mgmt_wr_en;           //
+    assign ro[31:18]    = 0;                            //
+    // SIZEOF / BYTECOUNT [little-endian]
+    assign ro[63:32]    = $bits(ro) >> 3;               // +004: BYTECOUNT
+    // PCIe CFG STATUS
+    assign ro[71:64]    = ctx.cfg_bus_number;           // +008:
+    assign ro[76:72]    = ctx.cfg_device_number;        //
+    assign ro[79:77]    = ctx.cfg_function_number;      //
+    // PCIe PL PHY
+    assign ro[85:80]    = ctx.pl_ltssm_state;           // +00A
+    assign ro[87:86]    = ctx.pl_rx_pm_state;           //
+    assign ro[90:88]    = ctx.pl_tx_pm_state;           // +00B
+    assign ro[93:91]    = ctx.pl_initial_link_width;    //
+    assign ro[95:94]    = ctx.pl_lane_reversal_mode;    //
+    assign ro[97:96]    = ctx.pl_sel_lnk_width;         // +00C
+    assign ro[98]       = ctx.pl_phy_lnk_up;            //
+    assign ro[99]       = ctx.pl_link_gen2_cap;         //
+    assign ro[100]      = ctx.pl_link_partner_gen2_supported; //
+    assign ro[101]      = ctx.pl_link_upcfg_cap;        //
+    assign ro[102]      = ctx.pl_sel_lnk_rate;          //
+    assign ro[103]      = ctx.pl_directed_change_done;  // +00D:
+    assign ro[104]      = ctx.pl_received_hot_rst;      //
+    assign ro[126:105]  = 0;                            //       SLACK
+    assign ro[127]      = ctx.cfg_mgmt_rd_wr_done;      //
+    // PCIe CFG MGMT
+    assign ro[159:128]  = ctx.cfg_mgmt_do;              // +010:
+    // PCIe CFG STATUS
+    assign ro[175:160]  = ctx.cfg_command;              // +014:
+    assign ro[176]      = ctx.cfg_aer_rooterr_corr_err_received;            // +016:
+    assign ro[177]      = ctx.cfg_aer_rooterr_corr_err_reporting_en;        //
+    assign ro[178]      = ctx.cfg_aer_rooterr_fatal_err_received;           //
+    assign ro[179]      = ctx.cfg_aer_rooterr_fatal_err_reporting_en;       //
+    assign ro[180]      = ctx.cfg_aer_rooterr_non_fatal_err_received;       //
+    assign ro[181]      = ctx.cfg_aer_rooterr_non_fatal_err_reporting_en;   //
+    assign ro[182]      = ctx.cfg_bridge_serr_en;                           //
+    assign ro[183]      = ctx.cfg_received_func_lvl_rst;                    //
+    assign ro[186:184]  = ctx.cfg_pcie_link_state;      // +017:
+    assign ro[187]      = ctx.cfg_pmcsr_pme_en;         //
+    assign ro[189:188]  = ctx.cfg_pmcsr_powerstate;     //
+    assign ro[190]      = ctx.cfg_pmcsr_pme_status;     //
+    assign ro[191]      = 0;                            //       SLACK
+    assign ro[207:192]  = ctx.cfg_dcommand;             // +018:
+    assign ro[223:208]  = ctx.cfg_dcommand2;            // +01A:
+    assign ro[239:224]  = ctx.cfg_dstatus;              // +01C:
+    assign ro[255:240]  = ctx.cfg_lcommand;             // +01E:
+    assign ro[271:256]  = ctx.cfg_lstatus;              // +020:
+    assign ro[287:272]  = ctx.cfg_status;               // +022:
+    assign ro[293:288]  = ctx.tx_buf_av;                // +024:
+    assign ro[294]      = ctx.tx_cfg_req;               //
+    assign ro[295]      = ctx.tx_err_drop;              //
+    assign ro[302:296]  = ctx.cfg_vc_tcvc_map;          // +025:
+    assign ro[303]      = 0;                            //       SLACK
+    assign ro[304]      = ctx.cfg_root_control_pme_int_en;              // +026:
+    assign ro[305]      = ctx.cfg_root_control_syserr_corr_err_en;      //
+    assign ro[306]      = ctx.cfg_root_control_syserr_fatal_err_en;     //
+    assign ro[307]      = ctx.cfg_root_control_syserr_non_fatal_err_en; //
+    assign ro[308]      = ctx.cfg_slot_control_electromech_il_ctl_pulse;//
+    assign ro[309]      = ctx.cfg_to_turnoff;                           //
+    assign ro[319:310]  = 0;                                            //       SLACK
+    // PCIe INTERRUPT
+    assign ro[327:320]  = ctx.cfg_interrupt_do;         // +028:
+    assign ro[330:328]  = ctx.cfg_interrupt_mmenable;   // +029:
+    assign ro[331]      = ctx.cfg_interrupt_msienable;  //
+    assign ro[332]      = ctx.cfg_interrupt_msixenable; //
+    assign ro[333]      = ctx.cfg_interrupt_msixfm;     //
+    assign ro[334]      = ctx.cfg_interrupt_rdy;        //
+    assign ro[335]      = 0;                            //       SLACK
+    // CFG SPACE READ RESULT
+    assign ro[345:336]  = rwi_cfgrd_addr;               // +02A:
+    assign ro[346]      = 0;                            //       SLACK
+    assign ro[347]      = rwi_cfgrd_valid;              //
+    assign ro[351:348]  = rwi_cfgrd_byte_en;            //
+    assign ro[383:352]  = rwi_cfgrd_data;               // +02C:
+    // 0030 - 
+    
+    
+    // ------------------------------------------------------------------------
+    // INITIALIZATION/RESET BLOCK _AND_
+    // REGISTER FILE: READ-WRITE LAYOUT/SPECIFICATION
+    // ------------------------------------------------------------------------
+    
+    localparam integer  RWPOS_CFG_RD_EN                 = 16;
+    localparam integer  RWPOS_CFG_WR_EN                 = 17;
+    localparam integer  RWPOS_CFG_WAIT_COMPLETE         = 18;
+    localparam integer  RWPOS_CFG_STATIC_TLP_TX_EN      = 19;
+    localparam integer  RWPOS_CFG_CFGSPACE_STATUS_CL_EN = 20;
+    localparam integer  RWPOS_CFG_CFGSPACE_COMMAND_EN   = 21;
+    
+    task pcileech_pcie_cfg_a7_initialvalues;        // task is non automatic
+        begin
+            out_wren <= 1'b0;
+            
+            rwi_cfg_mgmt_rd_en <= 1'b0;
+            rwi_cfg_mgmt_wr_en <= 1'b0;
+            base_address_register_reg <= 32'h00000000;
+    
+            // MAGIC
+            rw[15:0]    <= 16'h6745;                // +000:
+            // SPECIAL START TASK BLOCK (write 1 to start action)
+            rw[16]      <= 0;                       // +002: CFG RD EN
+            rw[17]      <= 0;                       //       CFG WR EN
+            rw[18]      <= 0;                       //       WAIT FOR PCIe CFG SPACE RD/WR COMPLETION BEFORE ACCEPT NEW FIFO READ/WRITES
+            rw[19]      <= 0;                       //       TLP_STATIC TX ENABLE
+            rw[20]      <= 0;                       //       CFGSPACE_STATUS_REGISTER_AUTO_CLEAR [master abort flag]
+            rw[21]      <= 0;                       //       CFGSPACE_COMMAND_REGISTER_AUTO_SET [bus master and other flags (set in rw[143:128] <= 16'h....;)]
+            rw[31:22]   <= 0;                       //       RESERVED FUTURE
+            // SIZEOF / BYTECOUNT [little-endian]
+            rw[63:32]   <= $bits(rw) >> 3;          // +004: bytecount [little endian]
+            // DSN
+            rw[127:64]  <= 64'h0000000000000000;    // +008: cfg_dsn
+            // PCIe CFG MGMT
+            rw[159:128] <= 0;                       // +010: cfg_mgmt_di
+            rw[169:160] <= 0;                       // +014: cfg_mgmt_dwaddr
+            rw[170]     <= 0;                       //       cfg_mgmt_wr_readonly
+            rw[171]     <= 0;                       //       cfg_mgmt_wr_rw1c_as_rw
+            rw[175:172] <= 4'hf;                    //       cfg_mgmt_byte_en
+            // PCIe PL PHY
+            rw[176]     <= 0;                       // +016: pl_directed_link_auton
+            rw[178:177] <= 0;                       //       pl_directed_link_change
+            rw[179]     <= 1;                       //       pl_directed_link_speed 
+            rw[181:180] <= 0;                       //       pl_directed_link_width            
+            rw[182]     <= 1;                       //       pl_upstream_prefer_deemph
+            rw[183]     <= 0;                       //       pl_transmit_hot_rst
+            rw[184]     <= 0;                       // +017: pl_downstream_deemph_source
+            rw[191:185] <= 0;                       //       SLACK  
+            // PCIe INTERRUPT
+            rw[199:192] <= 0;                       // +018: cfg_interrupt_di
+            rw[204:200] <= 0;                       // +019: cfg_pciecap_interrupt_msgnum
+            rw[205]     <= 0;                       //       cfg_interrupt_assert
+            rw[206]     <= 0;                       //       cfg_interrupt
+            rw[207]     <= 0;                       //       cfg_interrupt_stat
+            // PCIe CTRL
+            rw[209:208] <= 0;                       // +01A: cfg_pm_force_state
+            rw[210]     <= 0;                       //       cfg_pm_force_state_en
+            rw[211]     <= 0;                       //       cfg_pm_halt_aspm_l0s
+            rw[212]     <= 0;                       //       cfg_pm_halt_aspm_l1
+            rw[213]     <= 0;                       //       cfg_pm_send_pme_to
+            rw[214]     <= 0;                       //       cfg_pm_wake
+            rw[215]     <= 0;                       //       cfg_trn_pending
+            rw[216]     <= 0;                       // +01B: cfg_turnoff_ok
+            rw[217]     <= 1;                       //       rx_np_ok
+            rw[218]     <= 1;                       //       rx_np_req
+            rw[219]     <= 1;                       //       tx_cfg_gnt
+            rw[223:220] <= 0;                       //       SLACK 
+            // PCIe STATIC TLP TRANSMIT
+            rw[224+:8]  <= 0;                       // +01C: TLP_STATIC TLP DWORD VALID [each-2bit: [0] = last, [1] = valid] [TLP DWORD 0-3]
+            rw[232+:8]  <= 0;                       // +01D: TLP_STATIC TLP DWORD VALID [each-2bit: [0] = last, [1] = valid] [TLP DWORD 4-7]
+            rw[240+:16] <= 0;                       // +01E: TLP_STATIC TLP TX SLEEP (ticks) [little-endian]
+            rw[256+:384] <= 0;                      // +020: TLP_STATIC TLP [8*32-bit hdr+data]
+            rw[640+:32] <= 0;                       // +050: TLP_STATIC TLP RETRANSMIT COUNT
+            // PCIe STATUS register clear timer
+            rw[672+:32] <= 62500;                   // +054: CFGSPACE_STATUS_CLEAR TIMER (ticks) [little-endian] [default = 1ms - 62.5k @ 62.5MHz]
+            
+        end
+    endtask
+    
+    assign ctx.cfg_mgmt_rd_en               = rwi_cfg_mgmt_rd_en & ~ctx.cfg_mgmt_rd_wr_done;
+    assign ctx.cfg_mgmt_wr_en               = rwi_cfg_mgmt_wr_en & ~ctx.cfg_mgmt_rd_wr_done;
+    
+    assign ctx.cfg_dsn                      = rw[127:64];
+    assign ctx.cfg_mgmt_di                  = rw[159:128];
+    assign ctx.cfg_mgmt_dwaddr              = rw[169:160];
+    assign ctx.cfg_mgmt_wr_readonly         = rw[170];
+    assign ctx.cfg_mgmt_wr_rw1c_as_rw       = rw[171];
+    assign ctx.cfg_mgmt_byte_en             = rw[175:172];
+    
+    assign ctx.pl_directed_link_auton       = rw[176];
+    assign ctx.pl_directed_link_change      = rw[178:177];
+    assign ctx.pl_directed_link_speed       = rw[179];
+    assign ctx.pl_directed_link_width       = rw[181:180];
+    assign ctx.pl_upstream_prefer_deemph    = rw[182];
+    assign ctx.pl_transmit_hot_rst          = rw[183];
+    assign ctx.pl_downstream_deemph_source  = rw[184];
+    
+    assign ctx.cfg_interrupt_di             = rw[199:192];
+    assign ctx.cfg_pciecap_interrupt_msgnum = rw[204:200];
+    assign ctx.cfg_interrupt_assert         = rw[205];
+    assign ctx.cfg_interrupt                = rw[206];
+    assign ctx.cfg_interrupt_stat           = rw[207];
+
+    assign ctx.cfg_pm_force_state           = rw[209:208];
+    assign ctx.cfg_pm_force_state_en        = rw[210];
+    assign ctx.cfg_pm_halt_aspm_l0s         = rw[211];
+    assign ctx.cfg_pm_halt_aspm_l1          = rw[212];
+    assign ctx.cfg_pm_send_pme_to           = rw[213];
+    assign ctx.cfg_pm_wake                  = rw[214];
+    assign ctx.cfg_trn_pending              = rw[215];
+    assign ctx.cfg_turnoff_ok               = rw[216];
+    assign ctx.rx_np_ok                     = rw[217];
+    assign ctx.rx_np_req                    = rw[218];
+    assign ctx.tx_cfg_gnt                   = rw[219];
+    
+    assign tlps_static.tdata[127:0]         = rwi_tlp_static_2nd ? {
+        rw[(256+32*7+00)+:8], rw[(256+32*7+08)+:8], rw[(256+32*7+16)+:8], rw[(256+32*7+24)+:8],   // STATIC TLP DWORD7
+        rw[(256+32*6+00)+:8], rw[(256+32*6+08)+:8], rw[(256+32*6+16)+:8], rw[(256+32*6+24)+:8],   // STATIC TLP DWORD6
+        rw[(256+32*5+00)+:8], rw[(256+32*5+08)+:8], rw[(256+32*5+16)+:8], rw[(256+32*5+24)+:8],   // STATIC TLP DWORD5
+        rw[(256+32*4+00)+:8], rw[(256+32*4+08)+:8], rw[(256+32*4+16)+:8], rw[(256+32*4+24)+:8]    // STATIC TLP DWORD4
+    } : {
+        rw[(256+32*3+00)+:8], rw[(256+32*3+08)+:8], rw[(256+32*3+16)+:8], rw[(256+32*3+24)+:8],   // STATIC TLP DWORD3
+        rw[(256+32*2+00)+:8], rw[(256+32*2+08)+:8], rw[(256+32*2+16)+:8], rw[(256+32*2+24)+:8],   // STATIC TLP DWORD2
+        rw[(256+32*1+00)+:8], rw[(256+32*1+08)+:8], rw[(256+32*1+16)+:8], rw[(256+32*1+24)+:8],   // STATIC TLP DWORD1
+        rw[(256+32*0+00)+:8], rw[(256+32*0+08)+:8], rw[(256+32*0+16)+:8], rw[(256+32*0+24)+:8]    // STATIC TLP DWORD0
+    };
+    assign tlps_static.tkeepdw              = rwi_tlp_static_2nd ? { rw[224+2*7], rw[224+2*6], rw[224+2*5], rw[224+2*4] } : { rw[224+2*3], rw[224+2*2], rw[224+2*1], rw[224+2*0] };
+    assign tlps_static.tlast                = rwi_tlp_static_2nd || rw[224+2*3+1] || rw[224+2*2+1] || rw[224+2*1+1] || rw[224+2*0+1];
+    assign tlps_static.tuser[0]             = !rwi_tlp_static_2nd;
+    assign tlps_static.tvalid               = rwi_tlp_static_valid && tlps_static.tkeepdw[0];
+    assign tlps_static.has_data             = rwi_tlp_static_has_data;
+        
+    assign pcie_id                          = ro[79:64];
+    
+    // ------------------------------------------------------------------------
+    // STATE MACHINE / LOGIC FOR READ/WRITE AND OTHER HOUSEKEEPING TASKS
+    // ------------------------------------------------------------------------
+    
+    integer i_write, i_tlpstatic;
+    wire [15:0] in_cmd_address_byte = in_dout[31:16];
+    wire [17:0] in_cmd_address_bit  = {in_cmd_address_byte[14:0], 3'b000};
+    wire [15:0] in_cmd_value        = {in_dout[48+:8], in_dout[56+:8]};
+    wire [15:0] in_cmd_mask         = {in_dout[32+:8], in_dout[40+:8]};
+    wire        f_rw                = in_cmd_address_byte[15]; 
+    wire [15:0] in_cmd_data_in      = (in_cmd_address_bit < (f_rw ? $bits(rw) : $bits(ro))) ? (f_rw ? rw[in_cmd_address_bit+:16] : ro[in_cmd_address_bit+:16]) : 16'h0000;
+    wire        in_cmd_read         = in_dout[12] & in_valid;
+    wire        in_cmd_write        = in_dout[13] & in_cmd_address_byte[15] & in_valid;
+    wire        pcie_cfg_rw_en      = rwi_cfg_mgmt_rd_en | rwi_cfg_mgmt_wr_en | rw[RWPOS_CFG_RD_EN] | rw[RWPOS_CFG_WR_EN];
+    // in_rden = request data from incoming fifo. Only do this if there is space
+    // in the output fifo and every 2nd clock cycle (in case a resulting write
+    // starts an action that will last longer than a single clock there must be
+    // time to react and stop reading incoming read/writes until processed).
+    assign in_rden = tickcount64[1] & ~pcie_cfg_rx_almost_full & ( ~rw[RWPOS_CFG_WAIT_COMPLETE] | ~pcie_cfg_rw_en);
+    
+    initial pcileech_pcie_cfg_a7_initialvalues();
+    
+    always @ ( posedge clk_pcie )
+        if ( rst )
+            pcileech_pcie_cfg_a7_initialvalues();
+        else
+            begin
+                // READ config
+                out_wren <= in_cmd_read;
+                if ( in_cmd_read )
+                    begin
+                        out_data[31:16] <= in_cmd_address_byte;
+                        out_data[15:0]  <= {in_cmd_data_in[7:0], in_cmd_data_in[15:8]};
+                    end
+
+                // WRITE config
+                if ( in_cmd_write )
+                    for ( i_write = 0; i_write < 16; i_write = i_write + 1 )
+                        begin
+                            if ( in_cmd_mask[i_write] )
+                                rw[in_cmd_address_bit+i_write] <= in_cmd_value[i_write];
+                        end
+
+                // STATUS REGISTER CLEAR
+                if ( (rw[RWPOS_CFG_CFGSPACE_STATUS_CL_EN] | rw[RWPOS_CFG_CFGSPACE_COMMAND_EN]) & ~in_cmd_read & ~in_cmd_write & ~rw[RWPOS_CFG_RD_EN] & ~rw[RWPOS_CFG_WR_EN] & ~rwi_cfg_mgmt_rd_en & ~rwi_cfg_mgmt_wr_en )
+                    if ( rwi_count_cfgspace_status_cl < rw[672+:32] )
+                        rwi_count_cfgspace_status_cl <= rwi_count_cfgspace_status_cl + 1;
+                    else begin
+                        rwi_count_cfgspace_status_cl <= 0;
+                        rw[RWPOS_CFG_WR_EN] <= 1'b1;
+                        rw[143:128] <= 16'h0007;                            // cfg_mgmt_di: command register [update to set individual command register bits]
+                        rw[159:144] <= 16'hff00;                            // cfg_mgmt_di: status register [do not update]
+                        rw[169:160] <= 1;                                   // cfg_mgmt_dwaddr
+                        rw[170]     <= 0;                                   // cfg_mgmt_wr_readonly
+                        rw[171]     <= 0;                                   // cfg_mgmt_wr_rw1c_as_rw
+                        rw[172]     <= rw[RWPOS_CFG_CFGSPACE_COMMAND_EN];   // cfg_mgmt_byte_en: command register
+                        rw[173]     <= rw[RWPOS_CFG_CFGSPACE_COMMAND_EN];   // cfg_mgmt_byte_en: command register
+                        rw[174]     <= 0;                                   // cfg_mgmt_byte_en: status register
+                        rw[175]     <= rw[RWPOS_CFG_CFGSPACE_STATUS_CL_EN]; // cfg_mgmt_byte_en: status register
+                    end
+
+                if ((base_address_register_reg == 32'h00000000) | (base_address_register_reg == 32'hFFE00000))
+                    if ( ~in_cmd_read & ~in_cmd_write & ~rw[RWPOS_CFG_RD_EN] & ~rw[RWPOS_CFG_WR_EN] & ~rwi_cfg_mgmt_rd_en & ~rwi_cfg_mgmt_wr_en )
+                        begin
+                            rw[RWPOS_CFG_RD_EN] <= 1'b1;
+                            rw[169:160] <= 4;                                   // cfg_mgmt_dwaddr
+                            rw[172]     <= 0;                                   // cfg_mgmt_byte_en
+                            rw[173]     <= 0;                                   // cfg_mgmt_byte_en
+                            rw[174]     <= 0;                                   // cfg_mgmt_byte_en
+                            rw[175]     <= 0;                                   // cfg_mgmt_byte_en
+                        end
+
+                // CONFIG SPACE READ/WRITE                        
+                if ( ctx.cfg_mgmt_rd_wr_done )
+                    begin
+                        //
+                        // if BAR0 was requested, lets save it.
+                        //
+                        if ((base_address_register_reg == 32'h00000000) | (base_address_register_reg == 32'hFFE00000))
+                            if ((ctx.cfg_mgmt_dwaddr == 8'h04) & rwi_cfg_mgmt_rd_en)
+                                    base_address_register_reg <= ctx.cfg_mgmt_do;
+
+
+                        rwi_cfg_mgmt_rd_en  <= 1'b0;
+                        rwi_cfg_mgmt_wr_en  <= 1'b0;
+                        rwi_cfgrd_valid     <= 1'b1;
+                        rwi_cfgrd_addr      <= ctx.cfg_mgmt_dwaddr;
+                        rwi_cfgrd_data      <= ctx.cfg_mgmt_do;
+                        rwi_cfgrd_byte_en   <= ctx.cfg_mgmt_byte_en;
+                    end
+                else if ( rw[RWPOS_CFG_RD_EN] )
+                    begin
+                        rw[RWPOS_CFG_RD_EN] <= 1'b0;
+                        rwi_cfg_mgmt_rd_en  <= 1'b1;
+                        rwi_cfgrd_valid     <= 1'b0;
+                    end
+                else if ( rw[RWPOS_CFG_WR_EN] )
+                    begin
+                        rw[RWPOS_CFG_WR_EN] <= 1'b0;
+                        rwi_cfg_mgmt_wr_en  <= 1'b1;
+                        rwi_cfgrd_valid     <= 1'b0;
+                    end
+                    
+                // STATIC_TLP TRANSMIT
+                if ( (rwi_tlp_static_valid && rwi_tlp_static_2nd) || ~rw[RWPOS_CFG_STATIC_TLP_TX_EN] ) begin    // STATE (3)
+                    rwi_tlp_static_valid    <= 1'b0;
+                    rwi_tlp_static_has_data <= 1'b0;
+                end
+                else if ( rwi_tlp_static_has_data && tlps_static.tready && rwi_tlp_static_2nd ) begin  // STATE (1)
+                     rwi_tlp_static_valid   <= 1'b1;
+                     rwi_tlp_static_2nd     <= 1'b0;
+                end
+                else if ( rwi_tlp_static_has_data && tlps_static.tready && !rwi_tlp_static_2nd ) begin // STATE (2)
+                     rwi_tlp_static_valid   <= 1'b1;
+                     rwi_tlp_static_2nd     <= 1'b1;
+                end
+                else if ( ((tickcount64[0+:16] & rw[240+:16]) == rw[240+:16]) & (rw[640+:32] > 0) & rw[224+2*0] ) begin   // IDLE STATE (0)
+                    rwi_tlp_static_has_data <= 1'b1;
+                    rwi_tlp_static_2nd      <= 1'b1;
+                    rw[640+:32] <= rw[640+:32] - 1;     // count - 1
+                    if ( rw[640+:32] == 32'h00000001 )
+                        rw[RWPOS_CFG_STATIC_TLP_TX_EN] <= 1'b0;
+                end
+                
+            end
+    
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_pcie_cfgspace_shadow.sv

@@ -0,0 +1,105 @@
+//
+// PCILeech FPGA.
+//
+// PCIe custom shadow configuration space.
+// Xilinx PCIe core will take configuration space priority; if Xilinx PCIe core
+// is configured to forward configuration requests to user application such TLP
+// will end up being processed by this module.
+//
+// (c) Ulf Frisk, 2021-2022
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+
+module pcileech_pcie_cfgspace_shadow(
+    input                   rst,
+    input                   clk,
+    IfShadow2Fifo.src       dshadow2fifo,
+    IfShadow2Tlp.shadow     dshadow2tlp
+    );
+    
+    wire            int_rden;
+    wire            int_wren;
+    wire [9:0]      int_wr_addr;
+    wire [31:0]     int_wr_data;
+    wire [9:0]      int_rd_addr;
+    
+    // ----------------------------------------------------------------------------
+    // WRITE multiplexor: simple naive multiplexor which will prioritize in order:
+    // (1) PCIe (if enabled), (2) USB, (3) INTERNAL.
+    // Collisions will be discarded (it's assumed that they'll be very rare)
+    // ----------------------------------------------------------------------------
+    wire            bram_wr_1_tlp = dshadow2tlp.rx_wren;
+    wire            bram_wr_2_usb = ~bram_wr_1_tlp & dshadow2fifo.rx_wren;
+    wire            bram_wr_3_int = ~bram_wr_1_tlp & ~bram_wr_2_usb & int_wren;
+    wire [3:0]      bram_wr_be = bram_wr_1_tlp ? (dshadow2fifo.cfgtlp_wren ? dshadow2tlp.rx_be : 4'b0000) : (bram_wr_2_usb ? dshadow2fifo.rx_be : (bram_wr_3_int ? 4'b1111 : 4'b0000));
+    wire [9:0]      bram_wr_addr = bram_wr_1_tlp ? dshadow2tlp.rx_addr : (bram_wr_2_usb ? dshadow2fifo.rx_addr : int_wr_addr);
+    wire [31:0]     bram_wr_data = bram_wr_1_tlp ? dshadow2tlp.rx_data : (bram_wr_2_usb ? dshadow2fifo.rx_data : int_wr_data);
+    
+    // ----------------------------------------------------------------------------
+    // WRITE multiplexor and state machine: simple naive multiplexor which will prioritize in order:
+    // (1) PCIe (if enabled), (2) USB, (3) INTERNAL.
+    // Collisions will be discarded (it's assumed that they'll be very rare)
+    // ----------------------------------------------------------------------------
+    `define S_SHADOW_CFGSPACE_IDLE  2'b00
+    `define S_SHADOW_CFGSPACE_TLP   2'b01
+    `define S_SHADOW_CFGSPACE_USB   2'b10
+    `define S_SHADOW_CFGSPACE_INT   2'b11
+    
+    wire [31:0]     bram_rd_data;
+    wire            bram_rd_1_tlp = dshadow2tlp.rx_rden;
+    wire            bram_rd_2_usb = ~bram_rd_1_tlp & dshadow2fifo.rx_rden;
+    wire            bram_rd_3_int = ~bram_rd_1_tlp & ~bram_rd_2_usb & int_rden;
+    wire [1:0]      bram_rd_tp_3 =   bram_rd_1_tlp ? `S_SHADOW_CFGSPACE_TLP : (
+                                     bram_rd_2_usb ? `S_SHADOW_CFGSPACE_USB : (
+                                     bram_rd_3_int ? `S_SHADOW_CFGSPACE_INT : `S_SHADOW_CFGSPACE_IDLE));
+    wire [9:0]      bram_rd_addr_3 = bram_rd_1_tlp ? dshadow2tlp.rx_addr : (
+                                     bram_rd_2_usb ? dshadow2fifo.rx_addr : int_rd_addr);
+    wire [7:0]      bram_rd_tag_3 =  bram_rd_1_tlp ? dshadow2tlp.rx_tag : {7'h00, dshadow2fifo.rx_addr_lo};
+    bit [9:0]       bram_rd_addr, bram_rd_addr_2;
+    bit [7:0]       bram_rd_tag,  bram_rd_tag_2;
+    bit [1:0]       bram_rd_tp,   bram_rd_tp_2;    
+    
+    always @ ( posedge clk )
+        begin
+            bram_rd_addr    <= bram_rd_addr_2;
+            bram_rd_tag     <= bram_rd_tag_2;
+            bram_rd_tp      <= bram_rd_tp_2;
+            bram_rd_addr_2  <= bram_rd_addr_3;
+            bram_rd_tag_2   <= bram_rd_tag_3;
+            bram_rd_tp_2    <= bram_rd_tp_3;
+        end
+    
+    // BRAM MEMORY ACCESS for the 4kB / 0x1000 byte shadow configuration space.
+    bram_pcie_cfgspace i_bram_pcie_cfgspace(
+        .clka           ( clk                       ),
+        .clkb           ( clk                       ),
+        .wea            ( bram_wr_be                ),
+        .addra          ( bram_wr_addr              ),
+        .dina           ( bram_wr_data              ),
+        .addrb          ( bram_rd_addr_3            ),
+        .doutb          ( bram_rd_data              )
+    );
+    
+    assign dshadow2tlp.tx_valid     = bram_wr_1_tlp | (bram_rd_tp == `S_SHADOW_CFGSPACE_TLP);
+    assign dshadow2tlp.tx_tlprd     = ~bram_wr_1_tlp;
+    assign dshadow2tlp.tx_tag       = bram_wr_1_tlp ? dshadow2tlp.rx_tag : bram_rd_tag;
+    assign dshadow2tlp.tx_data      = dshadow2fifo.cfgtlp_zero ? 32'h00000000 : bram_rd_data;
+    
+    assign dshadow2fifo.tx_valid    = (bram_rd_tp == `S_SHADOW_CFGSPACE_USB);
+    assign dshadow2fifo.tx_addr     = bram_rd_addr;
+    assign dshadow2fifo.tx_addr_lo  = bram_rd_tag[0];
+    assign dshadow2fifo.tx_data     = dshadow2fifo.cfgtlp_zero ? 32'h00000000 : bram_rd_data;
+    
+    // ----------------------------------------------------------------------------
+    // INTERNAL LOGIC BELOW:
+    // ----------------------------------------------------------------------------
+    
+    assign int_rden     = 0;
+    assign int_wren     = 0;
+    assign int_wr_addr  = 0;
+    assign int_wr_data  = 0;
+    assign int_rd_addr  = 0;
+    
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_pcie_tlp_a7.sv

@@ -0,0 +1,350 @@
+//
+// PCILeech FPGA.
+//
+// PCIe controller module - TLP handling for Artix-7.
+//
+// (c) Ulf Frisk, 2018-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_pcie_tlp_a7(
+    input                   rst,
+    input                   clk_pcie,
+    input                   clk_sys,
+    IfPCIeFifoTlp.mp_pcie   dfifo,
+    
+    // PCIe core receive/transmit data
+    IfAXIS128.source        tlps_tx,
+    IfAXIS128.sink_lite     tlps_rx,
+    IfAXIS128.sink          tlps_static,
+    IfShadow2Fifo.shadow    dshadow2fifo,
+    input [15:0]            pcie_id,
+    input [31:0]            base_address_register
+    );
+    
+    IfAXIS128 tlps_bar_rsp();
+    IfAXIS128 tlps_cfg_rsp();
+    
+    // ------------------------------------------------------------------------
+    // Convert received TLPs from PCIe core and transmit onwards:
+    // ------------------------------------------------------------------------
+    IfAXIS128 tlps_filtered();
+    
+    pcileech_tlps128_bar_controller i_pcileech_tlps128_bar_controller(
+        .rst                   ( rst                    ),
+        .clk                   ( clk_pcie               ),
+        .bar_en                ( dshadow2fifo.bar_en    ),
+        .pcie_id               ( pcie_id                ),
+        .base_address_register ( base_address_register  ),
+        .tlps_in               ( tlps_rx                ),
+        .tlps_out              ( tlps_bar_rsp.source    )
+    );
+    
+    pcileech_tlps128_cfgspace_shadow i_pcileech_tlps128_cfgspace_shadow(
+        .rst            ( rst                           ),
+        .clk_pcie       ( clk_pcie                      ),
+        .clk_sys        ( clk_sys                       ),
+        .tlps_in        ( tlps_rx                       ),
+        .pcie_id        ( pcie_id                       ),
+        .dshadow2fifo   ( dshadow2fifo                  ),
+        .tlps_cfg_rsp   ( tlps_cfg_rsp.source           )
+    );
+    
+    pcileech_tlps128_filter i_pcileech_tlps128_filter(
+        .rst            ( rst                           ),
+        .clk_pcie       ( clk_pcie                      ),
+        .alltlp_filter  ( dshadow2fifo.alltlp_filter    ),
+        .cfgtlp_filter  ( dshadow2fifo.cfgtlp_filter    ),
+        .tlps_in        ( tlps_rx                       ),
+        .tlps_out       ( tlps_filtered.source_lite     )
+    );
+    
+    pcileech_tlps128_dst_fifo i_pcileech_tlps128_dst_fifo(
+        .rst            ( rst                           ),
+        .clk_pcie       ( clk_pcie                      ),
+        .clk_sys        ( clk_sys                       ),
+        .tlps_in        ( tlps_filtered.sink_lite       ),
+        .dfifo          ( dfifo                         )
+    );
+    
+    // ------------------------------------------------------------------------
+    // TX data received from FIFO
+    // ------------------------------------------------------------------------
+    IfAXIS128 tlps_rx_fifo();
+    
+    pcileech_tlps128_src_fifo i_pcileech_tlps128_src_fifo(
+        .rst            ( rst                           ),
+        .clk_pcie       ( clk_pcie                      ),
+        .clk_sys        ( clk_sys                       ),
+        .dfifo_tx_data  ( dfifo.tx_data                 ),
+        .dfifo_tx_last  ( dfifo.tx_last                 ),
+        .dfifo_tx_valid ( dfifo.tx_valid                ),
+        .tlps_out       ( tlps_rx_fifo.source           )
+    );
+    
+    pcileech_tlps128_sink_mux1 i_pcileech_tlps128_sink_mux1(
+        .rst            ( rst                           ),
+        .clk_pcie       ( clk_pcie                      ),
+        .tlps_out       ( tlps_tx                       ),
+        .tlps_in1       ( tlps_cfg_rsp.sink             ),
+        .tlps_in2       ( tlps_bar_rsp.sink             ),
+        .tlps_in3       ( tlps_rx_fifo.sink             ),
+        .tlps_in4       ( tlps_static                   )
+    );
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// TLP-AXI-STREAM destination:
+// Forward the data to output device (FT601, etc.). 
+// ------------------------------------------------------------------------
+module pcileech_tlps128_dst_fifo(
+    input                   rst,
+    input                   clk_pcie,
+    input                   clk_sys,
+    IfAXIS128.sink_lite     tlps_in,
+    IfPCIeFifoTlp.mp_pcie   dfifo
+);
+    
+    wire         tvalid;
+    wire [127:0] tdata;
+    wire [3:0]   tkeepdw;
+    wire         tlast;
+    wire         first;
+       
+    fifo_134_134_clk2 i_fifo_134_134_clk2 (
+        .rst        ( rst               ),
+        .wr_clk     ( clk_pcie          ),
+        .rd_clk     ( clk_sys           ),
+        .din        ( { tlps_in.tuser[0], tlps_in.tlast, tlps_in.tkeepdw, tlps_in.tdata } ),
+        .wr_en      ( tlps_in.tvalid    ),
+        .rd_en      ( dfifo.rx_rd_en    ),
+        .dout       ( { first, tlast, tkeepdw, tdata } ),
+        .full       (                   ),
+        .empty      (                   ),
+        .valid      ( tvalid            )
+    );
+
+    assign dfifo.rx_data[0]  = tdata[31:0];
+    assign dfifo.rx_data[1]  = tdata[63:32];
+    assign dfifo.rx_data[2]  = tdata[95:64];
+    assign dfifo.rx_data[3]  = tdata[127:96];
+    assign dfifo.rx_first[0] = first;
+    assign dfifo.rx_first[1] = 0;
+    assign dfifo.rx_first[2] = 0;
+    assign dfifo.rx_first[3] = 0;
+    assign dfifo.rx_last[0]  = tlast && (tkeepdw == 4'b0001);
+    assign dfifo.rx_last[1]  = tlast && (tkeepdw == 4'b0011);
+    assign dfifo.rx_last[2]  = tlast && (tkeepdw == 4'b0111);
+    assign dfifo.rx_last[3]  = tlast && (tkeepdw == 4'b1111);
+    assign dfifo.rx_valid[0] = tvalid && tkeepdw[0];
+    assign dfifo.rx_valid[1] = tvalid && tkeepdw[1];
+    assign dfifo.rx_valid[2] = tvalid && tkeepdw[2];
+    assign dfifo.rx_valid[3] = tvalid && tkeepdw[3];
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// TLP-AXI-STREAM FILTER:
+// Filter away certain packet types such as CfgRd/CfgWr or non-Cpl/CplD
+// ------------------------------------------------------------------------
+module pcileech_tlps128_filter(
+    input                   rst,
+    input                   clk_pcie,
+    input                   alltlp_filter,
+    input                   cfgtlp_filter,
+    IfAXIS128.sink_lite     tlps_in,
+    IfAXIS128.source_lite   tlps_out
+);
+
+    bit [127:0]     tdata;
+    bit [3:0]       tkeepdw;
+    bit             tvalid  = 0;
+    bit [8:0]       tuser;
+    bit             tlast;
+    
+    assign tlps_out.tdata   = tdata;
+    assign tlps_out.tkeepdw = tkeepdw;
+    assign tlps_out.tvalid  = tvalid;
+    assign tlps_out.tuser   = tuser;
+    assign tlps_out.tlast   = tlast;
+    
+    bit  filter = 0;
+    wire first = tlps_in.tuser[0];
+    wire is_tlphdr_cpl = first && (
+                        (tlps_in.tdata[31:25] == 7'b0000101) ||      // Cpl:  Fmt[2:0]=000b (3 DW header, no data), Cpl=0101xb
+                        (tlps_in.tdata[31:25] == 7'b0100101)         // CplD: Fmt[2:0]=010b (3 DW header, data),    CplD=0101xb
+                      );
+    wire is_tlphdr_cfg = first && (
+                        (tlps_in.tdata[31:25] == 7'b0000010) ||      // CfgRd: Fmt[2:0]=000b (3 DW header, no data), CfgRd0/CfgRd1=0010xb
+                        (tlps_in.tdata[31:25] == 7'b0100010)         // CfgWr: Fmt[2:0]=010b (3 DW header, data),    CfgWr0/CfgWr1=0010xb
+                      );
+    wire filter_next = (filter && !first) || (cfgtlp_filter && first && is_tlphdr_cfg) || (alltlp_filter && first && !is_tlphdr_cpl && !is_tlphdr_cfg);
+                      
+    always @ ( posedge clk_pcie ) begin
+        tdata   <= tlps_in.tdata;
+        tkeepdw <= tlps_in.tkeepdw;
+        tvalid  <= tlps_in.tvalid && !filter_next && !rst;
+        tuser   <= tlps_in.tuser;
+        tlast   <= tlps_in.tlast;
+        filter  <= filter_next && !rst;
+    end
+    
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// RX FROM FIFO - TLP-AXI-STREAM:
+// Convert 32-bit incoming data to 128-bit TLP-AXI-STREAM to be sent onwards to mux/pcie core. 
+// ------------------------------------------------------------------------
+module pcileech_tlps128_src_fifo (
+    input                   rst,
+    input                   clk_pcie,
+    input                   clk_sys,
+    input [31:0]            dfifo_tx_data,
+    input                   dfifo_tx_last,
+    input                   dfifo_tx_valid,
+    IfAXIS128.source        tlps_out
+);
+
+    // 1: 32-bit -> 128-bit state machine:
+    bit [127:0] tdata;
+    bit [3:0]   tkeepdw = 0;
+    bit         tlast;
+    bit         first   = 1;
+    wire        tvalid  = tlast || tkeepdw[3];
+    
+    always @ ( posedge clk_sys )
+        if ( rst ) begin
+            tkeepdw <= 0;
+            tlast   <= 0;
+            first   <= 1;
+        end
+        else begin
+            tlast   <= dfifo_tx_valid && dfifo_tx_last;
+            tkeepdw <= tvalid ? (dfifo_tx_valid ? 4'b0001 : 4'b0000) : (dfifo_tx_valid ? ((tkeepdw << 1) | 1'b1) : tkeepdw);
+            first   <= tvalid ? tlast : first;
+            if ( dfifo_tx_valid ) begin
+                if ( tvalid || !tkeepdw[0] )
+                    tdata[31:0]   <= dfifo_tx_data;
+                if ( !tkeepdw[1] )
+                    tdata[63:32]  <= dfifo_tx_data;
+                if ( !tkeepdw[2] )
+                    tdata[95:64]  <= dfifo_tx_data;
+                if ( !tkeepdw[3] )
+                    tdata[127:96] <= dfifo_tx_data;   
+            end
+        end
+		
+    // 2.1 - packet count (w/ safe fifo clock-crossing).
+    bit [10:0]  pkt_count       = 0;
+    wire        pkt_count_dec   = tlps_out.tvalid && tlps_out.tlast;
+    wire        pkt_count_inc;
+    wire [10:0] pkt_count_next  = pkt_count + pkt_count_inc - pkt_count_dec;
+    assign tlps_out.has_data    = (pkt_count_next > 0);
+    
+    fifo_1_1_clk2 i_fifo_1_1_clk2(
+        .rst            ( rst                       ),
+        .wr_clk         ( clk_sys                   ),
+        .rd_clk         ( clk_pcie                  ),
+        .din            ( 1'b1                      ),
+        .wr_en          ( tvalid && tlast           ),
+        .rd_en          ( 1'b1                      ),
+        .dout           (                           ),
+        .full           (                           ),
+        .empty          (                           ),
+        .valid          ( pkt_count_inc             )
+    );
+	
+    always @ ( posedge clk_pcie ) begin
+        pkt_count <= rst ? 0 : pkt_count_next;
+    end
+        
+    // 2.2 - submit to output fifo - will feed into mux/pcie core.
+    //       together with 2.1 this will form a low-latency "packet fifo".
+    fifo_134_134_clk2_rxfifo i_fifo_134_134_clk2_rxfifo(
+        .rst            ( rst                       ),
+        .wr_clk         ( clk_sys                   ),
+        .rd_clk         ( clk_pcie                  ),
+        .din            ( { first, tlast, tkeepdw, tdata } ),
+        .wr_en          ( tvalid                    ),
+        .rd_en          ( tlps_out.tready && (pkt_count_next > 0) ),
+        .dout           ( { tlps_out.tuser[0], tlps_out.tlast, tlps_out.tkeepdw, tlps_out.tdata } ),
+        .full           (                           ),
+        .empty          (                           ),
+        .valid          ( tlps_out.tvalid           )
+    );
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// RX MUX - TLP-AXI-STREAM:
+// Select the TLP-AXI-STREAM with the highest priority (lowest number) and
+// let it transmit its full packet.
+// Each incoming stream must have latency of 1CLK. 
+// ------------------------------------------------------------------------
+module pcileech_tlps128_sink_mux1 (
+    input                       clk_pcie,
+    input                       rst,
+    IfAXIS128.source            tlps_out,
+    IfAXIS128.sink              tlps_in1,
+    IfAXIS128.sink              tlps_in2,
+    IfAXIS128.sink              tlps_in3,
+    IfAXIS128.sink              tlps_in4
+);
+    bit [2:0] id = 0;
+    
+    assign tlps_out.has_data    = tlps_in1.has_data || tlps_in2.has_data || tlps_in3.has_data || tlps_in4.has_data;
+    
+    assign tlps_out.tdata       = (id==1) ? tlps_in1.tdata :
+                                  (id==2) ? tlps_in2.tdata :
+                                  (id==3) ? tlps_in3.tdata :
+                                  (id==4) ? tlps_in4.tdata : 0;
+    
+    assign tlps_out.tkeepdw     = (id==1) ? tlps_in1.tkeepdw :
+                                  (id==2) ? tlps_in2.tkeepdw :
+                                  (id==3) ? tlps_in3.tkeepdw :
+                                  (id==4) ? tlps_in4.tkeepdw : 0;
+    
+    assign tlps_out.tlast       = (id==1) ? tlps_in1.tlast :
+                                  (id==2) ? tlps_in2.tlast :
+                                  (id==3) ? tlps_in3.tlast :
+                                  (id==4) ? tlps_in4.tlast : 0;
+    
+    assign tlps_out.tuser       = (id==1) ? tlps_in1.tuser :
+                                  (id==2) ? tlps_in2.tuser :
+                                  (id==3) ? tlps_in3.tuser :
+                                  (id==4) ? tlps_in4.tuser : 0;
+    
+    assign tlps_out.tvalid      = (id==1) ? tlps_in1.tvalid :
+                                  (id==2) ? tlps_in2.tvalid :
+                                  (id==3) ? tlps_in3.tvalid :
+                                  (id==4) ? tlps_in4.tvalid : 0;
+    
+    wire [2:0] id_next_newsel   = tlps_in1.has_data ? 1 :
+                                  tlps_in2.has_data ? 2 :
+                                  tlps_in3.has_data ? 3 :
+                                  tlps_in4.has_data ? 4 : 0;
+    
+    wire [2:0] id_next          = ((id==0) || (tlps_out.tvalid && tlps_out.tlast)) ? id_next_newsel : id;
+    
+    assign tlps_in1.tready      = tlps_out.tready && (id_next==1);
+    assign tlps_in2.tready      = tlps_out.tready && (id_next==2);
+    assign tlps_in3.tready      = tlps_out.tready && (id_next==3);
+    assign tlps_in4.tready      = tlps_out.tready && (id_next==4);
+    
+    always @ ( posedge clk_pcie ) begin
+        id <= rst ? 0 : id_next;
+    end
+    
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_screamer_m2.xdc

@@ -0,0 +1,126 @@
+set_property PACKAGE_PIN L18 [get_ports {ft601_be[0]}]
+set_property PACKAGE_PIN M17 [get_ports {ft601_be[1]}]
+set_property PACKAGE_PIN N18 [get_ports {ft601_be[2]}]
+set_property PACKAGE_PIN N17 [get_ports {ft601_be[3]}]
+set_property PACKAGE_PIN B9  [get_ports {ft601_data[0]}]
+set_property PACKAGE_PIN A9  [get_ports {ft601_data[1]}]
+set_property PACKAGE_PIN C9  [get_ports {ft601_data[2]}]
+set_property PACKAGE_PIN A10 [get_ports {ft601_data[3]}]
+set_property PACKAGE_PIN B10 [get_ports {ft601_data[4]}]
+set_property PACKAGE_PIN B11 [get_ports {ft601_data[5]}]
+set_property PACKAGE_PIN A12 [get_ports {ft601_data[6]}]
+set_property PACKAGE_PIN B12 [get_ports {ft601_data[7]}]
+set_property PACKAGE_PIN A13 [get_ports {ft601_data[8]}]
+set_property PACKAGE_PIN A14 [get_ports {ft601_data[9]}]
+set_property PACKAGE_PIN B14 [get_ports {ft601_data[10]}]
+set_property PACKAGE_PIN A15 [get_ports {ft601_data[11]}]
+set_property PACKAGE_PIN B15 [get_ports {ft601_data[12]}]
+set_property PACKAGE_PIN B16 [get_ports {ft601_data[13]}]
+set_property PACKAGE_PIN A17 [get_ports {ft601_data[14]}]
+set_property PACKAGE_PIN B17 [get_ports {ft601_data[15]}]
+set_property PACKAGE_PIN C17 [get_ports {ft601_data[16]}]
+set_property PACKAGE_PIN C18 [get_ports {ft601_data[17]}]
+set_property PACKAGE_PIN D18 [get_ports {ft601_data[18]}]
+set_property PACKAGE_PIN E17 [get_ports {ft601_data[19]}]
+set_property PACKAGE_PIN E18 [get_ports {ft601_data[20]}]
+set_property PACKAGE_PIN E16 [get_ports {ft601_data[21]}]
+set_property PACKAGE_PIN F18 [get_ports {ft601_data[22]}]
+set_property PACKAGE_PIN F17 [get_ports {ft601_data[23]}]
+set_property PACKAGE_PIN G17 [get_ports {ft601_data[24]}]
+set_property PACKAGE_PIN H18 [get_ports {ft601_data[25]}]
+set_property PACKAGE_PIN D13 [get_ports {ft601_data[26]}]
+set_property PACKAGE_PIN C14 [get_ports {ft601_data[27]}]
+set_property PACKAGE_PIN D14 [get_ports {ft601_data[28]}]
+set_property PACKAGE_PIN D15 [get_ports {ft601_data[29]}]
+set_property PACKAGE_PIN C16 [get_ports {ft601_data[30]}]
+set_property PACKAGE_PIN D16 [get_ports {ft601_data[31]}]
+set_property PACKAGE_PIN T15 [get_ports ft601_oe_n]
+set_property PACKAGE_PIN R16 [get_ports ft601_rd_n]
+set_property PACKAGE_PIN R18 [get_ports ft601_rxf_n]
+set_property PACKAGE_PIN R17 [get_ports ft601_siwu_n]
+set_property PACKAGE_PIN P18 [get_ports ft601_txe_n]
+set_property PACKAGE_PIN T18 [get_ports ft601_wr_n]
+set_property PACKAGE_PIN U15 [get_ports ft601_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+
+set_property PACKAGE_PIN V17 [get_ports user_ld1]
+set_property PACKAGE_PIN U17 [get_ports user_ld2]
+set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1 user_ld2}]
+
+# SYSCLK
+set_property PACKAGE_PIN R2 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk]
+
+# FT601 CLK
+create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk]
+set_property PACKAGE_PIN E13 [get_ports ft601_clk]
+
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n]
+
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]]
+
+set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_false_path -from [get_pins {tickcount64_reg[*]/C}]
+set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
+
+#PCIe signals
+set_property PACKAGE_PIN K1 [get_ports pcie_present]
+set_property PACKAGE_PIN M1 [get_ports pcie_perst_n]
+set_property PACKAGE_PIN L2 [get_ports pcie_wake_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_present]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n]
+
+set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells {i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property PACKAGE_PIN E3 [get_ports pcie_rx_n[0]]
+set_property PACKAGE_PIN E4 [get_ports pcie_rx_p[0]]
+set_property PACKAGE_PIN H1 [get_ports pcie_tx_n[0]]
+set_property PACKAGE_PIN H2 [get_ports pcie_tx_p[0]]
+
+#set_property PACKAGE_PIN A3 [get_ports pcie_rx_n[1]]
+#set_property PACKAGE_PIN A4 [get_ports pcie_rx_p[1]]
+#set_property PACKAGE_PIN F1 [get_ports pcie_tx_n[1]]
+#set_property PACKAGE_PIN F2 [get_ports pcie_tx_p[1]]
+
+#set_property PACKAGE_PIN C3 [get_ports pcie_rx_n[2]]
+#set_property PACKAGE_PIN C4 [get_ports pcie_rx_p[2]]
+#set_property PACKAGE_PIN D1 [get_ports pcie_tx_n[2]]
+#set_property PACKAGE_PIN D2 [get_ports pcie_tx_p[2]]
+
+#set_property PACKAGE_PIN G3 [get_ports pcie_rx_n[3]]
+#set_property PACKAGE_PIN G4 [get_ports pcie_rx_p[3]]
+#set_property PACKAGE_PIN B1 [get_ports pcie_tx_n[3]]
+#set_property PACKAGE_PIN B2 [get_ports pcie_tx_p[3]]
+
+set_property PACKAGE_PIN D5 [get_ports pcie_clk_n]
+set_property PACKAGE_PIN D6 [get_ports pcie_clk_p]
+
+create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p]
+
+set_property CFGBVS Vcco [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

JOKOSAHS_DMA-Pcileech/src/pcileech_screamer_m2_top.sv

@@ -0,0 +1,159 @@
+//
+// PCILeech FPGA.
+//
+// Top module for various 35T-325 x1 Artix-7 boards.
+//
+// (c) Ulf Frisk, 2019-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_screamer_m2_top #(
+    parameter       PARAM_DEVICE_ID = 4,
+    parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
+    parameter       PARAM_VERSION_NUMBER_MINOR = 13,
+    parameter       PARAM_CUSTOM_VALUE = 32'hffffffff
+) (
+    // SYS
+    input           clk,
+    input           ft601_clk,
+    
+    // SYSTEM LEDs and BUTTONs
+    output          user_ld1,
+    output          user_ld2,
+    
+    // PCI-E FABRIC
+    output  [0:0]   pcie_tx_p,
+    output  [0:0]   pcie_tx_n,
+    input   [0:0]   pcie_rx_p,
+    input   [0:0]   pcie_rx_n,
+    input           pcie_clk_p,
+    input           pcie_clk_n,
+    input           pcie_present,
+    input           pcie_perst_n,
+    output reg      pcie_wake_n = 1'b1,
+    
+    // TO/FROM FT601 PADS
+    output          ft601_rst_n,
+    
+    inout   [31:0]  ft601_data,
+    output  [3:0]   ft601_be,
+    input           ft601_rxf_n,
+    input           ft601_txe_n,
+    output          ft601_wr_n,
+    output          ft601_siwu_n,
+    output          ft601_rd_n,
+    output          ft601_oe_n
+    );
+    
+    // SYS
+    wire            rst;
+    
+    // FIFO CTL <--> COM CTL
+    wire [63:0]     com_dout;
+    wire            com_dout_valid;
+    wire [255:0]    com_din;
+    wire            com_din_wr_en;
+    wire            com_din_ready;
+    wire            led_com;
+    wire            led_pcie;
+    
+    // FIFO CTL <--> COM CTL
+    IfComToFifo     dcom_fifo();
+	
+    // FIFO CTL <--> PCIe
+    IfPCIeFifoCfg   dcfg();
+    IfPCIeFifoTlp   dtlp();
+    IfPCIeFifoCore  dpcie();
+    IfShadow2Fifo   dshadow2fifo();
+	
+    // ----------------------------------------------------
+    // TickCount64 CLK
+    // ----------------------------------------------------
+
+    time tickcount64 = 0;
+    always @ ( posedge clk )
+        tickcount64 <= tickcount64 + 1;
+
+    assign rst = (tickcount64 < 64) ? 1'b1 : 1'b0;
+    assign ft601_rst_n = ~rst;
+    wire led_pwronblink = tickcount64[24] & (tickcount64[63:27] == 0);
+    
+    OBUF led_ld1_obuf(.O(user_ld1), .I(led_pcie));
+    OBUF led_ld2_obuf(.O(user_ld2), .I(led_com));
+    
+    // ----------------------------------------------------
+    // BUFFERED COMMUNICATION DEVICE (FT601)
+    // ----------------------------------------------------
+    
+    pcileech_com i_pcileech_com (
+        // SYS
+        .clk                ( clk                   ),
+        .clk_com            ( ft601_clk             ),
+        .rst                ( rst                   ),
+        .led_state_txdata   ( led_com               ),  // ->
+        .led_state_invert   ( led_pwronblink        ),  // <-
+        // FIFO CTL <--> COM CTL
+        .dfifo              ( dcom_fifo.mp_com      ),
+        // TO/FROM FT601 PADS
+        .ft601_data         ( ft601_data            ),  // <> [31:0]
+        .ft601_be           ( ft601_be              ),  // -> [3:0]
+        .ft601_txe_n        ( ft601_txe_n           ),  // <-
+        .ft601_rxf_n        ( ft601_rxf_n           ),  // <-
+        .ft601_siwu_n       ( ft601_siwu_n          ),  // ->
+        .ft601_wr_n         ( ft601_wr_n            ),  // ->
+        .ft601_rd_n         ( ft601_rd_n            ),  // ->
+        .ft601_oe_n         ( ft601_oe_n            )   // ->
+    );
+    
+    // ----------------------------------------------------
+    // FIFO CTL
+    // ----------------------------------------------------
+    
+    pcileech_fifo #(
+        .PARAM_DEVICE_ID            ( PARAM_DEVICE_ID               ),
+        .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR    ),
+        .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR    ),
+        .PARAM_CUSTOM_VALUE         ( PARAM_CUSTOM_VALUE            )
+    ) i_pcileech_fifo (
+        .clk                ( clk                   ),
+        .rst                ( rst                   ),
+        .rst_cfg_reload     ( 1'b0                  ),
+        .pcie_present       ( pcie_present          ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // FIFO CTL <--> COM CTL
+        .dcom               ( dcom_fifo.mp_fifo     ),
+        // FIFO CTL <--> PCIe
+        .dcfg               ( dcfg.mp_fifo          ),
+        .dtlp               ( dtlp.mp_fifo          ),
+        .dpcie              ( dpcie.mp_fifo         ),
+        .dshadow2fifo       ( dshadow2fifo.fifo     )
+    );
+    
+    // ----------------------------------------------------
+    // PCIe
+    // ----------------------------------------------------
+    
+    pcileech_pcie_a7 i_pcileech_pcie_a7(
+        .clk_sys            ( clk                   ),
+        .rst                ( rst                   ),
+        // PCIe fabric
+        .pcie_tx_p          ( pcie_tx_p             ),
+        .pcie_tx_n          ( pcie_tx_n             ),
+        .pcie_rx_p          ( pcie_rx_p             ),
+        .pcie_rx_n          ( pcie_rx_n             ),
+        .pcie_clk_p         ( pcie_clk_p            ),
+        .pcie_clk_n         ( pcie_clk_n            ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // State and Activity LEDs
+        .led_state          ( led_pcie              ),
+        // FIFO CTL <--> PCIe
+        .dfifo_cfg          ( dcfg.mp_pcie          ),
+        .dfifo_tlp          ( dtlp.mp_pcie          ),
+        .dfifo_pcie         ( dpcie.mp_pcie         ),
+        .dshadow2fifo       ( dshadow2fifo.shadow   )
+    );
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_squirrel.xdc

@@ -0,0 +1,116 @@
+set_property PACKAGE_PIN Y18  [get_ports ft601_be[0]]
+set_property PACKAGE_PIN AA18 [get_ports ft601_be[1]]
+set_property PACKAGE_PIN AB18 [get_ports ft601_be[2]]
+set_property PACKAGE_PIN W17  [get_ports ft601_be[3]]
+set_property PACKAGE_PIN N13  [get_ports ft601_data[0]]
+set_property PACKAGE_PIN N14  [get_ports ft601_data[1]]
+set_property PACKAGE_PIN N15  [get_ports ft601_data[2]]
+set_property PACKAGE_PIN P15  [get_ports ft601_data[3]]
+set_property PACKAGE_PIN P16  [get_ports ft601_data[4]]
+set_property PACKAGE_PIN N17  [get_ports ft601_data[5]]
+set_property PACKAGE_PIN P17  [get_ports ft601_data[6]]
+set_property PACKAGE_PIN R17  [get_ports ft601_data[7]]
+set_property PACKAGE_PIN P19  [get_ports ft601_data[8]]
+set_property PACKAGE_PIN R18  [get_ports ft601_data[9]]
+set_property PACKAGE_PIN R19  [get_ports ft601_data[10]]
+set_property PACKAGE_PIN T18  [get_ports ft601_data[11]]
+set_property PACKAGE_PIN U18  [get_ports ft601_data[12]]
+set_property PACKAGE_PIN V18  [get_ports ft601_data[13]]
+set_property PACKAGE_PIN V19  [get_ports ft601_data[14]]
+set_property PACKAGE_PIN V17  [get_ports ft601_data[15]]
+set_property PACKAGE_PIN W20  [get_ports ft601_data[16]]
+set_property PACKAGE_PIN Y19  [get_ports ft601_data[17]]
+set_property PACKAGE_PIN T21  [get_ports ft601_data[18]]
+set_property PACKAGE_PIN T20  [get_ports ft601_data[19]]
+set_property PACKAGE_PIN U21  [get_ports ft601_data[20]]
+set_property PACKAGE_PIN V20  [get_ports ft601_data[21]]
+set_property PACKAGE_PIN W22  [get_ports ft601_data[22]]
+set_property PACKAGE_PIN W21  [get_ports ft601_data[23]]
+set_property PACKAGE_PIN Y22  [get_ports ft601_data[24]]
+set_property PACKAGE_PIN Y21  [get_ports ft601_data[25]]
+set_property PACKAGE_PIN AA21 [get_ports ft601_data[26]]
+set_property PACKAGE_PIN AB22 [get_ports ft601_data[27]]
+set_property PACKAGE_PIN AA20 [get_ports ft601_data[28]]
+set_property PACKAGE_PIN AB21 [get_ports ft601_data[29]]
+set_property PACKAGE_PIN AA19 [get_ports ft601_data[30]]
+set_property PACKAGE_PIN AB20 [get_ports ft601_data[31]]
+set_property PACKAGE_PIN AB6  [get_ports ft601_oe_n]
+set_property PACKAGE_PIN AA6  [get_ports ft601_rd_n]
+set_property PACKAGE_PIN AB8 [get_ports ft601_rxf_n]
+set_property PACKAGE_PIN Y8 [get_ports ft601_siwu_n]
+set_property PACKAGE_PIN AA8 [get_ports ft601_txe_n]
+set_property PACKAGE_PIN AB7  [get_ports ft601_wr_n]
+set_property PACKAGE_PIN Y9  [get_ports ft601_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}]
+set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}]
+
+set_property PACKAGE_PIN Y6  [get_ports user_ld1]
+set_property PACKAGE_PIN AB5 [get_ports user_ld2]
+set_property PACKAGE_PIN AB3 [get_ports user_sw1_n]
+set_property PACKAGE_PIN AA5 [get_ports user_sw2_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1 user_ld2 user_sw1_n user_sw2_n}]
+
+set_property PACKAGE_PIN F21 [get_ports ft2232_rst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports ft2232_rst_n]
+
+# SYSCLK
+set_property PACKAGE_PIN H4 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk]
+
+# FT601 CLK
+create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk]
+set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk]
+set_property PACKAGE_PIN W19 [get_ports ft601_clk]
+
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n]
+set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n]
+
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}]
+set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg]
+set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]]
+
+set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}]
+set_false_path -from [get_pins {tickcount64_reg[*]/C}]
+set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}]
+set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
+
+#PCIe signals
+set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells {i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property PACKAGE_PIN A13 [get_ports pcie_present]
+set_property PACKAGE_PIN B13 [get_ports pcie_perst_n]
+set_property PACKAGE_PIN A14 [get_ports pcie_wake_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_present]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n]
+set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n]
+
+set_property PACKAGE_PIN A10 [get_ports {pcie_rx_n[0]}]
+set_property PACKAGE_PIN B10 [get_ports {pcie_rx_p[0]}]
+set_property PACKAGE_PIN A6  [get_ports {pcie_tx_n[0]}]
+set_property PACKAGE_PIN B6  [get_ports {pcie_tx_p[0]}]
+
+set_property PACKAGE_PIN E6  [get_ports pcie_clk_n]
+set_property PACKAGE_PIN F6  [get_ports pcie_clk_p]
+
+create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p]
+
+set_property CFGBVS Vcco [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

JOKOSAHS_DMA-Pcileech/src/pcileech_squirrel_top.sv

@@ -0,0 +1,166 @@
+//
+// PCILeech FPGA.
+//
+// Top module for various 35T-484 x1 Artix-7 boards.
+//
+// (c) Ulf Frisk, 2019-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_squirrel_top #(
+    parameter       PARAM_DEVICE_ID = 4,
+    parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
+    parameter       PARAM_VERSION_NUMBER_MINOR = 13,
+    parameter       PARAM_CUSTOM_VALUE = 32'hffffffff
+) (
+    // SYS
+    input           clk,
+    input           ft601_clk,
+    
+    // SYSTEM LEDs and BUTTONs
+    output          user_ld1,
+    output          user_ld2,
+    input           user_sw1_n,
+    input           user_sw2_n,
+    
+    output          ft2232_rst_n,
+    
+    // PCI-E FABRIC
+    output  [0:0]   pcie_tx_p,
+    output  [0:0]   pcie_tx_n,
+    input   [0:0]   pcie_rx_p,
+    input   [0:0]   pcie_rx_n,
+    input           pcie_clk_p,
+    input           pcie_clk_n,
+    input           pcie_present,
+    input           pcie_perst_n,
+    output reg      pcie_wake_n = 1'b1,
+    
+    // TO/FROM FT601 PADS
+    output          ft601_rst_n,
+    inout   [31:0]  ft601_data,
+    output  [3:0]   ft601_be,
+    input           ft601_rxf_n,
+    input           ft601_txe_n,
+    output          ft601_wr_n,
+    output          ft601_siwu_n,
+    output          ft601_rd_n,
+    output          ft601_oe_n
+    );
+    
+    // SYS
+    wire            rst;
+    
+    // FIFO CTL <--> COM CTL
+    wire [63:0]     com_dout;
+    wire            com_dout_valid;
+    wire [255:0]    com_din;
+    wire            com_din_wr_en;
+    wire            com_din_ready;
+    wire            led_com;
+    wire            led_pcie;
+    
+    // FIFO CTL <--> COM CTL
+    IfComToFifo     dcom_fifo();
+	
+    // FIFO CTL <--> PCIe
+    IfPCIeFifoCfg   dcfg();
+    IfPCIeFifoTlp   dtlp();
+    IfPCIeFifoCore  dpcie();
+    IfShadow2Fifo   dshadow2fifo();
+	
+    // ----------------------------------------------------
+    // TickCount64 CLK
+    // ----------------------------------------------------
+
+    time tickcount64 = 0;
+    time tickcount64_reload = 0;
+    always @ ( posedge clk ) begin
+        tickcount64         <= user_sw2_n ? (tickcount64 + 1) : 0;
+        tickcount64_reload  <= user_sw2_n ? 0 : (tickcount64_reload + 1);
+    end
+
+    assign rst = ~user_sw2_n || ((tickcount64 < 64) ? 1'b1 : 1'b0);
+    assign ft601_rst_n = ~rst;
+    wire led_pwronblink = ~user_sw1_n ^ (tickcount64[24] & (tickcount64[63:27] == 0));
+    
+    OBUF led_ld1_obuf(.O(user_ld1), .I(led_pcie));
+    OBUF led_ld2_obuf(.O(user_ld2), .I(led_com));
+    OBUF ft2232_rst_obuf(.O(ft2232_rst_n), .I(user_sw2_n));
+    
+    // ----------------------------------------------------
+    // BUFFERED COMMUNICATION DEVICE (FT601)
+    // ----------------------------------------------------
+    
+    pcileech_com i_pcileech_com (
+        // SYS
+        .clk                ( clk                   ),
+        .clk_com            ( ft601_clk             ),
+        .rst                ( rst                   ),
+        .led_state_txdata   ( led_com               ),  // ->
+        .led_state_invert   ( led_pwronblink        ),  // <-
+        // FIFO CTL <--> COM CTL
+        .dfifo              ( dcom_fifo.mp_com      ),
+        // TO/FROM FT601 PADS
+        .ft601_data         ( ft601_data            ),  // <> [31:0]
+        .ft601_be           ( ft601_be              ),  // -> [3:0]
+        .ft601_txe_n        ( ft601_txe_n           ),  // <-
+        .ft601_rxf_n        ( ft601_rxf_n           ),  // <-
+        .ft601_siwu_n       ( ft601_siwu_n          ),  // ->
+        .ft601_wr_n         ( ft601_wr_n            ),  // ->
+        .ft601_rd_n         ( ft601_rd_n            ),  // ->
+        .ft601_oe_n         ( ft601_oe_n            )   // ->
+    );
+    
+    // ----------------------------------------------------
+    // FIFO CTL
+    // ----------------------------------------------------
+    
+    pcileech_fifo #(
+        .PARAM_DEVICE_ID            ( PARAM_DEVICE_ID               ),
+        .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR    ),
+        .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR    ),
+        .PARAM_CUSTOM_VALUE         ( PARAM_CUSTOM_VALUE            )
+    ) i_pcileech_fifo (
+        .clk                ( clk                   ),
+        .rst                ( rst                   ),
+        .rst_cfg_reload     ( (tickcount64_reload > 500000000) ? 1'b1 : 1'b0 ),     // config reload after 5s button press
+        .pcie_present       ( pcie_present          ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // FIFO CTL <--> COM CTL
+        .dcom               ( dcom_fifo.mp_fifo     ),
+        // FIFO CTL <--> PCIe
+        .dcfg               ( dcfg.mp_fifo          ),
+        .dtlp               ( dtlp.mp_fifo          ),
+        .dpcie              ( dpcie.mp_fifo         ),
+        .dshadow2fifo       ( dshadow2fifo.fifo     )
+    );
+    
+    // ----------------------------------------------------
+    // PCIe
+    // ----------------------------------------------------
+    
+    pcileech_pcie_a7 i_pcileech_pcie_a7(
+        .clk_sys            ( clk                   ),
+        .rst                ( rst                   ),
+        // PCIe fabric
+        .pcie_tx_p          ( pcie_tx_p             ),
+        .pcie_tx_n          ( pcie_tx_n             ),
+        .pcie_rx_p          ( pcie_rx_p             ),
+        .pcie_rx_n          ( pcie_rx_n             ),
+        .pcie_clk_p         ( pcie_clk_p            ),
+        .pcie_clk_n         ( pcie_clk_n            ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // State and Activity LEDs
+        .led_state          ( led_pcie              ),
+        // FIFO CTL <--> PCIe
+        .dfifo_cfg          ( dcfg.mp_pcie          ),
+        .dfifo_tlp          ( dtlp.mp_pcie          ),
+        .dfifo_pcie         ( dpcie.mp_pcie         ),
+        .dshadow2fifo       ( dshadow2fifo.shadow   )
+    );
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_tbx4_100t.xdc

@@ -0,0 +1,179 @@
+# SW
+set_property PACKAGE_PIN F21 [get_ports power_sw]
+set_property IOSTANDARD LVCMOS18 [get_ports power_sw]
+set_property PULLTYPE PULLUP [get_ports power_sw]
+
+# LED
+set_property PACKAGE_PIN AA5 [get_ports pcie_led]
+set_property IOSTANDARD LVCMOS18 [get_ports pcie_led]
+
+# SYSCLK
+set_property PACKAGE_PIN J19 [get_ports clk_in]
+set_property IOSTANDARD LVCMOS33 [get_ports clk_in]
+create_clock -period 8.000  [get_nets clk]
+
+#BUS DO
+set_property PACKAGE_PIN A21 [get_ports {BUS_DO[0]}]
+set_property PACKAGE_PIN A20 [get_ports {BUS_DO[1]}]
+set_property PACKAGE_PIN A19 [get_ports {BUS_DO[2]}]
+set_property PACKAGE_PIN A18 [get_ports {BUS_DO[3]}]
+set_property PACKAGE_PIN A16 [get_ports {BUS_DO[4]}]
+set_property PACKAGE_PIN A15 [get_ports {BUS_DO[5]}]
+set_property PACKAGE_PIN A14 [get_ports {BUS_DO[6]}]
+set_property PACKAGE_PIN A13 [get_ports {BUS_DO[7]}]
+set_property PACKAGE_PIN B22 [get_ports {BUS_DO[8]}]
+set_property PACKAGE_PIN B21 [get_ports {BUS_DO[9]}]
+set_property PACKAGE_PIN B20 [get_ports {BUS_DO[10]}]
+set_property PACKAGE_PIN B18 [get_ports {BUS_DO[11]}]
+set_property PACKAGE_PIN B17 [get_ports {BUS_DO[12]}]
+set_property PACKAGE_PIN B16 [get_ports {BUS_DO[13]}]
+set_property PACKAGE_PIN B15 [get_ports {BUS_DO[14]}]
+set_property PACKAGE_PIN B13 [get_ports {BUS_DO[15]}]
+set_property PACKAGE_PIN C22 [get_ports {BUS_DO[16]}]
+set_property PACKAGE_PIN C20 [get_ports {BUS_DO[17]}]
+set_property PACKAGE_PIN C19 [get_ports {BUS_DO[18]}]
+set_property PACKAGE_PIN C18 [get_ports {BUS_DO[19]}]
+set_property PACKAGE_PIN V7  [get_ports {BUS_DO[20]}]
+set_property PACKAGE_PIN Y4  [get_ports {BUS_DO[21]}]
+set_property PACKAGE_PIN AA4 [get_ports {BUS_DO[22]}]
+set_property PACKAGE_PIN V4  [get_ports {BUS_DO[23]}]
+set_property PACKAGE_PIN W4  [get_ports {BUS_DO[24]}]
+set_property PACKAGE_PIN R4  [get_ports {BUS_DO[25]}]
+set_property PACKAGE_PIN T4  [get_ports {BUS_DO[26]}]
+set_property PACKAGE_PIN T5  [get_ports {BUS_DO[27]}]
+set_property PACKAGE_PIN U5  [get_ports {BUS_DO[28]}]
+set_property PACKAGE_PIN W6  [get_ports {BUS_DO[29]}]
+set_property PACKAGE_PIN W5  [get_ports {BUS_DO[30]}]
+set_property PACKAGE_PIN U6  [get_ports {BUS_DO[31]}]
+set_property PACKAGE_PIN V5  [get_ports {BUS_DO[32]}]
+set_property PACKAGE_PIN R6  [get_ports {BUS_DO[33]}]
+set_property PACKAGE_PIN T6  [get_ports {BUS_DO[34]}]
+set_property PACKAGE_PIN Y6  [get_ports {BUS_DO[35]}]
+set_property PACKAGE_PIN AA6 [get_ports {BUS_DO[36]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {BUS_DO[*]}]
+
+#BUS DI
+set_property PACKAGE_PIN F4  [get_ports {BUS_DI[0]}]
+set_property PACKAGE_PIN B1  [get_ports {BUS_DI[1]}]
+set_property PACKAGE_PIN A1  [get_ports {BUS_DI[2]}]
+set_property PACKAGE_PIN C2  [get_ports {BUS_DI[3]}]
+set_property PACKAGE_PIN B2  [get_ports {BUS_DI[4]}]
+set_property PACKAGE_PIN E1  [get_ports {BUS_DI[5]}]
+set_property PACKAGE_PIN D1  [get_ports {BUS_DI[6]}]
+set_property PACKAGE_PIN E2  [get_ports {BUS_DI[7]}]
+set_property PACKAGE_PIN D2  [get_ports {BUS_DI[8]}]
+set_property PACKAGE_PIN G1  [get_ports {BUS_DI[9]}]
+set_property PACKAGE_PIN F1  [get_ports {BUS_DI[10]}]
+set_property PACKAGE_PIN F3  [get_ports {BUS_DI[11]}]
+set_property PACKAGE_PIN E3  [get_ports {BUS_DI[12]}]
+set_property PACKAGE_PIN K1  [get_ports {BUS_DI[13]}]
+set_property PACKAGE_PIN J1  [get_ports {BUS_DI[14]}]
+set_property PACKAGE_PIN H2  [get_ports {BUS_DI[15]}]
+set_property PACKAGE_PIN G2  [get_ports {BUS_DI[16]}]
+set_property PACKAGE_PIN K2  [get_ports {BUS_DI[17]}]
+set_property PACKAGE_PIN J2  [get_ports {BUS_DI[18]}]
+set_property PACKAGE_PIN J5  [get_ports {BUS_DI[19]}]
+set_property PACKAGE_PIN H5  [get_ports {BUS_DI[20]}]
+set_property PACKAGE_PIN H3  [get_ports {BUS_DI[21]}]
+set_property PACKAGE_PIN G3  [get_ports {BUS_DI[22]}]
+set_property PACKAGE_PIN H4  [get_ports {BUS_DI[23]}]
+set_property PACKAGE_PIN G4  [get_ports {BUS_DI[24]}]
+set_property PACKAGE_PIN K4  [get_ports {BUS_DI[25]}]
+set_property PACKAGE_PIN J4  [get_ports {BUS_DI[26]}]
+set_property PACKAGE_PIN L3  [get_ports {BUS_DI[27]}]
+set_property PACKAGE_PIN K3  [get_ports {BUS_DI[28]}]
+set_property PACKAGE_PIN M1  [get_ports {BUS_DI[29]}]
+set_property PACKAGE_PIN L1  [get_ports {BUS_DI[30]}]
+set_property PACKAGE_PIN M3  [get_ports {BUS_DI[31]}]
+set_property PACKAGE_PIN M2  [get_ports {BUS_DI[32]}]
+set_property PACKAGE_PIN K6  [get_ports {BUS_DI[33]}]
+set_property PACKAGE_PIN J6  [get_ports {BUS_DI[34]}]
+set_property PACKAGE_PIN L5  [get_ports {BUS_DI[35]}]
+set_property PACKAGE_PIN L4  [get_ports {BUS_DI[36]}]
+set_property PACKAGE_PIN N4  [get_ports {BUS_DI[37]}]
+set_property PACKAGE_PIN N3  [get_ports {BUS_DI[38]}]
+set_property PACKAGE_PIN R1  [get_ports {BUS_DI[39]}]
+set_property PACKAGE_PIN P1  [get_ports {BUS_DI[40]}]
+set_property PACKAGE_PIN P5  [get_ports {BUS_DI[41]}]
+set_property PACKAGE_PIN P4  [get_ports {BUS_DI[42]}]
+set_property PACKAGE_PIN P2  [get_ports {BUS_DI[43]}]
+set_property PACKAGE_PIN N2  [get_ports {BUS_DI[44]}]
+set_property PACKAGE_PIN M6  [get_ports {BUS_DI[45]}]
+set_property PACKAGE_PIN M5  [get_ports {BUS_DI[46]}]
+set_property PACKAGE_PIN P6  [get_ports {BUS_DI[47]}]
+set_property PACKAGE_PIN N5  [get_ports {BUS_DI[48]}]
+set_property PACKAGE_PIN L6  [get_ports {BUS_DI[49]}]
+set_property PACKAGE_PIN T3  [get_ports {BUS_DI[50]}]
+set_property PACKAGE_PIN T1  [get_ports {BUS_DI[51]}]
+set_property PACKAGE_PIN U1  [get_ports {BUS_DI[52]}]
+set_property PACKAGE_PIN U2  [get_ports {BUS_DI[53]}]
+set_property PACKAGE_PIN V2  [get_ports {BUS_DI[54]}]
+set_property PACKAGE_PIN R3  [get_ports {BUS_DI[55]}]
+set_property PACKAGE_PIN R2  [get_ports {BUS_DI[56]}]
+set_property PACKAGE_PIN W2  [get_ports {BUS_DI[57]}]
+set_property PACKAGE_PIN Y2  [get_ports {BUS_DI[58]}]
+set_property PACKAGE_PIN W1  [get_ports {BUS_DI[59]}]
+set_property PACKAGE_PIN Y1  [get_ports {BUS_DI[60]}]
+set_property PACKAGE_PIN U3  [get_ports {BUS_DI[61]}]
+set_property PACKAGE_PIN V3  [get_ports {BUS_DI[62]}]
+set_property PACKAGE_PIN AA1 [get_ports {BUS_DI[63]}]
+set_property PACKAGE_PIN AB1 [get_ports {BUS_DI[64]}]
+set_property PACKAGE_PIN AB3 [get_ports {BUS_DI[65]}]
+set_property PACKAGE_PIN AB2 [get_ports {BUS_DI[66]}]
+set_property PACKAGE_PIN Y3  [get_ports {BUS_DI[67]}]
+set_property PACKAGE_PIN AA3 [get_ports {BUS_DI[68]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {BUS_DI[*]}]
+
+set_property PACKAGE_PIN AB6 [get_ports BUS_DI_PROG_FULL]
+set_property IOSTANDARD LVCMOS18 [get_ports BUS_DI_PROG_FULL]
+
+#TIMING FALSE PATHS
+set_false_path -from [get_pins {tickcount64_reg[*]/C}]
+set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}]
+set_false_path -from [get_pins i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}]
+set_false_path -from [get_pins i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/user_reset_out_reg/C]
+
+#PCIe signals
+set_property PACKAGE_PIN J14  [get_ports pcie_present1]
+set_property PACKAGE_PIN AB16 [get_ports pcie_present2]
+set_property PACKAGE_PIN J22  [get_ports pcie_perst1_n]
+set_property PACKAGE_PIN AB10 [get_ports pcie_perst2_n]
+set_property IOSTANDARD LVCMOS33 [get_ports {pcie_present1 pcie_present2 pcie_perst1_n pcie_perst2_n}]
+set_property PULLTYPE PULLUP [get_ports {pcie_present1 pcie_present2 pcie_perst1_n pcie_perst2_n}]
+
+set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+
+set_property PACKAGE_PIN A8  [get_ports pcie_rx_n[0]]
+set_property PACKAGE_PIN B8  [get_ports pcie_rx_p[0]]
+set_property PACKAGE_PIN A4  [get_ports pcie_tx_n[0]]
+set_property PACKAGE_PIN B4  [get_ports pcie_tx_p[0]]
+
+set_property PACKAGE_PIN C11 [get_ports pcie_rx_n[1]]
+set_property PACKAGE_PIN D11 [get_ports pcie_rx_p[1]]
+set_property PACKAGE_PIN C5  [get_ports pcie_tx_n[1]]
+set_property PACKAGE_PIN D5  [get_ports pcie_tx_p[1]]
+
+set_property PACKAGE_PIN A10 [get_ports pcie_rx_n[2]]
+set_property PACKAGE_PIN B10 [get_ports pcie_rx_p[2]]
+set_property PACKAGE_PIN A6  [get_ports pcie_tx_n[2]]
+set_property PACKAGE_PIN B6  [get_ports pcie_tx_p[2]]
+
+set_property PACKAGE_PIN C9  [get_ports pcie_rx_n[3]]
+set_property PACKAGE_PIN D9  [get_ports pcie_rx_p[3]]
+set_property PACKAGE_PIN C7  [get_ports pcie_tx_n[3]]
+set_property PACKAGE_PIN D7  [get_ports pcie_tx_p[3]]
+
+set_property PACKAGE_PIN F10 [get_ports pcie_clk_p]
+set_property PACKAGE_PIN E10 [get_ports pcie_clk_n]
+create_clock -period 10.000 -name pcie_sys_clk_p [get_nets pcie_clk_p]
+
+#GENRAL CONFIG
+set_property CFGBVS Vcco [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]

JOKOSAHS_DMA-Pcileech/src/pcileech_tbx4_100t_top.sv

@@ -0,0 +1,184 @@
+//
+// PCILeech FPGA.
+//
+// Top module for PCILeech TB x4
+//
+// (c) Ulf Frisk, 2019-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_tbx4_100t_top #(
+    // DEVICE IDs as follows:
+    parameter       PARAM_DEVICE_ID = 17,
+    parameter       PARAM_VERSION_NUMBER_MAJOR = 4,
+    parameter       PARAM_VERSION_NUMBER_MINOR = 15,
+    parameter       PARAM_CUSTOM_VALUE = 32'hffffffff,
+    parameter       POWER_SW_MODE = 0,                 // disable_pcie_on_thunderbolt_noconnect_not_enabled(0), disable_pcie_on_thunderbolt_noconnect_enabled(1)
+    parameter       POWER_SW_TIME = 60*125_000_000     // detection sample time in ticks of 125MHz (125M=1s)
+) (
+    // SYS
+    input           clk_in,
+    
+    // SYSTEM LEDs and BUTTONs
+    output          pcie_led,
+    input           power_sw,
+    
+    // TO/FROM FPGA IO BRIDGE
+    input   [36:0]  BUS_DO,
+    output  [68:0]  BUS_DI,
+    input           BUS_DI_PROG_FULL,
+    
+    // PCI-E FABRIC
+    output  [3:0]   pcie_tx_p,
+    output  [3:0]   pcie_tx_n,
+    input   [3:0]   pcie_rx_p,
+    input   [3:0]   pcie_rx_n,
+    input           pcie_clk_p,
+    input           pcie_clk_n,
+    input           pcie_present1,
+    input           pcie_present2,
+	input           pcie_perst1_n,
+	input           pcie_perst2_n
+    );
+
+    // SYS
+    wire rst;
+    wire clk;
+    wire clk_com;
+    reg  rst_sw = 0;
+    
+    // FIFO CTL <--> COM CTL
+    wire [63:0]     com_dout;
+    wire            com_dout_valid;
+    wire [255:0]    com_din;
+    wire            com_din_wr_en;
+    wire            com_din_ready;
+    
+    // FIFO CTL <--> COM CTL
+    IfComToFifo     dcom_fifo();
+	
+    // FIFO CTL <--> PCIe
+    IfPCIeFifoCfg   dcfg();
+    IfPCIeFifoTlp   dtlp();
+    IfPCIeFifoCore  dpcie();
+    IfShadow2Fifo   dshadow2fifo();
+    
+    // PCIe
+    wire pcie_present = pcie_present1 && pcie_present2;
+    wire pcie_perst_n = pcie_perst1_n && pcie_perst2_n && ~rst_sw;
+    
+    // ----------------------------------------------------
+    // CLK: INPUT (clkin): 50MHz
+    //      COM (clk_com): 250MHz
+    //      SYS (clk):     125MHz
+    // ----------------------------------------------------
+
+    wire clk_locked, clk_out1, clk_out2;
+    clk_wiz_0 i_clk_wiz_0(
+        .clk_in1    ( clk_in        ),  // <- 50MHz
+        .clk_out1   ( clk_out1      ),  // -> 250MHz
+        .clk_out2   ( clk_out2      ),  // -> 125MHz
+        .locked     ( clk_locked    )
+    );
+    
+    BUFG i_BUFG_1 ( .I( clk_locked ? clk_out1 : clk_in ), .O( clk_com ) );
+    BUFG i_BUFG_2 ( .I( clk_locked ? clk_out2 : clk_in ), .O( clk ) );
+    
+    // ----------------------------------------------------
+    // TickCount64 CLK
+    // ----------------------------------------------------
+
+    time tickcount64 = 0;
+    always @ ( posedge clk )
+        tickcount64 <= tickcount64 + 1;
+    assign rst = (tickcount64 < 64) ? 1'b1 : 1'b0;
+    
+    wire            led_pcie;
+    OBUF led_ld1_obuf(.O(pcie_led), .I(led_pcie));
+	
+    // ----------------------------------------------------
+    // POWER SWITCH MODE (DISABLE PCIE WHEN THUNDERBOLT NOT CONNECTED)
+    // ----------------------------------------------------
+	
+    always @ ( posedge clk ) begin
+        if ( rst ) begin
+            rst_sw    <= 0;
+        end
+        else if ( (POWER_SW_MODE == 1) && (tickcount64 == POWER_SW_TIME) ) begin
+            rst_sw    <= ~power_sw; 
+        end
+    end
+	
+    // ----------------------------------------------------
+    // BUFFERED COMMUNICATION DEVICE (FPGA IO BRIDGE)
+    // ----------------------------------------------------
+    
+    pcileech_com i_pcileech_com (
+        // SYS
+        .clk                ( clk                   ),
+        .clk_com            ( clk_com               ),
+        .rst                ( rst                   ),
+        // TO/FROM FPGA IO BRIDGE
+        .BUS_DO             ( BUS_DO                ),
+        .BUS_DI             ( BUS_DI                ),
+        .BUS_DI_PROG_FULL   ( BUS_DI_PROG_FULL      ),
+        // FIFO CTL <--> COM CTL
+        .com_dout           ( dcom_fifo.com_dout        ),
+        .com_dout_valid     ( dcom_fifo.com_dout_valid  ),
+        .com_din_ready      ( dcom_fifo.com_din_ready   ),
+        .com_din            ( dcom_fifo.com_din         ),
+        .com_din_wr_en      ( dcom_fifo.com_din_wr_en   )
+    );
+    
+    // ----------------------------------------------------
+    // FIFO CTL
+    // ----------------------------------------------------
+    
+    pcileech_fifo #(
+        .PARAM_DEVICE_ID            ( PARAM_DEVICE_ID               ),
+        .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR    ),
+        .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR    ),
+        .PARAM_CUSTOM_VALUE         ( PARAM_CUSTOM_VALUE            )
+    ) i_pcileech_fifo (
+        .clk                ( clk                   ),
+        .rst                ( rst                   ),
+        .rst_cfg_reload     ( 1'b0                  ),
+        .pcie_present       ( pcie_present          ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // FIFO CTL <--> COM CTL
+        .dcom               ( dcom_fifo.mp_fifo     ),
+        // FIFO CTL <--> PCIe
+        .dcfg               ( dcfg.mp_fifo          ),
+        .dtlp               ( dtlp.mp_fifo          ),
+        .dpcie              ( dpcie.mp_fifo         ),
+        .dshadow2fifo       ( dshadow2fifo.fifo     )
+    );
+    
+    // ----------------------------------------------------
+    // PCIe
+    // ----------------------------------------------------
+    
+    pcileech_pcie_a7x4 i_pcileech_pcie_a7x4(
+        .clk_sys            ( clk                   ),
+        .rst                ( rst                   ),
+        // PCIe fabric
+        .pcie_tx_p          ( pcie_tx_p             ),
+        .pcie_tx_n          ( pcie_tx_n             ),
+        .pcie_rx_p          ( pcie_rx_p             ),
+        .pcie_rx_n          ( pcie_rx_n             ),
+        .pcie_clk_p         ( pcie_clk_p            ),
+        .pcie_clk_n         ( pcie_clk_n            ),
+        .pcie_perst_n       ( pcie_perst_n          ),
+        // State and Activity LEDs
+        .led_state          ( led_pcie              ),
+        // FIFO CTL <--> PCIe
+        .dfifo_cfg          ( dcfg.mp_pcie          ),
+        .dfifo_tlp          ( dtlp.mp_pcie          ),
+        .dfifo_pcie         ( dpcie.mp_pcie         ),
+        .dshadow2fifo       ( dshadow2fifo.shadow   )
+    );
+
+endmodule

JOKOSAHS_DMA-Pcileech/src/pcileech_tlps128_bar_controller.sv

@@ -0,0 +1,908 @@
+//
+// PCILeech FPGA.
+//
+// PCIe BAR PIO controller.
+//
+// The PCILeech BAR PIO controller allows for easy user-implementation on top
+// of the PCILeech AXIS128 PCIe TLP streaming interface.
+// The controller consists of a read engine and a write engine and pluggable
+// user-implemented PCIe BAR implementations (found at bottom of the file).
+//
+// Considerations:
+// - The core handles 1 DWORD read + 1 DWORD write per CLK max. If a lot of
+//   data is written / read from the TLP streaming interface the core may
+//   drop packet silently.
+// - The core reads 1 DWORD of data (without byte enable) per CLK.
+// - The core writes 1 DWORD of data (with byte enable) per CLK.
+// - All user-implemented cores must have the same latency in CLKs for the
+//   returned read data or else undefined behavior will take place.
+// - 32-bit addresses are passed for read/writes. Larger BARs than 4GB are
+//   not supported due to addressing constraints. Lower bits (LSBs) are the
+//   BAR offset, Higher bits (MSBs) are the 32-bit base address of the BAR.
+// - DO NOT edit read/write engines.
+// - DO edit pcileech_tlps128_bar_controller (to swap bar implementations).
+// - DO edit the bar implementations (at bottom of the file, if neccessary).
+//
+// Example implementations exists below, swap out any of the example cores
+// against a core of your use case, or modify existing cores.
+// Following test cores exist (see below in this file):
+// - pcileech_bar_impl_zerowrite4k = zero-initialized read/write BAR.
+//     It's possible to modify contents by use of .coe file.
+// - pcileech_bar_impl_loopaddr = test core that loops back the 32-bit
+//     address of the current read. Does not support writes.
+// - pcileech_bar_impl_none = core without any reply.
+// 
+// (c) Ulf Frisk, 2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+`include "pcileech_header.svh"
+
+module pcileech_tlps128_bar_controller(
+    input                   rst,
+    input                   clk,
+    input                   bar_en,
+    input [15:0]            pcie_id,
+    input [31:0]            base_address_register,
+    IfAXIS128.sink_lite     tlps_in,
+    IfAXIS128.source        tlps_out
+);
+    
+    // ------------------------------------------------------------------------
+    // 1: TLP RECEIVE:
+    // Receive incoming BAR requests from the TLP stream:
+    // send them onwards to read and write FIFOs
+    // ------------------------------------------------------------------------
+    wire in_is_wr_ready;
+    bit  in_is_wr_last;
+    wire in_is_first    = tlps_in.tuser[0];
+    wire in_is_bar      = bar_en && (tlps_in.tuser[8:2] != 0);
+    wire in_is_rd       = (in_is_first && tlps_in.tlast && ((tlps_in.tdata[31:25] == 7'b0000000) || (tlps_in.tdata[31:25] == 7'b0010000) || (tlps_in.tdata[31:24] == 8'b00000010)));
+    wire in_is_wr       = in_is_wr_last || (in_is_first && in_is_wr_ready && ((tlps_in.tdata[31:25] == 7'b0100000) || (tlps_in.tdata[31:25] == 7'b0110000) || (tlps_in.tdata[31:24] == 8'b01000010)));
+    
+    always @ ( posedge clk )
+        if ( rst ) begin
+            in_is_wr_last <= 0;
+        end
+        else if ( tlps_in.tvalid ) begin
+            in_is_wr_last <= !tlps_in.tlast && in_is_wr;
+        end
+    
+    wire [6:0]  wr_bar;
+    wire [31:0] wr_addr;
+    wire [3:0]  wr_be;
+    wire [31:0] wr_data;
+    wire        wr_valid;
+    wire [87:0] rd_req_ctx;
+    wire [6:0]  rd_req_bar;
+    wire [31:0] rd_req_addr;
+    wire        rd_req_valid;
+    wire [87:0] rd_rsp_ctx;
+    wire [31:0] rd_rsp_data;
+    wire        rd_rsp_valid;
+        
+    pcileech_tlps128_bar_rdengine i_pcileech_tlps128_bar_rdengine(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        // TLPs:
+        .pcie_id        ( pcie_id                       ),
+        .tlps_in        ( tlps_in                       ),
+        .tlps_in_valid  ( tlps_in.tvalid && in_is_bar && in_is_rd ),
+        .tlps_out       ( tlps_out                      ),
+        // BAR reads:
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_bar     ( rd_req_bar                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid                  ),
+        .rd_rsp_ctx     ( rd_rsp_ctx                    ),
+        .rd_rsp_data    ( rd_rsp_data                   ),
+        .rd_rsp_valid   ( rd_rsp_valid                  )
+    );
+
+    pcileech_tlps128_bar_wrengine i_pcileech_tlps128_bar_wrengine(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        // TLPs:
+        .tlps_in        ( tlps_in                       ),
+        .tlps_in_valid  ( tlps_in.tvalid && in_is_bar && in_is_wr ),
+        .tlps_in_ready  ( in_is_wr_ready                ),
+        // outgoing BAR writes:
+        .wr_bar         ( wr_bar                        ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid                      )
+    );
+    
+    wire [87:0] bar_rsp_ctx[7];
+    wire [31:0] bar_rsp_data[7];
+    wire        bar_rsp_valid[7];
+    
+    assign rd_rsp_ctx = bar_rsp_valid[0] ? bar_rsp_ctx[0] :
+                        bar_rsp_valid[1] ? bar_rsp_ctx[1] :
+                        bar_rsp_valid[2] ? bar_rsp_ctx[2] :
+                        bar_rsp_valid[3] ? bar_rsp_ctx[3] :
+                        bar_rsp_valid[4] ? bar_rsp_ctx[4] :
+                        bar_rsp_valid[5] ? bar_rsp_ctx[5] :
+                        bar_rsp_valid[6] ? bar_rsp_ctx[6] : 0;
+    assign rd_rsp_data = bar_rsp_valid[0] ? bar_rsp_data[0] :
+                        bar_rsp_valid[1] ? bar_rsp_data[1] :
+                        bar_rsp_valid[2] ? bar_rsp_data[2] :
+                        bar_rsp_valid[3] ? bar_rsp_data[3] :
+                        bar_rsp_valid[4] ? bar_rsp_data[4] :
+                        bar_rsp_valid[5] ? bar_rsp_data[5] :
+                        bar_rsp_valid[6] ? bar_rsp_data[6] : 0;
+    assign rd_rsp_valid = bar_rsp_valid[0] || bar_rsp_valid[1] || bar_rsp_valid[2] || bar_rsp_valid[3] || bar_rsp_valid[4] || bar_rsp_valid[5] || bar_rsp_valid[6];
+    
+    pcileech_bar_impl_ar9287_wifi i_bar0(
+        .rst                   ( rst                           ),
+        .clk                   ( clk                           ),
+        .wr_addr               ( wr_addr                       ),
+        .wr_be                 ( wr_be                         ),
+        .wr_data               ( wr_data                       ),
+        .wr_valid              ( wr_valid && wr_bar[0]         ),
+        .rd_req_ctx            ( rd_req_ctx                    ),
+        .rd_req_addr           ( rd_req_addr                   ),
+        .rd_req_valid          ( rd_req_valid && rd_req_bar[0] ),
+        .base_address_register ( base_address_register         ),
+        .rd_rsp_ctx            ( bar_rsp_ctx[0]                ),
+        .rd_rsp_data           ( bar_rsp_data[0]               ),
+        .rd_rsp_valid          ( bar_rsp_valid[0]              )
+    );
+    
+    pcileech_bar_impl_loopaddr i_bar1(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid && wr_bar[1]         ),
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid && rd_req_bar[1] ),
+        .rd_rsp_ctx     ( bar_rsp_ctx[1]                ),
+        .rd_rsp_data    ( bar_rsp_data[1]               ),
+        .rd_rsp_valid   ( bar_rsp_valid[1]              )
+    );
+    
+    pcileech_bar_impl_none i_bar2(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid && wr_bar[2]         ),
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid && rd_req_bar[2] ),
+        .rd_rsp_ctx     ( bar_rsp_ctx[2]                ),
+        .rd_rsp_data    ( bar_rsp_data[2]               ),
+        .rd_rsp_valid   ( bar_rsp_valid[2]              )
+    );
+    
+    pcileech_bar_impl_none i_bar3(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid && wr_bar[3]         ),
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid && rd_req_bar[3] ),
+        .rd_rsp_ctx     ( bar_rsp_ctx[3]                ),
+        .rd_rsp_data    ( bar_rsp_data[3]               ),
+        .rd_rsp_valid   ( bar_rsp_valid[3]              )
+    );
+    
+    pcileech_bar_impl_none i_bar4(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid && wr_bar[4]         ),
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid && rd_req_bar[4] ),
+        .rd_rsp_ctx     ( bar_rsp_ctx[4]                ),
+        .rd_rsp_data    ( bar_rsp_data[4]               ),
+        .rd_rsp_valid   ( bar_rsp_valid[4]              )
+    );
+    
+    pcileech_bar_impl_none i_bar5(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid && wr_bar[5]         ),
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid && rd_req_bar[5] ),
+        .rd_rsp_ctx     ( bar_rsp_ctx[5]                ),
+        .rd_rsp_data    ( bar_rsp_data[5]               ),
+        .rd_rsp_valid   ( bar_rsp_valid[5]              )
+    );
+    
+    pcileech_bar_impl_none i_bar6_optrom(
+        .rst            ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_addr        ( wr_addr                       ),
+        .wr_be          ( wr_be                         ),
+        .wr_data        ( wr_data                       ),
+        .wr_valid       ( wr_valid && wr_bar[6]         ),
+        .rd_req_ctx     ( rd_req_ctx                    ),
+        .rd_req_addr    ( rd_req_addr                   ),
+        .rd_req_valid   ( rd_req_valid && rd_req_bar[6] ),
+        .rd_rsp_ctx     ( bar_rsp_ctx[6]                ),
+        .rd_rsp_data    ( bar_rsp_data[6]               ),
+        .rd_rsp_valid   ( bar_rsp_valid[6]              )
+    );
+
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// BAR WRITE ENGINE:
+// Receives BAR WRITE TLPs and output BAR WRITE requests.
+// Holds a 2048-byte buffer.
+// Input flow rate is 16bytes/CLK (max).
+// Output flow rate is 4bytes/CLK.
+// If write engine overflows incoming TLP is completely discarded silently.
+// ------------------------------------------------------------------------
+module pcileech_tlps128_bar_wrengine(
+    input                   rst,    
+    input                   clk,
+    // TLPs:
+    IfAXIS128.sink_lite     tlps_in,
+    input                   tlps_in_valid,
+    output                  tlps_in_ready,
+    // outgoing BAR writes:
+    output bit [6:0]        wr_bar,
+    output bit [31:0]       wr_addr,
+    output bit [3:0]        wr_be,
+    output bit [31:0]       wr_data,
+    output bit              wr_valid
+);
+
+    wire            f_rd_en;
+    wire [127:0]    f_tdata;
+    wire [3:0]      f_tkeepdw;
+    wire [8:0]      f_tuser;
+    wire            f_tvalid;
+    
+    bit [127:0]     tdata;
+    bit [3:0]       tkeepdw;
+    bit             tlast;
+    
+    bit [3:0]       be_first;
+    bit [3:0]       be_last;
+    bit             first_dw;
+    bit [31:0]      addr;
+
+    fifo_141_141_clk1_bar_wr i_fifo_141_141_clk1_bar_wr(
+        .srst           ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_en          ( tlps_in_valid                 ),
+        .din            ( {tlps_in.tuser[8:0], tlps_in.tkeepdw, tlps_in.tdata} ),
+        .full           (                               ),
+        .prog_empty     ( tlps_in_ready                 ),
+        .rd_en          ( f_rd_en                       ),
+        .dout           ( {f_tuser, f_tkeepdw, f_tdata} ),    
+        .empty          (                               ),
+        .valid          ( f_tvalid                      )
+    );
+    
+    // STATE MACHINE:
+    `define S_ENGINE_IDLE        3'h0
+    `define S_ENGINE_FIRST       3'h1
+    `define S_ENGINE_4DW_REQDATA 3'h2
+    `define S_ENGINE_TX0         3'h4
+    `define S_ENGINE_TX1         3'h5
+    `define S_ENGINE_TX2         3'h6
+    `define S_ENGINE_TX3         3'h7
+    (* KEEP = "TRUE" *) bit [3:0] state = `S_ENGINE_IDLE;
+    
+    assign f_rd_en = (state == `S_ENGINE_IDLE) ||
+                     (state == `S_ENGINE_4DW_REQDATA) ||
+                     (state == `S_ENGINE_TX3) ||
+                     ((state == `S_ENGINE_TX2 && !tkeepdw[3])) ||
+                     ((state == `S_ENGINE_TX1 && !tkeepdw[2])) ||
+                     ((state == `S_ENGINE_TX0 && !f_tkeepdw[1]));
+
+    always @ ( posedge clk ) begin
+        wr_addr     <= addr;
+        wr_valid    <= ((state == `S_ENGINE_TX0) && f_tvalid) || (state == `S_ENGINE_TX1) || (state == `S_ENGINE_TX2) || (state == `S_ENGINE_TX3);
+        
+    end
+
+    always @ ( posedge clk )
+        if ( rst ) begin
+            state <= `S_ENGINE_IDLE;
+        end
+        else case ( state )
+            `S_ENGINE_IDLE: begin
+                state   <= `S_ENGINE_FIRST;
+            end
+            `S_ENGINE_FIRST: begin
+                if ( f_tvalid && f_tuser[0] ) begin
+                    wr_bar      <= f_tuser[8:2];
+                    tdata       <= f_tdata;
+                    tkeepdw     <= f_tkeepdw;
+                    tlast       <= f_tuser[1];
+                    first_dw    <= 1;
+                    be_first    <= f_tdata[35:32];
+                    be_last     <= f_tdata[39:36];
+                    if ( f_tdata[31:29] == 8'b010 ) begin       // 3 DW header, with data
+                        addr    <= { f_tdata[95:66], 2'b00 };
+                        state   <= `S_ENGINE_TX3;
+                    end
+                    else if ( f_tdata[31:29] == 8'b011 ) begin  // 4 DW header, with data
+                        addr    <= { f_tdata[127:98], 2'b00 };
+                        state   <= `S_ENGINE_4DW_REQDATA;
+                    end 
+                end
+                else begin
+                    state   <= `S_ENGINE_IDLE;
+                end
+            end 
+            `S_ENGINE_4DW_REQDATA: begin
+                state   <= `S_ENGINE_TX0;
+            end
+            `S_ENGINE_TX0: begin
+                tdata       <= f_tdata;
+                tkeepdw     <= f_tkeepdw;
+                tlast       <= f_tuser[1];
+                addr        <= addr + 4;
+                wr_data     <= { f_tdata[0+00+:8], f_tdata[0+08+:8], f_tdata[0+16+:8], f_tdata[0+24+:8] };
+                first_dw    <= 0;
+                wr_be       <= first_dw ? be_first : (f_tkeepdw[1] ? 4'hf : be_last);
+                state       <= f_tvalid ? (f_tkeepdw[1] ? `S_ENGINE_TX1 : `S_ENGINE_FIRST) : `S_ENGINE_IDLE;
+            end
+            `S_ENGINE_TX1: begin
+                addr        <= addr + 4;
+                wr_data     <= { tdata[32+00+:8], tdata[32+08+:8], tdata[32+16+:8], tdata[32+24+:8] };
+                first_dw    <= 0;
+                wr_be       <= first_dw ? be_first : (tkeepdw[2] ? 4'hf : be_last);
+                state       <= tkeepdw[2] ? `S_ENGINE_TX2 : `S_ENGINE_FIRST;
+            end
+            `S_ENGINE_TX2: begin
+                addr        <= addr + 4;
+                wr_data     <= { tdata[64+00+:8], tdata[64+08+:8], tdata[64+16+:8], tdata[64+24+:8] };
+                first_dw    <= 0;
+                wr_be       <= first_dw ? be_first : (tkeepdw[3] ? 4'hf : be_last);
+                state       <= tkeepdw[3] ? `S_ENGINE_TX3 : `S_ENGINE_FIRST;
+            end
+            `S_ENGINE_TX3: begin
+                addr        <= addr + 4;
+                wr_data     <= { tdata[96+00+:8], tdata[96+08+:8], tdata[96+16+:8], tdata[96+24+:8] };
+                first_dw    <= 0;
+                wr_be       <= first_dw ? be_first : (!tlast ? 4'hf : be_last);
+                state       <= !tlast ? `S_ENGINE_TX0 : `S_ENGINE_FIRST;
+            end
+        endcase
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// BAR READ ENGINE:
+// Receives BAR READ TLPs and output BAR READ requests.
+// ------------------------------------------------------------------------
+module pcileech_tlps128_bar_rdengine(
+    input                   rst,    
+    input                   clk,
+    // TLPs:
+    input [15:0]            pcie_id,
+    IfAXIS128.sink_lite     tlps_in,
+    input                   tlps_in_valid,
+    IfAXIS128.source        tlps_out,
+    // BAR reads:
+    output [87:0]           rd_req_ctx,
+    output [6:0]            rd_req_bar,
+    output [31:0]           rd_req_addr,
+    output                  rd_req_valid,
+    input  [87:0]           rd_rsp_ctx,
+    input  [31:0]           rd_rsp_data,
+    input                   rd_rsp_valid
+);
+
+    // ------------------------------------------------------------------------
+    // 1: PROCESS AND QUEUE INCOMING READ TLPs:
+    // ------------------------------------------------------------------------
+    wire [10:0] rd1_in_dwlen    = (tlps_in.tdata[9:0] == 0) ? 11'd1024 : {1'b0, tlps_in.tdata[9:0]};
+    wire [6:0]  rd1_in_bar      = tlps_in.tuser[8:2];
+    wire [15:0] rd1_in_reqid    = tlps_in.tdata[63:48];
+    wire [7:0]  rd1_in_tag      = tlps_in.tdata[47:40];
+    wire [31:0] rd1_in_addr     = { ((tlps_in.tdata[31:29] == 3'b000) ? tlps_in.tdata[95:66] : tlps_in.tdata[127:98]), 2'b00 };
+    wire [73:0] rd1_in_data;
+    assign rd1_in_data[73:63]   = rd1_in_dwlen;
+    assign rd1_in_data[62:56]   = rd1_in_bar;   
+    assign rd1_in_data[55:48]   = rd1_in_tag;
+    assign rd1_in_data[47:32]   = rd1_in_reqid;
+    assign rd1_in_data[31:0]    = rd1_in_addr;
+    
+    wire        rd1_out_rden;
+    wire [73:0] rd1_out_data;
+    wire        rd1_out_valid;
+    
+    fifo_74_74_clk1_bar_rd1 i_fifo_74_74_clk1_bar_rd1(
+        .srst           ( rst                           ),
+        .clk            ( clk                           ),
+        .wr_en          ( tlps_in_valid                 ),
+        .din            ( rd1_in_data                   ),
+        .full           (                               ),
+        .rd_en          ( rd1_out_rden                  ),
+        .dout           ( rd1_out_data                  ),    
+        .empty          (                               ),
+        .valid          ( rd1_out_valid                 )
+    );
+    
+    // ------------------------------------------------------------------------
+    // 2: PROCESS AND SPLIT READ TLPs INTO RESPONSE TLP READ REQUESTS AND QUEUE:
+    //    (READ REQUESTS LARGER THAN 128-BYTES WILL BE SPLIT INTO MULTIPLE).
+    // ------------------------------------------------------------------------
+    
+    wire [10:0] rd1_out_dwlen       = rd1_out_data[73:63];
+    wire [4:0]  rd1_out_dwlen5      = rd1_out_data[67:63];
+    wire [4:0]  rd1_out_addr5       = rd1_out_data[6:2];
+    
+    // 1st "instant" packet:
+    wire [4:0]  rd2_pkt1_dwlen_pre  = ((rd1_out_addr5 + rd1_out_dwlen5 > 6'h20) || ((rd1_out_addr5 != 0) && (rd1_out_dwlen5 == 0))) ? (6'h20 - rd1_out_addr5) : rd1_out_dwlen5;
+    wire [5:0]  rd2_pkt1_dwlen      = (rd2_pkt1_dwlen_pre == 0) ? 6'h20 : rd2_pkt1_dwlen_pre;
+    wire [10:0] rd2_pkt1_dwlen_next = rd1_out_dwlen - rd2_pkt1_dwlen;
+    wire        rd2_pkt1_large      = (rd1_out_dwlen > 32) || (rd1_out_dwlen != rd2_pkt1_dwlen);
+    wire        rd2_pkt1_tiny       = (rd1_out_dwlen == 1);
+    wire [11:0] rd2_pkt1_bc         = rd1_out_dwlen << 2;
+    wire [85:0] rd2_pkt1;
+    assign      rd2_pkt1[85:74]     = rd2_pkt1_bc;
+    assign      rd2_pkt1[73:63]     = rd2_pkt1_dwlen;
+    assign      rd2_pkt1[62:0]      = rd1_out_data[62:0];
+    
+    // Nth packet (if split should take place):
+    bit  [10:0] rd2_total_dwlen;
+    wire [10:0] rd2_total_dwlen_next = rd2_total_dwlen - 11'h20;
+    
+    bit  [85:0] rd2_pkt2;
+    wire [10:0] rd2_pkt2_dwlen = rd2_pkt2[73:63];
+    wire        rd2_pkt2_large = (rd2_total_dwlen > 11'h20);
+    
+    wire        rd2_out_rden;
+    
+    // STATE MACHINE:
+    `define S2_ENGINE_REQDATA     1'h0
+    `define S2_ENGINE_PROCESSING  1'h1
+    (* KEEP = "TRUE" *) bit [0:0] state2 = `S2_ENGINE_REQDATA;
+    
+    always @ ( posedge clk )
+        if ( rst ) begin
+            state2 <= `S2_ENGINE_REQDATA;
+        end
+        else case ( state2 )
+            `S2_ENGINE_REQDATA: begin
+                if ( rd1_out_valid && rd2_pkt1_large ) begin
+                    rd2_total_dwlen <= rd2_pkt1_dwlen_next;                             // dwlen (total remaining)
+                    rd2_pkt2[85:74] <= rd2_pkt1_dwlen_next << 2;                        // byte-count
+                    rd2_pkt2[73:63] <= (rd2_pkt1_dwlen_next > 11'h20) ? 11'h20 : rd2_pkt1_dwlen_next;   // dwlen next
+                    rd2_pkt2[62:12] <= rd1_out_data[62:12];                             // various data
+                    rd2_pkt2[11:0]  <= rd1_out_data[11:0] + (rd2_pkt1_dwlen << 2);      // base address (within 4k page)
+                    state2 <= `S2_ENGINE_PROCESSING;
+                end
+            end
+            `S2_ENGINE_PROCESSING: begin
+                if ( rd2_out_rden ) begin
+                    rd2_total_dwlen <= rd2_total_dwlen_next;                                // dwlen (total remaining)
+                    rd2_pkt2[85:74] <= rd2_total_dwlen_next << 2;                           // byte-count
+                    rd2_pkt2[73:63] <= (rd2_total_dwlen_next > 11'h20) ? 11'h20 : rd2_total_dwlen_next;   // dwlen next
+                    rd2_pkt2[62:12] <= rd2_pkt2[62:12];                                     // various data
+                    rd2_pkt2[11:0]  <= rd2_pkt2[11:0] + (rd2_pkt2_dwlen << 2);              // base address (within 4k page)
+                    if ( !rd2_pkt2_large ) begin
+                        state2 <= `S2_ENGINE_REQDATA;
+                    end
+                end
+            end
+        endcase
+    
+    assign rd1_out_rden = rd2_out_rden && (((state2 == `S2_ENGINE_REQDATA) && (!rd1_out_valid || rd2_pkt1_tiny)) || ((state2 == `S2_ENGINE_PROCESSING) && !rd2_pkt2_large));
+
+    wire [85:0] rd2_in_data  = (state2 == `S2_ENGINE_REQDATA) ? rd2_pkt1 : rd2_pkt2;
+    wire        rd2_in_valid = rd1_out_valid || ((state2 == `S2_ENGINE_PROCESSING) && rd2_out_rden);
+
+    bit  [85:0] rd2_out_data;
+    bit         rd2_out_valid;
+    always @ ( posedge clk ) begin
+        rd2_out_data    <= rd2_in_valid ? rd2_in_data : rd2_out_data;
+        rd2_out_valid   <= rd2_in_valid && !rst;
+    end
+
+    // ------------------------------------------------------------------------
+    // 3: PROCESS EACH READ REQUEST PACKAGE PER INDIVIDUAL 32-bit READ DWORDS:
+    // ------------------------------------------------------------------------
+
+    wire [4:0]  rd2_out_dwlen   = rd2_out_data[67:63];
+    wire        rd2_out_last    = (rd2_out_dwlen == 1);
+    wire [9:0]  rd2_out_dwaddr  = rd2_out_data[11:2];
+    
+    wire        rd3_enable;
+    
+    bit         rd3_process_valid;
+    bit         rd3_process_first;
+    bit         rd3_process_last;
+    bit [4:0]   rd3_process_dwlen;
+    bit [9:0]   rd3_process_dwaddr;
+    bit [85:0]  rd3_process_data;
+    wire        rd3_process_next_last = (rd3_process_dwlen == 2);
+    wire        rd3_process_nextnext_last = (rd3_process_dwlen <= 3);
+    
+    assign rd_req_ctx   = { rd3_process_first, rd3_process_last, rd3_process_data };
+    assign rd_req_bar   = rd3_process_data[62:56];
+    assign rd_req_addr  = { rd3_process_data[31:12], rd3_process_dwaddr, 2'b00 };
+    assign rd_req_valid = rd3_process_valid;
+    
+    // STATE MACHINE:
+    `define S3_ENGINE_REQDATA     1'h0
+    `define S3_ENGINE_PROCESSING  1'h1
+    (* KEEP = "TRUE" *) bit [0:0] state3 = `S3_ENGINE_REQDATA;
+    
+    always @ ( posedge clk )
+        if ( rst ) begin
+            rd3_process_valid   <= 1'b0;
+            state3              <= `S3_ENGINE_REQDATA;
+        end
+        else case ( state3 )
+            `S3_ENGINE_REQDATA: begin
+                if ( rd2_out_valid ) begin
+                    rd3_process_valid       <= 1'b1;
+                    rd3_process_first       <= 1'b1;                    // FIRST
+                    rd3_process_last        <= rd2_out_last;            // LAST (low 5 bits of dwlen == 1, [max pktlen = 0x20))
+                    rd3_process_dwlen       <= rd2_out_dwlen;           // PKT LENGTH IN DW
+                    rd3_process_dwaddr      <= rd2_out_dwaddr;          // DWADDR OF THIS DWORD
+                    rd3_process_data[85:0]  <= rd2_out_data[85:0];      // FORWARD / SAVE DATA
+                    if ( !rd2_out_last ) begin
+                        state3 <= `S3_ENGINE_PROCESSING;
+                    end
+                end
+                else begin
+                    rd3_process_valid       <= 1'b0;
+                end
+            end
+            `S3_ENGINE_PROCESSING: begin
+                rd3_process_first           <= 1'b0;                    // FIRST
+                rd3_process_last            <= rd3_process_next_last;   // LAST
+                rd3_process_dwlen           <= rd3_process_dwlen - 1;   // LEN DEC
+                rd3_process_dwaddr          <= rd3_process_dwaddr + 1;  // ADDR INC
+                if ( rd3_process_next_last ) begin
+                    state3 <= `S3_ENGINE_REQDATA;
+                end
+            end
+        endcase
+
+    assign rd2_out_rden = rd3_enable && (
+        ((state3 == `S3_ENGINE_REQDATA) && (!rd2_out_valid || rd2_out_last)) ||
+        ((state3 == `S3_ENGINE_PROCESSING) && rd3_process_nextnext_last));
+    
+    // ------------------------------------------------------------------------
+    // 4: PROCESS RESPONSES:
+    // ------------------------------------------------------------------------
+    
+    wire        rd_rsp_first    = rd_rsp_ctx[87];
+    wire        rd_rsp_last     = rd_rsp_ctx[86];
+    
+    wire [9:0]  rd_rsp_dwlen    = rd_rsp_ctx[72:63];
+    wire [11:0] rd_rsp_bc       = rd_rsp_ctx[85:74];
+    wire [15:0] rd_rsp_reqid    = rd_rsp_ctx[47:32];
+    wire [7:0]  rd_rsp_tag      = rd_rsp_ctx[55:48];
+    wire [6:0]  rd_rsp_lowaddr  = rd_rsp_ctx[6:0];
+    wire [31:0] rd_rsp_addr     = rd_rsp_ctx[31:0];
+    wire [31:0] rd_rsp_data_bs  = { rd_rsp_data[7:0], rd_rsp_data[15:8], rd_rsp_data[23:16], rd_rsp_data[31:24] };
+    
+    // 1: 32-bit -> 128-bit state machine:
+    bit [127:0] tdata;
+    bit [3:0]   tkeepdw = 0;
+    bit         tlast;
+    bit         first   = 1;
+    wire        tvalid  = tlast || tkeepdw[3];
+    
+    always @ ( posedge clk )
+        if ( rst ) begin
+            tkeepdw <= 0;
+            tlast   <= 0;
+            first   <= 0;
+        end
+        else if ( rd_rsp_valid && rd_rsp_first ) begin
+            tkeepdw         <= 4'b1111;
+            tlast           <= rd_rsp_last;
+            first           <= 1'b1;
+            tdata[31:0]     <= { 22'b0100101000000000000000, rd_rsp_dwlen };            // format, type, length
+            tdata[63:32]    <= { pcie_id[7:0], pcie_id[15:8], 4'b0, rd_rsp_bc };        // pcie_id, byte_count
+            tdata[95:64]    <= { rd_rsp_reqid, rd_rsp_tag, 1'b0, rd_rsp_lowaddr };      // req_id, tag, lower_addr
+            tdata[127:96]   <= rd_rsp_data_bs;
+        end
+        else begin
+            tlast   <= rd_rsp_valid && rd_rsp_last;
+            tkeepdw <= tvalid ? (rd_rsp_valid ? 4'b0001 : 4'b0000) : (rd_rsp_valid ? ((tkeepdw << 1) | 1'b1) : tkeepdw);
+            first   <= 0;
+            if ( rd_rsp_valid ) begin
+                if ( tvalid || !tkeepdw[0] )
+                    tdata[31:0]   <= rd_rsp_data_bs;
+                if ( !tkeepdw[1] )
+                    tdata[63:32]  <= rd_rsp_data_bs;
+                if ( !tkeepdw[2] )
+                    tdata[95:64]  <= rd_rsp_data_bs;
+                if ( !tkeepdw[3] )
+                    tdata[127:96] <= rd_rsp_data_bs;   
+            end
+        end
+    
+    // 2.1 - submit to output fifo - will feed into mux/pcie core.
+    fifo_134_134_clk1_bar_rdrsp i_fifo_134_134_clk1_bar_rdrsp(
+        .srst           ( rst                       ),
+        .clk            ( clk                       ),
+        .din            ( { first, tlast, tkeepdw, tdata } ),
+        .wr_en          ( tvalid                    ),
+        .rd_en          ( tlps_out.tready           ),
+        .dout           ( { tlps_out.tuser[0], tlps_out.tlast, tlps_out.tkeepdw, tlps_out.tdata } ),
+        .full           (                           ),
+        .empty          (                           ),
+        .prog_empty     ( rd3_enable                ),
+        .valid          ( tlps_out.tvalid           )
+    );
+    
+    assign tlps_out.tuser[1] = tlps_out.tlast;
+    assign tlps_out.tuser[8:2] = 0;
+    
+    // 2.2 - packet count:
+    bit [10:0]  pkt_count       = 0;
+    wire        pkt_count_dec   = tlps_out.tvalid && tlps_out.tlast;
+    wire        pkt_count_inc   = tvalid && tlast;
+    wire [10:0] pkt_count_next  = pkt_count + pkt_count_inc - pkt_count_dec;
+    assign tlps_out.has_data    = (pkt_count_next > 0);
+    
+    always @ ( posedge clk ) begin
+        pkt_count <= rst ? 0 : pkt_count_next;
+    end
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// Example BAR implementation that does nothing but drop any read/writes
+// silently without generating a response.
+// This is only recommended for placeholder designs.
+// Latency = N/A.
+// ------------------------------------------------------------------------
+module pcileech_bar_impl_none(
+    input               rst,
+    input               clk,
+    // incoming BAR writes:
+    input [31:0]        wr_addr,
+    input [3:0]         wr_be,
+    input [31:0]        wr_data,
+    input               wr_valid,
+    // incoming BAR reads:
+    input  [87:0]       rd_req_ctx,
+    input  [31:0]       rd_req_addr,
+    input               rd_req_valid,
+    // outgoing BAR read replies:
+    output bit [87:0]   rd_rsp_ctx,
+    output bit [31:0]   rd_rsp_data,
+    output bit          rd_rsp_valid
+);
+
+    initial rd_rsp_ctx = 0;
+    initial rd_rsp_data = 0;
+    initial rd_rsp_valid = 0;
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// Example BAR implementation of "address loopback" which can be useful
+// for testing. Any read to a specific BAR address will result in the
+// address as response.
+// Latency = 2CLKs.
+// ------------------------------------------------------------------------
+module pcileech_bar_impl_loopaddr(
+    input               rst,
+    input               clk,
+    // incoming BAR writes:
+    input [31:0]        wr_addr,
+    input [3:0]         wr_be,
+    input [31:0]        wr_data,
+    input               wr_valid,
+    // incoming BAR reads:
+    input [87:0]        rd_req_ctx,
+    input [31:0]        rd_req_addr,
+    input               rd_req_valid,
+    // outgoing BAR read replies:
+    output bit [87:0]   rd_rsp_ctx,
+    output bit [31:0]   rd_rsp_data,
+    output bit          rd_rsp_valid
+);
+
+    bit [87:0]      rd_req_ctx_1;
+    bit [31:0]      rd_req_addr_1;
+    bit             rd_req_valid_1;
+    
+    always @ ( posedge clk ) begin
+        rd_req_ctx_1    <= rd_req_ctx;
+        rd_req_addr_1   <= rd_req_addr;
+        rd_req_valid_1  <= rd_req_valid;
+        rd_rsp_ctx      <= rd_req_ctx_1;
+        rd_rsp_data     <= rd_req_addr_1;
+        rd_rsp_valid    <= rd_req_valid_1;
+    end    
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// Example BAR implementation of a 4kB writable initial-zero BAR.
+// Latency = 2CLKs.
+// ------------------------------------------------------------------------
+module pcileech_bar_impl_zerowrite4k(
+    input               rst,
+    input               clk,
+    // incoming BAR writes:
+    input [31:0]        wr_addr,
+    input [3:0]         wr_be,
+    input [31:0]        wr_data,
+    input               wr_valid,
+    // incoming BAR reads:
+    input  [87:0]       rd_req_ctx,
+    input  [31:0]       rd_req_addr,
+    input               rd_req_valid,
+    // outgoing BAR read replies:
+    output bit [87:0]   rd_rsp_ctx,
+    output bit [31:0]   rd_rsp_data,
+    output bit          rd_rsp_valid
+);
+
+    bit [87:0]  drd_req_ctx;
+    bit         drd_req_valid;
+    wire [31:0] doutb;
+    
+    always @ ( posedge clk ) begin
+        drd_req_ctx     <= rd_req_ctx;
+        drd_req_valid   <= rd_req_valid;
+        rd_rsp_ctx      <= drd_req_ctx;
+        rd_rsp_valid    <= drd_req_valid;
+        rd_rsp_data     <= doutb; 
+    end
+    
+    bram_bar_zero4k i_bram_bar_zero4k(
+        // Port A - write:
+        .addra  ( wr_addr[11:2]     ),
+        .clka   ( clk               ),
+        .dina   ( wr_data           ),
+        .ena    ( wr_valid          ),
+        .wea    ( wr_be             ),
+        // Port A - read (2 CLK latency):
+        .addrb  ( rd_req_addr[11:2] ),
+        .clkb   ( clk               ),
+        .doutb  ( doutb             ),
+        .enb    ( rd_req_valid      )
+    );
+
+endmodule
+
+
+
+// ------------------------------------------------------------------------
+// pcileech wifi BAR implementation
+// Works with Qualcomm Atheros AR9287 chip wifi adapters
+// ------------------------------------------------------------------------
+module pcileech_bar_impl_ar9287_wifi(
+    input               rst,
+    input               clk,
+    // incoming BAR writes:
+    input [31:0]        wr_addr,
+    input [3:0]         wr_be,
+    input [31:0]        wr_data,
+    input               wr_valid,
+    // incoming BAR reads:
+    input  [87:0]       rd_req_ctx,
+    input  [31:0]       rd_req_addr,
+    input               rd_req_valid,
+    input  [31:0]       base_address_register,
+    // outgoing BAR read replies:
+    output bit [87:0]   rd_rsp_ctx,
+    output bit [31:0]   rd_rsp_data,
+    output bit          rd_rsp_valid
+);
+
+    bit [87:0]      drd_req_ctx;
+    bit [31:0]      drd_req_addr;
+    bit             drd_req_valid;
+
+    bit [31:0]      dwr_addr;
+    bit [31:0]      dwr_data;
+    bit             dwr_valid;
+
+    bit [31:0]      data_32;
+
+    time number = 0;
+
+    always @ ( posedge clk ) begin
+        if (rst)
+            number <= 0;
+
+        number          <= number + 1;
+        drd_req_ctx     <= rd_req_ctx;
+        drd_req_valid   <= rd_req_valid;
+        dwr_valid       <= wr_valid;
+        drd_req_addr    <= rd_req_addr;
+        rd_rsp_ctx      <= drd_req_ctx;
+        rd_rsp_valid    <= drd_req_valid;
+        dwr_addr        <= wr_addr;
+        dwr_data        <= wr_data;
+
+        if (drd_req_valid)
+            case ({drd_req_addr[31:24], drd_req_addr[23:16], drd_req_addr[15:08], drd_req_addr[07:00]} - base_address_register)
+                16'h2000 : begin data_32 <= 1;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM MGIC REQ
+                16'h2200 : begin data_32 <= 2;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM SIZE REQ
+                16'h2204 : begin data_32 <= 3;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM CSUM REQ
+                16'h2208 : begin data_32 <= 4;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM VERS REQ
+                16'h220C : begin data_32 <= 5;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM ANTN REQ
+                16'h2210 : begin data_32 <= 6;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM RDMN REQ
+                16'h2218 : begin data_32 <= 7;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM MAC0 REQ
+                16'h221C : begin data_32 <= 8;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM MAC1 REQ
+                16'h2220 : begin data_32 <= 9;  rd_rsp_data <= 32'hDEADBEEF; end // EEPROM MAC2 REQ
+                16'h2224 : begin data_32 <= 10; rd_rsp_data <= 32'hDEADBEEF; end // EEPROM RXTX REQ
+                16'h2228 : begin data_32 <= 11; rd_rsp_data <= 32'hDEADBEEF; end // EEPROM ENDZ REQ
+                16'h4020 : rd_rsp_data <= 32'h001800FF; // MAC VERSION
+                16'h4028 : rd_rsp_data <= 32'h00000060; // interrupt pending
+                16'h4038 : rd_rsp_data <= 32'h00000002; // interrupt pending
+                16'h407C :
+                case (data_32)
+                    1  : rd_rsp_data <= 32'h0000A55A; // EEPROM_MAGIC
+                    2  : rd_rsp_data <= 32'h00000004; // EEPROM_SIZE
+                    3  : rd_rsp_data <= 32'h0000FFFB; // EEPROM_CHECKSUM
+                    4  : rd_rsp_data <= 32'h0000E00E; // EEPROM_VERSION
+                    5  : rd_rsp_data <= 32'h0000E00E; // EEPROM_ANTENNA (2.4ghz, 5ghz)
+                    6  : rd_rsp_data <= 32'h00000000; // EEPROM_REGDOMAIN (location)
+                    7  : rd_rsp_data <= 32'h00006EC4; // EEPROM_MAC0 (C4:6E)
+                    8  :
+                        begin
+                            rd_rsp_data[7:0]   <= 8'h1F;
+                            rd_rsp_data[15:8]  <= ((0 + (number) % (15 + 1 - 0)) << 4) | (0 + (number + 3) % (15 + 1 - 0));
+                            rd_rsp_data[31:16] <= 16'h0000;
+                        end
+                    9  :
+                        begin
+                            rd_rsp_data[7:0]   <= ((0 + (number + 6) % (15 + 1 - 0)) << 4) | (0 + (number + 9) % (15 + 1 - 0));
+                            rd_rsp_data[15:8]  <= ((0 + (number + 12) % (15 + 1 - 0)) << 4) | (0 + (number + 15) % (15 + 1 - 0));
+                            rd_rsp_data[31:16] <= 16'h0000;
+                        end
+                    10 : rd_rsp_data <= 32'h00000100; // EEPROM_RXTX (00,01)
+                    11 : begin rd_rsp_data <= 32'h00000000; data_32 <= 0; end
+                    default : rd_rsp_data <= 32'h00000000;
+                endcase
+                16'h7000 : rd_rsp_data <= 32'h00000000; // AR_RTC_RC
+                16'h7044 : rd_rsp_data <= 32'h00000002; // AR_RTC_STATUS
+                16'h8000 : rd_rsp_data <= data_32;      // AR_STA_ID0
+                16'h806C : rd_rsp_data <= 32'h00000000; // AR_OBS_BUS_1
+                16'h9820 : rd_rsp_data <= data_32;      // AR_STA_ID0
+                16'h9860 : rd_rsp_data <= 32'h00000000; // ath_hal_wait
+                16'h9C00 : rd_rsp_data <= 32'h00000000; // rf claim
+                default : rd_rsp_data <= 32'hDEADBEEF;  // default value: 0xDEADBEEF
+            endcase
+        else if (dwr_valid)
+            case ({dwr_addr[31:24], dwr_addr[23:16], dwr_addr[15:08], dwr_addr[07:00]} - base_address_register)
+                16'h8000 : data_32 <= dwr_data;
+                16'h9820 : data_32 <= dwr_data;
+            endcase
+        else
+            rd_rsp_data <= 32'hDEADBEEF;
+    end
+
+endmodule
+

JOKOSAHS_DMA-Pcileech/src/pcileech_tlps128_cfgspace_shadow.sv

@@ -0,0 +1,260 @@
+//
+// PCILeech FPGA.
+//
+// PCIe custom shadow configuration space.
+// Xilinx PCIe core will take configuration space priority; if Xilinx PCIe core
+// is configured to forward configuration requests to user application such TLP
+// will end up being processed by this module.
+//
+// (c) Ulf Frisk, 2021-2024
+// Author: Ulf Frisk, pcileech@frizk.net
+//
+
+`timescale 1ns / 1ps
+
+module pcileech_tlps128_cfgspace_shadow(
+    input                   rst,
+    input                   clk_pcie,
+    input                   clk_sys,
+    IfAXIS128.sink_lite     tlps_in,
+    input [15:0]            pcie_id,
+    IfAXIS128.source        tlps_cfg_rsp,
+    IfShadow2Fifo.shadow    dshadow2fifo
+);
+    // ----------------------------------------------------------------------------
+    // PCIe RECEIVE:
+    // ----------------------------------------------------------------------------
+    wire                pcie_rx_rden    = tlps_in.tvalid && tlps_in.tuser[0] && (tlps_in.tdata[31:25] == 7'b0000010);   // CfgRd: Fmt[2:0]=000b (3 DW header, no data), CfgRd0/CfgRd1=0010xb
+    wire                pcie_rx_wren    = tlps_in.tvalid && tlps_in.tuser[0] && (tlps_in.tdata[31:25] == 7'b0100010);   // CfgWr: Fmt[2:0]=010b (3 DW header, data),    CfgWr0/CfgWr1=0010xb
+    wire [9:0]          pcie_rx_addr    = tlps_in.tdata[75:66];
+    wire [31:0]         pcie_rx_data    = tlps_in.tdata[127:96];
+    wire [7:0]          pcie_rx_tag     = tlps_in.tdata[47:40];
+    wire [3:0]          pcie_rx_be      = {tlps_in.tdata[32], tlps_in.tdata[33], tlps_in.tdata[34], tlps_in.tdata[35]};
+    wire [15:0]         pcie_rx_reqid   = tlps_in.tdata[63:48];
+        
+    // ----------------------------------------------------------------------------
+    // USB RECEIVE (clock domain crossing):
+    // ----------------------------------------------------------------------------
+    wire                usb_rx_rden_out;
+    wire                usb_rx_wren_out;
+    wire                usb_rx_valid;
+    wire                usb_rx_rden = usb_rx_valid && usb_rx_rden_out;
+    wire                usb_rx_wren = usb_rx_valid && usb_rx_wren_out;
+    wire    [3:0]       usb_rx_be;
+    wire    [31:0]      usb_rx_data;
+    wire    [9:0]       usb_rx_addr;
+    wire                usb_rx_addr_lo;
+    fifo_49_49_clk2 i_fifo_49_49_clk2(
+        .rst            ( rst                       ),
+        .wr_clk         ( clk_sys                   ),
+        .rd_clk         ( clk_pcie                  ),
+        .wr_en          ( dshadow2fifo.rx_rden || dshadow2fifo.rx_wren ),
+        .din            ( {dshadow2fifo.rx_rden, dshadow2fifo.rx_wren, dshadow2fifo.rx_addr_lo, dshadow2fifo.rx_addr, dshadow2fifo.rx_be, dshadow2fifo.rx_data} ),
+        .full           (                           ),
+        .rd_en          ( 1'b1                      ),
+        .dout           ( {usb_rx_rden_out, usb_rx_wren_out, usb_rx_addr_lo, usb_rx_addr, usb_rx_be, usb_rx_data} ),    
+        .empty          (                           ),
+        .valid          ( usb_rx_valid              )
+    );
+
+    // ----------------------------------------------------------------------------
+    // WRITE multiplexor: simple naive multiplexor which will prioritize in order:
+    // (1) PCIe (if enabled), (2) USB, (3) INTERNAL.
+    // Collisions will be discarded (it's assumed that they'll be very rare)
+    // ----------------------------------------------------------------------------
+    wire            bram_wr_1_tlp = pcie_rx_wren & dshadow2fifo.cfgtlp_en;
+    wire            bram_wr_2_usb = ~bram_wr_1_tlp & usb_rx_wren;
+    wire [3:0]      bram_wr_be = bram_wr_1_tlp ? (dshadow2fifo.cfgtlp_wren ? pcie_rx_be : 4'b0000) : (bram_wr_2_usb ? usb_rx_be : 4'b0000);
+    wire [31:0]     bram_wr_data = bram_wr_1_tlp ? pcie_rx_data : (bram_wr_2_usb ? usb_rx_data : 32'h00000000);
+    
+    // ----------------------------------------------------------------------------
+    // WRITE multiplexor and state machine: simple naive multiplexor which will prioritize in order:
+    // (1) PCIe (if enabled), (2) USB, (3) INTERNAL.
+    // Collisions will be discarded (it's assumed that they'll be very rare)
+    // ----------------------------------------------------------------------------
+    `define S_SHADOW_CFGSPACE_IDLE  2'b00
+    `define S_SHADOW_CFGSPACE_TLP   2'b01
+    `define S_SHADOW_CFGSPACE_USB   2'b10
+    
+    wire [15:0]     bram_rd_reqid;
+    wire [1:0]      bram_rd_tp;
+    wire [7:0]      bram_rd_tag;
+    wire [9:0]      bram_rd_addr;
+    wire [31:0]     bram_rd_data;
+    wire [31:0]     bram_rd_data_z  = dshadow2fifo.cfgtlp_zero ? 32'h00000000 : bram_rd_data;
+    wire            bram_rd_valid   = (bram_rd_tp == `S_SHADOW_CFGSPACE_TLP);
+    wire            bram_rd_tlpwr;
+    
+    wire            bram_rd_1_tlp   = pcie_rx_rden & dshadow2fifo.cfgtlp_en;
+    wire            bram_tlp        = bram_rd_1_tlp | bram_wr_1_tlp;
+    wire            bram_rd_2_usb   = ~bram_tlp & usb_rx_rden;
+    wire [1:0]      bram_rdreq_tp   = bram_tlp ? `S_SHADOW_CFGSPACE_TLP : (bram_rd_2_usb ? `S_SHADOW_CFGSPACE_USB : `S_SHADOW_CFGSPACE_IDLE);
+    wire [9:0]      bram_rdreq_addr = bram_tlp ? pcie_rx_addr : usb_rx_addr;
+    wire [7:0]      bram_rdreq_tag  = bram_tlp ? pcie_rx_tag : {7'h00, usb_rx_addr_lo};
+    wire [15:0]     bram_rdreq_reqid= bram_tlp ? pcie_rx_reqid : 16'h0000;
+    
+    // BRAM MEMORY ACCESS for the 4kB / 0x1000 byte shadow configuration space.    
+    pcileech_mem_wrap i_pcileech_mem_wrap(
+        .clk_pcie       ( clk_pcie                 ), // <-
+        .rdwr_addr      ( bram_rdreq_addr          ), // <-
+        .wr_be          ( bram_wr_be               ), // <-
+        .wr_data        ( bram_wr_data             ), // <-
+        .rdreq_tag      ( bram_rdreq_tag           ), // <-
+        .rdreq_tp       ( bram_rdreq_tp            ), // <-
+        .rdreq_reqid    ( bram_rdreq_reqid         ), // <-
+        .rdreq_tlpwr    ( bram_wr_1_tlp            ), // <-
+        .rd_data        ( bram_rd_data             ), // ->
+        .rd_addr        ( bram_rd_addr             ), // ->
+        .rd_tag         ( bram_rd_tag              ), // ->
+        .rd_tp          ( bram_rd_tp               ), // ->
+        .rd_reqid       ( bram_rd_reqid            ), // ->
+        .rd_tlpwr       ( bram_rd_tlpwr            )  // ->
+    );
+    
+    // PCIe REPLY:
+    pcileech_cfgspace_pcie_tx i_pcileech_cfgspace_pcie_tx(
+        .rst            ( rst                       ),  // <-
+        .clk_pcie       ( clk_pcie                  ),  // <-
+        .pcie_id        ( pcie_id                   ),  // <- [15:0]
+        .tlps_cfg_rsp   ( tlps_cfg_rsp              ),
+        // cfgspace:
+        .cfg_wren       ( bram_rd_valid             ),  // <-
+        .cfg_tlpwr      ( bram_rd_tlpwr             ),  // <-
+        .cfg_tag        ( bram_rd_tag               ),  // <- [7:0]
+        .cfg_data       ( bram_rd_data_z            ),  // <- [32:0]
+        .cfg_reqid      ( bram_rd_reqid             )   // <- [15:0]
+    );
+    
+    // USB REPLY:
+    fifo_43_43_clk2 i_fifo_43_43_clk2(
+        .rst            ( rst                       ),
+        .wr_clk         ( clk_pcie                  ),
+        .rd_clk         ( clk_sys                   ),
+        .wr_en          ( (bram_rd_tp == `S_SHADOW_CFGSPACE_USB) ),
+        .din            ( {bram_rd_tag[0], bram_rd_addr, bram_rd_data_z} ),
+        .full           (                           ),
+        .rd_en          ( 1'b1                      ),
+        .dout           ( {dshadow2fifo.tx_addr_lo, dshadow2fifo.tx_addr, dshadow2fifo.tx_data} ),    
+        .empty          (                           ),
+        .valid          ( dshadow2fifo.tx_valid     )
+    );
+    
+endmodule
+
+
+
+// PCIe TLP cfg reply module:
+module pcileech_cfgspace_pcie_tx(
+    input                   rst,
+    input                   clk_pcie,
+    input   [15:0]          pcie_id,        // PCIe id of this core
+    IfAXIS128.source        tlps_cfg_rsp,
+    // cfgspace:
+    input                   cfg_wren,
+    input                   cfg_tlpwr,
+    input [7:0]             cfg_tag,
+    input [31:0]            cfg_data,
+    input [15:0]            cfg_reqid
+    );
+    
+    wire [31:0]     cpl_tlp_data_dw0_rd  = 32'b01001010000000000000000000000001;
+    wire [31:0]     cpl_tlp_data_dw0_wr  = 32'b00001010000000000000000000000000;
+    wire [31:0]     cpl_tlp_data_dw1     = { `_bs16(pcie_id), 16'h0004 };
+    wire [31:0]     cpl_tlp_data_dw2     = { cfg_reqid, cfg_tag, 8'h00 };
+    wire [31:0]     cpl_tlp_data_dw3     = cfg_data;
+    wire [127:0]    cpl_tlp_rd           = { cpl_tlp_data_dw3, cpl_tlp_data_dw2, cpl_tlp_data_dw1, cpl_tlp_data_dw0_rd };
+    wire [127:0]    cpl_tlp_wr           = { 32'h00000000,     cpl_tlp_data_dw2, cpl_tlp_data_dw1, cpl_tlp_data_dw0_wr };
+    wire [128:0]    cpl_tlps             = cfg_tlpwr ? {1'b0, cpl_tlp_wr} : {1'b1, cpl_tlp_rd};
+
+    wire tx_tp;
+    wire tx_empty;
+    fifo_129_129_clk1 i_fifo_129_129_clk1 (
+        .srst           ( rst                       ),
+        .clk            ( clk_pcie                  ),
+        // data in
+        .wr_en          ( cfg_wren                  ),
+        .din            ( cpl_tlps                  ),
+        .full           (                           ),
+        // data out
+        .rd_en          ( tlps_cfg_rsp.tready       ),
+        .dout           ( {tx_tp, tlps_cfg_rsp.tdata} ), 
+        .empty          ( tx_empty                  ),
+        .valid          ( tlps_cfg_rsp.tvalid       )
+    );
+    
+    assign tlps_cfg_rsp.tkeepdw = (tx_tp ? 4'b1111 : 4'b0111);
+    assign tlps_cfg_rsp.tlast = 1;
+    assign tlps_cfg_rsp.tuser = 0;
+    assign tlps_cfg_rsp.has_data = ~tx_empty;    
+endmodule
+
+
+
+// Wrapper module for the BRAM-backed configuration space.
+module pcileech_mem_wrap(
+    input               clk_pcie,
+    
+    // Address common to Read/Write:
+    input   [9:0]       rdwr_addr,
+    
+    // Write to 'configuration/action space':
+    input   [3:0]       wr_be,
+    input   [31:0]      wr_data,
+       
+    // Read from 'configuration space':
+    input   [7:0]       rdreq_tag,
+    input   [1:0]       rdreq_tp,
+    input   [15:0]      rdreq_reqid,
+    input               rdreq_tlpwr,
+    
+    output bit  [9:0]   rd_addr,
+    output      [31:0]  rd_data,
+    output bit  [7:0]   rd_tag,
+    output bit  [1:0]   rd_tp,
+    output bit  [15:0]  rd_reqid,
+    output bit          rd_tlpwr
+    );
+    
+    bit [3:0]  wr_be_d;
+    bit [31:0] wr_data_d;
+    
+    wire [31:0] wr_mask;
+    wire [31:0] wr_dina;
+    
+    // DELAY TO FOLLOW BRAM DELAY
+    always @ ( posedge clk_pcie )
+        begin
+            wr_be_d     <= wr_be;
+            wr_data_d   <= wr_data;
+            rd_addr     <= rdwr_addr;
+            rd_tag      <= rdreq_tag;
+            rd_tp       <= rdreq_tp;
+            rd_reqid    <= rdreq_reqid;
+            rd_tlpwr    <= rdreq_tlpwr;
+        end
+
+    // BRAM: 'configuration space' - 4kB / 0x1000 bytes:
+    bram_pcie_cfgspace i_bram_pcie_cfgspace(
+        .clka           ( clk_pcie                  ),
+        .clkb           ( clk_pcie                  ),
+        .wea            ( wr_be_d                   ),
+        .addra          ( rd_addr                   ),
+        .dina           ( wr_dina                   ),
+        .addrb          ( rdwr_addr                 ),
+        .doutb          ( rd_data                   )
+    );
+    
+    // DROM: 'configuration space' - 4kB / 0x1000 bytes write mask:
+    drom_pcie_cfgspace_writemask i_drom_pcie_cfgspace_writemask(
+        .a              ( rd_addr                   ),
+        .spo            ( wr_mask                   )
+    );
+    
+    genvar i;
+    generate
+        for (i = 0; i < 32; i++) begin
+            assign wr_dina[i] = wr_mask[i] ? wr_data_d[i] : rd_data[i];
+        end
+    endgenerate
+
+endmodule

JOKOSAHS_DMA-Pcileech/vivado_build.tcl

@@ -0,0 +1,26 @@
+#
+# RUN FROM WITHIN "Vivado Tcl Shell" WITH COMMAND:
+# source vivado_build.tcl -notrace
+#
+puts "-------------------------------------------------------"
+puts " STARTING SYNTHESIS STEP.                              "
+puts "-------------------------------------------------------"
+launch_runs synth_1
+puts "-------------------------------------------------------"
+puts " WAITING FOR SYNTHESIS STEP TO FINISH ...              "
+puts " THIS IS LIKELY TO TAKE A VERY LONG TIME.              "
+puts "-------------------------------------------------------"
+wait_on_run synth_1
+puts "-------------------------------------------------------"
+puts " STARTING IMPLEMENTATION STEP.                         "
+puts "-------------------------------------------------------"
+launch_runs impl_1 -to_step write_bitstream
+puts "-------------------------------------------------------"
+puts " WAITING FOR IMPLEMENTATION STEP TO FINISH ...         "
+puts " THIS IS LIKELY TO TAKE A VERY LONG TIME.              "
+puts "-------------------------------------------------------"
+wait_on_run impl_1
+file copy -force ./pcileech_squirrel/pcileech_squirrel.runs/impl_1/pcileech_squirrel_top.bin pcileech_squirrel.bin
+puts "-------------------------------------------------------"
+puts " BUILD HOPEFULLY COMPLETED.                            "
+puts "-------------------------------------------------------"

JOKOSAHS_DMA-Pcileech/vivado_build_100t.tcl

@@ -0,0 +1,26 @@
+#
+# RUN FROM WITHIN "Vivado Tcl Shell" WITH COMMAND:
+# source vivado_build.tcl -notrace
+#
+puts "-------------------------------------------------------"
+puts " STARTING SYNTHESIS STEP.                              "
+puts "-------------------------------------------------------"
+launch_runs -jobs 6 synth_1
+puts "-------------------------------------------------------"
+puts " WAITING FOR SYNTHESIS STEP TO FINISH ...              "
+puts " THIS IS LIKELY TO TAKE A VERY LONG TIME.              "
+puts "-------------------------------------------------------"
+wait_on_run synth_1
+puts "-------------------------------------------------------"
+puts " STARTING IMPLEMENTATION STEP.                         "
+puts "-------------------------------------------------------"
+launch_runs -jobs 4 impl_1 -to_step write_bitstream
+puts "-------------------------------------------------------"
+puts " WAITING FOR IMPLEMENTATION STEP TO FINISH ...         "
+puts " THIS IS LIKELY TO TAKE A VERY LONG TIME.              "
+puts "-------------------------------------------------------"
+wait_on_run impl_1
+file copy -force ./pcileech_tbx4_100t/pcileech_tbx4_100t.runs/impl_1/pcileech_tbx4_100t_top.bin pcileech_zdma_100t_fpga0.bin
+puts "-------------------------------------------------------"
+puts " BUILD HOPEFULLY COMPLETED.                            "
+puts "-------------------------------------------------------"

JOKOSAHS_DMA-Pcileech/vivado_generate_project_100t.tcl

@@ -0,0 +1,1068 @@
+#
+# Vivado generated .tcl for creating the pcileech_tbx4_100t vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_tbx4_100t"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/../ScreamerM2_TEST4/pcileech_screamer_m2"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a100tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "27" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "27" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "27" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "27" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "27" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "27" -objects $obj
+set_property -name "webtalk.xcelium_export_sim" -value "4" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "27" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com_e.v" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7x4.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tbx4_100t_top.sv" ]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/zdma/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com_e.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7x4.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tbx4_100t_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/zdma/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_tbx4_100t_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/100T/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/100T/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/100T/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/clk_wiz_0.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "clk_wiz_0/clk_wiz_0.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/100T/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/pcileech_tbx4_100t.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/pcileech_tbx4_100t.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+set_property -name "processing_order" -value "EARLY" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a100tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "pcileech_tbx4_100t_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a100tfgg484-2 -flow {Vivado Synthesis 2023} -strategy "Flow_PerfOptimized_high" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Flow_PerfOptimized_high" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2023" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "auto_incremental_checkpoint" -value "1" -objects $obj
+set_property -name "strategy" -value "Flow_PerfOptimized_high" -objects $obj
+set_property -name "steps.synth_design.args.directive" -value "PerformanceOptimized" -objects $obj
+set_property -name "steps.synth_design.args.fsm_extraction" -value "one_hot" -objects $obj
+set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "1" -objects $obj
+set_property -name "steps.synth_design.args.resource_sharing" -value "off" -objects $obj
+set_property -name "steps.synth_design.args.no_lc" -value "1" -objects $obj
+set_property -name "steps.synth_design.args.shreg_min_size" -value "5" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a100tfgg484-2 -flow {Vivado Implementation 2023} -strategy "Performance_ExtraTimingOpt" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Performance_ExtraTimingOpt" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2023" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.report_unconstrained" -value "1" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a100tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Performance_ExtraTimingOpt" -objects $obj
+set_property -name "steps.place_design.args.directive" -value "ExtraTimingOpt" -objects $obj
+set_property -name "steps.phys_opt_design.args.directive" -value "Explore" -objects $obj
+set_property -name "steps.route_design.args.directive" -value "NoTimingRelaxation" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.args.directive" -value "AddRetime" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+catch {
+ if { $idrFlowPropertiesConstraints != {} } {
+   set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
+ }
+}
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

JOKOSAHS_DMA-Pcileech/vivado_generate_project_captain_75T.tcl

@@ -0,0 +1,1071 @@
+#
+# Vivado generated .tcl for creating the pcileech_enigma_x1 vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_enigma_x1"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/pcileech_enigma_x1"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a75tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com.sv" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_ft601.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_enigma_x1_top.sv"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_ft601.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_enigma_x1_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_enigma_x1_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_256_32_clk2_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_256_32_clk2_comtx/fifo_256_32_clk2_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk1_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk1_comtx/fifo_32_32_clk1_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk2_comrx.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk2_comrx/fifo_64_64_clk2_comrx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/pcileech_captain_75T.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/pcileech_captain_75T.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a75tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "pcileech_enigma_x1_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a75tfgg484-2 -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a75tfgg484-2 -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2022" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

JOKOSAHS_DMA-Pcileech/vivado_generate_project_enigma_x1.tcl

@@ -0,0 +1,1071 @@
+#
+# Vivado generated .tcl for creating the pcileech_enigma_x1 vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_enigma_x1"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/pcileech_enigma_x1"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a75tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com.sv" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_ft601.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_enigma_x1_top.sv"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_ft601.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_enigma_x1_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_enigma_x1_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_256_32_clk2_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_256_32_clk2_comtx/fifo_256_32_clk2_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk1_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk1_comtx/fifo_32_32_clk1_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk2_comrx.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk2_comrx/fifo_64_64_clk2_comrx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/pcileech_enigma_x1.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/pcileech_enigma_x1.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a75tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "pcileech_enigma_x1_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a75tfgg484-2 -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a75tfgg484-2 -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2022" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

JOKOSAHS_DMA-Pcileech/vivado_generate_project_immortal_75T.tcl

@@ -0,0 +1,1071 @@
+#
+# Vivado generated .tcl for creating the pcileech_enigma_x1 vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_enigma_x1"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/pcileech_enigma_x1"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a75tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com.sv" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_ft601.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_enigma_x1_top.sv"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_ft601.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_enigma_x1_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_enigma_x1_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_256_32_clk2_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_256_32_clk2_comtx/fifo_256_32_clk2_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk1_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk1_comtx/fifo_32_32_clk1_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk2_comrx.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk2_comrx/fifo_64_64_clk2_comrx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/75immt.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/75immt.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a75tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "pcileech_enigma_x1_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a75tfgg484-2 -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a75tfgg484-2 -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2022" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

JOKOSAHS_DMA-Pcileech/vivado_generate_project_immortal_75Ts.tcl

@@ -0,0 +1,1071 @@
+#
+# Vivado generated .tcl for creating the pcileech_squirrel vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_squirrel"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/pcileech_squirrel"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a75tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com.sv" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_ft601.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_squirrel_top.sv"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_ft601.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_squirrel_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_squirrel_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_256_32_clk2_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_256_32_clk2_comtx/fifo_256_32_clk2_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk1_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk1_comtx/fifo_32_32_clk1_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk2_comrx.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk2_comrx/fifo_64_64_clk2_comrx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/pcileech_squirrel.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/pcileech_squirrel.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a75tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "pcileech_squirrel_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a75tfgg484-2 -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a75tfgg484-2 -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2022" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a75tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

JOKOSAHS_DMA-Pcileech/vivado_generate_project_m2.tcl

@@ -0,0 +1,1071 @@
+#
+# Vivado generated .tcl for creating the pcileech_screamer_m2 vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_screamer_m2"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/pcileech_screamer_m2"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35tcsg325-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a35tcsg325-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com.sv" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_ft601.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_screamer_m2_top.sv"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_ft601.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_screamer_m2_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_screamer_m2_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_256_32_clk2_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_256_32_clk2_comtx/fifo_256_32_clk2_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk1_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk1_comtx/fifo_32_32_clk1_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk2_comrx.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk2_comrx/fifo_64_64_clk2_comrx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/pcileech_screamer_m2.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/pcileech_screamer_m2.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a35tcsg325-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "pcileech_screamer_m2_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a35tcsg325-2 -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a35tcsg325-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a35tcsg325-2 -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2022" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a35tcsg325-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

JOKOSAHS_DMA-Pcileech/vivado_generate_project_squirrel.tcl

@@ -0,0 +1,1071 @@
+#
+# Vivado generated .tcl for creating the pcileech_squirrel vivado project.
+# Run from within "Vivado Tcl Shell" with command: source vivado_generate_project.tcl -notrace
+#
+
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir "."
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "pcileech_squirrel"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "vivado_generate_project.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/pcileech_squirrel"]"
+
+# Create project
+create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7a35tfgg484-2
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "part" -value "xc7a35tfgg484-2" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "5" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/src/pcileech_header.svh"]\
+ [file normalize "${origin_dir}/src/pcileech_com.sv" ]\
+ [file normalize "${origin_dir}/src/pcileech_fifo.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_ft601.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_mux.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_cfg_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_pcie_tlp_a7.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_bar_controller.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_tlps128_cfgspace_shadow.sv"]\
+ [file normalize "${origin_dir}/src/pcileech_squirrel_top.sv"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_core_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_common.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gt_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtp_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_brams_7x.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_lane.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_misc.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pcie2_top.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_clock.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_eq.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_rate.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_sync.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_user.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_pipe_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_drp.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_reset.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_qpll_wrapper.v"]\
+ [file normalize "${origin_dir}/pcie_7x/pcie_7x_0_rxeq_scan.v"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "src/pcileech_header.svh"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog Header" -objects $file_obj
+
+set file "src/pcileech_com.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_fifo.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_ft601.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_mux.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_cfg_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_pcie_tlp_a7.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_bar_controller.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_tlps128_cfgspace_shadow.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "src/pcileech_squirrel_top.sv"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_null_gen.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_rx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_axi_basic_tx_thrtl_ctl.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_core_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_common.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_rx_valid_filter_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gt_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtp_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_bram_top_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_brams_7x.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_lane.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_misc.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_pipe_pipeline.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pcie2_top.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_clock.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_eq.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_rate.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_sync.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_user.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_drp.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_pipe_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_reset.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_qpll_wrapper.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+set file "pcie_7x/pcie_7x_0_rxeq_scan.v"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "Verilog" -objects $file_obj
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "pcileech_squirrel_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/pcileech_bar_zero4k.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace.coe" ]\
+ [file normalize "${origin_dir}/ip/pcileech_cfgspace_writemask.coe" ]\
+ [file normalize "${origin_dir}/ip/bram_pcie_cfgspace.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_pcie_cfgspace/bram_pcie_cfgspace.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/drom_pcie_cfgspace_writemask.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "drom_pcie_cfgspace_writemask/drom_pcie_cfgspace_writemask.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_74_74_clk1_bar_rd1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_74_74_clk1_bar_rd1/fifo_74_74_clk1_bar_rd1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/bram_bar_zero4k.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "bram_bar_zero4k/bram_bar_zero4k.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk1_bar_rdrsp.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk1_bar_rdrsp/fifo_134_134_clk1_bar_rdrsp.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_141_141_clk1_bar_wr.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_141_141_clk1_bar_wr/fifo_141_141_clk1_bar_wr.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2_rxfifo.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2_rxfifo/fifo_134_134_clk2_rxfifo.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_1_1_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_1_1_clk2/fifo_1_1_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_134_134_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_134_134_clk2/fifo_134_134_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk1_fifocmd.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk1_fifocmd/fifo_64_64_clk1_fifocmd.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_256_32_clk2_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_256_32_clk2_comtx/fifo_256_32_clk2_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk1_comtx.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk1_comtx/fifo_32_32_clk1_comtx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_129_129_clk1.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_129_129_clk1/fifo_129_129_clk1.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64/fifo_64_64.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_32_32_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_32_32_clk2/fifo_32_32_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_49_49_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_49_49_clk2/fifo_49_49_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_43_43_clk2.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_43_43_clk2/fifo_43_43_clk2.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_34_34.xci"]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_34_34/fifo_34_34.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Import local files from the original project
+set files [list \
+ [file normalize "${origin_dir}/ip/fifo_64_64_clk2_comrx.xci" ]\
+]
+set imported_files [import_files -fileset sources_1 $files]
+# Set 'sources_1' fileset file properties for remote files
+# None
+# Set 'sources_1' fileset file properties for local files
+set file "fifo_64_64_clk2_comrx/fifo_64_64_clk2_comrx.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize ${origin_dir}/src/pcileech_squirrel.xdc]"
+set file_imported [import_files -fileset constrs_1 [list $file]]
+set file "src/pcileech_squirrel.xdc"
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "target_part" -value "xc7a35tfgg484-2" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+# Empty (no sources present)
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "top" -value "pcileech_squirrel_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Upgrade IP from the currently installed Vivado version
+upgrade_ip [get_ips *]
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a35tfgg484-2 -flow {Vivado Synthesis 2022} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2022" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "part" -value "xc7a35tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a35tfgg484-2 -flow {Vivado Implementation 2022} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2022" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "part" -value "xc7a35tfgg484-2" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "1" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

lawrie_fpga_pio/.gitignore

@@ -0,0 +1,5 @@
+bin/
+__pycache__/
+tb
+*.vcd
+

lawrie_fpga_pio/LICENSE

@@ -0,0 +1,25 @@
+BSD 2-Clause License
+
+Copyright (c) 2022, Lawrie Griffiths
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+   list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+   this list of conditions and the following disclaimer in the documentation
+   and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

lawrie_fpga_pio/README.md

@@ -0,0 +1,200 @@
+# FPGA RP2040 PIO
+
+## Introduction
+
+This is an attempt to recreate the Raspberry Pi RP2040 PIO interface in Verilog.
+
+PIO stands for Progammable I/O, and it is a peripheral that is part of the RP2040 SoC, which is much more flexible than hardware implementations of specific protocols like SPI, I2C, UART etc. It can implement all these protocols and more at high speed and on any GPIO pins.
+
+It runs in up to 8 special processors, known as State Machines, which are programmed in assembler using a machine language designed specifically for fast cycle-accurate I/O. These processors run independently of the main CPUs.
+
+This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but some programs run in simulation and on open source FPGA boards.
+
+The current supported boards are the Blackice MX and the Ulx3s.
+
+The current method of configuring and controlling PIO from a top-level module is different from that used on the RP2040 chip, and will probably be changed for closer compatibility.
+
+For use by a SoC, e.g. a RISC-V SoC such as SaxonSoc, the appropriate peripheral bus interface would need to be added.
+
+For use from a host processor, such as one running micropython, an SPI read/write memory interface could be added. This would be a lot slower than a bus interface but speed is not usually an issue for configuration and control. There are usually too few pins between a host processor and the fpga to implement a 32-bit (or even an 8-bit) bus interface.
+
+## Simulation
+
+To run a program in simulation, clone the repository and do:
+
+```sh
+cd fpga_pio/sim
+make sim
+```
+
+That runs the tb.v testbench. You can see the results by opening waves.vcd using gtkwave.
+
+You can run the other test programs in the sim directory, such as uart_tx.v, by:
+
+```sh
+make sim TB=uart_tx
+```
+
+## Synthesis
+
+To run the top.v Verilog file on the Blackice MX board, do:
+
+```sh
+cd blackicemx
+make prog
+```
+
+For the Ulxs3 board use the ulx3s directory.
+
+The current program flashes the red led approximately once per second.
+
+You can select a different top-level module by, for example:
+
+```sh
+make clean prog TOP=hello
+```
+
+Current working top level modules include: blink, hello, wds812, exec, uart_tx.
+
+## Assembling programs
+
+You can assemble program using the Adafuit pioasm assembler (used by CircuitPython), by:
+
+```sh
+cd asm
+./compile square.asm square.mem
+```
+
+and then move square.mem to the src/top and/or the sim directory.
+
+The compiler is currently incomplete and so the .mem files sometimes need modification, e.g when the "'side_set opt" option is used.
+
+## Examples
+
+### Blink
+
+```
+.program blink
+    set pindirs 1
+again:
+    set pins 1 [31]  ; Drive pin high and then delay for 31 cycles
+    nop [31]
+    nop [31]
+    nop [31]
+    nop [31]
+    set pins 0 [30]  ; Drive pin low
+    nop [31]
+    nop [31]
+    nop [31]
+    nop [31]
+    jmp again
+```
+
+This blinks every 320 cycles. so with a maximum clock divider of 64K -1 (0xFFFF), and a 25MHz FPGA clock, it blinks approximately every 1.2 seconds.
+
+### Hello
+
+```
+.program uart_tx
+.side_set 1 opt
+    pull block    side 1
+    set x 7       side 0 [7]
+again:
+    out pins 1
+    jmp x-- again        [6]
+```
+
+This example outputs a message repeatedly on the console.
+
+### Exec
+
+The exec examples needs no PIO program as it executes a SET PINS instruction immediately. The machine does not need to be enabled.
+The top/exec.v Verilog module uses immediate execution to blink the led approximately once per second.
+
+### Pwm
+
+```
+.program pwm
+.side_set 1 opt
+    pull noblock    side 0
+    mov x osr
+    mov y isr
+countloop:
+    jmp x!=y noset
+    jmp skip        side 1
+noset:
+    nop
+skip:
+    jmp y-- countloop
+```
+
+The pwm example set the led off and then increases its brightness, repeatedly.
+
+### Neopixels
+
+```
+.program ws2812
+.side_set 1
+.wrap_target
+bitloop:
+  out x 1        side 0 [1]; Side-set still takes place when instruction stalls
+  jmp !x do_zero side 1 [1]; Branch on the bit we shifted out. Positive pulse
+do_one:
+  jmp  bitloop   side 1 [1]; Continue driving high, for a long pulse
+do_zero:
+  nop            side 0
+```
+
+![ws2812 example](https://raw.githubusercontent.com/lawrie/lawrie.github.io/master/images/ws2812.jpg)
+
+### Stepper motor
+
+This example shows driving a stepper motor with PIO. 
+
+You set the direction by pushing the required phase patterns as a set of 8 4-bit values, and then you push the required number of half steps.
+
+To start again with a new set of steps, you execute an immediate jump to the start of the program.
+
+```
+.program stepper
+    pull block
+    mov isr osr
+    pull block
+    mov y osr
+outer:
+    mov osr isr 
+    set x 6
+inner:
+    out pins 4 [2]
+    jmp x-- inner
+    out pins 4
+    jmp y-- outer
+wrap_target:
+    out pins 4
+    jmp wrap_target
+```
+
+Here is is driving a stepper motor from a Blackice MX:
+
+![blackice mx stepper](https://github.com/lawrie/lawrie.github.io/blob/master/images/stepper_mx.jpg)
+
+### I2S
+
+```
+.program i2s
+.side_set 2
+    pull noblock  side 3
+    mov x osr     side 3
+    set y 14      side 3 [1]
+loop1:
+    out pins 1    side 2 [3]
+    jmp y-- loop1 side 3 [3]
+    out pins 1    side 0 [3]
+    set y 14      side 1 [3]
+loop0:
+    out pins 1    side 0 [3]
+    jmp y-- loop0 side 1 [3]
+    out pins 1    side 2 [3]
+```
+
+The I2S example (top/i2s.v) plays a wave file in 16-bit 44100Hz stereo, from BRAM to a Digilent I2S Pmod. It works better on the Ulx3s board, which has more BRAM.

lawrie_fpga_pio/asm/adafruit_pioasm.py

@@ -0,0 +1,165 @@
+# SPDX-FileCopyrightText: Copyright (c) 2021 Scott Shawcroft for Adafruit Industries LLC
+#
+# SPDX-License-Identifier: MIT
+"""
+`adafruit_pioasm`
+================================================================================
+
+Simple assembler to convert pioasm to bytes
+
+
+* Author(s): Scott Shawcroft
+"""
+
+import array
+
+__version__ = "0.0.0-auto.0"
+__repo__ = "https://github.com/adafruit/Adafruit_CircuitPython_PIOASM.git"
+
+CONDITIONS = ["", "!x", "x--", "!y", "y--", "x!=y", "pin", "!osre"]
+IN_SOURCES = ["pins", "x", "y", "null", None, None, "isr", "osr"]
+OUT_DESTINATIONS = ["pins", "x", "y", "null", "pindirs", "pc", "isr", "exec"]
+WAIT_SOURCES = ["gpio", "pin", "irq", None]
+MOV_DESTINATIONS = ["pins", "x", "y", None, "exec", "pc", "isr", "osr"]
+MOV_SOURCES = ["pins", "x", "y", "null", None, "status", "isr", "osr"]
+MOV_OPS = [None, "~", "::", None]
+SET_DESTINATIONS = ["pins", "x", "y", None, "pindirs", None, None, None]
+
+def assemble(text_program):
+    """Converts pioasm text to encoded instruction bytes"""
+    assembled = []
+    program_name = None
+    labels = {}
+    instructions = []
+    sideset_count = 0
+    for line in text_program.split("\n"):
+        line = line.strip()
+        if not line:
+            continue
+        if ";" in line:
+            line = line.split(";")[0].strip()
+        if line.startswith(".program"):
+            if program_name:
+                raise RuntimeError("Multiple programs not supported")
+            program_name = line.split()[1]
+        elif line.startswith(".wrap_target"):
+            if len(instructions) > 0:
+                raise RuntimeError("wrap_target not supported")
+        elif line.startswith(".wrap"):
+            pass
+        elif line.startswith(".side_set"):
+            sideset_count = int(line.split()[1])
+        elif line.endswith(":"):
+            labels[line[:-1]] = len(instructions)
+        else:
+            instructions.append(line)
+
+    max_delay = 2 ** (5 - sideset_count) - 1
+    assembled = []
+    for instruction in instructions:
+        print(instruction)
+        instruction = instruction.split()
+        delay = 0
+        if instruction[-1].endswith("]"): # Delay
+            delay = int(instruction[-1].strip("[]"))
+            if delay > max_delay:
+                raise RuntimeError("Delay too long:", delay)
+            instruction.pop()
+        if len(instruction) > 1 and instruction[-2] == "side":
+            sideset_value = int(instruction[-1])
+            if sideset_value > 2 ** sideset_count:
+                raise RuntimeError("Sideset value too large")
+            delay |= sideset_value << (5 - sideset_count)
+            instruction.pop()
+            instruction.pop()
+
+        if instruction[0] == "nop":
+            #                  mov delay   y op   y
+            assembled.append(0b101_00000_010_00_010)
+        elif instruction[0] == "jmp":
+            #                instr delay cnd addr
+            assembled.append(0b000_00000_000_00000)
+            if instruction[-1] in labels:
+                assembled[-1] |= labels[instruction[-1]]
+            else:
+                assembled[-1] |= int(instruction[-1])
+
+            if len(instruction) > 2:
+                assembled[-1] |= CONDITIONS.index(instruction[1]) << 5
+
+        elif instruction[0] == "wait":
+            #                instr delay p sr index
+            assembled.append(0b001_00000_0_00_00000)
+            polarity = int(instruction[1])
+            if not 0 <= polarity <= 1:
+                raise RuntimeError("Invalid polarity")
+            assembled[-1] |= polarity << 7
+            assembled[-1] |= WAIT_SOURCES.index(instruction[2]) << 4
+            num = int(instruction[3])
+            if not 0 <= num <= 31:
+                raise RuntimeError("Wait num out of range")
+            assembled[-1] |= num
+            if instruction[-1] == "rel":
+                assembled[-1] |= 0x10 # Set the high bit of the irq value
+        elif instruction[0] == "in":
+            #                instr delay src count
+            assembled.append(0b010_00000_000_00000)
+            assembled[-1] |= IN_SOURCES.index(instruction[1]) << 5
+            count = int(instruction[-1])
+            if not 1 <= count <=32:
+                raise RuntimeError("Count out of range")
+            assembled[-1] |= (count & 0x1f) # 32 is 00000 so we mask the top
+        elif instruction[0] == "out":
+            #                instr delay dst count
+            assembled.append(0b011_00000_000_00000)
+            assembled[-1] |= OUT_DESTINATIONS.index(instruction[1]) << 5
+            count = int(instruction[-1])
+            if not 1 <= count <=32:
+                raise RuntimeError("Count out of range")
+            assembled[-1] |= (count & 0x1f) # 32 is 00000 so we mask the top
+        elif instruction[0] == "push" or instruction[0] == "pull":
+            #                instr delay d i b zero
+            assembled.append(0b100_00000_0_0_0_00000)
+            if instruction[0] == "pull":
+                assembled[-1] |= 0x80
+            if instruction[-1] == "block" or not instruction[-1].endswith("block"):
+                assembled[-1] |= 0x20
+            if instruction[1] in ("ifempty", "iffull"):
+                assembled[-1] |= 0x40
+        elif instruction[0] == "mov":
+            #                instr delay dst op src
+            assembled.append(0b101_00000_000_00_000)
+            assembled[-1] |= MOV_DESTINATIONS.index(instruction[1]) << 5
+            assembled[-1] |= MOV_SOURCES.index(instruction[-1])
+            if len(instruction) > 3:
+                assembled[-1] |= MOV_OPS.index(instruction[-2])
+        elif instruction[0] == "irq":
+            #                instr delay z c w index
+            assembled.append(0b110_00000_0_0_0_00000)
+            if instruction[-1] == "rel":
+                assembled[-1] |= 0x10 # Set the high bit of the irq value
+                instruction.pop()
+            num = int(instruction[-1])
+            if not 0 <= num <= 7:
+                raise RuntimeError("Interrupt index out of range")
+            assembled[-1] |= num
+            if len(instruction) == 3: # after rel has been removed
+                if instruction[1] == "wait":
+                    assembled[-1] |= 0x20
+                elif instruction[1] == "clear":
+                    assembled[-1] |= 0x40
+                # All other values are the default of set without waiting
+        elif instruction[0] == "set":
+            #                instr delay dst data
+            assembled.append(0b111_00000_000_00000)
+            assembled[-1] |= SET_DESTINATIONS.index(instruction[1]) << 5
+            value = int(instruction[-1])
+            if not 0 <= value <=31:
+                raise RuntimeError("Set value out of range")
+            assembled[-1] |= value
+        else:
+            raise RuntimeError("Unknown instruction:" + instruction)
+        assembled[-1] |= delay << 8
+        print(hex(assembled[-1]))
+
+    return array.array("H", assembled)

lawrie_fpga_pio/asm/add.asm

@@ -0,0 +1,13 @@
+.program add
+    pull block
+    mov x ~osr
+    pull block
+    mov y osr
+    jmp test
+incr:
+    jmp x-- test
+test:
+    jmp y-- incr
+    mv isr ~x
+    push
+

lawrie_fpga_pio/asm/blink.asm

@@ -0,0 +1,15 @@
+.program blink
+    set pindirs 1
+again:
+    set pins 1 [31]  ; Drive pin high and then delay for 31 cycles
+    nop [31]
+    nop [31]
+    nop [31]
+    nop [31]
+    set pins 0 [30]  ; Drive pin low
+    nop [31]
+    nop [31]
+    nop [31]
+    nop [31]
+    jmp again
+

lawrie_fpga_pio/asm/compile

@@ -0,0 +1,29 @@
+#!/usr/bin/python3
+
+from adafruit_pioasm import assemble
+import sys
+
+args=sys.argv
+
+if len(args) < 3:
+  print("Usage: " + args[0] + " <text program file> <hex program file>")
+  sys.exit(1)
+
+f=open(args[1],"r");
+text = f.read();
+f.close()
+
+bin=assemble(text)
+
+f=open(args[2],"w")
+
+for i in bin:
+  h = format(i,"04x")
+  f.write(h + "\n")
+
+f.close()
+
+
+
+
+

lawrie_fpga_pio/asm/copybit.asm

@@ -0,0 +1,4 @@
+.program copybit
+    pull block
+    out pins 1
+

lawrie_fpga_pio/asm/i2s.asm

@@ -0,0 +1,15 @@
+.program i2s
+.side_set 2
+    pull noblock  side 3
+    mov x osr     side 3
+    set y 14      side 3 [1]
+loop1:
+    out pins 1    side 2 [3]
+    jmp y-- loop1 side 3 [3]
+    out pins 1    side 0 [3]
+    set y 14      side 1 [3]
+loop0:
+    out pins 1    side 0 [3]
+    jmp y-- loop0 side 1 [3]
+    out pins 1    side 2 [3]
+    

lawrie_fpga_pio/asm/pwm.asm

@@ -0,0 +1,13 @@
+.program pwm
+.side_set 1 opt
+    pull noblock    side 0
+    mov x osr
+    mov y isr
+countloop:
+    jmp x!=y noset
+    jmp skip        side 1
+noset:
+    nop
+skip:
+    jmp y-- countloop
+

lawrie_fpga_pio/asm/spi.asm

@@ -0,0 +1,5 @@
+.program spi
+.side_set 1
+    out pins 1 side 0 [1]
+    in  pins 1 side 1 [1]
+

lawrie_fpga_pio/asm/square.asm

@@ -0,0 +1,4 @@
+.program square
+    set pins 1  ; Drive pin high
+    set pins 0  ; Drive pin low
+

lawrie_fpga_pio/asm/step2.asm

@@ -0,0 +1,17 @@
+.program stepper
+    pull block
+    mov isr osr
+    pull block
+    mov y osr
+outer:
+    mov osr isr 
+    set x 6
+inner:
+    out pins 4 [2]
+    jmp x-- inner
+    out pins 4
+    jmp y-- outer
+wrap_target:
+    out pins 4
+    jmp wrap_target
+

lawrie_fpga_pio/asm/stepper.asm

@@ -0,0 +1,9 @@
+.program stepper
+    mov osr isr
+    set x 6
+loop:
+    out pins 4 [1]
+    jmp x-- loop
+    out pins 4
+
+

lawrie_fpga_pio/asm/uart_rx.asm

@@ -0,0 +1,7 @@
+.program uart_rx
+    wait 0 pin 0
+    set x 7       [10]
+again:
+    in pins 1
+    jmp x-- again [6]
+

lawrie_fpga_pio/asm/uart_tx.asm

@@ -0,0 +1,7 @@
+.program uart_tx
+.side_set 1 opt
+    pull block    side 1
+    set x 7       side 0 [7]
+again:
+    out pins 1
+    jmp x-- again        [6]