Add Batch 8 with 1 repos

MaxXSoft_Fuxi/.github/workflows/test.yml

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+name: Test
+
+permissions:
+  contents: read
+
+on:
+  push:
+    branches:
+      - master
+  pull_request:
+    branches:
+      - master
+
+jobs:
+  test:
+    runs-on: ubuntu-latest
+    if: "!contains(github.event.head_commit.message, 'skip-ci')"
+
+    steps:
+    - name: Checkout Fuxi
+      uses: actions/checkout@v6
+
+    - name: Setup JDK
+      uses: actions/setup-java@v5
+      with:
+        distribution: temurin
+        java-version: 17
+        cache: sbt
+
+    - name: Setup sbt
+      uses: sbt/setup-sbt@v1
+
+    # Ubuntu 24.04 ships Verilator 5.020, which mis-simulates the Core
+    # CSR-write/xRET sequence exercised by the mecall trace.
+    - name: Setup Verilator
+      uses: veryl-lang/setup-verilator@b155747595eb4b817473a83045ba1da581c4084b
+      with:
+        version: 5.048
+
+    - name: Check Verilator version
+      run: verilator --version
+
+    - name: Generate Verilog
+      run: make
+
+    - name: Lint generated Verilog
+      run: |
+        verilator --lint-only -Wno-fatal --language 1364-2005 \
+          --top-module FuxiWrapper \
+          verilog/build/Fuxi.v verilog/FuxiWrapper.v
+
+    - name: Test BPU
+      run: sbt "Test / runMain bpu.BranchPredictorTest"
+
+    - name: Test CSR
+      run: sbt "Test / runMain csr.CsrFileTest"
+
+    - name: Test LSU
+      run: |
+        sbt "Test / runMain lsu.AmoExecuteTest"
+        sbt "Test / runMain lsu.ExclusiveMonitorTest"
+
+    - name: Test MDU
+      run: |
+        sbt "Test / runMain mdu.DividerTest"
+        sbt "Test / runMain mdu.MultiplierTest"
+        sbt "Test / runMain mdu.MduTest"
+
+    - name: Test Sim
+      run: sbt "Test / runMain sim.RamTest"
+
+    - name: Test Stages
+      run: |
+        sbt "Test / runMain core.FetchTest"
+        sbt "Test / runMain core.DecoderTest"
+        sbt "Test / runMain core.AluTest"
+        sbt "Test / runMain core.MemTest"
+        sbt "Test / runMain core.WriteBackTest"
+
+    - name: Test Bus
+      run: |
+        sbt "Test / runMain bus.TlbTest"
+        sbt "Test / runMain bus.MmuTest"
+        sbt "Test / runMain bus.UncachedTest"
+        sbt "Test / runMain bus.CoreBusTest"
+
+    - name: Test Core
+      run: |
+        sbt "Test / runMain core.CoreTest -if src/test/resources/fib.txt -tf src/test/resources/fib_trace.txt"
+        sbt "Test / runMain core.CoreTest -if src/test/resources/mdu.txt -tf src/test/resources/mdu_trace.txt"
+        sbt "Test / runMain core.CoreTest -if src/test/resources/mecall.txt -tf src/test/resources/mecall_trace.txt"
+        sbt "Test / runMain core.CoreTest -if src/test/resources/secall.txt -tf src/test/resources/secall_trace.txt"

MaxXSoft_Fuxi/README.md

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+# Fuxi
+
+[![Test](https://github.com/MaxXSoft/Fuxi/workflows/Test/badge.svg)](https://github.com/MaxXSoft/Fuxi)
+
+Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel.
+
+![datapath](img/datapath.svg)
+
+## Implemented ISAs
+
+* RV32I 2.1
+* Zifencei extension 2.0
+* Zicsr extension 2.0
+* M extension 2.0
+* A extension 2.0
+* Machine-level ISA 1.11
+* Supervisor-level ISA 1.11
+
+## Unimplemented Details
+
+Fuxi processor is designed for running [GeeOS](https://github.com/MaxXSoft/GeeOS), or other simple operating systems or bare-metal software. Considering the complexity, the following functions has not yet been implemented:
+
+* Memory privilege in `mstatus` register: `MPRV` bit and `MXR` bit are hardwired to 0.
+* Virtualization support in `mstatus` register: `TVM` bit, `TW` bit and `TSR` bit are hardwired to 0.
+* Physical Memory Protection: all PMP registers are hardwired to 0.
+
+## Performance
+
+With default configuration:
+
+* **Dhrystone 2.1**: 0.60 DMIPS/MHz.
+* **CoreMark**: 2.15 CoreMark/MHz.
+
+## Getting Started
+
+Fuxi currently targets Chisel 7.13.0 and Scala 2.13.18. JDK 17 and sbt are
+recommended for building it; running the unit tests also requires Verilator.
+
+By issuing the following command lines, you can get generated verilog file in directory `verilog/build`:
+
+```
+$ git clone https://github.com/MaxXSoft/Fuxi
+$ cd Fuxi
+$ make
+```
+
+## Running Tests
+
+### Running Unit Tests
+
+All unit tests are available in directory `src/test/scala`. For example, unit test for decode stage is available in `core/DecoderTest.scala`, you can run this test by executing the following command lines:
+
+```
+$ sbt
+> Test / runMain core.DecoderTest
+```
+
+### Running `CoreTest`
+
+`CoreTest` is a special unit test provided in this repository, it can run simple RISC-V programs using the Fuxi core. We also provided some programs in directory `src/test/resources`. For example, you can run one of it:
+
+```
+$ sbt
+> Test / runMain core.CoreTest -if src/test/resources/fib.txt
+```
+
+Trace information during running program `fib.txt` will be printed to the console.
+
+`CoreTest` supports the following command line arguments:
+
+| Option          | Abbreviation  | Argument              | Description
+| -               | -             | -                     | -
+| `--init-file`   | `-if`         | path to program file  | Specify the initialization file of ROM.
+| `--trace-file`  | `-tf`         | path to trace file    | Specify the trace file, default to empty.
+| `--gen-trace`   | `-gt`         | 0 or other values     | Set to 0 for trace comparison, otherwise use Fuxi core to generate trace file. Default to 0.
+
+So you can test the core using a trace file generated by other processor or emulator:
+
+```
+> Test / runMain core.CoreTest -if src/test/resources/fib.txt -tf src/test/resources/fib_trace.txt
+```
+
+For other details, please read [the source file](src/test/scala/core/CoreTest.scala) of `CoreTest.scala`.
+
+All provided programs:
+
+| Name        | Description
+| -           | -
+| fib.txt     | Generate the first 10 terms of the Fibonacci sequence.
+| mdu.txt     | Perform some multiplications and divisions.
+| mecall.txt  | Test machine mode environment call.
+| secall.txt  | Test supervisor mode environment call.
+
+### Running Other Test Benches
+
+> This part is under construction.
+
+As we see in [the top level module](src/main/scala/Fuxi.scala), the complete Fuxi processor consists of `Core` and `CoreBus`, the latter provides MMU, cache system and AXI4 interface for the `Core` part.
+
+All of the unit test cases currently contained in this repository can only test modules in the `Core` part, we are still preparing the test bench the entire processor system. For now, you can build a tiny SoC by yourself based on some AXI4 IP cores to run other test benches you want.
+
+## Copyright and License
+
+Copyright (C) 2010-2020 MaxXing. License GPLv3.
+
+Special thanks to [@Yukiteru Lee](https://github.com/wfly1998/).

MaxXSoft_Fuxi/soc/README.md

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+# Fuxi SoC
+
+Fuxi SoC is a simple system-on-chip based on Fuxi processor. This design can be synthesised and implemented on development board with Xilinx 7 Series FPGA.
+
+Fuxi SoC has already been tested on Loongson FPGA development board (with Xilinx XC7A200TFBG676-2).
+
+## Requirement
+
+* Xilinx Vivado 2018.3.
+* Xilinx FPGA.
+
+## Address Space Mapping of Peripherals
+
+| Peripheral            | Start       | End         | Length  | Type      |
+| -                     | -           | -           | -       | -         |
+| On-chip ROM           | 0x00000000  | 0x0000FFFF  | 64KB    | Memory    |
+| DDR3 Controller       | 0x80000000  | 0x87FFFFFF  | 128MB   | Memory    |
+| CFG Flash Controller  | 0x10000000  | 0x10FFFFFF  | 16MB    | Memory    |
+| CLINT                 | 0x11000000  | 0x11000FFF  | 4KB     | Register  |
+| PLIC                  | 0x11010000  | 0x1101FFFF  | 64KB    | Register  |
+| SPI Flash Controller  | 0x11020000  | 0x11020FFF  | 4KB     | Register  |
+| VGA Controller        | 0x11030000  | 0x1103FFFF  | 64KB    | Register  |
+| UART Controller       | 0x11040000  | 0x11041FFF  | 8KB     | Register  |
+| LCD Controller        | 0x11050000  | 0x11050FFF  | 4KB     | Register  |
+| Ethernet Controller   | 0x11060000  | 0x1106FFFF  | 64KB    | Register  |
+| GPIO Controller       | 0x11070000  | 0x1107FFFF  | 64KB    | Register  |
+
+# References
+
+Fuxi SoC is heavily influenced by SoC part of [NonTrivialMIPS](https://github.com/trivialmips/nontrivial-mips) project.

MaxXSoft_Fuxi/soc/peripherals/clint/AXIBridge.v

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+`timescale 1ns / 1ps
+
+module AXIBridge(
+  input           clk,
+  input           rst_n,
+  // AXI slave interface
+  input   [5:0]   axi_arid,
+  input   [31:0]  axi_araddr,
+  input   [7:0]   axi_arlen,
+  input   [2:0]   axi_arsize,
+  input   [1:0]   axi_arburst,
+  input   [1:0]   axi_arlock,
+  input   [3:0]   axi_arcache,
+  input   [2:0]   axi_arprot,
+  input           axi_arvalid,
+  output          axi_arready,
+  output  [5:0]   axi_rid,
+  output  [31:0]  axi_rdata,
+  output  [1:0]   axi_rresp,
+  output          axi_rlast,
+  output          axi_rvalid,
+  input           axi_rready,
+  input   [5:0]   axi_awid,
+  input   [31:0]  axi_awaddr,
+  input   [7:0]   axi_awlen,
+  input   [2:0]   axi_awsize,
+  input   [1:0]   axi_awburst,
+  input   [1:0]   axi_awlock,
+  input   [3:0]   axi_awcache,
+  input   [2:0]   axi_awprot,
+  input           axi_awvalid,
+  output          axi_awready,
+  input   [5:0]   axi_wid,
+  input   [31:0]  axi_wdata,
+  input   [3:0]   axi_wstrb,
+  input           axi_wlast,
+  input           axi_wvalid,
+  output          axi_wready,
+  output  [5:0]   axi_bid,
+  output  [1:0]   axi_bresp,
+  output          axi_bvalid,
+  input           axi_bready,
+  // general peripheral interface
+  output          gpi_read,
+  output          gpi_write,
+  output  [31:0]  gpi_addr,
+  output  [31:0]  gpi_wdata,
+  input   [31:0]  gpi_rdata
+);
+
+  reg busy, write, r_or_w;
+
+  wire    ar_enter    = axi_arvalid & axi_arready;
+  wire    r_retire    = axi_rvalid  & axi_rready & axi_rlast;
+  wire    r_valid     = busy & r_or_w & !r_retire;
+  wire    aw_enter    = axi_awvalid & axi_awready;
+  wire    w_enter     = axi_wvalid  & axi_wready & axi_wlast;
+  wire    b_retire    = axi_bvalid  & axi_bready;
+
+  assign  axi_arready = ~busy & (!r_or_w | !axi_awvalid);
+  assign  axi_awready = ~busy & ( r_or_w | !axi_arvalid);
+
+  reg [5 :0]  buf_id;
+  reg [31:0]  buf_addr;
+  reg [7 :0]  buf_len;
+  reg [2 :0]  buf_size;
+
+  always @(posedge clk) begin
+    if      (!rst_n             ) busy  <= 1'b0;
+    else if (ar_enter | aw_enter) busy  <= 1'b1;
+    else if (r_retire | b_retire) busy  <= 1'b0;
+  end
+
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      r_or_w    <= 1'b0;
+      buf_id    <= 6'b0;
+      buf_addr  <= 32'h0;
+      buf_len   <= 8'b0;
+      buf_size  <= 3'b0;
+    end
+    else if (ar_enter | aw_enter) begin
+      r_or_w    <= ar_enter;
+      buf_id    <= ar_enter ? axi_arid   : axi_awid  ;
+      buf_addr  <= ar_enter ? axi_araddr : axi_awaddr;
+      buf_len   <= ar_enter ? axi_arlen  : axi_awlen ;
+      buf_size  <= ar_enter ? axi_arsize : axi_awsize;
+    end
+  end
+
+  reg wready_reg;
+  assign  axi_wready  = wready_reg;
+  always @(posedge clk) begin
+    if      (!rst_n             ) wready_reg  <= 1'b0;
+    else if (aw_enter           ) wready_reg  <= 1'b1;
+    else if (w_enter & axi_wlast) wready_reg  <= 1'b0;
+  end
+
+  reg rvalid_reg;
+  reg rlast_reg;
+  assign  axi_rdata   = gpi_rdata;
+  assign  axi_rvalid  = rvalid_reg;
+  assign  axi_rlast   = rlast_reg;
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      rvalid_reg  <= 1'b0;
+      rlast_reg   <= 1'b0;
+    end
+    else if (r_valid) begin
+      rvalid_reg  <= 1'b1;
+      rlast_reg   <= 1'b1;
+    end
+    else if (r_retire) begin
+      rvalid_reg  <= 1'b0;
+    end
+  end
+
+  reg bvalid_reg;
+  assign  axi_bvalid  = bvalid_reg;
+  always @(posedge clk) begin
+    if      (!rst_n   ) bvalid_reg  <= 1'b0;
+    else if (w_enter  ) bvalid_reg  <= 1'b1;
+    else if (b_retire ) bvalid_reg  <= 1'b0;
+  end
+
+  assign  axi_rid     = buf_id;
+  assign  axi_bid     = buf_id;
+  assign  axi_bresp   = 2'b0;
+  assign  axi_rresp   = 2'b0;
+
+  assign  gpi_read    = r_valid;
+  assign  gpi_write   = w_enter;
+  assign  gpi_addr    = gpi_read ? axi_araddr :
+                        gpi_write ? axi_awaddr : 32'h0;
+  assign  gpi_wdata   = axi_wdata;
+
+endmodule

MaxXSoft_Fuxi/soc/peripherals/clint/Clint.v

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+`timescale 1ns / 1ps
+
+/*
+ * CLINT for Fuxi core
+ *
+ *  address:
+ *    0x000: msip
+ *    0x100: mtime lo
+ *    0x104: mtime hi
+ *    0x108: mtimecmp lo
+ *    0x10c: mtimecmp hi
+ */
+module Clint(
+  input           clk,
+  input           clk_rtc,
+  input           rst_n,
+  // AXI slave interface
+  input   [5:0]   axi_arid,
+  input   [31:0]  axi_araddr,
+  input   [7:0]   axi_arlen,
+  input   [2:0]   axi_arsize,
+  input   [1:0]   axi_arburst,
+  input   [1:0]   axi_arlock,
+  input   [3:0]   axi_arcache,
+  input   [2:0]   axi_arprot,
+  input           axi_arvalid,
+  output          axi_arready,
+  output  [5:0]   axi_rid,
+  output  [31:0]  axi_rdata,
+  output  [1:0]   axi_rresp,
+  output          axi_rlast,
+  output          axi_rvalid,
+  input           axi_rready,
+  input   [5:0]   axi_awid,
+  input   [31:0]  axi_awaddr,
+  input   [7:0]   axi_awlen,
+  input   [2:0]   axi_awsize,
+  input   [1:0]   axi_awburst,
+  input   [1:0]   axi_awlock,
+  input   [3:0]   axi_awcache,
+  input   [2:0]   axi_awprot,
+  input           axi_awvalid,
+  output          axi_awready,
+  input   [5:0]   axi_wid,
+  input   [31:0]  axi_wdata,
+  input   [3:0]   axi_wstrb,
+  input           axi_wlast,
+  input           axi_wvalid,
+  output          axi_wready,
+  output  [5:0]   axi_bid,
+  output  [1:0]   axi_bresp,
+  output          axi_bvalid,
+  input           axi_bready,
+  // interrupt signals
+  output          intr_timer,
+  output          intr_soft
+);
+
+  // address
+  localparam      ADDR_MSIP     = 12'h000;
+  localparam      ADDR_MTIME    = 12'h100,  ADDR_MTIMEH     = 12'h104;
+  localparam      ADDR_MTIMECMP = 12'h108,  ADDR_MTIMECMPH  = 12'h10c;
+
+
+  // convert AXI to peripheral interface
+  wire            gpi_read, gpi_write;
+  wire  [31:0]    gpi_addr, gpi_wdata;
+  wire  [11:0]    gpi_peri_addr;
+  reg   [31:0]    gpi_rdata;
+
+  assign gpi_peri_addr = gpi_addr[11:0];
+
+  AXIBridge axi_bridge(
+    .clk          (clk),
+    .rst_n        (rst_n),
+
+    .axi_arid     (axi_arid),
+    .axi_araddr   (axi_araddr),
+    .axi_arlen    (axi_arlen),
+    .axi_arsize   (axi_arsize),
+    .axi_arburst  (axi_arburst),
+    .axi_arlock   (axi_arlock),
+    .axi_arcache  (axi_arcache),
+    .axi_arprot   (axi_arprot),
+    .axi_arvalid  (axi_arvalid),
+    .axi_arready  (axi_arready),
+    .axi_rid      (axi_rid),
+    .axi_rdata    (axi_rdata),
+    .axi_rresp    (axi_rresp),
+    .axi_rlast    (axi_rlast),
+    .axi_rvalid   (axi_rvalid),
+    .axi_rready   (axi_rready),
+    .axi_awid     (axi_awid),
+    .axi_awaddr   (axi_awaddr),
+    .axi_awlen    (axi_awlen),
+    .axi_awsize   (axi_awsize),
+    .axi_awburst  (axi_awburst),
+    .axi_awlock   (axi_awlock),
+    .axi_awcache  (axi_awcache),
+    .axi_awprot   (axi_awprot),
+    .axi_awvalid  (axi_awvalid),
+    .axi_awready  (axi_awready),
+    .axi_wid      (axi_wid),
+    .axi_wdata    (axi_wdata),
+    .axi_wstrb    (axi_wstrb),
+    .axi_wlast    (axi_wlast),
+    .axi_wvalid   (axi_wvalid),
+    .axi_wready   (axi_wready),
+    .axi_bid      (axi_bid),
+    .axi_bresp    (axi_bresp),
+    .axi_bvalid   (axi_bvalid),
+    .axi_bready   (axi_bready),
+
+    .gpi_read     (gpi_read),
+    .gpi_write    (gpi_write),
+    .gpi_addr     (gpi_addr),
+    .gpi_wdata    (gpi_wdata),
+    .gpi_rdata    (gpi_rdata)
+  );
+
+
+  // registers
+  reg           msip;
+  reg   [31:0]  mtime, mtime_r1, mtime_r2;
+  reg   [31:0]  mtimeh, mtimeh_r1, mtimeh_r2;
+  reg   [31:0]  mtimecmp, mtimecmph;
+  wire  [63:0]  mtime_full, next_mtime_full;
+  wire  [31:0]  next_mtime, next_mtimeh;
+
+  assign mtime_full       = {mtimeh, mtime};
+  assign next_mtime_full  = mtime_full + 64'b1;
+  assign next_mtime       = next_mtime_full[31:0];
+  assign next_mtimeh      = next_mtime_full[63:32];
+
+
+  // interrupt signal output
+  wire  [63:0]  mtime_r2_full, mtimecmp_full;
+  reg           timer_intr;
+
+  assign mtime_r2_full  = {mtimeh_r2, mtime_r2};
+  assign mtimecmp_full  = {mtimecmph, mtimecmp};
+  assign intr_soft      = msip;
+  assign intr_timer     = timer_intr;
+
+  always @(posedge clk) begin
+    timer_intr <= mtime_r2_full >= mtimecmp_full;
+  end
+
+
+  // peripheral read
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      gpi_rdata <= 32'h0;
+    end
+    else if (gpi_read) begin
+      case (gpi_peri_addr)
+        ADDR_MSIP:      gpi_rdata <=  {31'b0, msip};
+        ADDR_MTIME:     gpi_rdata <=  mtime_r2;
+        ADDR_MTIMEH:    gpi_rdata <=  mtimeh_r2;
+        ADDR_MTIMECMP:  gpi_rdata <=  mtimecmp;
+        ADDR_MTIMECMPH: gpi_rdata <=  mtimecmph;
+        default:        gpi_rdata <= 32'h0;
+      endcase
+    end
+  end
+
+
+  // software interrupt
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      msip <= 1'b0;
+    end
+    else if (gpi_write && gpi_peri_addr == ADDR_MSIP) begin
+      msip <= gpi_wdata[0];
+    end
+  end
+
+
+  // mtime register write/update
+  reg         write_mtime_begin, write_mtime_begin_r1;
+  reg         write_mtime_begin_r2, write_mtime_begin_r3;
+  reg         write_mtime_end_r1, write_mtime_end_r2;
+  reg [31:0]  mtime_wdata, mtime_wdata_r1, mtime_wdata_r2;
+  wire        write_mtime = gpi_write && gpi_peri_addr == ADDR_MTIME;
+
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      write_mtime_begin   <= 1'b0;
+    end
+    else if (write_mtime) begin
+      write_mtime_begin   <= 1'b1;
+      mtime_wdata         <= gpi_wdata;
+    end
+    else if (write_mtime_end_r2) begin
+      write_mtime_begin   <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    write_mtime_end_r1    <= write_mtime_begin_r2;
+    write_mtime_end_r2    <= write_mtime_end_r1;
+    mtime_r1              <= mtime;
+    mtime_r2              <= mtime_r1;
+  end
+
+  always @(posedge clk_rtc) begin
+    write_mtime_begin_r1  <= write_mtime_begin;
+    write_mtime_begin_r2  <= write_mtime_begin_r1;
+    write_mtime_begin_r3  <= write_mtime_begin_r2;
+    mtime_wdata_r1        <= mtime_wdata;
+    mtime_wdata_r2        <= mtime_wdata_r1;
+  end
+
+  always @(posedge clk_rtc) begin
+    if (!rst_n) begin
+      mtime <= 32'h0;
+    end
+    else if (write_mtime_begin_r2 && !write_mtime_begin_r3) begin
+      mtime <= mtime_wdata_r2;
+    end
+    else begin
+      mtime <= next_mtime;
+    end
+  end
+
+
+  // mtimeh register write/update
+  reg         write_mtimeh_begin, write_mtimeh_begin_r1;
+  reg         write_mtimeh_begin_r2, write_mtimeh_begin_r3;
+  reg         write_mtimeh_end_r1, write_mtimeh_end_r2;
+  reg [31:0]  mtimeh_wdata, mtimeh_wdata_r1, mtimeh_wdata_r2;
+  wire        write_mtimeh = gpi_write && gpi_peri_addr == ADDR_MTIMEH;
+
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      write_mtimeh_begin  <= 1'b0;
+    end
+    else if (write_mtimeh) begin
+      write_mtimeh_begin  <= 1'b1;
+      mtimeh_wdata        <= gpi_wdata;
+    end
+    else if (write_mtimeh_end_r2) begin
+      write_mtimeh_begin  <= 1'b0;
+    end
+  end
+
+  always @(posedge clk) begin
+    write_mtimeh_end_r1   <= write_mtimeh_begin_r2;
+    write_mtimeh_end_r2   <= write_mtimeh_end_r1;
+    mtimeh_r1             <= mtimeh;
+    mtimeh_r2             <= mtimeh_r1;
+  end
+
+  always @(posedge clk_rtc) begin
+    write_mtimeh_begin_r1 <= write_mtimeh_begin;
+    write_mtimeh_begin_r2 <= write_mtimeh_begin_r1;
+    write_mtimeh_begin_r3 <= write_mtimeh_begin_r2;
+    mtimeh_wdata_r1       <= mtimeh_wdata;
+    mtimeh_wdata_r2       <= mtimeh_wdata_r1;
+  end
+
+  always @(posedge clk_rtc) begin
+    if (!rst_n) begin
+      mtimeh <= 32'h0;
+    end
+    else if (write_mtimeh_begin_r2 && !write_mtimeh_begin_r3) begin
+      mtimeh <= mtimeh_wdata_r2;
+    end
+    else begin
+      mtimeh <= next_mtimeh;
+    end
+  end
+
+
+  // mtimecmp register write
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      mtimecmp <= 32'h0;
+    end
+    else if (gpi_write && gpi_peri_addr == ADDR_MTIMECMP) begin
+      mtimecmp <= gpi_wdata;
+    end
+  end
+
+  // mtimecmph register write
+  always @(posedge clk) begin
+    if (!rst_n) begin
+      mtimecmph <= 32'h0;
+    end
+    else if (gpi_write && gpi_peri_addr == ADDR_MTIMECMPH) begin
+      mtimecmph <= gpi_wdata;
+    end
+  end
+
+endmodule

MaxXSoft_Fuxi/soc/peripherals/ddr/ResetSynchronizer.v

@@ -0,0 +1,42 @@
+// from https://github.com/trivialmips/nontrivial-mips
+// modified by: MaxXing, 2019-11
+
+`timescale 1ns / 1ps
+
+module ResetSynchronizer #(
+  parameter RESET_STAGE = 3,
+  parameter RESET_POSEDGE = 0
+) (
+  input   clk,
+  input   rst_i,
+  output  rst_o
+);
+
+  reg [RESET_STAGE - 1:0] reset_sync;
+
+  assign rst_o = reset_sync[RESET_STAGE - 1];
+
+  generate
+    if (RESET_POSEDGE == 0) begin: reset_negedge
+      always @(posedge clk, negedge rst_i) begin
+        if (!rst_i) begin
+          reset_sync <= {RESET_STAGE{1'b0}};
+        end
+        else begin
+          reset_sync <= {reset_sync[RESET_STAGE - 2:0], 1'b1};
+        end
+      end
+    end
+    else begin: reset_posedge
+      always @(posedge clk, posedge rst_i) begin
+        if (rst_i) begin
+          reset_sync <= {RESET_STAGE{1'b1}};
+        end
+        else begin
+          reset_sync <= {reset_sync[RESET_STAGE - 2:0], 1'b0};
+        end
+      end
+    end
+  endgenerate
+
+endmodule // ResetSynchronizer

MaxXSoft_Fuxi/soc/peripherals/gpio/confreg.v

@@ -0,0 +1,851 @@
+/*------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+Copyright (c) 2016, Loongson Technology Corporation Limited.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this
+list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation and/or
+other materials provided with the distribution.
+
+3. Neither the name of Loongson Technology Corporation Limited nor the names of
+its contributors may be used to endorse or promote products derived from this
+software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
+TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--------------------------------------------------------------------------------
+------------------------------------------------------------------------------*/
+
+//*************************************************************************
+//   > File Name   : confreg.v
+//   > Description : Control module of
+//                   16 red leds, 2 green/red leds,
+//                   7-segment display,
+//                   switchs,
+//                   key board,
+//                   bottom STEP,
+//                   timer.
+//
+//   > Author      : LOONGSON
+//   > Date        : 2017-08-04
+//   > Author      : Harry Chen
+//   > Date        : 2019-08
+//   > Author      : MaxXing
+//   > Date        : 2019-11
+//*************************************************************************
+`define RANDOM_SEED {7'b1010101,16'h00FF}
+
+`define CR0_ADDR       16'h8000   //32'hbfaf_8000
+`define CR1_ADDR       16'h8004   //32'hbfaf_8004
+`define CR2_ADDR       16'h8008   //32'hbfaf_8008
+`define CR3_ADDR       16'h800c   //32'hbfaf_800c
+`define CR4_ADDR       16'h8010   //32'hbfaf_8010
+`define CR5_ADDR       16'h8014   //32'hbfaf_8014
+`define CR6_ADDR       16'h8018   //32'hbfaf_8018
+`define CR7_ADDR       16'h801c   //32'hbfaf_801c
+
+`define LED_ADDR       16'hf000   //32'hbfaf_f000
+`define LED_RG0_ADDR   16'hf004   //32'hbfaf_f004
+`define LED_RG1_ADDR   16'hf008   //32'hbfaf_f008
+`define NUM_ADDR       16'hf010   //32'hbfaf_f010
+`define SWITCH_ADDR    16'hf020   //32'hbfaf_f020
+`define BTN_KEY_ADDR   16'hf024   //32'hbfaf_f024
+`define BTN_STEP_ADDR  16'hf028   //32'hbfaf_f028
+`define SW_INTER_ADDR  16'hf02c   //32'hbfaf_f02c
+`define TIMER_ADDR     16'he000   //32'hbfaf_e000
+
+`define IO_SIMU_ADDR      16'hffec  //32'hbfaf_ffec
+`define VIRTUAL_UART_ADDR 16'hfff0  //32'hbfaf_fff0
+`define SIMU_FLAG_ADDR    16'hfff4  //32'hbfaf_fff4
+`define OPEN_TRACE_ADDR   16'hfff8  //32'hbfaf_fff8
+`define NUM_MONITOR_ADDR  16'hfffc  //32'hbfaf_fffc
+module confreg #(
+    parameter SIMULATION=1'b0,
+    parameter BUS_WIDTH=6
+)
+(
+    input             aclk,
+    input             timer_clk,
+    input             aresetn,
+    // read and write from cpu
+    //ar
+    input  [BUS_WIDTH - 1 :0] arid   ,
+    input  [31:0] araddr ,
+    input  [7 :0] arlen  ,
+    input  [2 :0] arsize ,
+    input  [1 :0] arburst,
+    input  [1 :0] arlock ,
+    input  [3 :0] arcache,
+    input  [2 :0] arprot ,
+    input         arvalid,
+    output        arready,
+    //r
+    output [BUS_WIDTH - 1 :0] rid    ,
+    output [31:0] rdata  ,
+    output [1 :0] rresp  ,
+    output        rlast  ,
+    output        rvalid ,
+    input         rready ,
+    //aw
+    input  [BUS_WIDTH - 1  :0] awid   ,
+    input  [31:0] awaddr ,
+    input  [7 :0] awlen  ,
+    input  [2 :0] awsize ,
+    input  [1 :0] awburst,
+    input  [1 :0] awlock ,
+    input  [3 :0] awcache,
+    input  [2 :0] awprot ,
+    input         awvalid,
+    output        awready,
+    //w
+    input  [BUS_WIDTH - 1  :0] wid    ,
+    input  [31:0] wdata  ,
+    input  [3 :0] wstrb  ,
+    input         wlast  ,
+    input         wvalid ,
+    output        wready ,
+    //b
+    output [BUS_WIDTH - 1  :0] bid    ,
+    output [1 :0] bresp  ,
+    output        bvalid ,
+    input         bready ,
+
+    //for lab6
+    output     [4 :0] ram_random_mask  ,
+
+    // read and write to device on board
+    output     [15:0] led,
+    output     [1 :0] led_rg0,
+    output     [1 :0] led_rg1,
+    output reg [7 :0] num_csn,
+    output reg [6 :0] num_a_g,
+    input      [7 :0] switch,
+    output     [3 :0] btn_key_col,
+    input      [3 :0] btn_key_row,
+    input      [1 :0] btn_step,
+
+    // user-defined contents
+    output     [31:0] user_cr0,
+    output     [31:0] user_cr1
+);
+    reg  [31:0] cr0;
+    reg  [31:0] cr1;
+    reg  [31:0] cr2;
+    reg  [31:0] cr3;
+    reg  [31:0] cr4;
+    reg  [31:0] cr5;
+    reg  [31:0] cr6;
+    reg  [31:0] cr7;
+
+    reg  [31:0] led_data;
+    reg  [31:0] led_rg0_data;
+    reg  [31:0] led_rg1_data;
+    reg  [31:0] num_data;
+    wire [31:0] switch_data;
+    wire [31:0] sw_inter_data; //switch interleave
+    wire [31:0] btn_key_data;
+    wire [31:0] btn_step_data;
+    reg  [31:0] timer_r2;
+    reg  [31:0] simu_flag;
+    reg  [31:0] io_simu;
+    reg  [7 :0] virtual_uart_data;
+    reg         open_trace;
+    reg         num_monitor;
+
+    // user-defined contents
+    assign user_cr0 = cr0;
+    assign user_cr1 = cr1;
+
+//--------------------------{axi interface}begin-------------------------//
+    reg busy,write,R_or_W;
+    reg s_wready;
+
+    wire ar_enter = arvalid & arready;
+    wire r_retire = rvalid  & rready & rlast;
+    wire aw_enter = awvalid & awready;
+    wire w_enter  = wvalid  & wready & wlast;
+    wire b_retire = bvalid  & bready;
+
+    assign arready = ~busy & (!R_or_W| !awvalid);
+    assign awready = ~busy & ( R_or_W| !arvalid);
+
+    reg [BUS_WIDTH - 1  :0] buf_id;
+    reg [31:0] buf_addr;
+    reg [7 :0] buf_len;
+    reg [2 :0] buf_size;
+
+    always @(posedge aclk)
+    begin
+        if(~aresetn) busy <= 1'b0;
+        else if(ar_enter|aw_enter) busy <= 1'b1;
+        else if(r_retire|b_retire) busy <= 1'b0;
+    end
+
+    always @(posedge aclk)
+    begin
+        if(~aresetn)
+        begin
+            R_or_W      <= 1'b0;
+            buf_id      <= 6'b0;
+            buf_addr    <= 32'b0;
+            buf_len     <= 8'b0;
+            buf_size    <= 3'b0;
+        end
+        else
+        if(ar_enter | aw_enter)
+        begin
+            R_or_W      <= ar_enter;
+            buf_id      <= ar_enter ? arid   : awid   ;
+            buf_addr    <= ar_enter ? araddr : awaddr ;
+            buf_len     <= ar_enter ? arlen  : awlen  ;
+            buf_size    <= ar_enter ? arsize : awsize ;
+        end
+    end
+
+    reg conf_wready_reg;
+    assign wready = conf_wready_reg;
+    always@(posedge aclk)
+    begin
+        if     (~aresetn       ) conf_wready_reg <= 1'b0;
+        else if(aw_enter       ) conf_wready_reg <= 1'b1;
+        else if(w_enter & wlast) conf_wready_reg <= 1'b0;
+    end
+
+    // read data has one cycle delay
+    reg [31:0] conf_rdata_reg;
+    reg        conf_rvalid_reg;
+    reg        conf_rlast_reg;
+    assign rdata  = conf_rdata_reg;
+    assign rvalid = conf_rvalid_reg;
+    assign rlast  = conf_rlast_reg;
+    always @(posedge aclk)
+    begin
+        if(~aresetn)
+        begin
+            conf_rdata_reg  <= 32'd0;
+            conf_rvalid_reg <= 1'd0;
+            conf_rlast_reg  <= 1'd0;
+        end
+        else if(busy & R_or_W & !r_retire)
+        begin
+            conf_rvalid_reg <= 1'd1;
+            conf_rlast_reg  <= 1'd1;
+            case (buf_addr[15:0])
+                `CR0_ADDR      : conf_rdata_reg <= cr0          ;
+                `CR1_ADDR      : conf_rdata_reg <= cr1          ;
+                `CR2_ADDR      : conf_rdata_reg <= cr2          ;
+                `CR3_ADDR      : conf_rdata_reg <= cr3          ;
+                `CR4_ADDR      : conf_rdata_reg <= cr4          ;
+                `CR5_ADDR      : conf_rdata_reg <= cr5          ;
+                `CR6_ADDR      : conf_rdata_reg <= cr6          ;
+                `CR7_ADDR      : conf_rdata_reg <= cr7          ;
+                `LED_ADDR      : conf_rdata_reg <= led_data     ;
+                `LED_RG0_ADDR  : conf_rdata_reg <= led_rg0_data ;
+                `LED_RG1_ADDR  : conf_rdata_reg <= led_rg1_data ;
+                `NUM_ADDR      : conf_rdata_reg <= num_data     ;
+                `SWITCH_ADDR   : conf_rdata_reg <= switch_data  ;
+                `BTN_KEY_ADDR  : conf_rdata_reg <= btn_key_data ;
+                `BTN_STEP_ADDR : conf_rdata_reg <= btn_step_data;
+                `SW_INTER_ADDR : conf_rdata_reg <= sw_inter_data;
+                `TIMER_ADDR    : conf_rdata_reg <= timer_r2     ;
+                `SIMU_FLAG_ADDR: conf_rdata_reg <= simu_flag    ;
+                `IO_SIMU_ADDR  : conf_rdata_reg <= io_simu      ;
+                `VIRTUAL_UART_ADDR : conf_rdata_reg <= {24'd0,virtual_uart_data} ;
+                `OPEN_TRACE_ADDR : conf_rdata_reg <= {31'd0,open_trace} ;
+                `NUM_MONITOR_ADDR: conf_rdata_reg <= {31'd0,num_monitor} ;
+                default        : conf_rdata_reg <= 32'd0;
+            endcase
+        end
+        else if(r_retire)
+        begin
+            conf_rvalid_reg <= 1'b0;
+        end
+    end
+
+    //conf write, only support a word write
+    wire        conf_we;
+    wire [31:0] conf_addr;
+    wire [31:0] conf_wdata;
+    assign conf_we   = w_enter;
+    assign conf_addr = buf_addr;
+    assign conf_wdata= wdata;
+
+    reg conf_bvalid_reg;
+    assign bvalid = conf_bvalid_reg;
+    always @(posedge aclk)
+    begin
+        if     (~aresetn) conf_bvalid_reg <= 1'b0;
+        else if(w_enter ) conf_bvalid_reg <= 1'b1;
+        else if(b_retire) conf_bvalid_reg <= 1'b0;
+    end
+
+    assign rid   = buf_id;
+    assign bid   = buf_id;
+    assign bresp = 2'b0;
+    assign rresp = 2'b0;
+//---------------------------{axi interface}end--------------------------//
+
+//-------------------------{confreg register}begin-----------------------//
+wire write_cr0 = conf_we & (conf_addr[15:0]==`CR0_ADDR);
+wire write_cr1 = conf_we & (conf_addr[15:0]==`CR1_ADDR);
+wire write_cr2 = conf_we & (conf_addr[15:0]==`CR2_ADDR);
+wire write_cr3 = conf_we & (conf_addr[15:0]==`CR3_ADDR);
+wire write_cr4 = conf_we & (conf_addr[15:0]==`CR4_ADDR);
+wire write_cr5 = conf_we & (conf_addr[15:0]==`CR5_ADDR);
+wire write_cr6 = conf_we & (conf_addr[15:0]==`CR6_ADDR);
+wire write_cr7 = conf_we & (conf_addr[15:0]==`CR7_ADDR);
+always @(posedge aclk)
+begin
+    cr0 <= !aresetn    ? 32'd0      :
+           write_cr0 ? conf_wdata : cr0;
+    cr1 <= !aresetn    ? 32'd0      :
+           write_cr1 ? conf_wdata : cr1;
+    cr2 <= !aresetn    ? 32'd0      :
+           write_cr2 ? conf_wdata : cr2;
+    cr3 <= !aresetn    ? 32'd0      :
+           write_cr3 ? conf_wdata : cr3;
+    cr4 <= !aresetn    ? 32'd0      :
+           write_cr4 ? conf_wdata : cr4;
+    cr5 <= !aresetn    ? 32'd0      :
+           write_cr5 ? conf_wdata : cr5;
+    cr6 <= !aresetn    ? 32'd0      :
+           write_cr6 ? conf_wdata : cr6;
+    cr7 <= !aresetn    ? 32'd0      :
+           write_cr7 ? conf_wdata : cr7;
+end
+//--------------------------{confreg register}end------------------------//
+
+//-------------------------------{timer}begin----------------------------//
+reg         write_timer_begin,write_timer_begin_r1, write_timer_begin_r2,write_timer_begin_r3;
+reg         write_timer_end_r1, write_timer_end_r2;
+reg  [31:0] conf_wdata_r, conf_wdata_r1,conf_wdata_r2;
+
+reg  [31:0] timer_r1;
+reg  [31:0] timer;
+
+wire write_timer = conf_we & (conf_addr[15:0]==`TIMER_ADDR);
+always @(posedge aclk)
+begin
+    if (!aresetn)
+    begin
+        write_timer_begin <= 1'b0;
+    end
+    else if (write_timer)
+    begin
+        write_timer_begin <= 1'b1;
+        conf_wdata_r      <= conf_wdata;
+    end
+    else if (write_timer_end_r2)
+    begin
+        write_timer_begin <= 1'b0;
+    end
+
+    write_timer_end_r1 <= write_timer_begin_r2;
+    write_timer_end_r2 <= write_timer_end_r1;
+end
+
+always @(posedge timer_clk)
+begin
+    write_timer_begin_r1 <= write_timer_begin;
+    write_timer_begin_r2 <= write_timer_begin_r1;
+    write_timer_begin_r3 <= write_timer_begin_r2;
+    conf_wdata_r1        <= conf_wdata_r;
+    conf_wdata_r2        <= conf_wdata_r1;
+
+    if(!aresetn)
+    begin
+        timer <= 32'd0;
+    end
+    else if (write_timer_begin_r2 && !write_timer_begin_r3)
+    begin
+        timer <= conf_wdata_r2[31:0];
+    end
+    else
+    begin
+        timer <= timer + 1'b1;
+    end
+end
+
+always @(posedge aclk)
+begin
+    timer_r1 <= timer;
+    timer_r2 <= timer_r1;
+end
+//--------------------------------{timer}end-----------------------------//
+
+//--------------------------{simulation flag}begin-----------------------//
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        simu_flag <= {32{SIMULATION}};
+    end
+end
+//---------------------------{simulation flag}end------------------------//
+
+//---------------------------{io simulation}begin------------------------//
+wire write_io_simu = conf_we & (conf_addr[15:0]==`IO_SIMU_ADDR);
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        io_simu <= 32'd0;
+    end
+    else if(write_io_simu)
+    begin
+        io_simu <= {conf_wdata[15:0],conf_wdata[31:16]};
+    end
+end
+//----------------------------{io simulation}end-------------------------//
+
+//-----------------------------{open trace}begin-------------------------//
+wire write_open_trace = conf_we & (conf_addr[15:0]==`OPEN_TRACE_ADDR);
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        open_trace <= 1'b1;
+    end
+    else if(write_open_trace)
+    begin
+        open_trace <= |conf_wdata;
+    end
+end
+//-----------------------------{open trace}end---------------------------//
+
+//----------------------------{num monitor}begin-------------------------//
+wire write_num_monitor = conf_we & (conf_addr[15:0]==`NUM_MONITOR_ADDR);
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        num_monitor <= 1'b1;
+    end
+    else if(write_num_monitor)
+    begin
+        num_monitor <= conf_wdata[0];
+    end
+end
+//----------------------------{num monitor}end---------------------------//
+
+//---------------------------{virtual uart}begin-------------------------//
+wire [7:0] write_uart_data;
+wire write_uart_valid  = conf_we & (conf_addr[15:0]==`VIRTUAL_UART_ADDR);
+assign write_uart_data = conf_wdata[7:0];
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        virtual_uart_data <= 8'd0;
+    end
+    else if(write_uart_valid)
+    begin
+        virtual_uart_data <= write_uart_data;
+    end
+end
+//----------------------------{virtual uart}end--------------------------//
+
+//--------------------------{axirandom mask}begin------------------------//
+wire [15:0] switch_led;
+wire [15:0] led_r_n;
+assign led_r_n = ~switch_led;
+
+reg [22:0] pseudo_random_23;
+reg        no_mask;     //if led_r_n is all 1, no mask
+reg        short_delay; //memory long delay
+always @ (posedge aclk)
+begin
+   if (!aresetn)
+       pseudo_random_23 <= simu_flag[0] ? `RANDOM_SEED : {7'b1010101,led_r_n};
+   else
+       pseudo_random_23 <= {pseudo_random_23[21:0],pseudo_random_23[22] ^ pseudo_random_23[17]};
+
+   if(!aresetn)
+       no_mask <= pseudo_random_23[15:0]==16'h00FF;
+
+   if(!aresetn)
+       short_delay <= pseudo_random_23[7:0]==8'hFF;
+end
+assign ram_random_mask[0] = (pseudo_random_23[10]&pseudo_random_23[20]) & (short_delay|(pseudo_random_23[11]^pseudo_random_23[5]))
+                          | no_mask;
+assign ram_random_mask[1] = (pseudo_random_23[ 9]&pseudo_random_23[17]) & (short_delay|(pseudo_random_23[12]^pseudo_random_23[4]))
+                          | no_mask;
+assign ram_random_mask[2] = (pseudo_random_23[ 8]^pseudo_random_23[22]) & (short_delay|(pseudo_random_23[13]^pseudo_random_23[3]))
+                          | no_mask;
+assign ram_random_mask[3] = (pseudo_random_23[ 7]&pseudo_random_23[19]) & (short_delay|(pseudo_random_23[14]^pseudo_random_23[2]))
+                          | no_mask;
+assign ram_random_mask[4] = (pseudo_random_23[ 6]^pseudo_random_23[16]) & (short_delay|(pseudo_random_23[15]^pseudo_random_23[1]))
+                          | no_mask;
+
+//---------------------------{axirandom mask}end-------------------------//
+
+//--------------------------------{led}begin-----------------------------//
+//led display
+//led_data[31:0]
+wire write_led = conf_we & (conf_addr[15:0]==`LED_ADDR);
+
+assign led = led_data[15:0];
+
+assign switch_led = {{2{switch[7]}},{2{switch[6]}},{2{switch[5]}},{2{switch[4]}},
+                    {2{switch[3]}},{2{switch[2]}},{2{switch[1]}},{2{switch[0]}}};
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        led_data <= {16'h0,switch_led};
+    end
+    else if(write_led)
+    begin
+        led_data <= conf_wdata[31:0];
+    end
+end
+//---------------------------------{led}end------------------------------//
+
+//-------------------------------{switch}begin---------------------------//
+//switch data
+//switch_data[7:0]
+assign switch_data   = {24'd0,switch};
+assign sw_inter_data = {16'd0,
+                        switch[7],1'b0,switch[6],1'b0,
+                        switch[5],1'b0,switch[4],1'b0,
+                        switch[3],1'b0,switch[2],1'b0,
+                        switch[1],1'b0,switch[0],1'b0};
+//--------------------------------{switch}end----------------------------//
+
+//------------------------------{btn key}begin---------------------------//
+//btn key data
+reg [15:0] btn_key_r;
+assign btn_key_data = {16'd0,btn_key_r};
+
+//state machine
+reg  [2:0] state;
+wire [2:0] next_state;
+
+//eliminate jitter
+reg        key_flag;
+reg [19:0] key_count;
+reg [ 3:0] state_count;
+wire key_start = (state==3'b000) && !(&btn_key_row);
+wire key_end   = (state==3'b111) &&  (&btn_key_row);
+wire key_sample= key_count[19];
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        key_flag <= 1'd0;
+    end
+    else if (key_sample && state_count[3])
+    begin
+        key_flag <= 1'b0;
+    end
+    else if( key_start || key_end )
+    begin
+        key_flag <= 1'b1;
+    end
+
+    if(!aresetn || !key_flag)
+    begin
+        key_count <= 20'd0;
+    end
+    else
+    begin
+        key_count <= key_count + 1'b1;
+    end
+end
+
+always @(posedge aclk)
+begin
+    if(!aresetn || state_count[3])
+    begin
+        state_count <= 4'd0;
+    end
+    else
+    begin
+        state_count <= state_count + 1'b1;
+    end
+end
+
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        state <= 3'b000;
+    end
+    else if (state_count[3])
+    begin
+        state <= next_state;
+    end
+end
+
+assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
+                    (state == 3'b001) ? (                !(&btn_key_row)  ? 3'b111 : 3'b010 ) :
+                    (state == 3'b010) ? (                !(&btn_key_row)  ? 3'b111 : 3'b011 ) :
+                    (state == 3'b011) ? (                !(&btn_key_row)  ? 3'b111 : 3'b100 ) :
+                    (state == 3'b100) ? (                !(&btn_key_row)  ? 3'b111 : 3'b000 ) :
+                    (state == 3'b111) ? ( (key_sample &&  (&btn_key_row)) ? 3'b000 : 3'b111 ) :
+                                                                                        3'b000;
+assign btn_key_col = (state == 3'b000) ? 4'b0000:
+                     (state == 3'b001) ? 4'b1110:
+                     (state == 3'b010) ? 4'b1101:
+                     (state == 3'b011) ? 4'b1011:
+                     (state == 3'b100) ? 4'b0111:
+                                         4'b0000;
+wire [15:0] btn_key_tmp;
+always @(posedge aclk) begin
+    if(!aresetn) begin
+        btn_key_r   <= 16'd0;
+    end
+    else if(next_state==3'b000)
+    begin
+        btn_key_r   <=16'd0;
+    end
+    else if(next_state == 3'b111 && state != 3'b111) begin
+        btn_key_r   <= btn_key_tmp;
+    end
+end
+
+assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
+                     (state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
+                     (state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
+                     (state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
+                     (state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
+                     (state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
+                     (state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
+                     (state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
+                     (state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
+                     (state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
+                     (state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
+                     (state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
+                     (state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
+                     (state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
+                     (state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
+                     (state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
+//-------------------------------{btn key}end----------------------------//
+
+//-----------------------------{btn step}begin---------------------------//
+//btn step data
+reg btn_step0_r; //0:press
+reg btn_step1_r; //0:press
+assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
+
+//-----step0
+//eliminate jitter
+reg        step0_flag;
+reg [19:0] step0_count;
+wire step0_start = btn_step0_r && !btn_step[0];
+wire step0_end   = !btn_step0_r && btn_step[0];
+wire step0_sample= step0_count[19];
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        step0_flag <= 1'd0;
+    end
+    else if (step0_sample)
+    begin
+        step0_flag <= 1'b0;
+    end
+    else if( step0_start || step0_end )
+    begin
+        step0_flag <= 1'b1;
+    end
+
+    if(!aresetn || !step0_flag)
+    begin
+        step0_count <= 20'd0;
+    end
+    else
+    begin
+        step0_count <= step0_count + 1'b1;
+    end
+
+    if(!aresetn)
+    begin
+        btn_step0_r <= 1'b1;
+    end
+    else if(step0_sample)
+    begin
+        btn_step0_r <= btn_step[0];
+    end
+end
+
+//-----step1
+//eliminate jitter
+reg        step1_flag;
+reg [19:0] step1_count;
+wire step1_start = btn_step1_r && !btn_step[1];
+wire step1_end   = !btn_step1_r && btn_step[1];
+wire step1_sample= step1_count[19];
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        step1_flag <= 1'd0;
+    end
+    else if (step1_sample)
+    begin
+        step1_flag <= 1'b0;
+    end
+    else if( step1_start || step1_end )
+    begin
+        step1_flag <= 1'b1;
+    end
+
+    if(!aresetn || !step1_flag)
+    begin
+        step1_count <= 20'd0;
+    end
+    else
+    begin
+        step1_count <= step1_count + 1'b1;
+    end
+
+    if(!aresetn)
+    begin
+        btn_step1_r <= 1'b1;
+    end
+    else if(step1_sample)
+    begin
+        btn_step1_r <= btn_step[1];
+    end
+end
+//------------------------------{btn step}end----------------------------//
+
+//-------------------------------{led rg}begin---------------------------//
+//led_rg0_data[31:0]  led_rg0_data[31:0]
+//bfd0_f010           bfd0_f014
+wire write_led_rg0 = conf_we & (conf_addr[15:0]==`LED_RG0_ADDR);
+wire write_led_rg1 = conf_we & (conf_addr[15:0]==`LED_RG1_ADDR);
+assign led_rg0 = led_rg0_data[1:0];
+assign led_rg1 = led_rg1_data[1:0];
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        led_rg0_data <= 32'h0;
+    end
+    else if(write_led_rg0)
+    begin
+        led_rg0_data <= conf_wdata[31:0];
+    end
+
+    if(!aresetn)
+    begin
+        led_rg1_data <= 32'h0;
+    end
+    else if(write_led_rg1)
+    begin
+        led_rg1_data <= conf_wdata[31:0];
+    end
+end
+//--------------------------------{led rg}end----------------------------//
+
+//---------------------------{digital number}begin-----------------------//
+//digital number display
+//num_data[31:0]
+wire write_num = conf_we & (conf_addr[15:0]==`NUM_ADDR);
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        num_data <= 32'h0;
+    end
+    else if(write_num)
+    begin
+        num_data <= conf_wdata[31:0];
+    end
+end
+
+
+reg [19:0] count;
+always @(posedge aclk)
+begin
+    if(!aresetn)
+    begin
+        count <= 20'd0;
+    end
+    else
+    begin
+        count <= count + 1'b1;
+    end
+end
+//scan data
+reg [3:0] scan_data;
+always @ ( posedge aclk )
+begin
+    if ( !aresetn )
+    begin
+        scan_data <= 4'd0;
+        num_csn   <= 8'b1111_1111;
+    end
+    else
+    begin
+        case(count[19:17])
+            3'b000 : scan_data <= num_data[31:28];
+            3'b001 : scan_data <= num_data[27:24];
+            3'b010 : scan_data <= num_data[23:20];
+            3'b011 : scan_data <= num_data[19:16];
+            3'b100 : scan_data <= num_data[15:12];
+            3'b101 : scan_data <= num_data[11: 8];
+            3'b110 : scan_data <= num_data[7 : 4];
+            3'b111 : scan_data <= num_data[3 : 0];
+        endcase
+
+        case(count[19:17])
+            3'b000 : num_csn <= 8'b0111_1111;
+            3'b001 : num_csn <= 8'b1011_1111;
+            3'b010 : num_csn <= 8'b1101_1111;
+            3'b011 : num_csn <= 8'b1110_1111;
+            3'b100 : num_csn <= 8'b1111_0111;
+            3'b101 : num_csn <= 8'b1111_1011;
+            3'b110 : num_csn <= 8'b1111_1101;
+            3'b111 : num_csn <= 8'b1111_1110;
+        endcase
+    end
+end
+
+always @(posedge aclk)
+begin
+    if ( !aresetn )
+    begin
+        num_a_g <= 7'b0000000;
+    end
+    else
+    begin
+        case ( scan_data )
+            4'd0 : num_a_g <= 7'b1111110;   //0
+            4'd1 : num_a_g <= 7'b0110000;   //1
+            4'd2 : num_a_g <= 7'b1101101;   //2
+            4'd3 : num_a_g <= 7'b1111001;   //3
+            4'd4 : num_a_g <= 7'b0110011;   //4
+            4'd5 : num_a_g <= 7'b1011011;   //5
+            4'd6 : num_a_g <= 7'b1011111;   //6
+            4'd7 : num_a_g <= 7'b1110000;   //7
+            4'd8 : num_a_g <= 7'b1111111;   //8
+            4'd9 : num_a_g <= 7'b1111011;   //9
+            4'd10: num_a_g <= 7'b1110111;   //a
+            4'd11: num_a_g <= 7'b0011111;   //b
+            4'd12: num_a_g <= 7'b1001110;   //c
+            4'd13: num_a_g <= 7'b0111101;   //d
+            4'd14: num_a_g <= 7'b1001111;   //e
+            4'd15: num_a_g <= 7'b1000111;   //f
+        endcase
+    end
+end
+//----------------------------{digital number}end------------------------//
+endmodule

MaxXSoft_Fuxi/soc/peripherals/lcd/nt35510_controller/src/nt35510_apb_adapter_v1_0.v

@@ -0,0 +1,117 @@
+`define APB_INSTRUCTION_ADDR	(3'b000)
+`define APB_DATA_ADDR			(3'b100)
+
+`define APH_FSM_SETUP			(0)
+`define APH_FSM_SETUP_RS		(1)
+`define APH_FSM_ACCESS			(2)
+`define APH_FSM_READY			(3)
+`define APH_FSM_STALL			(4)
+
+`define NT35510_RD_CYCLE		(50)
+`define NT35510_WR_CYCLE		(5)
+`define NT35510_RS_CYCLE		(3)
+
+module nt35510_apb_adapter_v1_0 (
+	// Clock and reset
+	input  wire nrst,
+	input  wire clk,
+
+	// APB Bus i/f
+	input  wire [31:0] APB_paddr,
+	input  wire        APB_psel,
+	input  wire        APB_penable,
+	input  wire        APB_pwrite,
+	input  wire [31:0] APB_pwdata,
+	output wire        APB_pready,
+	output reg  [31:0] APB_prdata,
+	output wire        APB_pslverr,
+
+	// NT35510 LCD driver i/f
+	output wire        LCD_nrst,
+	output reg         LCD_csel,
+	output reg         LCD_rs,
+	output reg         LCD_wr,
+	output reg         LCD_rd,
+	input  wire [15:0] LCD_data_in,
+	output reg  [15:0] LCD_data_out,
+	output reg  [15:0] LCD_data_z
+);
+
+	reg [2:0] state;
+	reg [8:0] cyclecount;
+	reg [8:0] targetcount;
+
+    assign APB_pslverr = 1'b0;
+	assign APB_pready = (state == `APH_FSM_READY) ? 1'b1 : 1'b0;
+
+    assign LCD_nrst = nrst;
+
+	always @(posedge clk, negedge nrst) begin
+		if (~nrst) begin
+			state <= `APH_FSM_SETUP;
+			cyclecount <= 0;
+			targetcount <= 0;
+			LCD_csel <= 1'b1;
+			LCD_wr <= 1'b1;
+			LCD_rs <= 1'b0;
+			LCD_rd <= 1'b1;
+			LCD_data_z <= 16'hFFFF;
+		end else begin
+			case (state)
+				`APH_FSM_SETUP: begin
+					if (APB_penable&APB_psel) begin
+                        LCD_rs <= (APB_paddr[2:0] == `APB_INSTRUCTION_ADDR) ? 1'b0 : 1'b1;
+						state <= `APH_FSM_SETUP_RS;
+						cyclecount <= 0;
+					end
+				end
+				`APH_FSM_SETUP_RS: begin
+				    cyclecount = cyclecount + 1;
+                    if (cyclecount == `NT35510_RS_CYCLE) begin
+                        cyclecount <= 0;
+                        if (APB_pwrite) begin
+                            LCD_csel <= 1'b0;
+                            LCD_data_z <= 16'h0000;
+                            LCD_data_out <= APB_pwdata[15:0];
+                            LCD_wr <= 1'b0;
+                            targetcount <= `NT35510_WR_CYCLE;
+                        end else begin
+                            LCD_rd <= 1'b0;
+                            targetcount <= `NT35510_RD_CYCLE;
+                        end
+                        state <= `APH_FSM_ACCESS;
+                    end
+				end
+				`APH_FSM_ACCESS: begin
+					cyclecount = cyclecount + 1;
+					if (cyclecount == targetcount) begin
+						if (~APB_pwrite) begin
+							APB_prdata <= {16'b0, LCD_data_in};
+						end
+						LCD_wr <= 1'b1;
+						LCD_rd <= 1'b1;
+						state <= `APH_FSM_READY;
+					end
+				end
+				`APH_FSM_READY: begin
+				    if (~(APB_penable&APB_psel)) begin
+                        cyclecount = 0;
+						state <= `APH_FSM_STALL;
+					end
+				end
+				`APH_FSM_STALL: begin
+                    cyclecount = cyclecount + 1;
+                    if (cyclecount == targetcount) begin
+                        state <= `APH_FSM_SETUP;
+                        LCD_csel <= 1'b1;
+                        LCD_data_z <= 16'hFFFF;
+                    end
+                end
+				default: begin
+					state <= `APH_FSM_SETUP;
+				end
+			endcase
+		end
+	end
+
+endmodule

MaxXSoft_Fuxi/soc/peripherals/lcd/nt35510_controller/xgui/nt35510_apb_adapter_v1_0_v1_0.tcl

@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+

MaxXSoft_Fuxi/soc/peripherals/lcd/nt35510_controller/xgui/nt35510_controller_v1_0.tcl

@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+

MaxXSoft_Fuxi/soc/soc.srcs/sim_1/new/SoC_tb.v

@@ -0,0 +1,101 @@
+`timescale 1ns / 1ps
+
+module SoC_tb();
+
+  reg   clk, rst_n;
+  wire  cfg_si, cfg_so, cfg_ss;
+
+  SoC soc_inst(
+    .clk            (clk),
+    .rst_n          (rst_n),
+
+    .UART_rxd       (1'b0),
+    .UART_txd       (),
+
+    .SPI_FLASH_mosi (),
+    .SPI_FLASH_miso (),
+    .SPI_FLASH_ss   (),
+    .SPI_FLASH_sck  (),
+    .SPI_FLASH_io2  (),
+    .SPI_FLASH_io3  (),
+
+    .CFG_FLASH_mosi (cfg_si),
+    .CFG_FLASH_miso (cfg_so),
+    .CFG_FLASH_ss   (cfg_ss),
+
+    .VGA_r          (),
+    .VGA_g          (),
+    .VGA_b          (),
+    .VGA_hsync      (),
+    .VGA_vsync      (),
+
+    .led            (),
+    .led_rg0        (),
+    .led_rg1        (),
+    .num_csn        (),
+    .num_a_g        (),
+    .num_a_g_dp     (),
+    .btn_key_col    (),
+    .btn_key_row    (4'b0),
+    .btn_step       (2'b0),
+    .switch         (8'b0),
+
+    .DDR3_dq        (),
+    .DDR3_addr      (),
+    .DDR3_ba        (),
+    .DDR3_ras_n     (),
+    .DDR3_cas_n     (),
+    .DDR3_we_n      (),
+    .DDR3_odt       (),
+    .DDR3_reset_n   (),
+    .DDR3_cke       (),
+    .DDR3_dm        (),
+    .DDR3_dqs_p     (),
+    .DDR3_dqs_n     (),
+    .DDR3_ck_p      (),
+    .DDR3_ck_n      (),
+
+    .MDIO_mdc       (),
+    .MDIO_mdio      (),
+    .MII_col        (1'b0),
+    .MII_crs        (1'b0),
+    .MII_rst_n      (),
+    .MII_rx_clk     (1'b0),
+    .MII_rx_dv      (1'b0),
+    .MII_rx_er      (1'b0),
+    .MII_rxd        (4'b0),
+    .MII_tx_clk     (1'b0),
+    .MII_tx_en      (),
+    .MII_tx_er      (),
+    .MII_txd        (),
+
+    .LCD_data       (),
+    .LCD_nrst       (),
+    .LCD_csel       (),
+    .LCD_rd         (),
+    .LCD_rs         (),
+    .LCD_wr         (),
+    .LCD_lighton    ()
+  );
+
+  s25fl128s cfg_flash(
+    .SI             (cfg_si),
+    .SO             (cfg_so),
+    .SCK            (clk),
+    .CSNeg          (cfg_ss),
+    .RSTNeg         (1'b1),
+    .HOLDNeg        (),
+    .WPNeg          ()
+  );
+
+  always begin
+    #5 clk <= ~clk;
+  end
+
+  initial begin
+    clk <= 0;
+    rst_n <= 0;
+    #7 rst_n <= 1;
+  end
+
+endmodule

MaxXSoft_Fuxi/soc/soc.srcs/sources_1/bd/mref/Clint/xgui/Clint_v1_0.tcl

@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+

MaxXSoft_Fuxi/soc/soc.srcs/sources_1/bd/mref/FuxiWrapper/xgui/FuxiWrapper_v1_0.tcl

@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+

MaxXSoft_Fuxi/soc/soc.srcs/sources_1/bd/mref/ResetSynchronizer/xgui/ResetSynchronizer_v1_0.tcl

@@ -0,0 +1,40 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "RESET_POSEDGE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "RESET_STAGE" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.RESET_POSEDGE { PARAM_VALUE.RESET_POSEDGE } {
+	# Procedure called to update RESET_POSEDGE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.RESET_POSEDGE { PARAM_VALUE.RESET_POSEDGE } {
+	# Procedure called to validate RESET_POSEDGE
+	return true
+}
+
+proc update_PARAM_VALUE.RESET_STAGE { PARAM_VALUE.RESET_STAGE } {
+	# Procedure called to update RESET_STAGE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.RESET_STAGE { PARAM_VALUE.RESET_STAGE } {
+	# Procedure called to validate RESET_STAGE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.RESET_STAGE { MODELPARAM_VALUE.RESET_STAGE PARAM_VALUE.RESET_STAGE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.RESET_STAGE}] ${MODELPARAM_VALUE.RESET_STAGE}
+}
+
+proc update_MODELPARAM_VALUE.RESET_POSEDGE { MODELPARAM_VALUE.RESET_POSEDGE PARAM_VALUE.RESET_POSEDGE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.RESET_POSEDGE}] ${MODELPARAM_VALUE.RESET_POSEDGE}
+}
+

MaxXSoft_Fuxi/soc/soc.srcs/sources_1/bd/mref/confreg/xgui/confreg_v1_0.tcl

@@ -0,0 +1,40 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "BUS_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "SIMULATION" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.BUS_WIDTH { PARAM_VALUE.BUS_WIDTH } {
+	# Procedure called to update BUS_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.BUS_WIDTH { PARAM_VALUE.BUS_WIDTH } {
+	# Procedure called to validate BUS_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.SIMULATION { PARAM_VALUE.SIMULATION } {
+	# Procedure called to update SIMULATION when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SIMULATION { PARAM_VALUE.SIMULATION } {
+	# Procedure called to validate SIMULATION
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.SIMULATION { MODELPARAM_VALUE.SIMULATION PARAM_VALUE.SIMULATION } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SIMULATION}] ${MODELPARAM_VALUE.SIMULATION}
+}
+
+proc update_MODELPARAM_VALUE.BUS_WIDTH { MODELPARAM_VALUE.BUS_WIDTH PARAM_VALUE.BUS_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.BUS_WIDTH}] ${MODELPARAM_VALUE.BUS_WIDTH}
+}
+

MaxXSoft_Fuxi/soc/soc.srcs/sources_1/new/SoC.v

@@ -0,0 +1,220 @@
+// from https://github.com/trivialmips/nontrivial-mips
+// modified by: MaxXing, 2020-05
+
+`timescale 1ns / 1ps
+
+`include "iobuf.v"
+
+module SoC(
+  input           clk,
+  input           rst_n,
+  // UART
+  input           UART_rxd,
+  output          UART_txd,
+  // plugable SPI flash
+  inout           SPI_FLASH_mosi,
+  inout           SPI_FLASH_miso,
+  inout           SPI_FLASH_ss,
+  inout           SPI_FLASH_sck,
+  inout           SPI_FLASH_io2,
+  inout           SPI_FLASH_io3,
+  // non-plugable CFG SPI flash
+  inout           CFG_FLASH_mosi,
+  inout           CFG_FLASH_miso,
+  inout           CFG_FLASH_ss,
+  // VGA (use inout for high-Z output)
+  inout   [3:0]   VGA_r,
+  inout   [3:0]   VGA_g,
+  inout   [3:0]   VGA_b,
+  output          VGA_hsync,
+  output          VGA_vsync,
+  // GPIO
+  output  [15:0]  led,
+  output  [1:0]   led_rg0,
+  output  [1:0]   led_rg1,
+  output  [7:0]   num_csn,
+  output  [6:0]   num_a_g,
+  output          num_a_g_dp,
+  output  [3:0]   btn_key_col,
+  input   [3:0]   btn_key_row,
+  input   [1:0]   btn_step,
+  input   [7:0]   switch,
+  // DDR3
+  inout   [15:0]  DDR3_dq,
+  output  [12:0]  DDR3_addr,
+  output  [2:0]   DDR3_ba,
+  output          DDR3_ras_n,
+  output          DDR3_cas_n,
+  output          DDR3_we_n,
+  output          DDR3_odt,
+  output          DDR3_reset_n,
+  output          DDR3_cke,
+  output  [1:0]   DDR3_dm,
+  inout   [1:0]   DDR3_dqs_p,
+  inout   [1:0]   DDR3_dqs_n,
+  output          DDR3_ck_p,
+  output          DDR3_ck_n,
+  // ethernet
+  output          MDIO_mdc,
+  inout           MDIO_mdio,
+  input           MII_col,
+  input           MII_crs,
+  output          MII_rst_n,
+  input           MII_rx_clk,
+  input           MII_rx_dv,
+  input           MII_rx_er,
+  input   [3:0]   MII_rxd,
+  input           MII_tx_clk,
+  output          MII_tx_en,
+  output          MII_tx_er,
+  output  [3:0]   MII_txd,
+  // LCD
+  inout   [15:0]  LCD_data,
+  output          LCD_nrst,
+  output          LCD_csel,
+  output          LCD_rd,
+  output          LCD_rs,
+  output          LCD_wr,
+  output          LCD_lighton
+);
+
+  // plugable SPI flash
+  `IOBUF_GEN(SPI_FLASH_mosi, SPI_FLASH_io0)
+  `IOBUF_GEN(SPI_FLASH_miso, SPI_FLASH_io1)
+  `IOBUF_GEN_SIMPLE(SPI_FLASH_io2)
+  `IOBUF_GEN_SIMPLE(SPI_FLASH_io3)
+  `IOBUF_GEN_SIMPLE(SPI_FLASH_ss)
+  `IOBUF_GEN_SIMPLE(SPI_FLASH_sck)
+
+  // non-plugable CFG SPI flash
+  `IOBUF_GEN(CFG_FLASH_mosi, CFG_FLASH_io0)
+  `IOBUF_GEN(CFG_FLASH_miso, CFG_FLASH_io1)
+  `IOBUF_GEN_SIMPLE(CFG_FLASH_ss)
+
+  // Ethernet
+  `IOBUF_GEN_SIMPLE(MDIO_mdio)
+  // not provided in Ethernet Lite
+  assign MII_tx_er = 1'b0;
+
+  // GPIO
+  // not provided in confreg IP
+  assign num_a_g_dp = 1'b0;
+
+  // LCD
+  `IOBUF_GEN_VEC(16, LCD_data, LCD_data_tri)
+
+  // VGA
+  wire [5:0] VGA_red, VGA_green, VGA_blue;
+  genvar VGA_i;
+  generate
+    for (VGA_i = 0; VGA_i < 4; VGA_i = VGA_i+1) begin : VGA_gen
+      // match on-board DAC built by resistor
+      assign VGA_r[VGA_i] = VGA_red[VGA_i+2] ? 1'b1 : 1'bZ;
+      assign VGA_g[VGA_i] = VGA_green[VGA_i+2] ? 1'b1 : 1'bZ;
+      assign VGA_b[VGA_i] = VGA_blue[VGA_i+2] ? 1'b1 : 1'bZ;
+    end
+  endgenerate
+
+  // initialize block design
+  soc soc_inst(
+    .clk              (clk),
+    .rst_n            (rst_n),
+    // UART
+    .UART_txd         (UART_txd),
+    .UART_rxd         (UART_rxd),
+    .UART_ctsn        (1'b0),
+    .UART_dcdn        (1'b0),
+    .UART_dsrn        (1'b0),
+    .UART_ri          (1'b1),
+    // plugable SPI flash
+    .SPI_FLASH_io0_i  (SPI_FLASH_io0_i),
+    .SPI_FLASH_io0_o  (SPI_FLASH_io0_o),
+    .SPI_FLASH_io0_t  (SPI_FLASH_io0_t),
+    .SPI_FLASH_io1_i  (SPI_FLASH_io1_i),
+    .SPI_FLASH_io1_o  (SPI_FLASH_io1_o),
+    .SPI_FLASH_io1_t  (SPI_FLASH_io1_t),
+    .SPI_FLASH_io2_i  (SPI_FLASH_io2_i),
+    .SPI_FLASH_io2_o  (SPI_FLASH_io2_o),
+    .SPI_FLASH_io2_t  (SPI_FLASH_io2_t),
+    .SPI_FLASH_io3_i  (SPI_FLASH_io3_i),
+    .SPI_FLASH_io3_o  (SPI_FLASH_io3_o),
+    .SPI_FLASH_io3_t  (SPI_FLASH_io3_t),
+    .SPI_FLASH_sck_i  (SPI_FLASH_sck_i),
+    .SPI_FLASH_sck_o  (SPI_FLASH_sck_o),
+    .SPI_FLASH_sck_t  (SPI_FLASH_sck_t),
+    .SPI_FLASH_ss_i   (SPI_FLASH_ss_i),
+    .SPI_FLASH_ss_o   (SPI_FLASH_ss_o),
+    .SPI_FLASH_ss_t   (SPI_FLASH_ss_t),
+    // non-plugable CFG SPI flash
+    .CFG_FLASH_io0_i  (CFG_FLASH_io0_i),
+    .CFG_FLASH_io0_o  (CFG_FLASH_io0_o),
+    .CFG_FLASH_io0_t  (CFG_FLASH_io0_t),
+    .CFG_FLASH_io1_i  (CFG_FLASH_io1_i),
+    .CFG_FLASH_io1_o  (CFG_FLASH_io1_o),
+    .CFG_FLASH_io1_t  (CFG_FLASH_io1_t),
+    .CFG_FLASH_ss_i   (CFG_FLASH_ss_i),
+    .CFG_FLASH_ss_o   (CFG_FLASH_ss_o),
+    .CFG_FLASH_ss_t   (CFG_FLASH_ss_t),
+    // VGA
+    .VGA_hsync        (VGA_hsync),
+    .VGA_vsync        (VGA_vsync),
+    .VGA_red          (VGA_red),
+    .VGA_green        (VGA_green),
+    .VGA_blue         (VGA_blue),
+    .VGA_clk          (),
+    .VGA_de           (),
+    .VGA_dps          (),
+    // GPIO
+    .led              (led),
+    .led_rg0          (led_rg0),
+    .led_rg1          (led_rg1),
+    .num_csn          (num_csn),
+    .num_a_g          (num_a_g),
+    .btn_key_col      (btn_key_col),
+    .btn_key_row      (btn_key_row),
+    .btn_step         (btn_step),
+    .switch           (switch),
+    // DDR3
+    .DDR3_dq          (DDR3_dq),
+    .DDR3_addr        (DDR3_addr),
+    .DDR3_ba          (DDR3_ba),
+    .DDR3_ras_n       (DDR3_ras_n),
+    .DDR3_cas_n       (DDR3_cas_n),
+    .DDR3_we_n        (DDR3_we_n),
+    .DDR3_odt         (DDR3_odt),
+    .DDR3_reset_n     (DDR3_reset_n),
+    .DDR3_cke         (DDR3_cke),
+    .DDR3_dm          (DDR3_dm),
+    .DDR3_dqs_p       (DDR3_dqs_p),
+    .DDR3_dqs_n       (DDR3_dqs_n),
+    .DDR3_ck_p        (DDR3_ck_p),
+    .DDR3_ck_n        (DDR3_ck_n),
+    // ethernet
+    // .MII_tx_er is not connected
+    .MDIO_mdc         (MDIO_mdc),
+    .MDIO_mdio_i      (MDIO_mdio_i),
+    .MDIO_mdio_o      (MDIO_mdio_o),
+    .MDIO_mdio_t      (MDIO_mdio_t),
+    .MII_col          (MII_col),
+    .MII_crs          (MII_crs),
+    .MII_rst_n        (MII_rst_n),
+    .MII_rx_clk       (MII_rx_clk),
+    .MII_rx_dv        (MII_rx_dv),
+    .MII_rx_er        (MII_rx_er),
+    .MII_rxd          (MII_rxd),
+    .MII_tx_clk       (MII_tx_clk),
+    .MII_tx_en        (MII_tx_en),
+    .MII_txd          (MII_txd),
+    // LCD
+    .LCD_data_tri_i   (LCD_data_tri_i),
+    .LCD_data_tri_o   (LCD_data_tri_o),
+    .LCD_data_tri_t   (LCD_data_tri_t),
+    .LCD_nrst         (LCD_nrst),
+    .LCD_csel         (LCD_csel),
+    .LCD_rd           (LCD_rd),
+    .LCD_rs           (LCD_rs),
+    .LCD_wr           (LCD_wr),
+    .LCD_lighton      (LCD_lighton)
+  );
+
+endmodule

MaxXSoft_Fuxi/soc/soc.srcs/sources_1/new/iobuf.v

@@ -0,0 +1,35 @@
+// from https://github.com/trivialmips/nontrivial-mips
+// modified by: MaxXing, 2020-05
+
+`ifndef FUXISOC_IOBUF_V_
+`define FUXISOC_IOBUF_V_
+
+`define IOBUF_GEN(IN, OUT)          \
+    wire OUT``_i, OUT``_o, OUT``_t; \
+    IOBUF IN``_buf (                \
+      .IO(IN),                      \
+      .I(OUT``_o),                  \
+      .O(OUT``_i),                  \
+      .T(OUT``_t)                   \
+    );
+
+`define IOBUF_GEN_SIMPLE(IN) `IOBUF_GEN(IN, IN)
+
+`define IOBUF_GEN_VEC(BITS, IN, OUT)                            \
+    wire [BITS - 1:0] OUT``_i, OUT``_o, OUT``_t;                \
+    genvar IN``_gen_var;                                        \
+    generate                                                    \
+      for (IN``_gen_var = 0; IN``_gen_var < BITS;               \
+           IN``_gen_var = IN``_gen_var + 1) begin: IN``_buf_gen \
+        IOBUF IN``_buf (                                        \
+          .IO(IN[IN``_gen_var]),                                \
+          .O(OUT``_i[IN``_gen_var]),                            \
+          .I(OUT``_o[IN``_gen_var]),                            \
+          .T(OUT``_t[IN``_gen_var])                             \
+        );                                                      \
+      end                                                       \
+    endgenerate
+
+`define IOBUF_GEN_VEC_SIMPLE(BITS, IN) `IOBUF_GEN_VEC(BITS, IN, IN)
+
+`endif  // FUXISOC_IOBUF_V_

MaxXSoft_Fuxi/src/test/resources/fib.txt

@@ -0,0 +1,15 @@
+00a00413
+00100513
+00100593
+00000613
+00000693
+0086de63
+00b502b3
+00058613
+00050593
+00028513
+00168693
+fe9ff06f
+deadc537
+0de50513
+ff9ff06f

MaxXSoft_Fuxi/src/test/resources/fib_trace.txt

@@ -0,0 +1,57 @@
+00000200 08 0000000a
+00000204 10 00000001
+00000208 11 00000001
+0000020c 12 00000000
+00000210 13 00000000
+00000218 05 00000002
+0000021c 12 00000001
+00000220 11 00000001
+00000224 10 00000002
+00000228 13 00000001
+00000218 05 00000003
+0000021c 12 00000001
+00000220 11 00000002
+00000224 10 00000003
+00000228 13 00000002
+00000218 05 00000005
+0000021c 12 00000002
+00000220 11 00000003
+00000224 10 00000005
+00000228 13 00000003
+00000218 05 00000008
+0000021c 12 00000003
+00000220 11 00000005
+00000224 10 00000008
+00000228 13 00000004
+00000218 05 0000000d
+0000021c 12 00000005
+00000220 11 00000008
+00000224 10 0000000d
+00000228 13 00000005
+00000218 05 00000015
+0000021c 12 00000008
+00000220 11 0000000d
+00000224 10 00000015
+00000228 13 00000006
+00000218 05 00000022
+0000021c 12 0000000d
+00000220 11 00000015
+00000224 10 00000022
+00000228 13 00000007
+00000218 05 00000037
+0000021c 12 00000015
+00000220 11 00000022
+00000224 10 00000037
+00000228 13 00000008
+00000218 05 00000059
+0000021c 12 00000022
+00000220 11 00000037
+00000224 10 00000059
+00000228 13 00000009
+00000218 05 00000090
+0000021c 12 00000037
+00000220 11 00000059
+00000224 10 00000090
+00000228 13 0000000a
+00000230 10 deadc000
+00000234 10 deadc0de

MaxXSoft_Fuxi/src/test/resources/mdu.txt

@@ -0,0 +1,13 @@
+000032b7
+03928293
+00002337
+a8530313
+026283b3
+027303b3
+027303b3
+0262c3b3
+0262e3b3
+0040006f
+deadc537
+0de50513
+ff9ff06f

MaxXSoft_Fuxi/src/test/resources/mdu_trace.txt

@@ -0,0 +1,11 @@
+00000200 05 00003000
+00000204 05 00003039
+00000208 06 00002000
+0000020c 06 00001a85
+00000210 07 04fed79d
+00000214 07 7a4bf691
+00000218 07 4081d355
+0000021c 07 00000001
+00000220 07 000015b4
+00000228 10 deadc000
+0000022c 10 deadc0de

MaxXSoft_Fuxi/src/test/resources/mecall.txt

@@ -0,0 +1,13 @@
+00000297
+02428293
+30529073
+00000073
+abcdf537
+f0050513
+deadc537
+0de50513
+ff9ff06f
+341022f3
+00428293
+34129073
+30200073

MaxXSoft_Fuxi/src/test/resources/mecall_trace.txt

@@ -0,0 +1,8 @@
+00000200 05 00000200
+00000204 05 00000224
+00000224 05 0000020c
+00000228 05 00000210
+00000210 10 abcdf000
+00000214 10 abcdef00
+00000218 10 deadc000
+0000021c 10 deadc0de

MaxXSoft_Fuxi/src/test/resources/secall.txt

@@ -0,0 +1,24 @@
+00000297
+03428293
+34129073
+000102b7
+fff28293
+30229073
+000012b7
+80028293
+3002a073
+30200073
+deadc537
+0de50513
+ff9ff06f
+00000297
+01c28293
+10529073
+00000073
+abcdf537
+f0050513
+fddff06f
+141022f3
+00428293
+14129073
+10200073

MaxXSoft_Fuxi/src/test/resources/secall_trace.txt

@@ -0,0 +1,14 @@
+00000200 05 00000200
+00000204 05 00000234
+0000020c 05 00010000
+00000210 05 0000ffff
+00000218 05 00001000
+0000021c 05 00000800
+00000234 05 00000234
+00000238 05 00000250
+00000250 05 00000240
+00000254 05 00000244
+00000244 10 abcdf000
+00000248 10 abcdef00
+00000228 10 deadc000
+0000022c 10 deadc0de

MaxXSoft_Fuxi/verilog/FuxiWrapper.v

@@ -0,0 +1,252 @@
+// a Verilog wrapper module of Fuxi
+module FuxiWrapper(
+  input         clk,
+  input         rst,
+  // interrupt requests
+  input         irq_timer,
+  input         irq_soft,
+  input         irq_extern,
+  // debug signals
+  output        debug_wen,
+  output [4:0]  debug_waddr,
+  output [31:0] debug_wdata,
+  output [31:0] debug_pc,
+  // instruction AXI4 interface
+  input         inst_arready,
+  output        inst_arvalid,
+  output [31:0] inst_araddr,
+  output [3:0]  inst_arid,
+  output [2:0]  inst_arsize,
+  output [7:0]  inst_arlen,
+  output [1:0]  inst_arburst,
+  output        inst_arlock,
+  output [3:0]  inst_arcache,
+  output [2:0]  inst_arprot,
+  output        inst_rready,
+  input         inst_rvalid,
+  input  [31:0] inst_rdata,
+  input  [3:0]  inst_rid,
+  input         inst_rlast,
+  input  [1:0]  inst_rresp,
+  input         inst_awready,
+  output        inst_awvalid,
+  output [31:0] inst_awaddr,
+  output [3:0]  inst_awid,
+  output [2:0]  inst_awsize,
+  output [7:0]  inst_awlen,
+  output [1:0]  inst_awburst,
+  output        inst_awlock,
+  output [3:0]  inst_awcache,
+  output [2:0]  inst_awprot,
+  input         inst_wready,
+  output        inst_wvalid,
+  output [31:0] inst_wdata,
+  output [3:0]  inst_wid,
+  output        inst_wlast,
+  output [3:0]  inst_wstrb,
+  output        inst_bready,
+  input         inst_bvalid,
+  input  [3:0]  inst_bid,
+  input  [1:0]  inst_bresp,
+  // data AXI4 interface
+  input         data_arready,
+  output        data_arvalid,
+  output [31:0] data_araddr,
+  output [3:0]  data_arid,
+  output [2:0]  data_arsize,
+  output [7:0]  data_arlen,
+  output [1:0]  data_arburst,
+  output        data_arlock,
+  output [3:0]  data_arcache,
+  output [2:0]  data_arprot,
+  output        data_rready,
+  input         data_rvalid,
+  input  [31:0] data_rdata,
+  input  [3:0]  data_rid,
+  input         data_rlast,
+  input  [1:0]  data_rresp,
+  input         data_awready,
+  output        data_awvalid,
+  output [31:0] data_awaddr,
+  output [3:0]  data_awid,
+  output [2:0]  data_awsize,
+  output [7:0]  data_awlen,
+  output [1:0]  data_awburst,
+  output        data_awlock,
+  output [3:0]  data_awcache,
+  output [2:0]  data_awprot,
+  input         data_wready,
+  output        data_wvalid,
+  output [31:0] data_wdata,
+  output [3:0]  data_wid,
+  output        data_wlast,
+  output [3:0]  data_wstrb,
+  output        data_bready,
+  input         data_bvalid,
+  input  [3:0]  data_bid,
+  input  [1:0]  data_bresp,
+  // uncached AXI4 interface
+  input         uncached_arready,
+  output        uncached_arvalid,
+  output [31:0] uncached_araddr,
+  output [3:0]  uncached_arid,
+  output [2:0]  uncached_arsize,
+  output [7:0]  uncached_arlen,
+  output [1:0]  uncached_arburst,
+  output        uncached_arlock,
+  output [3:0]  uncached_arcache,
+  output [2:0]  uncached_arprot,
+  output        uncached_rready,
+  input         uncached_rvalid,
+  input  [31:0] uncached_rdata,
+  input  [3:0]  uncached_rid,
+  input         uncached_rlast,
+  input  [1:0]  uncached_rresp,
+  input         uncached_awready,
+  output        uncached_awvalid,
+  output [31:0] uncached_awaddr,
+  output [3:0]  uncached_awid,
+  output [2:0]  uncached_awsize,
+  output [7:0]  uncached_awlen,
+  output [1:0]  uncached_awburst,
+  output        uncached_awlock,
+  output [3:0]  uncached_awcache,
+  output [2:0]  uncached_awprot,
+  input         uncached_wready,
+  output        uncached_wvalid,
+  output [31:0] uncached_wdata,
+  output [3:0]  uncached_wid,
+  output        uncached_wlast,
+  output [3:0]  uncached_wstrb,
+  output        uncached_bready,
+  input         uncached_bvalid,
+  input  [3:0]  uncached_bid,
+  input  [1:0]  uncached_bresp
+);
+
+  Fuxi fuxi(
+    .clock                            (clk),
+    .reset                            (rst),
+    // interrupt requests
+    .io_irq_timer                     (irq_timer),
+    .io_irq_soft                      (irq_soft),
+    .io_irq_extern                    (irq_extern),
+    // debug signals
+    .io_debug_regWen                  (debug_wen),
+    .io_debug_regWaddr                (debug_waddr),
+    .io_debug_regWdata                (debug_wdata),
+    .io_debug_pc                      (debug_pc),
+    // instruction AXI4 interface
+    .io_inst_readAddr_ready           (inst_arready),
+    .io_inst_readAddr_valid           (inst_arvalid),
+    .io_inst_readAddr_bits_addr       (inst_araddr),
+    .io_inst_readAddr_bits_id         (inst_arid),
+    .io_inst_readAddr_bits_size       (inst_arsize),
+    .io_inst_readAddr_bits_len        (inst_arlen),
+    .io_inst_readAddr_bits_burst      (inst_arburst),
+    .io_inst_readAddr_bits_lock       (inst_arlock),
+    .io_inst_readAddr_bits_cache      (inst_arcache),
+    .io_inst_readAddr_bits_prot       (inst_arprot),
+    .io_inst_readData_ready           (inst_rready),
+    .io_inst_readData_valid           (inst_rvalid),
+    .io_inst_readData_bits_data       (inst_rdata),
+    .io_inst_readData_bits_id         (inst_rid),
+    .io_inst_readData_bits_last       (inst_rlast),
+    .io_inst_readData_bits_resp       (inst_rresp),
+    .io_inst_writeAddr_ready          (inst_awready),
+    .io_inst_writeAddr_valid          (inst_awvalid),
+    .io_inst_writeAddr_bits_addr      (inst_awaddr),
+    .io_inst_writeAddr_bits_id        (inst_awid),
+    .io_inst_writeAddr_bits_size      (inst_awsize),
+    .io_inst_writeAddr_bits_len       (inst_awlen),
+    .io_inst_writeAddr_bits_burst     (inst_awburst),
+    .io_inst_writeAddr_bits_lock      (inst_awlock),
+    .io_inst_writeAddr_bits_cache     (inst_awcache),
+    .io_inst_writeAddr_bits_prot      (inst_awprot),
+    .io_inst_writeData_ready          (inst_wready),
+    .io_inst_writeData_valid          (inst_wvalid),
+    .io_inst_writeData_bits_data      (inst_wdata),
+    .io_inst_writeData_bits_id        (inst_wid),
+    .io_inst_writeData_bits_last      (inst_wlast),
+    .io_inst_writeData_bits_strb      (inst_wstrb),
+    .io_inst_writeResp_ready          (inst_bready),
+    .io_inst_writeResp_valid          (inst_bvalid),
+    .io_inst_writeResp_bits_id        (inst_bid),
+    .io_inst_writeResp_bits_resp      (inst_bresp),
+    // data AXI4 interface
+    .io_data_readAddr_ready           (data_arready),
+    .io_data_readAddr_valid           (data_arvalid),
+    .io_data_readAddr_bits_addr       (data_araddr),
+    .io_data_readAddr_bits_id         (data_arid),
+    .io_data_readAddr_bits_size       (data_arsize),
+    .io_data_readAddr_bits_len        (data_arlen),
+    .io_data_readAddr_bits_burst      (data_arburst),
+    .io_data_readAddr_bits_lock       (data_arlock),
+    .io_data_readAddr_bits_cache      (data_arcache),
+    .io_data_readAddr_bits_prot       (data_arprot),
+    .io_data_readData_ready           (data_rready),
+    .io_data_readData_valid           (data_rvalid),
+    .io_data_readData_bits_data       (data_rdata),
+    .io_data_readData_bits_id         (data_rid),
+    .io_data_readData_bits_last       (data_rlast),
+    .io_data_readData_bits_resp       (data_rresp),
+    .io_data_writeAddr_ready          (data_awready),
+    .io_data_writeAddr_valid          (data_awvalid),
+    .io_data_writeAddr_bits_addr      (data_awaddr),
+    .io_data_writeAddr_bits_id        (data_awid),
+    .io_data_writeAddr_bits_size      (data_awsize),
+    .io_data_writeAddr_bits_len       (data_awlen),
+    .io_data_writeAddr_bits_burst     (data_awburst),
+    .io_data_writeAddr_bits_lock      (data_awlock),
+    .io_data_writeAddr_bits_cache     (data_awcache),
+    .io_data_writeAddr_bits_prot      (data_awprot),
+    .io_data_writeData_ready          (data_wready),
+    .io_data_writeData_valid          (data_wvalid),
+    .io_data_writeData_bits_data      (data_wdata),
+    .io_data_writeData_bits_id        (data_wid),
+    .io_data_writeData_bits_last      (data_wlast),
+    .io_data_writeData_bits_strb      (data_wstrb),
+    .io_data_writeResp_ready          (data_bready),
+    .io_data_writeResp_valid          (data_bvalid),
+    .io_data_writeResp_bits_id        (data_bid),
+    .io_data_writeResp_bits_resp      (data_bresp),
+    // uncached AXI4 interface
+    .io_uncached_readAddr_ready       (uncached_arready),
+    .io_uncached_readAddr_valid       (uncached_arvalid),
+    .io_uncached_readAddr_bits_addr   (uncached_araddr),
+    .io_uncached_readAddr_bits_id     (uncached_arid),
+    .io_uncached_readAddr_bits_size   (uncached_arsize),
+    .io_uncached_readAddr_bits_len    (uncached_arlen),
+    .io_uncached_readAddr_bits_burst  (uncached_arburst),
+    .io_uncached_readAddr_bits_lock   (uncached_arlock),
+    .io_uncached_readAddr_bits_cache  (uncached_arcache),
+    .io_uncached_readAddr_bits_prot   (uncached_arprot),
+    .io_uncached_readData_ready       (uncached_rready),
+    .io_uncached_readData_valid       (uncached_rvalid),
+    .io_uncached_readData_bits_data   (uncached_rdata),
+    .io_uncached_readData_bits_id     (uncached_rid),
+    .io_uncached_readData_bits_last   (uncached_rlast),
+    .io_uncached_readData_bits_resp   (uncached_rresp),
+    .io_uncached_writeAddr_ready      (uncached_awready),
+    .io_uncached_writeAddr_valid      (uncached_awvalid),
+    .io_uncached_writeAddr_bits_addr  (uncached_awaddr),
+    .io_uncached_writeAddr_bits_id    (uncached_awid),
+    .io_uncached_writeAddr_bits_size  (uncached_awsize),
+    .io_uncached_writeAddr_bits_len   (uncached_awlen),
+    .io_uncached_writeAddr_bits_burst (uncached_awburst),
+    .io_uncached_writeAddr_bits_lock  (uncached_awlock),
+    .io_uncached_writeAddr_bits_cache (uncached_awcache),
+    .io_uncached_writeAddr_bits_prot  (uncached_awprot),
+    .io_uncached_writeData_ready      (uncached_wready),
+    .io_uncached_writeData_valid      (uncached_wvalid),
+    .io_uncached_writeData_bits_data  (uncached_wdata),
+    .io_uncached_writeData_bits_id    (uncached_wid),
+    .io_uncached_writeData_bits_last  (uncached_wlast),
+    .io_uncached_writeData_bits_strb  (uncached_wstrb),
+    .io_uncached_writeResp_ready      (uncached_bready),
+    .io_uncached_writeResp_valid      (uncached_bvalid),
+    .io_uncached_writeResp_bits_id    (uncached_bid),
+    .io_uncached_writeResp_bits_resp  (uncached_bresp)
+  );
+
+endmodule