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verilog_data-1 / Evensgn_RISC-V-CPU /test /test.S

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Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)

df0a64a verified 8 days ago

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	.org 0x0
	.global _start
	_start:
	ori x1, x0, 0x210 # x1 = h210
	add x3, x1, x2