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verilog_data-1 / Evensgn_RISC-V-CPU /test /memory.ld

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Add batch 9 (Evensgn_RISC-V-CPU, nandland_nandland, stffrdhrn_sdram-controller, viduraakalanka_HDL-Bits-Solutions, suisuisi_FPGAandCNN)

df0a64a verified 7 days ago

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290 Bytes

	SECTIONS
	{
	. = 0x00000000;
	.rom :
	{
	*(.rom)
	}

	. = 0x00001000;
	.text :
	{
	*(.text)
	}

	.rodata ALIGN(4) :
	{
	*(.rodata)
	}

	.data ALIGN(4) :
	{
	*(.data)
	}

	__bss_start = .;

	.bss ALIGN(4) :
	{
	*(.bss)
	}

	__bss_end = .;
	__heap_start = (__bss_end + 0xfff) & 0xff000;
	}