# [feature/debug_module] Integrate RISC-V debug module

- Source URL: https://github.com/HiSA-Team/Simply-V/issues/22

## Issue Title
[feature/debug_module] Integrate RISC-V debug module

## Issue Description
Add RISC-V debug module (https://github.com/pulp-platform/riscv-dbg/tree/v0.8.1) and expose it on Xilinx scanchain to make it visible to hw_server.

Tentatively try to integrate it with jtag-ext-bscan.vhdl (https://github.com/eugene-tarassov/vivado-risc-v/blob/master/vhdl-wrapper/src/net/largest/riscv/vhdl/jtag-ext-bscan.vhdl).

Most likely there are going to be compatibility issues with JTAG, BSCAN and hw_server.

Alternatively, just fall-back to PULP BSCAN tap (https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_bscane_tap.sv) and OpenOCD. In this case, the issue would be the OpenOCD config file for Nexys and Alveo.

## Issue Comments
No comments are present on this issue.

## Issue Metadata
- Status: Closed
- Assignee: MaistoV
- Milestone: MCU release

## Linked Issues / PRs
- PR #48 — associated pull request (closed)