# [feature/rv64/rtl] RV64: RTL & IPs adjustments

- Source URL: https://github.com/HiSA-Team/Simply-V/issues/86

**UninaSoC RTL**

- [x]  header files (`svh`) for protocols can work with adjusting the DATA_WIDTH, STRB and ID. To do so, let's remove parameters (as they are not used) and move to parametric macros and declarations (including ports)
- [x] Update files in `rtl` to support new `svh` macros
- [x] Update `.svinc` file generation
- [x] uninasoc.sv should be independent from XLEN, however all hardcoded references to 32 bits must be removed (if any).
- [x] Clock_converters and Dwidth_converters: DDR4
- [x] Clock_converters and Dwidth_converters: PBUS
- [x] Clock_converters and Dwidth_converters: Sys Master
- [x] Clock_converters and Dwidth_converters: PLIC
- [x] Regarding the socket, the idea is to assume a user will always use a 64-bits CPU if XLEN=64; therefore a simple assert will do the job, stopping the build if the core selector is incompatible with the XLEN. **Note** in #83 core and xlen compatibility will be checked as well

**UninaSoC IPS**

- [x] Update files in `rtl` to support new `svh` macros
- [x] The IP config files should take into account the change of data width and address width. (e.g. block mem generator).
- [x] Custom IPS will be independent from the config flow. For now, all peripherals on the pbus will be at 32, and only the PLIC might change between 32 and 64.
- [x] Add PLIC new Target (for socket S-mode) -> Moved to #107