# change the directory structure in the verification

- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/442

The directory structure in the verification is a little strange and i think it can be improved.

The idea is that we will have the same main directory as the RTL.
Meaning the content of the "verif/cache" should be moved into mem_ss
and the content of "verif/router" should be moved into fabric.

Then the list.f file should be merged into a single file - but keep many different "_tb" files that can be used using the "-top" option in the compilation command.

This change will need carful merging in the list.f files, in the include and functions, and the workflow sanity command ext

PR Title: Move the verif files around to have less DUT and use the -top flag to…
PR Number: #452
Status: Merged
Author: amichai-bd
Reviewer/Merger: roman012285
Date Merged: January 19, 2024

Description:
The PR reorganizes verification files to reduce Device Under Test (DUT) instances and implements the -top flag for proper subIP execution, addressing issue #442 regarding directory structure changes in verification.

Key Comments:
amichai-bd (Jan 20-21): Explained that a pycache file was inadvertently committed during the reorganization. This Python-generated file was created when importing local scripts in mem_ss_pp.py. To prevent future generation, the contributor added sys.dont_write_bytecode = True before the import statement and subsequently suggested consolidating the separate ref_orderer.py file directly into the main script.

roman012285: Acknowledged understanding the rationale behind the solution and noted some errors in gui_build.py that were outside the scope of immediate fixes.

Commits:
Two commits were merged:
1. Primary restructuring commit (b72c071)
2. Flow name fix commit (d940f1e)

The branch was subsequently deleted on March 1, 2024.