# sc_core - screen is broken, and there is no reference model in TB

- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/423

2 things to fix:
1) add a reference model and EOT check to make sure IP is running correctly
2) Make sure the display works. (have a dedicated memory region for VGA space)

PR Title: integrate ref model to sc_core_tb and regress level 0
Status: Merged on January 14, 2024

Description:
Roman012285 implemented the following changes:
1. Added a reference model to sc_core_tb
2. Introduced test cases including bubblesort
3. Integrated rv32i_level0 into sc_core (modifying the mafia_sanity SC_CORE configuration)
4. Did not yet work on VGA functionality

The author noted that verification requires adding "+4" to an addition operation; "+1" causes timeouts.

Key Discussion:
Roman asked about releasing sc_core's data memory at line 124 in sc_core.tb.sv.

Amichai-bd responded: "The use of 'Force' is to force the priority to the assignment in the TB over the RTL... I think that in the case of the '$readmemh' its getting priority without the use of 'force'."

He explained that using "$readmemh" for both DMem and NextDMem ensures data memory initialization without explicit release statements.

Metadata:
- Author: roman012285
- Reviewer/Approver: amichai-bd
- Assignee: roman012285
- Labels: RV32I_REF, SC_CORE
- Milestone: MAFIA 0.1
- Linked Issue: #423 (sc_core screen broken, no reference model in TB)