# CNST - add new rule - Source URL: https://github.com/AsFigo/pyslint/issues/184 ```verilog class bli_c; bit foo_sel; rand int foo; constraint cst_1 { foo == (foo_sel) ? 5 :6; } function void post_randomize(); $display ("%p", this); endfunction endclass module m; bli_c u_bli_c_0; initial begin u_bli_c_0 = new(); repeat (5) u_bli_c_0.randomize(); #10; $finish (2); end endmodule ``` https://www.linkedin.com/posts/avidan-efody_appleabrdv-servingthenextbug-systemverilog-activity-7152673318020562944-tI2M?utm_source=share&utm_medium=member_desktop