# COMPAT SVA missing ;

- Source URL: https://github.com/AsFigo/pyslint/issues/174

```verilog
module m;
  bit clk, a, b;

  property p_ex;
    @(posedge clk) a |=> b
  endproperty : p_ex

endmodule : m
```

## PR Content from GitHub

# GitHub Pull Request Summary

**PR Title:** Added rule 174 - COMPAT

**PR Number:** #175

**Status:** Merged

**Author:** svenka3

**Merge Date:** December 8, 2023

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## PR Description
The PR description body is not explicitly shown in the provided content beyond the title.

## Comments

**svenka3** commented:
> "Fixes #174"

This brief comment references the linked issue.

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## Linked Issue

**Issue #174 Title:** "COMPAT SVA missing ;"

The issue title indicates this PR addresses a missing semicolon issue related to COMPAT SVA functionality.

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## Additional Details

- **Commits:** 1 commit merged (09108a8)
- **Branch:** Merged from `i174` into `main`
- **Reviewers:** None listed
- **Assignees:** None listed