# Avoid begin..end around task/function

- Source URL: https://github.com/AsFigo/pyslint/issues/160

```verilog

task Write();
begin

	$display("PADDR %h, PWDATA %h  ",paddr,pwdata);

end

endtask
```

## PR Content from GitHub

# GitHub Pull Request Summary

**PR Title:** Support for issue 160 added

**PR Number:** #167

**Author:** svenka3

**Status:** Merged (Dec 6, 2023)

---

## PR Description Body

The PR description body is not fully visible in the provided content. Only a comment referencing the issue is shown.

---

## PR Comments

**@svenka3** (Dec 6, 2023):
"Fixes #160"

---

## Linked Issue

**Issue #160 Title:** "Avoid begin..end around task/function"

**Issue Body:** Not provided in the source material.

---

## Additional Details

- **Commits:** 1 commit (18608ad)
- **Merged into:** main branch
- **Source branch:** i160
- **Reviews:** None
- **Assignees:** None