# VLT: no clocking blocks in interface

- Source URL: https://github.com/AsFigo/pyslint/issues/165

Verilator does not support clocking block based driving (as of today). Add a rule to check.

## PR Content from GitHub

# PR Summary

**PR Title:** Added rule for CB check for Verilator issue 165

**PR Number:** #166

**Status:** Merged

**Author:** svenka3

**Merge Date:** December 6, 2023

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## PR Description Body

The PR description was not fully visible in the provided content. Only a reference appears:

**Comment by svenka3:**
"Fixes #165"

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## Linked Issue

**Issue #165 Title:** VLT: no clocking blocks in interface

The issue details were not included in the available content, but the PR was designed to address this specific Verilator-related constraint.

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## Additional Context

The pull request contained 1 commit (ea905ff) that was merged into the main branch. The change implements a rule to check for clocking blocks within interfaces, addressing a Verilator linting requirement.