# Avoid begin..end around timing control

- Source URL: https://github.com/AsFigo/pyslint/issues/161

https://verificationacademy.com/forums/systemverilog/memory-read-showing-xxx-values-apb-verification#reply-117165

```verilog
task Write();
begin
   @(negedge pclk) begin 
	 	psel = 1;
       	penb = 0;
     for (int i = 0; i < 64; i=i+1) begin
    @(negedge pclk) begin 
        penb = 1 ;
	 	pwrite = 1;
		paddr = i;
		pwdata = i;
	$display("PADDR %h, PWDATA %h  ",paddr,pwdata);
	 end
end
   end
 end
endtask
 
```