# SVA: expect construct usage - compatibility issue

- Source URL: https://github.com/AsFigo/pyslint/issues/136

https://verificationacademy.com/forums/systemverilog/expect-assertion#answer-117075

```verilog
module test;
 
  bit req1,req2;
  bit clk;
 
  always #5 clk=~clk;
 
 
  initial begin
  #100;
    expect(@(posedge clk) req1 ##2 req2) else $error ("expect failure");
    $display("DONE");
end
 
  initial
    begin
      repeat(10)
        begin
            req1=$urandom;
            req2=$urandom;
            #12;
        end
      $finish;
    end
endmodule
```