diff --git a/snapshots/AsFigo_pyslint_pr140/.github/ISSUE_TEMPLATE/bug_report.md b/snapshots/AsFigo_pyslint_pr140/.github/ISSUE_TEMPLATE/bug_report.md new file mode 100644 index 0000000000000000000000000000000000000000..e1f5f208ae6c74b26c910e133c63dec705d7b6ff --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/.github/ISSUE_TEMPLATE/bug_report.md @@ -0,0 +1,26 @@ +--- +name: Bug report +about: Create a report to help us improve +title: '' +labels: '' +assignees: '' + +--- + +**Describe the bug/issue** +A clear and concise description of what the bug is. Specifically if you disagree with a PySlint Violation, mention the specific RULE_ID (e.g. I expected the rule NAME_AST_PREFIX not to fire on this assertion as the label is correct). + +**To Reproduce** +Steps to reproduce the behavior: +1. python3 ../py_src/pyslint.py -t ../sv_tests/my_issue.sv + +Add sample log below + +**Expected behavior** +A clear and concise description of what you expected to happen. + +Either you did NOT expect this Violation or you expected a Violation to be flagged, but unfortunately, PySlint did not flag it. + + +**Additional context** +Add any other context about the problem here. diff --git a/snapshots/AsFigo_pyslint_pr140/.github/ISSUE_TEMPLATE/feature-request.md b/snapshots/AsFigo_pyslint_pr140/.github/ISSUE_TEMPLATE/feature-request.md new file mode 100644 index 0000000000000000000000000000000000000000..164699681ff51bc125f97a55e797057d86825ed9 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/.github/ISSUE_TEMPLATE/feature-request.md @@ -0,0 +1,20 @@ +--- +name: Feature request +about: Suggest an idea for this project +title: '' +labels: '' +assignees: '' + +--- + +**Is your feature request related to a new rule? Please describe.** +A clear and concise description of what the rule you want to see being implemented. + +**Describe the solution you'd like** +A clear and concise description of what you want to happen. + +**Describe alternatives you've considered** +A clear and concise description of any alternative solutions or features you've considered. + +**Additional context** +Add any other context or screenshots about the feature request here. diff --git a/snapshots/AsFigo_pyslint_pr140/exec_dir/Makefile b/snapshots/AsFigo_pyslint_pr140/exec_dir/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..1cabed2a0edd57fc69425035ae59629205bf0acf --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/exec_dir/Makefile @@ -0,0 +1,94 @@ +run: naming + +naming: + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_01_p.sv > pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_cg_arr_bin_default_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_cg_ill_bins_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_cg_type_opt_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_cnst_arr_method.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_dpi_openar_1_p.c >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_dpi_openar_1_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_dpi_rval_2st_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_dpi_spec_str_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_enum_inside_mod_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_02_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_03_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_04_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_05_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_06_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_07_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_08_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_09_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_10_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_11_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_12_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_13_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_14_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_15_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_16_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_17_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_18_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_19_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_20_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_21_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_22_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_23_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_naming_24_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_proc_conc_in_fe_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_proc_conc_in_for_loop_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_proc_conc_in_while_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_qual_1_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_qual_2_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_qual_cg_cv32e40x_mod_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_wc_assoc_array_26_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_uvm_driver_param.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_sva_emp_mat_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_sva_emp_mat_1_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_sva_emp_mat_2_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/AxiPC.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_reuse_one_cl_def_27_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_reuse_one_cl_def_27_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_reuse_one_mod_def_27_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_reuse_one_mod_def_27_p.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue92_auto_var.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue94_counter.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_106_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_108_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_109_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_110_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_111_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_112_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_113_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_114_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_115_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_118_inters.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_119_local_var.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_120_seq_untyped.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_121_temp.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_122_test2_5_4.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_123_test_models_temp.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_124_test_vacurity.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_125_unexpectedA_5_2.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_126_unexpectedB_5_2.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_127_unique_m.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_128_uvm_sva_ex.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_90_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_92_auto_var.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_93_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_94_counter.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_96_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_35.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_35_1.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_37.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_37_1.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_37_2.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_37_3.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_40.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_41.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_42.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_sv_issue_49_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_136_f.sv >> pyslint.log + python3 ../py_src/pyslint.py -t ../sv_tests/test_issue_137_f.sv >> pyslint.log + + cat pyslint.log + diff --git a/snapshots/AsFigo_pyslint_pr140/exec_dir/pyslint.log b/snapshots/AsFigo_pyslint_pr140/exec_dir/pyslint.log new file mode 100644 index 0000000000000000000000000000000000000000..ae2fc039d0548a3b5e2f531ad2f02e6282a923cd --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/exec_dir/pyslint.log @@ -0,0 +1,859 @@ +PySlint: Violation: [PERF_CG_NO_ABIN_W_DEF_CL]: Found Array-bins: + covergroup: cg_with_arr_def + coverpoint: i + BIN: others + bins others[] = default; + + While IEEE 1800 LRM allows this syntax, this is bad for Performance aspect as it ends up creating large number of bins. Recommended to remove this bin. +PySlint: Violation: [REUSE_CG_NO_ILBINS_CL]: Found 'illegal_bins' under user-defined bins: +covergroup: cg_o_sig for coverpoint: cpt_osig : o_sig_8b invalid_vals +While IEEE 1800 LRM allows this syntax, this is bad for REUSE aspect as it does not flag as UVM_ERROR or $error. +Also if coverage is turned OFF, this error is likely to go unflagged. Recommended to use 'ignore_bins' instead +from coverage perspective and add SVA or scoreboard for illegal values. +PySlint: Violation: [COMPAT_CG_OPT_PI_CL]: Found 'type_option.per_instance' inside a covergroup: cg_o_sig +IEEE 1800 LRM does not allow such usage though some tools do compile. +To avoid compatibility issues, please move the per_instance to 'option.per_instance ' +PySlint: Violation: [FUNC_CNST_MISSING_CAST]: Potentially incorrect constraint expression! An expression involving the array-reduction methods sum()/product()/and()/or()/xor() was found, but is missing an explicit cast. This can lead to strange results as array reduction methods return an expression of the size of its elements, check if you need a with (int'( cast around the following expression: + num_list.sum() +PySlint: Violation: [FUNC_CNST_MISSING_CAST]: Potentially incorrect constraint expression! An expression involving the array-reduction methods sum()/product()/and()/or()/xor() was found, but is missing an explicit cast. This can lead to strange results as array reduction methods return an expression of the size of its elements, check if you need a with (int'( cast around the following expression: + num_list.and() +PySlint: Violation: [FUNC_CNST_MISSING_CAST]: Potentially incorrect constraint expression! An expression involving the array-reduction methods sum()/product()/and()/or()/xor() was found, but is missing an explicit cast. This can lead to strange results as array reduction methods return an expression of the size of its elements, check if you need a with (int'( cast around the following expression: + num_list.xor() +PySlint: Violation: [FUNC_CNST_MISSING_CAST]: Potentially incorrect constraint expression! An expression involving the array-reduction methods sum()/product()/and()/or()/xor() was found, but is missing an explicit cast. This can lead to strange results as array reduction methods return an expression of the size of its elements, check if you need a with (int'( cast around the following expression: + num_list.product() +PySlint: Violation: [FUNC_DPI_NO_4STATE_IN_RETURN]: DPI functions shall use 2-state types in return value. Using 4-state type can lead to unnecessary complication as C-side does not naturally support 4-state value system Found code as: + + import "DPI-C" function integer c_sum(input bit [31:0] input_array[]); +PySlint: Violation: [COMPAT_DPI_OLD_SPECSTR]: Wrong Spec-STR in DPI declaration IEEE 1800-2012 specifies "DPI-C" as Spec-STR. Found code as: + + import "DPI" function int c_sum(input bit [31:0] input_array[]); +PySlint: Violation: [REUSE_NO_TDEF_IN_MOD]: A typedef was found inside a module This prevents reuse as the enum/typedef scope is module only An assertion model that binds to this module and check the states using the typedef will be harder to implement in such cases. Please move the typedef to a package and import that package inside the module + typedef enum logic [1:0] {S0, S1, S2} state_t; +PySlint: Violation: [NAME_INTF_SUFFIX]: Improper naming of identifier: af_sv_intf_bad: expected suffix: _if +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: af_bad_class_name: expected suffix: _c +PySlint: Violation: [NAME_CG_PREFIX]: Improper naming of identifier: bad_group_name: expected prefix: cg_ +PySlint: Violation: [NAME_CG_PREFIX]: Improper naming of identifier: bad_group_name: expected prefix: cg_ +PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: + // BAD - unnamed SVA + assert property (@(posedge clk) var1) + else $error ("Bad style - unnamed SVA"); +PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: + // BAD - unnamed SVA + assert property (@(posedge clk) var1) + else $error ("Bad style - unnamed SVA"); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: bad_sva_label: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // BAD - missing FAIL action block in SVA + a_var1 : assert property (@(posedge clk) var1); +PySlint: Violation: [SVA_NO_PASS_AB]: Avoid using PASS Action block - likely to cause too many vacuous prints: + // BAD - avoid using PASS action block in SVA + // It usually leads to too many vacuous prints + a_var1 : assert property (@(posedge clk) var1) + begin : pass_ab + $info ("Pass Action Block"); + end : pass_ab + else $error ("Fail AB"); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: bad_name: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: p_good_name +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: bad_name: expected prefix: p_ +PySlint: Violation: [NAME_ASM_PREFIX]: Improper naming of assume directive: wrong_label: expected prefix: m_ +PySlint: Violation: [NAME_COV_PREFIX]: Improper naming of cover directive: wrong_label: expected prefix: c_ +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: should_have_been_extern +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: ex_c +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_new : assert property ((@posedge clk) p_req_cycle +PySlint: Violation: [SVA_NO_PASS_AB]: Avoid using PASS Action block - likely to cause too many vacuous prints: + a_new : assert property ((@posedge clk) p_req_cycle +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: randvar: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: randvar +PySlint: Violation: [COMPAT_SVA_NO_CONC_IN_FE]: A procedural concurrent assertion was found inside a forever loop; IEEE 1800 LRM does not allow such usage though some tools do compile To avoid compatibility issues, please remodel the code: + forever_asrt: assert property(forever_pp); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: always_pp: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: always_pp +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: forever_pp: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: forever_pp +PySlint: Violation: [COMPAT_SVA_NO_CONC_IN_FE]: A procedural concurrent assertion was found inside a forever loop; IEEE 1800 LRM does not allow such usage though some tools do compile To avoid compatibility issues, please remodel the code: + forever_asrt: assert property(forever_pp); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: always_pp: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: always_pp +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: forever_pp: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: forever_pp +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: always_pp: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: always_pp +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: a_imp_b: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: a_imp_b +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: disp +PySlint: Violation: [REUSE_NO_WILDC_AA_CL]: Found an associative array declaration with wild-card as key + + string fruits[*]; +This is bad for reuse as it does not allow 'foreach' iterator and other handy built-in functions. +Consider using a typed key such as int/string etc. +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: alu_driver: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: build_phase +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: connect_phase +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: run_phase +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: drive +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: extension: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: extension +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: ab: expected prefix: p_ +PySlint: Violation: [COMPAT_SVA_NO_DEGEN_CONSEQ]: Empty match ([*0] or variants) found in a property expression. + Though some compilers allow this, IEEE 1800 LRM prevents such usage, so for maximum compatibility across EDA + tools and LRM compliance, please remove the empty match. + a |=> b[=0] +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: ab +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_p_ab : assert property (ab); +PySlint: Violation: [COMPAT_SVA_NO_DEGEN_CONSEQ]: Empty match ([*0] or variants) found in a property expression. + Though some compilers allow this, IEEE 1800 LRM prevents such usage, so for maximum compatibility across EDA + tools and LRM compliance, please remove the empty match. + + (a[*0]) +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_p_empty_sequence_1 : assert property (p_empty_sequence_1); +PySlint: Violation: [COMPAT_SVA_NO_DEGEN_CONSEQ]: Empty match ([*0] or variants) found in a property expression. + Though some compilers allow this, IEEE 1800 LRM prevents such usage, so for maximum compatibility across EDA + tools and LRM compliance, please remove the empty match. + + (a |-> a[*0:3]) +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_p_empty_sequence_2 : assert property (empty_sequence_2); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWADDR_BOUNDARY: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWADDR_BOUNDARY +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awaddr_boundary: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWADDR_WRAP_ALIGN: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWADDR_WRAP_ALIGN +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awaddr_wrap_align: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWBURST: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWBURST +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awburst: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWCACHE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWCACHE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awcache: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLEN_WRAP: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLEN_WRAP +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlen_wrap: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK_END: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK_END +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock_end: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK_ID: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK_ID +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock_id: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK_LAST: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK_LAST +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock_last: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK_START: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK_START +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock_start: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWSIZE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWSIZE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awsize: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWVALID_RESET: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWVALID_RESET +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awvalid_reset: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_AWLOCK_BOUNDARY: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_AWLOCK_BOUNDARY +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_awlock_boundary: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_AWLOCK_CTRL: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_AWLOCK_CTRL +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_awlock_ctrl: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_AWLOCK_NUM: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_AWLOCK_NUM +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_awlock_num: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWADDR_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWADDR_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awaddr_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWBURST_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWBURST_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awburst_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWCACHE_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWCACHE_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awcache_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLEN_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLEN_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlen_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWPROT_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWPROT_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awprot_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWSIZE_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWSIZE_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awsize_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWVALID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWVALID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awvalid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECS_AWREADY_MAX_WAIT: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECS_AWREADY_MAX_WAIT +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recs_awready_max_wait: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWADDR_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWADDR_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awaddr_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWBURST_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWBURST_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awburst_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWCACHE_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWCACHE_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awcache_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLEN_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLEN_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlen_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWLOCK_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWLOCK_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awlock_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWPROT_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWPROT_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awprot_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWSIZE_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWSIZE_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awsize_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWVALID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWVALID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awvalid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_AWREADY_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_AWREADY_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_awready_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WDATA_NUM: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WDATA_NUM +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wdata_num: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WDATA_ORDER: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WDATA_ORDER +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wdata_order: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WDEPTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WDEPTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wdepth: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WSTRB: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WSTRB +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wstrb: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WVALID_RESET: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WVALID_RESET +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wvalid_reset: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WDATA_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WDATA_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wdata_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WLAST_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WLAST_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wlast_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WSTRB_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WSTRB_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wstrb_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WVALID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WVALID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wvalid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECS_WREADY_MAX_WAIT: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECS_WREADY_MAX_WAIT +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recs_wready_max_wait: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WDATA_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WDATA_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wdata_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WLAST_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WLAST_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wlast_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WSTRB_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WSTRB_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wstrb_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WVALID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WVALID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wvalid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_WREADY_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_WREADY_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_wready_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BRESP: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BRESP +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bresp: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BRESP_EXOKAY: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BRESP_EXOKAY +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bresp_exokay: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BVALID_RESET: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BVALID_RESET +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bvalid_reset: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECS_BRESP: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECS_BRESP +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recs_bresp: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BRESP_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BRESP_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bresp_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BVALID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BVALID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bvalid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_BREADY_MAX_WAIT: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_BREADY_MAX_WAIT +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_bready_max_wait: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_BREADY_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_BREADY_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_bready_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BRESP_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BRESP_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bresp_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BVALID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BVALID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_bvalid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARADDR_BOUNDARY: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARADDR_BOUNDARY +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_araddr_boundary: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARADDR_WRAP_ALIGN: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARADDR_WRAP_ALIGN +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_araddr_wrap_align: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARBURST: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARBURST +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arburst: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARCACHE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARCACHE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arcache: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLEN_WRAP: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLEN_WRAP +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlen_wrap: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK_END: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK_END +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock_end: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK_ID: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK_ID +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock_id: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK_LAST: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK_LAST +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock_last: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK_START: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK_START +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock_start: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARSIZE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARSIZE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arsize: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARVALID_RESET: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARVALID_RESET +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arvalid_reset: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_ARLOCK_BOUNDARY: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_ARLOCK_BOUNDARY +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_arlock_boundary: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_ARLOCK_CTRL: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_ARLOCK_CTRL +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_arlock_ctrl: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_ARLOCK_NUM: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_ARLOCK_NUM +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_arlock_num: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARADDR_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARADDR_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_araddr_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARBURST_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARBURST_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arburst_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARCACHE_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARCACHE_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arcache_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLEN_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLEN_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlen_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARPROT_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARPROT_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arprot_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARSIZE_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARSIZE_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arsize_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARVALID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARVALID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arvalid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECS_ARREADY_MAX_WAIT: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECS_ARREADY_MAX_WAIT +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recs_arready_max_wait: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARADDR_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARADDR_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_araddr_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARBURST_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARBURST_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arburst_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARCACHE_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARCACHE_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arcache_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLEN_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLEN_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlen_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARLOCK_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARLOCK_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arlock_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARPROT_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARPROT_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arprot_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARSIZE_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARSIZE_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arsize_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARVALID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARVALID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_arvalid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_ARREADY_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_ARREADY_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_arready_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RDATA_NUM: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RDATA_NUM +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rdata_num: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RID: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RID +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rid: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RRESP_EXOKAY: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RRESP_EXOKAY +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rresp_exokay: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RVALID_RESET: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RVALID_RESET +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rvalid_reset: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RDATA_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RDATA_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rdata_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RLAST_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RLAST_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rlast_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RRESP_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RRESP_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rresp_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RVALID_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RVALID_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rvalid_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_RREADY_MAX_WAIT: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_RREADY_MAX_WAIT +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_rready_max_wait: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RDATA_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RDATA_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rdata_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_RREADY_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_RREADY_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_rready_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RLAST_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RLAST_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rlast_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RRESP_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RRESP_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rresp_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RVALID_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RVALID_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_rvalid_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CSYSACK_FALL: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CSYSACK_FALL +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_csysack_fall: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CSYSACK_RISE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CSYSACK_RISE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_csysack_rise: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CSYSREQ_FALL: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CSYSREQ_FALL +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_csysreq_fall: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CSYSREQ_RISE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CSYSREQ_RISE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_csysreq_rise: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CACTIVE_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CACTIVE_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_cactive_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CSYSACK_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CSYSACK_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_csysack_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRL_CSYSREQ_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRL_CSYSREQ_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errl_csysreq_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_EXCL_ALIGN: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_EXCL_ALIGN +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_excl_align: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_EXCL_LEN: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_EXCL_LEN +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_excl_len: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_EXCL_MATCH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_EXCL_MATCH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_excl_match: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_EXCL_MAX: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_EXCL_MAX +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_excl_max: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_RECM_EXCL_PAIR: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_RECM_EXCL_PAIR +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_recm_excl_pair: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWUSER_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWUSER_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awuser_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WUSER_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WUSER_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wuser_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BUSER_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BUSER_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_buser_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARUSER_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARUSER_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_aruser_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RUSER_STABLE: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RUSER_STABLE +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_ruser_stable: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_AWUSER_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_AWUSER_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_awuser_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_WUSER_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_WUSER_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_wuser_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_BUSER_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_BUSER_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_buser_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRM_ARUSER_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRM_ARUSER_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errm_aruser_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_ERRS_RUSER_X: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_ERRS_RUSER_X +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_errs_ruser_x: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_DATA_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_DATA_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_data_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_ADDR_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_ADDR_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_addr_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_AWUSER_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_AWUSER_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_awuser_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_WUSER_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_WUSER_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_wuser_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_BUSER_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_BUSER_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_buser_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_ARUSER_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_ARUSER_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_aruser_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_RUSER_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_RUSER_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_ruser_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_ID_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_ID_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_id_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_EXMON_WIDTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_EXMON_WIDTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_exmon_width: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_WDEPTH: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_WDEPTH +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_wdepth: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_MAXRBURSTS: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_MAXRBURSTS +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_maxrbursts: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_MAXWBURSTS: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_MAXWBURSTS +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_maxwbursts: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_RCAM_OVERFLOW: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_RCAM_OVERFLOW +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_rcam_overflow: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_RCAM_UNDERFLOW: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_RCAM_UNDERFLOW +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_rcam_underflow: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_WCAM_OVERFLOW: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_WCAM_OVERFLOW +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_wcam_overflow: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_WCAM_UNDERFLOW: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_WCAM_UNDERFLOW +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_wcam_underflow: expected prefix: a_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: AXI_AUXM_EXCL_OVERFLOW: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_ENDLABEL]: Missing End Label for property: AXI_AUXM_EXCL_OVERFLOW +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: axi_auxm_excl_overflow: expected prefix: a_ +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_MOD_PER_FILE]: Always use one-module definition per file +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_q_test: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_q_test: assert property(q_test); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: q_req_ack: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_q_req_ack : assert property (q_req_ack); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pCounterMaxed: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apCounterMaxed: expected prefix: a_ +PySlint: Violation: [REUSE_NO_TDEF_IN_MOD]: A typedef was found inside a module This prevents reuse as the enum/typedef scope is module only An assertion model that binds to this module and check the states using the typedef will be harder to implement in such cases. Please move the typedef to a package and import that package inside the module + typedef logic [WIDTH-1 : 0] word_t; +PySlint: Violation: [REUSE_NO_TDEF_IN_MOD]: A typedef was found inside a module This prevents reuse as the enum/typedef scope is module only An assertion model that binds to this module and check the states using the typedef will be harder to implement in such cases. Please move the typedef to a package and import that package inside the module + typedef word_t [0 : (2**BIT_DEPTH-1)] buffer_t; +PySlint: Violation: [REUSE_ONE_MOD_PER_FILE]: Always use one-module definition per file +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_push_error_1: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_push_error_1 : assert property (p_push_error); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_pop_error_1: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_pop_error_1 : assert property (p_pop_error); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_read_data_integrity: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_read_data_integrity : assert property (p_read_data_integrity); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_never_read_on_empty: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_never_read_on_empty : assert property (p_never_read_on_empty); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_write_on_max_buff: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_write_on_max_buff : assert property (p_never_write_on_max_buff); +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: c_xactn: expected suffix: _c +PySlint: Violation: [REUSE_ONE_MOD_PER_FILE]: Always use one-module definition per file +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_read_after_write: expected prefix: a_ +PySlint: Violation: [SVA_NO_PASS_AB]: Avoid using PASS Action block - likely to cause too many vacuous prints: + ap_read_after_write : assert property (p_read_after_write) + $info("addr =%h, rdata=%h", $sampled(addr), $sampled(rdata)); else + $error("addr =%h, rdata=%h", $sampled(addr), $sampled(rdata)); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_read_before_write: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_read_before_write : assert property (p_read_before_write); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_read_after_write: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_read_after_write : assert property (p_read_after_write); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_read_before_write: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_read_before_write : assert property (p_read_before_write); +PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: + assert property(@(posedge clk) p_never_read_on_empty); +PySlint: Violation: [SVA_MISSING_LABEL]: Unnamed assumption - use a meaningful label: + assert property(@(posedge clk) p_never_read_on_empty); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apxxOK: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // Asserting on an illegal multiply clocked temporal expression. + // The clock flow cannot change in the RHS of 'intersect' operator. +// apxx: assert property( +// @ (posedge clk) e |-> (a ##1 b) intersect (@ (posedge clk2) c ##1 d)); // +// + apxxOK: assert property( + @ (posedge clk) e |-> (a ##1 b) intersect (e ##1 @ (posedge clk2) c ##1 @ (posedge clk) d)); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: P: expected prefix: p_ +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: P_init: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_P: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_P: assert property(P_init); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: P3_OK: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_P3: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_P3: assert property(P3_OK); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: P3_Illegal: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_Illegal: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_Illegal: assert property(P3_Illegal); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: P4: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_P4: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_P4: assert property(P4); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: P5: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_P5: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_P5: assert property(P5); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_never_q_logic_untyped: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // equivalent to (not (a!=b ##2 a8==8'FF) ) + ap_never_q_logic_untyped: assert property( + not(q_logic_untyped(a, b, a8==8'hFF)) + ); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_bits: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // equivalent to ($rose(e) |-> a ##2 b) + ap_bits: assert property($rose(e) |-> q_untyped(a, b)); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_bits2: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // equivalent to ( b ##2 a8==d8) |-> f + ap_bits2: assert property(q_untyped(b, a8==d8) |-> f); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_sequences: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // equivalent to $rose(f) |-> ($rose(a) ##1 b[->1] ##1 c) ##2 (d==e) + ap_sequences: assert property($rose(f) |-> q_untyped(q_abc, + q_mn( d, e))); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_int: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // equivalent to $rose(e) |-> i==j + ap_int: assert property($rose(e) |-> q_mn(a8, d8)); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: a1: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + // equivalent to e ##2 f[*3:$] + a1: assert property(q_delay(e, f ,3,50, 2)); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_ab: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_ab: assert property (@ (posedge clk) + disable iff (!go) // if go==0, cancel checking asynchronously + a |=> b); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pReqAck: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apReqAck: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + apReqAck : assert property(@ (posedge clk) pReqAck($rose(req), ack, max)); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pAckDone: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apAckDone: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + apAckDone : assert property(@ (posedge clk) pAckDone($rose(ack), xfr, 2)); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apReqAckDoneSuccess: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + apReqAckDoneSuccess: assert property( + first_match($rose(req) ##[1:5] ack ##[1:100] done) + |-> (status_reg == 1'b0) ); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apReqAckDoneFail: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + apReqAckDoneFail: assert property( + $rose(req) |=> !done[*105] |-> (status_reg == 1'b1) ); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: vac_true: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_vac_true: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_vac_true: assert property(vac_true); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_vac_false: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_vac_false: assert property(not(vac_true)); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_vac_not_false: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_vac_not_false: assert property(not(not(vac_true))) count_of_ap_vac_not_false++; +PySlint: Violation: [SVA_NO_PASS_AB]: Avoid using PASS Action block - likely to cause too many vacuous prints: + ap_vac_not_false: assert property(not(not(vac_true))) count_of_ap_vac_not_false++; +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_reject_on: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_reject_on: assert property(reject_on(1'b1) 1'b1); +PySlint: Violation: [REUSE_NO_TDEF_IN_MOD]: A typedef was found inside a module This prevents reuse as the enum/typedef scope is module only An assertion model that binds to this module and check the states using the typedef will be harder to implement in such cases. Please move the typedef to a package and import that package inside the module +typedef enum {IDLE, STATE1, STATE2, STATE3} state_enum; +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: UNEXPECTED_PROP: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_UNEXPECTED_PROP : assert property (UNEXPECTED_PROP); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: UNEXPECTED_PROP: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: UA1: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + UA1: assert property (UNEXPECTED_PROP); +PySlint: Violation: [REUSE_ONE_MOD_PER_FILE]: Always use one-module definition per file +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: p: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_active_bus: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_active_bus : assert property( + disable iff (bus_switch) + if (bus_select) p + else p); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_an_an_co: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_an_an_co: assert property(@ (posedge clk) + a[*1:2] |-> ##[1:3] b |=> c[*1:2]); +PySlint: Violation: [NAME_ASM_PREFIX]: Improper naming of assume directive: am_an_an_co: expected prefix: m_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_an_an_coFM: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_an_an_coFM: assert property(@ (posedge clk) + first_match(a[*1:2]) |-> + first_match(##[1:3] b) |=> c[*1:2]); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_q_test: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_q_test: assert property(q_test); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: q_req_ack: expected prefix: p_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + a_q_req_ack : assert property (q_req_ack); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pNeverReadWrite: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: d17assert: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + d17assert : assert property (pNeverReadWrite); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pReadSchedule: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: d17assert1: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + d17assert1 : assert property (pReadSchedule); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pWriteSchedule: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: d17assert2: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + d17assert2 : assert property (pWriteSchedule); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: d17assert3: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + d17assert3 : assert property (qNewInterrupt); +PySlint: Violation: [NAME_PROP_PREFIX]: Improper naming of property: pCounterMaxed: expected prefix: p_ +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: apCounterMaxed: expected prefix: a_ +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: generator: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: generator +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: gen: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: pre_randomize +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: post_randomize +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: gen +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: transaction: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: display +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: copy +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: transaction +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: generator: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: run +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: generator +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: driver: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: reset +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: run +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: driver +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: monitor: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: run +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: monitor +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: scoreboard: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: run +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: scoreboard +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: environment: expected suffix: _c +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: pre_test +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: test +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: post_test +PySlint: Violation: [CL_METHOD_NOT_EXTERN]: method is not declared extern: run +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: environment +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [REUSE_ONE_CL_PER_FILE]: Always use one-class definition per file +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: distribution: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: distribution +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: distribution: expected suffix: _c +PySlint: Violation: [FUNC_CNST_DIST_COL_EQ]: Potentially incorrect constraint expression! An expression involving dist ColonEquals if found And the range used with ColonEquals is large This is likely to skew the random generation and prevent other values in the dist expression to be generated less-frequently than the large range values Review to check if you intended to use ColonSlash instead of ColonEquals + data1_bad dist {0:=10, [1:30]:=60} +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: distribution +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: data: expected suffix: _c +PySlint: Violation: [FUNC_CNST_DIST_COL_EQ]: Potentially incorrect constraint expression! An expression involving dist ColonEquals if found And the range used with ColonEquals is large This is likely to skew the random generation and prevent other values in the dist expression to be generated less-frequently than the large range values Review to check if you intended to use ColonSlash instead of ColonEquals field1 dist {[0:31] := 1, [32:65535] := 1} +PySlint: Violation: [FUNC_CNST_DIST_COL_EQ]: Potentially incorrect constraint expression! An expression involving dist ColonEquals if found And the range used with ColonEquals is large This is likely to skew the random generation and prevent other values in the dist expression to be generated less-frequently than the large range values Review to check if you intended to use ColonSlash instead of ColonEquals field1 dist {[0:31] := 1, [32:65535] := 1} +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: data +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: clk: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: clk +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: A: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: A +PySlint: Violation: [NAME_CLASS_SUFFIX]: Improper naming of identifier: c: expected suffix: _c +PySlint: Violation: [CL_MISSING_ENDLABEL]: Missing End Label for class: c +PySlint: Violation: [FUNC_NO_2STATE_IN_INTF]: Potential DUT bug hiding construct in use: Inside SystemVerilog interface, it is recommended to use only 4-state signals/nets. Found a 2-state declaration as: + bit bad_2st; +PySlint: Violation: [FUNC_NO_2STATE_IN_INTF]: Potential DUT bug hiding construct in use: Inside SystemVerilog interface, it is recommended to use only 4-state signals/nets. Found a 2-state declaration as: + bit [7:0] bad_2st_vec; +PySlint: Violation: [FUNC_NO_2STATE_IN_INTF]: Potential DUT bug hiding construct in use: Inside SystemVerilog interface, it is recommended to use only 4-state signals/nets. Found a 2-state declaration as: + bit [3:0] bad_2st_2d [10]; +PySlint: Violation: [FUNC_NO_2STATE_IN_INTF]: Potential DUT bug hiding construct in use: Inside SystemVerilog interface, it is recommended to use only 4-state signals/nets. Found a 2-state declaration as: + bit [9:0] bad_2st_3d [10][5]; +PySlint: Violation: [COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT]: A procedural 'expect' construct with temporal expression was found inside an initial block; IEEE 1800 LRM does allow such usage though some tools do NOT support To avoid compatibility issues, please remodel the code: + expect (@(posedge clk) req1 ##1 1); +PySlint: Violation: [COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT]: A procedural 'expect' construct with temporal expression was found inside an initial block; IEEE 1800 LRM does allow such usage though some tools do NOT support To avoid compatibility issues, please remodel the code: + expect(@(posedge clk) req1 ##2 req2) else $error ("expect failure"); +PySlint: Violation: [NAME_AST_PREFIX]: Improper naming of assert directive: ap_ReqAckBusy: expected prefix: a_ +PySlint: Violation: [SVA_MISSING_FAIL_AB]: Missing FAIL Action block - use $error/`uvm_error: + ap_ReqAckBusy: assert property($rose(req) |=> busy s_until_with ack ); +PySlint: Violation: [COMPAT_SVA_NO_S_UNTIL_WITH]: Found usage of s_util_with on consequent of a concurrent assertion. + Though LRM supports this, some compilers do NOT support this. So for maximum compatibility across EDA + tools consider remodeling this SVA. +$rose(req) |=> busy s_until_with ack diff --git a/snapshots/AsFigo_pyslint_pr140/py_src/pyslint.py b/snapshots/AsFigo_pyslint_pr140/py_src/pyslint.py new file mode 100644 index 0000000000000000000000000000000000000000..d53ed436b50f30a1ec6d9d25f45501f5fd719b6d --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/py_src/pyslint.py @@ -0,0 +1,857 @@ +# ---------------------------------------------------- +# SPDX-FileCopyrightText: Srinivasan Venkataramanan, +# AsFigo Technologies, UK +# SPDX-License-Identifier: MIT +# ---------------------------------------------------- + +import pyslang +import argparse +import tomli +import copy +import functools + +# Fix labels Done +# Add lv_id Done + +def rhasattr(obj, path): + try: + functools.reduce(getattr, path.split("."), obj) + return True + except AttributeError: + return False + +print_verbose = False + +def pyslint_update_rule_ids(): + lv_sv_ruleid_l = list() + lv_sv_ruleid_l.append('NAME_INTF_SUFFIX') + lv_sv_ruleid_l.append('NAME_CLASS_SUFFIX') + lv_sv_ruleid_l.append('NAME_CNST_SUFFIX') + lv_sv_ruleid_l.append('NAME_CG_PREFIX') + lv_sv_ruleid_l.append('NAME_CP_PREFIX') + lv_sv_ruleid_l.append('NAME_CR_PREFIX') + lv_sv_ruleid_l.append('NAME_PROP_PREFIX') + lv_sv_ruleid_l.append('NAME_AST_PREFIX') + lv_sv_ruleid_l.append('NAME_ASM_PREFIX') + lv_sv_ruleid_l.append('NAME_COV_PREFIX') + lv_sv_ruleid_l.append('SVA_MISSING_FAIL_AB') + lv_sv_ruleid_l.append('SVA_MISSING_LABEL') + lv_sv_ruleid_l.append('SVA_MISSING_ENDLABEL') + lv_sv_ruleid_l.append('SVA_NO_PASS_AB') + lv_sv_ruleid_l.append('COMPAT_SVA_NO_CONC_IN_FE') + lv_sv_ruleid_l.append('COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT') + lv_sv_ruleid_l.append('COMPAT_DPI_OLD_SPECSTR') + lv_sv_ruleid_l.append('CL_METHOD_NOT_EXTERN') + lv_sv_ruleid_l.append('CL_MISSING_ENDLABEL') + lv_sv_ruleid_l.append('PERF_CG_TOO_MANY_CROSS') + lv_sv_ruleid_l.append('FUNC_CNST_MISSING_CAST') + lv_sv_ruleid_l.append('FUNC_CNST_WRONG_OPER_PRI') + lv_sv_ruleid_l.append('FUNC_CNST_DIST_COL_EQ') + lv_sv_ruleid_l.append('REUSE_NO_TDEF_IN_MOD') + lv_sv_ruleid_l.append('COMPAT_CG_OPT_PI_CL') + lv_sv_ruleid_l.append('REUSE_CG_NO_ILBINS_CL') + lv_sv_ruleid_l.append('REUSE_NO_WILDC_AA_CL') + lv_sv_ruleid_l.append('PERF_CG_NO_ABIN_W_DEF_CL') + lv_sv_ruleid_l.append('COMPAT_SVA_NO_DEGEN_CONSEQ') + lv_sv_ruleid_l.append('COMPAT_SVA_NO_DEGEN_AST') + lv_sv_ruleid_l.append('REUSE_ONE_CL_PER_FILE') + lv_sv_ruleid_l.append('REUSE_ONE_MOD_PER_FILE') + lv_sv_ruleid_l.append ('DBG_SVA_AST_MISSING_LABEL') + lv_sv_ruleid_l.append ('DBG_SVA_ASM_MISSING_LABEL') + lv_sv_ruleid_l.append ('DBG_SVA_COV_MISSING_LABEL') + +''' +with open("cfg.toml", mode="rb") as fp: + config = tomli.load(fp) + #print(config) +''' + +def pyslint_rule_enabled(rule_id): + return True + +def pyslint_msg(rule_id, msg): + if (pyslint_rule_enabled(rule_id)): + pyslint_str = 'PySlint: Violation: [' + pyslint_str += rule_id + pyslint_str += ']: ' + pyslint_str += msg + print(pyslint_str) + +#PySlint: Error Use extern methods +def CL_METHOD_NOT_EXTERN(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ClassDeclaration'): + for cl_item in (lv_cu_scope.items): + + if (cl_item.kind.name == 'ClassMethodDeclaration'): + if (cl_item.declaration.prototype.name.kind.name != 'ConstructorName'): + msg = 'method is not declared extern: '+ str(cl_item.declaration.prototype.name) + lv_rule_id = "CL_METHOD_NOT_EXTERN" + pyslint_msg(lv_rule_id, msg) + +def FUNC_CNST_DIST_COL_EQ(cnst_i): + for lv_dist_item_i in cnst_i.expr.distribution.items: + lv_cnst_expr_s = cnst_i.expr.__str__() + lv_large_range = False + if (lv_dist_item_i.kind.name == 'DistItem'): + if (lv_dist_item_i.range.kind.name == 'OpenRangeExpression'): + lv_large_range = False + lv_dist_range_left = int(lv_dist_item_i.range.left.literal.value) + lv_dist_range_right = int(lv_dist_item_i.range.right.literal.value) + if (abs(lv_dist_range_right - lv_dist_range_left) > 10): + lv_large_range = True + + + if (lv_dist_item_i.weight.op.kind.name == 'ColonEquals'): + if (lv_large_range): + msg = 'Potentially incorrect constraint expression!' + msg += ' An expression involving dist ColonEquals if found' + msg += ' And the range used with ColonEquals is large' + msg += ' This is likely to skew the random generation' + msg += ' and prevent other values in the dist expression' + msg += ' to be generated less-frequently than the large range values' + msg += ' Review to check if you intended to use ColonSlash' + msg += ' instead of ColonEquals' + msg += lv_cnst_expr_s + lv_rule_id = 'FUNC_CNST_DIST_COL_EQ' + pyslint_msg(lv_rule_id, msg) + +def FUNC_CNST_MISSING_CAST (lv_cu_scope): + if (lv_cu_scope.kind.name == 'ClassDeclaration'): + for cl_item in (lv_cu_scope.items): + if (cl_item.kind.name == 'ConstraintDeclaration'): + for lv_cnst_i in (cl_item.block.items): + if (not hasattr(lv_cnst_i, 'expr')): + continue + # Fix for Issue 35, Unary expressions + # do not have left/right + if (lv_cnst_i.expr.kind.name == 'UnaryLogicalNotExpression'): + continue + # Fix for Issue 36, inside expressions + # do not have left/right + if (lv_cnst_i.expr.kind.name == 'InsideExpression'): + continue + # Fix for Issue 37, dist expressions + # do not have left/right + if (lv_cnst_i.expr.kind.name == 'ExpressionOrDist'): + FUNC_CNST_DIST_COL_EQ (lv_cnst_i) + continue + if (lv_cnst_i.expr.left.kind.name == 'InvocationExpression'): + lv_cnst_expr_s = lv_cnst_i.expr.left.__str__() + lv_arr_red_methods = [".sum()", ".sum ()", + ".product()", ".product ()", + ".and()", ".and ()", + ".or()", ".or ()", + ".xor()", ".xor ()"] + if any([x in lv_cnst_expr_s for x in lv_arr_red_methods]): + msg = 'Potentially incorrect constraint expression!' + msg += ' An expression involving the array-reduction methods' + msg += ' sum()/product()/and()/or()/xor()' + msg += ' was found, but is missing an explicit cast.' + msg += ' This can lead to strange results as' + msg += ' array reduction methods return an expression' + msg += ' of the size of' + msg += ' its elements, check if you need a with' + msg += ' (int\'( cast around the following expression:' + msg += lv_cnst_expr_s + lv_rule_id = "FUNC_CNST_MISSING_CAST" + pyslint_msg(lv_rule_id, msg) + +def FUNC_CNST_WRONG_OPER_PRI (lv_cu_scope): + if (lv_cu_scope.kind.name == 'ClassDeclaration'): + for cl_item in (lv_cu_scope.items): + if (cl_item.kind.name == 'ConstraintDeclaration'): + for lv_cnst_i in (cl_item.block.items): + if (not hasattr(lv_cnst_i, 'expr')): + continue + if (not hasattr(lv_cnst_i.expr, 'operatorToken')): + continue + + if (lv_cnst_i.expr.operatorToken.kind.name == 'DoubleAnd' or + lv_cnst_i.expr.operatorToken.kind.name == 'DoubleOr' + ): + lv_cnst_expr_s = lv_cnst_i.expr.__str__() + if ( + lv_cnst_i.expr.left.operatorToken.kind.name == 'DoubleEquals' or + lv_cnst_i.expr.left.operatorToken.kind.name == 'ExclamationEquals' + ): + msg = 'Potentially incorrect constraint expression!' + msg += ' An expression involving operators with different' + msg += ' precedence is observed. As per LRM, Equality' + msg += ' operators have higher precedence than Logical operators' + msg += ' Review and use \'( )\' appropriately' + msg += ' around the constraint expression' + msg += lv_cnst_expr_s + lv_rule_id = "FUNC_CNST_WRONG_OPER_PRI" + pyslint_msg(lv_rule_id, msg) + +def COMPAT_CG_OPT_PI_CL(lv_m): + if (lv_m.kind.name == 'ClassDeclaration'): + for cl_item_i in (lv_m.items): + if (cl_item_i.kind.name == 'CovergroupDeclaration'): + for lv_cg_m_i in cl_item_i.members: + if (lv_cg_m_i.kind.name == 'CoverageOption'): + lv_cg_name = cl_item_i.name.valueText + lv_cg_opt = lv_cg_m_i.expr.left.__str__() + if ('type_option.per_instance' in lv_cg_opt): + msg = 'Found \'type_option.per_instance\' ' + msg += 'inside a covergroup: ' + msg += lv_cg_name + msg += '\nIEEE 1800 LRM does not' + msg += ' allow such usage though some tools do compile. \n' + msg += 'To avoid compatibility issues,' + msg += ' please move the per_instance to' + msg += ' \'option.per_instance \'' + lv_rule_id = "COMPAT_CG_OPT_PI_CL" + pyslint_msg(lv_rule_id, msg) + +def REUSE_CG_NO_ILBINS_CL(lv_m): + if (lv_m.kind.name == 'ClassDeclaration'): + for cl_item_i in (lv_m.items): + if (cl_item_i.kind.name == 'CovergroupDeclaration'): + lv_cg_name = cl_item_i.name.valueText.strip() + for lv_cg_m_i in cl_item_i.members: + if (lv_cg_m_i.kind.name == 'Coverpoint'): + lv_cpt_expr = lv_cg_m_i.expr.__str__() + lv_cpt_label = lv_cg_m_i.label.__str__() + lv_cpt_name = lv_cpt_label + lv_cpt_expr + lv_cpt_name = lv_cpt_name.strip() + for lv_cpt_m_i in lv_cg_m_i.members: + if (lv_cpt_m_i.kind.name == 'CoverageBins'): + lv_cpt_bin_s = lv_cpt_m_i.keyword.__str__() + if ('illegal_bins' in lv_cpt_bin_s): + lv_cpt_bin_name = lv_cpt_m_i.name.valueText + msg = 'Found \'illegal_bins\' under user-defined bins: \n' + msg += 'covergroup: ' + msg += lv_cg_name + msg += ' for coverpoint: ' + msg += lv_cpt_name + ' ' + msg += lv_cpt_bin_name + msg += '\nWhile IEEE 1800 LRM allows this syntax, this ' + msg += 'is bad for REUSE aspect as it does not flag ' + msg += 'as UVM_ERROR or $error. \n' + msg += 'Also if coverage is turned OFF, this error ' + msg += 'is likely to go unflagged. ' + msg += 'Recommended to use \'ignore_bins\' instead \n' + msg += 'from coverage perspective and add SVA or ' + msg += 'scoreboard for illegal values.' + lv_rule_id = "REUSE_CG_NO_ILBINS_CL" + pyslint_msg(lv_rule_id, msg) + +def REUSE_NO_WILDC_AA_CL(lv_m): + if (lv_m.kind.name == 'ClassDeclaration'): + for cl_item_i in (lv_m.items): + if (cl_item_i.kind.name == 'ClassPropertyDeclaration'): + lv_decl_str_s = cl_item_i.__str__() + for lv_decl_i in cl_item_i.declaration.declarators: + if (not hasattr(lv_decl_i, 'dimensions')): + continue + for lv_decl_dim_i in lv_decl_i.dimensions: + if (lv_decl_dim_i.specifier.kind.name == 'WildcardDimensionSpecifier'): + msg = 'Found an associative array declaration with wild-card as key\n' + msg += lv_decl_str_s + msg += '\nThis is bad for reuse as it does not allow \'foreach\' iterator and other handy built-in functions.\n' + msg += 'Consider using a typed key such as int/string etc.' + lv_rule_id = 'REUSE_NO_WILDC_AA_CL' + pyslint_msg(lv_rule_id, msg) + +def PERF_CG_NO_ABIN_W_DEF_CL(lv_m): + if (lv_m.kind.name == 'ClassDeclaration'): + for cl_item_i in (lv_m.items): + if (cl_item_i.kind.name == 'CovergroupDeclaration'): + lv_cg_name = cl_item_i.name.valueText.strip() + for lv_cg_m_i in cl_item_i.members: + if (lv_cg_m_i.kind.name == 'Coverpoint'): + lv_cpt_expr = lv_cg_m_i.expr.__str__() + lv_cpt_label = lv_cg_m_i.label.__str__() + if (lv_cpt_label == 'None'): + lv_cpt_label = '' + lv_cpt_name = lv_cpt_label + lv_cpt_expr + lv_cpt_name = lv_cpt_name.strip() + for lv_cpt_m_i in lv_cg_m_i.members: + if (lv_cpt_m_i.size is None): + continue + if (lv_cpt_m_i.size.kind.name == 'CoverageBinsArraySize'): + if (lv_cpt_m_i.size.expr is None): + lv_arr_bin_rhs_s = lv_cpt_m_i.initializer.__str__().strip() + if (lv_arr_bin_rhs_s == 'default'): + lv_cpt_bin_name = lv_cpt_m_i.name.valueText + msg = 'Found Array-bins: \n' + msg += '\tcovergroup: ' + msg += lv_cg_name + msg += '\n\tcoverpoint: ' + msg += lv_cpt_name + '\n\tBIN: ' + msg += lv_cpt_bin_name + '\n\t' + msg += lv_cpt_m_i.__str__().strip() + msg += '\n\n\tWhile IEEE 1800 LRM allows this syntax, this ' + msg += 'is bad for Performance aspect as it ends up creating' + msg += ' large number of bins. Recommended to remove this bin.' + lv_rule_id = 'PERF_CG_NO_ABIN_W_DEF_CL' + pyslint_msg(lv_rule_id, msg) + +def NAME_CG_PREFIX(lv_m): + if (lv_m.kind.name == 'ClassDeclaration'): + for cl_item_i in (lv_m.items): + if (cl_item_i.kind.name == 'CovergroupDeclaration'): + lv_cg_name = cl_item_i.name.valueText + lv_exp_s = 'cg_' + if (not lv_cg_name.startswith(lv_exp_s)): + msg = 'Improper naming of identifier: ' + msg += lv_cg_name + msg += ': expected prefix: ' + msg += lv_exp_s + lv_rule_id = "NAME_CG_PREFIX" + pyslint_msg(lv_rule_id, msg) + + if (lv_m.kind.name == 'CovergroupDeclaration'): + lv_cg_name = lv_m.name.valueText + lv_exp_s = 'cg_' + if (not lv_cg_name.startswith(lv_exp_s)): + msg = 'Improper naming of identifier: ' + msg += lv_cg_name + msg += ': expected prefix: ' + msg += lv_exp_s + lv_rule_id = 'NAME_CG_PREFIX' + pyslint_msg(lv_rule_id, msg) + +def DBG_SVA_AST_MISSING_LABEL(lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + lv_sva_vdir = lv_m.statement.keyword.valueText + if (lv_sva_vdir != 'assert'): + return + if (lv_m.statement.label is None): + msg = 'Unnamed assertion - use a meaningful label: ' + msg += str(lv_m.statement) + lv_rule_id = 'DBG_SVA_AST_MISSING_LABEL' + pyslint_msg (lv_rule_id, msg) + +def NAME_AST_PREFIX (lv_m): + + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + + lv_sva_vdir = lv_m.statement.keyword.valueText + if (lv_sva_vdir != 'assert'): + return + + if (lv_m.statement.label is None): + return + + lv_label = lv_m.statement.label.name.value + + lv_exp_s = sv_prefix_d['assert'] + if (not lv_label.startswith(lv_exp_s)): + msg = 'Improper naming of assert directive: ' + msg += lv_label + msg += ': expected prefix: ' + msg += lv_exp_s + lv_rule_id = 'NAME_AST_PREFIX' + pyslint_msg (lv_rule_id, msg) + + +def NAME_ASM_PREFIX(lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + if (lv_m.statement.label is None): + msg = 'Unnamed assumption - use a meaningful label: ' + msg += str(lv_m.statement) + lv_rule_id = "SVA_MISSING_LABEL" + pyslint_msg(lv_rule_id, msg) + else: + lv_label = lv_m.statement.label.name.value + lv_sva_vdir = lv_m.statement.keyword.valueText + if (lv_sva_vdir != 'assume'): + return + + lv_exp_s = sv_prefix_d['assume'] + if (not lv_label.startswith(lv_exp_s)): + msg = 'Improper naming of assume directive: ' + msg += lv_label + msg += ': expected prefix: ' + msg += lv_exp_s + lv_rule_id = 'NAME_ASM_PREFIX' + pyslint_msg(lv_rule_id, msg) + +def NAME_COV_PREFIX(lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + if (lv_m.statement.label is None): + msg = 'Unnamed assumption - use a meaningful label: ' + msg += str(lv_m.statement) + lv_rule_id = "SVA_MISSING_LABEL" + pyslint_msg(lv_rule_id, msg) + else: + lv_label = lv_m.statement.label.name.value + lv_sva_vdir = lv_m.statement.keyword.valueText + if (lv_sva_vdir != 'cover'): + return + + lv_exp_s = sv_prefix_d['cover'] + if (not lv_label.startswith(lv_exp_s)): + msg = 'Improper naming of cover directive: ' + msg += lv_label + msg += ': expected prefix: ' + msg += lv_exp_s + lv_rule_id = 'NAME_COV_PREFIX' + pyslint_msg(lv_rule_id, msg) + + +def COMPAT_SVA_NO_DEGEN_AST (lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + + lv_found_rep_val = False + + lv_p_expr = lv_m.statement.propertySpec + lv_p_str = lv_p_expr.__str__() + + if (hasattr(lv_p_expr, 'expr')): + lv_p_expr_r = lv_p_expr.expr + + if (hasattr(lv_p_expr_r, 'right') and + hasattr(lv_p_expr_r.right, 'expr')): + lv_p_expr_r_1 = lv_p_expr_r.right.expr + + if (hasattr(lv_p_expr_r, 'left')): + lv_p_expr_r_1 = lv_p_expr_r.left.expr + #TBD move the below code to a new def + # and make it common for both ANT and CNSQ + + + if (hasattr(lv_p_expr_r_1, 'first')): + lv_p_expr_r_1 = lv_p_expr_r_1.first + + if (hasattr(lv_p_expr_r_1, 'repetition')): + lv_p_expr_r_2 = lv_p_expr_r_1.repetition + + if (hasattr(lv_p_expr_r_2, 'selector')): + lv_p_expr_r_3 = lv_p_expr_r_2.selector + + if (hasattr(lv_p_expr_r_3, 'expr')): + lv_p_expr_r_4 = lv_p_expr_r_3.expr + lv_rep_val = "UNKNOWN" + lv_rep_val = lv_p_expr_r_4.literal.valueText.strip() + lv_found_rep_val = True + + if (hasattr(lv_p_expr_r_3, 'left')): + lv_p_expr_r_4 = lv_p_expr_r_3.left + lv_rep_val = "UNKNOWN" + lv_rep_val = lv_p_expr_r_4.literal.valueText.strip() + lv_found_rep_val = True + + if (hasattr(lv_m, 'propertySpec') and + hasattr(lv_p_expr_r, 'expr')): + lv_p_expr_r = lv_m.propertySpec.expr.expr.expr + if (hasattr(lv_p_expr_r, 'repetition')): + lv_rep_val = lv_m.propertySpec.expr.expr.expr.repetition.selector.expr.literal.valueText.strip() + lv_found_rep_val = True + + + if (hasattr(lv_p_expr, 'right')): + lv_p_expr_r = lv_m.propertySpec.expr.right.expr + if (hasattr(lv_p_expr_r, 'repetition')): + lv_p_expr_r = lv_m.propertySpec.expr.right.expr.repetition + if (hasattr(lv_p_expr_r, 'selector')): + lv_rep_val = lv_m.propertySpec.expr.right.expr.repetition.selector.expr.literal.valueText.strip() + lv_found_rep_val = True + + if (lv_found_rep_val and lv_rep_val == "0"): + msg = 'Empty match ([*0] or variants) found in a property expression. \n' + msg += '\tThough some compilers allow this, IEEE 1800 LRM prevents' + msg += ' such usage, so for maximum compatibility across EDA \n' + msg += '\ttools and LRM compliance, please remove the empty match. \n' + msg += lv_p_str + lu_rule_id = 'COMPAT_SVA_NO_DEGEN_AST' + pyslint_msg (lu_rule_id, msg) + +def COMPAT_SVA_NO_S_UNTIL_WITH (lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + + lv_found_rep_val = False + + lv_p_expr = lv_m.statement.propertySpec + lv_p_str = lv_p_expr.__str__() + + if (hasattr(lv_p_expr, 'expr')): + lv_p_expr_r = lv_p_expr.expr + + if (hasattr(lv_p_expr_r, 'right') and + hasattr(lv_p_expr_r.right, 'op')): + lv_p_expr_r_1 = lv_p_expr_r.right.op + + if (lv_p_expr_r_1.kind.name == 'SUntilWithKeyword'): + + msg = 'Found usage of s_util_with on consequent of a concurrent assertion. \n' + msg += '\tThough LRM supports this, some compilers do NOT support this.' + msg += ' So for maximum compatibility across EDA \n' + msg += '\ttools consider remodeling this SVA. \n' + msg += lv_p_str + lu_rule_id = 'COMPAT_SVA_NO_S_UNTIL_WITH' + pyslint_msg (lu_rule_id, msg) + +def COMPAT_SVA_NO_DEGEN_CONSEQ(lv_m): + if (lv_m.kind.name == 'PropertyDeclaration' or + lv_m.kind.name == 'ConcurrentAssertionMember'): + + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + lv_p_expr = lv_m.statement.propertySpec.expr + else: + lv_p_expr = lv_m.propertySpec.expr + + lv_p_str = lv_p_expr.__str__() + lv_found_rep_val = False + + if (hasattr(lv_p_expr, 'expr')): + lv_p_expr_r = lv_p_expr.expr + if (hasattr(lv_p_expr_r, 'right')): + lv_p_expr_r_1 = lv_p_expr_r.right.expr + if (hasattr(lv_p_expr_r_1, 'repetition')): + lv_p_expr_r_2 = lv_p_expr_r_1.repetition + if (hasattr(lv_p_expr_r_2, 'selector')): + lv_p_expr_r_3 = lv_p_expr_r_2.selector + if (hasattr(lv_p_expr_r_3, 'left')): + lv_p_expr_r_4 = lv_p_expr_r_3.left + lv_rep_val = "UNKNOWN" + lv_rep_val = lv_p_expr_r_4.literal.valueText.strip() + lv_found_rep_val = True + + if (hasattr(lv_p_expr_r, 'expr')): + lv_p_expr_r = lv_p_expr_r.expr + if (hasattr(lv_p_expr_r, 'repetition')): + if (lv_p_expr_r.repetition is not None): + lv_p_expr_r = lv_p_expr_r.repetition + if (hasattr(lv_p_expr_r, 'selector')): + lv_rep_val = lv_p_expr_r.selector.expr.literal.valueText.strip() + lv_found_rep_val = True + + + if (hasattr(lv_p_expr, 'right')): + if (hasattr(lv_p_expr.right, 'expr')): + lv_p_expr_r = lv_p_expr.right.expr + if (hasattr(lv_p_expr_r, 'first')): + lv_p_expr_r = lv_p_expr_r.first + if (hasattr(lv_p_expr_r, 'repetition')): + lv_p_expr_r = lv_p_expr_r.repetition + if (hasattr(lv_p_expr_r, 'selector')): + lv_p_expr_r = lv_p_expr_r.selector + if (hasattr(lv_p_expr_r, 'expr')): + lv_rep_val = lv_p_expr_r.expr.literal.valueText.strip() + lv_found_rep_val = True + + if (lv_found_rep_val and lv_rep_val == "0"): + msg = 'Empty match ([*0] or variants) found in a property expression. \n' + msg += '\tThough some compilers allow this, IEEE 1800 LRM prevents' + msg += ' such usage, so for maximum compatibility across EDA \n' + msg += '\ttools and LRM compliance, please remove the empty match. \n' + msg += lv_p_str + lv_rule_id = 'COMPAT_SVA_NO_DEGEN_CONSEQ' + pyslint_msg(lv_rule_id, msg) + +def NAME_PROP_PREFIX(lv_m): + if (lv_m.kind.name == 'PropertyDeclaration'): + lv_prop_label = lv_m.name.valueText + lv_exp_s = sv_prefix_d['prop'] + if (not lv_prop_label.startswith(lv_exp_s)): + msg = 'Improper naming of property: ' + msg += lv_prop_label + msg += ': expected prefix: ' + msg += lv_exp_s + lv_rule_id = 'NAME_PROP_PREFIX' + pyslint_msg(lv_rule_id, msg) + +def SVA_MISSING_ENDLABEL(lv_m): + if (lv_m.kind.name == 'PropertyDeclaration'): + if (lv_m.endBlockName is None): + lv_prop_label = lv_m.name.valueText + msg = 'Missing End Label for property: ' + msg += lv_prop_label + lv_rule_id = 'SVA_MISSING_ENDLABEL' + pyslint_msg(lv_rule_id, msg) + +def CL_MISSING_ENDLABEL(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ClassDeclaration'): + if (lv_cu_scope.endBlockName is None): + lv_cl_label = lv_cu_scope.name.valueText + msg = 'Missing End Label for class: ' + msg += lv_cl_label + lv_rule_id = 'CL_MISSING_ENDLABEL' + pyslint_msg(lv_rule_id, msg) + +def SVA_NO_PASS_AB(lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + if (lv_m.statement.action.statement is None): + return + if (lv_m.statement.action.statement.kind.name == 'EmptyStatement'): + return + + if (lv_m.statement.action.statement is not None): + msg = 'Avoid using PASS Action block - likely to cause too many vacuous prints: ' + msg += str(lv_m.statement) + lv_rule_id = 'SVA_NO_PASS_AB' + pyslint_msg(lv_rule_id, msg) + +def SVA_MISSING_FAIL_AB(lv_m): + if (lv_m.kind.name == 'ConcurrentAssertionMember'): + if (lv_m.statement.label is None): + return + + lv_label = lv_m.statement.label.name.value + lv_sva_vdir = lv_m.statement.keyword.valueText + + if (lv_sva_vdir != 'assert'): + return + + if (lv_m.statement.action.elseClause is None): + msg = 'Missing FAIL Action block - use $error/`uvm_error: ' + msg += str(lv_m.statement) + lv_rule_id = 'SVA_MISSING_FAIL_AB' + pyslint_msg(lv_rule_id, msg) + +def pyslint_argparse(): + # Create the parser + parser = argparse.ArgumentParser() + # Add an argument + parser.add_argument('-t', '--test', type=str, required=True) + # Parse the argument + args = parser.parse_args() + return args + +def pyslint_update_prefixes(): + lv_sv_prefix_d = {} + lv_sv_prefix_d.update({"prop": "p_"}) + lv_sv_prefix_d.update({"cover": "c_"}) + lv_sv_prefix_d.update({"assert": "a_"}) + lv_sv_prefix_d.update({"assume": "m_"}) + return lv_sv_prefix_d + +def pyslint_update_suffixes(): + lv_sv_suffix_d = {} + lv_sv_suffix_d.update({"intf": "_if"}) + lv_sv_suffix_d.update({"class": "_c"}) + lv_sv_suffix_d.update({"cnst": "_cst"}) + lv_sv_suffix_d.update({"mod": "_m"}) + return lv_sv_suffix_d + +def chk_name_style_prefix(lv_rule_id, lv_name, lv_exp_p): + if (lv_name.startswith(lv_exp_p)): + if (print_verbose): + print('AF: Good naming: ', lv_name) + else: + msg = 'Improper naming of identifier: ' + msg += lv_name + msg += ': expected prefix: ' + msg += lv_exp_p + pyslint_msg(lv_rule_id, msg) + +def chk_name_style_suffix(lv_rule_id, lv_name, lv_exp_s): + if (lv_name.endswith(lv_exp_s)): + if (print_verbose): + print('AF: Good naming: ', lv_name) + else: + msg = 'Improper naming of identifier: ' + msg += lv_name + msg += ': expected suffix: ' + msg += lv_exp_s + pyslint_msg(lv_rule_id, msg) + +def FUNC_NO_2STATE_IN_INTF(lv_intf_scope): + for lv_intf_mem_i in lv_intf_scope.members: + if (lv_intf_mem_i.kind.name == 'DataDeclaration'): + if (lv_intf_mem_i.type.kind.name == 'BitType'): + lv_var_decl = lv_intf_mem_i.declarators.getFirstToken() + lv_name = lv_var_decl.valueText + msg = 'Potential DUT bug hiding construct in use: ' + msg += ' Inside SystemVerilog interface, it is recommended' + msg += ' to use only 4-state signals/nets.' + msg += ' Found a 2-state declaration as: ' + msg += lv_intf_mem_i.__str__() + lv_rule_id = 'FUNC_NO_2STATE_IN_INTF' + pyslint_msg(lv_rule_id, msg) + +def FUNC_DPI_NO_4STATE_IN_RETURN(lv_dpi_mem): + lv_rval_type_s = lv_dpi_mem.method.returnType.keyword.__str__().strip() + lv_rval_4st_types = ["integer", "logic", + "reg"] + if any([x in lv_rval_type_s for x in lv_rval_4st_types]): + msg = 'DPI functions shall use 2-state types in return value.' + msg += ' Using 4-state type can lead to unnecessary complication' + msg += ' as C-side does not naturally support 4-state value system' + msg += ' Found code as: \n' + msg += str(lv_dpi_mem) + lv_rule_id = 'FUNC_DPI_NO_4STATE_IN_RETURN' + pyslint_msg(lv_rule_id, msg) + +def COMPAT_DPI_OLD_SPECSTR(lv_dpi_mem): + lv_spec_str_val_s = lv_dpi_mem.specString.__str__().strip() + if (lv_spec_str_val_s != '\"DPI-C\"'): + msg = 'Wrong Spec-STR in DPI declaration' + msg += ' IEEE 1800-2012 specifies \"DPI-C\" as Spec-STR.' + msg += ' Found code as: \n' + msg += str(lv_dpi_mem) + lv_rule_id = 'COMPAT_DPI_OLD_SPECSTR' + pyslint_msg(lv_rule_id, msg) + +def COMPAT_SVA_NO_CONC_IN_FE(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ModuleDeclaration'): + for lv_mod_mem_i in lv_cu_scope.members: + if (lv_mod_mem_i.kind.name == 'InitialBlock'): + if (not hasattr(lv_mod_mem_i.statement, 'items')): + continue + for lv_init_items_i in lv_mod_mem_i.statement.items: + + if (lv_init_items_i.kind.name == 'ForeverStatement'): + if (not hasattr(lv_init_items_i.statement.statement, 'items')): + continue + for lv_fe_i in lv_init_items_i.statement.statement.items: + lv_code_s = lv_fe_i.__str__() + if (lv_fe_i.kind.name == 'AssertPropertyStatement'): + msg = 'A procedural concurrent assertion was found' + msg += ' inside a forever loop; IEEE 1800 LRM does not' + msg += ' allow such usage though some tools do compile' + msg += ' To avoid compatibility issues,' + msg += ' please remodel the code:' + msg += str(lv_code_s) + lv_rule_id = 'COMPAT_SVA_NO_CONC_IN_FE' + pyslint_msg(lv_rule_id, msg) + +def COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ModuleDeclaration'): + for lv_mod_mem_i in lv_cu_scope.members: + if (lv_mod_mem_i.kind.name == 'InitialBlock'): + if (not hasattr(lv_mod_mem_i.statement, 'items')): + continue + for lv_init_items_i in lv_mod_mem_i.statement.items: + if (lv_init_items_i.kind.name == 'ExpectPropertyStatement'): + if ( + hasattr(lv_init_items_i, 'propertySpec') and + hasattr(lv_init_items_i.propertySpec, 'expr') and + hasattr(lv_init_items_i.propertySpec.expr, 'expr') and + hasattr(lv_init_items_i.propertySpec.expr.expr, 'elements') + ): + lv_code_s = lv_init_items_i.__str__() + msg = 'A procedural \'expect\' construct with temporal' + msg += ' expression was found' + msg += ' inside an initial block; IEEE 1800 LRM does ' + msg += ' allow such usage though some tools do NOT support' + msg += ' To avoid compatibility issues,' + msg += ' please remodel the code:' + msg += str(lv_code_s) + lv_rule_id = 'COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT' + pyslint_msg(lv_rule_id, msg) + + ''' + if (not hasattr(lv_init_items_i.statement.statement, 'items')): + continue + for lv_fe_i in lv_init_items_i.statement.statement.items: + lv_code_s = lv_fe_i.__str__() + if (lv_fe_i.kind.name == 'AssertPropertyStatement'): + ''' + +def REUSE_NO_TDEF_IN_MOD(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ModuleDeclaration'): + for lv_mod_mem_i in lv_cu_scope.members: + if (lv_mod_mem_i.kind.name == 'TypedefDeclaration'): + lv_tdef_s = lv_mod_mem_i.__str__() + msg = 'A typedef was found inside a module' + msg += ' This prevents reuse as the enum/typedef scope is module only' + msg += ' An assertion model that binds to this module' + msg += ' and check the states using the typedef will be harder' + msg += ' to implement in such cases.' + msg += ' Please move the typedef to a package' + msg += ' and import that package inside the module' + msg += str(lv_tdef_s) + lv_rule_id = 'REUSE_NO_TDEF_IN_MOD' + pyslint_msg(lv_rule_id, msg) + +class_count = [] + +def REUSE_ONE_CL_PER_FILE (lv_m): + if (lv_m.kind.name == 'ClassDeclaration'): + for cl_rep in lv_m: + if (cl_rep.kind.name == 'EndClassKeyword'): + class_count.append(cl_rep.kind.name) + continue + elif len(class_count) > 1: + msg = 'Always use one-class definition per file' + lv_rule_id = 'REUSE_ONE_CL_PER_FILE' + pyslint_msg (lv_rule_id, msg) + +mod_count = [] + +def REUSE_ONE_MOD_PER_FILE (lv_m): + if (lv_m.kind.name == 'ModuleDeclaration'): + for mod_rep in lv_m.header: + if (mod_rep.kind.name == 'ModuleKeyword'): + mod_count.append(mod_rep.kind.name) + continue + elif len(mod_count) > 1: + msg = 'Always use one-module definition per file' + lv_rule_id = 'REUSE_ONE_MOD_PER_FILE' + pyslint_msg (lv_rule_id, msg) + break + +def chk_dpi_rules(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ModuleDeclaration'): + for lv_mod_mem_i in lv_cu_scope.members: + if (lv_mod_mem_i.kind.name == 'DPIImport'): + COMPAT_DPI_OLD_SPECSTR (lv_mod_mem_i) + FUNC_DPI_NO_4STATE_IN_RETURN (lv_mod_mem_i) + +def chk_naming(lv_cu_scope): + if (lv_cu_scope.kind.name == 'ClassDeclaration'): + lv_ident_name = str(lv_cu_scope.name) + lv_exp_s = sv_suffix_d['class'] + chk_name_style_suffix ('NAME_CLASS_SUFFIX', lv_ident_name, lv_exp_s) + + if (lv_cu_scope.kind.name == 'InterfaceDeclaration'): + lv_ident_name = str(lv_cu_scope.header.name) + lv_exp_s = sv_suffix_d['intf'] + chk_name_style_suffix ('NAME_INTF_SUFFIX', lv_ident_name, lv_exp_s) + FUNC_NO_2STATE_IN_INTF(lv_cu_scope) + + NAME_CG_PREFIX(lv_cu_scope) + +args = pyslint_argparse() + +sv_prefix_d = pyslint_update_prefixes() +sv_suffix_d = pyslint_update_suffixes() +pyslint_rules_l = pyslint_update_rule_ids() + +inp_test_name = args.test + +tree = pyslang.SyntaxTree.fromFile(inp_test_name) +r = tree.root + +if (tree.root.members.__str__() == ''): + print("PySlint: No modules/interfaces/classes found") + exit(0) + +for scope_i in (tree.root.members): + chk_naming(scope_i) + chk_dpi_rules(scope_i) + + CL_METHOD_NOT_EXTERN(scope_i) + FUNC_CNST_MISSING_CAST(scope_i) + FUNC_CNST_WRONG_OPER_PRI(scope_i) + CL_MISSING_ENDLABEL(scope_i) + REUSE_NO_TDEF_IN_MOD(scope_i) + COMPAT_SVA_NO_CONC_IN_FE(scope_i) + COMPAT_SVA_NO_EXPECT_EXPR_IN_INIT(scope_i) + COMPAT_CG_OPT_PI_CL(scope_i) + REUSE_CG_NO_ILBINS_CL(scope_i) + PERF_CG_NO_ABIN_W_DEF_CL(scope_i) + REUSE_NO_WILDC_AA_CL(scope_i) + REUSE_ONE_CL_PER_FILE(scope_i) + REUSE_ONE_MOD_PER_FILE(scope_i) + +cu_scope = tree.root.members[0] +if (cu_scope.kind.name != 'ClassDeclaration'): + if (hasattr(cu_scope, 'members')): + for m_i in (cu_scope.members): + NAME_AST_PREFIX(m_i) + NAME_ASM_PREFIX(m_i) + NAME_COV_PREFIX(m_i) + SVA_MISSING_FAIL_AB(m_i) + SVA_NO_PASS_AB(m_i) + NAME_PROP_PREFIX(m_i) + COMPAT_SVA_NO_DEGEN_CONSEQ(m_i) + COMPAT_SVA_NO_DEGEN_AST(m_i) + COMPAT_SVA_NO_S_UNTIL_WITH(m_i) + SVA_MISSING_ENDLABEL(m_i) + NAME_CG_PREFIX(m_i) + diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/AxiPC.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/AxiPC.sv new file mode 100644 index 0000000000000000000000000000000000000000..3f1da9a09b816249a20821a17a051e48848cf6eb --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/AxiPC.sv @@ -0,0 +1,4551 @@ +//============================================================================-- +// This confidential and proprietary software may be used only as +// authorised by a licensing agreement from ARM Limited +// (C) COPYRIGHT 2003-2009 ARM Limited +// ALL RIGHTS RESERVED +// The entire notice above must be reproduced on all authorised +// copies and copies may only be made to the extent permitted +// by a licensing agreement from ARM Limited. +// +// +//------------------------------------------------------------------------------ +// Version and Release Control Information: +// +// File Name : AxiPC.sv,v +// File Revision : 66202 +// +// Release Information : BP062-VL-70004-r0p1-00rel0 +// +//------------------------------------------------------------------------------ +// Purpose : This is the AXI Protocol Checker using SVA +// +// Supports bus widths of 32, 64, 128, 256, 512, 1024 bit +// Parameterisable write interleave depth +// Supports a single outstanding exclusive read per ID +//============================================================================-- + +//---------------------------------------------------------------------------- +// CONTENTS +// ======== +// 299. Module: AxiPC +// 366. 1) Parameters +// 370. - Configurable (user can set) +// 424. - Calculated (user should not override) +// 497. 2) Inputs (no outputs) +// 501. - Global Signals +// 507. - Write Address Channel +// 522. - Write Data Channel +// 533. - Write Response Channel +// 542. - Read Address Channel +// 557. - Read Data Channel +// 567. - Low Power Interface +// 575. 3) Wire and Reg Declarations +// 722. 4) Verilog Defines +// 726. - Lock FSM States +// 735. - Clock and Reset +// 768. 5) Initialize simulation +// 773. - Format for time reporting +// 779. - Indicate version and release state of AxiPC +// 784. - Warn if any/some recommended rules are disabled +// 804. - Warn if any/some channel rules are ignored +// 820. +// 821. AXI Rules: Write Address Channel (*_AW*) +// 826. 1) Functional Rules +// 830. - AXI_ERRM_AWADDR_BOUNDARY +// 854. - AXI_ERRM_AWADDR_WRAP_ALIGN +// 866. - AXI_ERRM_AWBURST +// 878. - AXI_ERRM_AWCACHE +// 890. - AXI_ERRM_AWLEN_WRAP +// 905. - AXI_ERRM_AWLOCK +// 917. - AXI_ERRM_AWLOCK_END +// 931. - AXI_ERRM_AWLOCK_ID +// 954. - AXI_ERRM_AWLOCK_LAST +// 970. - AXI_ERRM_AWLOCK_START +// 986. - AXI_ERRM_AWSIZE +// 1000. - AXI_ERRM_AWVALID_RESET +// 1012. - AXI_RECM_AWLOCK_BOUNDARY +// 1037. - AXI_RECM_AWLOCK_CTRL +// 1061. - AXI_RECM_AWLOCK_NUM +// 1084. 2) Handshake Rules +// 1088. - AXI_ERRM_AWADDR_STABLE +// 1101. - AXI_ERRM_AWBURST_STABLE +// 1114. - AXI_ERRM_AWCACHE_STABLE +// 1127. - AXI_ERRM_AWID_STABLE +// 1140. - AXI_ERRM_AWLEN_STABLE +// 1153. - AXI_ERRM_AWLOCK_STABLE +// 1166. - AXI_ERRM_AWPROT_STABLE +// 1179. - AXI_ERRM_AWSIZE_STABLE +// 1192. - AXI_ERRM_AWVALID_STABLE +// 1204. - AXI_RECS_AWREADY_MAX_WAIT +// 1220. 3) X-Propagation Rules +// 1226. - AXI_ERRM_AWADDR_X +// 1237. - AXI_ERRM_AWBURST_X +// 1248. - AXI_ERRM_AWCACHE_X +// 1259. - AXI_ERRM_AWID_X +// 1270. - AXI_ERRM_AWLEN_X +// 1281. - AXI_ERRM_AWLOCK_X +// 1292. - AXI_ERRM_AWPROT_X +// 1303. - AXI_ERRM_AWSIZE_X +// 1314. - AXI_ERRM_AWVALID_X +// 1325. - AXI_ERRS_AWREADY_X +// 1339. +// 1340. AXI Rules: Write Data Channel (*_W*) +// 1345. 1) Functional Rules +// 1349. - AXI_ERRM_WDATA_NUM +// 1364. - AXI_ERRM_WDATA_ORDER +// 1375. - AXI_ERRM_WDEPTH +// 1387. - AXI_ERRM_WSTRB +// 1398. - AXI_ERRM_WVALID_RESET +// 1411. 2) Handshake Rules +// 1415. - AXI_ERRM_WDATA_STABLE +// 1428. - AXI_ERRM_WID_STABLE +// 1441. - AXI_ERRM_WLAST_STABLE +// 1454. - AXI_ERRM_WSTRB_STABLE +// 1467. - AXI_ERRM_WVALID_STABLE +// 1479. - AXI_RECS_WREADY_MAX_WAIT +// 1495. 3) X-Propagation Rules +// 1501. - AXI_ERRM_WDATA_X +// 1512. - AXI_ERRM_WID_X +// 1523. - AXI_ERRM_WLAST_X +// 1534. - AXI_ERRM_WSTRB_X +// 1545. - AXI_ERRM_WVALID_X +// 1556. - AXI_ERRS_WREADY_X +// 1570. +// 1571. AXI Rules: Write Response Channel (*_B*) +// 1576. 1) Functional Rules +// 1580. - AXI_ERRS_BRESP +// 1591. - AXI_ERRS_BRESP_ALL_DONE_EOS +// 1608. - AXI_ERRS_BRESP_EXOKAY +// 1619. - AXI_ERRS_BVALID_RESET +// 1631. - AXI_RECS_BRESP +// 1644. 2) Handshake Rules +// 1648. - AXI_ERRS_BID_STABLE +// 1661. - AXI_ERRS_BRESP_STABLE +// 1674. - AXI_ERRS_BVALID_STABLE +// 1686. - AXI_RECM_BREADY_MAX_WAIT +// 1702. 3) X-Propagation Rules +// 1708. - AXI_ERRM_BREADY_X +// 1719. - AXI_ERRS_BID_X +// 1730. - AXI_ERRS_BRESP_X +// 1741. - AXI_ERRS_BVALID_X +// 1755. +// 1756. AXI Rules: Read Address Channel (*_AR*) +// 1761. 1) Functional Rules +// 1765. - AXI_ERRM_ARADDR_BOUNDARY +// 1789. - AXI_ERRM_ARADDR_WRAP_ALIGN +// 1801. - AXI_ERRM_ARBURST +// 1813. - AXI_ERRM_ARCACHE +// 1825. - AXI_ERRM_ARLEN_WRAP +// 1840. - AXI_ERRM_ARLOCK +// 1852. - AXI_ERRM_ARLOCK_END +// 1866. - AXI_ERRM_ARLOCK_ID +// 1889. - AXI_ERRM_ARLOCK_LAST +// 1904. - AXI_ERRM_ARLOCK_START +// 1920. - AXI_ERRM_ARSIZE +// 1932. - AXI_ERRM_ARVALID_RESET +// 1944. - AXI_RECM_ARLOCK_BOUNDARY +// 1969. - AXI_RECM_ARLOCK_CTRL +// 1993. - AXI_RECM_ARLOCK_NUM +// 2016. 2) Handshake Rules +// 2020. - AXI_ERRM_ARADDR_STABLE +// 2033. - AXI_ERRM_ARBURST_STABLE +// 2046. - AXI_ERRM_ARCACHE_STABLE +// 2059. - AXI_ERRM_ARID_STABLE +// 2072. - AXI_ERRM_ARLEN_STABLE +// 2085. - AXI_ERRM_ARLOCK_STABLE +// 2098. - AXI_ERRM_ARPROT_STABLE +// 2111. - AXI_ERRM_ARSIZE_STABLE +// 2124. - AXI_ERRM_ARVALID_STABLE +// 2136. - AXI_RECS_ARREADY_MAX_WAIT +// 2152. 3) X-Propagation Rules +// 2158. - AXI_ERRM_ARADDR_X +// 2169. - AXI_ERRM_ARBURST_X +// 2180. - AXI_ERRM_ARCACHE_X +// 2191. - AXI_ERRM_ARID_X +// 2202. - AXI_ERRM_ARLEN_X +// 2213. - AXI_ERRM_ARLOCK_X +// 2224. - AXI_ERRM_ARPROT_X +// 2235. - AXI_ERRM_ARSIZE_X +// 2246. - AXI_ERRM_ARVALID_X +// 2257. - AXI_ERRS_ARREADY_X +// 2271. +// 2272. AXI Rules: Read Data Channel (*_R*) +// 2277. 1) Functional Rules +// 2281. - AXI_ERRS_RDATA_NUM +// 2295. - AXI_ERRS_RLAST_ALL_DONE_EOS +// 2312. - AXI_ERRS_RID +// 2325. - AXI_ERRS_RRESP_EXOKAY +// 2337. - AXI_ERRS_RVALID_RESET +// 2350. 2) Handshake Rules +// 2354. - AXI_ERRS_RDATA_STABLE +// 2369. - AXI_ERRS_RID_STABLE +// 2382. - AXI_ERRS_RLAST_STABLE +// 2395. - AXI_ERRS_RRESP_STABLE +// 2408. - AXI_ERRS_RVALID_STABLE +// 2420. - AXI_RECM_RREADY_MAX_WAIT +// 2436. 3) X-Propagation Rules +// 2442. - AXI_ERRS_RDATA_X +// 2453. - AXI_ERRM_RREADY_X +// 2464. - AXI_ERRS_RID_X +// 2475. - AXI_ERRS_RLAST_X +// 2486. - AXI_ERRS_RRESP_X +// 2497. - AXI_ERRS_RVALID_X +// 2511. +// 2512. AXI Rules: Low Power Interface (*_C*) +// 2517. 1) Functional Rules (none for Low Power signals) +// 2522. 2) Handshake Rules (asynchronous to ACLK) +// 2529. - AXI_ERRL_CSYSACK_FALL +// 2540. - AXI_ERRL_CSYSACK_RISE +// 2551. - AXI_ERRL_CSYSREQ_FALL +// 2562. - AXI_ERRL_CSYSREQ_RISE +// 2574. 3) X-Propagation Rules +// 2580. - AXI_ERRL_CACTIVE_X +// 2591. - AXI_ERRL_CSYSACK_X +// 2602. - AXI_ERRL_CSYSREQ_X +// 2616. +// 2617. AXI Rules: Exclusive Access +// 2625. 1) Functional Rules +// 2627. - +// 2630. - AXI_ERRM_EXCL_ALIGN +// 2651. - AXI_ERRM_EXCL_LEN +// 2669. - AXI_RECM_EXCL_MATCH +// 2692. - AXI_ERRM_EXCL_MAX +// 2713. - AXI_RECM_EXCL_PAIR +// 2730. +// 2731. AXI Rules: USER_* Rules (extension to AXI) +// 2739. 1) Functional Rules (none for USER signals) +// 2744. 2) Handshake Rules +// 2748. - AXI_ERRM_AWUSER_STABLE +// 2761. - AXI_ERRM_WUSER_STABLE +// 2774. - AXI_ERRS_BUSER_STABLE +// 2787. - AXI_ERRM_ARUSER_STABLE +// 2800. - AXI_ERRS_RUSER_STABLE +// 2814. 3) X-Propagation Rules +// 2820. - AXI_ERRM_AWUSER_X +// 2831. - AXI_ERRM_WUSER_X +// 2842. - AXI_ERRS_BUSER_X +// 2853. - AXI_ERRM_ARUSER_X +// 2864. - AXI_ERRS_RUSER_X +// 2878. +// 2879. Auxiliary Logic +// 2884. 1) Rules for Auxiliary Logic +// 2889. a) Master (AUXM*) +// 2893. - AXI_AUXM_DATA_WIDTH +// 2908. - AXI_AUXM_ADDR_WIDTH +// 2918. - AXI_AUXM_AWUSER_WIDTH +// 2928. - AXI_AUXM_WUSER_WIDTH +// 2938. - AXI_AUXM_BUSER_WIDTH +// 2948. - AXI_AUXM_ARUSER_WIDTH +// 2958. - AXI_AUXM_RUSER_WIDTH +// 2968. - AXI_AUXM_ID_WIDTH +// 2978. - AXI_AUXM_EXMON_WIDTH +// 2988. - AXI_AUXM_WDEPTH +// 2998. - AXI_AUXM_MAXRBURSTS +// 3008. - AXI_AUXM_MAXWBURSTS +// 3018. - AXI_AUXM_RCAM_OVERFLOW +// 3029. - AXI_AUXM_RCAM_UNDERFLOW +// 3040. - AXI_AUXM_WCAM_OVERFLOW +// 3051. - AXI_AUXM_WCAM_UNDERFLOW +// 3062. - AXI_AUXM_EXCL_OVERFLOW +// 3074. 2) Combinatorial Logic +// 3079. a) Masks +// 3083. - AlignMaskR +// 3105. - AlignMaskW +// 3127. - ExclMask +// 3135. - WdataMask +// 3148. - RdataMask +// 3154. b) Increments +// 3158. - ArAddrIncr +// 3166. - AwAddrIncr +// 3175. c) Conversions +// 3179. - ArLenInBytes +// 3187. - ArSizeInBits +// 3195. - AwSizeInBits +// 3204. d) Other +// 3208. - ArExclPending +// 3214. - ArLenPending +// 3219. - ArCountPending +// 3226. 3) EXCL & LOCK Accesses +// 3230. - Exclusive Access ID Lookup +// 3356. - Exclusive Access Storage +// 3411. - Lock State Machine +// 3452. - Lock State Register +// 3475. - Lock Property Logic +// 3585. 4) Content addressable memories (CAMs) +// 3589. - Read CAMSs (CAM+Shift) +// 3729. - Write CAMs (CAM+Shift) +// 4113. - Write Depth array +// 4207. 5) Verilog Functions +// 4211. - CheckBurst +// 4310. - CheckStrb +// 4348. - ReadDataMask +// 4368. - ByteShift +// 4463. - ByteCount +// 4510. +// 4511. End of File +// 4516. 1) Clear Verilog Defines +// 4538. 2) End of module +//---------------------------------------------------------------------------- + +`timescale 1ns/1ns + +//------------------------------------------------------------------------------ +// AXI Standard Defines +//------------------------------------------------------------------------------ +`include "Axi.v" + + +//------------------------------------------------------------------------------ +// INDEX: Module: AxiPC +//------------------------------------------------------------------------------ +module AxiPC + ( + // Global Signals + ACLK, + ARESETn, + + // Write Address Channel + AWID, + AWADDR, + AWLEN, + AWSIZE, + AWBURST, + AWLOCK, + AWCACHE, + AWPROT, + AWUSER, + AWVALID, + AWREADY, + + // Write Channel + WID, + WLAST, + WDATA, + WSTRB, + WUSER, + WVALID, + WREADY, + + // Write Response Channel + BID, + BRESP, + BUSER, + BVALID, + BREADY, + + // Read Address Channel + ARID, + ARADDR, + ARLEN, + ARSIZE, + ARBURST, + ARLOCK, + ARCACHE, + ARPROT, + ARUSER, + ARVALID, + ARREADY, + + // Read Channel + RID, + RLAST, + RDATA, + RRESP, + RUSER, + RVALID, + RREADY, + + // Low power interface + CACTIVE, + CSYSREQ, + CSYSACK + ); + + +//------------------------------------------------------------------------------ +// INDEX: 1) Parameters +//------------------------------------------------------------------------------ + + + // INDEX: - Configurable (user can set) + // ===== + // Parameters below can be set by the user. + + // Set DATA_WIDTH to the data-bus width required + parameter DATA_WIDTH = 64; // data bus width, default = 64-bit + + // Select the number of channel ID bits required + parameter ID_WIDTH = 4; // (A|W|R|B)ID width + + // Select the size of the USER buses, default = 32-bit + parameter AWUSER_WIDTH = 32; // width of the user AW sideband field + parameter WUSER_WIDTH = 32; // width of the user W sideband field + parameter BUSER_WIDTH = 32; // width of the user B sideband field + parameter ARUSER_WIDTH = 32; // width of the user AR sideband field + parameter RUSER_WIDTH = 32; // width of the user R sideband field + + // Write-interleave Depth of monitored slave interface + parameter WDEPTH = 1; + + // Size of CAMs for storing outstanding read bursts, this should match or + // exceed the number of outstanding read addresses accepted into the slave + // interface + parameter MAXRBURSTS = 16; + + // Size of CAMs for storing outstanding write bursts, this should match or + // exceed the number of outstanding write bursts into the slave interface + parameter MAXWBURSTS = 16; + + // Maximum number of cycles between VALID -> READY high before a warning is + // generated + parameter MAXWAITS = 16; + + // OVL instances property_type parameter (0=assert, 1=assume, 2=ignore) + parameter AXI_ERRM_PropertyType = 0; // default: assert Master is AXI compliant + parameter AXI_RECM_PropertyType = 0; // default: assert Master is AXI compliant + parameter AXI_AUXM_PropertyType = 0; // default: assert Master auxiliary logic checks + // + parameter AXI_ERRS_PropertyType = 0; // default: assert Slave is AXI compliant + parameter AXI_RECS_PropertyType = 0; // default: assert Slave is AXI compliant + parameter AXI_AUXS_PropertyType = 0; // default: assert Slave auxiliary logic checks + // + parameter AXI_ERRL_PropertyType = 0; // default: assert LP Int is AXI compliant + + // Recommended Rules Enable + parameter RecommendOn = 1'b1; // enable/disable reporting of all AXI_REC*_* rules + parameter RecMaxWaitOn = 1'b1; // enable/disable reporting of just AXI_REC*_MAX_WAIT rules + + // Set ADDR_WIDTH to the address-bus width required + parameter ADDR_WIDTH = 32; // address bus width, default = 32-bit + + // Set EXMON_WIDTH to the exclusive access monitor width required + parameter EXMON_WIDTH = 4; // exclusive access width, default = 4-bit + + // INDEX: - Calculated (user should not override) + // ===== + // Do not override the following parameters: they must be calculated exactly + // as shown below + parameter DATA_MAX = DATA_WIDTH-1; // data max index + parameter ADDR_MAX = ADDR_WIDTH-1; // address max index + parameter STRB_WIDTH = DATA_WIDTH/8; // WSTRB width + parameter STRB_MAX = STRB_WIDTH-1; // WSTRB max index + parameter STRB_1 = {{STRB_MAX{1'b0}}, 1'b1}; // value 1 in strobe width + parameter ID_MAX = ID_WIDTH-1; // ID max index + parameter EXMON_MAX = EXMON_WIDTH-1; // EXMON max index + parameter EXMON_HI = {EXMON_WIDTH{1'b1}}; // EXMON max value + + parameter AWUSER_MAX = AWUSER_WIDTH-1; // AWUSER max index + parameter WUSER_MAX = WUSER_WIDTH-1; // WUSER max index + parameter BUSER_MAX = BUSER_WIDTH-1; // BUSER max index + parameter ARUSER_MAX = ARUSER_WIDTH-1; // ARUSER max index + parameter RUSER_MAX = RUSER_WIDTH-1; // RUSER max index + + // FLAGLL/LO/UN WSTRB16...WSTRB1 ID BURST ASIZE ALEN LOCKED EXCL LAST ADDR[6:0] + parameter ADDRLO = 0; // ADDRLO = 0 + parameter ADDRHI = 6; // ADDRHI = 6 + parameter EXCL = ADDRHI + 1; // Transaction is exclusive + parameter LOCKED = EXCL + 1; // Transaction is locked + parameter ALENLO = LOCKED + 1; // ALENLO = 9 + parameter ALENHI = ALENLO + 3; // ALENHI = 12 + parameter ASIZELO = ALENHI + 1; // ASIZELO = 13 + parameter ASIZEHI = ASIZELO + 2; // ASIZEHI = 15 + parameter BURSTLO = ASIZEHI + 1; // BURSTLO = 16 + parameter BURSTHI = BURSTLO + 1; // BURSTHI = 17 + parameter IDLO = BURSTHI + 1; // IDLO = 18 + parameter IDHI = IDLO+ID_MAX; // IDHI = 21 if ID_WIDTH=4 + parameter STRB1LO = IDHI+1; // STRB1LO = 22 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB1HI = STRB1LO+STRB_MAX; // STRB1HI = 29 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB2LO = STRB1HI+1; // STRB2LO = 30 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB2HI = STRB2LO+STRB_MAX; // STRB2HI = 37 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB3LO = STRB2HI+1; // STRB3LO = 38 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB3HI = STRB3LO+STRB_MAX; // STRB3HI = 45 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB4LO = STRB3HI+1; // STRB4LO = 46 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB4HI = STRB4LO+STRB_MAX; // STRB4HI = 53 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB5LO = STRB4HI+1; // STRB5LO = 54 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB5HI = STRB5LO+STRB_MAX; // STRB5HI = 61 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB6LO = STRB5HI+1; // STRB6LO = 62 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB6HI = STRB6LO+STRB_MAX; // STRB6HI = 69 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB7LO = STRB6HI+1; // STRB7LO = 70 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB7HI = STRB7LO+STRB_MAX; // STRB7HI = 77 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB8LO = STRB7HI+1; // STRB8LO = 78 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB8HI = STRB8LO+STRB_MAX; // STRB8HI = 85 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB9LO = STRB8HI+1; // STRB9LO = 86 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB9HI = STRB9LO+STRB_MAX; // STRB9HI = 93 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB10LO = STRB9HI+1; // STRB10LO = 94 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB10HI = STRB10LO+STRB_MAX; // STRB10HI = 101 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB11LO = STRB10HI+1; // STRB11LO = 102 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB11HI = STRB11LO+STRB_MAX; // STRB11HI = 109 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB12LO = STRB11HI+1; // STRB12LO = 110 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB12HI = STRB12LO+STRB_MAX; // STRB12HI = 117 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB13LO = STRB12HI+1; // STRB13LO = 118 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB13HI = STRB13LO+STRB_MAX; // STRB13HI = 125 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB14LO = STRB13HI+1; // STRB14LO = 126 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB14HI = STRB14LO+STRB_MAX; // STRB14HI = 133 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB15LO = STRB14HI+1; // STRB15LO = 134 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB15HI = STRB15LO+STRB_MAX; // STRB15HI = 141 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB16LO = STRB15HI+1; // STRB16LO = 142 if ID_WIDTH=4 & STRB_MAX=7 + parameter STRB16HI = STRB16LO+STRB_MAX; // STRB16HI = 149 if ID_WIDTH=4 & STRB_MAX=7 + parameter FLAGUN = STRB16HI+1; // Seen coincident with unlocked transactions + parameter FLAGLO = FLAGUN+1; // Seen coincident with locked transactions + parameter FLAGLL = FLAGLO+1; // Seen coincident with lock last transaction + + parameter WBURSTMAX = FLAGLL; // Write burst register array maximum + parameter RBURSTMAX = IDHI; // Read burst register array maximum + + +//------------------------------------------------------------------------------ +// INDEX: 2) Inputs (no outputs) +//------------------------------------------------------------------------------ + + + // INDEX: - Global Signals + // ===== + input ACLK; // AXI Clock + input ARESETn; // AXI Reset + + + // INDEX: - Write Address Channel + // ===== + input [ID_MAX:0] AWID; + input [ADDR_MAX:0] AWADDR; + input [3:0] AWLEN; + input [2:0] AWSIZE; + input [1:0] AWBURST; + input [3:0] AWCACHE; + input [2:0] AWPROT; + input [1:0] AWLOCK; + input [AWUSER_MAX:0] AWUSER; + input AWVALID; + input AWREADY; + + + // INDEX: - Write Data Channel + // ===== + input [ID_MAX:0] WID; + input [DATA_MAX:0] WDATA; + input [STRB_MAX:0] WSTRB; + input [WUSER_MAX:0] WUSER; + input WLAST; + input WVALID; + input WREADY; + + + // INDEX: - Write Response Channel + // ===== + input [ID_MAX:0] BID; + input [1:0] BRESP; + input [BUSER_MAX:0] BUSER; + input BVALID; + input BREADY; + + + // INDEX: - Read Address Channel + // ===== + input [ID_MAX:0] ARID; + input [ADDR_MAX:0] ARADDR; + input [3:0] ARLEN; + input [2:0] ARSIZE; + input [1:0] ARBURST; + input [3:0] ARCACHE; + input [2:0] ARPROT; + input [1:0] ARLOCK; + input [ARUSER_MAX:0] ARUSER; + input ARVALID; + input ARREADY; + + + // INDEX: - Read Data Channel + // ===== + input [ID_MAX:0] RID; + input [DATA_MAX:0] RDATA; + input [1:0] RRESP; + input [RUSER_MAX:0] RUSER; + input RLAST; + input RVALID; + input RREADY; + + // INDEX: - Low Power Interface + // ===== + input CACTIVE; + input CSYSREQ; + input CSYSACK; + + +//------------------------------------------------------------------------------ +// INDEX: 3) Wire and Reg Declarations +//------------------------------------------------------------------------------ + + // User signal definitions are defined as weak pull-down in the case + // that they are unconnected. + tri0 [AWUSER_MAX:0] AWUSER; + tri0 [WUSER_MAX:0] WUSER; + tri0 [BUSER_MAX:0] BUSER; + tri0 [ARUSER_MAX:0] ARUSER; + tri0 [RUSER_MAX:0] RUSER; + + // Low power interface signals are defined as weak pull-up in the case + // that they are unconnected. + tri1 CACTIVE; + tri1 CSYSREQ; + tri1 CSYSACK; + + // Write CAMs + integer WIndex; + reg [WBURSTMAX:0] WBurstCam[1:MAXWBURSTS]; // store outstanding write bursts + reg [4:0] WCountCam[1:MAXWBURSTS]; // number of write data stored + reg WLastCam[1:MAXWBURSTS]; // WLAST for outstanding writes + reg WAddrCam[1:MAXWBURSTS]; // flag for valid write addr + reg BRespCam[1:MAXWBURSTS]; // flag for valid write resp + reg nWAddrTrans; // flag for an empty WAddrCam + reg UnlockedInWCam; // At least one unlocked read in WBurstCam + reg LockedInWCam; // At least one locked read in WBurstCam + reg FlagUNInWCam; // At least one write transaction has FLAGUN set + reg FlagLOInWCam; // At least one write transaction has FLAGLO set + reg FlagLLInWCam; // At least one write transaction has FLAGLL set + + // WDepth array + reg [ID_MAX:0] WdepthId[WDEPTH:0]; // Write ID lookup table + reg [WDEPTH:0] WdepthIdValid; // Write ID lookup table entry valid + reg WdepthIdDelta; // Write ID lookup table has changed + wire WdepthIdFull; // Write ID lookup table is full + reg [15:0] WdepthIdFreePtr; // Write ID lookup table next free entry + wire [15:0] WdepthIdWrPtr; // Write ID lookup table write pointer + reg WdepthWMatch; // Write ID lookup table WID match found + reg [15:0] WdepthWId; // Write ID lookup table matching WID reference + integer WidDepth; // Number of write data IDs currently in use + + // Read CAMs + reg [RBURSTMAX:0] RBurstCam[1:MAXRBURSTS]; + reg [4:0] RCountCam[1:MAXRBURSTS]; + integer RIndex; + integer RIndexNext; + wire RPop; + wire RPush; + wire nROutstanding; // flag for an empty RBurstCam + reg RIdCamDelta; // flag indicates that RidCam has changed + reg UnlockedInRCam; // flag for unlocked reads in RBurstCam + reg LockedInRCam; // flag for locked reads in RBurstCam + + // Protocol error flags + wire WriteDataNumError; // flag for AXI_ERRM_WDATA_NUM rule + reg AWDataNumError; // flag to derive WriteDataNumError + reg WDataNumError; // flag to derive WriteDataNumError + reg WDataOrderError; // flag for AXI_ERRM_WDATA_ORDER rule + reg BrespError; // flag for AXI_ERRS_BRESP rule + reg BrespExokError; // flag for AXI_ERRS_BRESP_EXOKAY rule + wire StrbError; // flag for AXI_ERRM_WSTRB rule + reg AWStrbError; // flag to derive StrbError + reg BStrbError; // flag to derive StrbError + + // Protocol recommendation flags + reg BrespLeadingRec; // flag for AXI_RECS_BRESP rule + + // signals for checking for match in ID CAMs + integer AidMatch; + integer WidMatch; + integer RidMatch; + integer BidMatch; + + reg [6:0] AlignMaskR; // mask for checking read address alignment + reg [6:0] AlignMaskW; // mask for checking write address alignment + + // signals for Address Checking + reg [ADDR_MAX:0] ArAddrIncr; + reg [ADDR_MAX:0] AwAddrIncr; + + // signals for Data Checking + wire [DATA_MAX:0] RdataMask; + reg [DATA_MAX:0] WdataMask; + reg [10:0] ArSizeInBits; + reg [10:0] AwSizeInBits; + reg [11:0] ArLenInBytes; + wire [4:0] ArLenPending; + wire [4:0] ArCountPending; + wire ArExclPending; + + // Lock signals + wire AWLockNew; // Initial locking write address valid for a locked sequence + wire ARLockNew; // Initial locking read address valid for a locked sequence + wire AWLockLastNew; // Unlocking write address valid for a locked sequence + wire ARLockLastNew; // Unlocking read address valid for a locked sequence + wire LockedRead; // At least one locked read on the bus + wire UnlockedRead; // At least one unlocked read on the bus + wire LockedWrite; // At least one locked write on the bus + wire UnlockedWrite; // At least one unlocked write on the bus + reg PrevAWVALID; // Prev cycle had AWVALID=1 + reg PrevAWREADY; // Prev cycle had AWREADY=1 + reg PrevARVALID; // Prev cycle had ARVALID=1 + reg PrevARREADY; // Prev cycle had ARREADY=1 + wire AWNew; // New valid write address in current cycle + wire ARNew; // New valid read address in current cycle + reg [1:0] LockState; + reg [1:0] LockStateNext; + reg [ID_MAX:0] LockIdNext; + reg [ID_MAX:0] LockId; + reg [3:0] LockCacheNext; + reg [3:0] LockCache; + reg [2:0] LockProtNext; + reg [2:0] LockProt; + reg [ADDR_MAX:0] LockAddrNext; + reg [ADDR_MAX:0] LockAddr; + + // arrays to store exclusive access control info + reg [ID_MAX:0] ExclId[EXMON_HI:0]; + reg ExclIdDelta; + reg [EXMON_HI:0] ExclIdValid; + wire ExclIdFull; + wire ExclIdOverflow; + reg [EXMON_MAX:0] ExclIdFreePtr; + wire [EXMON_MAX:0] ExclIdWrPtr; + reg [EXMON_MAX:0] ExclAwId; + reg ExclAwMatch; + reg [EXMON_MAX:0] ExclArId; + reg ExclArMatch; + reg [EXMON_MAX:0] ExclRId; + reg ExclRMatch; + reg ExclReadAddr[EXMON_HI:0]; // tracks excl read addr + reg ExclReadData[EXMON_HI:0]; // tracks excl read data + reg [ADDR_MAX:0] ExclAddr[EXMON_HI:0]; + reg [2:0] ExclSize[EXMON_HI:0]; + reg [3:0] ExclLen[EXMON_HI:0]; + reg [1:0] ExclBurst[EXMON_HI:0]; + reg [3:0] ExclCache[EXMON_HI:0]; + reg [2:0] ExclProt[EXMON_HI:0]; + reg [AWUSER_MAX:0] ExclUser[EXMON_HI:0]; + reg [10:0] ExclMask; // mask to check alignment of exclusive address + + // Signals to avoid feeding parameters directly into assertions as this can + // stop assertions triggering in some cases + reg i_RecommendOn; + reg i_RecMaxWaitOn; + + +//------------------------------------------------------------------------------ +// INDEX: 4) Verilog Defines +//------------------------------------------------------------------------------ + + + // INDEX: - Lock FSM States + // ===== + // Lock FSM States (3-state FSM, so one state encoding is not used) + `define AXI_AUX_ST_UNLOCKED 2'b00 + `define AXI_AUX_ST_LOCKED 2'b01 + `define AXI_AUX_ST_LOCK_LAST 2'b10 + `define AXI_AUX_ST_NOT_USED 2'b11 + + + // INDEX: - Clock and Reset + // ===== + // Can be overridden by user for a clock enable. + // + // Can also be used to clock SVA on negedge (to avoid race hazards with + // auxiliary logic) by compiling with the override: + // + // +define+AXI_SVA_CLK=~ACLK + // + // SVA: Assertions + `ifdef AXI_SVA_CLK + `else + `define AXI_SVA_CLK ACLK + `endif + // + `ifdef AXI_SVA_RSTn + `else + `define AXI_SVA_RSTn ARESETn + `endif + // + // AUX: Auxiliary Logic + `ifdef AXI_AUX_CLK + `else + `define AXI_AUX_CLK ACLK + `endif + // + `ifdef AXI_AUX_RSTn + `else + `define AXI_AUX_RSTn ARESETn + `endif + + +//------------------------------------------------------------------------------ +// INDEX: 5) Initialize simulation +//------------------------------------------------------------------------------ + initial + begin + + // INDEX: - Format for time reporting + // ===== + // Format for time reporting + $timeformat(-9, 0, " ns", 0); + + + // INDEX: - Indicate version and release state of AxiPC + // ===== + $display("AXI_INFO: Running AxiPC version BP062-BU-01000-r0p1-00rel0"); + + + // INDEX: - Warn if any/some recommended rules are disabled + // ===== + if (~RecommendOn) + // All AXI_REC*_* rules disabled + $display("AXI_WARN: All recommended AXI rules have been disabled by the RecommendOn parameter"); + else if (~RecMaxWaitOn) + // Just AXI_REC*_MAX_WAIT rules disabled + $display("AXI_WARN: Five recommended MAX_WAIT rules have been disabled by the RecMaxWaitOn parameter"); + + if (RecommendOn) + i_RecommendOn = 1'b1; + else + i_RecommendOn = 1'b0; + + if (RecMaxWaitOn) + i_RecMaxWaitOn = 1'b1; + else + i_RecMaxWaitOn = 1'b0; + + + // INDEX: - Warn if any/some channel rules are ignored + // ===== + if (AXI_ERRM_PropertyType > 0) $display("AXI_WARN: The AXI_ERRM_PropertyType parameter is currently not used by the SVA version"); + if (AXI_RECM_PropertyType > 0) $display("AXI_WARN: The AXI_RECM_PropertyType parameter is currently not used by the SVA version"); + if (AXI_AUXM_PropertyType > 0) $display("AXI_WARN: The AXI_AUXM_PropertyType parameter is currently not used by the SVA version"); + // + if (AXI_ERRS_PropertyType > 0) $display("AXI_WARN: The AXI_ERRS_PropertyType parameter is currently not used by the SVA version"); + if (AXI_RECS_PropertyType > 0) $display("AXI_WARN: The AXI_RECS_PropertyType parameter is currently not used by the SVA version"); + if (AXI_AUXS_PropertyType > 0) $display("AXI_WARN: The AXI_AUXS_PropertyType parameter is currently not used by the SVA version"); + // + if (AXI_ERRL_PropertyType > 0) $display("AXI_WARN: The AXI_ERRL_PropertyType parameter is currently not used by the SVA version"); + + end + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Write Address Channel (*_AW*) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_AWADDR_BOUNDARY + // ===== + // 4kbyte boundary: only bottom twelve bits (11 to 0) can change + // + // Only need to check INCR bursts since: + // + // a) FIXED bursts cannot violate the 4kB boundary by definition + // + // b) WRAP bursts always stay within a <4kB region because of the wrap + // address boundary. The biggest WRAP burst possible has length 16, + // size 128 bytes (1024 bits), so it can transfer 2048 bytes. The + // individual transfer addresses wrap at a 2048 byte address boundary, + // and the max data transferred in also 2048 bytes, so a 4kB boundary + // can never be broken. + property AXI_ERRM_AWADDR_BOUNDARY; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWBURST,AWADDR})) & + AWVALID & (AWBURST == `AXI_ABURST_INCR) + |-> (AwAddrIncr[ADDR_MAX:12] == AWADDR[ADDR_MAX:12]); + endproperty + axi_errm_awaddr_boundary: assert property (AXI_ERRM_AWADDR_BOUNDARY) else + $error("AXI_ERRM_AWADDR_BOUNDARY. A write burst cannot cross a 4kbyte boundary. Spec: section 4.1 on page 4-2."); + + + // INDEX: - AXI_ERRM_AWADDR_WRAP_ALIGN + // ===== + property AXI_ERRM_AWADDR_WRAP_ALIGN; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWBURST,AWADDR})) & + AWVALID & (AWBURST == `AXI_ABURST_WRAP) + |-> ((AWADDR[6:0] & AlignMaskW) == AWADDR[6:0]); + endproperty + axi_errm_awaddr_wrap_align: assert property (AXI_ERRM_AWADDR_WRAP_ALIGN) else + $error("AXI_ERRM_AWADDR_WRAP_ALIGN. A write transaction with burst type WRAP must have an aligned address. Spec: section 4.4.3 on page 4-6."); + + + // INDEX: - AXI_ERRM_AWBURST + // ===== + property AXI_ERRM_AWBURST; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWBURST})) & + AWVALID + |-> (AWBURST != 2'b11); + endproperty + axi_errm_awburst: assert property (AXI_ERRM_AWBURST) else + $error("AXI_ERRM_AWBURST. When AWVALID is high, a value of 2'b11 on AWBURST is not permitted. Spec: table 4-3 on page 4-5."); + + + // INDEX: - AXI_ERRM_AWCACHE + // ===== + property AXI_ERRM_AWCACHE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWCACHE})) & + AWVALID & ~AWCACHE[1] + |-> (AWCACHE[3:2] == 2'b00); + endproperty + axi_errm_awcache: assert property (AXI_ERRM_AWCACHE) else + $error("AXI_ERRM_AWCACHE. When AWVALID is high, if AWCACHE[1] is low then AWCACHE[3] and AWCACHE[2] must also be low. Spec: table 5-1 on page 5-3."); + + + // INDEX: - AXI_ERRM_AWLEN_WRAP + // ===== + property AXI_ERRM_AWLEN_WRAP; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWBURST,AWLEN})) & + AWVALID & (AWBURST == `AXI_ABURST_WRAP) + |-> (AWLEN == `AXI_ALEN_2 || + AWLEN == `AXI_ALEN_4 || + AWLEN == `AXI_ALEN_8 || + AWLEN == `AXI_ALEN_16); + endproperty + axi_errm_awlen_wrap: assert property (AXI_ERRM_AWLEN_WRAP) else + $error("AXI_ERRM_AWLEN_WRAP. A write transaction with burst type WRAP must have length 2, 4, 8 or 16. Spec: section 4.4.3 on page 4-6."); + + + // INDEX: - AXI_ERRM_AWLOCK + // ===== + property AXI_ERRM_AWLOCK; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWLOCK})) & + AWVALID + |-> (AWLOCK != 2'b11); + endproperty + axi_errm_awlock: assert property (AXI_ERRM_AWLOCK) else + $error("AXI_ERRM_AWLOCK. When AWVALID is high, a value of 2'b11 on AWLOCK is not permitted. Spec: table 6-1 on page 6-2."); + + + // INDEX: - AXI_ERRM_AWLOCK_END + // ===== + property AXI_ERRM_AWLOCK_END; + @(posedge `AXI_SVA_CLK) + (LockState == `AXI_AUX_ST_LOCK_LAST) & // the unlocking transfer has begun and should have completed + AWNew // new valid write address + |-> nROutstanding & // no outstanding reads + nWAddrTrans & // no writes other than leading write data (checked separately) + !FlagLLInWCam; // no leading write transactions from previous lock last period + endproperty + axi_errm_awlock_end: assert property (AXI_ERRM_AWLOCK_END) else + $error("AXI_ERRM_AWLOCK_END. A master must wait for an unlocked transaction at the end of a locked sequence to complete before issuing another write transaction. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_AWLOCK_ID + // ===== + property AXI_ERRM_AWLOCK_ID; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWID,AWLOCK, + ARID,ARLOCK})) + |-> + // case for in lock or going into lock last + !(AWNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid write address in a locked sequence + (AWID != LockId) // id value does not match current lock id + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) && // in unlocked or lock last state + (AWID != ARID) // lock id values do not agree + ); + endproperty + axi_errm_awlock_id: assert property (AXI_ERRM_AWLOCK_ID) else + $error("AXI_ERRM_AWLOCK_ID. A sequence of locked transactions must use a single ID. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_AWLOCK_LAST + // ===== + property AXI_ERRM_AWLOCK_LAST; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID})) & + AWLockLastNew // going into lock last with a locked write + |-> nROutstanding & // no outstanding reads + nWAddrTrans & // no writes other than leading write data (checked separately) + (WIndex <= 2) & // at most there can only be one leading write transaction + ~ARVALID & // no read activity + !FlagLOInWCam; // no leading write transactions from previous locked period + endproperty + axi_errm_awlock_last: assert property (AXI_ERRM_AWLOCK_LAST) else + $error("AXI_ERRM_AWLOCK_LAST. A master must wait for all locked transactions to complete before issuing an unlocking write transaction. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_AWLOCK_START + // ===== + property AXI_ERRM_AWLOCK_START; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARLOCK})) & + AWLockNew // going into locked with a locked write + |-> nROutstanding & // no outstanding reads + nWAddrTrans & // no writes other than leading write data (checked separately) + !(ARVALID & (ARLOCK != `AXI_ALOCK_LOCKED)) & // allow a new read but only if it is locked + !FlagUNInWCam & // no leading write transactions from previous unlocked period + !FlagLLInWCam; // no leading write transactions from previous lock last period + endproperty + axi_errm_awlock_start: assert property (AXI_ERRM_AWLOCK_START) else + $error("AXI_ERRM_AWLOCK_START. A master must wait for all outstanding transactions to complete before issuing a write transaction which is the first in a locked sequence. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_AWSIZE + // ===== + // Deliberately keeping AwSizeInBits logic outside of assertion, to + // simplify formal-proofs flow. + property AXI_ERRM_AWSIZE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWSIZE})) & + AWVALID + |-> (AwSizeInBits <= DATA_WIDTH); + endproperty + axi_errm_awsize: assert property (AXI_ERRM_AWSIZE) else + $error("AXI_ERRM_AWSIZE. The size of a write transfer must not exceed the width of the data port. Spec: section 4.3 on page 4-4."); + + + // INDEX: - AXI_ERRM_AWVALID_RESET + // ===== + property AXI_ERRM_AWVALID_RESET; + @(posedge `AXI_SVA_CLK) + !(`AXI_SVA_RSTn) & !($isunknown(`AXI_SVA_RSTn)) + ##1 `AXI_SVA_RSTn + |-> !AWVALID; + endproperty + axi_errm_awvalid_reset: assert property (AXI_ERRM_AWVALID_RESET) else + $error("AXI_ERRM_AWVALID_RESET. AWVALID must be low in the cycle when ARESETn first goes high. Spec: section 11.1.2 on page 11-2."); + + + // INDEX: - AXI_RECM_AWLOCK_BOUNDARY + // ===== + // 4kbyte boundary: only bottom twelve bits (11 to 0) can change + property AXI_RECM_AWLOCK_BOUNDARY; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWADDR,AWLOCK, + ARADDR,ARLOCK})) & + i_RecommendOn // Parameter that can disable all AXI_REC*_* rules + |-> + // case for in lock or going into lock last + !(AWNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid write address in a locked sequence + (AWADDR[ADDR_MAX:12] != LockAddr[ADDR_MAX:12]) // address does not match current lock region + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) && // in unlocked or lock last state + (AWADDR[ADDR_MAX:12] != ARADDR[ADDR_MAX:12]) // lock address region values do not agree + ); + endproperty + axi_recm_awlock_boundary: assert property (AXI_RECM_AWLOCK_BOUNDARY) else + $warning("AXI_RECM_AWLOCK_BOUNDARY. It is recommended that all locked transaction sequences are kept within the same 4KB address region. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_RECM_AWLOCK_CTRL + // ===== + property AXI_RECM_AWLOCK_CTRL; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWPROT,AWCACHE,AWLOCK, + ARPROT,ARCACHE,ARLOCK})) & + i_RecommendOn // Parameter that can disable all AXI_REC*_* rules + |-> + // case for in lock or going into lock last + !(AWNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid write address in a locked sequence + ((AWPROT != LockProt) || (AWCACHE != LockCache)) // PROT or CACHE values do not match current lock + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) && // in unlocked or lock last state + ((AWPROT != ARPROT) || (AWCACHE != ARCACHE)) // lock PROT or CACHE values do not agree + ); + endproperty + axi_recm_awlock_ctrl: assert property (AXI_RECM_AWLOCK_CTRL) else + $warning("AXI_RECM_AWLOCK_CTRL. It is recommended that a master should not change AxPROT or AxCACHE during a sequence of locked accesses. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_RECM_AWLOCK_NUM + // ===== + property AXI_RECM_AWLOCK_NUM; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWLOCK,ARLOCK})) & + i_RecommendOn // Parameter that can disable all AXI_REC*_* rules + |-> + // case for in lock or going into lock last + !(AWNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid write address in a locked sequence + (AWLOCK == `AXI_ALOCK_LOCKED) // write is locked + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) // in unlocked or lock last state + ); + endproperty + axi_recm_awlock_num: assert property (AXI_RECM_AWLOCK_NUM) else + $warning("AXI_RECM_AWLOCK_NUM. It is recommended that locked transaction sequences are limited to two transactions. Spec: section 6.3 on page 6-7."); + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_AWADDR_STABLE + // ===== + property AXI_ERRM_AWADDR_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWADDR})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWADDR); + endproperty + axi_errm_awaddr_stable: assert property (AXI_ERRM_AWADDR_STABLE) else + $error("AXI_ERRM_AWADDR_STABLE. AWADDR must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWBURST_STABLE + // ===== + property AXI_ERRM_AWBURST_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWBURST})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWBURST); + endproperty + axi_errm_awburst_stable: assert property (AXI_ERRM_AWBURST_STABLE) else + $error("AXI_ERRM_AWBURST_STABLE. AWBURST must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWCACHE_STABLE + // ===== + property AXI_ERRM_AWCACHE_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWCACHE})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWCACHE); + endproperty + axi_errm_awcache_stable: assert property (AXI_ERRM_AWCACHE_STABLE) else + $error("AXI_ERRM_AWCACHE_STABLE. AWCACHE must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWID_STABLE + // ===== + property AXI_ERRM_AWID_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWID})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWID); + endproperty + axi_errm_awid_stable: assert property (AXI_ERRM_AWID_STABLE) else + $error("AXI_ERRM_AWID_STABLE. AWID must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWLEN_STABLE + // ===== + property AXI_ERRM_AWLEN_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWLEN})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWLEN); + endproperty + axi_errm_awlen_stable: assert property (AXI_ERRM_AWLEN_STABLE) else + $error("AXI_ERRM_AWLEN_STABLE. AWLEN must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWLOCK_STABLE + // ===== + property AXI_ERRM_AWLOCK_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWLOCK})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWLOCK); + endproperty + axi_errm_awlock_stable: assert property (AXI_ERRM_AWLOCK_STABLE) else + $error("AXI_ERRM_AWLOCK_STABLE. AWLOCK must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWPROT_STABLE + // ===== + property AXI_ERRM_AWPROT_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWPROT})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWPROT); + endproperty + axi_errm_awprot_stable: assert property (AXI_ERRM_AWPROT_STABLE) else + $error("AXI_ERRM_AWPROT_STABLE. AWPROT must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWSIZE_STABLE + // ===== + property AXI_ERRM_AWSIZE_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWSIZE})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWSIZE); + endproperty + axi_errm_awsize_stable: assert property (AXI_ERRM_AWSIZE_STABLE) else + $error("AXI_ERRM_AWSIZE_STABLE. AWSIZE must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_AWVALID_STABLE + // ===== + property AXI_ERRM_AWVALID_STABLE; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID & !AWREADY & !($isunknown({AWVALID,AWREADY})) + ##1 `AXI_SVA_RSTn + |-> AWVALID; + endproperty + axi_errm_awvalid_stable: assert property (AXI_ERRM_AWVALID_STABLE) else + $error("AXI_ERRM_AWVALID_STABLE. Once AWVALID is asserted, it must remain asserted until AWREADY is high. Spec: section 3.1.1 on page 3-2."); + + + // INDEX: - AXI_RECS_AWREADY_MAX_WAIT + // ===== + // Note: this rule does not error if VALID goes low (breaking VALID_STABLE rule) + property AXI_RECS_AWREADY_MAX_WAIT; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown({AWVALID,AWREADY})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + i_RecMaxWaitOn & // Parameter that can disable just AXI_REC*_MAX_WAIT rules + ( AWVALID & !AWREADY) + |-> ##[1:MAXWAITS] (!AWVALID | AWREADY); // READY=1 within MAXWAITS cycles (or VALID=0) + endproperty + axi_recs_awready_max_wait: assert property (AXI_RECS_AWREADY_MAX_WAIT) else + $warning("AXI_RECS_AWREADY_MAX_WAIT. AWREADY should be asserted within MAXWAITS cycles of AWVALID being asserted."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRM_AWADDR_X + // ===== + property AXI_ERRM_AWADDR_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWADDR); + endproperty + axi_errm_awaddr_x: assert property (AXI_ERRM_AWADDR_X) else + $error("AXI_ERRM_AWADDR_X. When AWVALID is high, a value of X on AWADDR is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWBURST_X + // ===== + property AXI_ERRM_AWBURST_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWBURST); + endproperty + axi_errm_awburst_x: assert property (AXI_ERRM_AWBURST_X) else + $error("AXI_ERRM_AWBURST_X. When AWVALID is high, a value of X on AWBURST is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWCACHE_X + // ===== + property AXI_ERRM_AWCACHE_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWCACHE); + endproperty + axi_errm_awcache_x: assert property (AXI_ERRM_AWCACHE_X) else + $error("AXI_ERRM_AWCACHE_X. When AWVALID is high, a value of X on AWCACHE is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWID_X + // ===== + property AXI_ERRM_AWID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWID); + endproperty + axi_errm_awid_x: assert property (AXI_ERRM_AWID_X) else + $error("AXI_ERRM_AWID_X. When AWVALID is high, a value of X on AWID is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWLEN_X + // ===== + property AXI_ERRM_AWLEN_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWLEN); + endproperty + axi_errm_awlen_x: assert property (AXI_ERRM_AWLEN_X) else + $error("AXI_ERRM_AWLEN_X. When AWVALID is high, a value of X on AWLEN is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWLOCK_X + // ===== + property AXI_ERRM_AWLOCK_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWLOCK); + endproperty + axi_errm_awlock_x: assert property (AXI_ERRM_AWLOCK_X) else + $error("AXI_ERRM_AWLOCK_X. When AWVALID is high, a value of X on AWLOCK is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWPROT_X + // ===== + property AXI_ERRM_AWPROT_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWPROT); + endproperty + axi_errm_awprot_x: assert property (AXI_ERRM_AWPROT_X) else + $error("AXI_ERRM_AWPROT_X. When AWVALID is high, a value of X on AWPROT is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWSIZE_X + // ===== + property AXI_ERRM_AWSIZE_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWSIZE); + endproperty + axi_errm_awsize_x: assert property (AXI_ERRM_AWSIZE_X) else + $error("AXI_ERRM_AWSIZE_X. When AWVALID is high, a value of X on AWSIZE is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_AWVALID_X + // ===== + property AXI_ERRM_AWVALID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(AWVALID); + endproperty + axi_errm_awvalid_x: assert property (AXI_ERRM_AWVALID_X) else + $error("AXI_ERRM_AWVALID_X. When not in reset, a value of X on AWVALID is not permitted."); + + + // INDEX: - AXI_ERRS_AWREADY_X + // ===== + property AXI_ERRS_AWREADY_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(AWREADY); + endproperty + axi_errs_awready_x: assert property (AXI_ERRS_AWREADY_X) else + $error("AXI_ERRS_AWREADY_X. When not in reset, a value of X on AWREADY is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Write Data Channel (*_W*) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_WDATA_NUM + // ===== + // This will fire in one of the following situations: + // 1) Write data arrives and WLAST set and WDATA count is not equal to AWLEN + // 2) Write data arrives and WLAST not set and WDATA count is equal to AWLEN + // 3) ADDR arrives, WLAST already received and WDATA count not equal to AWLEN + property AXI_ERRM_WDATA_NUM; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(WriteDataNumError)) + |-> ~WriteDataNumError; + endproperty + axi_errm_wdata_num: assert property (AXI_ERRM_WDATA_NUM) else + $error("AXI_ERRM_WDATA_NUM. The number of write data items must match AWLEN for the corresponding address. Spec: table 4-1 on page 4-3."); + + + // INDEX: - AXI_ERRM_WDATA_ORDER + // ===== + property AXI_ERRM_WDATA_ORDER; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(WDataOrderError)) + |-> ~WDataOrderError; + endproperty + axi_errm_wdata_order: assert property (AXI_ERRM_WDATA_ORDER) else + $error("AXI_ERRM_WDATA_ORDER. The order in which addresses and the first write data item are produced must match. Spec: section 8.5 on page 8-6."); + + + // INDEX: - AXI_ERRM_WDEPTH + // ===== + property AXI_ERRM_WDEPTH; + @(posedge `AXI_SVA_CLK) + !($isunknown({WVALID,WREADY,WidDepth})) & + WVALID & WREADY + |-> (WidDepth <= WDEPTH); + endproperty + axi_errm_wdepth: assert property (AXI_ERRM_WDEPTH) else + $error("AXI_ERRM_WDEPTH. A master can interleave a maximum of WDEPTH write data bursts. Spec: section 8.5 on page 8-6."); + + + // INDEX: - AXI_ERRM_WSTRB + // ===== + property AXI_ERRM_WSTRB; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(StrbError)) + |-> ~StrbError; + endproperty + axi_errm_wstrb: assert property (AXI_ERRM_WSTRB) else + $error("AXI_ERRM_WSTRB. Write strobes must only be asserted for the correct byte lanes as determined from start address, transfer size and beat number. Spec: section 9.2 on page 9-3."); + + + // INDEX: - AXI_ERRM_WVALID_RESET + // ===== + property AXI_ERRM_WVALID_RESET; + @(posedge `AXI_SVA_CLK) + !(`AXI_SVA_RSTn) & !($isunknown(`AXI_SVA_RSTn)) + ##1 `AXI_SVA_RSTn + |-> !WVALID; + endproperty + axi_errm_wvalid_reset: assert property (AXI_ERRM_WVALID_RESET) else + $error("AXI_ERRM_WVALID_RESET. WVALID must be low in the cycle when ARESETn first goes high. Spec: section 11.1.2 on page 11-2."); + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_WDATA_STABLE + // ===== + property AXI_ERRM_WDATA_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({WVALID,WREADY,WDATA})) & + `AXI_SVA_RSTn & WVALID & !WREADY + ##1 `AXI_SVA_RSTn + |-> $stable(WDATA & WdataMask); + endproperty + axi_errm_wdata_stable: assert property (AXI_ERRM_WDATA_STABLE) else + $error("AXI_ERRM_WDATA_STABLE. WDATA must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_WID_STABLE + // ===== + property AXI_ERRM_WID_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({WVALID,WREADY,WID})) & + `AXI_SVA_RSTn & WVALID & !WREADY + ##1 `AXI_SVA_RSTn + |-> $stable(WID); + endproperty + axi_errm_wid_stable: assert property (AXI_ERRM_WID_STABLE) else + $error("AXI_ERRM_WID_STABLE. WID must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_WLAST_STABLE + // ===== + property AXI_ERRM_WLAST_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({WVALID,WREADY,WLAST})) & + `AXI_SVA_RSTn & WVALID & !WREADY + ##1 `AXI_SVA_RSTn + |-> $stable(WLAST); + endproperty + axi_errm_wlast_stable: assert property (AXI_ERRM_WLAST_STABLE) else + $error("AXI_ERRM_WLAST_STABLE. WLAST must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_WSTRB_STABLE + // ===== + property AXI_ERRM_WSTRB_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({WVALID,WREADY,WSTRB})) & + `AXI_SVA_RSTn & WVALID & !WREADY + ##1 `AXI_SVA_RSTn + |-> $stable(WSTRB); + endproperty + axi_errm_wstrb_stable: assert property (AXI_ERRM_WSTRB_STABLE) else + $error("AXI_ERRM_WSTRB_STABLE. WSTRB must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_WVALID_STABLE + // ===== + property AXI_ERRM_WVALID_STABLE; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & WVALID & !WREADY & !($isunknown({WVALID,WREADY})) + ##1 `AXI_SVA_RSTn + |-> WVALID; + endproperty + axi_errm_wvalid_stable: assert property (AXI_ERRM_WVALID_STABLE) else + $error("AXI_ERRM_WVALID_STABLE. Once WVALID is asserted, it must remain asserted until WREADY is high. Spec: section 3.1.2 on page 3-4."); + + + // INDEX: - AXI_RECS_WREADY_MAX_WAIT + // ===== + // Note: this rule does not error if VALID goes low (breaking VALID_STABLE rule) + property AXI_RECS_WREADY_MAX_WAIT; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown({WVALID,WREADY})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + i_RecMaxWaitOn & // Parameter that can disable just AXI_REC*_MAX_WAIT rules + ( WVALID & !WREADY) + |-> ##[1:MAXWAITS] (!WVALID | WREADY); // READY=1 within MAXWAITS cycles (or VALID=0) + endproperty + axi_recs_wready_max_wait: assert property (AXI_RECS_WREADY_MAX_WAIT) else + $warning("AXI_RECS_WREADY_MAX_WAIT. WREADY should be asserted within MAXWAITS cycles of WVALID being asserted."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRM_WDATA_X + // ===== + property AXI_ERRM_WDATA_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & WVALID & !($isunknown(WdataMask)) + |-> ! $isunknown(WDATA & WdataMask); + endproperty + axi_errm_wdata_x: assert property (AXI_ERRM_WDATA_X) else + $error("AXI_ERRM_WDATA_X. When WVALID is high, a value of X on active byte lanes of WDATA is not permitted."); + + + // INDEX: - AXI_ERRM_WID_X + // ===== + property AXI_ERRM_WID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & WVALID + |-> ! $isunknown(WID); + endproperty + axi_errm_wid_x: assert property (AXI_ERRM_WID_X) else + $error("AXI_ERRM_WID_X. When WVALID is high, a value of X on WID is not permitted. Spec: section 3.1.2 on page 3-4."); + + + // INDEX: - AXI_ERRM_WLAST_X + // ===== + property AXI_ERRM_WLAST_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & WVALID + |-> ! $isunknown(WLAST); + endproperty + axi_errm_wlast_x: assert property (AXI_ERRM_WLAST_X) else + $error("AXI_ERRM_WLAST_X. When WVALID is high, a value of X on WLAST is not permitted."); + + + // INDEX: - AXI_ERRM_WSTRB_X + // ===== + property AXI_ERRM_WSTRB_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & WVALID + |-> ! $isunknown(WSTRB); + endproperty + axi_errm_wstrb_x: assert property (AXI_ERRM_WSTRB_X) else + $error("AXI_ERRM_WSTRB_X. When WVALID is high, a value of X on WSTRB is not permitted."); + + + // INDEX: - AXI_ERRM_WVALID_X + // ===== + property AXI_ERRM_WVALID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(WVALID); + endproperty + axi_errm_wvalid_x: assert property (AXI_ERRM_WVALID_X) else + $error("AXI_ERRM_WVALID_X. When not in reset, a value of X on WVALID is not permitted."); + + + // INDEX: - AXI_ERRS_WREADY_X + // ===== + property AXI_ERRS_WREADY_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(WREADY); + endproperty + axi_errs_wready_x: assert property (AXI_ERRS_WREADY_X) else + $error("AXI_ERRS_WREADY_X. When not in reset, a value of X on WREADY is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Write Response Channel (*_B*) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRS_BRESP + // ===== + property AXI_ERRS_BRESP; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(BrespError)) + |-> ~BrespError; + endproperty + axi_errs_bresp: assert property (AXI_ERRS_BRESP) else + $error("AXI_ERRS_BRESP. A slave must only give a write response after the last write data item is transferred. Spec: section 3.3 on page 3-7, and figure 3-5 on page 3-8."); + + + // INDEX: - AXI_ERRS_BRESP_ALL_DONE_EOS + // ===== + // EOS: End-Of-Simulation check (not suitable for formal proofs). + // Use +define+AXI_END_OF_SIMULATION=tb.EOS_signal when compiling. +`ifdef AXI_END_OF_SIMULATION + property AXI_ERRS_BRESP_ALL_DONE_EOS; + @(posedge `AXI_SVA_CLK) + !($isunknown(`AXI_END_OF_SIMULATION)) & + `AXI_SVA_RSTn + ##1 `AXI_SVA_RSTn & $rose(`AXI_END_OF_SIMULATION) + |-> (WIndex == 1); + endproperty + axi_errs_bresp_all_done_eos: assert property (AXI_ERRS_BRESP_ALL_DONE_EOS) else + $error("AXI_ERRS_BRESP_ALL_DONE_EOS. All write transaction addresses must have been matched with corresponding write response."); +`endif + + + // INDEX: - AXI_ERRS_BRESP_EXOKAY + // ===== + property AXI_ERRS_BRESP_EXOKAY; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(BrespExokError)) + |-> ~BrespExokError; + endproperty + axi_errs_bresp_exokay: assert property (AXI_ERRS_BRESP_EXOKAY) else + $error("AXI_ERRS_BRESP_EXOKAY. An EXOKAY write response can only be given to an exclusive write access. Spec: section 6.2.3 on page 6-4."); + + + // INDEX: - AXI_ERRS_BVALID_RESET + // ===== + property AXI_ERRS_BVALID_RESET; + @(posedge `AXI_SVA_CLK) + !(`AXI_SVA_RSTn) & !($isunknown(`AXI_SVA_RSTn)) + ##1 `AXI_SVA_RSTn + |-> !BVALID; + endproperty + axi_errs_bvalid_reset: assert property (AXI_ERRS_BVALID_RESET) else + $error("AXI_ERRS_BVALID_RESET. BVALID must be low in the cycle when ARESETn first goes high. Spec: section 11.1.2 on page 11-2."); + + + // INDEX: - AXI_RECS_BRESP + // ===== + property AXI_RECS_BRESP; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(BrespLeadingRec)) & + i_RecommendOn + |-> ~BrespLeadingRec; + endproperty + axi_recs_bresp: assert property (AXI_RECS_BRESP) else + $error("AXI_RECS_BRESP. A slave should not give a write response before the write address. ARM FAQs: 11424"); + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRS_BID_STABLE + // ===== + property AXI_ERRS_BID_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({BVALID,BREADY,BID})) & + `AXI_SVA_RSTn & BVALID & !BREADY + ##1 `AXI_SVA_RSTn + |-> $stable(BID); + endproperty + axi_errs_bid_stable: assert property (AXI_ERRS_BID_STABLE) else + $error("AXI_ERRS_BID_STABLE. BID must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_BRESP_STABLE + // ===== + property AXI_ERRS_BRESP_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({BVALID,BREADY,BRESP})) & + `AXI_SVA_RSTn & BVALID & !BREADY + ##1 `AXI_SVA_RSTn + |-> $stable(BRESP); + endproperty + axi_errs_bresp_stable: assert property (AXI_ERRS_BRESP_STABLE) else + $error("AXI_ERRS_BRESP_STABLE. BRESP must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_BVALID_STABLE + // ===== + property AXI_ERRS_BVALID_STABLE; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & BVALID & !BREADY & !($isunknown({BVALID,BREADY})) + ##1 `AXI_SVA_RSTn + |-> BVALID; + endproperty + axi_errs_bvalid_stable: assert property (AXI_ERRS_BVALID_STABLE) else + $error("AXI_ERRS_BVALID_STABLE. Once BVALID is asserted, it must remain asserted until BREADY is high. Spec: section 3.1.3 on page 3-4."); + + + // INDEX: - AXI_RECM_BREADY_MAX_WAIT + // ===== + // Note: this rule does not error if VALID goes low (breaking VALID_STABLE rule) + property AXI_RECM_BREADY_MAX_WAIT; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown({BVALID,BREADY})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + i_RecMaxWaitOn & // Parameter that can disable just AXI_REC*_MAX_WAIT rules + ( BVALID & !BREADY) + |-> ##[1:MAXWAITS] (!BVALID | BREADY); // READY=1 within MAXWAITS cycles (or VALID=0) + endproperty + axi_recm_bready_max_wait: assert property (AXI_RECM_BREADY_MAX_WAIT) else + $warning("AXI_RECM_BREADY_MAX_WAIT. BREADY should be asserted within MAXWAITS cycles of BVALID being asserted."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRM_BREADY_X + // ===== + property AXI_ERRM_BREADY_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(BREADY); + endproperty + axi_errm_bready_x: assert property (AXI_ERRM_BREADY_X) else + $error("AXI_ERRM_BREADY_X. When not in reset, a value of X on BREADY is not permitted."); + + + // INDEX: - AXI_ERRS_BID_X + // ===== + property AXI_ERRS_BID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & BVALID + |-> ! $isunknown(BID); + endproperty + axi_errs_bid_x: assert property (AXI_ERRS_BID_X) else + $error("AXI_ERRS_BID_X. When BVALID is high, a value of X on BID is not permitted."); + + + // INDEX: - AXI_ERRS_BRESP_X + // ===== + property AXI_ERRS_BRESP_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & BVALID + |-> ! $isunknown(BRESP); + endproperty + axi_errs_bresp_x: assert property (AXI_ERRS_BRESP_X) else + $error("AXI_ERRS_BRESP_X. When BVALID is high, a value of X on BRESP is not permitted. Spec: section 3.1.3 on page 3-4."); + + + // INDEX: - AXI_ERRS_BVALID_X + // ===== + property AXI_ERRS_BVALID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(BVALID); + endproperty + axi_errs_bvalid_x: assert property (AXI_ERRS_BVALID_X) else + $error("AXI_ERRS_BVALID_X. When not in reset, a value of X on BVALID is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Read Address Channel (*_AR*) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_ARADDR_BOUNDARY + // ===== + // 4kbyte boundary: only bottom twelve bits (11 to 0) can change + // + // Only need to check INCR bursts since: + // + // a) FIXED bursts cannot violate the 4kB boundary by definition + // + // b) WRAP bursts always stay within a <4kB region because of the wrap + // address boundary. The biggest WRAP burst possible has length 16, + // size 128 bytes (1024 bits), so it can transfer 2048 bytes. The + // individual transfer addresses wrap at a 2048 byte address boundary, + // and the max data transferred in also 2048 bytes, so a 4kB boundary + // can never be broken. + property AXI_ERRM_ARADDR_BOUNDARY; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARBURST,ARADDR})) & + ARVALID & (ARBURST == `AXI_ABURST_INCR) + |-> (ArAddrIncr[ADDR_MAX:12] == ARADDR[ADDR_MAX:12]); + endproperty + axi_errm_araddr_boundary: assert property (AXI_ERRM_ARADDR_BOUNDARY) else + $error("AXI_ERRM_ARADDR_BOUNDARY. A read burst cannot cross a 4kbyte boundary. Spec: section 4.1 on page 4-2."); + + + // INDEX: - AXI_ERRM_ARADDR_WRAP_ALIGN + // ===== + property AXI_ERRM_ARADDR_WRAP_ALIGN; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARBURST,ARADDR})) & + ARVALID & (ARBURST == `AXI_ABURST_WRAP) + |-> ((ARADDR[6:0] & AlignMaskR) == ARADDR[6:0]); + endproperty + axi_errm_araddr_wrap_align: assert property (AXI_ERRM_ARADDR_WRAP_ALIGN) else + $error("AXI_ERRM_ARADDR_WRAP_ALIGN. A read transaction with burst type WRAP must have an aligned address. Spec: section 4.4.3 on page 4-6."); + + + // INDEX: - AXI_ERRM_ARBURST + // ===== + property AXI_ERRM_ARBURST; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARBURST})) & + ARVALID + |-> (ARBURST != 2'b11); + endproperty + axi_errm_arburst: assert property (AXI_ERRM_ARBURST) else + $error("AXI_ERRM_ARBURST. When ARVALID is high, a value of 2'b11 on ARBURST is not permitted. Spec: table 4-3 on page 4-5."); + + + // INDEX: - AXI_ERRM_ARCACHE + // ===== + property AXI_ERRM_ARCACHE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARCACHE})) & + ARVALID & ~ARCACHE[1] + |-> (ARCACHE[3:2] == 2'b00); + endproperty + axi_errm_arcache: assert property (AXI_ERRM_ARCACHE) else + $error("AXI_ERRM_ARCACHE. When ARVALID is high, if ARCACHE[1] is low then ARCACHE[3] and ARCACHE[2] must also be low. Spec: table 5-1 on page 5-3."); + + + // INDEX: - AXI_ERRM_ARLEN_WRAP + // ===== + property AXI_ERRM_ARLEN_WRAP; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARBURST,ARLEN})) & + ARVALID & (ARBURST == `AXI_ABURST_WRAP) + |-> (ARLEN == `AXI_ALEN_2 || + ARLEN == `AXI_ALEN_4 || + ARLEN == `AXI_ALEN_8 || + ARLEN == `AXI_ALEN_16); + endproperty + axi_errm_arlen_wrap: assert property (AXI_ERRM_ARLEN_WRAP) else + $error("AXI_ERRM_ARLEN_WRAP. A read transaction with burst type WRAP must have length 2, 4, 8 or 16. Spec: section 4.4.3 on page 4-6."); + + + // INDEX: - AXI_ERRM_ARLOCK + // ===== + property AXI_ERRM_ARLOCK; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARLOCK})) & + ARVALID + |-> (ARLOCK != 2'b11); + endproperty + axi_errm_arlock: assert property (AXI_ERRM_ARLOCK) else + $error("AXI_ERRM_ARLOCK. When ARVALID is high, a value of 2'b11 on ARLOCK is not permitted. Spec: table 6-1 on page 6-2."); + + + // INDEX: - AXI_ERRM_ARLOCK_END + // ===== + property AXI_ERRM_ARLOCK_END; + @(posedge `AXI_SVA_CLK) + (LockState == `AXI_AUX_ST_LOCK_LAST) & // the unlocking transfer has begun and should have completed + ARNew // new valid read address + |-> nROutstanding & // no outstanding reads + nWAddrTrans & // no writes other than leading write data (checked separately) + !FlagLLInWCam; // no leading write transactions from previous lock last period + endproperty + axi_errm_arlock_end: assert property (AXI_ERRM_ARLOCK_END) else + $error("AXI_ERRM_ARLOCK_END. A master must wait for an unlocked transaction at the end of a locked sequence to complete before issuing another read transaction. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_ARLOCK_ID + // ===== + property AXI_ERRM_ARLOCK_ID; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWID,AWLOCK, + ARID,ARLOCK})) + |-> + // case for in lock or going into lock last + !(ARNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid read address in a locked sequence + (ARID != LockId) // id value does not match current lock id + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) && // in unlocked or lock last state + (AWID != ARID) // lock id values do not agree + ); + endproperty + axi_errm_arlock_id: assert property (AXI_ERRM_ARLOCK_ID) else + $error("AXI_ERRM_ARLOCK_ID. A sequence of locked transactions must use a single ID. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_ARLOCK_LAST + // ===== + property AXI_ERRM_ARLOCK_LAST; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,WVALID})) & + ARLockLastNew // going into lock last with a locked read + |-> nROutstanding & // no outstanding reads + (WIndex == 1) & // no writes (including leading write data) + ~AWVALID & ~WVALID & // no activity on write channels + !FlagLOInWCam; // no leading write transactions from previous locked period + endproperty + axi_errm_arlock_last: assert property (AXI_ERRM_ARLOCK_LAST) else + $error("AXI_ERRM_ARLOCK_LAST. A master must wait for all locked transactions to complete before issuing an unlocking read transaction. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_ARLOCK_START + // ===== + property AXI_ERRM_ARLOCK_START; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWLOCK})) & + ARLockNew // going into locked with a locked read + |-> nROutstanding & // no outstanding reads + nWAddrTrans & // no writes other than leading write data (checked separately) + !(AWVALID & (AWLOCK != `AXI_ALOCK_LOCKED)) & // allow a new write but only if it is locked + !FlagUNInWCam & // no leading write transactions from previous unlocked period + !FlagLLInWCam; // no leading write transactions from previous lock last period + endproperty + axi_errm_arlock_start: assert property (AXI_ERRM_ARLOCK_START) else + $error("AXI_ERRM_ARLOCK_START. A master must wait for all outstanding transactions to complete before issuing a read transaction which is the first in a locked sequence. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_ERRM_ARSIZE + // ===== + property AXI_ERRM_ARSIZE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARSIZE})) & + ARVALID + |-> (ArSizeInBits <= DATA_WIDTH); + endproperty + axi_errm_arsize: assert property (AXI_ERRM_ARSIZE) else + $error("AXI_ERRM_ARSIZE. The size of a read transfer must not exceed the width of the data port. Spec: section 4.3 on page 4-4."); + + + // INDEX: - AXI_ERRM_ARVALID_RESET + // ===== + property AXI_ERRM_ARVALID_RESET; + @(posedge `AXI_SVA_CLK) + !(`AXI_SVA_RSTn) & !($isunknown(`AXI_SVA_RSTn)) + ##1 `AXI_SVA_RSTn + |-> !ARVALID; + endproperty + axi_errm_arvalid_reset: assert property (AXI_ERRM_ARVALID_RESET) else + $error("AXI_ERRM_ARVALID_RESET. ARVALID must be low in the cycle when ARESETn first goes high. Spec: section 11.1.2 on page 11-2."); + + + // INDEX: - AXI_RECM_ARLOCK_BOUNDARY + // ===== + // 4kbyte boundary: only bottom twelve bits (11 to 0) can change + property AXI_RECM_ARLOCK_BOUNDARY; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWADDR,AWLOCK, + ARADDR,ARLOCK})) & + i_RecommendOn // Parameter that can disable all AXI_REC*_* rules + |-> + // case for in lock or going into lock last + !(ARNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid read address in a locked sequence + (ARADDR[ADDR_MAX:12] != LockAddr[ADDR_MAX:12]) // address does not match current lock region + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) && // in unlocked or lock last state + (AWADDR[ADDR_MAX:12] != ARADDR[ADDR_MAX:12]) // lock address region values do not agree + ); + endproperty + axi_recm_arlock_boundary: assert property (AXI_RECM_ARLOCK_BOUNDARY) else + $warning("AXI_RECM_ARLOCK_BOUNDARY. It is recommended that all locked transaction sequences are kept within the same 4KB address region. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_RECM_ARLOCK_CTRL + // ===== + property AXI_RECM_ARLOCK_CTRL; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWPROT,AWCACHE,AWLOCK, + ARPROT,ARCACHE,ARLOCK})) & + i_RecommendOn // Parameter that can disable all AXI_REC*_* rules + |-> + // case for in lock or going into lock last + !(ARNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid read address in a locked sequence + ((ARPROT != LockProt) || (ARCACHE != LockCache)) // PROT or CACHE values do not match current lock + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) && // in unlocked or lock last state + ((AWPROT != ARPROT) || (AWCACHE != ARCACHE)) // lock PROT or CACHE values do not agree + ); + endproperty + axi_recm_arlock_ctrl: assert property (AXI_RECM_ARLOCK_CTRL) else + $warning("AXI_RECM_ARLOCK_CTRL. It is recommended that a master should not change AxPROT or AxCACHE during a sequence of locked accesses. Spec: section 6.3 on page 6-7."); + + + // INDEX: - AXI_RECM_ARLOCK_NUM + // ===== + property AXI_RECM_ARLOCK_NUM; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWLOCK,ARLOCK})) & + i_RecommendOn // Parameter that can disable all AXI_REC*_* rules + |-> + // case for in lock or going into lock last + !(ARNew && (LockState == `AXI_AUX_ST_LOCKED) && // new valid read address in a locked sequence + (ARLOCK == `AXI_ALOCK_LOCKED) // read is locked + ) && + // case for going into lock from either unlocked or lock last with both a locked read and write + !(AWNew && (AWLOCK == `AXI_ALOCK_LOCKED) && // new valid locked write + ARNew && (ARLOCK == `AXI_ALOCK_LOCKED) && // new valid locked read + ((LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST)) // in unlocked or lock last state + ); + endproperty + axi_recm_arlock_num: assert property (AXI_RECM_ARLOCK_NUM) else + $warning("AXI_RECM_ARLOCK_NUM. It is recommended that locked transaction sequences are limited to two transactions. Spec: section 6.3 on page 6-7."); + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_ARADDR_STABLE + // ===== + property AXI_ERRM_ARADDR_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARADDR})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARADDR); + endproperty + axi_errm_araddr_stable: assert property (AXI_ERRM_ARADDR_STABLE) else + $error("AXI_ERRM_ARADDR_STABLE. ARADDR must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARBURST_STABLE + // ===== + property AXI_ERRM_ARBURST_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARBURST})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARBURST); + endproperty + axi_errm_arburst_stable: assert property (AXI_ERRM_ARBURST_STABLE) else + $error("AXI_ERRM_ARBURST_STABLE. ARBURST must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARCACHE_STABLE + // ===== + property AXI_ERRM_ARCACHE_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARCACHE})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARCACHE); + endproperty + axi_errm_arcache_stable: assert property (AXI_ERRM_ARCACHE_STABLE) else + $error("AXI_ERRM_ARCACHE_STABLE. ARCACHE must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARID_STABLE + // ===== + property AXI_ERRM_ARID_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARID})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARID); + endproperty + axi_errm_arid_stable: assert property (AXI_ERRM_ARID_STABLE) else + $error("AXI_ERRM_ARID_STABLE. ARID must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARLEN_STABLE + // ===== + property AXI_ERRM_ARLEN_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARLEN})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARLEN); + endproperty + axi_errm_arlen_stable: assert property (AXI_ERRM_ARLEN_STABLE) else + $error("AXI_ERRM_ARLEN_STABLE. ARLEN must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARLOCK_STABLE + // ===== + property AXI_ERRM_ARLOCK_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARLOCK})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARLOCK); + endproperty + axi_errm_arlock_stable: assert property (AXI_ERRM_ARLOCK_STABLE) else + $error("AXI_ERRM_ARLOCK_STABLE. ARLOCK must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARPROT_STABLE + // ===== + property AXI_ERRM_ARPROT_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARPROT})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARPROT); + endproperty + axi_errm_arprot_stable: assert property (AXI_ERRM_ARPROT_STABLE) else + $error("AXI_ERRM_ARPROT_STABLE. ARPROT must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARSIZE_STABLE + // ===== + property AXI_ERRM_ARSIZE_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARSIZE})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARSIZE); + endproperty + axi_errm_arsize_stable: assert property (AXI_ERRM_ARSIZE_STABLE) else + $error("AXI_ERRM_ARSIZE_STABLE. ARSIZE must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARVALID_STABLE + // ===== + property AXI_ERRM_ARVALID_STABLE; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID & !ARREADY & !($isunknown({ARVALID,ARREADY})) + ##1 `AXI_SVA_RSTn + |-> ARVALID; + endproperty + axi_errm_arvalid_stable: assert property (AXI_ERRM_ARVALID_STABLE) else + $error("AXI_ERRM_ARVALID_STABLE. Once ARVALID is asserted, it must remain asserted until ARREADY is high. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_RECS_ARREADY_MAX_WAIT + // ===== + // Note: this rule does not error if VALID goes low (breaking VALID_STABLE rule) + property AXI_RECS_ARREADY_MAX_WAIT; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown({ARVALID,ARREADY})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + i_RecMaxWaitOn & // Parameter that can disable just AXI_REC*_MAX_WAIT rules + ( ARVALID & !ARREADY) + |-> ##[1:MAXWAITS] (!ARVALID | ARREADY); // READY=1 within MAXWAITS cycles (or VALID=0) + endproperty + axi_recs_arready_max_wait: assert property (AXI_RECS_ARREADY_MAX_WAIT) else + $warning("AXI_RECS_ARREADY_MAX_WAIT. ARREADY should be asserted within MAXWAITS cycles of ARVALID being asserted."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRM_ARADDR_X + // ===== + property AXI_ERRM_ARADDR_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARADDR); + endproperty + axi_errm_araddr_x: assert property (AXI_ERRM_ARADDR_X) else + $error("AXI_ERRM_ARADDR_X. When ARVALID is high, a value of X on ARADDR is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARBURST_X + // ===== + property AXI_ERRM_ARBURST_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARBURST); + endproperty + axi_errm_arburst_x: assert property (AXI_ERRM_ARBURST_X) else + $error("AXI_ERRM_ARBURST_X. When ARVALID is high, a value of X on ARBURST is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARCACHE_X + // ===== + property AXI_ERRM_ARCACHE_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARCACHE); + endproperty + axi_errm_arcache_x: assert property (AXI_ERRM_ARCACHE_X) else + $error("AXI_ERRM_ARCACHE_X. When ARVALID is high, a value of X on ARCACHE is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARID_X + // ===== + property AXI_ERRM_ARID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARID); + endproperty + axi_errm_arid_x: assert property (AXI_ERRM_ARID_X) else + $error("AXI_ERRM_ARID_X. When ARVALID is high, a value of X on ARID is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARLEN_X + // ===== + property AXI_ERRM_ARLEN_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARLEN); + endproperty + axi_errm_arlen_x: assert property (AXI_ERRM_ARLEN_X) else + $error("AXI_ERRM_ARLEN_X. When ARVALID is high, a value of X on ARLEN is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARLOCK_X + // ===== + property AXI_ERRM_ARLOCK_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARLOCK); + endproperty + axi_errm_arlock_x: assert property (AXI_ERRM_ARLOCK_X) else + $error("AXI_ERRM_ARLOCK_X. When ARVALID is high, a value of X on ARLOCK is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARPROT_X + // ===== + property AXI_ERRM_ARPROT_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARPROT); + endproperty + axi_errm_arprot_x: assert property (AXI_ERRM_ARPROT_X) else + $error("AXI_ERRM_ARPROT_X. When ARVALID is high, a value of X on ARPROT is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARSIZE_X + // ===== + property AXI_ERRM_ARSIZE_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARSIZE); + endproperty + axi_errm_arsize_x: assert property (AXI_ERRM_ARSIZE_X) else + $error("AXI_ERRM_ARSIZE_X. When ARVALID is high, a value of X on ARSIZE is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRM_ARVALID_X + // ===== + property AXI_ERRM_ARVALID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(ARVALID); + endproperty + axi_errm_arvalid_x: assert property (AXI_ERRM_ARVALID_X) else + $error("AXI_ERRM_ARVALID_X. When not in reset, a value of X on ARVALID is not permitted."); + + + // INDEX: - AXI_ERRS_ARREADY_X + // ===== + property AXI_ERRS_ARREADY_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(ARREADY); + endproperty + axi_errs_arready_x: assert property (AXI_ERRS_ARREADY_X) else + $error("AXI_ERRS_ARREADY_X. When not in reset, a value of X on ARREADY is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Read Data Channel (*_R*) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRS_RDATA_NUM + // ===== + property AXI_ERRS_RDATA_NUM; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RLAST,ArLenPending})) & + RVALID & RREADY + |-> ( ((ArCountPending == ArLenPending) & RLAST) // Last RDATA and RLAST is asserted + |((ArCountPending != ArLenPending) & ~RLAST) // Not last RDATA and RLAST is not asserted + ); + endproperty + axi_errs_rdata_num: assert property (AXI_ERRS_RDATA_NUM) else + $error("AXI_ERRS_RDATA_NUM. The number of read data items must match the corresponding ARLEN. Spec: table 4-1 on page 4-3."); + + + // INDEX: - AXI_ERRS_RLAST_ALL_DONE_EOS + // ===== + // EOS: End-Of-Simulation check (not suitable for formal proofs). + // Use +define+AXI_END_OF_SIMULATION=tb.EOS_signal when compiling. +`ifdef AXI_END_OF_SIMULATION + property AXI_ERRS_RLAST_ALL_DONE_EOS; + @(posedge `AXI_SVA_CLK) + !($isunknown({`AXI_END_OF_SIMULATION,nROutstanding})) & + `AXI_SVA_RSTn + ##1 `AXI_SVA_RSTn & $rose(`AXI_END_OF_SIMULATION) + |-> (nROutstanding == 1'b1); + endproperty + axi_errs_rlast_all_done_eos: assert property (AXI_ERRS_RLAST_ALL_DONE_EOS) else + $error("AXI_ERRS_RLAST_ALL_DONE_EOS. All outstanding read bursts must have completed."); +`endif + + + // INDEX: - AXI_ERRS_RID + // ===== + // Read data must always follow the address that it relates to. + property AXI_ERRS_RID; + @(posedge `AXI_SVA_CLK) + !($isunknown(RVALID)) & + RVALID + |-> (RidMatch > 0); + endproperty + axi_errs_rid: assert property (AXI_ERRS_RID) else + $error("AXI_ERRS_RID. A slave can only give read data with an ID to match an outstanding read transaction. Spec: section 8.3 on page 8-4."); + + + // INDEX: - AXI_ERRS_RRESP_EXOKAY + // ===== + property AXI_ERRS_RRESP_EXOKAY; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RRESP})) & + RVALID & RREADY & (RRESP == `AXI_RESP_EXOKAY) + |-> (ArExclPending); + endproperty + axi_errs_rresp_exokay: assert property (AXI_ERRS_RRESP_EXOKAY) else + $error("AXI_ERRS_RRESP_EXOKAY. An EXOKAY read response can only be given to an exclusive read access. Spec: section 6.2.3 on page 6-4."); + + + // INDEX: - AXI_ERRS_RVALID_RESET + // ===== + property AXI_ERRS_RVALID_RESET; + @(posedge `AXI_SVA_CLK) + !(`AXI_SVA_RSTn) & !($isunknown(`AXI_SVA_RSTn)) + ##1 `AXI_SVA_RSTn + |-> !RVALID; + endproperty + axi_errs_rvalid_reset: assert property (AXI_ERRS_RVALID_RESET) else + $error("AXI_ERRS_RVALID_RESET. RVALID must be low in the cycle when ARESETn first goes high. Spec: section 11.1.2 on page 11-2."); + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRS_RDATA_STABLE + // ===== + property AXI_ERRS_RDATA_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RDATA})) & + `AXI_SVA_RSTn & RVALID & !RREADY + ##1 `AXI_SVA_RSTn + |-> $stable(RDATA + | ~RdataMask + ); + endproperty + axi_errs_rdata_stable: assert property (AXI_ERRS_RDATA_STABLE) else + $error("AXI_ERRS_RDATA_STABLE. RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_RID_STABLE + // ===== + property AXI_ERRS_RID_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RID})) & + `AXI_SVA_RSTn & RVALID & !RREADY + ##1 `AXI_SVA_RSTn + |-> $stable(RID); + endproperty + axi_errs_rid_stable: assert property (AXI_ERRS_RID_STABLE) else + $error("AXI_ERRS_RID_STABLE. RID must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_RLAST_STABLE + // ===== + property AXI_ERRS_RLAST_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RLAST})) & + `AXI_SVA_RSTn & RVALID & !RREADY + ##1 `AXI_SVA_RSTn + |-> $stable(RLAST); + endproperty + axi_errs_rlast_stable: assert property (AXI_ERRS_RLAST_STABLE) else + $error("AXI_ERRS_RLAST_STABLE. RLAST must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_RRESP_STABLE + // ===== + property AXI_ERRS_RRESP_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RRESP})) & + `AXI_SVA_RSTn & RVALID & !RREADY + ##1 `AXI_SVA_RSTn + |-> $stable(RRESP); + endproperty + axi_errs_rresp_stable: assert property (AXI_ERRS_RRESP_STABLE) else + $error("AXI_ERRS_RRESP_STABLE. RRESP must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_RVALID_STABLE + // ===== + property AXI_ERRS_RVALID_STABLE; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & RVALID & !RREADY & !($isunknown({RVALID,RREADY})) + ##1 `AXI_SVA_RSTn + |-> RVALID; + endproperty + axi_errs_rvalid_stable: assert property (AXI_ERRS_RVALID_STABLE) else + $error("AXI_ERRS_RVALID_STABLE. Once RVALID is asserted, it must remain asserted until RREADY is high. Spec: section 3.1.5 on page 3-5."); + + + // INDEX: - AXI_RECM_RREADY_MAX_WAIT + // ===== + // Note: this rule does not error if VALID goes low (breaking VALID_STABLE rule) + property AXI_RECM_RREADY_MAX_WAIT; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown({RVALID,RREADY})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + i_RecMaxWaitOn & // Parameter that can disable just AXI_REC*_MAX_WAIT rules + ( RVALID & !RREADY) + |-> ##[1:MAXWAITS] (!RVALID | RREADY); // READY=1 within MAXWAITS cycles (or VALID=0) + endproperty + axi_recm_rready_max_wait: assert property (AXI_RECM_RREADY_MAX_WAIT) else + $warning("AXI_RECM_RREADY_MAX_WAIT. RREADY should be asserted within MAXWAITS cycles of RVALID being asserted."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRS_RDATA_X + // ===== + property AXI_ERRS_RDATA_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & RVALID + |-> ! $isunknown(RDATA | ~RdataMask); + endproperty + axi_errs_rdata_x: assert property (AXI_ERRS_RDATA_X) else + $error("AXI_ERRS_RDATA_X. When RVALID is high, a value of X on RDATA valid byte lanes is not permitted."); + + + // INDEX: - AXI_ERRM_RREADY_X + // ===== + property AXI_ERRM_RREADY_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(RREADY); + endproperty + axi_errm_rready_x: assert property (AXI_ERRM_RREADY_X) else + $error("AXI_ERRM_RREADY_X. When not in reset, a value of X on RREADY is not permitted."); + + + // INDEX: - AXI_ERRS_RID_X + // ===== + property AXI_ERRS_RID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & RVALID + |-> ! $isunknown(RID); + endproperty + axi_errs_rid_x: assert property (AXI_ERRS_RID_X) else + $error("AXI_ERRS_RID_X. When RVALID is high, a value of X on RID is not permitted."); + + + // INDEX: - AXI_ERRS_RLAST_X + // ===== + property AXI_ERRS_RLAST_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & RVALID + |-> ! $isunknown(RLAST); + endproperty + axi_errs_rlast_x: assert property (AXI_ERRS_RLAST_X) else + $error("AXI_ERRS_RLAST_X. When RVALID is high, a value of X on RLAST is not permitted."); + + + // INDEX: - AXI_ERRS_RRESP_X + // ===== + property AXI_ERRS_RRESP_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & RVALID + |-> ! $isunknown(RRESP); + endproperty + axi_errs_rresp_x: assert property (AXI_ERRS_RRESP_X) else + $error("AXI_ERRS_RRESP_X. When RVALID is high, a value of X on RRESP is not permitted."); + + + // INDEX: - AXI_ERRS_RVALID_X + // ===== + property AXI_ERRS_RVALID_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(RVALID); + endproperty + axi_errs_rvalid_x: assert property (AXI_ERRS_RVALID_X) else + $error("AXI_ERRS_RVALID_X. When not in reset, a value of X on RVALID is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Low Power Interface (*_C*) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules (none for Low Power signals) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules (asynchronous to ACLK) +// ===== +// The low-power handshake rules below use rising/falling edges on REQ and ACK, +// in order to detect changes within ACLK cycles (including low power state). +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRL_CSYSACK_FALL + // ===== + property AXI_ERRL_CSYSACK_FALL; + @(negedge CSYSACK) // falling edge of CSYSACK + `AXI_SVA_RSTn & !($isunknown(CSYSREQ)) + |-> ~CSYSREQ; // CSYSREQ low + endproperty + axi_errl_csysack_fall: assert property (AXI_ERRL_CSYSACK_FALL) else + $error("AXI_ERRL_CSYSACK_FALL. When CSYSACK transitions from high to low, CSYSREQ must be low. Spec: figure 12-1 on page 12-3."); + + + // INDEX: - AXI_ERRL_CSYSACK_RISE + // ===== + property AXI_ERRL_CSYSACK_RISE; + @(posedge CSYSACK) // rising edge of CSYSACK + `AXI_SVA_RSTn & !($isunknown(CSYSREQ)) + |-> CSYSREQ; // CSYSREQ high + endproperty + axi_errl_csysack_rise: assert property (AXI_ERRL_CSYSACK_RISE) else + $error("AXI_ERRL_CSYSACK_RISE. When CSYSACK transitions from low to high, CSYSREQ must be high. Spec: figure 12-1 on page 12-3."); + + + // INDEX: - AXI_ERRL_CSYSREQ_FALL + // ===== + property AXI_ERRL_CSYSREQ_FALL; + @(negedge CSYSREQ) // falling edge of CSYSREQ + `AXI_SVA_RSTn & !($isunknown(CSYSACK)) + |-> CSYSACK; // CSYSACK high + endproperty + axi_errl_csysreq_fall: assert property (AXI_ERRL_CSYSREQ_FALL) else + $error("AXI_ERRL_CSYSREQ_FALL. When CSYSREQ transitions from high to low, CSYSACK must be high. Spec: figure 12-1 on page 12-3."); + + + // INDEX: - AXI_ERRL_CSYSREQ_RISE + // ===== + property AXI_ERRL_CSYSREQ_RISE; + @(posedge CSYSREQ) // rising edge of CSYSREQ + `AXI_SVA_RSTn & !($isunknown(CSYSACK)) + |-> ~CSYSACK; // CSYSACK low + endproperty + axi_errl_csysreq_rise: assert property (AXI_ERRL_CSYSREQ_RISE) else + $error("AXI_ERRL_CSYSREQ_RISE. When CSYSREQ transitions from low to high, CSYSACK must be low. Spec: figure 12-1 on page 12-3."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRL_CACTIVE_X + // ===== + property AXI_ERRL_CACTIVE_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(CACTIVE); + endproperty + axi_errl_cactive_x: assert property (AXI_ERRL_CACTIVE_X) else + $error("AXI_ERRL_CACTIVE_X. When not in reset, a value of X on CACTIVE is not permitted."); + + + // INDEX: - AXI_ERRL_CSYSACK_X + // ===== + property AXI_ERRL_CSYSACK_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(CSYSACK); + endproperty + axi_errl_csysack_x: assert property (AXI_ERRL_CSYSACK_X) else + $error("AXI_ERRL_CSYSACK_X. When not in reset, a value of X on CSYSACK is not permitted."); + + + // INDEX: - AXI_ERRL_CSYSREQ_X + // ===== + property AXI_ERRL_CSYSREQ_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn + |-> ! $isunknown(CSYSREQ); + endproperty + axi_errl_csysreq_x: assert property (AXI_ERRL_CSYSREQ_X) else + $error("AXI_ERRL_CSYSREQ_X. When not in reset, a value of X on CSYSREQ is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: Exclusive Access +// ===== +// These are inter-channel rules. +// Supports one outstanding exclusive access per ID +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules +//------------------------------------------------------------------------------ +// INDEX: - + + + // INDEX: - AXI_ERRM_EXCL_ALIGN + // ===== + // Burst lengths that are not a power of two are not checked here, because + // these will violate EXCLLEN. Checked for excl reads only as AXI_RECM_EXCL_PAIR + // or AXI_RECM_EXCL_MATCH will fire if an excl write violates. + property AXI_ERRM_EXCL_ALIGN; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARLOCK,ARLEN,ARADDR})) & + (ARVALID & // valid address + (ARLOCK == `AXI_ALOCK_EXCL) & // exclusive transaction + (ARLEN == `AXI_ALEN_1 || // length is power of 2 + ARLEN == `AXI_ALEN_2 || + ARLEN == `AXI_ALEN_4 || + ARLEN == `AXI_ALEN_8 || + ARLEN == `AXI_ALEN_16)) + |-> ((ARADDR[10:0] & ExclMask) == ARADDR[10:0]); // address aligned + endproperty + axi_errm_excl_align: assert property (AXI_ERRM_EXCL_ALIGN) else + $error("AXI_ERRM_EXCL_ALIGN. The address of an exclusive access must be aligned to the total number of bytes in the transaction. Spec: section 6.2.4 on page 6-5."); + + + // INDEX: - AXI_ERRM_EXCL_LEN + // ===== + // Checked for excl reads only as AXI_RECM_EXCL_PAIR or AXI_RECM_EXCL_MATCH will + // fire if an excl write violates. + property AXI_ERRM_EXCL_LEN; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARLOCK,ARLEN})) & + ARVALID & (ARLOCK == `AXI_ALOCK_EXCL) + |-> ((ARLEN == `AXI_ALEN_1) || + (ARLEN == `AXI_ALEN_2) || + (ARLEN == `AXI_ALEN_4) || + (ARLEN == `AXI_ALEN_8) || + (ARLEN == `AXI_ALEN_16)); + endproperty + axi_errm_excl_len: assert property (AXI_ERRM_EXCL_LEN) else + $error("AXI_ERRM_EXCL_LEN. The number of bytes to be transferred in an exclusive access burst must be a power of 2. Spec: section 6.2.4 on page 6-5."); + + + // INDEX: - AXI_RECM_EXCL_MATCH + // ===== + // Recommendation as it can be affected by software, e.g. if a dummy STREX is used to clear any outstanding exclusive accesses. + property AXI_RECM_EXCL_MATCH; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWLOCK,ExclAwId,ExclAwMatch,AWADDR,AWSIZE,AWLEN,AWBURST,AWCACHE,AWPROT,AWUSER})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + AWVALID & AWREADY & + (AWLOCK == `AXI_ALOCK_EXCL) & ExclReadAddr[ExclAwId] // excl write & excl read outstanding + & ExclAwMatch + |-> ((ExclAddr[ExclAwId] == AWADDR) & + (ExclSize[ExclAwId] == AWSIZE) & + (ExclLen[ExclAwId] == AWLEN) & + (ExclBurst[ExclAwId]== AWBURST)& + (ExclCache[ExclAwId]== AWCACHE)& + (ExclProt[ExclAwId] == AWPROT) & + (ExclUser[ExclAwId] == AWUSER) + ); + endproperty + axi_recm_excl_match: assert property (AXI_RECM_EXCL_MATCH) else + $warning("AXI_RECM_EXCL_MATCH. The address, size and length of an exclusive write should be the same as the preceding exclusive read with the same ID. Spec: section 6.2.4 on page 6-5."); + + + // INDEX: - AXI_ERRM_EXCL_MAX + // ===== + // Burst lengths that are not a power of two are not checked here, because + // these will violate EXCLLEN. Bursts of length 1 can never violate this + // rule. Checked for excl reads only as AXI_RECM_EXCL_PAIR or AXI_RECM_EXCL_MATCH will + // fire if an excl write violates. + property AXI_ERRM_EXCL_MAX; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARLOCK,ARLEN})) & + (ARVALID & // valid address + (ARLOCK == `AXI_ALOCK_EXCL) & // exclusive transaction + (ARLEN == `AXI_ALEN_2 || // length is power of 2 + ARLEN == `AXI_ALEN_4 || + ARLEN == `AXI_ALEN_8 || + ARLEN == `AXI_ALEN_16)) + |-> (ArLenInBytes <= 128 ); // max 128 bytes transferred + endproperty + axi_errm_excl_max: assert property (AXI_ERRM_EXCL_MAX) else + $error("AXI_ERRM_EXCL_MAX. The maximum number of bytes that can be transferred in an exclusive burst is 128. Spec: section 6.2.4 on page 6-5."); + + + // INDEX: - AXI_RECM_EXCL_PAIR + // ===== + // Recommendation as it can be affected by software, e.g. if a dummy STREX is used to clear any outstanding exclusive accesses. + property AXI_RECM_EXCL_PAIR; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWLOCK,ExclAwMatch,ExclAwId})) & + i_RecommendOn & // Parameter that can disable all AXI_REC*_* rules + AWVALID & AWREADY & (AWLOCK == `AXI_ALOCK_EXCL) // excl write + |-> (ExclAwMatch && + ExclReadAddr[ExclAwId] && + ExclReadData[ExclAwId]); // excl read with same ID complete + endproperty + axi_recm_excl_pair: assert property (AXI_RECM_EXCL_PAIR) else + $warning("AXI_RECM_EXCL_PAIR. An exclusive write should have an earlier outstanding completed exclusive read with the same ID. Spec: section 6.2.2 on page 6-4."); + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: AXI Rules: USER_* Rules (extension to AXI) +// ===== +// The USER signals are user-defined extensions to the AXI spec, so have been +// located separately from the channel-specific rules. +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Functional Rules (none for USER signals) +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 2) Handshake Rules +//------------------------------------------------------------------------------ + + + // INDEX: - AXI_ERRM_AWUSER_STABLE + // ===== + property AXI_ERRM_AWUSER_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({AWVALID,AWREADY,AWUSER})) & + `AXI_SVA_RSTn & AWVALID & !AWREADY + ##1 `AXI_SVA_RSTn + |-> $stable(AWUSER); + endproperty + axi_errm_awuser_stable: assert property (AXI_ERRM_AWUSER_STABLE) else + $error("AXI_ERRM_AWUSER_STABLE. AWUSER must remain stable when AWVALID is asserted and AWREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_WUSER_STABLE + // ===== + property AXI_ERRM_WUSER_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({WVALID,WREADY,WUSER})) & + `AXI_SVA_RSTn & WVALID & !WREADY + ##1 `AXI_SVA_RSTn + |-> $stable(WUSER); + endproperty + axi_errm_wuser_stable: assert property (AXI_ERRM_WUSER_STABLE) else + $error("AXI_ERRM_WUSER_STABLE. WUSER must remain stable when WVALID is asserted and WREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_BUSER_STABLE + // ===== + property AXI_ERRS_BUSER_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({BVALID,BREADY,BUSER})) & + `AXI_SVA_RSTn & BVALID & !BREADY + ##1 `AXI_SVA_RSTn + |-> $stable(BUSER); + endproperty + axi_errs_buser_stable: assert property (AXI_ERRS_BUSER_STABLE) else + $error("AXI_ERRS_BUSER_STABLE. BUSER must remain stable when BVALID is asserted and BREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRM_ARUSER_STABLE + // ===== + property AXI_ERRM_ARUSER_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({ARVALID,ARREADY,ARUSER})) & + `AXI_SVA_RSTn & ARVALID & !ARREADY + ##1 `AXI_SVA_RSTn + |-> $stable(ARUSER); + endproperty + axi_errm_aruser_stable: assert property (AXI_ERRM_ARUSER_STABLE) else + $error("AXI_ERRM_ARUSER_STABLE. ARUSER must remain stable when ARVALID is asserted and ARREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + + // INDEX: - AXI_ERRS_RUSER_STABLE + // ===== + property AXI_ERRS_RUSER_STABLE; + @(posedge `AXI_SVA_CLK) + !($isunknown({RVALID,RREADY,RUSER})) & + `AXI_SVA_RSTn & RVALID & !RREADY + ##1 `AXI_SVA_RSTn + |-> $stable(RUSER); + endproperty + axi_errs_ruser_stable: assert property (AXI_ERRS_RUSER_STABLE) else + $error("AXI_ERRS_RUSER_STABLE. RUSER must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2."); + + +//------------------------------------------------------------------------------ +// INDEX: 3) X-Propagation Rules +//------------------------------------------------------------------------------ +`ifdef AXI_XCHECK_OFF +`else // X-Checking on by default + + + // INDEX: - AXI_ERRM_AWUSER_X + // ===== + property AXI_ERRM_AWUSER_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & AWVALID + |-> ! $isunknown(AWUSER); + endproperty + axi_errm_awuser_x: assert property (AXI_ERRM_AWUSER_X) else + $error("AXI_ERRM_AWUSER_X. When AWVALID is high, a value of X on AWUSER is not permitted. Spec: section 3.1.1 on page 3-3."); + + + // INDEX: - AXI_ERRM_WUSER_X + // ===== + property AXI_ERRM_WUSER_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & WVALID + |-> ! $isunknown(WUSER); + endproperty + axi_errm_wuser_x: assert property (AXI_ERRM_WUSER_X) else + $error("AXI_ERRM_WUSER_X. When WVALID is high, a value of X on WUSER is not permitted."); + + + // INDEX: - AXI_ERRS_BUSER_X + // ===== + property AXI_ERRS_BUSER_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & BVALID + |-> ! $isunknown(BUSER); + endproperty + axi_errs_buser_x: assert property (AXI_ERRS_BUSER_X) else + $error("AXI_ERRS_BUSER_X. When BVALID is high, a value of X on BUSER is not permitted."); + + + // INDEX: - AXI_ERRM_ARUSER_X + // ===== + property AXI_ERRM_ARUSER_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & ARVALID + |-> ! $isunknown(ARUSER); + endproperty + axi_errm_aruser_x: assert property (AXI_ERRM_ARUSER_X) else + $error("AXI_ERRM_ARUSER_X. When ARVALID is high, a value of X on ARUSER is not permitted. Spec: section 3.1.4 on page 3-4."); + + + // INDEX: - AXI_ERRS_RUSER_X + // ===== + property AXI_ERRS_RUSER_X; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & RVALID + |-> ! $isunknown(RUSER); + endproperty + axi_errs_ruser_x: assert property (AXI_ERRS_RUSER_X) else + $error("AXI_ERRS_RUSER_X. When RVALID is high, a value of X on RUSER is not permitted."); + +`endif // AXI_XCHECK_OFF + + +//------------------------------------------------------------------------------ +// INDEX: +// INDEX: Auxiliary Logic +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// INDEX: 1) Rules for Auxiliary Logic +//------------------------------------------------------------------------------ + + + //---------------------------------------------------------------------------- + // INDEX: a) Master (AUXM*) + //---------------------------------------------------------------------------- + + + // INDEX: - AXI_AUXM_DATA_WIDTH + // ===== + property AXI_AUXM_DATA_WIDTH; + @(posedge `AXI_SVA_CLK) + (DATA_WIDTH == 32 || + DATA_WIDTH == 64 || + DATA_WIDTH == 128 || + DATA_WIDTH == 256 || + DATA_WIDTH == 512 || + DATA_WIDTH == 1024); + endproperty + axi_auxm_data_width: assert property (AXI_AUXM_DATA_WIDTH) else + $error("AXI_AUXM_DATA_WIDTH. Parameter DATA_WIDTH must be 32, 64, 128, 256, 512 or 1024"); + + + // INDEX: - AXI_AUXM_ADDR_WIDTH + // ===== + property AXI_AUXM_ADDR_WIDTH; + @(posedge `AXI_SVA_CLK) + (ADDR_WIDTH >= 32 && ADDR_WIDTH <= 64); + endproperty + axi_auxm_addr_width: assert property (AXI_AUXM_ADDR_WIDTH) else + $error("AXI_AUXM_ADDR_WIDTH. Parameter ADDR_WIDTH must be between 32 and 64 bits inclusive"); + + + // INDEX: - AXI_AUXM_AWUSER_WIDTH + // ===== + property AXI_AUXM_AWUSER_WIDTH; + @(posedge `AXI_SVA_CLK) + (AWUSER_WIDTH >= 1); + endproperty + axi_auxm_awuser_width: assert property (AXI_AUXM_AWUSER_WIDTH) else + $error("AXI_AUXM_AWUSER_WIDTH. Parameter AWUSER_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_WUSER_WIDTH + // ===== + property AXI_AUXM_WUSER_WIDTH; + @(posedge `AXI_SVA_CLK) + (WUSER_WIDTH >= 1); + endproperty + axi_auxm_wuser_width: assert property (AXI_AUXM_WUSER_WIDTH) else + $error("AXI_AUXM_WUSER_WIDTH. Parameter WUSER_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_BUSER_WIDTH + // ===== + property AXI_AUXM_BUSER_WIDTH; + @(posedge `AXI_SVA_CLK) + (BUSER_WIDTH >= 1); + endproperty + axi_auxm_buser_width: assert property (AXI_AUXM_BUSER_WIDTH) else + $error("AXI_AUXM_BUSER_WIDTH. Parameter BUSER_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_ARUSER_WIDTH + // ===== + property AXI_AUXM_ARUSER_WIDTH; + @(posedge `AXI_SVA_CLK) + (ARUSER_WIDTH >= 1); + endproperty + axi_auxm_aruser_width: assert property (AXI_AUXM_ARUSER_WIDTH) else + $error("AXI_AUXM_ARUSER_WIDTH. Parameter ARUSER_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_RUSER_WIDTH + // ===== + property AXI_AUXM_RUSER_WIDTH; + @(posedge `AXI_SVA_CLK) + (RUSER_WIDTH >= 1); + endproperty + axi_auxm_ruser_width: assert property (AXI_AUXM_RUSER_WIDTH) else + $error("AXI_AUXM_RUSER_WIDTH. Parameter RUSER_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_ID_WIDTH + // ===== + property AXI_AUXM_ID_WIDTH; + @(posedge `AXI_SVA_CLK) + (ID_WIDTH >= 1); + endproperty + axi_auxm_id_width: assert property (AXI_AUXM_ID_WIDTH) else + $error("AXI_AUXM_ID_WIDTH. Parameter ID_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_EXMON_WIDTH + // ===== + property AXI_AUXM_EXMON_WIDTH; + @(posedge `AXI_SVA_CLK) + (EXMON_WIDTH >= 1); + endproperty + axi_auxm_exmon_width: assert property (AXI_AUXM_EXMON_WIDTH) else + $error("AXI_AUXM_EXMON_WIDTH. Parameter EXMON_WIDTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_WDEPTH + // ===== + property AXI_AUXM_WDEPTH; + @(posedge `AXI_SVA_CLK) + (WDEPTH >= 1); + endproperty + axi_auxm_wdepth: assert property (AXI_AUXM_WDEPTH) else + $error("AXI_AUXM_WDEPTH. Parameter WDEPTH must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_MAXRBURSTS + // ===== + property AXI_AUXM_MAXRBURSTS; + @(posedge `AXI_SVA_CLK) + (MAXRBURSTS >= 1); + endproperty + axi_auxm_maxrbursts: assert property (AXI_AUXM_MAXRBURSTS) else + $error("AXI_AUXM_MAXRBURSTS. Parameter MAXRBURSTS must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_MAXWBURSTS + // ===== + property AXI_AUXM_MAXWBURSTS; + @(posedge `AXI_SVA_CLK) + (MAXWBURSTS >= 1); + endproperty + axi_auxm_maxwbursts: assert property (AXI_AUXM_MAXWBURSTS) else + $error("AXI_AUXM_MAXWBURSTS. Parameter MAXWBURSTS must be greater than or equal to 1"); + + + // INDEX: - AXI_AUXM_RCAM_OVERFLOW + // ===== + property AXI_AUXM_RCAM_OVERFLOW; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(RIndex)) + |-> (RIndex <= (MAXRBURSTS+1)); + endproperty + axi_auxm_rcam_overflow: assert property (AXI_AUXM_RCAM_OVERFLOW) else + $error("AXI_AUXM_RCAM_OVERFLOW. Read CAM overflow, increase MAXRBURSTS parameter."); + + + // INDEX: - AXI_AUXM_RCAM_UNDERFLOW + // ===== + property AXI_AUXM_RCAM_UNDERFLOW; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(RIndex)) + |-> (RIndex > 0); + endproperty + axi_auxm_rcam_underflow: assert property (AXI_AUXM_RCAM_UNDERFLOW) else + $error("AXI_AUXM_RCAM_UNDERFLOW. Read CAM underflow."); + + + // INDEX: - AXI_AUXM_WCAM_OVERFLOW + // ===== + property AXI_AUXM_WCAM_OVERFLOW; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(WIndex)) + |-> (WIndex <= (MAXWBURSTS+1)); + endproperty + axi_auxm_wcam_overflow: assert property (AXI_AUXM_WCAM_OVERFLOW) else + $error("AXI_AUXM_WCAM_OVERFLOW. Write CAM overflow, increase MAXWBURSTS parameter."); + + + // INDEX: - AXI_AUXM_WCAM_UNDERFLOW + // ===== + property AXI_AUXM_WCAM_UNDERFLOW; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(WIndex)) + |-> (WIndex > 0); + endproperty + axi_auxm_wcam_underflow: assert property (AXI_AUXM_WCAM_UNDERFLOW) else + $error("AXI_AUXM_WCAM_UNDERFLOW. Write CAM underflow"); + + + // INDEX: - AXI_AUXM_EXCL_OVERFLOW + // ===== + property AXI_AUXM_EXCL_OVERFLOW; + @(posedge `AXI_SVA_CLK) + `AXI_SVA_RSTn & !($isunknown(ExclIdOverflow)) + |-> (!ExclIdOverflow); + endproperty + axi_auxm_excl_overflow: assert property (AXI_AUXM_EXCL_OVERFLOW) else + $error("AXI_AUXM_EXCL_OVERFLOW. Exclusive access monitor overflow, increase EXMON_WIDTH parameter."); + + +//------------------------------------------------------------------------------ +// INDEX: 2) Combinatorial Logic +//------------------------------------------------------------------------------ + + + //---------------------------------------------------------------------------- + // INDEX: a) Masks + //---------------------------------------------------------------------------- + + + // INDEX: - AlignMaskR + // ===== + // Calculate wrap mask for read address + always @(ARSIZE or ARVALID) + begin + if (ARVALID) + case (ARSIZE) + `AXI_ASIZE_1024: AlignMaskR = 7'b0000000; + `AXI_ASIZE_512: AlignMaskR = 7'b1000000; + `AXI_ASIZE_256: AlignMaskR = 7'b1100000; + `AXI_ASIZE_128: AlignMaskR = 7'b1110000; + `AXI_ASIZE_64: AlignMaskR = 7'b1111000; + `AXI_ASIZE_32: AlignMaskR = 7'b1111100; + `AXI_ASIZE_16: AlignMaskR = 7'b1111110; + `AXI_ASIZE_8: AlignMaskR = 7'b1111111; + default: AlignMaskR = 7'b1111111; + endcase + else + AlignMaskR = 7'b1111111; + end + + + // INDEX: - AlignMaskW + // ===== + // Calculate wrap mask for write address + always @(AWSIZE or AWVALID) + begin + if (AWVALID) + case (AWSIZE) + `AXI_ASIZE_1024: AlignMaskW = 7'b0000000; + `AXI_ASIZE_512: AlignMaskW = 7'b1000000; + `AXI_ASIZE_256: AlignMaskW = 7'b1100000; + `AXI_ASIZE_128: AlignMaskW = 7'b1110000; + `AXI_ASIZE_64: AlignMaskW = 7'b1111000; + `AXI_ASIZE_32: AlignMaskW = 7'b1111100; + `AXI_ASIZE_16: AlignMaskW = 7'b1111110; + `AXI_ASIZE_8: AlignMaskW = 7'b1111111; + default: AlignMaskW = 7'b1111111; + endcase // case(AWSIZE) + else + AlignMaskW = 7'b1111111; + end + + + // INDEX: - ExclMask + // ===== + always @(ARLEN or ARSIZE) + begin : p_ExclMaskComb + ExclMask = ~((({7'b000_0000, ARLEN} + 11'b000_0000_0001) << ARSIZE) - 11'b000_0000_0001); + end // block: p_ExclMaskComb + + + // INDEX: - WdataMask + // ===== + always @(WSTRB) + begin : p_WdataMaskComb + integer i; // data byte loop counter + integer j; // data bit loop counter + + for (i = 0; i < STRB_WIDTH; i = i + 1) + for (j = i * 8; j <= (i * 8) + 7; j = j + 1) + WdataMask[j] = WSTRB[i]; + end + + + // INDEX: - RdataMask + // ===== + assign RdataMask = ReadDataMask(RBurstCam[RidMatch], RCountCam[RidMatch]); + + + //---------------------------------------------------------------------------- + // INDEX: b) Increments + //---------------------------------------------------------------------------- + + + // INDEX: - ArAddrIncr + // ===== + always @(ARSIZE or ARLEN or ARADDR) + begin : p_RAddrIncrComb + ArAddrIncr = ARADDR + (ARLEN << ARSIZE); // The final address of the burst + end + + + // INDEX: - AwAddrIncr + // ===== + always @(AWSIZE or AWLEN or AWADDR) + begin : p_WAddrIncrComb + AwAddrIncr = AWADDR + (AWLEN << AWSIZE); // The final address of the burst + end + + + //---------------------------------------------------------------------------- + // INDEX: c) Conversions + //---------------------------------------------------------------------------- + + + // INDEX: - ArLenInBytes + // ===== + always @(ARSIZE or ARLEN) + begin : p_ArLenInBytes + ArLenInBytes = (({8'h00, ARLEN} + 12'h001) << ARSIZE); // bytes = (ARLEN+1) data transfers x ARSIZE bytes + end + + + // INDEX: - ArSizeInBits + // ===== + always @(ARSIZE) + begin : p_ArSizeInBits + ArSizeInBits = (11'b000_0000_1000 << ARSIZE); // bits = 8 x ARSIZE bytes + end + + + // INDEX: - AwSizeInBits + // ===== + always @(AWSIZE) + begin : p_AwSizeInBits + AwSizeInBits = (11'b000_0000_1000 << AWSIZE); // bits = 8 x AWSIZE bytes + end + + + //---------------------------------------------------------------------------- + // INDEX: d) Other + //---------------------------------------------------------------------------- + + + // INDEX: - ArExclPending + // ===== + // Avoid putting on assertion directly as index is an integer + assign ArExclPending = RBurstCam[RidMatch][EXCL]; + + + // INDEX: - ArLenPending + // ===== + // Avoid putting on assertion directly as index is an integer + assign ArLenPending = {1'b0, RBurstCam[RidMatch][ALENHI:ALENLO]}; + + // INDEX: - ArCountPending + // ===== + // Avoid putting on assertion directly as index is an integer + assign ArCountPending = RCountCam[RidMatch]; + + +//------------------------------------------------------------------------------ +// INDEX: 3) EXCL & LOCK Accesses +//------------------------------------------------------------------------------ + + + // INDEX: - Exclusive Access ID Lookup + // ===== + // Map transaction IDs to the available exclusive access storage loactions + + // Lookup table for IDs used by the exclusive access monitor + // Each location in the table has a valid flag to indicate if the ID is in use + // The location of an ID flagged as valid is used as a virtual ID in the + // exclusive access monitor checks + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_ExclIdSeq + integer i; // loop counter + if (!`AXI_AUX_RSTn) + begin + ExclIdValid <= {EXMON_HI+1{1'b0}}; + ExclIdDelta <= 1'b0; + for (i = 0; i <= EXMON_HI; i = i + 1) + begin + ExclId[i] <= {ID_WIDTH{1'b0}}; + end + end + else // clk edge + begin + // exclusive read address transfer + if (ARVALID && ARREADY && (ARLOCK == `AXI_ALOCK_EXCL) && + !ExclIdFull) + begin + ExclId[ExclIdWrPtr] <= ARID; + ExclIdValid[ExclIdWrPtr] <= 1'b1; + ExclIdDelta <= ~ExclIdDelta; + end + // exclusive write + if (AWVALID && AWREADY && (AWLOCK == `AXI_ALOCK_EXCL) && + ExclAwMatch) + begin + ExclIdValid[ExclAwId] <= 1'b0; + ExclIdDelta <= ~ExclIdDelta; + end + end // else: !if(!`AXI_AUX_RSTn) + end // block: p_ExclIdSeq + + // Lookup table is full when all valid bits are set + assign ExclIdFull = &ExclIdValid; + + // Lookup table overflows when it is full and another exclusive read happens + // with an ID that does not match any already being monitored + assign ExclIdOverflow = ExclIdFull && + ARVALID && ARREADY && (ARLOCK == `AXI_ALOCK_EXCL) && + !ExclRMatch; + + // New IDs are written to the highest location + // that does not have the valid flag set + always @(ExclIdValid or ExclIdDelta) + begin : p_ExclIdFreePtrComb + integer i; // loop counter + ExclIdFreePtr = 0; + for (i = 0; i <= EXMON_HI; i = i + 1) + begin + if (ExclIdValid[i] == 1'b0) + begin + ExclIdFreePtr = i; + end + end + end // p_ExclIdFreePtrComb + + // If the ID is already being monitored then reuse the location + // New IDs are written to the highest location + // that does not have the valid flag set + assign ExclIdWrPtr = ExclArMatch ? ExclArId : ExclIdFreePtr; + + // Write address ID comparator + always @(AWVALID or AWID or ExclIdValid or ExclIdDelta) + begin : p_ExclAwMatchComb + integer i; // loop counter + ExclAwMatch = 1'b0; + ExclAwId = {EXMON_WIDTH{1'b0}}; + if (AWVALID) + begin + for (i = 0; i <= EXMON_HI; i = i + 1) + begin + if (ExclIdValid[i] && (AWID == ExclId[i])) + begin + ExclAwMatch = 1'b1; + ExclAwId = i; + end + end + end + end // p_ExclAwMatchComb + + // Read address ID comparator + always @(ARVALID or ARID or ExclIdValid or ExclIdDelta) + begin : p_ExclArMatchComb + integer i; // loop counter + ExclArMatch = 1'b0; + ExclArId = {EXMON_WIDTH{1'b0}}; + if (ARVALID) + begin + for (i = 0; i <= EXMON_HI; i = i + 1) + begin + if (ExclIdValid[i] && (ARID == ExclId[i])) + begin + ExclArMatch = 1'b1; + ExclArId = i; + end + end + end + end // p_ExclArMatchComb + + // Read data ID comparator + always @(RVALID or RID or ExclIdValid or ExclIdDelta) + begin : p_ExclRMatchComb + integer i; // loop counter + ExclRMatch = 1'b0; + ExclRId = {EXMON_WIDTH{1'b0}}; + if (RVALID) + begin + for (i = 0; i <= EXMON_HI; i = i + 1) + begin + if (ExclIdValid[i] && (RID == ExclId[i])) + begin + ExclRMatch = 1'b1; + ExclRId = i; + end + end + end + end // p_ExclRMatchComb + + // INDEX: - Exclusive Access Storage + // ===== + // Store exclusive control info on each read for checking against write + + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_ExclCtrlSeq + integer i; // loop counter + + if (!`AXI_AUX_RSTn) + for (i = 0; i <= EXMON_HI; i = i + 1) + begin + ExclReadAddr[i] <= 1'b0; + ExclReadData[i] <= 1'b0; + ExclAddr[i] <= {ADDR_WIDTH{1'b0}}; + ExclSize[i] <= 3'b000; + ExclLen[i] <= 4'h0; + ExclBurst[i] <= 2'b00; + ExclCache[i] <= 4'h0; + ExclProt[i] <= 3'b000; + ExclUser[i] <= {ARUSER_WIDTH{1'b0}}; + end + else // clk edge + begin + // exclusive read address transfer + if (ARVALID && ARREADY && (ARLOCK == `AXI_ALOCK_EXCL) && + !ExclIdFull) + begin + ExclReadAddr[ExclIdWrPtr] <= 1'b1; // set exclusive read addr flag for ARID + ExclReadData[ExclIdWrPtr] <= 1'b0; // reset exclusive read data flag for ARID + ExclAddr[ExclIdWrPtr] <= ARADDR; + ExclSize[ExclIdWrPtr] <= ARSIZE; + ExclLen[ExclIdWrPtr] <= ARLEN; + ExclBurst[ExclIdWrPtr] <= ARBURST; + ExclCache[ExclIdWrPtr] <= ARCACHE; + ExclProt[ExclIdWrPtr] <= ARPROT; + ExclUser[ExclIdWrPtr] <= ARUSER; + end + // exclusive write + if (AWVALID && AWREADY && (AWLOCK == `AXI_ALOCK_EXCL) && + ExclAwMatch) + begin + ExclReadAddr[ExclAwId] <= 1'b0; // reset exclusive address flag for AWID + ExclReadData[ExclAwId] <= 1'b0; // reset exclusive read data flag for AWID + end + // completion of exclusive read data transaction + if ((RVALID && RREADY && RLAST && ExclReadAddr[ExclRId] && + ExclRMatch) && + // check the read CAM that this is part of an exclusive transfer + RBurstCam[RidMatch][EXCL] + ) + ExclReadData[ExclRId] <= 1'b1; // set exclusive read data flag for RID + end // else: !if(!`AXI_AUX_RSTn) + end // block: p_ExclCtrlSeq + + + // INDEX: - Lock State Machine + // ===== + // The state machine transitions when address valid + always @( ARLOCK or ARNew or + AWLOCK or AWNew or + LockState) + begin : p_LockStateNextComb + case (LockState) + `AXI_AUX_ST_UNLOCKED : + if ((ARNew & (ARLOCK == `AXI_ALOCK_LOCKED)) || + (AWNew & (AWLOCK == `AXI_ALOCK_LOCKED))) + LockStateNext = `AXI_AUX_ST_LOCKED; + else + LockStateNext = `AXI_AUX_ST_UNLOCKED; + + `AXI_AUX_ST_LOCKED : + if ((ARNew & (ARLOCK != `AXI_ALOCK_LOCKED)) || + (AWNew & (AWLOCK != `AXI_ALOCK_LOCKED))) + LockStateNext = `AXI_AUX_ST_LOCK_LAST; + else + LockStateNext = `AXI_AUX_ST_LOCKED; + + `AXI_AUX_ST_LOCK_LAST : + if ((ARNew & (ARLOCK == `AXI_ALOCK_LOCKED)) || + (AWNew & (AWLOCK == `AXI_ALOCK_LOCKED))) + LockStateNext = `AXI_AUX_ST_LOCKED; + + else if ((ARNew & (ARLOCK != `AXI_ALOCK_LOCKED)) || + (AWNew & (AWLOCK != `AXI_ALOCK_LOCKED))) + LockStateNext = `AXI_AUX_ST_UNLOCKED; + else + LockStateNext = `AXI_AUX_ST_LOCK_LAST; + + `AXI_AUX_ST_NOT_USED : LockStateNext = 2'bXX; + // Unreachable encoding, so X assigned for synthesis don't-care + + default : LockStateNext = 2'bXX; // X-propagation + endcase // case(LockState) + end // always p_LockStateNextComb + + + // INDEX: - Lock State Register + // ===== + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_LockStateSeq + if (!`AXI_AUX_RSTn) + begin + LockState <= `AXI_AUX_ST_UNLOCKED; + LockId <= {ID_WIDTH{1'b0}}; + LockCache <= 4'b0000; + LockProt <= 3'b000; + LockAddr <= {ADDR_WIDTH{1'b0}}; + end + else + begin + LockState <= LockStateNext; + LockId <= LockIdNext; + LockCache <= LockCacheNext; + LockProt <= LockProtNext; + LockAddr <= LockAddrNext; + end + end + + + // INDEX: - Lock Property Logic + // ===== + + // registering write/read ready/valid values + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_ValidReadyReg + if (!`AXI_AUX_RSTn) + begin + PrevAWVALID <= 1'b0; + PrevAWREADY <= 1'b0; + PrevARVALID <= 1'b0; + PrevARREADY <= 1'b0; + end + else + begin + PrevAWVALID <= AWVALID; + PrevAWREADY <= AWREADY; + PrevARVALID <= ARVALID; + PrevARREADY <= ARREADY; + end + end + + // AWNew=1 for the first cycle valid of a write address + assign AWNew = (AWVALID & ~PrevAWVALID) | + (AWVALID & PrevAWVALID & PrevAWREADY); + + // ARNew=1 for the first cycle valid of a read address + assign ARNew = (ARVALID & ~PrevARVALID) | + (ARVALID & PrevARVALID & PrevARREADY); + + // AWLockNew=1 for the first cycle of the initial locking write address + // valid for a locked sequence + assign AWLockNew = ( + (LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST) + ) & AWNew & (AWLOCK == `AXI_ALOCK_LOCKED); + + // ARLockNew=1 for the first cycle of the initial locking read address + // valid for a locked sequence + assign ARLockNew = ( + (LockState == `AXI_AUX_ST_UNLOCKED) || + (LockState == `AXI_AUX_ST_LOCK_LAST) + ) & ARNew & (ARLOCK == `AXI_ALOCK_LOCKED); + + // AWLockLastNew=1 for the first cycle of the unlocking write address + // valid for a locked sequence + assign AWLockLastNew = (LockState == `AXI_AUX_ST_LOCKED) & + AWNew & (AWLOCK != `AXI_ALOCK_LOCKED); + + // ARLockLastNew=1 for the first cycle of the unlocking read address + // valid for a locked sequence + assign ARLockLastNew = (LockState == `AXI_AUX_ST_LOCKED) & + ARNew & (ARLOCK != `AXI_ALOCK_LOCKED); + + + // Store the ID of the first locked transfer + always @(AWLockNew or ARLockNew or + LockId or AWID or ARID) + begin : p_LockIdNextComb + case ({ARLockNew,AWLockNew}) + 2'b00 : LockIdNext = LockId; // No new locked burst + 2'b01 : LockIdNext = AWID; // New locked write burst + 2'b10 : LockIdNext = ARID; // New locked read burst + 2'b11 : LockIdNext = AWID; // Both new locked write and read bursts + default : LockIdNext = {ID_WIDTH{1'bx}}; // X propagation + endcase + end // p_LockIdNextComb + + // Store the AxCACHE of the first locked transfer + always @(AWLockNew or ARLockNew or + LockCache or AWCACHE or ARCACHE) + begin : p_LockCacheNextComb + case ({ARLockNew,AWLockNew}) + 2'b00 : LockCacheNext = LockCache;// No new locked burst + 2'b01 : LockCacheNext = AWCACHE; // New locked write burst + 2'b10 : LockCacheNext = ARCACHE; // New locked read burst + 2'b11 : LockCacheNext = AWCACHE; // Both new locked write and read bursts + default : LockCacheNext = 4'bxxxx; // X propagation + endcase + end // p_LockCacheNextComb + + + // Store the AxPROT of the first locked transfer + always @(AWLockNew or ARLockNew or + LockProt or AWPROT or ARPROT) + begin : p_LockProtNextComb + case ({ARLockNew,AWLockNew}) + 2'b00 : LockProtNext = LockProt; // No new locked burst + 2'b01 : LockProtNext = AWPROT; // New locked write burst + 2'b10 : LockProtNext = ARPROT; // New locked read burst + 2'b11 : LockProtNext = AWPROT; // Both new locked write and read bursts + default : LockProtNext = 3'bxxx; // X propagation + endcase + end // p_LockProtNextComb + + // Store the AxADDR of the first locked transfer + always @(AWLockNew or ARLockNew or + LockAddr or AWADDR or ARADDR) + begin : p_LockAddrNextComb + case ({ARLockNew,AWLockNew}) + 2'b00 : LockAddrNext = LockAddr; // No new locked burst + 2'b01 : LockAddrNext = AWADDR; // New locked write burst + 2'b10 : LockAddrNext = ARADDR; // New locked read burst + 2'b11 : LockAddrNext = AWADDR; // Both new locked write and read bursts + default : LockAddrNext = {ADDR_WIDTH{1'bX}}; // X propagation + endcase + end // p_LockAddrNextComb + + +//------------------------------------------------------------------------------ +// INDEX: 4) Content addressable memories (CAMs) +//------------------------------------------------------------------------------ + + + // INDEX: - Read CAMSs (CAM+Shift) + // ===== + // New entries are added at the end of the CAM. + // Elements may be removed from any location in the CAM, determined by the + // first matching RID. When an element is removed, remaining elements + // with a higher index are shifted down to fill the empty space. + + // Read CAMs store all outstanding addresses for read transactions + assign RPush = ARVALID & ARREADY; // Push on address handshake + assign RPop = RVALID & RREADY & RLAST; // Pop on last handshake + + // Flag when there are no outstanding read transactions + assign nROutstanding = (RIndex == 1); + + // Find the index of the first item in the CAM that matches the current RID + // (Note that RIdCamDelta is used to determine when RIdCam has changed) + always @(RID or RIndex or RIdCamDelta) + begin : p_RidMatch + integer i; // loop counter + RidMatch = 0; + for (i=MAXRBURSTS; i>0; i=i-1) + if ((i < RIndex) && (RID == RBurstCam[i][IDHI:IDLO])) + RidMatch = i; + end + + // Update the flags indicating if RBurstCam contains locked/unlocked + // transactions + // (Note that RIdCamDelta is used to determine when RIdCam has changed) + always @(RIndex or RIdCamDelta) + begin : p_TxxRcamUpdate + integer i; // loop counter + UnlockedInRCam = 1'b0; + LockedInRCam = 1'b0; + for (i=MAXRBURSTS; i>0; i=i-1) + begin + if (i < RIndex) + begin + if (RBurstCam[i][LOCKED]) + LockedInRCam = 1'b1; + else + UnlockedInRCam = 1'b1; + end + end + end + + // Combine cam flags with current bus state to drive the flags + // indicating which types of lock read transactions are present + // on the bus (if any) + assign LockedRead = LockedInRCam || + (ARVALID && (ARLOCK == `AXI_ALOCK_LOCKED)); + assign UnlockedRead = UnlockedInRCam || + (ARVALID && (ARLOCK != `AXI_ALOCK_LOCKED)); + + // Calculate the index of the next free element in the CAM + always @(RIndex or RPop or RPush) + begin : p_RIndexNextComb + case ({RPush,RPop}) + 2'b00 : RIndexNext = RIndex; // no push, no pop + 2'b01 : RIndexNext = RIndex - 1; // pop, no push + 2'b10 : RIndexNext = RIndex + 1; // push, no pop + 2'b11 : RIndexNext = RIndex; // push and pop + default : RIndexNext = 'bX; // X-propagation + endcase + end + // + // RIndex Register + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_RIndexSeq + if (!`AXI_AUX_RSTn) + RIndex <= 1; + else + RIndex <= RIndexNext; + end + // + // CAM Implementation + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_ReadCam + reg [RBURSTMAX:0] Burst; // temporary store for burst data structure + if (!`AXI_AUX_RSTn) + begin : p_ReadCamReset + integer i; // loop counter + // Reset all the entries in the CAM + for (i=1; i<=MAXRBURSTS; i=i+1) + begin + RBurstCam[i] <= {RBURSTMAX+1{1'b0}}; + RCountCam[i] <= 5'h0; + RIdCamDelta <= 1'b0; + end + end + else + + begin + + // Pop item from the CAM, at location determined by RidMatch + if (RPop) + begin : p_ReadCamPop + integer i; // loop counter + // Delete item by shifting remaining items + for (i=1; i= RidMatch) + begin + RBurstCam[i] <= RBurstCam[i+1]; + RCountCam[i] <= RCountCam[i+1]; + RIdCamDelta <= ~RIdCamDelta; + end + end + else + // if not last data item, increment beat count + if (RVALID & RREADY) + RCountCam[RidMatch] <= RCountCam[RidMatch] + 5'h01; + + Burst[ADDRHI:ADDRLO] = ARADDR[ADDRHI:ADDRLO]; + Burst[EXCL] = (ARLOCK == `AXI_ALOCK_EXCL); + Burst[LOCKED] = (ARLOCK == `AXI_ALOCK_LOCKED); + Burst[BURSTHI:BURSTLO] = ARBURST; + Burst[ALENHI:ALENLO] = ARLEN; + Burst[ASIZEHI:ASIZELO] = ARSIZE; + Burst[IDHI:IDLO] = ARID; + + // Push item at end of the CAM + // Note that the value of the final index in the CAM is depends on + // whether another item has been popped + if (RPush) + begin + if (RPop) + begin + RBurstCam[RIndex-1] <= Burst; + RCountCam[RIndex-1] <= 5'h00; + end + else + begin + RBurstCam[RIndex] <= Burst; + RCountCam[RIndex] <= 5'h00; + end // else: !if(RPop) + RIdCamDelta <= ~RIdCamDelta; + end // if (RPush) + end // else: if(!`AXI_AUX_RSTn) + end // always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + + + // INDEX: - Write CAMs (CAM+Shift) + // ===== + // New entries are added at the end of the CAM. + // Elements may be removed from any location in the CAM, determined by the + // first matching WID and/or BID. When an element is removed, remaining + // elements with a higher index are shifted down to fill the empty space. + + + // Write bursts stored in single structure for checking when complete. + // This avoids the problem of early write data. + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_WriteCam + reg [WBURSTMAX:0] Burst; // temporary store for burst data structure + integer i; // loop counter + if (!`AXI_AUX_RSTn) + begin : p_WriteCamReset + for (i=1; i<=MAXWBURSTS; i=i+1) + begin + WBurstCam[i] = {WBURSTMAX+1{1'b0}}; // initialise to zero on reset + WCountCam[i] = 5'b0; // initialise beat counters to zero + WLastCam[i] = 1'b0; + WAddrCam[i] = 1'b0; + BRespCam[i] = 1'b0; + end + WIndex = 1; + AidMatch = 1; + BidMatch = 1; + WidMatch = 1; + Burst = {WBURSTMAX+1{1'b0}}; + AWDataNumError <= 1'b0; + WDataNumError <= 1'b0; + WDataOrderError <= 1'b0; + BrespError <= 1'b0; + BrespExokError <= 1'b0; + AWStrbError <= 1'b0; + BStrbError <= 1'b0; + BrespLeadingRec <= 1'b0; + nWAddrTrans <= 1'b1; + UnlockedInWCam <= 1'b0; + LockedInWCam <= 1'b0; + FlagUNInWCam <= 1'b0; + FlagLOInWCam <= 1'b0; + FlagLLInWCam <= 1'b0; + end + else + begin + // default is no errors + AWDataNumError <= 1'b0; + WDataNumError <= 1'b0; + WDataOrderError <= 1'b0; + BrespError <= 1'b0; + BrespExokError <= 1'b0; + AWStrbError <= 1'b0; + BStrbError <= 1'b0; + BrespLeadingRec <= 1'b0; + + // ----------------------------------------------------------------------- + // Valid write response + if (BVALID) + begin + + // Find matching burst + begin : p_WriteCamMatchB + + BidMatch = WIndex; // default is no match + for (i=MAXWBURSTS; i>0; i=i-1) + if (i < WIndex) // only consider valid entries in WBurstCam + begin + Burst = WBurstCam[i]; + if (BID == Burst[IDHI:IDLO] && // BID matches, and + ~BRespCam[i]) // write response not already transferred + BidMatch = i; + end + end // p_WriteCamMatchB + + Burst = WBurstCam[BidMatch]; // set temporary burst signal + + BRespCam[BidMatch] = BREADY; // record if write response completed + + + // Check that BID matches outstanding WID or AWID + if (~(BidMatch < WIndex)) + BrespError <= 1'b1; // trigger AXI_ERRS_BRESP + + // The following checks are only performed if the write response matches + // an existing burst + else begin + + // Check all write data in burst is complete + // Note: this test must occur before the WLastCam is updated + if (~WLastCam[BidMatch]) // last data not received + BrespError <= 1'b1; // trigger AXI_ERRS_BRESP + + // Check for EXOKAY response to non-exclusive transaction + if (Burst[EXCL] == 1'b0 && BRESP == `AXI_RESP_EXOKAY) + BrespExokError <= 1'b1; + + // Check if a write address has not been received and + // flag that this not recommended + // This must be done before the CAMs are popped when the + // the address has been received + if (!WAddrCam[BidMatch]) + BrespLeadingRec <= 1'b1; + + // Write response handshake completes burst when write address has + // already been received, and triggers protocol checking + if (BREADY & WAddrCam[BidMatch]) + begin : p_WriteCamPopB + // Check WSTRB + BStrbError <= CheckBurst(WBurstCam[BidMatch], WCountCam[BidMatch]); + + // pop completed burst from CAM + for (i = 1; i < MAXWBURSTS; i = i+1) + begin + if (i >= BidMatch) // only shift items after popped burst + begin + WBurstCam[i] = WBurstCam[i+1]; + WCountCam[i] = WCountCam[i+1]; + WLastCam[i] = WLastCam[i+1]; + WAddrCam[i] = WAddrCam[i+1]; + BRespCam[i] = BRespCam[i+1]; + end + end + + WIndex = WIndex - 1; // decrement index + + // Reset flags on new empty element + WBurstCam[WIndex] = {WBURSTMAX+1{1'b0}}; + WCountCam[WIndex] = 5'b0; + WLastCam[WIndex] = 1'b0; + WAddrCam[WIndex] = 1'b0; + BRespCam[WIndex] = 1'b0; + + end // if (BREADY & WAddrCam[BidMatch]) + + end // else !(~(BidMatch < WIndex)) + end // if (BVALID) + + // ----------------------------------------------------------------------- + // Valid write data + if (WVALID) + begin : p_WriteCamWValid + + // find matching burst in progress + WidMatch = WIndex; // default - no match + for (i = MAXWBURSTS; i > 0; i = i-1) + if (i < WIndex) // only consider valid entries in WBurstCam + begin + Burst = WBurstCam[i]; + if (WID == Burst[IDHI:IDLO] && // ID matches + ~WLastCam[i]) // not already received last data item + WidMatch = i; + end + + Burst = WBurstCam[WidMatch]; // temp store for 2-D burst lookup + + // if last data item or correct number of data items received already, + // check number of data items and WLAST against AWLEN. + // WCountCam hasn't yet incremented so can be compared with AWLEN + if ( WAddrCam[WidMatch] & // Only perform test if address is known + ( (WLAST & (WCountCam[WidMatch] != {1'b0,Burst[ALENHI:ALENLO]})) | + (~WLAST & (WCountCam[WidMatch] == {1'b0,Burst[ALENHI:ALENLO]})) + ) + ) + WDataNumError <= 1'b1; + + // if 1st data item, check that earlier bursts have all got 1st data + // item to enforce the AXI_ERRM_WDATA_ORDER protocol rule + if (WCountCam[WidMatch] == 5'b0) + begin + for (i = 1; i <= MAXWBURSTS; i = i+1) + if (i < WidMatch) + if (WCountCam[i] == 0) + WDataOrderError <= 1'b1; + end + + // need to use full case statement to occupy WSTRB as in Verilog the + // bit slice range must be bounded by constant expressions + case (WCountCam[WidMatch]) + 5'h0 : Burst[STRB1HI:STRB1LO] = WSTRB; + 5'h1 : Burst[STRB2HI:STRB2LO] = WSTRB; + 5'h2 : Burst[STRB3HI:STRB3LO] = WSTRB; + 5'h3 : Burst[STRB4HI:STRB4LO] = WSTRB; + 5'h4 : Burst[STRB5HI:STRB5LO] = WSTRB; + 5'h5 : Burst[STRB6HI:STRB6LO] = WSTRB; + 5'h6 : Burst[STRB7HI:STRB7LO] = WSTRB; + 5'h7 : Burst[STRB8HI:STRB8LO] = WSTRB; + 5'h8 : Burst[STRB9HI:STRB9LO] = WSTRB; + 5'h9 : Burst[STRB10HI:STRB10LO] = WSTRB; + 5'hA : Burst[STRB11HI:STRB11LO] = WSTRB; + 5'hB : Burst[STRB12HI:STRB12LO] = WSTRB; + 5'hC : Burst[STRB13HI:STRB13LO] = WSTRB; + 5'hD : Burst[STRB14HI:STRB14LO] = WSTRB; + 5'hE : Burst[STRB15HI:STRB15LO] = WSTRB; + 5'hF : Burst[STRB16HI:STRB16LO] = WSTRB; + default : Burst[STRB16HI:STRB16LO] = {STRB_WIDTH{1'bx}}; + endcase + + // Store the WID in the CAM + Burst[IDHI:IDLO] = WID; // record ID in case address not yet received + WBurstCam[WidMatch] = Burst; // copy back from temp store + + // when write data transfer completes, determine if last + WLastCam[WidMatch] = WLAST & WREADY; // record whether last data completed + + // When transfer completes, increment the count + WCountCam[WidMatch] = + WREADY ? WCountCam[WidMatch] + 5'b00001: // inc count + WCountCam[WidMatch]; + + + if (WidMatch == WIndex) // if new burst, increment CAM index + WIndex = WIndex + 1; + + end // if (WVALID) + + // ----------------------------------------------------------------------- + // Valid write address + if (AWVALID) + begin + + // find matching burst in progress + begin : p_WriteCamMatchAw + + AidMatch = WIndex; // assume no match + + for (i = MAXWBURSTS; i > 0; i = i-1) + if (i < WIndex) // only consider valid entries in WBurstCam + begin + Burst = WBurstCam[i]; + if (AWID == Burst[IDHI:IDLO] && // AWID matches, and + ~WAddrCam[i]) // write address not already transferred + AidMatch = i; + end + end // p_WriteCamMatchAw + + Burst = WBurstCam[AidMatch]; + + Burst[ADDRHI:ADDRLO] = AWADDR[ADDRHI:ADDRLO]; + Burst[EXCL] = AWLOCK[0]; + Burst[LOCKED] = (AWLOCK == `AXI_ALOCK_LOCKED); + Burst[BURSTHI:BURSTLO] = AWBURST; + Burst[ALENHI:ALENLO] = AWLEN; + Burst[ASIZEHI:ASIZELO] = AWSIZE; + Burst[IDHI:IDLO] = AWID; + + WBurstCam[AidMatch] = Burst; // copy back from temp store + + WAddrCam[AidMatch] = AWREADY; // record if write address completed + + // assert protocol error flag if address received after leading write + // data and: + // - WLAST was asserted when the beat count is less than AWLEN + // - WLAST was not asserted when the beat count is equal to AWLEN + // - the beat count is greater than AWLEN + if ((WLastCam[AidMatch] & + (({1'b0, Burst[ALENHI:ALENLO]} + 5'b00001) > WCountCam[AidMatch])) || + (~WLastCam[AidMatch] & + (({1'b0, Burst[ALENHI:ALENLO]} + 5'b00001) == WCountCam[AidMatch])) || + (({1'b0, Burst[ALENHI:ALENLO]} + 5'b00001) < WCountCam[AidMatch])) + AWDataNumError <= 1'b1; + + // Check that earlier bursts have all got address to enforce the + // AXI_ERRM_WDATA_ORDER protocol rule + begin : p_WriteCamWdataOrder + + for (i = 1; i <= MAXWBURSTS; i=i+1) + begin + if (i < AidMatch) // check all earlier bursts + if (WAddrCam[i] != 1'b1) // address not yet received + WDataOrderError <= 1'b1; // trigger assertion + end + end // p_WriteCamWdataOrder + + // If new burst, increment CAM index + if (AidMatch == WIndex) + WIndex = WIndex + 1; + + // Write address handshake completes burst when write response has + // already been received, and triggers protocol checking + else if (AWREADY & BRespCam[AidMatch]) + begin : p_WriteCamPopAw + // Check WSTRB + AWStrbError <= CheckBurst(WBurstCam[AidMatch], WCountCam[AidMatch]); + + // pop completed burst from CAM + for (i = 1; i < MAXWBURSTS; i = i+1) + if (i >= AidMatch) // only shift items after popped burst + begin + WBurstCam[i] = WBurstCam[i+1]; + WCountCam[i] = WCountCam[i+1]; + WLastCam[i] = WLastCam[i+1]; + WAddrCam[i] = WAddrCam[i+1]; + BRespCam[i] = BRespCam[i+1]; + end + + WIndex = WIndex - 1; // decrement index + + // Reset flags on new empty element + WBurstCam[WIndex] = {WBURSTMAX+1{1'b0}}; + WCountCam[WIndex] = 5'b0; + WLastCam[WIndex] = 1'b0; + WAddrCam[WIndex] = 1'b0; + BRespCam[WIndex] = 1'b0; + + end // if (AWREADY & BRespCam[AidMatch]) + + end // new write address + + // Update all write transactions with the coincident transaction info + // given by the locked/unlocked flags and the lock state of the + // current cycle + for (i = 1; i <= MAXWBURSTS; i = i+1) + begin + if (i < WIndex) // only consider valid entries in WBurstCam + begin + case (LockStateNext) + `AXI_AUX_ST_UNLOCKED : + begin + if (UnlockedRead | UnlockedWrite) + WBurstCam[i][FLAGUN] = 1'b1; + if (LockedRead | LockedWrite) + WBurstCam[i][FLAGLO] = 1'b1; + end + `AXI_AUX_ST_LOCKED : + begin + if (UnlockedRead | UnlockedWrite) + WBurstCam[i][FLAGUN] = 1'b1; + if (LockedRead | LockedWrite) + WBurstCam[i][FLAGLO] = 1'b1; + end + `AXI_AUX_ST_LOCK_LAST : + begin + if (UnlockedRead | UnlockedWrite) + WBurstCam[i][FLAGLL] = 1'b1; + if (LockedRead | LockedWrite) + WBurstCam[i][FLAGLO] = 1'b1; + end + `AXI_AUX_ST_NOT_USED : + ; // Unreachable, don't-care + default : ; // Unreachable, don't-care + endcase // case (LockState) + end + end + + // Check for an empty WAddrCam, clearing the nWAddrTrans flag + // if any write addresses are present + // Update the flags indicating if WBurstCam contains locked/unlocked + // transactions and bus state flags + nWAddrTrans <= 1'b1; + UnlockedInWCam <= 1'b0; + LockedInWCam <= 1'b0; + FlagUNInWCam <= 1'b0; + FlagLOInWCam <= 1'b0; + FlagLLInWCam <= 1'b0; + for (i = 1; i <= MAXWBURSTS; i = i+1) + begin + if (i < WIndex) // only consider valid entries in WBurstCam + begin + if (WBurstCam[i][FLAGUN]) + FlagUNInWCam <= 1'b1; + if (WBurstCam[i][FLAGLO]) + FlagLOInWCam <= 1'b1; + if (WBurstCam[i][FLAGLL]) + FlagLLInWCam <= 1'b1; + if (WAddrCam[i]) + begin + nWAddrTrans <= 1'b0; + if (WBurstCam[i][LOCKED]) + LockedInWCam <= 1'b1; + else + UnlockedInWCam <= 1'b1; + end + end + end + + end // else: !if(!`AXI_AUX_RSTn) + end // always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + + // Combine cam flags with current bus state to drive the flags + // indicating which types of lock write transactions are present + // on the bus (if any) + assign LockedWrite = LockedInWCam || + (AWVALID && (AWLOCK == `AXI_ALOCK_LOCKED)); + assign UnlockedWrite = UnlockedInWCam || + (AWVALID && (AWLOCK != `AXI_ALOCK_LOCKED)); + + assign StrbError = AWStrbError | BStrbError; + + assign WriteDataNumError = AWDataNumError | WDataNumError; + + + // INDEX: - Write Depth array + // ===== + // Array monitors interleaved write data + + // Lookup table for IDs used by the exclusive access monitor + // Each location in the table has a valid flag to indicate if the ID is in use + always @(negedge `AXI_AUX_RSTn or posedge `AXI_AUX_CLK) + begin : p_WdepthIdSeq + integer i; // loop counter + if (!`AXI_AUX_RSTn) + begin + WdepthIdValid <= {WDEPTH+1{1'b0}}; + WdepthIdDelta <= 1'b0; + for (i = 0; i <= WDEPTH; i = i + 1) + begin + WdepthId[i] <= {ID_WIDTH{1'b0}}; + end + end + else // clk edge + begin + // write transfer + if (WVALID && WREADY && + !WdepthIdFull) + begin + WdepthId[WdepthIdWrPtr] <= WID; + WdepthIdValid[WdepthIdWrPtr] <= !WLAST; + WdepthIdDelta <= ~WdepthIdDelta; + end + end // else: !if(!`AXI_AUX_RSTn) + end // block: p_WdepthIdSeq + + // Lookup table is full when all valid bits are set + assign WdepthIdFull = &WdepthIdValid; + + // New IDs are written to the highest location + // that does not have the valid flag set + always @(WdepthIdValid or WdepthIdDelta) + begin : p_WdepthIdFreePtrComb + integer i; // loop counter + WdepthIdFreePtr = 0; + for (i = 0; i <= WDEPTH; i = i + 1) + begin + if (WdepthIdValid[i] == 1'b0) + begin + WdepthIdFreePtr = i; + end + end + end // p_WdepthIdFreePtrComb + + // If the ID is already being monitored then reuse the location + // New IDs are written to the highest location + // that does not have the valid flag set + assign WdepthIdWrPtr = WdepthWMatch ? WdepthWId : WdepthIdFreePtr; + + // Write address ID comparator + always @(WVALID or WID or WdepthIdValid or WdepthIdDelta) + begin : p_WdepthWMatchComb + integer i; // loop counter + WdepthWMatch = 1'b0; + WdepthWId = {WDEPTH+1{1'b0}}; + if (WVALID) + begin + for (i = 0; i <= WDEPTH; i = i + 1) + begin + if (WdepthIdValid[i] && (WID == WdepthId[i])) + begin + WdepthWMatch = 1'b1; + WdepthWId = i; + end + end + end + end // p_WdepthWMatchComb + + // Sum the bits from the WidInUse register to give the current write depth + always @(WdepthIdValid or WdepthWMatch or WVALID) + begin : p_WidDepthComb + integer id; // loop counter + WidDepth = 0; + for (id = 0; id <= WDEPTH; id = id + 1) + begin + if (WdepthIdValid[id] == 1'b1) + begin + WidDepth = 1 + WidDepth; + end + end + // Add one if a new WID is in use + if (WVALID && !WdepthWMatch) + begin + WidDepth = WidDepth + 1'b1; + end + end // p_WidDepthComb + + +//------------------------------------------------------------------------------ +// INDEX: 5) Verilog Functions +//------------------------------------------------------------------------------ + + + // INDEX: - CheckBurst + // ===== + // Inputs: Burst (burst data structure) + // Count (number of data items) + // Returns: High is any of the write strobes are illegal + // Calls CheckStrb to test each WSTRB value. + //------------------------------------------------------------------------------ + function CheckBurst; + input [WBURSTMAX:0] Burst; // burst vector + input [5:0] Count; // number of beats in the burst + integer loop; // general loop counter + integer NumBytes; // number of bytes in the burst + reg [6:0] StartAddr; // start address of burst + reg [6:0] StrbAddr; // address used to check WSTRB + reg [2:0] StrbSize; // size used to check WSTRB + reg [3:0] StrbLen; // length used to check WSTRB + reg [STRB_MAX:0] Strb; // WSTRB to be checked + reg [9:0] WrapMaskWide; // address mask for wrapping bursts + reg [6:0] WrapMask; // relevant bits WrapMaskWide + begin + + StartAddr = Burst[ADDRHI:ADDRLO]; + StrbAddr = StartAddr; // incrementing address initialises to start addr + StrbSize = Burst[ASIZEHI:ASIZELO]; + StrbLen = Burst[ALENHI:ALENLO]; + CheckBurst = 1'b0; + + // Initialize to avoid latch warnings (not really latches as they are set in loop) + Strb = {STRB_WIDTH{1'bX}}; + WrapMask = {7{1'bX}}; + WrapMaskWide = {10{1'bX}}; + + // determine the number of bytes in the burst for wrapping purposes + NumBytes = (StrbLen + 1) << StrbSize; + + // Check the strobe for each write data transfer + for (loop=1; loop<=16; loop=loop+1) + begin + if (loop <= Count) // Only consider entries up to burst length + begin + + // Need to use full case statement to index WSTRB as in Verilog the + // bit slice range must be bounded by constant expressions + case (loop) + 1 : Strb = Burst[STRB1HI:STRB1LO]; + 2 : Strb = Burst[STRB2HI:STRB2LO]; + 3 : Strb = Burst[STRB3HI:STRB3LO]; + 4 : Strb = Burst[STRB4HI:STRB4LO]; + 5 : Strb = Burst[STRB5HI:STRB5LO]; + 6 : Strb = Burst[STRB6HI:STRB6LO]; + 7 : Strb = Burst[STRB7HI:STRB7LO]; + 8 : Strb = Burst[STRB8HI:STRB8LO]; + 9 : Strb = Burst[STRB9HI:STRB9LO]; + 10 : Strb = Burst[STRB10HI:STRB10LO]; + 11 : Strb = Burst[STRB11HI:STRB11LO]; + 12 : Strb = Burst[STRB12HI:STRB12LO]; + 13 : Strb = Burst[STRB13HI:STRB13LO]; + 14 : Strb = Burst[STRB14HI:STRB14LO]; + 15 : Strb = Burst[STRB15HI:STRB15LO]; + 16 : Strb = Burst[STRB16HI:STRB16LO]; + default : Strb = {STRB_WIDTH{1'bx}}; + endcase + + // returns high if any strobes are illegal + if (CheckStrb(StrbAddr, StrbSize, Strb)) + begin + CheckBurst = 1'b1; + end + + // ----------------------------------------------------------------------- + // Increment aligned StrbAddr + if (Burst[BURSTHI:BURSTLO] != `AXI_ABURST_FIXED) + // fixed bursts don't increment or align the address + begin + // align and increment address, + // Address is incremented from an aligned version + StrbAddr = StrbAddr & + (7'b111_1111 - (7'b000_0001 << StrbSize) + 7'b000_0001); + // align to size + StrbAddr = StrbAddr + (7'b000_0001 << StrbSize); // increment + end // if (Burst[BURSTHI:BURSTLO] != `AXI_ABURST_FIXED) + + // for wrapping bursts the top bits of the strobe address remain fixed + if (Burst[BURSTHI:BURSTLO] == `AXI_ABURST_WRAP) + begin + WrapMaskWide = (10'b11_1111_1111 - NumBytes + 10'b00_0000_0001); + // To wrap the address, need 10 bits + WrapMask = WrapMaskWide[6:0]; + // Only 7 bits of address are necessary to calculate strobe + StrbAddr = (StartAddr & WrapMask) | (StrbAddr & ~WrapMask); + // upper bits remain stable for wrapping bursts depending on the + // number of bytes in the burst + end + end // if (loop < Count) + end // for (loop=1; loop<=WDEPTH; loop=loop+1) + end + endfunction // CheckBurst + + + // INDEX: - CheckStrb + // ===== + function CheckStrb; + input [6:0] StrbAddr; + input [2:0] StrbSize; + input [STRB_MAX:0] Strb; + reg [STRB_MAX:0] StrbMask; + begin + + // The basic strobe for an aligned address + StrbMask = (STRB_1 << (STRB_1 << StrbSize)) - STRB_1; + + // Zero the unaligned byte lanes + // Note: the number of unaligned byte lanes is given by: + // (StrbAddr & ((1 << StrbSize) - 1)), i.e. the unaligned part of the + // address with respect to the transfer size + // + // Note! {{STRB_MAX{1'b0}}, 1'b1} gives 1 in the correct vector length + + StrbMask = StrbMask & // Mask off unaligned byte lanes + (StrbMask << // shift the strb mask left by + (StrbAddr & ((STRB_1 << StrbSize) - STRB_1)) + // the number of unaligned byte lanes + ); + + // Shift mask into correct byte lanes + // Note: (STRB_MAX << StrbSize) & STRB_MAX is used as a mask on the address + // to pick out the bits significant bits, with respect to the bus width and + // transfer size, for shifting the mask to the correct byte lanes. + StrbMask = StrbMask << (StrbAddr & ((STRB_MAX << StrbSize) & STRB_MAX)); + + // check for strobe error + CheckStrb = (|(Strb & ~StrbMask)); + + end + endfunction // CheckStrb + + + // INDEX: - ReadDataMask + // ===== + // Inputs: Burst (Burst data structure) + // Beat (Data beat number) + // Returns: Read data mask for valid byte lanes. + //------------------------------------------------------------------------------ + function [DATA_MAX:0] ReadDataMask; + input [STRB16HI:0] Burst; // burst vector + input [5:0] Beat; // beat number in the burst (0-15) + reg [11:0] bit_count; + reg [DATA_MAX+1:0] byte_mask; + begin + bit_count = ByteCount(Burst, Beat) << 3; + byte_mask = (1'b1 << bit_count) - 1; + // Result is the valid byte mask shifted by the calculated bit shift + ReadDataMask = byte_mask[DATA_MAX:0] << (ByteShift(Burst, Beat)*8); + end + endfunction // ReadDataMask + + + // INDEX: - ByteShift + // ===== + // Inputs: Burst (Burst data structure) + // Beat (Data beat number) + // Returns: Byte Shift for valid byte lanes. + //------------------------------------------------------------------------------ + function [DATA_MAX:0] ByteShift; + input [STRB16HI:0] Burst; // burst vector + input [5:0] Beat; // beat number in the burst (0-15) + reg [6:0] axaddr; + reg [2:0] axsize; + reg [3:0] axlen; + reg [1:0] axburst; + integer bus_data_bytes; + integer length; + integer unaligned_byte_shift; + integer beat_addr_inc; + integer addr_trans_bus; + integer addr_trans_bus_inc; + integer wrap_point; + integer transfer_byte_shift; + begin + axaddr = Burst[ADDRHI:ADDRLO]; + axsize = Burst[ASIZEHI:ASIZELO]; + axlen = Burst[ALENHI:ALENLO]; + axburst = Burst[BURSTHI:BURSTLO]; + + bus_data_bytes = STRB_WIDTH; + + length = axlen + 1; + + // Number of bytes that the data needs to be shifted when + // the address is unaligned + unaligned_byte_shift = + axaddr & // Byte address + ((1<>axsize; + + // The address may increment with each beat. The increment will be zero + // for a FIXED burst. + addr_trans_bus_inc = addr_trans_bus + beat_addr_inc; + + // Modify the byte shift for wrapping bursts + if (axburst == 2) + begin + // The upper address of the transfer before wrapping + wrap_point = length + (addr_trans_bus & ~(length - 1)); + // If adding the beat number to the transfer address causes it to + // pass the upper wrap address then wrap to the lower address. + if (addr_trans_bus_inc >= wrap_point) + begin + addr_trans_bus_inc = addr_trans_bus_inc - length; + end + end + + // Address calculation may exceed the number of transfers that can fit + // in the data bus for INCR bursts. So the calculation is truncated to + // make the byte shift wrap round to zero. + addr_trans_bus_inc = addr_trans_bus_inc & ((bus_data_bytes-1)>>axsize); + + // Number of bytes that the data needs to be shifted when + // the transfer size is less than the data bus width + transfer_byte_shift = (1<11111100) so casting to unsigned + $display("value of reqA:%0b",reqA); +end +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/string_literal_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/string_literal_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..79c3ab6e3f7a69c9e2ef5e1d7a1a7e1dbfd59951 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/string_literal_p.sv @@ -0,0 +1,13 @@ +module string_literal_p; + + initial begin + string strValue = "Hello, World!"; + integer intValue; + + // Try to assign the string value to an integer + intValue = int'(strValue);//type casting from string to integer + $display("String Value: %s", strValue); + $display("Integer Value: %d", intValue); + end + +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/switch_cov_enum_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/switch_cov_enum_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..d27c3d286a875651292a998433d1d5d6fbae143e --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/switch_cov_enum_p.sv @@ -0,0 +1,16 @@ +module switch_issue; + typedef enum int { A, B, C, D, E, F, G, H} packet_type_t; + packet_type_t pkt_type; + + initial begin + pkt_type = A; + //void'(randomize(pkt_type)); + case (pkt_type) inside + A,D : $write("case 1 "); + B,C : $write("case 2 "); + [E:G] : $write("case 3 "); + default : $write("default "); + endcase // case (pkt_type) + $display(pkt_type.name); + end +endmodule diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/uninitialized_vars_in_constexp_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/uninitialized_vars_in_constexp_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..5745e27867b5c53da0f80a17bbe91f423ac4a58a --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/uninitialized_vars_in_constexp_p.sv @@ -0,0 +1,10 @@ +module uninitialized_vars_in_constexp_p; +int data; +const int unsigned my_const = 10; // This is a valid constant + +initial begin + data = my_const; + $display("data:%0d",data); +end + +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unreachable_code_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unreachable_code_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..a17afc81069277f1d5c14d15b8ef7a781a0f2fa4 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unreachable_code_p.sv @@ -0,0 +1,11 @@ +module unreachable_code_p; + +initial +begin + if (1'b1) begin + $display("The code is reachable");// Reachable code + end else begin + $display("The code is not reachable"); // unreachable code + end +end +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_field_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_field_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..2198564f326c3d1a0a9eab971299452379b9f1fc --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_field_p.sv @@ -0,0 +1,15 @@ + module unused_field_p; + + logic a; + //unused field now used + logic unused_signal; + + initial + begin + a=0; + $display("value of a:%0d",a); + unused_signal=1; + $display("value of unused_signal:%0d",unused_signal); + end + endmodule + \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_function_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_function_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..70b9a9748f76b816d900a09ea1641586765cabee --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_function_p.sv @@ -0,0 +1,17 @@ +module unused_function_p; + + initial begin + + x(); //function x used + y(); //function y used + + end +function void x; + //function definition +endfunction + +function void y; + //function definition +endfunction + +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_parameter_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_parameter_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..a5bca5613117988345d7e4f52655e78c9440e28e --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_parameter_p.sv @@ -0,0 +1,13 @@ +module unused_parameter_p #(parameter DATA_WIDTH = 8, ID_WIDTH = 32) (data, id); + //Used the parameters declared as DATA_WIDTH and ID_WIDTH + input bit [DATA_WIDTH-1: 0] data; + input bit [ID_WIDTH-1: 0] id; + + initial begin + // Display width values + $display("DATA_WIDTH = %0d, ID_WIDTH = %0d", DATA_WIDTH, ID_WIDTH); + + // Display variables + $display("data = %0d, id = %0d", data, id); + end +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_typedef_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_typedef_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..38e8a129eac6eae0b01acf3ff913d9ee0737d115 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_typedef_p.sv @@ -0,0 +1,20 @@ +//unused typedef +typedef enum bit [1:0] {RED,BLUE,GREEN,YELLOW} colours_1 ; +typedef enum bit {RD,WR} eight; + +module unused_typedef_p; + initial + begin + + eight a1;//used the typedef declared outside the module + colours_1 ch1; + + ch1 = RED; + $display("ch1:%0d",ch1); + + a1 = WR; + $display("a1:%0d",a1); + +end + +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_variable_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_variable_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..7f77c3046bb479208cec409a93b52eb664b06cdb --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/unused_variable_p.sv @@ -0,0 +1,14 @@ +module unused_variable_p; + + int a; + int b; + + initial + begin + //all variables are used + a=0; + $display("value of a:%0d",a); + b=1; + $display("value of b:%0d",b); + end + endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/upward_name_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/upward_name_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..91b6ec2d7945e66046581f9be8bf2bdb862875de --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/mike_pylint_issues/pass_test_cases/upward_name_p.sv @@ -0,0 +1,13 @@ +module upward_name_p; + +initial + begin:TB_INITIAL + reg signal; + end + +initial + begin + TB_INITIAL.signal = 0;//calling "signal" using the begin label "TB_INITIAL" + $display("value of signal:%0d",TB_INITIAL.signal); + end +endmodule \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_issue_110_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_issue_110_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..1064dfdbbeee741fe789671e370f328177ba366a --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_issue_110_f.sv @@ -0,0 +1,56 @@ + + module memory_data_integrity_check (); + logic write; // memory write + logic read; // memory read + logic wdata; // data written to memory + logic rdata; // data read from memory + logic addr; // memory address + bit reset_n; // active low reset + bit clk; + + timeunit 1ns; + timeprecision 100ps; + int mem_aarray[*]; // associative array to be used by property + wire mem_aaray_exists; // exists at specified address + initial forever #10 clk=!clk; + default clocking cb_clk @ (posedge clk); endclocking + assign mem_aarray_exists = mem_aarray.exists(addr); + + always@ (posedge clk) + if (reset_n==1'b0) mem_aarray.delete; // Clears AA elements + else if (write) mem_aarray[addr] = wdata; // store data + + + property p_read_after_write; + @(posedge clk) + (read && mem_aarray_exists) |-> mem_aarray[addr]==rdata; + endproperty : p_read_after_write + ap_read_after_write : assert property (p_read_after_write); + + property p_read_before_write; + @(posedge clk) + not (read && !mem_aarray_exists); + endproperty : p_read_before_write + ap_read_before_write : assert property (p_read_before_write); + + initial begin + + // Apply reset + reset_n = 0; + reset_n = 1; + + + addr = 4'h0; + read = 1; + write = 0; + wdata = 32'hA5A5A5A5; + + read = 0; + + addr = 4'h1; + write = 1; + wdata = 32'h12345678; + ##10; $finish; + end + + endmodule : memory_data_integrity_check diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_issue_128_uvm_sva_ex.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_issue_128_uvm_sva_ex.sv new file mode 100644 index 0000000000000000000000000000000000000000..3e794b2a024077a44898778340f77d76b8279534 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_issue_128_uvm_sva_ex.sv @@ -0,0 +1,40 @@ +import uvm_pkg::*; `include "uvm_macros.svh" +module uvm_sva_ex; // File ch4/asn_testuvm_sva_ex.sv + bit clk, a, b, c, req, ack; + parameter CLK_HPERIOD = 10; + string tID="UART "; + initial begin : clk_gen forever #CLK_HPERIOD clk <= !clk; end : clk_gen + default clocking def_cb @ (posedge clk); endclocking : def_cb + ap_LOW: assert property(a) else + `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_LOW); // Line 9 + ap_MEDIUM: assert property(a) else + `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_MEDIUM); // Line 11 + ap_HIGH: assert property(a) else + `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_HIGH); // Line 13 + ap_FULL: assert property(a) else + `uvm_info(tID,$sformatf("%m : error in a %b", a), UVM_FULL); // Line 15 + ap_test2: assert property(a) else + `uvm_error(tID,$sformatf("%m : error in a %b", a)); // Line 17 + ap_handshake0 : assert property ($rose(req) |=> ##[0:4] ack) else + $error(tID, $sformatf("%m req = %0h, ack=%0h", // Line 19 + $sampled(req), $sampled (ack))); + ap_handshake : assert property ($rose(req) |=> ##[0:4] ack) else + `uvm_error(tID, $sformatf("%m req = %0h, ack=%0h", // // Line 22 + $sampled(req), $sampled (ack))); + + + initial begin + + req = 0; + ack = 1; + a = 1; + #10;req = 1; + ack = 1; + a = 1; + + #100; + $finish + end + + +endmodule : uvm_sva_ex \ No newline at end of file diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_cg_arr_bin_default_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_cg_arr_bin_default_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..952b767f290da12ebf5b89364412721f10580497 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_cg_arr_bin_default_f.sv @@ -0,0 +1,17 @@ +class ex_c + bit [31:0] i; + + covergroup cg_with_arr_def; + coverpoint i { + bins b_zero = { 0 }; + bins b_small = { [1:100] }; + bins b_100s[5] = {200, 300, 400, 500, 600, + 700}; + bins b_large_vals = { [1001:$] }; + ignore_bins b_ignore = { [701:999] }; + bins others[] = default; + } + endgroup + +endclass : ex_c + diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_cnst_arr_method.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_cnst_arr_method.sv new file mode 100644 index 0000000000000000000000000000000000000000..8f66956b0f664f278199d98d04ba3d91df5e42fe --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_cnst_arr_method.sv @@ -0,0 +1,14 @@ +class bug_c; + rand bit num_list[32]; + rand int a; + + constraint cst_sum { + num_list.sum() == 1; + num_list.and() == 1; + num_list.xor() == 1; + num_list.product() == 1; + //num_list.sum() with (6'(item)) == 1; + //a > 1; + } +endclass : bug_c + diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_issue_37_2.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_issue_37_2.sv new file mode 100644 index 0000000000000000000000000000000000000000..29d2653c75ef0365f2fe8061ddac787eb1bbae95 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_issue_37_2.sv @@ -0,0 +1,43 @@ + + class distribution; + + // actually if we are not using ranges of values there is no diff between (:=) and (:/) operators + rand bit sel;// := + rand bit en;// :/ + + // but if we use ranges of values there we can recognize the diff + + rand bit [0:3] data1;//:= + rand bit [0:3] data1_bad;//:= + rand bit [0:3] data2;//:/ + + constraint one{ + sel dist {0:=10, 1:=90}; + en dist {0:/10, 1:/90}; + data1 dist {0:=10, [1:3]:=60}; + data1_bad dist {0:=10, [1:30]:=60}; + data2 dist {0:/10, [1:3]:/60}; + } + + endclass + + module tb(); + + distribution d; + + initial begin + d = new(); + + for(int i = 0; i < 10; i++) begin + if(d.randomize()) begin + end else begin + $display("randomization failed"); + end + #10 + $display("sel = %0d, en = %0d ", d.sel, d.en); + $display("data1 = %0d, data2 = %0d ", d.data1, d.data2); + + end + end + + endmodule diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_02_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_02_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..8e15d20e382dadfa01cdc8de4d89e939c8268737 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_02_f.sv @@ -0,0 +1,10 @@ +//---------------------------------------------------- +// SPDX-FileCopyrightText: Srinivasan Venkataramanan, +// AsFigo Technologies, UK +// SPDX-License-Identifier: MIT +//---------------------------------------------------- + + +interface af_sv_intf_bad (); +endinterface : af_sv_intf_bad + diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_08_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_08_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..cb57fdf0ae937e6e4b10f2e03d034c98e1720c1d --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_08_f.sv @@ -0,0 +1,15 @@ +//---------------------------------------------------- +// SPDX-FileCopyrightText: Srinivasan Venkataramanan, +// AsFigo Technologies, UK +// SPDX-License-Identifier: MIT +//---------------------------------------------------- + + +module cg_wrap_m; + bit var1; + + covergroup bad_group_name; + cp_good : coverpoint var1; + endgroup : bad_group_name +endmodule : cg_wrap_m + diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_18_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_18_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..8a98158f43a1d3172e8f708c3d81910f15ac3f76 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_18_f.sv @@ -0,0 +1,21 @@ +//---------------------------------------------------- +// SPDX-FileCopyrightText: Srinivasan Venkataramanan, +// AsFigo Technologies, UK +// SPDX-License-Identifier: MIT +//---------------------------------------------------- + + +module sva_m; + bit var1; + bit clk; + + property p_good_name; + var1; + endproperty : p_good_name + + // BAD label should have m_ as prefix for assume + wrong_label : assume property (@(posedge clk) p_good_name) + else $error ("Fail AB"); + +endmodule : sva_m + diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_23_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_23_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..f77a3aa4c000ec95afd80a321097eba97b13bc81 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_naming_23_f.sv @@ -0,0 +1,13 @@ +module test_new_m; + bit req,grnt; + bit clk; + + property p_req_cycle; + @(posedgeclk) $rose (req) |-> ##[1:3] grnt; + endproperty : p_req_cycle + + a_new : assert property ((@posedge clk) p_req_cycle); + else $error ("Fail"); + + +endmodule : test_new_m diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_proc_conc_in_fe_f.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_proc_conc_in_fe_f.sv new file mode 100644 index 0000000000000000000000000000000000000000..34922f55d5857ad61f579fac7d8545ea204a1b39 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_proc_conc_in_fe_f.sv @@ -0,0 +1,39 @@ + +module test; + +bit clk; +bit a,b; + +default clocking @(posedge clk); endclocking + +always #1 clk = ~clk; + +//----------------------// + property always_pp; + a |-> b; + endproperty + + //----------------------// + property forever_pp; + a |-> b; + endproperty + + //----------------------// + always @(posedge clk) begin + always_asrt: assert property(always_pp); + end + + //----------------------// + initial begin + forever @(posedge clk)begin + forever_asrt: assert property(forever_pp); + end + end + + //----------------------// + initial begin + #2 a=1; b=0; + #20 $finish; + end + +endmodule diff --git a/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_qual_1_p.sv b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_qual_1_p.sv new file mode 100644 index 0000000000000000000000000000000000000000..ca2caa3e8f988c58df1eceaf7dacc04e6ac30a20 --- /dev/null +++ b/snapshots/AsFigo_pyslint_pr140/sv_tests/test_sv_qual_1_p.sv @@ -0,0 +1,50 @@ +//---------------------------------------------------- +// SPDX-FileCopyrightText: Srinivasan Venkataramanan, +// AsFigo Technologies, UK +// SPDX-License-Identifier: MIT +//---------------------------------------------------- + + +module sv_qual (input bit clk, rst_n, + input [3:0] sig_4b, + output [7:0] o_sig_8b); + + bit var1; + + wire sample_w; + logic and_c, and_in_a, and_in_b; + + assign sample_w = 1'b0; + + always_comb begin : alw_c + and_c = and_in_a && and_in_b; + end : alw_c + + initial begin : init_blk + $timeformat (-9, 3, " ns", 5); + end : init_blk + + + // Sample one line comment + + sequence s_a_b; + @(posedge clk) and_in_a ##10 and_in_b; + endsequence : s_a_b + + property p_good_name; + var1 |=> s_a_b; + endproperty : p_good_name + + /* Multi-line comment + * Second line + * Third line + */ + + a_p_good_name : assert property (@(posedge clk) p_good_name) + else $error ("Fail AB"); + + m_oneh_inp : assume property (@(posedge clk) $onehot0 (sig_4b)); + c_inp : cover property (@(posedge clk) (sig_4b == 4'b0010)); + +endmodule : sv_qual + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/config/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/config/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e54d2de163a999974f515eb8f4ef92c5675c6cf7 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/config/Makefile @@ -0,0 +1,55 @@ +# Variables +PYTHON ?= python3.10 # Requires >= 3.10 + +# Configurations +CONFIG_MBUS_CSV ?= ${CONFIG_ROOT}/configs/${SOC_CONFIG}/config_main_bus.csv +CONFIG_PBUS_CSV ?= ${CONFIG_ROOT}/configs/${SOC_CONFIG}/config_peripheral_bus.csv +CONFIG_HBUS_CSV ?= ${CONFIG_ROOT}/configs/${SOC_CONFIG}/config_highperformance_bus.csv +# csv for system-level configuration +CONFIG_SYSTEM_CSV ?= ${CONFIG_ROOT}/configs/common/config_system.csv +# CSVs list +CONFIG_BUS_CSVS ?= ${CONFIG_MBUS_CSV} \ + ${CONFIG_PBUS_CSV} \ + ${CONFIG_HBUS_CSV} + +all: config_main_bus config_peripheral_bus config_highperformance_bus config_ld config_sw config_xilinx + +config_main_bus: OUTPUT_TCL_FILE = ${XILINX_ROOT}/ips/common/xlnx_main_crossbar/config.tcl +config_peripheral_bus: OUTPUT_TCL_FILE = ${XILINX_ROOT}/ips/common/xlnx_peripheral_crossbar/config.tcl +config_highperformance_bus: OUTPUT_TCL_FILE = ${XILINX_ROOT}/ips/hpc/xlnx_highperformance_crossbar/config.tcl +config_%_bus: CONFIG_BUS_CSV = ${CONFIG_ROOT}/configs/${SOC_CONFIG}/config_$*_bus.csv +config_%_bus: +config_%_bus: config_check + ${PYTHON} ${CONFIG_ROOT}/scripts/create_crossbar_config.py \ + ${CONFIG_SYSTEM_CSV} \ + ${CONFIG_BUS_CSV} \ + ${OUTPUT_TCL_FILE} + ${PYTHON} ${CONFIG_ROOT}/scripts/declare_and_concat_buses_rtl.py ${CONFIG_BUS_CSV} + ${PYTHON} ${CONFIG_ROOT}/scripts/declare_and_assign_clocks_rtl.py ${CONFIG_BUS_CSV} + + +OUTPUT_LD_FILE ?= ${SW_ROOT}/SoC/common/UninaSoC.ld +# Generate HAL configuration file +OUTPUT_HAL_CONF_FILE ?= ${SW_ROOT}/SoC/lib/uninasoc/inc/uninasoc_conf.h + +config_ld: config_check + ${PYTHON} ${CONFIG_ROOT}/scripts/create_linker_script.py \ + ${CONFIG_BUS_CSVS} \ + ${OUTPUT_LD_FILE} + @echo "[CONFIG] Output file is at ${OUTPUT_LD_FILE}" + + +config_check: + ${PYTHON} ${CONFIG_ROOT}/scripts/check_config.py ${CONFIG_SYSTEM_CSV} ${CONFIG_BUS_CSVS} + +# Update config Makefiles +OUTPUT_XILINX_MK_FILE ?= ${XILINX_ROOT}/make/config.mk +OUTPUT_SW_MK_FILE ?= $(SW_ROOT)/SoC/common/config.mk +config_xilinx: + ${CONFIG_ROOT}/scripts/config_xilinx.sh ${CONFIG_SYSTEM_CSV} ${CONFIG_BUS_CSVS} ${OUTPUT_XILINX_MK_FILE} + +config_sw: config_check + ${CONFIG_ROOT}/scripts/config_sw.sh ${CONFIG_SYSTEM_CSV} ${OUTPUT_SW_MK_FILE} + ${PYTHON} ${CONFIG_ROOT}/scripts/create_uninasoc_conf_header.py ${CONFIG_PBUS_CSV} ${OUTPUT_HAL_CONF_FILE} + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/config/README.md b/snapshots/HiSA-Team_Simply-V_pr166/config/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3b8e6f49d9dd190d3deb07489873fab1bcb7199e --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/config/README.md @@ -0,0 +1,144 @@ +# Configuration Generation Flow +This tree allows for the automatic generation of the AXI crossbar IP and linker script for software development. + +## Prerequisites and Tools versions +This tree has been verified with the following tools and versions +* Vivado 2022.2 - 2024.2 +* AXI Interconnect v2.1 +* Pyhton >= 3.10 +* Pandas >= 2.2.3 + +## Configuration file format +The input configuration files are CSV files. These files are under the configs directory structured as follows: +``` bash +configs +├── common # Config files shared between hpc and embedded +│ └── config_system.csv # System-level configurations +├── embedded # Config files for embedded +│ ├── config_main_bus.csv # Main bus config file +│ └── config_peripheral_bus.csv # Peripheral bus config file +└── hpc # Config files for hpc + ├── config_main_bus.csv # Main bus config file + └── config_peripheral_bus.csv # Peripheral bus config file +``` + +A configuration file can either refer to system-level options or to a specific bus. For now only main bus and peripheral bus are supported, **but file names must match those above**. + +In each file, each row of the file holds a property name and value pair. +Some properties are array, with elements separated by a white space " " character. + +The following table details the supported properties. + +### System Configuration + +> **IMPORTANT NOTE**: XLEN parameter will only affect main bus sizes. Other buses (such as the peripheral bus) will have a hardcoded DATA_WIDTH and ADDRESS_WIDTH value. + +| Name | Description | Values | Default +|-|-|-|-| +| CORE_SELECTOR | Select target RV core | CORE_PICORV32, CORE_CV32E40P, CORE_IBEX, CORE_MICROBLAZEV_RV32, CORE_DUAL_MICROBLAZEV_RV32, CORE_MICROBLAZEV_RV64, CORE_CV64A6 | None (**mandatory value**) +| VIO_RESETN_DEFAULT | Select value for VIO resetn | [0,1] | 1 +| XLEN | Defines Bus DATA_WIDTH, supported cores and Toolchain version | [32,64] | 32 +| PHYSICAL_ADDR_WIDTH | Select the phyisical address width. If XLEN=32 it must equal 32. If XLEN=64, it must be > 32 | (32..64) | 32 + +### Notes for CORE_SELECTOR +**XLEN** configuration must match the selected `CORE_SELECTOR`: +- `XLEN=64` requires `CORE_SELECTOR in {CORE_MICROBLAZEV_RV64, CORE_CV64A6}` +- `XLEN=32` requires `CORE_SELECTOR in {CORE_PICORV32, CORE_CV32E40P, CORE_IBEX, CORE_MICROBLAZEV_RV32, CORE_DUAL_MICROBLAZEV_RV32}` + +Additional notes: +- `CORE_SELECTOR = CORE_PICORV32`: the external PicoRV32 IP is currently bugged in CSR support. Any code running with CORE_PICORV32 must not perform any CSR operation. +- `CORE_SELECTOR = CORE_DUAL_MICROBLAZEV_RV32` requires two additional `MASTER_NAMES` into `config_main_bus.csv`, namely `RV_SOCKET_DATA1 RV_SOCKET_INSTR1`. + +### VIO resetn default +The `VIO_RESETN_DEFAULT` parameter controls the programming-time value of core reset. +- `VIO_RESETN_DEFAULT = 1` (default): VIO resetn is non-active, the CPU starts running at programming-time, allowing debugging with DTM and GDB. +- `VIO_RESETN_DEFAULT = 0`: VIO resetn is active, keeping the core in a reset state when the bitstream is programmed. + +### Bus Configuration + +> **IMPORTANT NOTE**: the address range of a bus (child) that is a slave of another bus (parent), in its configuration (.csv) file, must be an absolute address range, this means that if the child bus is mapped in the parent bus at the address 0x1000 to 0x1FFF, then the peripherals in the child bus must be in the address range 0x1000 to 0x1FFFE + +| Name | Description | Values | Default +|-|-|-|-| +| PROTOCOL | AXI PROTOCOL | (AXI4, AXI4LITE, AXI3, DISABLE*) | N/A +| CONNECTIVITY_MODE | Crossbar Interconnection | Shared-Address, Multiple-Data(SAMD), Shared-Address/Shared-Data(SASD) | SAMD +| ID_WIDTH | AXI ID Width | (4..32) | 4 +| NUM_MI | Number of Master Interfaces (number of slaves) | (0..16) | 2 +| NUM_SI | Number of Slave Interfaces (number of masters) | (0..16) | 1 +| MASTER_NAMES | Names of masters connected to the bus | [NUM_SI] Strings | N/A +| RANGE_NAMES | Names of slave memory ranges | [NUM_MI] Strings | N/A +| MAIN_CLOCK_DOMAIN | Clock domain of the core + MBUS | (10, 20, 50, 100) for embedded. (10, 20, 50, 100, 250) for hpc | None +| RANGE_CLOCK_DOMAINS | Clock domains of the slaves (RANGE_NAMES) of the MBUS | [NUM_MI] (10, 20, 50, 100, 250 hpc only)| Note: the BRAM, DM_mem, PLIC clock domain must be the same as MAIN_CLOCK_DOMAIN, while the DDR clock domain must have the same frequency of the DDR board clock (i.e. 300MHz) +| ADDR_RANGES | Number of ranges for master interfaces | (1..16) | 1 +| BASE_ADDR | The Base Addresses for each range of each Master | [NUM_MI*ADDR_RANGES] 64 bits hex | 0x100000 for the first range of every Master, otherwise is 0xffffffffffffffff [not used], it must be lesser or equal of Global ADDR_WIDTH +| RANGE_ADDR_WIDTH | Number of bytes covered by each range of each Master | [NUM_MI*ADDR_RANGES] (12..64) for AXI4 and AXI3, (1..64) for AXI4LITE | 12 for the first range of every Master, otherwise is 0 [not used] +| READ_CONNECTIVITY | Master to slave read connectivity | [NUM_MI*NUM_SI] not enabled (0), enabled (1) | 1 +| WRITE_CONNECTIVITY | Master to slave write connectivity | [NUM_MI*NUM_SI] not enabled (0), enabled (1) | 1 +| STRATEGY | Implementation strategy | Minimize Area (1), Maximize Performance (2) | 0 +| Slave_Priority | Scheduling Slave Priorities | [NUM_SI] (0..16) | 0 which is Round-Robin +| SI_READ_ACCEPTANCE | Number of concurrent Read Transactions for each Slave | [NUM_SI] (1..32) | 2, only 1 with SASD [forced by STRATEGY, Connectivity Mode and R_REGISTER choices] +| SI_WRITE_ACCEPTANCE | Number of concurrent Write Transactions for each Slave | [NUM_SI] (1..32) | 2, only 1 with SASD [forced by STRATEGY, Connectivity Mode and R_REGISTER choices] +| THREAD_ID_WIDTH | Number of ID bits used for Thread ID for each Slave | [NUM_SI] (0..32) | 0 is default, at the moment it’s forced to 0 +| SINGLE_THREAD | Support for multiple Threads for each Slave | [NUM_SI] Multiple Threads (0), Single Thread (1) | 0 +| BASE_ID | ID Base value for each Slave | [NUM_SI] (0x0..0xffffffff) | N/A +| MI_READ_ISSUING | Number of concurrent Read Transactions for each Master | [NUM_MI] (1..32) | 4, only 1 with AXI4LITE and AXI3 [forced by PROTOCOL] +| MI_WRITE_ISSUING | Number of concurrent Write Transactions for each Master | [NUM_MI] (1..32) | 4, only 1 AXI4LITE and AXI3 [forced by PROTOCOL] +| SECURE | SECURE Mode for each Master | [NUM_MI] Non-SECURE (0), SECURE (1) | 0 +| R_REGISTER | Read channel register slice | None (0), Full (1), Light(8), Automatic (8) | 0, 1 only with SASD [forced by STRATEGY] +| AWUSER_WIDTH | AXI AW User width | (0..1024) | 0 +| ARUSER_WIDTH | AXI AR User width | (0..1024) | 0 +| WUSER_WIDTH | AXI W User width | (0..1024) | 0 +| RUSER_WIDTH | AXI R User width | (0..1024) | 0 +| BUSER_WIDTH | AXI B User width | (0..1024) | 0 + +> \* Using `DISABLE` as AXI PROTOCOL, disable all checks for a given bus. Useful for non-instantiated buses, e.g. HBUS in `embedded` profile + +## Genenerate Configurations +After applying configuration changes to the target CSV files (`embedded` or `hpc`), apply though `make`. + +Alternatively, you can control the generation of single targets: +``` bash +$ make config_check # Preliminary sanity check for configuration +$ make config_main_bus # Generates MBUS config +$ make config_peripheral_bus # Generates PBUS config +$ make config_highperformance_bus # Generates HBUS config +$ make config_ld # Generates linker script +$ make config_xilinx # Update xilinx config +$ make config_sw # Update software config +``` + +### BRAM size configuration +The `config_xilinx` flow also configures the BRAM size of the IP `xlnx_blk_mem_gen_` (where i is the BRAM index) according to the `RANGE_ADDR_WIDTH` assigned to the BRAM in the CSV. + +> **NOTE**: The `xlnx_blk_mem_gen_0/config.tcl` file configures the first BRAM occurrence, hence it uses the index 0. For now, a single BRAM is supported, if multiple BRAMs are declared in the config (CSV) file, the config flow gives an error. Multiple BRAMs would be simple to add in the future. + +> **NOTE**: All the `xlnx_blk_mem_gen_/config.tcl` configuration files must be in the `ips/common` directory. + +### Clock domains +The configuration flow gives the possibility to specify clock domains. +The `MAIN_CLOCK_DOMAIN` is the closk domain of the core and the main bus (`MBUS`). All the slaves attached to the `MBUS` can have their own clock domain. If a slave has a domain different from the `MAIN_CLOCK_DOMAIN`, it needs a `xlnx_axi_clock_converter` to cross the clock domains. In this case the configuration flow will set the `_HAS_CLOCK_DOMAIN` (i.e. `PBUS_HAS_CLOCK_DOMAIN`) variable which informs that the slave has its own clock domain. + +### Scripting Architecture +The directory `scripts/` holds multiple scripts, acting in the following scripting architecture: + +![Configuration flow](./doc/axi_xbar_config_with_check.png) + +The multiple scripts generate outputs from common inputs: +1. The Xilinx-related environment configuration in [`config.mk`](../hw/xilinx/make/config.mk) is handled by [`config_xilinx.sh`](scripts/config_xilinx.sh). +1. The software-related environment (including toolchain and compilation flags) configuration in [`config.mk`](../sw/SoC/common/config.mk) is handled by [`config_sw.sh`](scripts/config_sw.sh). +1. [Linker script](../sw/SoC/common/UninaSoC.ld) generation is handled solely by [`create_linker_script.py`](scripts/create_linker_script.py) source. +1. Configuration TCL files (for [MBUS](../hw/xilinx/ips/common/xlnx_main_crossbar/config.tcl) and [PBUS](../hw/xilinx/ips/common/xlnx_peripheral_crossbar/config.tcl)) for the platform crossbars are generated with [`create_crossbar_config.py`](scripts/create_crossbar_config.py) as master script. + +### How to add a new property +In the table above, multiple properties are supported, but more can be added. +To add a new property: +1. In the target CSV file, e.g. `config_main_bus.csv`, add the new key-value pair. +2. In file `configuration.py`, add the new property to the config class. Name must match the key in `config_main_bus.csv`. +3. In file `parse_properties_wrapper.py`, file add a case that composes the new function call. +4. In file `parse_properties_impl.py`, add a function that handles the new property: + - how it is parsed. + - how it is sanitized. + - how it updates the `configuration` structure. +5. In file `create_crossbar_config.py` file, after the loop setting the `configuration` structure, +create the tcl property string and add it to the list of commands, which will then be flushed on the output file. +6. If necessary, add new checks in the `check_config.py` script. diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..eb9d5c8f2374b283911ab96200adf3f55bffe591 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/.gitignore @@ -0,0 +1,5 @@ +# Ignore rtl folders for downloaded sources +*/rtl/* + +# Downloaded binaries +bender diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..948563e8c98ad8bdd42c1b793130c2ca5f1ae6c9 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/Makefile @@ -0,0 +1,34 @@ +# Environment check +ifndef ROOT_DIR +$(error Setup script settings.sh has not been sourced, aborting) +endif + +SHELL := /bin/bash + +# All custom IPs directories, excluding custom_template +IP_RTL_LIST = $(filter-out custom_template, $(shell basename --multiple ${HW_UNITS_ROOT}/custom_*) ) + +all: units + +units: $(addsuffix /rtl, ${IP_RTL_LIST}) + +# Fetch sources for all IPs without local rtl +custom_%/rtl: + cd ${HW_UNITS_ROOT}/custom_$*; source fetch_sources.sh \ +# Check if sources are preset, error otherwise and clean stale dir + if [ -z "$(shell ls -A $${HW_UNITS_ROOT}/$$@)" ]; then \ + echo "[UNITS] Failed to fetch sources for $@" >&2; \ + rm -rf $@; \ + false; \ + fi + +# Selectively remove a single RTL dir +clean_custom_%: + rm -rf ${HW_UNITS_ROOT}/custom_$*/rtl + +# Remove all RTL dirs +clean: + rm -rf ${HW_UNITS_ROOT}/*/rtl + + +.PHONY: clean diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/README.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/README.md new file mode 100644 index 0000000000000000000000000000000000000000..241e8f877b4b9e68f965bb9fef2e0c292b9c8d4a --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/README.md @@ -0,0 +1,53 @@ +# Custom IP Implementation and Simulation + +The source files for the custom IPs used in the SoC are located in this directory. These custom IPs are packaged using the Makefile IPs flow found in the `hw/xilinx` directory. Each IP's build and packaging process directly references the source files in `units/custom_IP_NAME`. + +## Custom Units Integration + +Each custom IP, or unit, is represented by two subdirectories: one in `hw/units` and another in `hw/xilinx/ips`. + +``` +├── units +│ └── custom_ +| ├── assets/ +| ├── custom_top_wrapper.sv +| └── fetch_sources.sh +└── xilinx + ├── doc + └── ips + ├── common + │ └── custom_ + | └── config.tcl -> ../tcl/custom_config.tcl + ├── embedded + └── hpc +``` + +These two directories must share the same name, both using the `custom_` prefix: +- The directory in `hw/xilinx/ips`, only need a `config.tcl` scrtipt, usually simply soft-linking to the `ips/common/config.tcl` file. +- The directory in `hw/units` must expose: + 1. A `fetch_sources.sh` script. + 1. A `custom_top_wrapper.sv` RTL source to wrap all RTL in a single top module. + 1. An `assets/` directory holding any other file used by the one script or wrapper above, e.g. a configuration file, a static file list, an RTL source, etc. + +If the custom IP originates from a remote repository (e.g., a GitHub project), the `fetch_sources.sh` script should: +1. create an `rtl/` directory, +1. clone and copy all source files into the `rtl/` directory in a **flattened structure**, and +1. remove all temporary files created during this process. + +> The `custom_template/` directory contains a template project for custom IPs, including a wrapper module and a script. + +With such tree in place, you can fetch rtl sources for all custom IPs with: +``` +make units +``` + +Once all sources are flattened in the `hw/units//custom_` directory, the make flow in `hw/xilinx` will take care of building a out-of-context IP, `custom_`, out of them. + +### Using MEM and AXI interfaces + +The file `custom_top_wrapper.sv` RTL wrapper can leverage platform-compatible interfaces, namely MEM, AXI4 and AXI-lite. + +It can leverage the `hw/xilinx/rtl/uninasoc_mem.svh` and `hw/xilinx/rtl/uninasoc_axi.svh` headers (which are already included in the Vivado project packaging flow) to define macros for the MEM and AXI bus interfaces. While custom signals are allowed, we expect the custom IP to primarily communicate via either AXI (preferably) or MEM. + +> NOTE: [[#121](https://github.com/HiSA-Team/Simply-V/issues/121)] Vivado does not allow macros when exporting SystemVerilog IPs. +So we can't import config-based parameters, e.g. `MBUS_ID_WIDTH`, and IP interfaces must be manually aligned with configuration. diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..ecd30cc422fb5b14206c99dc6e952e39e3a4cb27 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/.gitignore @@ -0,0 +1,2 @@ +axi/ +*.flist \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..e601cd47e74c20f30828016fa85b2cee2a7319b4 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/custom_top_wrapper.sv @@ -0,0 +1,161 @@ +// Author: Stefano Mercogliano +// Description: Top level wrapper module for PULP AXI axi_from_mem adapter. + + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" +`include "typedef.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // TODO121: Automatically align with config + parameter LOCAL_MEM_ADDR_WIDTH = 32, + parameter LOCAL_MEM_DATA_WIDTH = 32, + parameter LOCAL_AXI_DATA_WIDTH = 32, + parameter LOCAL_AXI_ADDR_WIDTH = 32, + parameter LOCAL_AXI_STRB_WIDTH = LOCAL_AXI_DATA_WIDTH / 8, + parameter LOCAL_AXI_ID_WIDTH = 4, + parameter LOCAL_AXI_REGION_WIDTH = 4, + parameter LOCAL_AXI_LEN_WIDTH = 8, + parameter LOCAL_AXI_SIZE_WIDTH = 3, + parameter LOCAL_AXI_BURST_WIDTH = 2, + parameter LOCAL_AXI_LOCK_WIDTH = 1, + parameter LOCAL_AXI_CACHE_WIDTH = 4, + parameter LOCAL_AXI_PROT_WIDTH = 3, + parameter LOCAL_AXI_QOS_WIDTH = 4, + parameter LOCAL_AXI_VALID_WIDTH = 1, + parameter LOCAL_AXI_READY_WIDTH = 1, + parameter LOCAL_AXI_LAST_WIDTH = 1, + parameter LOCAL_AXI_RESP_WIDTH = 2 + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + input logic clk_i, + input logic rst_ni, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // AXI4 Full Master interface from SRAM protocol (mem) + `DEFINE_AXI_MASTER_PORTS (m, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH), + // Mem interface + `DEFINE_MEM_SLAVE_PORTS (s, LOCAL_MEM_DATA_WIDTH, LOCAL_MEM_ADDR_WIDTH) +); + + // Define the req_t and resp_t type using typedef.svh macro + `AXI_TYPEDEF_ALL( + axi, + logic [LOCAL_AXI_ADDR_WIDTH-1:0], + logic [LOCAL_AXI_ID_WIDTH-1:0], + logic [LOCAL_AXI_DATA_WIDTH-1:0], + logic [LOCAL_AXI_STRB_WIDTH-1:0], + logic [0:0] // This is for the user field, which is missing from our interface (or unused) + ) + + axi_req_t axi_req; + axi_resp_t axi_rsp; + + // Define internal Cache signals (just a passthrough for clarity) + logic [LOCAL_AXI_CACHE_WIDTH -1 : 0] slv_aw_cache; + logic [LOCAL_AXI_CACHE_WIDTH -1 : 0] slv_ar_cache; + + + // Instantiation of axi_from_mem module + axi_from_mem #( + .MemAddrWidth ( LOCAL_MEM_ADDR_WIDTH ), // Memory request address width + .AxiAddrWidth ( LOCAL_AXI_ADDR_WIDTH ), // AXI4-Lite address width + .DataWidth ( LOCAL_AXI_DATA_WIDTH ), // Data width of memory and AXI4-Lite + .MaxRequests ( 1 ), // Max number of in-flight requests + .AxiProt ( 3'b000 ), // Protection signal for AXI4 transactions + .axi_req_t ( axi_req_t ), // AXI4 request struct type + .axi_rsp_t ( axi_resp_t ) // AXI4 response struct type + ) axi_from_mem_u ( + // Clock and Reset + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + // Memory Slave Port Inputs + .mem_req_i ( s_mem_req ), + .mem_addr_i ( s_mem_addr ), + .mem_we_i ( s_mem_we ), + .mem_wdata_i ( s_mem_wdata ), + .mem_be_i ( s_mem_be ), + + // Memory Slave Port Outputs + .mem_gnt_o ( s_mem_gnt ), + .mem_rsp_valid_o ( s_mem_valid ), + .mem_rsp_rdata_o ( s_mem_rdata ), + .mem_rsp_error_o ( s_mem_error ), + + // AXI4 Master Port Inputs + .slv_aw_cache_i ( slv_aw_cache ), + .slv_ar_cache_i ( slv_ar_cache ), + + // AXI4 Master Port Outputs + .axi_req_o ( axi_req ), + + // AXI4 Master Port Inputs + .axi_rsp_i ( axi_rsp ) + ); + + // Unwrap axi_from_mem structured type + + // Map Cache signals + assign slv_aw_cache = m_axi_awcache; + assign slv_ar_cache = m_axi_arcache; + + // Map OUTPUT signals + assign m_axi_awid = axi_req.aw.id; + assign m_axi_awaddr = axi_req.aw.addr; + assign m_axi_awlen = axi_req.aw.len; + assign m_axi_awsize = axi_req.aw.size; + assign m_axi_awburst = axi_req.aw.burst; + assign m_axi_awlock = axi_req.aw.lock; + assign m_axi_awcache = axi_req.aw.cache; + assign m_axi_awprot = axi_req.aw.prot; + assign m_axi_awqos = axi_req.aw.qos; + assign m_axi_awregion = axi_req.aw.region; + assign m_axi_awvalid = axi_req.aw_valid; + assign m_axi_wdata = axi_req.w.data; + assign m_axi_wstrb = axi_req.w.strb; + assign m_axi_wlast = axi_req.w.last; + assign m_axi_wvalid = axi_req.w_valid; + assign m_axi_bready = axi_req.b_ready; + assign m_axi_araddr = axi_req.ar.addr; + assign m_axi_arlen = axi_req.ar.len; + assign m_axi_arsize = axi_req.ar.size; + assign m_axi_arburst = axi_req.ar.burst; + assign m_axi_arlock = axi_req.ar.lock; + assign m_axi_arcache = axi_req.ar.cache; + assign m_axi_arprot = axi_req.ar.prot; + assign m_axi_arqos = axi_req.ar.qos; + assign m_axi_arregion = axi_req.ar.region; + assign m_axi_arvalid = axi_req.ar_valid; + assign m_axi_rready = axi_req.r_ready; + assign m_axi_arid = axi_req.ar.id; + + assign axi_rsp.aw_ready = m_axi_awready; + assign axi_rsp.w_ready = m_axi_wready; + assign axi_rsp.b.id = m_axi_bid; + assign axi_rsp.b.resp = m_axi_bresp; + assign axi_rsp.b_valid = m_axi_bvalid; + assign axi_rsp.ar_ready = m_axi_arready; + assign axi_rsp.r.id = m_axi_rid; + assign axi_rsp.r.data = m_axi_rdata; + assign axi_rsp.r.resp = m_axi_rresp; + assign axi_rsp.r.last = m_axi_rlast; + assign axi_rsp.r_valid = m_axi_rvalid; + +endmodule : custom_top_wrapper + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..94b9985feeaa97b483e9a29e8a383710ca5b66c8 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_axi_from_mem/fetch_sources.sh @@ -0,0 +1,56 @@ +#!/bin/bash +# Author: Vincenzo Maisto +# Description: +# This script downloads axi_to_mem from https://github.com/pulp-platform/axi/ sources and flattens them into the rtl directory + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +# Create rtl dir +RTL_DIR=rtl +mkdir ${RTL_DIR} + +# clone repo +GIT_URL=https://github.com/pulp-platform/axi.git +GIT_TAG=v0.39.6 +CLONE_DIR=axi +printf "${YELLOW}[FETCH_SOURCES] Cloning source repository at ${GIT_TAG} ${NC}\n" +git clone ${GIT_URL} -b ${GIT_TAG} --depth 1 ${CLONE_DIR} +cd ${CLONE_DIR}; + +# Clone Bender +printf "${YELLOW}[FETCH_SOURCES] Download Bender${NC}\n" +curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh + +# Download dependencies (specify Target RTL and FPGA) +printf "${YELLOW}[FETCH_SOURCES] Resolve dependencies with Bender${NC}\n" +./bender checkout +BENDER_TARGETS="-t xilinx -t fpga" +./bender script flist ${BENDER_TARGETS} > ../rtl.flist +cd .. + +# Copy all RTL files into rtl dir +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into ${RTL_DIR}/${NC}\n" s +for rtl_file in $(cat rtl.flist) ; do + cp $rtl_file ${RTL_DIR} +done; + +# Add header files, not listed by bender +cp $(find ${CLONE_DIR} -name typedef.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name assertions.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name registers.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name assign.svh) ${RTL_DIR}/ + +# Remove interface-based files, since Vivado does not like them +rm $(find ${RTL_DIR}/ -name axi_intf.sv) + +# Patch files for flat includes +for rtl_file in ${RTL_DIR}/* ; do + sed -i "s|\`include \"common_cells\/|\`include \"|g" $rtl_file + sed -i "s|\`include \"axi\/|\`include \"|g" $rtl_file +done + +# Info +printf "${GREEN}[FETCH_SOURCES] Completed${NC}\n" \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..c8af5de04e9c87ff9ce0ba9a82168e13ff98f295 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/.gitignore @@ -0,0 +1,2 @@ +cv32e40p/ +*.flist \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/assets/cv32e40_Bender.lock b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/assets/cv32e40_Bender.lock new file mode 100644 index 0000000000000000000000000000000000000000..83ea461fb22e7bcde83bf39fd1ac03783e8457d1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/assets/cv32e40_Bender.lock @@ -0,0 +1,36 @@ +packages: + common_cells: + revision: 9afda9abb565971649c2aa0985639c096f351171 + version: 1.38.0 + source: + Git: https://github.com/pulp-platform/common_cells.git + dependencies: + - common_verification + - tech_cells_generic + common_verification: + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 + source: + Git: https://github.com/pulp-platform/common_verification.git + dependencies: [] + fpnew: + revision: 8dc44406b1ccbc4487121710c1883e805f893965 + version: 0.6.6 + source: + Git: https://github.com/pulp-platform/fpnew.git + dependencies: + - common_cells + - fpu_div_sqrt_mvp + fpu_div_sqrt_mvp: + revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac + version: 1.0.4 + source: + Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git + dependencies: + - common_cells + tech_cells_generic: + revision: 04b7b2735d42e4715c1bc9227027a3d8fb770c08 + version: 0.1.16 + source: + Git: https://github.com/pulp-platform/tech_cells_generic.git + dependencies: [] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..11945d172d11480445445a310365d7b5fc71937d --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/custom_top_wrapper.sv @@ -0,0 +1,133 @@ +// Author: Stefano Mercogliano +// Description: Top level wrapper for CV32E40P CPU. + + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // TODO121: Automatically align with config + parameter LOCAL_DATA_WIDTH = 32, // AXI/MEM macros parameter + parameter LOCAL_ADDR_WIDTH = 32, // AXI/MEM macros parameter + parameter COREV_PULP = 0, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) + parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw) + parameter FPU = 0, // Floating Point Unit (interfaced via APU interface) + parameter FPU_ADDMUL_LAT = 0, // Floating-Point ADDition/MULtiplication computing lane pipeline registers number + parameter FPU_OTHERS_LAT = 0, // Floating-Point COMParison/CONVersion computing lanes pipeline registers number + parameter ZFINX = 0, // Float-in-General Purpose registers + parameter NUM_MHPMCOUNTERS = 1 + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + input logic clk_i, + input logic rst_ni, + + input logic pulp_clock_en_i, // PULP clock enable (only used if COREV_CLUSTER = 1) + input logic scan_cg_en_i, // Enable all clock gates for testing + + // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static + input logic [31:0] boot_addr_i, + input logic [31:0] mtvec_addr_i, + input logic [31:0] dm_halt_addr_i, + input logic [31:0] hart_id_i, + input logic [31:0] dm_exception_addr_i, + + // Interrupt inputs + input logic [31:0] irq_i, // CLINT interrupts + CLINT extension interrupts + output logic irq_ack_o, + output logic [ 4:0] irq_id_o, + + // Debug Interface + input logic debug_req_i, + output logic debug_havereset_o, + output logic debug_running_o, + output logic debug_halted_o, + + // CPU Control Signals + input logic fetch_enable_i, + output logic core_sleep_o, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // MEM Master Interface Array + `DEFINE_MEM_MASTER_PORTS(instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH), + // MEM Slave Interface Array + `DEFINE_MEM_MASTER_PORTS(data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH) +); + + // Tie-off non-driven signals + assign instr_mem_wdata = '0; + assign instr_mem_we = '0; + assign instr_mem_be = '0; + + cv32e40p_top #( + .COREV_PULP ( COREV_PULP ), // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw) + .COREV_CLUSTER ( COREV_CLUSTER ), // PULP Cluster interface (incl. cv.elw) + .FPU ( FPU ), // Floating Point Unit (interfaced via APU interface) + .FPU_ADDMUL_LAT ( FPU_ADDMUL_LAT ), // Floating-Point ADDition/MULtiplication computing lane pipeline registers number + .FPU_OTHERS_LAT ( FPU_OTHERS_LAT ), // Floating-Point COMParison/CONVersion computing lanes pipeline registers number + .ZFINX ( ZFINX ), // Float-in-General Purpose registers + .NUM_MHPMCOUNTERS ( NUM_MHPMCOUNTERS ) + ) ( + // Clock and Reset + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .pulp_clock_en_i ( pulp_clock_en_i ), // PULP clock enable (only used if COREV_CLUSTER = 1) + .scan_cg_en_i ( scan_cg_en_i ), // Enable all clock gates for testing + + // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static + .boot_addr_i ( boot_addr_i ), + .mtvec_addr_i ( mtvec_addr_i ), + .dm_halt_addr_i ( dm_halt_addr_i ), + .hart_id_i ( hart_id_i ), + .dm_exception_addr_i ( dm_exception_addr_i ), + + // Instruction memory interface + .instr_req_o ( instr_mem_req ), + .instr_gnt_i ( instr_mem_gnt ), + .instr_rvalid_i ( instr_mem_valid ), + .instr_addr_o ( instr_mem_addr ), + .instr_rdata_i ( instr_mem_rdata ), + + // Data memory interface + .data_req_o ( data_mem_req ), + .data_gnt_i ( data_mem_gnt ), + .data_rvalid_i ( data_mem_valid ), + .data_we_o ( data_mem_we ), + .data_be_o ( data_mem_be ), + .data_addr_o ( data_mem_addr ), + .data_wdata_o ( data_mem_wdata ), + .data_rdata_i ( data_mem_rdata ), + + // Interrupt inputs + .irq_i ( irq_i ), // CLINT interrupts + CLINT extension interrupts + .irq_ack_o ( irq_ack_o ), + .irq_id_o ( irq_id_o ), + + // Debug Interface + .debug_req_i ( debug_req_i ), + .debug_havereset_o ( debug_havereset_o ), + .debug_running_o ( debug_running_o ), + .debug_halted_o ( debug_halted_o ), + + // CPU Control Signals + .fetch_enable_i ( fetch_enable_i ), + .core_sleep_o ( core_sleep_o ) + ); + +endmodule : custom_top_wrapper + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..1b1a2ce3111fefb4bc3f71584e6c048054ac6d6c --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv32e40p/fetch_sources.sh @@ -0,0 +1,60 @@ +#!/bin/bash +# Author: Stefano Mercogliano +# Description: +# This script downloads cv32e40p cv32e40p_v1.8.3 sources and flattens them into the rtl directory + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +# Create rtl dir +mkdir rtl + +# clone repo (Release v1.8.3 Jul 15 2024) +GIT_URL=https://github.com/openhwgroup/cv32e40p.git +GIT_TAG=cv32e40p_v1.8.3 +CLONE_DIR=cv32e40p +printf "${YELLOW}[FETCH_SOURCES] Cloning source repository${NC}\n" +git clone ${GIT_URL} -b ${GIT_TAG} --depth 1 ${CLONE_DIR} +cd ${CLONE_DIR}; + +# Clone Bender +printf "${YELLOW}[FETCH_SOURCES] Download Bender${NC}\n" +curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh + +# Download dependencies (specify Target RTL and FPGA) +printf "${YELLOW}[FETCH_SOURCES] Resolve dependencies with Bender${NC}\n" +# Inject pre-solved conflicts +# - package `riscv` requires `^0.1.1` +# - package `common_cells` requires `^0.2.11` +cp ../assets/cv32e40_Bender.lock Bender.lock +# Checkout +./bender checkout +BENDER_TARGETS="-t xilinx -t fpga" +./bender script flist ${BENDER_TARGETS} > rtl.flist +./bender script flist > rtl.flist +cp cv32e40p_fpu_manifest.flist ../local.flist + +# Process remote.flist (just save the .bender files) +printf "${YELLOW}[FETCH_SOURCES] Create final rtl file list${NC}\n" +grep .bender ../remote.flist > ../rtl.flist + +# Process local.flist +cd rtl; +DIR=$(pwd) +cd ../..; +grep -v '^/' local.flist > local_tmp.flist +grep -v '^+' local_tmp.flist > local_tmp_2.flist +sed 's/${DESIGN_RTL_DIR}/DESIGN_RTL_DIR/g' local_tmp_2.flist > local_tmp_3.flist +sed -i "s|DESIGN_RTL_DIR|$DIR|" local_tmp_3.flist +cat local_tmp_3.flist >> rtl.flist + +# Copy all RTL files into rtl dir +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into rtl${NC}\n" s +for rtl_file in $(cat rtl.flist) ; do + cp $rtl_file rtl +done; + +# Info +printf "${GREEN}[FETCH_SOURCES] Completed${NC}\n" diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..bc7ab87f9e055681ea17ffff9f01ce9a996327c6 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/.gitignore @@ -0,0 +1,2 @@ +cva6/ +*.flist \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/cv64a6_config_pkg.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/cv64a6_config_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..a026f97f6413dbea3865805d52421003b38f7920 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/cv64a6_config_pkg.sv @@ -0,0 +1,165 @@ +// Copyright 2021 Thales DIS design services SAS +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +// You may obtain a copy of the License at https://solderpad.org/licenses/ +// +// Original Author: Jean-Roch COULON - Thales + + +// Author: Stefano Mercogliano +// This configuration file is a slightly modified version compare to the OpenHW one. +// Differently, we support FpgaEn and Setup our own debug addresses + + +package cva6_config_pkg; + + localparam CVA6ConfigXlen = 64; + localparam CVA6ConfigVlen = 64; + + localparam CVA6ConfigFpgaEn = 1; + + localparam CVA6ConfigDmBaseAddress = 64'h10000; + localparam CVA6ConfigDmHaltAddress = 64'h800; + localparam CVA6ConfigDmExceptionAddress = 64'h810; + + localparam CVA6ConfigRVF = 1; + localparam CVA6ConfigF16En = 0; + localparam CVA6ConfigF16AltEn = 0; + localparam CVA6ConfigF8En = 0; + localparam CVA6ConfigFVecEn = 0; + + localparam CVA6ConfigCvxifEn = 1; + localparam CVA6ConfigCExtEn = 1; + localparam CVA6ConfigZcbExtEn = 1; + localparam CVA6ConfigZcmpExtEn = 0; + localparam CVA6ConfigAExtEn = 1; + localparam CVA6ConfigHExtEn = 1; + localparam CVA6ConfigBExtEn = 1; + localparam CVA6ConfigVExtEn = 0; + localparam CVA6ConfigRVZiCond = 1; + + localparam CVA6ConfigAxiIdWidth = 4; + localparam CVA6ConfigAxiAddrWidth = 64; + localparam CVA6ConfigAxiDataWidth = 64; + localparam CVA6ConfigFetchUserEn = 0; + localparam CVA6ConfigFetchUserWidth = CVA6ConfigXlen; + localparam CVA6ConfigDataUserEn = 0; + localparam CVA6ConfigDataUserWidth = CVA6ConfigXlen; + + localparam CVA6ConfigIcacheByteSize = 16384; + localparam CVA6ConfigIcacheSetAssoc = 4; + localparam CVA6ConfigIcacheLineWidth = 128; + localparam CVA6ConfigDcacheByteSize = 32768; + localparam CVA6ConfigDcacheSetAssoc = 8; + localparam CVA6ConfigDcacheLineWidth = 128; + + localparam CVA6ConfigDcacheFlushOnFence = 1'b0; + localparam CVA6ConfigDcacheInvalidateOnFlush = 1'b0; + + localparam CVA6ConfigDcacheIdWidth = 1; + localparam CVA6ConfigMemTidWidth = 2; + localparam CVA6ConfigWtDcacheWbufDepth = 8; + localparam CVA6ConfigNrScoreboardEntries = 8; + localparam CVA6ConfigNrLoadPipeRegs = 1; + localparam CVA6ConfigNrStorePipeRegs = 0; + localparam CVA6ConfigNrLoadBufEntries = 2; + localparam CVA6ConfigRASDepth = 2; + localparam CVA6ConfigBTBEntries = 32; + localparam CVA6ConfigBHTEntries = 128; + localparam CVA6ConfigTvalEn = 1; + localparam CVA6ConfigNrPMPEntries = 8; + localparam CVA6ConfigPerfCounterEn = 1; + localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT; + localparam CVA6ConfigMmuPresent = 1; + localparam CVA6ConfigRvfiTrace = 1; + + localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{ + XLEN: unsigned'(CVA6ConfigXlen), + VLEN: unsigned'(CVA6ConfigVlen), + FpgaEn: bit'(CVA6ConfigFpgaEn), // for Xilinx and Altera + FpgaAlteraEn: bit'(0), // for Altera (only) + TechnoCut: bit'(0), + SuperscalarEn: bit'(0), + NrCommitPorts: unsigned'(2), + AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth), + AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth), + AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth), + AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth), + MemTidWidth: unsigned'(CVA6ConfigMemTidWidth), + NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries), + RVF: bit'(CVA6ConfigRVF), + RVD: bit'(CVA6ConfigRVF), + XF16: bit'(CVA6ConfigF16En), + XF16ALT: bit'(CVA6ConfigF16AltEn), + XF8: bit'(CVA6ConfigF8En), + RVA: bit'(CVA6ConfigAExtEn), + RVB: bit'(CVA6ConfigBExtEn), + ZKN: bit'(1), + RVV: bit'(CVA6ConfigVExtEn), + RVC: bit'(CVA6ConfigCExtEn), + RVH: bit'(CVA6ConfigHExtEn), + RVZCB: bit'(CVA6ConfigZcbExtEn), + RVZCMT: bit'(0), + RVZCMP: bit'(CVA6ConfigZcmpExtEn), + XFVec: bit'(CVA6ConfigFVecEn), + CvxifEn: bit'(CVA6ConfigCvxifEn), + RVZiCond: bit'(CVA6ConfigRVZiCond), + RVZicntr: bit'(1), + RVZihpm: bit'(1), + NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries), + PerfCounterEn: bit'(CVA6ConfigPerfCounterEn), + MmuPresent: bit'(CVA6ConfigMmuPresent), + RVS: bit'(1), + RVU: bit'(1), + SoftwareInterruptEn: bit'(1), + HaltAddress: unsigned'(CVA6ConfigDmHaltAddress), + ExceptionAddress: unsigned'(CVA6ConfigDmExceptionAddress), + RASDepth: unsigned'(CVA6ConfigRASDepth), + BTBEntries: unsigned'(CVA6ConfigBTBEntries), + BHTEntries: unsigned'(CVA6ConfigBHTEntries), + DmBaseAddress: unsigned'(CVA6ConfigDmBaseAddress), + TvalEn: bit'(CVA6ConfigTvalEn), + DirectVecOnly: bit'(0), + NrPMPEntries: unsigned'(CVA6ConfigNrPMPEntries), + PMPCfgRstVal: {64{64'h0}}, + PMPAddrRstVal: {64{64'h0}}, + PMPEntryReadOnly: 64'd0, + PMPNapotEn: bit'(1), + NOCType: config_pkg::NOC_TYPE_AXI4_ATOP, + NrNonIdempotentRules: unsigned'(2), + NonIdempotentAddrBase: 1024'({64'b0, 64'b0}), + NonIdempotentLength: 1024'({64'b0, 64'b0}), + NrExecuteRegionRules: unsigned'(1), + ExecuteRegionAddrBase: 1024'({64'h0}), // Regions here could be tweaked depending on the system config + ExecuteRegionLength: 1024'({64'hffff_ffff_ffff_ffff}), // Regions here could be tweaked depending on the system config + NrCachedRegionRules: unsigned'(1), + CachedRegionAddrBase: 1024'({64'h8000_0000}), + CachedRegionLength: 1024'({64'h40000000}), + MaxOutstandingStores: unsigned'(7), + DebugEn: bit'(1), + AxiBurstWriteEn: bit'(0), + IcacheByteSize: unsigned'(CVA6ConfigIcacheByteSize), + IcacheSetAssoc: unsigned'(CVA6ConfigIcacheSetAssoc), + IcacheLineWidth: unsigned'(CVA6ConfigIcacheLineWidth), + DCacheType: CVA6ConfigDcacheType, + DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize), + DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc), + DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth), + DcacheFlushOnFence: unsigned'(CVA6ConfigDcacheFlushOnFence), + DcacheInvalidateOnFlush: unsigned'(CVA6ConfigDcacheInvalidateOnFlush), + DataUserEn: unsigned'(CVA6ConfigDataUserEn), + WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth), + FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth), + FetchUserEn: unsigned'(CVA6ConfigFetchUserEn), + InstrTlbEntries: int'(16), + DataTlbEntries: int'(16), + UseSharedTlb: bit'(0), + SharedTlbDepth: int'(64), + NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs), + NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs), + DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth) + }; + +endpackage diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/headers.flist b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/headers.flist new file mode 100644 index 0000000000000000000000000000000000000000..448d5944444e7c12a5dbc6c862ed221f2c018266 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/headers.flist @@ -0,0 +1,9 @@ +${DIR}/vendor/pulp-platform/common_cells/include/common_cells/assertions.svh +${DIR}/vendor/pulp-platform/common_cells/include/common_cells/registers.svh +${DIR}/vendor/pulp-platform/axi/include/axi/assign.svh +${DIR}/vendor/pulp-platform/axi/include/axi/typedef.svh +${DIR}/core/cache_subsystem/hpdcache/rtl/include/hpdcache_typedef.svh +${DIR}/corev_apu/register_interface/include/register_interface/assign.svh +${DIR}/corev_apu/register_interface/include/register_interface/typedef.svh +${DIR}/core/include/cvxif_types.svh +${DIR}/core/include/rvfi_types.svh diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/sources.flist b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/sources.flist new file mode 100644 index 0000000000000000000000000000000000000000..98a35432a9317128dd7e78a4790f341005e80668 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/sources.flist @@ -0,0 +1,267 @@ +${DIR}/corev_apu/tb/ariane_axi_pkg.sv +${DIR}/corev_apu/tb/axi_intf.sv +${DIR}/corev_apu/register_interface/src/reg_intf.sv +${DIR}/corev_apu/tb/ariane_soc_pkg.sv +${DIR}/corev_apu/riscv-dbg/src/dm_pkg.sv +${DIR}/corev_apu/tb/ariane_axi_soc_pkg.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv +${DIR}/core/cvfpu/src/fpnew_pkg.sv +${DIR}/core/cvfpu/src/fpnew_cast_multi.sv +${DIR}/core/cvfpu/src/fpnew_classifier.sv +${DIR}/core/cvfpu/src/fpnew_divsqrt_multi.sv +${DIR}/core/cvfpu/src/fpnew_fma_multi.sv +${DIR}/core/cvfpu/src/fpnew_fma.sv +${DIR}/core/cvfpu/src/fpnew_noncomp.sv +${DIR}/core/cvfpu/src/fpnew_opgroup_block.sv +${DIR}/core/cvfpu/src/fpnew_opgroup_fmt_slice.sv +${DIR}/core/cvfpu/src/fpnew_opgroup_multifmt_slice.sv +${DIR}/core/cvfpu/src/fpnew_rounding.sv +${DIR}/core/cvfpu/src/fpnew_top.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv +${DIR}/core/cvfpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv +${DIR}/core/include/config_pkg.sv +${DIR}/core/include/riscv_pkg.sv +${DIR}/core/include/ariane_pkg.sv +${DIR}/vendor/pulp-platform/axi/src/axi_pkg.sv +${DIR}/core/include/wt_cache_pkg.sv +${DIR}/core/include/std_cache_pkg.sv +${DIR}/core/include/build_config_pkg.sv +${DIR}/core/cvxif_compressed_if_driver.sv +${DIR}/core/cvxif_issue_register_commit_if_driver.sv +${DIR}/core/cvxif_example/include/cvxif_instr_pkg.sv +${DIR}/core/cvxif_fu.sv +${DIR}/core/cvxif_example/cvxif_example_coprocessor.sv +${DIR}/core/cvxif_example/instr_decoder.sv +${DIR}/core/cvxif_example/compressed_instr_decoder.sv +${DIR}/core/cvxif_example/copro_alu.sv +${DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv +${DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv +${DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv +${DIR}/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv +${DIR}/vendor/pulp-platform/common_cells/src/stream_arbiter.sv +${DIR}/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv +${DIR}/vendor/pulp-platform/common_cells/src/stream_mux.sv +${DIR}/vendor/pulp-platform/common_cells/src/stream_demux.sv +${DIR}/vendor/pulp-platform/common_cells/src/lzc.sv +${DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv +${DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv +${DIR}/vendor/pulp-platform/common_cells/src/unread.sv +${DIR}/vendor/pulp-platform/common_cells/src/popcount.sv +${DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv +${DIR}/vendor/pulp-platform/common_cells/src/counter.sv +${DIR}/vendor/pulp-platform/common_cells/src/delta_counter.sv +${DIR}/core/cva6.sv +${DIR}/core/cva6_rvfi_probes.sv +${DIR}/core/alu.sv +${DIR}/core/fpu_wrap.sv +${DIR}/core/branch_unit.sv +${DIR}/core/compressed_decoder.sv +${DIR}/core/macro_decoder.sv +${DIR}/core/controller.sv +${DIR}/core/zcmt_decoder.sv +${DIR}/core/csr_buffer.sv +${DIR}/core/csr_regfile.sv +${DIR}/core/decoder.sv +${DIR}/core/ex_stage.sv +${DIR}/core/instr_realign.sv +${DIR}/core/id_stage.sv +${DIR}/core/issue_read_operands.sv +${DIR}/core/issue_stage.sv +${DIR}/core/load_unit.sv +${DIR}/core/load_store_unit.sv +${DIR}/core/lsu_bypass.sv +${DIR}/core/mult.sv +${DIR}/core/multiplier.sv +${DIR}/core/serdiv.sv +${DIR}/core/perf_counters.sv +${DIR}/core/ariane_regfile_ff.sv +${DIR}/core/ariane_regfile_fpga.sv +${DIR}/core/scoreboard.sv +${DIR}/core/store_buffer.sv +${DIR}/core/amo_buffer.sv +${DIR}/core/store_unit.sv +${DIR}/core/commit_stage.sv +${DIR}/core/axi_shim.sv +${DIR}/core/cva6_accel_first_pass_decoder_stub.sv +${DIR}/core/acc_dispatcher.sv +${DIR}/core/cva6_fifo_v3.sv +${DIR}/core/frontend/btb.sv +${DIR}/core/frontend/bht.sv +${DIR}/core/frontend/ras.sv +${DIR}/core/frontend/instr_scan.sv +${DIR}/core/frontend/instr_queue.sv +${DIR}/core/frontend/frontend.sv +${DIR}/core/cache_subsystem/wt_dcache_ctrl.sv +${DIR}/core/cache_subsystem/wt_dcache_mem.sv +${DIR}/core/cache_subsystem/wt_dcache_missunit.sv +${DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv +${DIR}/core/cache_subsystem/wt_dcache.sv +${DIR}/core/cache_subsystem/cva6_icache.sv +${DIR}/core/cache_subsystem/wt_cache_subsystem.sv +${DIR}/core/cache_subsystem/wt_axi_adapter.sv +${DIR}/core/cache_subsystem/tag_cmp.sv +${DIR}/core/cache_subsystem/axi_adapter.sv +${DIR}/core/cache_subsystem/miss_handler.sv +${DIR}/core/cache_subsystem/cache_ctrl.sv +${DIR}/core/cache_subsystem/cva6_icache_axi_wrapper.sv +${DIR}/core/cache_subsystem/std_cache_subsystem.sv +${DIR}/core/cache_subsystem/std_nbdcache.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_pkg.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_read_arbiter.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_req_write_arbiter.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_demux.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_lfsr.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sync_buffer.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fifo_reg_initialized.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_fxarb.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_rrarb.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_mux.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_decoder.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_1hot_to_binary.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_prio_1hot_encoder.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wbyteenable.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_sram_wmask.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wbyteenable_1rw.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_regbank_wmask_1rw.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_downsize.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_upsize.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/common/hpdcache_data_resize.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_pkg.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_arb.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hwpf_stride/hwpf_stride_wrapper.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_amo.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_cmo.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_core_arbiter.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_ctrl_pe.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_memctrl.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_miss_handler.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_mshr.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_rtab.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_uncached.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_plru.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_random.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_victim_sel.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_wbuf.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/hpdcache_flush.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_resp_demux.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_read.sv +${DIR}/core/cache_subsystem/hpdcache/rtl/src/utils/hpdcache_mem_to_axi_write.sv +${DIR}/core/cache_subsystem/cva6_hpdcache_subsystem.sv +${DIR}/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv +${DIR}/core/cache_subsystem/cva6_hpdcache_if_adapter.sv +${DIR}/core/cache_subsystem/cva6_hpdcache_wrapper.sv +${DIR}/core/pmp/src/pmp.sv +${DIR}/core/pmp/src/pmp_entry.sv +${DIR}/core/pmp/src/pmp_data_if.sv +${DIR}/common/local/util/tc_sram_wrapper_cache_techno.sv +${DIR}/common/local/util/sram.sv +${DIR}/common/local/util/sram_cache.sv +${DIR}/core/cva6_mmu/cva6_mmu.sv +${DIR}/core/cva6_mmu/cva6_ptw.sv +${DIR}/core/cva6_mmu/cva6_tlb.sv +${DIR}/core/cva6_mmu/cva6_shared_tlb.sv +${DIR}/core/cva6_rvfi.sv +${DIR}/corev_apu/src/ariane.sv +${DIR}/corev_apu/clint/axi_lite_interface.sv +${DIR}/corev_apu/clint/clint.sv +${DIR}/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv +${DIR}/corev_apu/fpga/src/axi2apb/src/axi2apb.sv +${DIR}/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv +${DIR}/corev_apu/fpga/src/apb_timer/apb_timer.sv +${DIR}/corev_apu/fpga/src/apb_timer/timer.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_slice.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv +${DIR}/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv +${DIR}/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv +${DIR}/corev_apu/axi_mem_if/src/axi2mem.sv +${DIR}/corev_apu/riscv-dbg/src/dm_csrs.sv +${DIR}/corev_apu/riscv-dbg/src/dmi_cdc.sv +${DIR}/corev_apu/riscv-dbg/src/dmi_jtag.sv +${DIR}/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv +${DIR}/corev_apu/riscv-dbg/src/dm_mem.sv +${DIR}/corev_apu/riscv-dbg/src/dm_sba.sv +${DIR}/corev_apu/riscv-dbg/src/dm_top.sv +${DIR}/corev_apu/rv_plic/rtl/rv_plic_target.sv +${DIR}/corev_apu/rv_plic/rtl/rv_plic_gateway.sv +${DIR}/corev_apu/rv_plic/rtl/plic_regmap.sv +${DIR}/corev_apu/rv_plic/rtl/plic_top.sv +${DIR}/corev_apu/riscv-dbg/debug_rom/debug_rom.sv +${DIR}/corev_apu/register_interface/src/apb_to_reg.sv +${DIR}/vendor/pulp-platform/axi/src/axi_multicut.sv +${DIR}/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv +${DIR}/vendor/pulp-platform/common_cells/src/rstgen.sv +${DIR}/vendor/pulp-platform/common_cells/src/addr_decode.sv +${DIR}/vendor/pulp-platform/common_cells/src/stream_register.sv +${DIR}/vendor/pulp-platform/axi/src/axi_cut.sv +${DIR}/vendor/pulp-platform/axi/src/axi_join.sv +${DIR}/vendor/pulp-platform/axi/src/axi_delayer.sv +${DIR}/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv +${DIR}/vendor/pulp-platform/axi/src/axi_id_prepend.sv +${DIR}/vendor/pulp-platform/axi/src/axi_atop_filter.sv +${DIR}/vendor/pulp-platform/axi/src/axi_err_slv.sv +${DIR}/vendor/pulp-platform/axi/src/axi_mux.sv +${DIR}/vendor/pulp-platform/axi/src/axi_demux.sv +${DIR}/vendor/pulp-platform/axi/src/axi_xbar.sv +${DIR}/vendor/pulp-platform/common_cells/src/cdc_2phase.sv +${DIR}/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv +${DIR}/vendor/pulp-platform/common_cells/src/spill_register.sv +${DIR}/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv +${DIR}/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv +${DIR}/vendor/pulp-platform/common_cells/src/stream_delay.sv +${DIR}/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv +${DIR}/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv +${DIR}/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv +${DIR}/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv +${DIR}/corev_apu/tb/rvfi_tracer.sv +${DIR}/corev_apu/tb/common/uart.sv +${DIR}/corev_apu/tb/common/SimDTM.sv +${DIR}/corev_apu/tb/common/SimJTAG.sv +${DIR}/corev_apu/fpga/src/ariane_peripherals_xilinx.sv +${DIR}/corev_apu/fpga/src/ariane_xilinx.sv +${DIR}/corev_apu/fpga/src/fan_ctrl.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/axis_gmii_rx.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/axis_gmii_tx.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/dualmem_widen.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii_fifo.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/eth_mac_1g.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/framing_top.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/iddr.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/oddr.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/rgmii_core.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/rgmii_lfsr.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/rgmii_phy_if.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/rgmii_soc.sv +${DIR}/corev_apu/fpga/src/ariane-ethernet/ssio_ddr_in.sv +${DIR}/common/local/util/tc_sram_fpga_wrapper.sv +${DIR}/common/local/util/hpdcache_sram_1rw.sv +${DIR}/common/local/util/hpdcache_sram_wbyteenable_1rw.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv +${DIR}/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/unread.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/unread.sv new file mode 100644 index 0000000000000000000000000000000000000000..aa55a0e4e41c1105ef47db094663ae7e09bc93c0 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/assets/unread.sv @@ -0,0 +1,26 @@ +`define TARGET_VIVADO +// Copyright 2018 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Florian Zaruba, ETH Zurich +// Date: 29.10.2018 +// Description: Dummy circuit to mitigate Open Pin warnings + +/* verilator lint_off UNUSED */ +module unread ( + input logic d_i +); + // Vivado treats this module as black box otherwise +`ifdef TARGET_VIVADO + logic x; + assign d_i = x; +`endif +endmodule +/* verilator lint_on UNUSED */ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..b895f7364a5cef2a7277758a157f677757f64952 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/custom_top_wrapper.sv @@ -0,0 +1,153 @@ +// Author: Stefano Mercogliano +// Description: +// This module is intended as a top-level wrapper for the custom_cv64a6 +// unit used in the SoC rtl (in the Socket). It wraps the CV64A6 CPU from OpenHW. +// By default, CV64A6 expects a configuration file describing its extensions +// Cache sizes and microarchitectural features, such as RAS or BTB size. +// We use a slightly modified config file suited on our needs in ./assets. +// Extensions supported are: I M A F D C H + + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" + +`include "axi_typedef.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // TODO121: Automatically align with config + parameter LOCAL_AXI_DATA_WIDTH = 64, + parameter LOCAL_AXI_ADDR_WIDTH = 64, + parameter LOCAL_AXI_STRB_WIDTH = LOCAL_AXI_DATA_WIDTH / 8, + parameter LOCAL_AXI_ID_WIDTH = 4, + parameter LOCAL_AXI_REGION_WIDTH = 4, + parameter LOCAL_AXI_LEN_WIDTH = 8, + parameter LOCAL_AXI_SIZE_WIDTH = 3, + parameter LOCAL_AXI_BURST_WIDTH = 2, + parameter LOCAL_AXI_LOCK_WIDTH = 1, + parameter LOCAL_AXI_CACHE_WIDTH = 4, + parameter LOCAL_AXI_PROT_WIDTH = 3, + parameter LOCAL_AXI_QOS_WIDTH = 4, + parameter LOCAL_AXI_VALID_WIDTH = 1, + parameter LOCAL_AXI_READY_WIDTH = 1, + parameter LOCAL_AXI_LAST_WIDTH = 1, + parameter LOCAL_AXI_RESP_WIDTH = 2, + parameter LOCAL_AXI_USER_WIDTH = 64 + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + // Subsystem Clock - SUBSYSTEM + input logic clk_i, + // Asynchronous reset active low - SUBSYSTEM + input logic rst_ni, + // Reset boot address - SUBSYSTEM + input logic [64-1:0] boot_addr_i, + // Hard ID reflected as CSR - SUBSYSTEM + input logic [64-1:0] hart_id_i, + // Level sensitive (async) interrupts - SUBSYSTEM + input logic [1:0] irq_i, + // Inter-processor (async) interrupt - SUBSYSTEM + input logic ipi_i, + // Timer (async) interrupt - SUBSYSTEM + input logic time_irq_i, + // Debug (async) request - SUBSYSTEM + input logic debug_req_i, + // Probes to build RVFI, can be left open when not used - RVFI + // output rvfi_probes_t rvfi_probes_o, + // // CVXIF request - SUBSYSTEM + // output cvxif_req_t cvxif_req_o, + // // CVXIF response - SUBSYSTEM + // input cvxif_resp_t cvxif_resp_i, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // AXI Master Interface Array + `DEFINE_AXI_MASTER_PORTS(m, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH) +); + + // Baseline noc_req_t type is the axi_typedef.svh axi format + `AXI_TYPEDEF_ALL( + axi, + logic [LOCAL_AXI_ADDR_WIDTH-1:0], + logic [LOCAL_AXI_ID_WIDTH-1:0], + logic [LOCAL_AXI_DATA_WIDTH-1:0], + logic [LOCAL_AXI_STRB_WIDTH-1:0], + logic [LOCAL_AXI_USER_WIDTH-1:0] // This is for the user field, which is missing from our interface (or unused) + ) + + axi_req_t axi_req; + axi_resp_t axi_rsp; + + cva6 #( + + ) cva6_u ( + + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .boot_addr_i ( boot_addr_i ), + .hart_id_i ( hart_id_i ), + .irq_i ( irq_i ), + .ipi_i ( ipi_i ), + .time_irq_i ( time_irq_i ), + .debug_req_i ( debug_req_i ), + .rvfi_probes_o ( ), + .cvxif_req_o ( ), + .cvxif_resp_i ( '0 ), + .noc_req_o ( axi_req ), + .noc_resp_i ( axi_rsp ) + ); + + // Map master port signals + assign m_axi_awid = axi_req.aw.id; + assign m_axi_awaddr = axi_req.aw.addr; + assign m_axi_awlen = axi_req.aw.len; + assign m_axi_awsize = axi_req.aw.size; + assign m_axi_awburst = axi_req.aw.burst; + assign m_axi_awlock = axi_req.aw.lock; + assign m_axi_awcache = axi_req.aw.cache; + assign m_axi_awprot = axi_req.aw.prot; + assign m_axi_awqos = axi_req.aw.qos; + assign m_axi_awregion = axi_req.aw.region; + assign m_axi_awvalid = axi_req.aw_valid; + assign m_axi_wdata = axi_req.w.data; + assign m_axi_wstrb = axi_req.w.strb; + assign m_axi_wlast = axi_req.w.last; + assign m_axi_wvalid = axi_req.w_valid; + assign m_axi_bready = axi_req.b_ready; + assign m_axi_araddr = axi_req.ar.addr; + assign m_axi_arlen = axi_req.ar.len; + assign m_axi_arsize = axi_req.ar.size; + assign m_axi_arburst = axi_req.ar.burst; + assign m_axi_arlock = axi_req.ar.lock; + assign m_axi_arcache = axi_req.ar.cache; + assign m_axi_arprot = axi_req.ar.prot; + assign m_axi_arqos = axi_req.ar.qos; + assign m_axi_arregion = axi_req.ar.region; + assign m_axi_arvalid = axi_req.ar_valid; + assign m_axi_rready = axi_req.r_ready; + assign m_axi_arid = axi_req.ar.id; + + assign axi_rsp.aw_ready = m_axi_awready; + assign axi_rsp.w_ready = m_axi_wready; + assign axi_rsp.b.id = m_axi_bid; + assign axi_rsp.b.resp = m_axi_bresp; + assign axi_rsp.b_valid = m_axi_bvalid; + assign axi_rsp.ar_ready = m_axi_arready; + assign axi_rsp.r.id = m_axi_rid; + assign axi_rsp.r.data = m_axi_rdata; + assign axi_rsp.r.resp = m_axi_rresp; + assign axi_rsp.r.last = m_axi_rlast; + assign axi_rsp.r_valid = m_axi_rvalid; + +endmodule : custom_top_wrapper diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..eb0b9f3625f9ea64a6ba8614794b485166c4fbeb --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_cv64a6/fetch_sources.sh @@ -0,0 +1,105 @@ +#!/bin/bash +# Author: Stefano Mercogliano +# Description: +# This script is used to fetch CV64A6 Sources from OpenHW repo. +# It is updated to the latest release till Feb 2025. +# We use the stock configuration file from OpenHW repo, with some +# Modifications to make it fit also for the embedded profile and on FPGA + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +# Directories +RTL_DIR=$(pwd)/rtl +mkdir ${RTL_DIR} + +ASSETS_DIR=$(pwd)/assets + +####################################### +# Fetch CVA6 sources and depencencies # +####################################### + +# clone repo ( Release v5.3.0 Feb 3 2025 ) +GIT_URL=https://github.com/openhwgroup/cva6.git +GIT_TAG=v5.3.0 +CLONE_DIR=$(pwd)/cva6 +FLIST=${ASSETS_DIR}/flist + +printf "${YELLOW}[FETCH_SOURCES] Cloning source repository${NC}\n" +git clone ${GIT_URL} -b ${GIT_TAG} --depth 1 ${CLONE_DIR} +cd ${CLONE_DIR}; +git submodule update --init --recursive +cd ..; + +###################### +# Prepare file lists # +###################### + +# Load file lines into an array +mapfile -t sources < ${ASSETS_DIR}/sources.flist +mapfile -t headers < ${ASSETS_DIR}/headers.flist + +# Replace ${DIR} with ${CLONE_DIR} in each element +for i in "${!sources[@]}"; do sources[$i]="${sources[$i]//\$\{DIR\}/${CLONE_DIR}}"; done +for i in "${!headers[@]}"; do headers[$i]="${headers[$i]//\$\{DIR\}/${CLONE_DIR}}"; done + +################################ +# Move source files to RTL dir # +################################ + +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into rtl${NC}\n" s +for rtl_file in "${sources[@]}" ; do + cp $rtl_file ${RTL_DIR} +done; + +################################ +# Move header files to RTL dir # +################################ + +printf "${YELLOW}[FETCH_SOURCES] Copy all headers into rtl${NC}\n" s +for rtl_file in "${headers[@]}" ; do + + filename=$(basename "$rtl_file") + + if [[ "$rtl_file" == *"axi"* ]]; then + filename="axi_${filename}" + elif [[ "$rtl_file" == *"register_interface"* ]]; then + filename="register_interface_${filename}" + fi + + cp "$rtl_file" "${RTL_DIR}/${filename}" + +done; + +################# +# Patch sources # +################# + +# Loop through all files in the rtl directory +echo -e "${YELLOW}[PATCH_SOURCES] Patching include paths for flat includes and specific substitutions${NC}" +for rtl_file in ${RTL_DIR}/*; do + if [[ -f $rtl_file ]]; then + # Substitute AXI includes + sed -i "s|\`include \"axi/typedef.svh\"|\`include \"axi_typedef.svh\"|g" $rtl_file + sed -i "s|\`include \"axi/assign.svh\"|\`include \"axi_assign.svh\"|g" $rtl_file + + # Flatten remaining includes + sed -i 's#`include "[^/]*/\([^"]*\.svh\)"#`include "\1"#g' $rtl_file + fi +done + +# Selectively patch exe_stage: superscalarity on forwarding signals is not supported (in the current version) +sed -i '/<=/ s/rs1_forwarding_i/rs1_forwarding_i[0]/g' ${RTL_DIR}/ex_stage.sv +sed -i '/<=/ s/rs2_forwarding_i/rs2_forwarding_i[0]/g' ${RTL_DIR}/ex_stage.sv + +# The unread.sv file used in the openhw repo is not VIVADO compatible. +# Therefore we save the PULP one in the assets and copy it on demand +cp ${ASSETS_DIR}/unread.sv ${RTL_DIR} + +# Symbolic link configuration file. Check in assets for further info +ln -s ${ASSETS_DIR}/cv64a6_config_pkg.sv ${RTL_DIR} + +# Info +echo -e "${GREEN}[FETCH_SOURCES] Completed${NC}" \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..df1e7be0eea008e22cd77d5ba67c8efdaf19b87f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/.gitignore @@ -0,0 +1,7 @@ +build +Vitis_workspace/ +conv_hbus + +.Xil +xcd.log +*.zip diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..77e7b06447bd3dd957291be51948125412419b7e --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/Makefile @@ -0,0 +1,54 @@ +# Author: Vincenzo Merola +# Description: +# This Makefile uses Vitis compiler to simulate and synthesize HLS kernel + +DIR = conv_hbus + +VITIS_HLS = vitis-run --mode hls +VPP = v++ +VFLAGS = -c --mode hls +CSIM = ${VITIS_HLS} --csim +COSIM = ${VITIS_HLS} --cosim +SYN = ${VPP} ${VFLAGS} +PACK = ${VITIS_HLS} --package +IP = ${DIR}_hls + +CONFIG = --config src/hls_config.cfg +WORK_DIR = --work_dir ${DIR} + + +.PHONY: csim +csim: + @echo "[INFO] C-Simulation starting..." + ${CSIM} ${CONFIG} ${WORK_DIR} + @echo "[INFO] C-Simulation ended" + + +.PHONY: syn +syn: + @echo "Synthesis starting..." + ${SYN} ${CONFIG} ${WORK_DIR} + @echo "[INFO] Synthesis ended" + + +.PHONY: cosim +cosim: + @echo "[INFO] Cosimulation starting ..." + ${COSIM} ${CONFIG} ${WORK_DIR} + @echo "[INFO] Cosimulation ended" + + +.PHONY: package +package: + @echo "[INFO] Packaging IP..." + ${PACK} ${CONFIG} ${WORK_DIR} + @echo "[INFO] Packaging ended" + + +.PHONY: clean +clean: + @echo "[INFO] Cleaning..." + rm -f ${IP}.zip + rm -fr ${DIR} + rm -f xcd.log + rm -fr .Xil \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/conv_hbus/hls/impl/ip/drivers/krnl_conv_hbus_v1_0/src/xkrnl_conv_hbus_hw.h b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/conv_hbus/hls/impl/ip/drivers/krnl_conv_hbus_v1_0/src/xkrnl_conv_hbus_hw.h new file mode 100644 index 0000000000000000000000000000000000000000..41d3aca030883f536e6b4cb25f87d469c7e01f7f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/conv_hbus/hls/impl/ip/drivers/krnl_conv_hbus_v1_0/src/xkrnl_conv_hbus_hw.h @@ -0,0 +1,74 @@ +// ============================================================== +// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.2 (64-bit) +// Tool Version Limit: 2024.11 +// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. +// +// ============================================================== +// control +// 0x00 : Control signals +// bit 0 - ap_start (Read/Write/COH) +// bit 1 - ap_done (Read) +// bit 2 - ap_idle (Read) +// bit 3 - ap_ready (Read/COR) +// bit 4 - ap_continue (Read/Write/SC) +// bit 7 - auto_restart (Read/Write) +// bit 9 - interrupt (Read) +// others - reserved +// 0x04 : Global Interrupt Enable Register +// bit 0 - Global Interrupt Enable (Read/Write) +// others - reserved +// 0x08 : IP Interrupt Enable Register (Read/Write) +// bit 0 - enable ap_done interrupt (Read/Write) +// bit 1 - enable ap_ready interrupt (Read/Write) +// others - reserved +// 0x0c : IP Interrupt Status Register (Read/TOW) +// bit 0 - ap_done (Read/TOW) +// bit 1 - ap_ready (Read/TOW) +// others - reserved +// 0x10 : Data signal of I +// bit 31~0 - I[31:0] (Read/Write) +// 0x14 : Data signal of I +// bit 31~0 - I[63:32] (Read/Write) +// 0x18 : reserved +// 0x1c : Data signal of W +// bit 31~0 - W[31:0] (Read/Write) +// 0x20 : Data signal of W +// bit 31~0 - W[63:32] (Read/Write) +// 0x24 : reserved +// 0x28 : Data signal of O +// bit 31~0 - O[31:0] (Read/Write) +// 0x2c : Data signal of O +// bit 31~0 - O[63:32] (Read/Write) +// 0x30 : reserved +// 0x34 : Data signal of N_input +// bit 7~0 - N_input[7:0] (Read/Write) +// others - reserved +// 0x38 : reserved +// 0x3c : Data signal of C_input +// bit 7~0 - C_input[7:0] (Read/Write) +// others - reserved +// 0x40 : reserved +// 0x44 : Data signal of K_input +// bit 7~0 - K_input[7:0] (Read/Write) +// others - reserved +// 0x48 : reserved +// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) + +#define XKRNL_CONV_HBUS_CONTROL_ADDR_AP_CTRL 0x00 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_GIE 0x04 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_IER 0x08 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_ISR 0x0c +#define XKRNL_CONV_HBUS_CONTROL_ADDR_I_DATA 0x10 +#define XKRNL_CONV_HBUS_CONTROL_BITS_I_DATA 64 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_W_DATA 0x1c +#define XKRNL_CONV_HBUS_CONTROL_BITS_W_DATA 64 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_O_DATA 0x28 +#define XKRNL_CONV_HBUS_CONTROL_BITS_O_DATA 64 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_N_INPUT_DATA 0x34 +#define XKRNL_CONV_HBUS_CONTROL_BITS_N_INPUT_DATA 8 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_C_INPUT_DATA 0x3c +#define XKRNL_CONV_HBUS_CONTROL_BITS_C_INPUT_DATA 8 +#define XKRNL_CONV_HBUS_CONTROL_ADDR_K_INPUT_DATA 0x44 +#define XKRNL_CONV_HBUS_CONTROL_BITS_K_INPUT_DATA 8 + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/hls_config.cfg b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/hls_config.cfg new file mode 100644 index 0000000000000000000000000000000000000000..bd53130b2fd3936c9763318a7fe357372afae454 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/hls_config.cfg @@ -0,0 +1,30 @@ +part=xcu250-figd2104-2L-e + +[hls] +flow_target=vitis +# 333 Mhz +clock=3ns + +package.output.format=ip_catalog +package.output.file=../conv_hbus +package.ip.vendor=vincenzo_maisto +package.ip.library=hls +package.ip.name=conv_hbus +package.ip.version=1.0 +package.output.syn=false + +tb.file=krnl_conv_hbus_tb.cpp + +syn.file=krnl_conv_hbus.cpp +syn.file=krnl_conv_hbus.h +syn.interface.m_axi_auto_max_ports=false +syn.interface.m_axi_max_widen_bitwidth=512 +syn.interface.m_axi_alignment_byte_size=64 + +# csim.code_analyzer=1 + +syn.top=krnl_conv_hbus + +csim.sanitize_address=1 +csim.sanitize_undefined=1 +csim.clean=True \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus.cpp b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus.cpp new file mode 100644 index 0000000000000000000000000000000000000000..30f2e29fa50f3f1df34b564e6b1b56c4addee1b7 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus.cpp @@ -0,0 +1,128 @@ +// Author: Vincenzo Maisto +// Description: +// HLS implementation of a CONV2D engine. +// Version HBUS: Wide M_AXI port for HBUS. + +// Headers +#include // For printf() +#include // For assert() +#include "krnl_conv_hbus.h" + +void krnl_conv_hbus ( + m_axi_port_type_t * I, + m_axi_port_type_t * W, + m_axi_port_type_t * O, + uint8_t N_input, + uint8_t C_input, + uint8_t K_input + ) { + + #pragma HLS INTERFACE mode=m_axi depth=((SIZE_I/sizeof(m_axi_port_type_t))) bundle=gmem0 port=I \ + max_read_burst_length=16 \ + max_widen_bitwidth=512 \ + max_write_burst_length=16 + + #pragma HLS INTERFACE mode=m_axi depth=((SIZE_W/sizeof(m_axi_port_type_t))+1) bundle=gmem0 port=W \ + max_read_burst_length=16 \ + max_widen_bitwidth=512 \ + max_write_burst_length=16 + + #pragma HLS INTERFACE mode=m_axi depth=((SIZE_O/sizeof(m_axi_port_type_t))+1) bundle=gmem0 port=O \ + max_read_burst_length=16 \ + max_widen_bitwidth=512 \ + max_write_burst_length=16 \ + num_read_outstanding=16 + + // Help the compiler infer minimum loop iterations + assert ( N_input > 0 ); + assert ( K_input > 0 ); + assert ( C_input > 0 ); + + // Pre-load Input feature map + #define FETCH_LEN_I ((SIZE_I/sizeof(m_axi_port_type_t))) // No need for +1, since it is already m_axi_port_type_t-aligned + m_axi_port_type_t I_fetch_line [FETCH_LEN_I] = {0}; + // printf("FETCH_LEN_I %lu\n\r", FETCH_LEN_I); + // printf("sizeof(m_axi_port_type_t) %u\n\r", sizeof(m_axi_port_type_t)); + // printf("I [ 0 ] = %s\n\r", I [ 0 ].to_string(16).c_str()); + // printf("I [ 1 ] = %s\n\r", I [ 1 ].to_string(16).c_str()); + // printf("I [ 2 ] = %s\n\r", I [ 2 ].to_string(16).c_str()); + // printf("I [ 3 ] = %s\n\r", I [ 3 ].to_string(16).c_str()); + // printf("I [ 4 ] = %s\n\r", I [ 4 ].to_string(16).c_str()); + // printf("I [ 5 ] = %s\n\r", I [ 5 ].to_string(16).c_str()); + // printf("I [ 6 ] = %s\n\r", I [ 6 ].to_string(16).c_str()); + // Fetch line-wise + for ( uint64_t fetch_index = 0; fetch_index < FETCH_LEN_I; fetch_index++ ) { + I_fetch_line [ fetch_index ] = I [ fetch_index ]; + } + // Fetch byte-wise + // NOTE: no need, since it is already m_axi_port_type_t-aligned + + // Pre-fetch all filter weights + #define FETCH_LEN_W ((SIZE_W/sizeof(m_axi_port_type_t))+1) + m_axi_port_type_t W_fetch_line [FETCH_LEN_W] = {0}; + // printf("FETCH_LEN_W %lu\n\r", FETCH_LEN_W); + // printf("W [ 0 ] = %s\n\r", W [ 0 ].to_string(16).c_str()); + // printf("W [ 1 ] = %s\n\r", W [ 1 ].to_string(16).c_str()); + // printf("W [ 2 ] = %s\n\r", W [ 2 ].to_string(16).c_str()); + // Fetch line-wise + for ( uint64_t fetch_index = 0; fetch_index < (FETCH_LEN_W-1); fetch_index++ ) { + W_fetch_line [ fetch_index ] = W [ fetch_index ]; + } + // Fetch byte-wise + #define FETCH_LEN_W_LAST (SIZE_W) + for ( uint64_t fetch_index = (SIZE_W/sizeof(m_axi_port_type_t)); fetch_index < FETCH_LEN_W_LAST; fetch_index++ ) { + ((uint8_t*)W_fetch_line) [ fetch_index ] = ((uint8_t*)W) [ fetch_index ]; + } + + // For input batch size + for ( uint8_t n = 0; n < N_input; n++ ) { + + // Local buffer for I [N][C][ Y][ X] + target_type_t I_local [C * Y * X]; + for ( uint64_t cyx = 0; cyx < (C * X * Y); cyx++ ) { + ((target_type_t*)I_fetch_line) [ cyx ] = ((target_type_t*)I) [(n * C * X * Y) + cyx]; + } + + // For output batch size + for ( uint8_t k = 0; k < K_input; k++ ) { + + // Reset accumulator + target_type_t accumulator[Y1 * X1] = {0}; + + // For each input channel + for ( uint8_t c = 0; c < C_input; c++ ) { + // Local buffers for W [K][C][R][S] + target_type_t W_local [R * S]; + // Preload buffer + for ( uint8_t rs = 0; rs < R * S; rs++ ) { + #define INDEX_W ( ( ( k * C_input ) + c ) * R * S + rs ) + #define INDEX_W_LOCAL ( rs ) + W_local [INDEX_W_LOCAL] = ((target_type_t*)W_fetch_line) [INDEX_W]; + #undef INDEX_W_LOCAL + } // rs < R * S + + // For I dimensions Y1 and X1 + for ( uint8_t y1 = 0; y1 < Y1; y1++ ) { + for ( uint8_t x1 = 0; x1 < X1; x1++ ) { + // Compute + for ( uint8_t r = 0; r < R; r++ ) { + for ( uint8_t s = 0; s < S; s++ ) { + #define INDEX_W_LOCAL ( r * S + s ) + #define INDEX_I ( ( ( c * Y ) + (y1+r) ) * X + (x1+s) ) + #define INDEX_ACC ( y1 * X1 + x1 ) + accumulator[INDEX_ACC] += W_local [INDEX_W_LOCAL] * ((target_type_t*)I_fetch_line) [INDEX_I]; + #undef INDEX_W_LOCAL + } // s < S + } // r < R + } // x1 < x1 + } // y1 < Y1 + } // c < C + + // Store result + for ( uint8_t y1x1 = 0; y1x1 < Y1 * X1; y1x1++ ) { + #define INDEX_O ( ( ( n * K_input ) + k ) * Y1 * X1 + y1x1 ) + ((target_type_t*)O) [ INDEX_O ] = accumulator [y1x1]; + } // y1x1 < Y1 * X1 + } // k < K + } // n < N +} // krnl_conv_hbus() \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus.h b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus.h new file mode 100644 index 0000000000000000000000000000000000000000..21d526a8889c7074b372dce71e84ea0326f3a1e2 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus.h @@ -0,0 +1,79 @@ +#ifndef __CONV2D_HBUS_H +#define __CONV2D_HBUS_H + +#include // uint32_t +#include "ap_int.h" + +/////////////////////////// +// Notation from MAESTRO // +/////////////////////////// + +// Tensor Dimension Notation +// Input Batch N +#define N 1 +// Output Channel K +#define K 3 +// Input Channel C +#define C 6 +// Input Row Y +#define Y 8 +// Input Column X +#define X 8 +// Filter Row R +#define R 3 +// Filter Column S +#define S 3 +// Output Row Y’ +#define Y1 6 +// Output Column X’ +#define X1 6 + +// Tensor Tensor Index +// Input Activation I [n][c][y][x] +// Filter Weight W [k][c][r][s] +// Partial Sum P [n][k][c][y’][x’][r][s] +// Output Activation O [n][k][y’][x’] + +// Tensor sizes +#define SIZE_I ( N * C * Y * X ) +#define SIZE_W ( K * C * R * S ) +#define SIZE_O ( N * K * Y1 * X1 ) + +typedef uint8_t target_type_t; +#ifdef MOCK_AP_INT + typedef uint8_t m_axi_port_type_t; +#else + #define M_AXI_DWIDTH 512 + typedef ap_uint m_axi_port_type_t; +#endif + + +void krnl_conv_hbus ( + m_axi_port_type_t * I, + m_axi_port_type_t * W, + m_axi_port_type_t * O, + uint8_t N_input, + uint8_t C_input, + uint8_t K_input + ); + + +void init_data ( + target_type_t I[N][C][ Y][ X], + target_type_t W[K][C][ R][ S], + target_type_t O[N][K][Y1][X1] + ); + +void compute_expected ( + target_type_t I[N][C][ Y][ X], + target_type_t W[K][C][ R][ S], + target_type_t expected[N][K][Y1][X1] + ); + +int check_values ( + target_type_t out [N][K][Y1][X1], + target_type_t expected[N][K][Y1][X1] + ); + + +#endif // __CONV_OPT1_H__ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus_tb.cpp b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus_tb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..417b006e9e6847aadb62e4cb45161b6e7d75de6e --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/krnl_conv_hbus_tb.cpp @@ -0,0 +1,52 @@ +#include "krnl_conv_hbus.h" +#include // For printf() + +// NOTE: Dirty workaround to Vitis HLS project configuration. Just include the source file here. +#include "utils.h" + +int main(int argc, const char **argv) { + + // Pre-allocate tensors, with alignment + target_type_t I [N][C][ Y][ X]__attribute__((aligned(sizeof(m_axi_port_type_t)))); + target_type_t W [K][C][ R][ S]__attribute__((aligned(sizeof(m_axi_port_type_t)))); + target_type_t O [N][K][Y1][X1]__attribute__((aligned(sizeof(m_axi_port_type_t)))); + target_type_t expected[N][K][Y1][X1] = {0}; + + // Init + printf("[INFO] Init data\n"); + init_data(I, W, O); + + // Compute locally + printf("[INFO] Compute expected\n"); + compute_expected(I, W, expected); + + // Call to kernel + printf("[INFO] Call to kernel\n"); + krnl_conv_hbus( + (m_axi_port_type_t*)I, + (m_axi_port_type_t*)W, + (m_axi_port_type_t*)O, + N, C, K + ); + + // Dump + // printf("I **********************************:\n\r"); print_tensor((target_type_t*)I,N,C,Y,X); + // printf("W **********************************:\n\r"); print_tensor((target_type_t*)W,K,C,R,S); + // printf("expected ***************************:\n\r"); print_tensor((target_type_t*)expected,N,K,Y1,X1); + // printf("O **********************************:\n\r"); print_tensor((target_type_t*)O,N,K,Y1,X1); + // printf("++++++++++++++++++++++++++++++++++ 0x%08lx\n\r",((uint64_t*)I)[0] ); + + // Check result + printf("[INFO] Checking results...\n"); + bool result = check_values(O, expected); + if ( !result ) { + printf("[ERROR] Check failed!\n"); + return 1; + } + else { + printf("[INFO] Check successful!\n"); + } + + return 0; + +} \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/utils.h b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/utils.h new file mode 100644 index 0000000000000000000000000000000000000000..41852dbcdf49ef433f0a6f8e770639a6c2c9beca --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/hw/src/utils.h @@ -0,0 +1,125 @@ +#ifndef __UTILS_C_ +#define __UTILS_C_ + +#include +#include + +// Init I and W tensors with pseudo-random values +// Init O tensor with constant 0x55555555 +void init_data ( + target_type_t I[N][C][ Y][ X], + target_type_t W[K][C][ R][ S], + target_type_t O[N][K][Y1][X1] + ) { + + // Init I + for ( uint32_t n = 0; n < N; n++ ) + for ( uint32_t c = 0; c < C; c++ ) + for ( uint32_t y = 0; y < Y; y++ ) + for ( uint32_t x = 0; x < X; x++ ) + I[n][c][y][x] = (x << 4) + y; + + // Init W + for ( uint32_t k = 0; k < K; k++ ) + for ( uint32_t c = 0; c < C; c++ ) + for ( uint32_t r = 0; r < R; r++ ) + for ( uint32_t s = 0; s < S; s++ ) + W[k][c][s][r] = (s << 4) + r; + + // Init O + for ( uint32_t n = 0; n < N; n++ ) + for ( uint32_t k = 0; k < K; k++ ) + for ( uint32_t y1 = 0; y1 < Y1; y1++ ) + for ( uint32_t x1 = 0; x1 < X1; x1++ ) + O[n][k][y1][x1] = (target_type_t)0x55555555; + +} + +// Print num_batch x num_chan x num_rows x num_cols tensor +void print_tensor ( + target_type_t * data, + uint32_t num_batch, + uint32_t num_chan, + uint32_t num_rows, + uint32_t num_cols + ) { + for ( uint32_t n = 0; n < num_batch; n++ ) { + printf("Batch %u \n\r", n); + for ( uint32_t ch = 0; ch < num_chan; ch++ ) { + printf("\tChannel %u \n\r\t\t", ch); + for ( uint32_t r = 0; r < num_rows; r++ ) { + for ( uint32_t c = 0; c < num_cols; c++ ) { + printf("0x%02x ", ((target_type_t(*)[num_chan][num_rows][num_cols])data)[n][ch][r][c]); + // #define INDEX ( ( n * num_chan + ch ) * num_rows + r ) * num_cols + c + // printf("0x%02x ", data[INDEX]); + } + printf("\n\r\t\t"); + } + printf("\n\r"); + } + printf("\n\r"); + } +} + +// Compute expected result with software +void compute_expected ( + target_type_t I[N][C][ Y][ X], + target_type_t W[K][C][ R][ S], + target_type_t expected[N][K][Y1][X1] + ) { + + for ( uint32_t n = 0; n < N; n++ ) { + for ( uint32_t k = 0; k < K; k++ ) { + for ( uint32_t c = 0; c < C; c++ ) { + for ( uint32_t y1 = 0; y1 < Y1; y1++ ) { + for ( uint32_t x1 = 0; x1 < X1; x1++ ) { + for ( uint32_t r = 0; r < R; r++ ) { + for ( uint32_t s = 0; s < S; s++ ) { + // O[n][k][y’][x’] += W[n][k][c][r][s] * I[n][c][y’+r][x’+s]; + expected[n][k][y1][x1] += W[k][c][r][s] * I[n][c][y1+r][x1+s]; + } // s < S + } // r < R + } // x1 < X1 + } // y1 < Y1 + } // c < C + } // k < K + } // n < N +} + +// Compare two output tensors +int check_values ( + target_type_t out [N][K][Y1][X1], + target_type_t expected[N][K][Y1][X1] + ) { + + // Compare + for ( uint32_t n = 0; n < N; n++ ) { + for ( uint32_t k = 0; k < K; k++ ) { + for ( uint32_t y1 = 0; y1 < Y1; y1++ ) { + for ( uint32_t x1 = 0; x1 < X1; x1++ ) { + if ( out[n][k][y1][x1] != expected[n][k][y1][x1] ) { + printf("[ERROR] Failing [%u,%u,%u,%u]: expected 0x%04x != 0x%04x\n\r", + n, k, y1, x1, + expected[n][k][y1][x1], + out [n][k][y1][x1] + ); + // Return immediately + return false; + } + // DEBUG + // printf("[INFO] Check [%u,%u,%u,%u]: expected 0x%04x == 0x%04x\n", + // n, k, y1, x1, + // expected[n][k][y1][x1], + // out [n][k][y1][x1] + // ); + + } + } + } + } + + // No error occurred + return true; +} + +#endif // __UTILS_C_ diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/sw/host.c b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/sw/host.c new file mode 100644 index 0000000000000000000000000000000000000000..d6f6977c02624d0ac01feb08d24fa6fa384e7347 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/conv_hbus/sw/host.c @@ -0,0 +1,189 @@ +// Author: Vincenzo Maisto +// Description: Baremetal host code for conv_hbus HLS IP core. + +#include "uninasoc.h" +#include "xlnx/xlnx.h" +#include "krnl_conv_hbus.h" +#include "utils.h" + +void dump_conv_hbus_csrs () { + // Read in order + uint32_t AP_CTRL = Xil_In32(Xkrnl_Control ); + uint32_t GIE = Xil_In32(Xkrnl_GIE ); + uint32_t IER = Xil_In32(Xkrnl_IER ); + uint32_t ISR = Xil_In32(Xkrnl_ISR ); + uint32_t AXI_I_ADDR = Xil_In32(Xkrnl_AXI_ADDR_I); + uint32_t AXI_W_ADDR = Xil_In32(Xkrnl_AXI_ADDR_W); + uint32_t AXI_O_ADDR = Xil_In32(Xkrnl_AXI_ADDR_O); + uint32_t AXI_N = Xil_In32(Xkrnl_N ); + uint32_t AXI_C = Xil_In32(Xkrnl_C ); + uint32_t AXI_K = Xil_In32(Xkrnl_K ); + + // Print + printf( "CSR DUMP:\n\r"); + // Use formatting, e.g. + // AP_CTRL = 0x0000 AXI_I_ADDR = 0x0000 + // GIE = 0x0000 AXI_W_ADDR = 0x0000 + // IER = 0x0000 AXI_O_ADDR = 0x0000 + // ISR = 0x0000 AXI_N = 0x0000 + // AXI_C = 0x0000 + // AXI_K = 0x0000 + printf( " AP_CTRL = 0x%04x ", AP_CTRL ); + printf( " AXI_I_ADDR = 0x%04x\n\r", AXI_I_ADDR ); + printf( " GIE = 0x%04x ", GIE ); + printf( " AXI_W_ADDR = 0x%04x\n\r", AXI_W_ADDR ); + printf( " IER = 0x%04x ", IER ); + printf( " AXI_O_ADDR = 0x%04x\n\r", AXI_O_ADDR ); + printf( " ISR = 0x%04x ", ISR ); + printf( " AXI_N = 0x%04x\n\r", AXI_N ); + printf( " AXI_C = 0x%04x\n\r", AXI_C ); + printf( " AXI_K = 0x%04x\n\r", AXI_K ); +} + +// Print each field of a control CSR word +void print_control_csr ( uint32_t csr_read_in ) { + // Print fields + printf("AP_CTRL = 0x%04x\n\r", csr_read_in); + printf(" START = 0x%x ", ( csr_read_in & AP_START ) >> (AP_START_BIT )); + printf(" DONE = 0x%x\n\r", ( csr_read_in & AP_DONE ) >> (AP_DONE_BIT )); + printf(" IDLE = 0x%x ", ( csr_read_in & AP_IDLE ) >> (AP_IDLE_BIT )); + printf(" READY = 0x%x\n\r", ( csr_read_in & AP_READY ) >> (AP_READY_BIT )); + printf(" CONTINUE = 0x%x ", ( csr_read_in & AP_CONTINUE ) >> (AP_CONTINUE_BIT )); + printf(" AUTORESTART = 0x%x\n\r", ( csr_read_in & AP_AUTORESTART) >> (AP_AUTORESTART_BIT)); + printf(" INTERRUPT = 0x%x\n\r", ( csr_read_in & AP_INTERRUPT) >> (AP_INTERRUPT_BIT)); +} + +#define PRINT_LEAP 10 + +int main() { + + // Control CSR + uint32_t csr_read; + uint32_t cnt; + + // Init platform + uninasoc_init(); + + // Pre-allocate tensors, aligned to power of two + #define ALIGN_I 2048 + #define ALIGN_W 1024 + #define ALIGN_O 1024 + target_type_t I [N][C][ Y][ X]__attribute__((aligned(ALIGN_I))); + target_type_t W [K][C][ R][ S]__attribute__((aligned(ALIGN_W))); + target_type_t O [N][K][Y1][X1]__attribute__((aligned(ALIGN_O))); + target_type_t expected[N][K][Y1][X1] = {0}; + + printf("\n\r"); + printf("------------------\n\r"); + printf("- HLS CONV HBUS -\n\r"); + printf("------------------\n\r"); + printf("\n\r"); + + // Debug + printf("Convolution parameters:\n\r"); + printf(" I = 0x%p\n\r", (uintptr_t)I); + printf(" W = 0x%p\n\r", (uintptr_t)W); + printf(" O = 0x%p\n\r", (uintptr_t)O); + printf(" N = %hhu\n\r", (uint8_t)N); + printf(" C = %hhu\n\r", (uint8_t)C); + printf(" K = %hhu\n\r", (uint8_t)K); + printf(" Y = %hhu\n\r", (uint8_t) Y); + printf(" X = %hhu\n\r", (uint8_t) X); + printf(" R = %hhu\n\r", (uint8_t) R); + printf(" S = %hhu\n\r", (uint8_t) S); + printf(" Y1 = %hhu\n\r", (uint8_t) Y1); + printf(" X1 = %hhu\n\r", (uint8_t) X1); + + // Initializing input/output data + init_data(I, W, O); + + // Compute expected + printf("[INFO] Compute expected\n\r"); + compute_expected(I, W, expected); + + printf("[INFO] Waiting for idle...\n\r"); + // Reset counter + cnt = 0; + do { + // Increment counter + cnt++; + if ( cnt == PRINT_LEAP ) { + // Reset counter + cnt = 0; + // Read + csr_read = -1; + csr_read = Xil_In32(Xkrnl_Control); + // Print + print_control_csr(csr_read); + } + } while ( XKrnl_IsIdle() ); + + /////////////////////// + // Enable interrupts // + /////////////////////// + // Global Interrupts Enable + XKrnl_InterruptGlobalEnable(); + // Enable done and ready interrupts + XKrnl_InterruptEnable_ap_done(); + // XKrnl_InterruptEnable_ap_ready(); + + ///////////////////////// + // Starting the kernel // + ///////////////////////// + + // Writing input/output addresses + Xil_Out32(Xkrnl_AXI_ADDR_I, (uintptr_t)I); + Xil_Out32(Xkrnl_AXI_ADDR_W, (uintptr_t)W); + Xil_Out32(Xkrnl_AXI_ADDR_O, (uintptr_t)O); + Xil_Out32(Xkrnl_N, (uint8_t)N); + Xil_Out32(Xkrnl_C, (uint8_t)C); + Xil_Out32(Xkrnl_K, (uint8_t)K); + + // Enable auto-restart + XKrnl_EnableAutoRestart(); + // Raising ap_start to start the kernel + XKrnl_Start(); + + // Waiting for the kernel to finish (polling the ap_done control bit) + printf("[INFO] Waiting for done...\n\r"); + // Reset counter + cnt = 0; + do { + // Increment counter + cnt++; + if ( cnt == PRINT_LEAP ) { + // Reset counter + cnt = 0; + // Read + csr_read = -1; + csr_read = Xil_In32(Xkrnl_Control); + // Print + print_control_csr(csr_read); + } + } while ( XKrnl_IsDone() ); + + // Read pending interrupts + printf( " ISR = 0x%04x\n\r", XKrnl_InterruptGetStatus() ); + // Clear interrupts + XKrnl_InterruptClear_ap_done(); + // XKrnl_InterruptClear_ap_ready(); + // Read pending interrupts + printf( " ISR = 0x%04x\n\r", XKrnl_InterruptGetStatus() ); + + // // Write continue + // XKrnl_Continue(); + + // Checking results + printf("[INFO] Checking results...\n\r"); + bool result = check_values(O, expected); + if ( !result ) { + printf("[ERROR] Check failed!\n\r"); + return 1; + } + else { + printf("[INFO] Check successful!\n\r"); + } + + return 0; + +} \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/rebuild_hls.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/rebuild_hls.sh new file mode 100644 index 0000000000000000000000000000000000000000..fee5f23de6aa4eb68c280d46d5c86c20de328eb9 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/assets/rebuild_hls.sh @@ -0,0 +1,50 @@ +#!/bin/bash +# Author: Vincenzo Merola +# Author: Vincenzo Maisto +# Description: +# Rebuild HLS sources to Verilog and copy in rtl/ dir. +# Package C standalone drivers and copy to UninaSoC software dir + +# Colors +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +################### +# Local variables # +################### +TOP_DIR=$PWD + +# This script dir +WORK_DIR=$( dirname $( realpath -se ${BASH_SOURCE[0]} ) ) +cd $WORK_DIR +# Get the first dir in this path +HLS_DIR=$(realpath $(find ./ -maxdepth 1 -mindepth 1 -type d)) +COMPONENT_NAME=$(basename ${HLS_DIR}) + +# Clean old sources +RTL_DIR=$(realpath $WORK_DIR/../rtl) +printf "\n${YELLOW}[REBUILD_HLS] Cleaning old RTL from ${RTL_DIR} ${NC}\n" +rm -rf $(ls -A ${RTL_DIR}) +mkdir -p ${RTL_DIR} + +# Move into HLS project +cd ${HLS_DIR}/hw + +# Synthesizing and copying verilog rtl files +printf "\n${YELLOW}[REBUILD_HLS] Starting c-synthesis for HLS sources${NC}\n" +make clean +make syn +printf "\n${YELLOW}[REBUILD_HLS] Copying all sources into rtl${NC}\n" +cp ${HLS_DIR}/hw/${COMPONENT_NAME}/hls/syn/verilog/* ${RTL_DIR}/ + +# Packaging for the C driver files +# NOTE: requires Vitis HLS 2024 +CUSTOM_IP_NAME=$(basename $(realpath $WORK_DIR/..)) +printf "\n${YELLOW}[FETCH_SOURCES] Packaging for C standalone driver files${NC}\n" +make package + +# Back to top +cd ${TOP_DIR} +unset TOP_DIR diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..02efe3fcb9462010123a2faccaba540fa57a1c9f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/custom_top_wrapper.sv @@ -0,0 +1,116 @@ +// Author: Vincenzo Merola +// Description: Top level wrapper for HLS-generated IP, with configurable AXI master interface. + + +// Import headers +`include "uninasoc_mem.svh" +`include "uninasoc_axi.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + // AXI master parameters + localparam LOCAL_AXI_DATA_WIDTH = 512, + localparam LOCAL_AXI_ADDR_WIDTH = 32, + localparam LOCAL_AXI_ID_WIDTH = 4, + // AXI-lite slave parameters + localparam LOCAL_AXILITE_DATA_WIDTH = 32, + localparam LOCAL_AXILITE_ADDR_WIDTH = 32, + localparam LOCAL_AXILITE_ID_WIDTH = 4 + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + input logic clk_i, + input logic rst_ni, + output logic interrupt_o, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // AXI Master Interfaces + `DEFINE_AXI_MASTER_PORTS(gmem0, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH), + + // AXI Slave Interfaces + `DEFINE_AXILITE_SLAVE_PORTS(control, LOCAL_AXILITE_DATA_WIDTH, LOCAL_AXILITE_ADDR_WIDTH, LOCAL_AXILITE_ID_WIDTH) + +); + + // HLS top + krnl_conv_hbus krnl_conv_hbus_u ( + .ap_clk ( clk_i ), + .ap_rst_n ( rst_ni ), + .interrupt ( interrupt_o ), + // AXI-lite slave + .s_axi_control_AWVALID ( control_axilite_awvalid ), + .s_axi_control_AWREADY ( control_axilite_awready ), + .s_axi_control_AWADDR ( control_axilite_awaddr ), + .s_axi_control_WVALID ( control_axilite_wvalid ), + .s_axi_control_WREADY ( control_axilite_wready ), + .s_axi_control_WDATA ( control_axilite_wdata ), + .s_axi_control_WSTRB ( control_axilite_wstrb ), + .s_axi_control_ARVALID ( control_axilite_arvalid ), + .s_axi_control_ARREADY ( control_axilite_arready ), + .s_axi_control_ARADDR ( control_axilite_araddr ), + .s_axi_control_RVALID ( control_axilite_rvalid ), + .s_axi_control_RREADY ( control_axilite_rready ), + .s_axi_control_RDATA ( control_axilite_rdata ), + .s_axi_control_RRESP ( control_axilite_rresp ), + .s_axi_control_BVALID ( control_axilite_bvalid ), + .s_axi_control_BREADY ( control_axilite_bready ), + .s_axi_control_BRESP ( control_axilite_bresp ), + // AXI master + .m_axi_gmem0_AWVALID ( gmem0_axi_awvalid ), + .m_axi_gmem0_AWREADY ( gmem0_axi_awready ), + .m_axi_gmem0_AWADDR ( gmem0_axi_awaddr ), + .m_axi_gmem0_AWID ( gmem0_axi_awid ), + .m_axi_gmem0_AWLEN ( gmem0_axi_awlen ), + .m_axi_gmem0_AWSIZE ( gmem0_axi_awsize ), + .m_axi_gmem0_AWBURST ( gmem0_axi_awburst ), + .m_axi_gmem0_AWLOCK ( gmem0_axi_awlock ), + .m_axi_gmem0_AWCACHE ( gmem0_axi_awcache ), + .m_axi_gmem0_AWPROT ( gmem0_axi_awprot ), + .m_axi_gmem0_AWQOS ( gmem0_axi_awqos ), + .m_axi_gmem0_AWREGION ( gmem0_axi_awregion ), + .m_axi_gmem0_AWUSER ( gmem0_axi_awuser ), + .m_axi_gmem0_WVALID ( gmem0_axi_wvalid ), + .m_axi_gmem0_WREADY ( gmem0_axi_wready ), + .m_axi_gmem0_WDATA ( gmem0_axi_wdata ), + .m_axi_gmem0_WSTRB ( gmem0_axi_wstrb ), + .m_axi_gmem0_WLAST ( gmem0_axi_wlast ), + .m_axi_gmem0_WID ( gmem0_axi_wid ), + .m_axi_gmem0_WUSER ( gmem0_axi_wuser ), + .m_axi_gmem0_ARVALID ( gmem0_axi_arvalid ), + .m_axi_gmem0_ARREADY ( gmem0_axi_arready ), + .m_axi_gmem0_ARADDR ( gmem0_axi_araddr ), + .m_axi_gmem0_ARID ( gmem0_axi_arid ), + .m_axi_gmem0_ARLEN ( gmem0_axi_arlen ), + .m_axi_gmem0_ARSIZE ( gmem0_axi_arsize ), + .m_axi_gmem0_ARBURST ( gmem0_axi_arburst ), + .m_axi_gmem0_ARLOCK ( gmem0_axi_arlock ), + .m_axi_gmem0_ARCACHE ( gmem0_axi_arcache ), + .m_axi_gmem0_ARPROT ( gmem0_axi_arprot ), + .m_axi_gmem0_ARQOS ( gmem0_axi_arqos ), + .m_axi_gmem0_ARREGION ( gmem0_axi_arregion ), + .m_axi_gmem0_ARUSER ( gmem0_axi_aruser ), + .m_axi_gmem0_RVALID ( gmem0_axi_rvalid ), + .m_axi_gmem0_RREADY ( gmem0_axi_rready ), + .m_axi_gmem0_RDATA ( gmem0_axi_rdata ), + .m_axi_gmem0_RLAST ( gmem0_axi_rlast ), + .m_axi_gmem0_RID ( gmem0_axi_rid ), + .m_axi_gmem0_RUSER ( gmem0_axi_ruser ), + .m_axi_gmem0_RRESP ( gmem0_axi_rresp ), + .m_axi_gmem0_BVALID ( gmem0_axi_bvalid ), + .m_axi_gmem0_BREADY ( gmem0_axi_bready ), + .m_axi_gmem0_BRESP ( gmem0_axi_bresp ), + .m_axi_gmem0_BID ( gmem0_axi_bid ), + .m_axi_gmem0_BUSER ( gmem0_axi_buser ) + ); + +endmodule : custom_top_wrapper \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..98f57fdf7e6b464d3b152e19a697c143816482d3 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_hls_conv_hbus/fetch_sources.sh @@ -0,0 +1,24 @@ +#!/bin/bash +# Author: Vincenzo Merola +# Author: Vincenzo Maisto +# Description: Fetch HLS sources and build Verilog and C standalone drivers + +# Colors +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +WORK_DIR=$(pwd -P) +# Creating build/ dir +mkdir -p rtl +BUILD="$(pwd -P)/rtl" + +# Rebuild HLS sources +cd assets +source rebuild_hls.sh + +# Back to top +cd ${WORK_DIR} + +printf "\n${GREEN}[FETCH_SOURCES] Completed${NC}\n" \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..5e34423f140f3af4c6d5200688b181edffbcd0af --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/.gitignore @@ -0,0 +1 @@ +ibex/ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/assets/flist b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/assets/flist new file mode 100644 index 0000000000000000000000000000000000000000..f6df493d99043c7e51878abfe34e4dc5c56645fb --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/assets/flist @@ -0,0 +1,131 @@ +prim_count_pkg.sv +prim_count.sv +prim_secded_inv_hamming_72_64_enc.sv +prim_secded_72_64_dec.sv +prim_secded_hamming_72_64_dec.sv +prim_secded_inv_hamming_22_16_dec.sv +prim_secded_inv_64_57_dec.sv +prim_secded_39_32_enc.sv +prim_secded_72_64_enc.sv +prim_secded_hamming_22_16_dec.sv +prim_secded_inv_22_16_dec.sv +prim_secded_hamming_76_68_enc.sv +prim_secded_hamming_39_32_enc.sv +prim_secded_inv_64_57_enc.sv +prim_secded_inv_hamming_22_16_enc.sv +prim_secded_inv_hamming_76_68_enc.sv +prim_secded_28_22_enc.sv +prim_secded_inv_22_16_enc.sv +prim_secded_inv_39_32_enc.sv +prim_secded_hamming_22_16_enc.sv +prim_secded_pkg.sv +prim_secded_22_16_dec.sv +prim_secded_inv_28_22_dec.sv +prim_secded_64_57_dec.sv +prim_secded_64_57_enc.sv +prim_secded_hamming_76_68_dec.sv +prim_secded_22_16_enc.sv +prim_secded_28_22_dec.sv +prim_secded_inv_72_64_enc.sv +prim_secded_inv_39_32_dec.sv +prim_secded_inv_72_64_dec.sv +prim_secded_39_32_dec.sv +prim_secded_inv_hamming_76_68_dec.sv +prim_secded_hamming_72_64_enc.sv +prim_secded_inv_hamming_72_64_dec.sv +prim_secded_inv_28_22_enc.sv +prim_secded_inv_hamming_39_32_enc.sv +prim_secded_inv_hamming_39_32_dec.sv +prim_secded_hamming_39_32_dec.sv +prim_clock_gating.sv +prim_generic_and2.sv +prim_xilinx_flop.sv +prim_ram_1p_adv.sv +prim_util_pkg.sv +prim_assert.sv +prim_flop_macros.sv +prim_flop.sv +prim_and2.sv +prim_xilinx_buf.sv +prim_generic_clock_gating.sv +prim_onehot_mux.sv +prim_onehot_enc.sv +prim_generic_flop.sv +prim_prince.sv +prim_subst_perm.sv +prim_present.sv +prim_ram_1p.sv +ibex_pkg.sv +prim_generic_clock_mux2.sv +prim_lfsr.sv +prim_buf.sv +ibex_lockstep.sv +ibex_register_file_fpga.sv +ibex_register_file_latch.sv +ibex_top.sv +ibex_register_file_ff.sv +prim_ram_1p_scr.sv +prim_badbit_ram_1p.sv +prim_cipher_pkg.sv +ibex_decoder.sv +ibex_ex_block.sv +ibex_if_stage.sv +ibex_controller.sv +ibex_multdiv_slow.sv +ibex_branch_predict.sv +ibex_fetch_fifo.sv +ibex_prefetch_buffer.sv +ibex_compressed_decoder.sv +ibex_alu.sv +ibex_dummy_instr.sv +ibex_load_store_unit.sv +ibex_core.sv +ibex_multdiv_fast.sv +ibex_wb_stage.sv +ibex_cs_registers.sv +ibex_counter.sv +ibex_id_stage.sv +ibex_csr.sv +ibex_pmp.sv +prim_ram_1p_pkg.sv +prim_mubi32_sender.sv +prim_mubi16_dec.sv +prim_mubi28_dec.sv +prim_mubi8_sync.sv +prim_mubi_pkg.sv +prim_mubi4_sender.sv +prim_mubi20_dec.sv +prim_mubi24_dec.sv +prim_mubi16_sync.sv +prim_mubi24_sync.sv +prim_mubi8_dec.sv +prim_mubi12_sender.sv +prim_mubi32_sync.sv +prim_mubi4_dec.sv +prim_mubi12_dec.sv +prim_mubi28_sync.sv +prim_mubi28_sender.sv +prim_mubi12_sync.sv +prim_mubi24_sender.sv +prim_mubi20_sender.sv +prim_mubi8_sender.sv +prim_mubi16_sender.sv +prim_mubi20_sync.sv +prim_mubi32_dec.sv +prim_mubi4_sync.sv +prim_xilinx_clock_mux2.sv +ibex_icache.sv +prim_onehot_check.sv +prim_clock_mux2.sv +prim_pkg.sv +prim_xilinx_and2.sv +prim_xilinx_clock_gating.sv +prim_generic_ram_1p.sv +prim_generic_buf.sv +dv_fcov_macros.svh +prim_util_memload.svh +prim_assert_dummy_macros.svh +prim_assert_standard_macros.svh +prim_assert_sec_cm.svh +prim_assert_yosys_macros.svh +prim_util_get_scramble_params.svh diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..212ecf11de146c20941cdcb26538ee726f23ec6f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/custom_top_wrapper.sv @@ -0,0 +1,221 @@ +// Author: Stefano Mercogliano +// Description: Top level wrapper for Ibex CPU. +// Ibex CPU is fully functional in 3 configurations: LIGHTWEIGHT, PERFORMANCE and OPENTITAN +// By Default, PERFORMANCE configuration is slected. Uncomment the appropriate define to select. + + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" + +///////////////////////// +// Ibex Configurations // +///////////////////////// +//`define IBEX_LIGHTWEIGHT +`define IBEX_PERFORMANCE +//`define IBEX_OPENTITAN // Does not support debugger + +module custom_top_wrapper import ibex_pkg::*; # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + + // TODO121: Automatically align with config + // AXI/MEM macros parameter + parameter LOCAL_DATA_WIDTH = 32, + parameter LOCAL_ADDR_WIDTH = 32, + + // Debug-related Parameters + parameter unsigned DmBaseAddr = 32'h00010800, + parameter unsigned DmAddrMask = 32'h00000FFF, + parameter unsigned DmHaltAddr = 32'h00010800, + parameter unsigned DmExceptionAddr = DmHaltAddr + 32'h10 + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + // Clock and Reset + input logic clk_i, + input logic rst_ni, + + input logic [31:0] hart_id_i, + input logic [31:0] boot_addr_i, + + // Interrupt inputs + input logic irq_software_i, + input logic irq_timer_i, + input logic irq_external_i, + input logic [14:0] irq_fast_i, + input logic irq_nm_i, // non-maskable interrupt + + // Debug Interface + input logic debug_req_i, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // MEM Master Interface Array + `DEFINE_MEM_MASTER_PORTS(instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH), + // MEM Slave Interface Array + `DEFINE_MEM_MASTER_PORTS(data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH) +); + + ibex_top #( + + `ifdef IBEX_LIGHTWEIGHT + + /////////////////////// + // Ibex small config // + /////////////////////// + + .RV32E ( 1'b0 ), + .RV32M ( RV32MFast ), + .RV32B ( RV32BNone ), + .RegFile ( ibex_pkg::RegFileFPGA ), + .BranchTargetALU ( 0 ), + .WritebackStage ( 0 ), + .ICache ( 0 ), + .ICacheECC ( 0 ), + .ICacheScramble ( 0 ), + .BranchPredictor ( 0 ), + .DbgTriggerEn ( 0 ), + .SecureIbex ( 0 ), + .PMPEnable ( 0 ), + .PMPGranularity ( 0 ), + .PMPNumRegions ( 4 ), + .MHPMCounterNum ( 0 ), + .MHPMCounterWidth ( 40 ), + + `elsif IBEX_PERFORMANCE + + ///////////////////////////// + // Ibex Performance config // + ///////////////////////////// + + .RV32E ( 0 ), + .RV32M ( ibex_pkg::RV32MSingleCycle ), + .RV32B ( ibex_pkg::RV32BBalanced ), + .RegFile ( ibex_pkg::RegFileFPGA ), + .BranchTargetALU ( 1 ), + .WritebackStage ( 1 ), + .ICache ( 0 ), + .ICacheECC ( 0 ), + .ICacheScramble ( 0 ), + .BranchPredictor ( 0 ), + .DbgTriggerEn ( 0 ), + .SecureIbex ( 0 ), + .PMPEnable ( 1 ), + .PMPGranularity ( 0 ), + .PMPNumRegions ( 16 ), + .MHPMCounterNum ( 0 ), + .MHPMCounterWidth ( 40 ), + + `elsif IBEX_OPENTITAN + + /////////////////////////// + // Ibex OpenTitan config // + /////////////////////////// + // NOTE: Currently, this config does not support Debug Transport Module + + .RV32E ( 0 ), + .RV32M ( ibex_pkg::RV32MSingleCycle ), + .RV32B ( ibex_pkg::RV32BOTEarlGrey ), + .RegFile ( ibex_pkg::RegFileFPGA ), + .BranchTargetALU ( 1 ), + .WritebackStage ( 1 ), + .ICache ( 1 ), + .ICacheECC ( 1 ), + .ICacheScramble ( 1 ), + .BranchPredictor ( 0 ), + .DbgTriggerEn ( 1 ), + .SecureIbex ( 1 ), + .PMPEnable ( 1 ), + .PMPGranularity ( 0 ), + .PMPNumRegions ( 16 ), + .MHPMCounterNum ( 10 ), + .MHPMCounterWidth ( 32 ), + + `endif + + ////////////////////// + // Debug Parameters // + ////////////////////// + + .DmBaseAddr ( DmBaseAddr ), + .DmAddrMask ( DmAddrMask ), + .DmHaltAddr ( DmHaltAddr ), + .DmExceptionAddr ( DmExceptionAddr ) + + ) ibex_u ( + // Clock and Reset + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + + .test_en_i ( 1'b0 ), + .scan_rst_ni ( 1'b1 ), + .ram_cfg_i ( '0 ), + + .hart_id_i ( hart_id_i ), + // First instruction executed is going to be at boot_addr_i + 0x80 (i.e. right after the vector table) + .boot_addr_i ( boot_addr_i ), + + // Instruction memory interface + .instr_req_o ( instr_mem_req ), + .instr_gnt_i ( instr_mem_gnt ), + .instr_rvalid_i ( instr_mem_valid ), + .instr_addr_o ( instr_mem_addr ), + .instr_rdata_i ( instr_mem_rdata ), + .instr_rdata_intg_i ( '0 ), + .instr_err_i ( '0 ), + + // Data memory interface + .data_req_o ( data_mem_req ), + .data_gnt_i ( data_mem_gnt ), + .data_rvalid_i ( data_mem_valid ), + .data_we_o ( data_mem_we ), + .data_be_o ( data_mem_be ), + .data_addr_o ( data_mem_addr ), + .data_wdata_o ( data_mem_wdata ), + .data_rdata_i ( data_mem_rdata ), + .data_wdata_intg_o ( ), + .data_rdata_intg_i ( '0 ), + .data_err_i ( '0 ), + + .irq_software_i ( irq_software_i ), + .irq_timer_i ( irq_timer_i ), + .irq_external_i ( irq_external_i ), + .irq_fast_i ( irq_fast_i ), + .irq_nm_i ( irq_nm_i ), + + .scramble_key_valid_i ('0 ), + .scramble_key_i ('0 ), + .scramble_nonce_i ('0 ), + .scramble_req_o ( ), + + .debug_req_i ( debug_req_i ), + .crash_dump_o ( ), + .double_fault_seen_o ( ), + + .fetch_enable_i ( ibex_pkg::IbexMuBiOn ), + .alert_minor_o ( ), + .alert_major_internal_o ( ), + .alert_major_bus_o ( ), + .core_sleep_o ( ) + ); + + + // Tie-off non-driven signals + assign instr_mem_wdata = '0; + assign instr_mem_we = '0; + assign instr_mem_be = '0; + + +endmodule : custom_top_wrapper + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..2efb6013afbbeb120781db3cec63953773e792bd --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_ibex/fetch_sources.sh @@ -0,0 +1,52 @@ +#!/bin/bash +# Author: Stefano Mercogliano +# Description: +# This script downloads LowRISC Ibex sources and flattens them into the rtl directory + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + + +# Create rtl dir +mkdir -p rtl + +# clone repo (Ibex releases are inconsistent, therefore we must stick to a specific commit). +GIT_URL=https://github.com/lowRISC/ibex.git +GIT_BRANCH=master +GIT_COMMIT=6e466c1504b61333d1b2ba85c69bff94b65e9284 +CLONE_DIR=ibex +printf "${YELLOW}[FETCH_SOURCES] Cloning source repository${NC}\n" +git clone ${GIT_URL} -b ${GIT_BRANCH} ${CLONE_DIR} +cd ${CLONE_DIR}; +git checkout ${GIT_COMMIT} + +# Copy all RTL files into rtl dir +# We use the flist pre-generated with fusesoc and saved in assets +# the flist is generated using: +# fusesoc --cores-root . run --target=lint --setup --build-root ./build/ibex_out lowrisc:ibex:ibex_top +# Python version 3.6 +cd ..; +FLIST="$PWD/assets/flist" +LOOKUP_DIR="$PWD/ibex" +RTL_DIR="$PWD/rtl" + +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into rtl${NC}\n" s +while IFS= read -r filename; do + # Find the file in LOOKUP_DIR + filepath=$(find "$LOOKUP_DIR" -type f -name "$filename" 2>/dev/null | head -n 1) + + # If found + if [ -n "$filepath" ]; then + cp "$filepath" "$RTL_DIR/" + # Error + else + printf "${RED}[FETCH_SOURCES] Error: $filename not found in $LOOKUP_DIR${NC}\n" + exit 1 + fi +done < "$FLIST" + +# Info +printf "${GREEN}[FETCH_SOURCES] Completed${NC}\n" + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..5bfaa4e04765e7791afb28e9ee81f49b9f63cd0a --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/.gitignore @@ -0,0 +1 @@ +picorv32/ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..e5e2b4144a779f9f1456ca7da656f224cc4034af --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/custom_top_wrapper.sv @@ -0,0 +1,290 @@ +// Author: Stefano Mercogliano +// Description: Top level module for PICORV32 core with MEM-adapted memory interfaces. + + +// Import headers +`include "uninasoc_mem.svh" +`include "uninasoc_axi.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // TODO121: Automatically align with config + // AXI/MEM macros parameter + parameter LOCAL_DATA_WIDTH = 32, + parameter LOCAL_ADDR_WIDTH = 32, + + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] LATCHED_MEM_RDATA = 0, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 1, + parameter [ 0:0] ENABLE_FAST_MUL = 1, + parameter [ 0:0] ENABLE_DIV = 1, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + input logic clk_i, + input logic rst_ni, + output logic trap_o, + + // IRQ Interface + input logic [31:0] irq_i, + +`ifdef RISCV_FORMAL + output logic rvfi_valid, + output logic [63:0] rvfi_order, + output logic [31:0] rvfi_insn, + output logic rvfi_trap, + output logic rvfi_halt, + output logic rvfi_intr, + output logic [ 1:0] rvfi_mode, + output logic [ 1:0] rvfi_ixl, + output logic [ 4:0] rvfi_rs1_addr, + output logic [ 4:0] rvfi_rs2_addr, + output logic [31:0] rvfi_rs1_rdata, + output logic [31:0] rvfi_rs2_rdata, + output logic [ 4:0] rvfi_rd_addr, + output logic [31:0] rvfi_rd_wdata, + output logic [31:0] rvfi_pc_rdata, + output logic [31:0] rvfi_pc_wdata, + output logic [31:0] rvfi_mem_addr, + output logic [ 3:0] rvfi_mem_rmask, + output logic [ 3:0] rvfi_mem_wmask, + output logic [31:0] rvfi_mem_rdata, + output logic [31:0] rvfi_mem_wdata, + + output logic [63:0] rvfi_csr_mcycle_rmask, + output logic [63:0] rvfi_csr_mcycle_wmask, + output logic [63:0] rvfi_csr_mcycle_rdata, + output logic [63:0] rvfi_csr_mcycle_wdata, + + output logic [63:0] rvfi_csr_minstret_rmask, + output logic [63:0] rvfi_csr_minstret_wmask, + output logic [63:0] rvfi_csr_minstret_rdata, + output logic [63:0] rvfi_csr_minstret_wdata, +`endif + + // Trace Interface + output logic trace_valid_o, + output logic [35:0] trace_data_o, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // MEM Master Interface Array + `DEFINE_MEM_MASTER_PORTS(instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH), + // MEM Slave Interface Array + `DEFINE_MEM_MASTER_PORTS(data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH) +); + + ////////////////////////// + // PicoRV32 // + ////////////////////////// + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31), + .ENABLE_REGS_DUALPORT (ENABLE_REGS_DUALPORT), + .LATCHED_MEM_RDATA (LATCHED_MEM_RDATA), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT), + .BARREL_SHIFTER (BARREL_SHIFTER), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU), + .COMPRESSED_ISA (COMPRESSED_ISA), + .CATCH_MISALIGN (CATCH_MISALIGN), + .CATCH_ILLINSN (CATCH_ILLINSN), + .ENABLE_PCPI (ENABLE_PCPI), + .ENABLE_MUL (ENABLE_MUL), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL), + .ENABLE_DIV (ENABLE_DIV), + .ENABLE_IRQ (ENABLE_IRQ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER), + .ENABLE_TRACE (ENABLE_TRACE), + .REGS_INIT_ZERO (REGS_INIT_ZERO), + .MASKED_IRQ (MASKED_IRQ), + .LATCHED_IRQ (LATCHED_IRQ), + .PROGADDR_RESET (PROGADDR_RESET), + .PROGADDR_IRQ (PROGADDR_IRQ), + .STACKADDR (STACKADDR) + ) core ( + .clk (clk_i ), + .resetn (rst_ni), + .trap (trap), + + .mem_valid (mem_valid), + .mem_addr (mem_addr ), + .mem_wdata (mem_data_wdata), + .mem_wstrb (mem_wstrb), + .mem_instr (mem_instr), + .mem_ready (mem_ready), + .mem_rdata (mem_rdata), + + // Ignored + .mem_la_read (), + .mem_la_write (), + .mem_la_addr (), + .mem_la_wdata (), + .mem_la_wstrb (), + .pcpi_valid (), + .pcpi_insn (), + .pcpi_rs1 (), + .pcpi_rs2 (), + .pcpi_wr ('0), + .pcpi_rd ('0), + .pcpi_wait ('0), + .pcpi_ready ('0), + + .irq (irq_i), + .eoi (), + + `ifdef RISCV_FORMAL + .rvfi_valid (), + .rvfi_order (), + .rvfi_insn (), + .rvfi_trap (), + .rvfi_halt (), + .rvfi_intr (), + .rvfi_rs1_addr (), + .rvfi_rs2_addr (), + .rvfi_rs1_rdata(), + .rvfi_rs2_rdata(), + .rvfi_rd_addr (), + .rvfi_rd_wdata (), + .rvfi_pc_rdata (), + .rvfi_pc_wdata (), + .rvfi_mem_addr (), + .rvfi_mem_rmask(), + .rvfi_mem_wmask(), + .rvfi_mem_rdata(), + .rvfi_mem_wdata(), + `endif + + .trace_valid (trace_valid), + .trace_data (trace_data) + ); + + + ////////////////////////////// + // Signal Definitions // + ////////////////////////////// + + // Trap, interrupts and trace signals. They might + // not be used outside of Pico. + logic trap; + logic [31:0] irq; + logic [31:0] eoi; + logic trace_valid; + logic [35:0] trace_data; + + // This signal is used to distinguish between + // instr and data transactions + logic mem_instr; + + // Memory signals + logic mem_instr_req; + logic mem_instr_gnt; + logic mem_instr_valid; + logic [31:0] mem_instr_addr; + logic [31:0] mem_instr_rdata; + logic mem_instr_error; + logic mem_data_req; + logic mem_data_gnt; + logic mem_data_valid; + logic [31:0] mem_data_addr; + logic [31:0] mem_data_rdata; + logic [31:0] mem_data_wdata; + logic [ 3:0] mem_data_be; + logic mem_data_we; + logic mem_data_error; + + logic mem_valid; + logic mem_ready; + logic [31:0] mem_addr; + logic [31:0] mem_rdata; + logic [3:0] mem_wstrb; + + ////////////////////////// + // Demultiplexing // + ////////////////////////// + + // Instruction Transaction + assign mem_instr_req = (mem_instr) ? mem_valid: '0; + assign mem_instr_addr = (mem_instr) ? mem_addr: '0; + // Data Transaction + assign mem_data_req = (~mem_instr) ? mem_valid: '0; + assign mem_data_addr = (~mem_instr) ? mem_addr: '0; + assign mem_data_we = (~mem_instr & |mem_wstrb) ? 1'b1: 1'b0; + assign mem_data_be = mem_wstrb; + + //////////////////////// + // Multiplexing // + //////////////////////// + + assign mem_ready = (mem_instr) ? instr_mem_valid : data_mem_valid; + assign mem_rdata = (mem_instr) ? instr_mem_rdata : data_mem_rdata; + + //////////////////////////////////// + // Mem "lite" to Mem "full" // + ////////////////////////////////////////////////////////////////////////////////// + // Pico mem protocol uses different names compared to the "full" Mem protocol. // + // This was adjusted in the Demultiplexing section. In addition, Pico ignores // + // the gnt_i signal, but only cares for the valid one. When valid is asserted, // + // data is instantly available for the processor to be read. Therefore, this // + // section is empty, because the conversion only consists in demultiplexing // + // and ignoring both grant and error signals. // + ////////////////////////////////////////////////////////////////////////////////// + + assign mem_instr_gnt = instr_mem_gnt; + assign mem_data_gnt = data_mem_gnt; + + ////////////////////////////// + // Output Assignments // + ////////////////////////////// + + assign trace_valid_o = trace_valid; + assign trace_data_o = trace_data; + assign trap_o = trap; + + assign instr_mem_req = mem_instr_req; + assign instr_mem_addr = mem_instr_addr; + assign data_mem_req = mem_data_req; + assign data_mem_addr = mem_data_addr; + assign data_mem_be = mem_data_be; + assign data_mem_we = mem_data_we; + assign data_mem_wdata = mem_data_wdata; + + + +endmodule : custom_top_wrapper + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..4bd4b76bd3a170874a98f8ba1fb154090b9d13e3 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_picorv32/fetch_sources.sh @@ -0,0 +1,27 @@ +#!/bin/bash +# Author: Stefano Mercogliano +# Description: +# This script downloads picorv32 sources and flattens them into the rtl directory + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +# Create rtl dir +mkdir rtl + +# clone repo (Branch main, Release v1.0 Mar 2, 2019, Commit 87c89ac) +GIT_URL=https://github.com/YosysHQ/picorv32.git +GIT_COMMIT=87c89ac +printf "${YELLOW}[FETCH_SOURCES] Cloning source repository${NC}\n" +git clone ${GIT_URL} --depth 1 picorv32 +cd picorv32; +git reset --hard ${GIT_COMMIT} + +# Copy all RTL files into rtl dir +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into rtl${NC}\n" s +cp picorv32.v ../rtl + +# Info +printf "${GREEN}[FETCH_SOURCES] Completed${NC}\n" diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7801c0b023214b658504a00d1af8f2b9c15206f3 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/.gitignore @@ -0,0 +1,2 @@ +*.flist +.bender/ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/assets/Bender.lock b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/assets/Bender.lock new file mode 100644 index 0000000000000000000000000000000000000000..efca9de907fbe2c6875917957035cf14dabaf584 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/assets/Bender.lock @@ -0,0 +1,39 @@ +packages: + axi: + revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7 + version: 0.39.6 + source: + Git: https://github.com/pulp-platform/axi.git + dependencies: + - common_cells + - common_verification + - tech_cells_generic + common_cells: + revision: 9afda9abb565971649c2aa0985639c096f351171 + version: 1.38.0 + source: + Git: https://github.com/pulp-platform/common_cells.git + dependencies: + - common_verification + - tech_cells_generic + common_verification: + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 + source: + Git: https://github.com/pulp-platform/common_verification.git + dependencies: [] + riscv-dbg: + revision: 358f90110220adf7a083f8b65d157e836d706236 + version: 0.8.1 + source: + Git: https://github.com/pulp-platform/riscv-dbg.git + dependencies: + - common_cells + - tech_cells_generic + tech_cells_generic: + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 + source: + Git: https://github.com/pulp-platform/tech_cells_generic.git + dependencies: + - common_verification diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/assets/Bender.yml b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/assets/Bender.yml new file mode 100644 index 0000000000000000000000000000000000000000..30fcebc35ed641e74a1950269ad3b8bf12a41665 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/assets/Bender.yml @@ -0,0 +1,7 @@ +package: + name: axi-riscv-dbg + authors: + - "Vincenzo Maisto " +dependencies: + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.6 } + riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..396466343ee65548cc66a7f78e01f9b3bc44bc68 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/custom_top_wrapper.sv @@ -0,0 +1,383 @@ +// Author: Vincenzo Maisto +// Description: Top level wrapper module for PULP DTM and AXI adapters, 32-bit version. + +// Import UninaSoC headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" +// From axi/include +`include "typedef.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + parameter int unsigned NrHarts = 1, + // parameter int unsigned BusWidth = 32, + parameter logic [31:0] DmBaseAddress = 32'h10000, // TODO121: match from config + // parameter int unsigned DmBaseAddress = 'h1000, // default to non-zero page + // Bitmask to select physically available harts for systems + // that don't use hart numbers in a contiguous fashion. + parameter logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}}, + // toggle new behavior to drive master_be_o during a read + parameter bit ReadByteEnable = 1, + + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // TODO121: Automatically align with config + parameter LOCAL_MEM_DATA_WIDTH = 32, + parameter LOCAL_MEM_ADDR_WIDTH = 32, + + parameter LOCAL_AXI_DATA_WIDTH = 32, + parameter LOCAL_AXI_ADDR_WIDTH = 32, + parameter LOCAL_AXI_STRB_WIDTH = 4, + parameter LOCAL_AXI_ID_WIDTH = 4, + parameter LOCAL_AXI_REGION_WIDTH = 4, + parameter LOCAL_AXI_LEN_WIDTH = 8, + parameter LOCAL_AXI_SIZE_WIDTH = 3, + parameter LOCAL_AXI_BURST_WIDTH = 2, + parameter LOCAL_AXI_LOCK_WIDTH = 1, + parameter LOCAL_AXI_CACHE_WIDTH = 4, + parameter LOCAL_AXI_PROT_WIDTH = 3, + parameter LOCAL_AXI_QOS_WIDTH = 4, + parameter LOCAL_AXI_VALID_WIDTH = 1, + parameter LOCAL_AXI_READY_WIDTH = 1, + parameter LOCAL_AXI_LAST_WIDTH = 1, + parameter LOCAL_AXI_RESP_WIDTH = 2 + +) ( + + /////////////////////// + // IP-related ports // + /////////////////////// + + input logic clk_i, // clock + input logic rst_ni, // System reset + // input logic debug_reset_ni, // Power-on-reset, not the system reset + output logic ndmreset_o, // non-debug module reset + output logic dmactive_o, // debug module is active + output logic [NrHarts-1:0] debug_req_o, // async debug request + input logic [NrHarts-1:0] unavailable_i, // communicate whether the hart is unavailable (e.g.: power down) + + ////////////////////// + // Bus Interfaces // + ////////////////////// + `DEFINE_AXI_MASTER_PORTS(dbg_master, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH), + `DEFINE_AXI_SLAVE_PORTS(dbg_slave, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH) +); + + // Architecture: + // __________ _________________ + // | (bscane) | | | + // | dmi_jtag | -- DMI --> | dm_top | -- debug_req_o --> + // |__________| |_________________| + // | ^ + // v | + // MEM master MEM slave + // | ^ + // _______v______ _____|______ + // | | | | + // | axi_from_mem | | axi_to_mem | + // |______________| |____________| + // | ^ + // v | + // AXI master AXI slave + // + + /////////////////// + // Local signals // + /////////////////// + + // Define the req_t and resp_t type using typedef.svh macro + `AXI_TYPEDEF_ALL( + axi, + logic [LOCAL_AXI_ADDR_WIDTH -1:0], + logic [LOCAL_AXI_ID_WIDTH -1:0], + logic [LOCAL_AXI_DATA_WIDTH -1:0], + logic [LOCAL_AXI_STRB_WIDTH -1:0], + logic [0:0] // This is for the user field, which is missing from our interface (or unused) + ) + + // AXI request/response structs + axi_req_t dbg_slave_axi_req; + axi_resp_t dbg_slave_axi_resp; + axi_req_t dbg_master_axi_req; + axi_resp_t dbg_master_axi_resp; + + // Mem buses + `DECLARE_MEM_BUS(dbg_slave, LOCAL_MEM_DATA_WIDTH, LOCAL_MEM_ADDR_WIDTH); + `DECLARE_MEM_BUS(dbg_master, LOCAL_MEM_DATA_WIDTH, LOCAL_MEM_ADDR_WIDTH); + + // Pack hartinfo_t struct + dm::hartinfo_t hartinfo; + // From ariane_pkg::DebugHartInfo + // Same as https://github.com/lowRISC/ibex-demo-system/blob/main/rtl/system/dm_top.sv + assign hartinfo.zero1 = '0; + assign hartinfo.nscratch = 2; // Debug module needs at least two scratch regs + assign hartinfo.zero0 = '0; + assign hartinfo.dataaccess = 1'b1; // data registers are memory mapped in the debugger + assign hartinfo.datasize = dm::DataCount; + assign hartinfo.dataaddr = dm::DataAddr; + + // DMI interface + // DM package-specific structs + dm::dmi_req_t dmi_req; + dm::dmi_resp_t dmi_resp; + // Valid/ready + logic dmi_req_ready ; + logic dmi_req_valid ; + logic dmi_resp_ready ; + logic dmi_resp_valid ; + // Reset + logic dmi_rst_n; + + ////////////////// + // Debug Module // + ////////////////// + + // Tie-off unconnected signals + assign dbg_slave_mem_gnt = '0; + assign dbg_slave_mem_error = '0; + + // Debug Module + dm_top #( + .NrHarts ( NrHarts ), + .BusWidth ( LOCAL_MEM_DATA_WIDTH ), // Must be the same as LOCAL_MEM_ADDR_WIDTH + .DmBaseAddress ( DmBaseAddress ) + ) dm_top_u ( + .clk_i, + .rst_ni, + // Deug ports + .testmode_i ( '0 ), + .ndmreset_o ( ndmreset_o ), + .dmactive_o ( dmactive_o ), + .unavailable_i ( unavailable_i ), + .hartinfo_i ( hartinfo ), + // To RV core + .debug_req_o ( debug_req_o ), + // Slave mem + .slave_req_i ( dbg_slave_mem_req ), + .slave_we_i ( dbg_slave_mem_we ), + .slave_addr_i ( dbg_slave_mem_addr ), + .slave_be_i ( dbg_slave_mem_be ), + .slave_wdata_i ( dbg_slave_mem_wdata ), + .slave_rdata_o ( dbg_slave_mem_rdata ), + // Master mem + .master_req_o ( dbg_master_mem_req ), + .master_add_o ( dbg_master_mem_addr ), + .master_we_o ( dbg_master_mem_we ), + .master_wdata_o ( dbg_master_mem_wdata ), + .master_be_o ( dbg_master_mem_be ), + .master_gnt_i ( dbg_master_mem_gnt ), + .master_r_valid_i ( dbg_master_mem_valid ), + .master_r_rdata_i ( dbg_master_mem_rdata ), + .master_r_err_i ( dbg_master_mem_error ), + .master_r_other_err_i ( 1'b0 ), + // From DTM + .dmi_rst_ni ( dmi_rst_n ), + .dmi_req_valid_i ( dmi_req_valid ), + .dmi_req_ready_o ( dmi_req_ready ), + .dmi_req_i ( dmi_req ), + .dmi_resp_valid_o ( dmi_resp_valid ), + .dmi_resp_ready_i ( dmi_resp_ready ), + .dmi_resp_o ( dmi_resp ) + ); + + // Debug Transport Module and JTAG interface + dmi_jtag dtm_u ( + .clk_i, + .rst_ni, + // To DM + .dmi_rst_no ( dmi_rst_n ), + .dmi_req_o ( dmi_req ), + .dmi_req_ready_i ( dmi_req_ready ), + .dmi_req_valid_o ( dmi_req_valid ), + .dmi_resp_i ( dmi_resp ), + .dmi_resp_ready_o ( dmi_resp_ready ), + .dmi_resp_valid_i ( dmi_resp_valid ), + .testmode_i ( '0 ), // Unused + // From JTAG + .tck_i ( '0 ), // Unused + .tms_i ( '0 ), // Unused + .trst_ni ( '1 ), // Unused + .td_i ( '0 ), // Unused + .td_o ( ), // Open + .tdo_oe_o ( ) // Open + ); + + ////////////////// + // AXI adapters // + ////////////////// + + // From cheshire_soc.sv + localparam int unsigned axi_to_mem_NumBanks = 1; + localparam int unsigned axi_to_mem_BufDepth = 4; + + // AXI access to debug module + // axi_to_mem_interleaved #( + axi_to_mem #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AddrWidth ( LOCAL_AXI_ADDR_WIDTH ), + .DataWidth ( LOCAL_AXI_DATA_WIDTH ), + .IdWidth ( LOCAL_AXI_ID_WIDTH ), + .NumBanks ( axi_to_mem_NumBanks ), + .BufDepth ( axi_to_mem_BufDepth ) + ) axi_to_mem_u ( + .clk_i, + .rst_ni, + // .test_i ( test_mode_i ), // only for axi_to_mem_interleaved + .busy_o ( busy_o ), // Open + .axi_req_i ( dbg_slave_axi_req ), + .axi_resp_o ( dbg_slave_axi_resp ), + .mem_req_o ( dbg_slave_mem_req ), + .mem_gnt_i ( dbg_slave_mem_req ), // From cheshire_soc.sv + .mem_addr_o ( dbg_slave_mem_addr ), + .mem_wdata_o ( dbg_slave_mem_wdata ), + .mem_strb_o ( dbg_slave_mem_be ), + .mem_atop_o ( mem_atop_o ), // Open + .mem_we_o ( dbg_slave_mem_we ), + .mem_rvalid_i ( dbg_slave_mem_valid ), + .mem_rdata_i ( dbg_slave_mem_rdata ) + ); + + // From cheshire_soc.sv + // Read response is valid one cycle after request + always_ff @(posedge clk_i or negedge rst_ni) begin + if ( !rst_ni ) begin + dbg_slave_mem_valid <= '0; + end + else begin + dbg_slave_mem_valid <= dbg_slave_mem_req; + end + end + + // From cheshire_pkg.sv + localparam int unsigned axi_from_mem_MaxRequests = 4; + localparam axi_pkg::prot_t axi_from_mem_AxiProt = 3'b000; + + // Debug module system bus access to AXI crossbar + axi_from_mem #( + .MemAddrWidth ( LOCAL_AXI_ADDR_WIDTH ), + .AxiAddrWidth ( LOCAL_AXI_ADDR_WIDTH ), + .DataWidth ( LOCAL_AXI_DATA_WIDTH ), + .MaxRequests ( axi_from_mem_MaxRequests ), + .AxiProt ( axi_from_mem_AxiProt ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_resp_t ) + ) axi_from_mem_u ( + .clk_i, + .rst_ni, + .mem_req_i ( dbg_master_mem_req ), + .mem_addr_i ( dbg_master_mem_addr ), + .mem_we_i ( dbg_master_mem_we ), + .mem_wdata_i ( dbg_master_mem_wdata ), + .mem_be_i ( dbg_master_mem_be ), + .mem_gnt_o ( dbg_master_mem_gnt ), + .mem_rsp_valid_o ( dbg_master_mem_valid ), + .mem_rsp_rdata_o ( dbg_master_mem_rdata ), + .mem_rsp_error_o ( dbg_master_mem_error ), + .slv_aw_cache_i ( axi_pkg::CACHE_MODIFIABLE ), + .slv_ar_cache_i ( axi_pkg::CACHE_MODIFIABLE ), + .axi_req_o ( dbg_master_axi_req ), + .axi_rsp_i ( dbg_master_axi_resp ) + ); + + + //////////////////////////////// + // Unwrap axi structured type // + //////////////////////////////// + + // AXI slave request + assign dbg_slave_axi_req.aw.id = dbg_slave_axi_awid; + assign dbg_slave_axi_req.aw.addr = dbg_slave_axi_awaddr; + assign dbg_slave_axi_req.aw.len = dbg_slave_axi_awlen; + assign dbg_slave_axi_req.aw.size = dbg_slave_axi_awsize; + assign dbg_slave_axi_req.aw.burst = dbg_slave_axi_awburst; + assign dbg_slave_axi_req.aw.lock = dbg_slave_axi_awlock; + assign dbg_slave_axi_req.aw.cache = dbg_slave_axi_awcache; + assign dbg_slave_axi_req.aw.prot = dbg_slave_axi_awprot; + assign dbg_slave_axi_req.aw.qos = dbg_slave_axi_awqos; + assign dbg_slave_axi_req.aw.region = dbg_slave_axi_awregion; + assign dbg_slave_axi_req.aw_valid = dbg_slave_axi_awvalid; + assign dbg_slave_axi_req.w.data = dbg_slave_axi_wdata; + assign dbg_slave_axi_req.w.strb = dbg_slave_axi_wstrb; + assign dbg_slave_axi_req.w.last = dbg_slave_axi_wlast; + assign dbg_slave_axi_req.w_valid = dbg_slave_axi_wvalid; + assign dbg_slave_axi_req.b_ready = dbg_slave_axi_bready; + assign dbg_slave_axi_req.ar.addr = dbg_slave_axi_araddr; + assign dbg_slave_axi_req.ar.len = dbg_slave_axi_arlen; + assign dbg_slave_axi_req.ar.size = dbg_slave_axi_arsize; + assign dbg_slave_axi_req.ar.burst = dbg_slave_axi_arburst; + assign dbg_slave_axi_req.ar.lock = dbg_slave_axi_arlock; + assign dbg_slave_axi_req.ar.cache = dbg_slave_axi_arcache; + assign dbg_slave_axi_req.ar.prot = dbg_slave_axi_arprot; + assign dbg_slave_axi_req.ar.qos = dbg_slave_axi_arqos; + assign dbg_slave_axi_req.ar.region = dbg_slave_axi_arregion; + assign dbg_slave_axi_req.ar_valid = dbg_slave_axi_arvalid; + assign dbg_slave_axi_req.r_ready = dbg_slave_axi_rready; + assign dbg_slave_axi_req.ar.id = dbg_slave_axi_arid; + + // AXI slave response + assign dbg_slave_axi_awready = dbg_slave_axi_resp.aw_ready ; + assign dbg_slave_axi_wready = dbg_slave_axi_resp.w_ready ; + assign dbg_slave_axi_bid = dbg_slave_axi_resp.b.id ; + assign dbg_slave_axi_bresp = dbg_slave_axi_resp.b.resp ; + assign dbg_slave_axi_bvalid = dbg_slave_axi_resp.b_valid ; + assign dbg_slave_axi_arready = dbg_slave_axi_resp.ar_ready ; + assign dbg_slave_axi_rid = dbg_slave_axi_resp.r.id ; + assign dbg_slave_axi_rdata = dbg_slave_axi_resp.r.data ; + assign dbg_slave_axi_rresp = dbg_slave_axi_resp.r.resp ; + assign dbg_slave_axi_rlast = dbg_slave_axi_resp.r.last ; + assign dbg_slave_axi_rvalid = dbg_slave_axi_resp.r_valid ; + + // AXI master request + assign dbg_master_axi_awid = dbg_master_axi_req.aw.id; + assign dbg_master_axi_awaddr = dbg_master_axi_req.aw.addr; + assign dbg_master_axi_awlen = dbg_master_axi_req.aw.len; + assign dbg_master_axi_awsize = dbg_master_axi_req.aw.size; + assign dbg_master_axi_awburst = dbg_master_axi_req.aw.burst; + assign dbg_master_axi_awlock = dbg_master_axi_req.aw.lock; + assign dbg_master_axi_awcache = dbg_master_axi_req.aw.cache; + assign dbg_master_axi_awprot = dbg_master_axi_req.aw.prot; + assign dbg_master_axi_awqos = dbg_master_axi_req.aw.qos; + assign dbg_master_axi_awregion = dbg_master_axi_req.aw.region; + assign dbg_master_axi_awvalid = dbg_master_axi_req.aw_valid; + assign dbg_master_axi_wdata = dbg_master_axi_req.w.data; + assign dbg_master_axi_wstrb = dbg_master_axi_req.w.strb; + assign dbg_master_axi_wlast = dbg_master_axi_req.w.last; + assign dbg_master_axi_wvalid = dbg_master_axi_req.w_valid; + assign dbg_master_axi_bready = dbg_master_axi_req.b_ready; + assign dbg_master_axi_araddr = dbg_master_axi_req.ar.addr; + assign dbg_master_axi_arlen = dbg_master_axi_req.ar.len; + assign dbg_master_axi_arsize = dbg_master_axi_req.ar.size; + assign dbg_master_axi_arburst = dbg_master_axi_req.ar.burst; + assign dbg_master_axi_arlock = dbg_master_axi_req.ar.lock; + assign dbg_master_axi_arcache = dbg_master_axi_req.ar.cache; + assign dbg_master_axi_arprot = dbg_master_axi_req.ar.prot; + assign dbg_master_axi_arqos = dbg_master_axi_req.ar.qos; + assign dbg_master_axi_arregion = dbg_master_axi_req.ar.region; + assign dbg_master_axi_arvalid = dbg_master_axi_req.ar_valid; + assign dbg_master_axi_rready = dbg_master_axi_req.r_ready; + assign dbg_master_axi_arid = dbg_master_axi_req.ar.id; + + // AXI master response + assign dbg_master_axi_resp.aw_ready = dbg_master_axi_awready; + assign dbg_master_axi_resp.w_ready = dbg_master_axi_wready; + assign dbg_master_axi_resp.b.id = dbg_master_axi_bid; + assign dbg_master_axi_resp.b.resp = dbg_master_axi_bresp; + assign dbg_master_axi_resp.b_valid = dbg_master_axi_bvalid; + assign dbg_master_axi_resp.ar_ready = dbg_master_axi_arready; + assign dbg_master_axi_resp.r.id = dbg_master_axi_rid; + assign dbg_master_axi_resp.r.data = dbg_master_axi_rdata; + assign dbg_master_axi_resp.r.resp = dbg_master_axi_rresp; + assign dbg_master_axi_resp.r.last = dbg_master_axi_rlast; + assign dbg_master_axi_resp.r_valid = dbg_master_axi_rvalid; + + +endmodule : custom_top_wrapper + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..ce3b6b294bbaa3bb0965a035bef3fd14ad09d766 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv32_dbg_bscane/fetch_sources.sh @@ -0,0 +1,56 @@ +#!/bin/bash +# Author: Vincenzo Maisto +# Description: +# This script uses bender to download riscv-dbg and axi sources, and flattens them into the rtl/ directory + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + + +# Create rtl dir +RTL_DIR=$(pwd)/rtl +mkdir ${RTL_DIR} + +############## +# Bender.yml # +############## + +# Move into assets dir +cd assets/ + +# Download Bender +printf "${YELLOW}[FETCH_SOURCES] Download Bender${NC}\n" +curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh + +# Download dependencies (specify Target RTL and FPGA) +printf "${YELLOW}[FETCH_SOURCES] Resolve dependencies with Bender${NC}\n" +./bender checkout +BENDER_TARGETS="-t xilinx -t bscane" +./bender script flist ${BENDER_TARGETS} > rtl.flist + +# Copy all RTL files into rtl dir +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into ${RTL_DIR}/${NC}\n" s +for rtl_file in $(cat rtl.flist) ; do + cp $rtl_file ${RTL_DIR} +done; + +# Add header files, not listed by bender +CLONE_DIR=.bender +cp $(find ${CLONE_DIR} -name typedef.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name assertions.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name registers.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name assign.svh) ${RTL_DIR}/ + +# Remove interface-based files, since Vivado does not like them +rm $(find ${RTL_DIR}/ -name axi_intf.sv) + +# Patch files for flat includes +for rtl_file in ${RTL_DIR}/* ; do + sed -i "s|\`include \"common_cells\/|\`include \"|g" $rtl_file + sed -i "s|\`include \"axi\/|\`include \"|g" $rtl_file +done + +# Info +printf "${GREEN}[FETCH_SOURCES] Completed${NC}\n" diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7801c0b023214b658504a00d1af8f2b9c15206f3 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/.gitignore @@ -0,0 +1,2 @@ +*.flist +.bender/ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/assets/Bender.lock b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/assets/Bender.lock new file mode 100644 index 0000000000000000000000000000000000000000..efca9de907fbe2c6875917957035cf14dabaf584 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/assets/Bender.lock @@ -0,0 +1,39 @@ +packages: + axi: + revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7 + version: 0.39.6 + source: + Git: https://github.com/pulp-platform/axi.git + dependencies: + - common_cells + - common_verification + - tech_cells_generic + common_cells: + revision: 9afda9abb565971649c2aa0985639c096f351171 + version: 1.38.0 + source: + Git: https://github.com/pulp-platform/common_cells.git + dependencies: + - common_verification + - tech_cells_generic + common_verification: + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 + source: + Git: https://github.com/pulp-platform/common_verification.git + dependencies: [] + riscv-dbg: + revision: 358f90110220adf7a083f8b65d157e836d706236 + version: 0.8.1 + source: + Git: https://github.com/pulp-platform/riscv-dbg.git + dependencies: + - common_cells + - tech_cells_generic + tech_cells_generic: + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 + source: + Git: https://github.com/pulp-platform/tech_cells_generic.git + dependencies: + - common_verification diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/assets/Bender.yml b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/assets/Bender.yml new file mode 100644 index 0000000000000000000000000000000000000000..30fcebc35ed641e74a1950269ad3b8bf12a41665 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/assets/Bender.yml @@ -0,0 +1,7 @@ +package: + name: axi-riscv-dbg + authors: + - "Vincenzo Maisto " +dependencies: + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.6 } + riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 } \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..b064f03193e2a1ca82d2dcd6bcce3e966ae3a1cd --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/custom_top_wrapper.sv @@ -0,0 +1,384 @@ +// Author: Vincenzo Maisto +// Author: Stefano Mercogliano +// Description: Top level wrapper module for PULP DTM and AXI adapters, 32-bit version. + + +// Import UninaSoC headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" +// From axi/include +`include "typedef.svh" + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + parameter int unsigned NrHarts = 1, + // parameter int unsigned BusWidth = 32, + parameter logic [31:0] DmBaseAddress = 32'h10000, // TODO121: match from config + // parameter int unsigned DmBaseAddress = 'h1000, // default to non-zero page + // Bitmask to select physically available harts for systems + // that don't use hart numbers in a contiguous fashion. + parameter logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}}, + // toggle new behavior to drive master_be_o during a read + parameter bit ReadByteEnable = 1, + + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // TODO121: Automatically align with config + parameter LOCAL_MEM_DATA_WIDTH = 64, + parameter LOCAL_MEM_ADDR_WIDTH = 64, + + parameter LOCAL_AXI_DATA_WIDTH = 64, + parameter LOCAL_AXI_ADDR_WIDTH = 64, + parameter LOCAL_AXI_STRB_WIDTH = 8, + parameter LOCAL_AXI_ID_WIDTH = 4, + parameter LOCAL_AXI_REGION_WIDTH = 4, + parameter LOCAL_AXI_LEN_WIDTH = 8, + parameter LOCAL_AXI_SIZE_WIDTH = 3, + parameter LOCAL_AXI_BURST_WIDTH = 2, + parameter LOCAL_AXI_LOCK_WIDTH = 1, + parameter LOCAL_AXI_CACHE_WIDTH = 4, + parameter LOCAL_AXI_PROT_WIDTH = 3, + parameter LOCAL_AXI_QOS_WIDTH = 4, + parameter LOCAL_AXI_VALID_WIDTH = 1, + parameter LOCAL_AXI_READY_WIDTH = 1, + parameter LOCAL_AXI_LAST_WIDTH = 1, + parameter LOCAL_AXI_RESP_WIDTH = 2 + +) ( + + /////////////////////// + // IP-related ports // + /////////////////////// + + input logic clk_i, // clock + input logic rst_ni, // System reset + // input logic debug_reset_ni, // Power-on-reset, not the system reset + output logic ndmreset_o, // non-debug module reset + output logic dmactive_o, // debug module is active + output logic [NrHarts-1:0] debug_req_o, // async debug request + input logic [NrHarts-1:0] unavailable_i, // communicate whether the hart is unavailable (e.g.: power down) + + ////////////////////// + // Bus Interfaces // + ////////////////////// + `DEFINE_AXI_MASTER_PORTS(dbg_master, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH), + `DEFINE_AXI_SLAVE_PORTS(dbg_slave, LOCAL_AXI_DATA_WIDTH, LOCAL_AXI_ADDR_WIDTH, LOCAL_AXI_ID_WIDTH) +); + + // Architecture: + // __________ _________________ + // | (bscane) | | | + // | dmi_jtag | -- DMI --> | dm_top | -- debug_req_o --> + // |__________| |_________________| + // | ^ + // v | + // MEM master MEM slave + // | ^ + // _______v______ _____|______ + // | | | | + // | axi_from_mem | | axi_to_mem | + // |______________| |____________| + // | ^ + // v | + // AXI master AXI slave + // + + /////////////////// + // Local signals // + /////////////////// + + // Define the req_t and resp_t type using typedef.svh macro + `AXI_TYPEDEF_ALL( + axi, + logic [LOCAL_AXI_ADDR_WIDTH -1:0], + logic [LOCAL_AXI_ID_WIDTH -1:0], + logic [LOCAL_AXI_DATA_WIDTH -1:0], + logic [LOCAL_AXI_STRB_WIDTH -1:0], + logic [0:0] // This is for the user field, which is missing from our interface (or unused) + ) + + // AXI request/response structs + axi_req_t dbg_slave_axi_req; + axi_resp_t dbg_slave_axi_resp; + axi_req_t dbg_master_axi_req; + axi_resp_t dbg_master_axi_resp; + + // Mem buses + `DECLARE_MEM_BUS(dbg_slave, LOCAL_MEM_DATA_WIDTH, LOCAL_MEM_ADDR_WIDTH); + `DECLARE_MEM_BUS(dbg_master, LOCAL_MEM_DATA_WIDTH, LOCAL_MEM_ADDR_WIDTH); + + // Pack hartinfo_t struct + dm::hartinfo_t hartinfo; + // From ariane_pkg::DebugHartInfo + // Same as https://github.com/lowRISC/ibex-demo-system/blob/main/rtl/system/dm_top.sv + assign hartinfo.zero1 = '0; + assign hartinfo.nscratch = 2; // Debug module needs at least two scratch regs + assign hartinfo.zero0 = '0; + assign hartinfo.dataaccess = 1'b1; // data registers are memory mapped in the debugger + assign hartinfo.datasize = dm::DataCount; + assign hartinfo.dataaddr = dm::DataAddr; + + // DMI interface + // DM package-specific structs + dm::dmi_req_t dmi_req; + dm::dmi_resp_t dmi_resp; + // Valid/ready + logic dmi_req_ready ; + logic dmi_req_valid ; + logic dmi_resp_ready ; + logic dmi_resp_valid ; + // Reset + logic dmi_rst_n; + + ////////////////// + // Debug Module // + ////////////////// + + // Tie-off unconnected signals + assign dbg_slave_mem_gnt = '0; + assign dbg_slave_mem_error = '0; + + // Debug Module + dm_top #( + .NrHarts ( NrHarts ), + .BusWidth ( LOCAL_MEM_DATA_WIDTH ), // Must be the same as LOCAL_MEM_ADDR_WIDTH + .DmBaseAddress ( DmBaseAddress ) + ) dm_top_u ( + .clk_i, + .rst_ni, + // Deug ports + .testmode_i ( '0 ), + .ndmreset_o ( ndmreset_o ), + .dmactive_o ( dmactive_o ), + .unavailable_i ( unavailable_i ), + .hartinfo_i ( hartinfo ), + // To RV core + .debug_req_o ( debug_req_o ), + // Slave mem + .slave_req_i ( dbg_slave_mem_req ), + .slave_we_i ( dbg_slave_mem_we ), + .slave_addr_i ( dbg_slave_mem_addr ), + .slave_be_i ( dbg_slave_mem_be ), + .slave_wdata_i ( dbg_slave_mem_wdata ), + .slave_rdata_o ( dbg_slave_mem_rdata ), + // Master mem + .master_req_o ( dbg_master_mem_req ), + .master_add_o ( dbg_master_mem_addr ), + .master_we_o ( dbg_master_mem_we ), + .master_wdata_o ( dbg_master_mem_wdata ), + .master_be_o ( dbg_master_mem_be ), + .master_gnt_i ( dbg_master_mem_gnt ), + .master_r_valid_i ( dbg_master_mem_valid ), + .master_r_rdata_i ( dbg_master_mem_rdata ), + .master_r_err_i ( dbg_master_mem_error ), + .master_r_other_err_i ( 1'b0 ), + // From DTM + .dmi_rst_ni ( dmi_rst_n ), + .dmi_req_valid_i ( dmi_req_valid ), + .dmi_req_ready_o ( dmi_req_ready ), + .dmi_req_i ( dmi_req ), + .dmi_resp_valid_o ( dmi_resp_valid ), + .dmi_resp_ready_i ( dmi_resp_ready ), + .dmi_resp_o ( dmi_resp ) + ); + + // Debug Transport Module and JTAG interface + dmi_jtag dtm_u ( + .clk_i, + .rst_ni, + // To DM + .dmi_rst_no ( dmi_rst_n ), + .dmi_req_o ( dmi_req ), + .dmi_req_ready_i ( dmi_req_ready ), + .dmi_req_valid_o ( dmi_req_valid ), + .dmi_resp_i ( dmi_resp ), + .dmi_resp_ready_o ( dmi_resp_ready ), + .dmi_resp_valid_i ( dmi_resp_valid ), + .testmode_i ( '0 ), // Unused + // From JTAG + .tck_i ( '0 ), // Unused + .tms_i ( '0 ), // Unused + .trst_ni ( '1 ), // Unused + .td_i ( '0 ), // Unused + .td_o ( ), // Open + .tdo_oe_o ( ) // Open + ); + + ////////////////// + // AXI adapters // + ////////////////// + + // From cheshire_soc.sv + localparam int unsigned axi_to_mem_NumBanks = 1; + localparam int unsigned axi_to_mem_BufDepth = 4; + + // AXI access to debug module + axi_to_mem_interleaved #( + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AddrWidth ( LOCAL_AXI_ADDR_WIDTH ), + .DataWidth ( LOCAL_AXI_DATA_WIDTH ), + .IdWidth ( LOCAL_AXI_ID_WIDTH ), + .NumBanks ( axi_to_mem_NumBanks ), + .BufDepth ( axi_to_mem_BufDepth ) + ) axi_to_mem_u ( + .clk_i, + .rst_ni, + .test_i ( '0 ), // only for axi_to_mem_interleaved + .busy_o ( busy_o ), // Open + .axi_req_i ( dbg_slave_axi_req ), + .axi_resp_o ( dbg_slave_axi_resp ), + .mem_req_o ( dbg_slave_mem_req ), + .mem_gnt_i ( dbg_slave_mem_req ), // From cheshire_soc.sv + .mem_addr_o ( dbg_slave_mem_addr ), + .mem_wdata_o ( dbg_slave_mem_wdata ), + .mem_strb_o ( dbg_slave_mem_be ), + .mem_atop_o ( mem_atop_o ), // Open + .mem_we_o ( dbg_slave_mem_we ), + .mem_rvalid_i ( dbg_slave_mem_valid ), + .mem_rdata_i ( dbg_slave_mem_rdata ) + ); + + // From cheshire_soc.sv + // Read response is valid one cycle after request + always_ff @(posedge clk_i or negedge rst_ni) begin + if ( !rst_ni ) begin + dbg_slave_mem_valid <= '0; + end + else begin + dbg_slave_mem_valid <= dbg_slave_mem_req; + end + end + + // From cheshire_pkg.sv + localparam int unsigned axi_from_mem_MaxRequests = 4; + localparam axi_pkg::prot_t axi_from_mem_AxiProt = 3'b000; + + // Debug module system bus access to AXI crossbar + axi_from_mem #( + .MemAddrWidth ( LOCAL_AXI_ADDR_WIDTH ), + .AxiAddrWidth ( LOCAL_AXI_ADDR_WIDTH ), + .DataWidth ( LOCAL_AXI_DATA_WIDTH ), + .MaxRequests ( axi_from_mem_MaxRequests ), + .AxiProt ( axi_from_mem_AxiProt ), + .axi_req_t ( axi_req_t ), + .axi_rsp_t ( axi_resp_t ) + ) axi_from_mem_u ( + .clk_i, + .rst_ni, + .mem_req_i ( dbg_master_mem_req ), + .mem_addr_i ( dbg_master_mem_addr ), + .mem_we_i ( dbg_master_mem_we ), + .mem_wdata_i ( dbg_master_mem_wdata ), + .mem_be_i ( dbg_master_mem_be ), + .mem_gnt_o ( dbg_master_mem_gnt ), + .mem_rsp_valid_o ( dbg_master_mem_valid ), + .mem_rsp_rdata_o ( dbg_master_mem_rdata ), + .mem_rsp_error_o ( dbg_master_mem_error ), + .slv_aw_cache_i ( axi_pkg::CACHE_MODIFIABLE ), + .slv_ar_cache_i ( axi_pkg::CACHE_MODIFIABLE ), + .axi_req_o ( dbg_master_axi_req ), + .axi_rsp_i ( dbg_master_axi_resp ) + ); + + + //////////////////////////////// + // Unwrap axi structured type // + //////////////////////////////// + + // AXI slave request + assign dbg_slave_axi_req.aw.id = dbg_slave_axi_awid; + assign dbg_slave_axi_req.aw.addr = dbg_slave_axi_awaddr; + assign dbg_slave_axi_req.aw.len = dbg_slave_axi_awlen; + assign dbg_slave_axi_req.aw.size = dbg_slave_axi_awsize; + assign dbg_slave_axi_req.aw.burst = dbg_slave_axi_awburst; + assign dbg_slave_axi_req.aw.lock = dbg_slave_axi_awlock; + assign dbg_slave_axi_req.aw.cache = dbg_slave_axi_awcache; + assign dbg_slave_axi_req.aw.prot = dbg_slave_axi_awprot; + assign dbg_slave_axi_req.aw.qos = dbg_slave_axi_awqos; + assign dbg_slave_axi_req.aw.region = dbg_slave_axi_awregion; + assign dbg_slave_axi_req.aw_valid = dbg_slave_axi_awvalid; + assign dbg_slave_axi_req.w.data = dbg_slave_axi_wdata; + assign dbg_slave_axi_req.w.strb = dbg_slave_axi_wstrb; + assign dbg_slave_axi_req.w.last = dbg_slave_axi_wlast; + assign dbg_slave_axi_req.w_valid = dbg_slave_axi_wvalid; + assign dbg_slave_axi_req.b_ready = dbg_slave_axi_bready; + assign dbg_slave_axi_req.ar.addr = dbg_slave_axi_araddr; + assign dbg_slave_axi_req.ar.len = dbg_slave_axi_arlen; + assign dbg_slave_axi_req.ar.size = dbg_slave_axi_arsize; + assign dbg_slave_axi_req.ar.burst = dbg_slave_axi_arburst; + assign dbg_slave_axi_req.ar.lock = dbg_slave_axi_arlock; + assign dbg_slave_axi_req.ar.cache = dbg_slave_axi_arcache; + assign dbg_slave_axi_req.ar.prot = dbg_slave_axi_arprot; + assign dbg_slave_axi_req.ar.qos = dbg_slave_axi_arqos; + assign dbg_slave_axi_req.ar.region = dbg_slave_axi_arregion; + assign dbg_slave_axi_req.ar_valid = dbg_slave_axi_arvalid; + assign dbg_slave_axi_req.r_ready = dbg_slave_axi_rready; + assign dbg_slave_axi_req.ar.id = dbg_slave_axi_arid; + + // AXI slave response + assign dbg_slave_axi_awready = dbg_slave_axi_resp.aw_ready ; + assign dbg_slave_axi_wready = dbg_slave_axi_resp.w_ready ; + assign dbg_slave_axi_bid = dbg_slave_axi_resp.b.id ; + assign dbg_slave_axi_bresp = dbg_slave_axi_resp.b.resp ; + assign dbg_slave_axi_bvalid = dbg_slave_axi_resp.b_valid ; + assign dbg_slave_axi_arready = dbg_slave_axi_resp.ar_ready ; + assign dbg_slave_axi_rid = dbg_slave_axi_resp.r.id ; + assign dbg_slave_axi_rdata = dbg_slave_axi_resp.r.data ; + assign dbg_slave_axi_rresp = dbg_slave_axi_resp.r.resp ; + assign dbg_slave_axi_rlast = dbg_slave_axi_resp.r.last ; + assign dbg_slave_axi_rvalid = dbg_slave_axi_resp.r_valid ; + + // AXI master request + assign dbg_master_axi_awid = dbg_master_axi_req.aw.id; + assign dbg_master_axi_awaddr = dbg_master_axi_req.aw.addr; + assign dbg_master_axi_awlen = dbg_master_axi_req.aw.len; + assign dbg_master_axi_awsize = dbg_master_axi_req.aw.size; + assign dbg_master_axi_awburst = dbg_master_axi_req.aw.burst; + assign dbg_master_axi_awlock = dbg_master_axi_req.aw.lock; + assign dbg_master_axi_awcache = dbg_master_axi_req.aw.cache; + assign dbg_master_axi_awprot = dbg_master_axi_req.aw.prot; + assign dbg_master_axi_awqos = dbg_master_axi_req.aw.qos; + assign dbg_master_axi_awregion = dbg_master_axi_req.aw.region; + assign dbg_master_axi_awvalid = dbg_master_axi_req.aw_valid; + assign dbg_master_axi_wdata = dbg_master_axi_req.w.data; + assign dbg_master_axi_wstrb = dbg_master_axi_req.w.strb; + assign dbg_master_axi_wlast = dbg_master_axi_req.w.last; + assign dbg_master_axi_wvalid = dbg_master_axi_req.w_valid; + assign dbg_master_axi_bready = dbg_master_axi_req.b_ready; + assign dbg_master_axi_araddr = dbg_master_axi_req.ar.addr; + assign dbg_master_axi_arlen = dbg_master_axi_req.ar.len; + assign dbg_master_axi_arsize = dbg_master_axi_req.ar.size; + assign dbg_master_axi_arburst = dbg_master_axi_req.ar.burst; + assign dbg_master_axi_arlock = dbg_master_axi_req.ar.lock; + assign dbg_master_axi_arcache = dbg_master_axi_req.ar.cache; + assign dbg_master_axi_arprot = dbg_master_axi_req.ar.prot; + assign dbg_master_axi_arqos = dbg_master_axi_req.ar.qos; + assign dbg_master_axi_arregion = dbg_master_axi_req.ar.region; + assign dbg_master_axi_arvalid = dbg_master_axi_req.ar_valid; + assign dbg_master_axi_rready = dbg_master_axi_req.r_ready; + assign dbg_master_axi_arid = dbg_master_axi_req.ar.id; + + // AXI master response + assign dbg_master_axi_resp.aw_ready = dbg_master_axi_awready; + assign dbg_master_axi_resp.w_ready = dbg_master_axi_wready; + assign dbg_master_axi_resp.b.id = dbg_master_axi_bid; + assign dbg_master_axi_resp.b.resp = dbg_master_axi_bresp; + assign dbg_master_axi_resp.b_valid = dbg_master_axi_bvalid; + assign dbg_master_axi_resp.ar_ready = dbg_master_axi_arready; + assign dbg_master_axi_resp.r.id = dbg_master_axi_rid; + assign dbg_master_axi_resp.r.data = dbg_master_axi_rdata; + assign dbg_master_axi_resp.r.resp = dbg_master_axi_rresp; + assign dbg_master_axi_resp.r.last = dbg_master_axi_rlast; + assign dbg_master_axi_resp.r_valid = dbg_master_axi_rvalid; + + +endmodule : custom_top_wrapper + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..bde123cef1328627fdf78b5aacb51b9633b605d9 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv64_dbg_bscane/fetch_sources.sh @@ -0,0 +1,56 @@ +#!/bin/bash +# Author: Vincenzo Maisto +# Description: +# This script uses bender to download riscv-dbg and axi sources, and flattens them into the rtl/ directory + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + + +# Create rtl dir +RTL_DIR=$(pwd)/rtl +mkdir ${RTL_DIR} + +############## +# Bender.yml # +############## + +# Move into assets dir +cd assets/ + +# Download Bender +printf "${YELLOW}[FETCH_SOURCES] Download Bender${NC}\n" +curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh + +# Download dependencies (specify Target RTL and FPGA) +printf "${YELLOW}[FETCH_SOURCES] Resolve dependencies with Bender${NC}\n" +./bender checkout +BENDER_TARGETS="-t xilinx -t bscane" +./bender script flist ${BENDER_TARGETS} > rtl.flist + +# Copy all RTL files into rtl dir +printf "${YELLOW}[FETCH_SOURCES] Copy all sources into ${RTL_DIR}/${NC}\n" s +for rtl_file in $(cat rtl.flist) ; do + cp $rtl_file ${RTL_DIR} +done; + +# Add header files, not listed by bender +CLONE_DIR=.bender +cp $(find ${CLONE_DIR} -name typedef.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name assertions.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name registers.svh) ${RTL_DIR}/ +cp $(find ${CLONE_DIR} -name assign.svh) ${RTL_DIR}/ + +# Remove interface-based files, since Vivado does not like them +rm $(find ${RTL_DIR}/ -name axi_intf.sv) + +# Patch files for flat includes +for rtl_file in ${RTL_DIR}/* ; do + sed -i "s|\`include \"common_cells\/|\`include \"|g" $rtl_file + sed -i "s|\`include \"axi\/|\`include \"|g" $rtl_file +done + +# Info +printf "${GREEN}[FETCH_SOURCES] Completed${NC}\n" \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7a8d41a8ee684763b95950815e899dfea429916a --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/.gitignore @@ -0,0 +1 @@ +otp/ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/Bender.lock b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/Bender.lock new file mode 100644 index 0000000000000000000000000000000000000000..1d5c9495f030dd745d6dd976831abd09c06cb35f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/Bender.lock @@ -0,0 +1,48 @@ +packages: + apb: + revision: 77ddf073f194d44b9119949d2421be59789e69ae + version: 0.2.4 + source: + Git: https://github.com/pulp-platform/apb.git + dependencies: + - common_cells + axi: + revision: 78831b6feba265d5ee2683bbf42b4150f8a35c43 + version: 0.39.8 + source: + Git: https://github.com/pulp-platform/axi.git + dependencies: + - common_cells + - common_verification + - tech_cells_generic + common_cells: + revision: 9afda9abb565971649c2aa0985639c096f351171 + version: 1.38.0 + source: + Git: https://github.com/pulp-platform/common_cells.git + dependencies: + - common_verification + - tech_cells_generic + common_verification: + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 + source: + Git: https://github.com/pulp-platform/common_verification.git + dependencies: [] + register_interface: + revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 + version: 0.4.5 + source: + Git: https://github.com/pulp-platform/register_interface.git + dependencies: + - apb + - axi + - common_cells + - common_verification + tech_cells_generic: + revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf + version: 0.2.13 + source: + Git: https://github.com/pulp-platform/tech_cells_generic.git + dependencies: + - common_verification diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/Bender.yml b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/Bender.yml new file mode 100644 index 0000000000000000000000000000000000000000..16dfd63e47ae0d16744b6c399217dec35acd53a7 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/Bender.yml @@ -0,0 +1,141 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package: + name: opentitan_peripherals + authors: + - "Paul Scheffler " # current maintainer + - "lowRISC Contributors" + +dependencies: + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.25.0 } + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.5 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.8 } + +vendor_package: + - name: lowrisc_opentitan + target_dir: "." + upstream: { git: "https://github.com/lowRISC/opentitan.git", rev: "9f497f6339b4484fc5b7e5dc5d4bc63f55ec3c35" } + patch_dir: "patches" + mapping: + # Hardware + - {from: 'hw/ip/prim', to: 'src/prim', patch_dir: 'prim'} + - {from: 'hw/ip/gpio', to: 'src/gpio', patch_dir: 'gpio'} + - {from: 'hw/ip/i2c', to: 'src/i2c', patch_dir: 'i2c'} + - {from: 'hw/ip/spi_host', to: 'src/spi_host', patch_dir: 'spi_host'} + - {from: 'hw/ip_templates/rv_plic/data', to: 'src/rv_plic/tpl/rv_plic/data', patch_dir: 'rv_plic/tpl/data'} + - {from: 'hw/ip_templates/rv_plic/rtl', to: 'src/rv_plic/tpl/rv_plic/rtl', patch_dir: 'rv_plic/tpl/rtl'} + # Software dependencies + - {from: 'sw/device/lib/base/internal', to: 'sw/device/lib/base/internal'} + - {from: 'sw/device/lib/base/macros.h', to: 'sw/device/lib/base/macros.h'} + - {from: 'sw/device/lib/base/multibits.h', to: 'sw/device/lib/base/multibits.h'} + - {from: 'sw/device/lib/base/memory.c', to: 'sw/device/lib/base/memory.c'} + - {from: 'sw/device/lib/base/memory.h', to: 'sw/device/lib/base/memory.h'} + - {from: 'sw/device/lib/base/bitfield.c', to: 'sw/device/lib/base/bitfield.c'} + - {from: 'sw/device/lib/base/bitfield.h', to: 'sw/device/lib/base/bitfield.h'} + - {from: 'sw/device/lib/base/mmio.c', to: 'sw/device/lib/base/mmio.c'} + - {from: 'sw/device/lib/base/mmio.h', to: 'sw/device/lib/base/mmio.h'} + - {from: 'sw/device/lib/dif/dif_base.c', to: 'sw/device/lib/dif/dif_base.c'} + - {from: 'sw/device/lib/dif/dif_base.h', to: 'sw/device/lib/dif/dif_base.h'} + # Autogenerated SW + # Note: these only work as-is as we changed nothing except the TL-UL interface + - {from: 'sw/device/lib/dif/autogen/dif_gpio_autogen.c', to: 'sw/device/lib/dif/autogen/dif_gpio_autogen.c'} + - {from: 'sw/device/lib/dif/autogen/dif_gpio_autogen.h', to: 'sw/device/lib/dif/autogen/dif_gpio_autogen.h'} + - {from: 'sw/device/lib/dif/autogen/dif_i2c_autogen.c', to: 'sw/device/lib/dif/autogen/dif_i2c_autogen.c'} + - {from: 'sw/device/lib/dif/autogen/dif_i2c_autogen.h', to: 'sw/device/lib/dif/autogen/dif_i2c_autogen.h'} + - {from: 'sw/device/lib/dif/autogen/dif_spi_host_autogen.c', to: 'sw/device/lib/dif/autogen/dif_spi_host_autogen.c'} + - {from: 'sw/device/lib/dif/autogen/dif_spi_host_autogen.h', to: 'sw/device/lib/dif/autogen/dif_spi_host_autogen.h'} + - {from: 'sw/device/lib/dif/autogen/dif_rv_plic_autogen.c', to: 'sw/device/lib/dif/autogen/dif_rv_plic_autogen.c'} + - {from: 'sw/device/lib/dif/autogen/dif_rv_plic_autogen.h', to: 'sw/device/lib/dif/autogen/dif_rv_plic_autogen.h'} + # Main DIFs + - {from: 'sw/device/lib/dif/dif_gpio.c', to: 'sw/device/lib/dif/dif_gpio.c'} + - {from: 'sw/device/lib/dif/dif_gpio.h', to: 'sw/device/lib/dif/dif_gpio.h'} + - {from: 'sw/device/lib/dif/dif_i2c.c', to: 'sw/device/lib/dif/dif_i2c.c'} + - {from: 'sw/device/lib/dif/dif_i2c.h', to: 'sw/device/lib/dif/dif_i2c.h'} + - {from: 'sw/device/lib/dif/dif_spi_host.c', to: 'sw/device/lib/dif/dif_spi_host.c', patch_dir: 'sw/dif_spi_host_c'} + - {from: 'sw/device/lib/dif/dif_spi_host.h', to: 'sw/device/lib/dif/dif_spi_host.h', patch_dir: 'sw/dif_spi_host_h'} + - {from: 'sw/device/lib/dif/dif_rv_plic.c', to: 'sw/device/lib/dif/dif_rv_plic.c', patch_dir: 'sw/dif_rv_plic_c'} + - {from: 'sw/device/lib/dif/dif_rv_plic.h', to: 'sw/device/lib/dif/dif_rv_plic.h'} + # Utilities + - {from: 'util/ipgen', to: 'util/ipgen', patch_dir: 'ipgen'} + - {from: 'util/ipgen.py', to: 'util/ipgen.py'} + exclude_from_upstream: + - "*.core" + - "*doc" + - "*dv" + - "*lint" + - "*fpv" + - "*.prj.hjson" + - "*_testplan.hjson" + - "*_testplan.hjson.tpl" + - "*README.md" + - "*BUILD" + # We do not need primitive generation + - "hw/ip/prim/util" + # Exclude various primitives to reduce clutter (keep in sync with sources) + - "hw/ip/prim/rtl/*.svh*" + - "hw/ip/prim/rtl/prim_[!fipsum]*" + - "hw/ip/prim/rtl/prim_m[us]*" + - "hw/ip/prim/rtl/prim_flop_[e]*" + - "hw/ip/prim/rtl/prim_sec*" + - "hw/ip/prim/rtl/prim_subreg*" + - "hw/ip/prim/rtl/prim_sum_tree.sv" + - "hw/ip/prim/rtl/prim_sparse_fsm_flop.sv" + # Exclude ipgen tests + - "util/ipgen/tests" + +sources: + ### lowRISC Primitives ### + # Patched in + - src/prim/prim_pulp_platform/prim_flop_2sync.sv + - src/prim/prim_pulp_platform/prim_flop_en.sv + # Level 0 + - src/prim/rtl/prim_fifo_sync_cnt.sv + - src/prim/rtl/prim_util_pkg.sv + # Level 1 + - src/prim/rtl/prim_max_tree.sv + - src/prim/rtl/prim_sync_reqack.sv + - src/prim/rtl/prim_sync_reqack_data.sv + - src/prim/rtl/prim_pulse_sync.sv + - src/prim/rtl/prim_packer_fifo.sv + - src/prim/rtl/prim_fifo_sync.sv + - src/prim/rtl/prim_filter_ctr.sv + - src/prim/rtl/prim_intr_hw.sv + + # Level 2 + - src/prim/rtl/prim_fifo_async.sv + ### Peripheral sources ### + # Level 0 (generated, see README for regeneration) + - src/gpio/rtl/gpio_reg_pkg.sv + - src/i2c/rtl/i2c_reg_pkg.sv + - src/rv_plic/rtl/rv_plic_reg_pkg.sv + - src/spi_host/rtl/spi_host_reg_pkg.sv + # Level 1 (generated, see README for regeneration) + - src/gpio/rtl/gpio_reg_top.sv + - src/i2c/rtl/i2c_reg_top.sv + - src/rv_plic/rtl/rv_plic_reg_top.sv + - src/spi_host/rtl/spi_host_reg_top.sv + # Level 2 + - src/i2c/rtl/i2c_pkg.sv + # Level 3 + - src/i2c/rtl/i2c_fsm.sv + - src/rv_plic/rtl/rv_plic_gateway.sv + - src/spi_host/rtl/spi_host_byte_merge.sv + - src/spi_host/rtl/spi_host_byte_select.sv + - src/spi_host/rtl/spi_host_cmd_pkg.sv + - src/spi_host/rtl/spi_host_command_queue.sv + - src/spi_host/rtl/spi_host_fsm.sv + - src/spi_host/rtl/spi_host_window.sv + - src/spi_host/rtl/spi_host_data_fifos.sv + - src/spi_host/rtl/spi_host_shift_register.sv + # Level 4 + - src/i2c/rtl/i2c_core.sv + - src/rv_plic/rtl/rv_plic_target.sv + - src/spi_host/rtl/spi_host_core.sv + # Level 5 + - src/gpio/rtl/gpio.sv + - src/i2c/rtl/i2c.sv + - src/spi_host/rtl/spi_host.sv + - src/rv_plic/rtl/rv_plic.sv diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/otp.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/otp.mk new file mode 100644 index 0000000000000000000000000000000000000000..e7ed8c8ea780a6e66f97165448378c4b12393f8b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/assets/otp.mk @@ -0,0 +1,57 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Paul Scheffler + +# Import this GNU Make fragment in your project's makefile to regenerate and +# reconfigure these IPs. You can modify the original RTL, configuration, and +# templates from your project without entering this dependency repo by adding +# build targets for them. To build the IPs, `make otp`. + +# You may need to adapt these environment variables to your configuration. +BENDER ?= bender +REGTOOL ?= $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py +PLICOPT ?= -s 32 -t 1 -p 7 + +OTPROOT ?= $(shell $(BENDER) path opentitan_peripherals) +IPGEN ?= $(OTPROOT)/util/ipgen.py +DIFGEN ?= $(OTPROOT)/util/make_new_dif.py + +_otp: otp_rv_plic + +# PLIC generation inputs and outputs +OTP_PLIC_TPLD = $(OTPROOT)/src/rv_plic/tpl/rv_plic +OTP_PLIC_IN = $(addprefix $(OTP_PLIC_TPLD)/rtl/, rv_plic.sv.tpl rv_plic_gateway.sv.tpl rv_plic_target.sv.tpl) +OTP_PLIC_IN += $(addprefix $(OTP_PLIC_TPLD)/data/, rv_plic.hjson.tpl rv_plic.tpldesc.hjson) +OTP_PLIC_OUTD = $(OTPROOT)/src/rv_plic +OTP_PLIC_OUT = $(addprefix $(OTP_PLIC_OUTD)/rtl/, rv_plic.sv rv_plic_gateway.sv rv_plic_target.sv) +OTP_PLIC_OUT += $(addprefix $(OTP_PLIC_OUTD)/data/, rv_plic.hjson rv_plic.ipconfig.hjson) + +# Only one target must be built to build them all +otp_rv_plic: $(OTP_PLIC_OUTD)/rtl/rv_plic.sv + +$(OTP_PLIC_OUT): $(OTP_PLIC_IN) + rm -rf $(OTP_PLIC_OUTD)/gen + PYTHONPATH=$(dir $(REGTOOL)) python3.10 $(IPGEN) generate -C $(OTP_PLIC_TPLD) -o $(OTP_PLIC_OUTD)/gen -c $(OTPROOT)/src/rv_plic/rv_plic.cfg.hjson + cp -a --no-preserve=mode $(OTP_PLIC_OUTD)/gen/* $(OTP_PLIC_OUTD)/ + rm -rf $(OTP_PLIC_OUTD)/gen + +# Generate software for peripherals +OTP_REG_DIR = $(OTPROOT)/sw/include + +define hdr_gen_rule +OTP_REG_HDRS += $$(OTP_REG_DIR)/$(1)_regs.h + +$$(OTP_REG_DIR)/$(1)_regs.h: $(2) otp_$(1) + @mkdir -p $$(dir $$@) + $$(REGTOOL) --cdefines $$< > $$@ +endef + +$(eval $(call hdr_gen_rule,rv_plic,$(OTPROOT)/src/rv_plic/data/rv_plic.hjson)) + +otp_reg_hdrs: $(OTP_REG_HDRS) + +otp: + @echo '[PULP] Generate OpenTitan peripherals: PLIC Only' + @$(MAKE) -B _otp diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/custom_top_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/custom_top_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..5d296e02572d6fd8b454015a2edca4ae28231f4a --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/custom_top_wrapper.sv @@ -0,0 +1,207 @@ +// Author: Valerio Di Domenico +// Author: Stefano Mercogliano +// Description: Top level wrapper module for PULP DTM and AXI adapters, 32-bit version. + + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" +`include "axi_typedef.svh" +`include "reg_typedef.svh" +`include "assertions.svh" + +import axi_pkg::*; + +module custom_top_wrapper # ( + + ////////////////////////////////////// + // Add here IP-related parameters // + ////////////////////////////////////// + + // Sources are the number of possible interrupts + // Targets are the number of harts receiving interrupts + parameter int unsigned SOURCE_NUM = 32, + parameter int unsigned TARGET_NUM = 1, + // 0 means level interrupts. 1 should be Edge Trigger, but it is not supported + parameter logic [SOURCE_NUM-1:0] LEVEL_EDGE_TRIGGER = '0, + parameter int SRCW = $clog2(SOURCE_NUM), + + // TODO121: Automatically align with config + // AXI-related paraamters + parameter AXI_DATA_WIDTH = 32, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_STRB_WIDTH = AXI_ADDR_WIDTH / 8, + parameter AXI_ID_WIDTH = 4, + parameter AXI_USER_WIDTH = 2, + parameter AXI_REGION_WIDTH = 4, + parameter AXI_LEN_WIDTH = 8, + parameter AXI_SIZE_WIDTH = 3, + parameter AXI_BURST_WIDTH = 2, + parameter AXI_LOCK_WIDTH = 1, + parameter AXI_CACHE_WIDTH = 4, + parameter AXI_PROT_WIDTH = 3, + parameter AXI_QOS_WIDTH = 4, + parameter AXI_VALID_WIDTH = 1, + parameter AXI_READY_WIDTH = 1, + parameter AXI_LAST_WIDTH = 1, + parameter AXI_RESP_WIDTH = 2, + + // REG-related parameters + parameter int unsigned REG_DATA_WIDTH = 32, + parameter bit CUT_MEM_REQS = 1'b0, + parameter bit CUT_MEM_RSPS = 1'b0 + + +) ( + + /////////////////////////////////// + // Add here IP-related signals // + /////////////////////////////////// + + input logic clk_i, + input logic rst_ni, + + // Interrupt Sources + input [SOURCE_NUM-1:0] intr_src_i, + + // Interrupt notification to targets + output [TARGET_NUM-1:0] irq_o, + output [TARGET_NUM-1:0][SRCW-1:0] irq_id_o, + output logic [TARGET_NUM-1:0] msip_o, + + //////////////////////////// + // Bus Array Interfaces // + //////////////////////////// + + // AXI Slave Interface + `DEFINE_AXI_SLAVE_PORTS(s, AXI_DATA_WIDTH, AXI_ADDR_WIDTH, AXI_ID_WIDTH) +); + + //////////////////////// + // Signals Definition // + //////////////////////// + + // First, we need to redefine the pulp axi types and reg types. + // Define the req_t and resp_t type using axi_typedef.svh macro + `AXI_TYPEDEF_ALL( + axi, + logic [AXI_ADDR_WIDTH-1:0], + logic [AXI_ID_WIDTH-1:0], + logic [AXI_DATA_WIDTH-1:0], + logic [AXI_STRB_WIDTH-1:0], + logic [0:0] // This is for the user field, which is missing from our interface (or unused) + ) + // Define the req_t and resp_t type using reg_typedef.svh macro + `REG_BUS_TYPEDEF_ALL( + reg, + logic [AXI_ADDR_WIDTH-1:0], + logic [AXI_DATA_WIDTH-1:0], + logic [AXI_STRB_WIDTH-1:0] + ) + + // Instantiate intermediate signals to connect the axi converter to the reg-based plic interface + axi_req_t axi_req; + axi_resp_t axi_rsp; + reg_req_t reg_req; + reg_rsp_t reg_rsp; + + /////////////////////// + // Instantiate Units // + /////////////////////// + + logic [SRCW-1:0] irq_id_int[TARGET_NUM]; + + rv_plic #( + .reg_req_t ( reg_req_t ), + .reg_rsp_t ( reg_rsp_t ), + .LevelEdgeTrig ( LEVEL_EDGE_TRIGGER ) + + ) rv_plic_u ( + // Clock and Reset + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .reg_req_i ( reg_req ), + .reg_rsp_o ( reg_rsp ), + + // Interrupt Sources + .intr_src_i ( intr_src_i ), + + // Interrupt notification to targets + .irq_o ( irq_o ), + .irq_id_o ( irq_id_int ), + .msip_o ( msip_o ) + + ); + + axi_to_reg_v2 #( + .AxiAddrWidth ( AXI_ADDR_WIDTH ), + .AxiDataWidth ( AXI_DATA_WIDTH ), + .AxiIdWidth ( AXI_ID_WIDTH ), + .AxiUserWidth ( AXI_USER_WIDTH ), + .RegDataWidth ( REG_DATA_WIDTH ) , + .CutMemReqs ( CUT_MEM_REQS ) , + .CutMemRsps ( CUT_MEM_RSPS ) , + .axi_req_t ( axi_req_t), + .axi_rsp_t ( axi_resp_t), + .reg_req_t ( reg_req_t), + .reg_rsp_t ( reg_rsp_t), + .id_t ( logic[AXI_ID_WIDTH-1:0] ) + )axi_to_reg_v2_u ( + .clk_i (clk_i), + .rst_ni (rst_ni), + .axi_req_i (axi_req), + .axi_rsp_o (axi_rsp), + .reg_req_o (reg_req), + .reg_rsp_i (reg_rsp), + .reg_id_o ( ), + .busy_o ( ) + ); + + + // Map interrupt ports + for(genvar i = 0; i < TARGET_NUM; i++) + assign irq_id_o[i][SRCW-1:0] = irq_id_int[i]; + + // Map input/output AXI port + assign axi_req.aw.id = s_axi_awid; + assign axi_req.aw.addr = {'0, s_axi_awaddr[25:0]}; + assign axi_req.aw.len = s_axi_awlen; + assign axi_req.aw.size = s_axi_awsize; + assign axi_req.aw.burst = s_axi_awburst; + assign axi_req.aw.lock = s_axi_awlock; + assign axi_req.aw.cache = s_axi_awcache; + assign axi_req.aw.prot = s_axi_awprot; + assign axi_req.aw.qos = s_axi_awqos; + assign axi_req.aw.region = s_axi_awregion; + assign axi_req.aw_valid = s_axi_awvalid; + assign axi_req.w.data = s_axi_wdata; + assign axi_req.w.strb = s_axi_wstrb; + assign axi_req.w.last = s_axi_wlast; + assign axi_req.w_valid = s_axi_wvalid; + assign axi_req.b_ready = s_axi_bready; + assign axi_req.ar.addr = {'0, s_axi_araddr[25:0]}; + assign axi_req.ar.len = s_axi_arlen; + assign axi_req.ar.size = s_axi_arsize; + assign axi_req.ar.burst = s_axi_arburst; + assign axi_req.ar.lock = s_axi_arlock; + assign axi_req.ar.cache = s_axi_arcache; + assign axi_req.ar.prot = s_axi_arprot; + assign axi_req.ar.qos = s_axi_arqos; + assign axi_req.ar.region = s_axi_arregion; + assign axi_req.ar_valid = s_axi_arvalid; + assign axi_req.r_ready = s_axi_rready; + assign axi_req.ar.id = s_axi_arid; + + assign s_axi_awready = axi_rsp.aw_ready; + assign s_axi_wready = axi_rsp.w_ready; + assign s_axi_bid = axi_rsp.b.id; + assign s_axi_bresp = axi_rsp.b.resp; + assign s_axi_bvalid = axi_rsp.b_valid; + assign s_axi_arready = axi_rsp.ar_ready; + assign s_axi_rid = axi_rsp.r.id; + assign s_axi_rdata = axi_rsp.r.data; + assign s_axi_rresp = axi_rsp.r.resp; + assign s_axi_rlast = axi_rsp.r.last; + assign s_axi_rvalid = axi_rsp.r_valid; + +endmodule : custom_top_wrapper diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/fetch_sources.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/fetch_sources.sh new file mode 100644 index 0000000000000000000000000000000000000000..77197fae53b52ab09d79ce9c11b3ebfa47d5f13b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/custom_rv_plic/fetch_sources.sh @@ -0,0 +1,109 @@ +#!/bin/bash +# Author: Stefano Mercogliano , Valerio Di Domenico +# Description: +# This script fetches risc-v compliant PLIC sources. +# Files are mostly fetched from open-titan ips. + +RED='\033[1;31m' +GREEN='\033[1;32m' +YELLOW='\033[1;33m' +NC='\033[0m' # No Color + +# Directories +RTL_DIR=$(pwd)/rtl +ASSETS_DIR=$(pwd)/assets + +###################### +# Python Environment # +###################### + +# TODO142: migrate to venv + +# Install the required modules +echo -e "${YELLOW}[FETCH_SOURCES] Installing Python modules: hjson, tabulate, pyyaml, mako ...${NC}" +pip3.10 install --upgrade pip +pip3.10 install hjson tabulate pyyaml mako + +####################################### +# Fetch PLIC sources and depencencies # +####################################### + +# Create the rtl directory structure +# Create rtl dir +echo -e "${YELLOW}[FETCH_SOURCES] Creating the rtl directory structure${NC}" +mkdir ${RTL_DIR} + +echo -e "${YELLOW}[FETCH_SOURCES] Fetching Open-Titan Peripherals (aiming to PLIC) sources${NC}" +# clone repo (Release v1.8.3 Jul 15 2024) +GIT_URL=https://github.com/pulp-platform/opentitan_peripherals.git +GIT_TAG=v0.4.0 +CLONE_DIR=otp +git clone ${GIT_URL} -b ${GIT_TAG} --depth 1 ${CLONE_DIR} +cd ${CLONE_DIR}; + +echo -e "${YELLOW}[FETCH_SOURCES] Use Bender to retrieve dependencies ${NC}" +# Open-Titan peripherals (by PULP) requires a preliminar configuration and patching +# Apply hjson configurations and patches +cp ${ASSETS_DIR}/Bender.yml ./ +cp ${ASSETS_DIR}/otp.mk ./ +make -B otp; +cp ${ASSETS_DIR}/Bender.lock ./ +./bender checkout; + +###################################### +# Move PLIC sources and depencencies # +###################################### + +echo -e "${YELLOW}[FETCH_SOURCES] Configure and Patch${NC}" +DEP_REGISTER_INTERFACE="$(./bender path register_interface)" +DEP_AXI="$(./bender path axi)" +DEP_COMMON_CELLS="$(./bender path common_cells)" +cd ..; + +# Move Source Files +echo -e "${YELLOW}[FETCH_SOURCES] Move all RTL files${NC}" +cp ${CLONE_DIR}/src/rv_plic/rtl/* ${RTL_DIR}; +cp ${CLONE_DIR}/src/prim/rtl/* ${RTL_DIR}; +cp ${CLONE_DIR}/src/prim/prim_pulp_platform/* ${RTL_DIR}; + +cp ${DEP_REGISTER_INTERFACE}/src/*.sv ${RTL_DIR}; +cp ${DEP_REGISTER_INTERFACE}/vendor/lowrisc_opentitan/src/*.sv ${RTL_DIR}; +cp ${DEP_AXI}/src/*.sv ${RTL_DIR}; +cp ${DEP_COMMON_CELLS}/src/*.sv ${RTL_DIR}; + +# Move Header Files into flatten representation in rtl +cp ${DEP_COMMON_CELLS}/include/common_cells/*.svh ${RTL_DIR}; +for file in ${DEP_REGISTER_INTERFACE}/include/register_interface/*.svh; do [ -f "$file" ] && cp "$file" "${RTL_DIR}/reg_$(basename "$file")"; done +for file in ${DEP_AXI}/include/axi/*.svh; do [ -f "$file" ] && cp "$file" "${RTL_DIR}/axi_$(basename "$file")"; done + +################# +# Patch sources # +################# + +# We need a second step of local patching +# 1 - Remove absolute path in source files in order to allow a flatten source code organization +# 2 - Remove interface definitions as vivado complaints even if interfaces are not instantiated at all +echo -e "${YELLOW}[PATCH_SOURCES] Patching include paths for flat includes and specific substitutions${NC}" +for rtl_file in ${RTL_DIR}/*; do + if [[ -f $rtl_file ]]; then + # Flatten includes for common_cells + sed -i "s|\`include \"common_cells\/|\`include \"|g" $rtl_file + + # Specific substitutions + sed -i "s|\`include \"axi/typedef.svh\"|\`include \"axi_typedef.svh\"|g" $rtl_file + sed -i "s|\`include \"axi/assign.svh\"|\`include \"axi_assign.svh\"|g" $rtl_file + sed -i "s|\`include \"register_interface/typedef.svh\"|\`include \"reg_typedef.svh\"|g" $rtl_file + sed -i "s|\`include \"register_interface/assign.svh\"|\`include \"reg_assign.svh\"|g" $rtl_file + sed -i "s|\`include \"prim_assert.sv\"|\`include \"assertions.svh\"|g" $rtl_file + + # Remove interfaces + sed -i '/_intf #/{:a;N;/endmodule/!ba;d;}' "$rtl_file" + #sed -i '/module .*_intf/,$d' "$rtl_file" + fi +done + +rm ${RTL_DIR}/reg_intf.sv + +# Info +echo -e "${GREEN}[FETCH_SOURCES] Completed${NC}" + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/common/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/common/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..6e624fdee6c56953412ce84d2574be96984c7647 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/common/Makefile @@ -0,0 +1,70 @@ +############## +# Tools path # +############## + +GXX ?= g++ +VERILATOR ?= verilator +GTKWAVE ?= gtkwave + +# Verilator path - Insert here your include path +VERILATOR_INC = /usr/share/verilator/include +VLTSTD_INC = /usr/share/verilator/include/vltstd/ + +####################### +# Project directories # +####################### + +# Unit-Under-Test top module sv file name +PROJECT_NAME ?= test +# Directory containing the RTL module +RTL_DIR = rtl +# Directory containing the TestBench module +TB_DIR = tb +# Directory containing the simulation traces (waves) +WAVES_DIR = waves +# Directory containing the simulation executable +BIN_DIR = bin +# Directory containing the verilator generated files +VGEN_DIR = verilator + +####################### +# Verilator Testbench # +####################### + +# TestBench name for UUT +TB = $(TB_DIR)/$(PROJECT_NAME)_tb + +# Add here all the .sv dependencies dirs (e.g. -y dir0 -y dir1 -y dir2 etc.) +SV_INC_DIR = +# TestBench included cpp files, separated by space (e.g. $(RTL_DIR)/module0.cpp $(RTL_DIR)/module1.cpp $(RTL_DIR)/module2.cpp etc.) +TB_INC_DIR = +TB_SRC_DIR = +# Verilator warning suppression. (Check https://verilator.org/guide/latest/warnings.html) +WARNINGSBYPASS = -Wno-UNUSED -Wno-PINCONNECTEMPTY -Wno-SYNCASYNCNET -Wno-IMPORTSTAR -Wno-MODDUP +# Enable Verilator debug messages +VERILATOR_DEBUG = #--debug --gdbbt + +verilate: + $(VERILATOR) $(VERILATOR_DEBUG) -Wall $(WARNINGSBYPASS) --top-module $(PROJECT_NAME) --trace -cc $(PROJECT_NAME)/$(RTL_DIR)/$(PROJECT_NAME).sv $(SV_INC_DIR); + @if [ -d "obj_dir" ]; then cp obj_dir/* $(PROJECT_NAME)/$(VGEN_DIR); rm -r obj_dir; else echo "[Error] Verilator files were not correctly created"; fi; + cd $(PROJECT_NAME)/$(VGEN_DIR); make -f V$(PROJECT_NAME).mk + +compile: + $(GXX) \ + -I $(VERILATOR_INC) -I $(VLTSTD_INC) -I $(PROJECT_NAME)/$(VGEN_DIR) -I $(PROJECT_NAME)/$(TB_DIR) \ + $(VERILATOR_INC)/verilated.cpp $(VERILATOR_INC)/verilated_vcd_c.cpp \ + $(PROJECT_NAME)/$(TB).cpp $(TB_INC_DIR) \ + $(PROJECT_NAME)/$(VGEN_DIR)/V$(PROJECT_NAME)__ALL.a -o $(PROJECT_NAME)/$(BIN_DIR)/$(PROJECT_NAME)_run + +run: + $(PROJECT_NAME)/$(BIN_DIR)/$(PROJECT_NAME)_run + +wave: + $(GTKWAVE) $(WAVES_DIR)/trace.vcd $(WAVES_DIR)/conf.gtkw & + +clean: + rm -f $(PROJECT_NAME)/$(VGEN_DIR)/* + rm -f "$(PROJECT_NAME)/$(BIN_DIR)/$(PROJECT_NAME)_run + rm -f $(PROJECT_NAME)/$(WAVES_DIR)/trace.vcd; + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/create_project.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/create_project.sh new file mode 100644 index 0000000000000000000000000000000000000000..4ea2244ec214d093be7f0350fc2f9c99d0a3fd60 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/create_project.sh @@ -0,0 +1,44 @@ +#!/bin/bash + +####################### +# Project directories # +####################### + +# Unit-Under-Test top module sv file name +PROJECT_NAME=test.prj +if [ $1 != "" ]; then + PROJECT_NAME=$1.prj +fi +# Directory containing the RTL module +RTL_DIR=src/rtl +# Directory containing the TestBench module +TB_DIR=tb +# Directory containing the simulation traces (waves) +WAVES_DIR=waves +# Directory containing the simulation executable +BIN_DIR=bin +# Directory containing the verilator generated files +VGEN_DIR=verilator + +####################### +# Verilator Testbench # +####################### + +# TestBench name for UUT +TB=${TB_DIR}/${PROJECT_NAME}_tb + +if [ -d "${PROJECT_NAME}" ]; then + echo "[Error] Project directory ${PROJECT_NAME} already exists" +else + # Copy the whole template directory + cp -r template.prj/ ${PROJECT_NAME} + # Create artifact directories + mkdir ${PROJECT_NAME}/${BIN_DIR} + mkdir ${PROJECT_NAME}/${VGEN_DIR} + mkdir ${PROJECT_NAME}/${WAVES_DIR} + # Rename tb module + mv ${PROJECT_NAME}/${TB_DIR}/template_tb.cpp ${PROJECT_NAME}/${TB_DIR}/${PROJECT_NAME}_tb.cpp + sed -i 's/template.prj/\${PROJECT_NAME}/g' ${PROJECT_NAME}/${TB_DIR}/${PROJECT_NAME}_tb.cpp +fi + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..160738005e4593e87edc9655cae8a68623752ad9 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/Makefile @@ -0,0 +1,8 @@ +# Variables override +# <...> + +# Include common Makefile +include ../common/Makefile + +# Project-specific targets +# <...> \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/rtl/template.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/rtl/template.sv new file mode 100644 index 0000000000000000000000000000000000000000..4eba6db17283d3c69849184b9b89423c0203ab25 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/rtl/template.sv @@ -0,0 +1,9 @@ +module template( + input logic rstn_i, + input logic clk_i, + input logic a_i, + output logic bit_o + ); + + assign bit_o = a_i | 1'b1; +endmodule diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/tb/template_tb.cpp b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/tb/template_tb.cpp new file mode 100644 index 0000000000000000000000000000000000000000..273b2f9c98804a9fabd898be1e17bd86e93ac9f3 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/units/sim/template.prj/tb/template_tb.cpp @@ -0,0 +1,60 @@ +#include +#include +#include "Vdummy.h" +#include "verilated_vcd_c.h" +#include "verilated.h" + +#define CLK_NS 20 +#define CYCLES 1000 + +void tick(int tickcount, Vdummy *tb, VerilatedVcdC *tfp); +void trace_init(Vdummy *tb, VerilatedVcdC * tfp); + +int main(int argc, char **argv){ + + Vdummy * tb = new Vdummy; + VerilatedVcdC * tfp = new VerilatedVcdC; + + unsigned tickcount = 0; + trace_init(tb,tfp); + + printf("Welcome to Verilator Simulation\n\n"); + + for(int i = 0; i < CYCLES; i++){ + + (i == 0) ? tb->rstn_i = 0 : tb->rstn_i = 1; + + tick(++tickcount,tb,tfp); + + } + + delete tb; + delete tfp; + +} + +void tick(int tickcount, Vdummy *tb, VerilatedVcdC *tfp){ + tb->eval(); + if(tfp) //dump 2ns before the tick + tfp->dump(tickcount*CLK_NS - 2); + tb->clk_i = 1; + tb->eval(); + if(tfp) //Tick every CLK_NS + tfp->dump(tickcount*CLK_NS); + tb->clk_i = 0; + tb->eval(); + if(tfp){ //Trailing edge dump + tfp->dump(tickcount*CLK_NS+5); + tfp->flush(); + } +} + +void trace_init(Vdummy *tb, VerilatedVcdC * tfp){ + + Verilated::traceEverOn(true); + + tb->trace(tfp,99); + tfp->open("waves/trace.vcd"); +} + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..df4b4ad30c2035fba1210325ca3ed7d93004b749 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/.gitignore @@ -0,0 +1,11 @@ +# Phony xci IP files +*.xci + +# Xilinx local artifacts +.Xil +# Memory initialization files +*.mif +# Vivado outputs +.Xil +vivado* +webtalk* \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..cdfeea051e87f2ea0b2ede41200dc7d08e0967af --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/Makefile @@ -0,0 +1,65 @@ +# Environment check +ifndef XILINX_ROOT +$(error Setup script settings.sh has not been sourced, aborting) +endif + +######################### +# Include configuration # +######################### + +include make/config.mk + +###################### +# Vivado environment # +###################### + +include make/environment.mk + +# Default target +all: bitstream + +######### +# Build # +######### + +include make/build.mk + +############# +# Utilities # +############# + +include make/utils.mk + +############## +# Simulation # +############## + +include make/sim.mk + +############### +# Load binary # +############### + +include make/load_binary.mk + +############ +# Cleaning # +############ +# Clean up project +clean: + rm -rf ${XILINX_PROJECT_BUILD_DIR} + rm -rf vivado*.log vivado*.jou vivado*.str + +clean_ips/%.xci: + rm -rf ${XILINX_IPS_ROOT}/*/$*/build + rm -rf ${XILINX_IPS_ROOT}/$*.xci + +clean_ips: + rm -rf ${XILINX_IPS_ROOT}/*/*/build + rm -rf ${XILINX_IPS_ROOT}/*.xci + +########### +# PHONIES # +########### +.PHONY: bitstream ips clean clean_ips + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/README.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/README.md new file mode 100644 index 0000000000000000000000000000000000000000..1e107ad4f34f3c95971bcfcf7038e339c6e167ef --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/README.md @@ -0,0 +1,108 @@ +# Xilinx FPGA Flow +This tree holds the building environment for Xilinx FPGAs. + +## Installation + +Additional installation-related technical documentation can be found in the `doc/` folder for: +* [UART FDTI connection](doc/UART_CONNECTION.md). +* [Board-specific installation instructions](doc/BOARDS_INSTALLATION.md). +* [Linux-specific instructions for Vivado](doc/INSTALL_CABLE_DRIVERS.md). +* [Vivado-specific patches](doc/VIVADO_PATCHES.md). + + +## Build Bitstream and Program Device +In order to build the bitstream all sources for custom IPs must be available for the project. +Check [hw/units/README.md](../units/README.md) for more info. + +To build Xilinx and custom IPs: +``` bash +make ips -j +make ips/.xci # For a single IP +``` + +To build the bitstream just run: +``` bash +make bistream +``` +Bitstream build parameters: + +| Parameter | Description | Default | Supported values | +|---------------------|-----------------------------------------------|----------------------------|---------------------------| +| SYNTH_STRATEGY | Vivado synthesis strategy | Flow_PerfOptimized_high | Vivado-version compatible | +| IMPL_STRATEGY | Vivado implementation strategy | Performance_ExtraTimingOpt | Vivado-version compatible | +| XILINX_ILA | Enable ILA for marked nets (see below) | 0 | 0,1 | +| XILINX_ILA_CLOCK | Clock for ILA probes | main_clk | Legal clock in the design | + +Once the build is completed, program target device running: +``` bash +make program_bitstream +``` +Program bitstream parameters: +| Parameter | Description | Default | Supported values | +|--------------------------|---------------------------|-----------------|------------------| +| XILINX_VIVADO_MODE | Vivado `-mode` flag value | batch | batch, tcl, gui | +| XILINX_PROJECT_BUILD_DIR | Target build directory | hw/xilinx/build | Legal directory | +| XILINX_BITSTREAM | Target bitstream file | `${XILINX_PROJECT_BUILD_DIR}`/uninasoc.runs/impl_1/uninasoc.bit | Legal file path | +| XILINX_PROBE_LTX | Target probe file | `${XILINX_PROJECT_BUILD_DIR}`/uninasoc.runs/impl_1/uninasoc.ltx | Legal file path | + +## Directory Structure +This tree is structured as follows: +``` +├── ips # Xilinx IPs directory +│ ├── common # Common IPs (both hpc and embedded) +│ │ ├── tcl # Common IP flow scripts +│ │ | ├── post_config.tcl +| | | └── pre_config.tcl +│ | └── # IP directory, configuration-specific +│ │ └── config.tcl # Script setting IP properties +| ├── embedded # Embedded IPs +| └── hpc # HPC IPs +├── make # Included Makefiles +├── Makefile # Top Make file for Xilinx flow +├── README.md # This file +├── rtl # RTL sources +├── scripts # Utilty scripts +├── sim # Xilinx-specific simulation +└── synth # Xilinx-specific synthesis + ├── constraints # Constraint files for Xilinx FPGA designs + └── tcl # Synthesis-related TCL scripts +``` + +## IPs Flow +The system features both Xilinx-provided and custom IPs. + +### Add and Configure a Xilinx IP +IPs are characterized by being profile-specific (hpc or embedded) or common: +* `ips/common/` +* `ips/embedded/` +* `ips/hpc/` + +The name of the directory will be the name of your IP in the design. In the directory, put a single file `config.tcl` with the two basic commands to import your target IP: +* `create_ip ... -module_name $::env(IP_NAME)` +* `set_property -dict [list CONFIG. {} CONFIG. {} ...] [get_ips $::env(IP_NAME)]` + +(Re-)configure the IP by: +1. Editing the property keys and values in `config.tcl`; +2. Running `make ips/.xci` +> NOTE: Vivado versions must match between IP build and IP import during system build. + +## Custom IPs +Custom IPs are built alongside Xilinx IPs. + +For further info on custom IPs see [related documentation](../units/README.md). + +## In-system Debug Probing with Xilinx ILAs +This environment supports the automatic insertion of Internal Logic Analyzer (ILA) probes, ([PG172](https://docs.amd.com/v/u/en-US/pg172-ila) ). + +ILA probes are enabled by default, and can be disabled by setting the envvar `XILINX_ILA=0`. +To add probe on a net, you should mark it as `MARK_DEBUG=1` or `TRUE`, in one of the following ways: +* Mark it in RTL with a source code specifier, e.g. `(* MARK_DEBUG = "TRUE" *) wire debug_wire;` +* Mark it in the [hw/xilinx/synth/tcl/mark_debug_nets.tcl](hw/xilinx/synth/tcl/mark_debug_nets.tcl) script, e.g. `set_property MARK_DEBUG true [get_nets ...]` + +### Notes on Using ILAs +1. Using the ILA core adds a few minutes to the synthesis flow. +2. Max 1023 nets can be probed in the current single-ILA setup. +3. Adding many probes might complicate the design and make it more difficult to route. + +## Running Software +To load and run software on the platform, check the [related documentation](doc/PROGRAM_LOADING.md). diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/BOARDS_INSTALLATION.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/BOARDS_INSTALLATION.md new file mode 100644 index 0000000000000000000000000000000000000000..3d44e8c282b35edd90ca0d038b08b6fe85a3b3ca --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/BOARDS_INSTALLATION.md @@ -0,0 +1,25 @@ +# Board installation +In the following the required installation steps for the supported boards + +## Nexys, Basys, Arty, Zybo and Zedboard Families +Verified on Vivado 2022.1 (should be working from 2015.1 onward): + - Download the [Digilent Legacy board files](https://github.com/Digilent/vivado-boards/archive/master.zip) + - Extract the downloaded zip and copy new/board_files/* into \/data/boards/board_files + - Restart vivado + +## Alveo U250 +Verified on Vivado 2023.1 and 2024.1: + - Download the [Alveo U250 board files](https://www.xilinx.com/bin/public/openDownload?filename=au250_board_files_20200616.zip) + - Extract the downloaded zip into \/data/xhub/boards/XilinxBoardStore/boards/Xilinx/ + - Restart Vivado + +## Alveo U280 +The Alveo U280 is no longer supported by AMD Xilinx, thus Vivado 2023.1 is the last version to support it: + - Download the [Alveo U280 board files](https://www.xilinx.com/bin/public/openDownload?filename=au280_boardfiles_v1_2.zip) + - Extract the downloaded zip into \/data/xhub/boards/XilinxBoardStore/boards/Xilinx/ + - Restart Vivado + +### XDMA maximum BAR size +> The safe (and adopted) maximum BAR size is 32 MB (see [XBAR config](../ips/hpc/xlnx_xdma/config.tcl)) on the MSI Z590 PLUS (MS-7D11) motherboard, but it strictly depends on the motherboard. + +> **WARNING** If you use a greater BAR size your system BIOS could not be able to allocate the required space for the PCIe device, hence it cannot be able to boot properly and the entire system will crash. diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/INSTALL_CABLE_DRIVERS.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/INSTALL_CABLE_DRIVERS.md new file mode 100644 index 0000000000000000000000000000000000000000..3b40fb29a0ab9e95bac588a047594bff6274dd0b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/INSTALL_CABLE_DRIVERS.md @@ -0,0 +1,14 @@ +# Install Linux Cable Drivers +Installing Vivado on Linux by regular installer does not install device cable drivers, since it would require root access. Therefore, this step must be performed manually. + +## Digilent Devices +Refer to [this guide](https://digilent.com/reference/programmable-logic/guides/install-cable-drivers?srsltid=AfmBOooM1cKdqktUmDoPwlNzoN9zTsPGdju7_pBQfquQ5r9d5ZPqLZ8n) from Digilent and +[this guide](https://docs.amd.com/r/en-US/ug973-vivado-release-notes-install-license/Install-Cable-Drivers) from Xilinx. + +In general, each Linux Vivado installation comes with an installation script, to be run with sudo: +```console +cd /data/xicom/cable_drivers/lin64/install_script/install_drivers/ +sudo ./install_drivers +``` +> NOTE: for regualar Vivado installations, `` path can be retrieved from `XILINX_VIVADO` environment variable. + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/PROGRAM_LOADING.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/PROGRAM_LOADING.md new file mode 100644 index 0000000000000000000000000000000000000000..0873efba82ec8ced00467fe7ab08e9c76c7a322e --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/PROGRAM_LOADING.md @@ -0,0 +1,45 @@ +# Program Loading + +Once the target board is programmed with a valid bitstream, a program can be loaded into SoC memory using different methods, depending on the selected RISC-V CPU specified by `CORE_SELECTOR`. Example programs can be compiled and built in the `sw/SoC` directory using `make`. Externally compiled programs can also be used, but ensure they are built with the appropriate compilation flags for the selected CPU. + +We offer two loading options: +- **Binary Loading**: load the flat .bin file starting from a memory address +- **ELF Loading**: load the .elf file using sections + +For both flows, the default application loaded is `sw/SoC/examples/blinky` + +## Load an ELF file + +To load a .elf file, a backend that supports the target platform and CPU is required. Currently, we support two backends: +[OpenOCD](../../../sw/doc/OPENOCD_INSTALLATION.md) and XSDB (coming with Vivado). Both connect to port 3004 for all cores, except for `CORE_MICROBLAZEV_RV64`, which requires port 3005. +For loading, we primarily use the GDB debugger, though XSDB is also a viable option. + +If `CORE_SELECTOR` is set to `CORE_MICROBLAZEV_RV32`, `CORE_DUAL_MICROBLAZEV_RV32`, `CORE_MICROBLAZEV_RV64`, the .elf file can be loaded into memory and executed using: +``` bash +make xsdb_run +``` +Instead, if the `CORE_SELECTOR` is another one (e.g. `CORE_CV32E40P`) use openocd (be sure to have closed connections with Xilinx HW server before) +``` bash +make openocd_run +``` +Once the backend is enabled, load the .elf file using +``` bash +make gdb_run ELF_PATH= +``` + +## Load a binary file + +Since not all CPUs supported by `CORE_SELECTOR` have a backend or dedicated loading infrastructure (e.g. `CORE_PICORV32`), memory can also be programmed with a flat binary using _Xilinx jtag2axi_ or _Xilinx DMA_ IPs, both integrated into our `rtl/sys_master` component. This binary loading process is straightforward, as it directly writes bytes into memory. + +> NOTE: This loading flow writes a flat binary image, including zero-padding between memory sections. Therefore, during linking, you might need to keep an eye for this. + +``` bash +make load_binary BIN_PATH= BASE_ADDRESS= JTAG_READBACK= +``` +Once the binary is loaded, manually trigger a CPU reset with: +``` bash +make vio_resetn +``` +The VIO resetn controls the CPU reset instead of GDB, allowing the user to directly manage the core reset. +**Warning**: this option works only if `VIO_RESETN_DEFAULT = 0` in `configs//config_main_bus.csv` + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/UART_CONNECTION.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/UART_CONNECTION.md new file mode 100644 index 0000000000000000000000000000000000000000..7bb9412c119281d0d38f74624e1b5c0574ae4f99 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/UART_CONNECTION.md @@ -0,0 +1,16 @@ +# Uart Connection + +The UART peripheral is available in both `hpc` and `embedded` configurations. The `hpc` configuration virtualizes the serial protocol over PCIe, whereas the `embedded` configuration maps the `rx` and `tx` signals to physical output ports. Currently, only Nexys boards are supported for the `embedded` profile. This document outlines how to connect a UART transceiver to UninaSoC. + +By default, the UART `rx` and `tx` signals are mapped to PMOD port C, as defined in [`synth/constraints/Nexys-A7-*T-Master.xdc`](../synth/constraints). We use an [FDTI FT232R USB UART transceiver](https://ftdichip.com/wp-content/uploads/2020/08/DS_FT232R.pdf) to connect UninaSoC UART to an external terminal via a USB serial connection (see reference picture). + +Nexys to FTDI front | Nexys to FTDI back +:-------------------------:|:-------------------------: +![Nexys to FTDI Front](nexys_ftdi_front.jpeg) | ![Nexys to FTDI Back](nexys_ftdi_back.jpeg) + +Any compatible FTDI device can be used, provided the UART pins are correctly connected. +In the current implementation, the UART operates at a baud rate of 9600. For further details on the UART hardware configuration, refer to `hw/ips/embedded/xlnx_axi_uartlite/config.tcl`. + + + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/VIVADO_PATCHES.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/VIVADO_PATCHES.md new file mode 100644 index 0000000000000000000000000000000000000000..c155e06b8f8f918d7216587a02899d92ff9b3e82 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/doc/VIVADO_PATCHES.md @@ -0,0 +1,3 @@ +# Vivado Patches +This document lists useful patches for Vivado versions and verified OS (Ubuntu 22.04): +* Vivado 2022.2: [AR000035739](https://adaptivesupport.amd.com/s/article/000035739?language=en_US): Tactical patch - schematic viewer is not displaying cell names or port names with Ubuntu 22.04 diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_axi_from_mem/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_axi_from_mem/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_axi_from_mem/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_cv32e40p/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_cv32e40p/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_cv32e40p/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_cv64a6/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_cv64a6/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_cv64a6/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_ibex/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_ibex/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_ibex/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_picorv32/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_picorv32/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_picorv32/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv32_dbg_bscane/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv32_dbg_bscane/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv32_dbg_bscane/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv64_dbg_bscane/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv64_dbg_bscane/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv64_dbg_bscane/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv_plic/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv_plic/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/custom_rv_plic/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi4_to_axilite_d32_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi4_to_axilite_d32_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..cd1f6f47ff2509aac603f6c97952491114f295a1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi4_to_axilite_d32_converter/config.tcl @@ -0,0 +1,15 @@ +# Import IP by version +create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +# Configure IP +set_property -dict [list \ + CONFIG.MI_PROTOCOL {AXI4LITE} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.SI_PROTOCOL {AXI4} \ + CONFIG.TRANSLATION_MODE {2} \ + ] [get_ips $::env(IP_NAME)] + +# Currently this is only used in the PBUS, hence its size is fixed at 32 +set_property CONFIG.DATA_WIDTH 32 [get_ips $::env(IP_NAME)] +set_property CONFIG.ADDR_WIDTH 32 [get_ips $::env(IP_NAME)] +set_property CONFIG.ID_WIDTH $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_cdma/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_cdma/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..22edb44e162f96879b8bda56277f0aa7da02ad97 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_cdma/config.tcl @@ -0,0 +1,28 @@ +# Author: Michele Giugliano +# Description: Simple DMA Mode (C_INCLUDE_SG=0) for AXI CDMA IP + +# Import the IP core +create_ip -name axi_cdma -vendor xilinx.com -library ip -version 4.1 -module_name $::env(IP_NAME) + +# Main Parameters +set CDMA_SG_MODE 0 ;# 0 = Simple DMA +set CDMA_DATA_WIDTH 32 ;# 32-bit workaround (64-bit bug) +set CDMA_ADDR_WIDTH 32 +set CDMA_CLK_FREQ 100000000 + +# IP Core Configuration +set_property -dict [list \ + CONFIG.C_INCLUDE_SG $CDMA_SG_MODE \ + CONFIG.C_INCLUDE_DRE {1} \ + CONFIG.C_INCLUDE_SF {1} \ + CONFIG.C_USE_DATAMOVER_LITE {0} \ + CONFIG.C_ENABLE_KEYHOLE {0} \ + CONFIG.C_AXI_LITE_IS_ASYNC {0} \ + CONFIG.C_ADDR_WIDTH $CDMA_ADDR_WIDTH \ + CONFIG.C_M_AXI_DATA_WIDTH $CDMA_DATA_WIDTH \ + CONFIG.C_M_AXI_MAX_BURST_LEN {256} \ + CONFIG.C_READ_ADDR_PIPE_DEPTH {1} \ + CONFIG.C_WRITE_ADDR_PIPE_DEPTH {1} \ + CONFIG.M_AXI_ACLK.FREQ_HZ $CDMA_CLK_FREQ \ + CONFIG.S_AXI_LITE_ACLK.FREQ_HZ $CDMA_CLK_FREQ \ +] [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d32_clock_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d32_clock_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..80ad5985770463d4fb1af81f51351c6c9e1f6119 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d32_clock_converter/config.tcl @@ -0,0 +1,14 @@ +# Author: Manuel Maddaluno +# Description: AXI Clock Converter - Needed to do clock-domain crossing + +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.SYNCHRONIZATION_STAGES {8} \ +] [get_ips $::env(IP_NAME)] + +# Fixed to 32 bits +set_property CONFIG.DATA_WIDTH 32 [get_ips $::env(IP_NAME)] +set_property CONFIG.ADDR_WIDTH 32 [get_ips $::env(IP_NAME)] +set_property CONFIG.ID_WIDTH $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d512_clock_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d512_clock_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..940306b744032e9e7b6bf93f462911e1dc87bbd7 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d512_clock_converter/config.tcl @@ -0,0 +1,15 @@ +# Author: Manuel Maddaluno +# Description: AXI Clock Converter - Needed to do clock-domain crossing + +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.SYNCHRONIZATION_STAGES {8} \ +] [get_ips $::env(IP_NAME)] + +# Fixed to 512 bits +set_property CONFIG.DATA_WIDTH 512 [get_ips $::env(IP_NAME)] +set_property CONFIG.ADDR_WIDTH $::env(MBUS_ADDR_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.ID_WIDTH $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d64_clock_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d64_clock_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..8f4b044fc55c1dcb07b9d3a11b52e3e5c4e75050 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_d64_clock_converter/config.tcl @@ -0,0 +1,14 @@ +# Author: Manuel Maddaluno +# Description: AXI Clock Converter - Needed to do clock-domain crossing + +create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.ACLK_ASYNC {1} \ + CONFIG.SYNCHRONIZATION_STAGES {8} \ +] [get_ips $::env(IP_NAME)] + +# Fixed to 64 bits +set_property CONFIG.DATA_WIDTH 64 [get_ips $::env(IP_NAME)] +set_property CONFIG.ADDR_WIDTH 64 [get_ips $::env(IP_NAME)] +set_property CONFIG.ID_WIDTH $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_dwidth_32_to_64_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_dwidth_32_to_64_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..2f812eef8730fe148c57857890a96cb8090c89c4 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_dwidth_32_to_64_converter/config.tcl @@ -0,0 +1,10 @@ +# Author: Manuel Maddaluno +# Description: AXI Data Width Converter - Needed to link the XDMA (minimum 64 bits) to the AXI crossbar (32 bits) + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.MI_DATA_WIDTH {64} \ + CONFIG.SI_DATA_WIDTH {32} \ + CONFIG.SI_ID_WIDTH $::env(MBUS_ID_WIDTH) \ +] [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_dwidth_64_to_32_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_dwidth_64_to_32_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..a33de1a0f79033fdd9f5631254c9e0112ee362a8 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axi_dwidth_64_to_32_converter/config.tcl @@ -0,0 +1,10 @@ +# Author: Manuel Maddaluno +# Description: AXI Data Width Converter - Needed to link the XDMA (minimum 64 bits) to the AXI crossbar (32 bits) + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.MI_DATA_WIDTH {32} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.SI_ID_WIDTH {4} \ +] [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axilite_timer/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axilite_timer/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c1d96d117af8312c1bc1b93511702482479d8081 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axilite_timer/config.tcl @@ -0,0 +1,14 @@ +# Import IP +create_ip -name axi_timer -vendor xilinx.com -library ip -version 2.0 -module_name $::env(IP_NAME) +# Configure IP +set_property -dict [list \ + CONFIG.COUNT_WIDTH {32} \ + CONFIG.GEN0_ASSERT {Active_High} \ + CONFIG.GEN1_ASSERT {Active_High} \ + CONFIG.TRIG0_ASSERT {Active_High} \ + CONFIG.TRIG1_ASSERT {Active_High} \ + CONFIG.enable_timer2 {1} \ + CONFIG.mode_64bit {0} \ + ] [get_ips $::env(IP_NAME)] + +# Note: ADDR_WIDTH is fixed at 5 bits, DATA_WIDTH is fixed at 32 diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axilite_to_axi4_d32_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axilite_to_axi4_d32_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..10891534955a24f82428acfce94f1af04bd19ba2 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_axilite_to_axi4_d32_converter/config.tcl @@ -0,0 +1,15 @@ +# Import IP by version +create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +# Configure IP +set_property -dict [list CONFIG.MI_PROTOCOL {AXI4} \ + CONFIG.READ_WRITE_MODE {READ_WRITE} \ + CONFIG.SI_PROTOCOL {AXI4LITE} \ + CONFIG.TRANSLATION_MODE {2} \ + ] [get_ips $::env(IP_NAME)] + +# Currently it is only used for the microblaze-V, that is only allowed as a 32-bits master +set_property CONFIG.DATA_WIDTH 32 [get_ips $::env(IP_NAME)] +set_property CONFIG.ADDR_WIDTH 32 [get_ips $::env(IP_NAME)] +set_property CONFIG.ID_WIDTH $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..0bc6293973e9a0681b359af3dd240dcbc9b2f6a1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/config.tcl @@ -0,0 +1,43 @@ +# Import IP +create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name $::env(IP_NAME) + +# COE file to pre-load in BRAM +# The bootrom default value is currently a (non-compressed) nop-slide ending with a WFI. +# TODO: implementation of a proper bootrom is deferred to issue #36 +set coe_file $::env(IP_DIR)/initRV$::env(MBUS_DATA_WIDTH).coe + +puts "$coe_file" + +# Set the bram depth +# WARNING: Do not change the following line, it is modified by config-based script +set bram_depth {16384} + +# Use envvars out of list +set_property CONFIG.Write_Width_A $::env(MBUS_DATA_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.Read_Width_A $::env(MBUS_DATA_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.Write_Width_B $::env(MBUS_DATA_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.Read_Width_B $::env(MBUS_DATA_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.AXI_ID_Width $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] + +# Configure IP +set_property -dict [list CONFIG.Interface_Type {AXI4} \ + CONFIG.AXI_Slave_Type {Memory_Slave} \ + CONFIG.Use_AXI_ID {true} \ + CONFIG.Use_Byte_Write_Enable {TRUE} \ + CONFIG.Memory_Type {Simple_Dual_Port_RAM} \ + CONFIG.Byte_Size {8} \ + CONFIG.Assume_Synchronous_Clk {true} \ + CONFIG.Operating_Mode_A {READ_FIRST} \ + CONFIG.Operating_Mode_B {READ_FIRST} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.Reset_Type {ASYNC} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.EN_SAFETY_CKT {true} \ + CONFIG.Load_Init_File {true} \ + CONFIG.Coe_File $coe_file \ + CONFIG.Fill_Remaining_Memory_Locations {true} \ + CONFIG.Write_Depth_A $bram_depth \ + ] [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/initRV32.coe b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/initRV32.coe new file mode 100644 index 0000000000000000000000000000000000000000..111202d34b7b9c376ec5157983beeffafccf9343 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/initRV32.coe @@ -0,0 +1,6 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +00000013, +00000013, +00000013, +10500073; \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/initRV64.coe b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/initRV64.coe new file mode 100644 index 0000000000000000000000000000000000000000..ad78d02a8c51efad27f87800a9c07eed3de09e7e --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_blk_mem_gen_0/initRV64.coe @@ -0,0 +1,10 @@ +memory_initialization_radix = 16; +memory_initialization_vector = +0000001300000013, +0000001300000013, +0000001300000013, +0000001300000013, +0000001300000013, +0000001300000013, +0000001300000013, +0000006f00000013; \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_dual_microblaze_debug_module_v/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_dual_microblaze_debug_module_v/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..108d90db67c4f5670459c4e7d179c225ee6af8ac --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_dual_microblaze_debug_module_v/config.tcl @@ -0,0 +1,11 @@ +# Import IP by version +create_ip -name mdm_riscv -vendor xilinx.com -library ip -version 1.0 -module_name $::env(IP_NAME) + +# Configure IP +set_property -dict [list CONFIG.C_DBG_MEM_ACCESS {0} \ + CONFIG.C_DBG_REG_ACCESS {0} \ + CONFIG.C_JTAG_CHAIN {2} \ + CONFIG.C_MB_DBG_PORTS {2} \ + CONFIG.C_USE_BSCAN {0} \ + CONFIG.C_USE_UART {0} + ] [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblaze_debug_module_v/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblaze_debug_module_v/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..448e1f5ee7513e93acc74b4579d9210b5236f6f0 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblaze_debug_module_v/config.tcl @@ -0,0 +1,11 @@ +# Import IP by version +create_ip -name mdm_riscv -vendor xilinx.com -library ip -version 1.0 -module_name $::env(IP_NAME) + +# Configure IP +set_property -dict [list CONFIG.C_DBG_MEM_ACCESS {0} \ + CONFIG.C_DBG_REG_ACCESS {0} \ + CONFIG.C_JTAG_CHAIN {2} \ + CONFIG.C_MB_DBG_PORTS {1} \ + CONFIG.C_USE_BSCAN {0} \ + CONFIG.C_USE_UART {0} + ] [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblazev_rv32/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblazev_rv32/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..4e67ab2c7ceb9c41bdc22c597184c02cf34e8a62 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblazev_rv32/config.tcl @@ -0,0 +1,93 @@ +# Import IP by version +create_ip -name microblaze_riscv -vendor xilinx.com -library ip -version 1.0 -module_name $::env(IP_NAME) + + +# Configure IP + +# Set configuration preset (1: Microcontroller, 2: Real-time, 4: RVIMC, 5: RVIMAC, 6: RVIMAFC) +# NOTE: Set this first, since it overrides other configs +set_property CONFIG.G_TEMPLATE_LIST {1} [get_ips $::env(IP_NAME)] + +############## +# Interfaces # +############## +# - Enable debug for MDMV (PG428) +# - Disable trace +# - Disable discrete +# - Enable only AXI memory +# - AXI-full data port +# - AXI-lite instruction port (no AXI-full support) +# - Disable all other instruction/memory interfaces (ILMB/DLMB: local memory bus, IC/DC: Cache interfaces) +# - Disable AXI stream +# - Changing C_HARTID is actually ineffective +set_property -dict [list \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_HARTID {0} \ + CONFIG.C_ENABLE_DISCRETE_PORTS {0} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_I_AXI {1} \ + CONFIG.C_USE_DCACHE {0} \ + CONFIG.C_USE_ICACHE {0} \ + CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_DP_EXCLUSIVE_ACCESS {1} \ + CONFIG.C_D_LMB {0} \ + CONFIG.C_I_LMB {0} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_COUNTERS {1} \ + CONFIG.C_ILL_INSTR_EXCEPTION {2} \ + CONFIG.C_USE_INTERRUPT {1} \ + ] [get_ips $::env(IP_NAME)] + +# More unset properties for future reference +# set_property -dict [list \ +# CONFIG.C_DEBUG_EVENT_COUNTERS {0} \ +# CONFIG.C_DEBUG_LATENCY_COUNTERS {0} \ +# CONFIG.C_FAULT_TOLERANT {0} \ +# CONFIG.C_FSL_LINKS {0} \ +# CONFIG.C_LOCKSTEP_SELECT {0} \ +# CONFIG.C_NUMBER_OF_PC_BRK {1} \ +# CONFIG.C_NUMBER_OF_RD_ADDR_BRK {0} \ +# CONFIG.C_NUMBER_OF_WR_ADDR_BRK {0} \ +# CONFIG.C_TRACE {0} \ +# CONFIG.C_USE_BRANCH_TARGET_CACHE {0} \ +# CONFIG.C_INTERCONNECT {2} \ +# ] [get_ips $::env(IP_NAME)] + +############################### +# AXI interconnect parameters # +############################### +# Data width +set_property CONFIG.C_DATA_SIZE 32 [get_ips $::env(IP_NAME)] +# Address width +# - If RV32, address width is fixed equal to data width +# - If RV64, supported: 32, 36, 40, 44, 48, 52, 56, 64 +set_property CONFIG.C_ADDR_SIZE 32 [get_ips $::env(IP_NAME)] +# AXI ID width is fixed to 1 + +########## +# RISC-V # +########## +# C-ext +set_property CONFIG.C_USE_COMPRESSION {1} [get_ips $::env(IP_NAME)] +# A-ext +set_property CONFIG.C_USE_ATOMIC {1} [get_ips $::env(IP_NAME)] +# M-ext (1: STANDARD; 2: OPTIMIZED) +set_property CONFIG.C_USE_MULDIV {1} [get_ips $::env(IP_NAME)] +# F/D-ext (0: none; 1: F; 2: D) +# - F only if RV32 (C_DATA_SIZE = 32) +# - D only if RV64 (C_DATA_SIZE = 64) +set_property CONFIG.C_USE_FPU {0} [get_ips $::env(IP_NAME)] +# Bit-manipulation (Zba, Zbb, Zbc, Zbs) +set_property CONFIG.C_USE_BITMAN_A {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_USE_BITMAN_B {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_USE_BITMAN_C {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_USE_BITMAN_S {0} [get_ips $::env(IP_NAME)] +# PMP entries and granularity +set_property CONFIG.C_PMP_ENTRIES {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_PMP_GRANULARITY {2} [get_ips $::env(IP_NAME)] +# Enable User mode (no Supervisor for now) +set_property CONFIG.C_USE_MMU {0} [get_ips $::env(IP_NAME)] +# set_property CONFIG.C_MMU_PRIVILEGED_INSTR {0} [get_ips $::env(IP_NAME)] +# Illegal instruction exception (1:BASIC, 2: COMPLETE) +set_property CONFIG.C_ILL_INSTR_EXCEPTION {2} [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblazev_rv64/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblazev_rv64/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..621585b06e014e3b5c5293fbf2b2ac4e219c4c8a --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_microblazev_rv64/config.tcl @@ -0,0 +1,93 @@ +# Import IP by version +create_ip -name microblaze_riscv -vendor xilinx.com -library ip -version 1.0 -module_name $::env(IP_NAME) + + +# Configure IP + +# Set configuration preset (1: Microcontroller, 2: Real-time, 4: RVIMC, 5: RVIMAC, 6: RVIMAFC) +# NOTE: Set this first, since it overrides other configs +set_property CONFIG.G_TEMPLATE_LIST {1} [get_ips $::env(IP_NAME)] + +############## +# Interfaces # +############## +# - Enable debug for MDMV (PG428) +# - Disable trace +# - Disable discrete +# - Enable only AXI memory +# - AXI-full data port +# - AXI-lite instruction port (no AXI-full support) +# - Disable all other instruction/memory interfaces (ILMB/DLMB: local memory bus, IC/DC: Cache interfaces) +# - Disable AXI stream +# - Changing C_HARTID is actually ineffective +set_property -dict [list \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_HARTID {0} \ + CONFIG.C_ENABLE_DISCRETE_PORTS {0} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_I_AXI {1} \ + CONFIG.C_USE_DCACHE {0} \ + CONFIG.C_USE_ICACHE {0} \ + CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_DP_EXCLUSIVE_ACCESS {1} \ + CONFIG.C_D_LMB {0} \ + CONFIG.C_I_LMB {0} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_COUNTERS {1} \ + CONFIG.C_ILL_INSTR_EXCEPTION {2} \ + CONFIG.C_USE_INTERRUPT {1} \ + ] [get_ips $::env(IP_NAME)] + +# More unset properties for future reference +# set_property -dict [list \ +# CONFIG.C_DEBUG_EVENT_COUNTERS {0} \ +# CONFIG.C_DEBUG_LATENCY_COUNTERS {0} \ +# CONFIG.C_FAULT_TOLERANT {0} \ +# CONFIG.C_FSL_LINKS {0} \ +# CONFIG.C_LOCKSTEP_SELECT {0} \ +# CONFIG.C_NUMBER_OF_PC_BRK {1} \ +# CONFIG.C_NUMBER_OF_RD_ADDR_BRK {0} \ +# CONFIG.C_NUMBER_OF_WR_ADDR_BRK {0} \ +# CONFIG.C_TRACE {0} \ +# CONFIG.C_USE_BRANCH_TARGET_CACHE {0} \ +# CONFIG.C_INTERCONNECT {2} \ +# ] [get_ips $::env(IP_NAME)] + +############################### +# AXI interconnect parameters # +############################### +# Data width +set_property CONFIG.C_DATA_SIZE 64 [get_ips $::env(IP_NAME)] +# Address width +# - If RV32, address width is fixed equal to data width +# - If RV64, supported: 32, 36, 40, 44, 48, 52, 56, 64 +set_property CONFIG.C_ADDR_SIZE $::env(MBUS_ADDR_WIDTH) [get_ips $::env(IP_NAME)] +# AXI ID width is fixed to 1 + +########## +# RISC-V # +########## +# C-ext +set_property CONFIG.C_USE_COMPRESSION {1} [get_ips $::env(IP_NAME)] +# A-ext +set_property CONFIG.C_USE_ATOMIC {1} [get_ips $::env(IP_NAME)] +# M-ext (1: STANDARD; 2: OPTIMIZED) +set_property CONFIG.C_USE_MULDIV {1} [get_ips $::env(IP_NAME)] +# F/D-ext (0: none; 1: F; 2: D) +# - F only if RV32 (C_DATA_SIZE = 32) +# - D only if RV64 (C_DATA_SIZE = 64) +set_property CONFIG.C_USE_FPU {0} [get_ips $::env(IP_NAME)] +# Bit-manipulation (Zba, Zbb, Zbc, Zbs) +set_property CONFIG.C_USE_BITMAN_A {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_USE_BITMAN_B {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_USE_BITMAN_C {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_USE_BITMAN_S {0} [get_ips $::env(IP_NAME)] +# PMP entries and granularity +set_property CONFIG.C_PMP_ENTRIES {0} [get_ips $::env(IP_NAME)] +set_property CONFIG.C_PMP_GRANULARITY {2} [get_ips $::env(IP_NAME)] +# Enable User mode (no Supervisor for now) +set_property CONFIG.C_USE_MMU {0} [get_ips $::env(IP_NAME)] +# set_property CONFIG.C_MMU_PRIVILEGED_INSTR {0} [get_ips $::env(IP_NAME)] +# Illegal instruction exception (1:BASIC, 2: COMPLETE) +set_property CONFIG.C_ILL_INSTR_EXCEPTION {2} [get_ips $::env(IP_NAME)] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_peripheral_crossbar/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_peripheral_crossbar/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..ce1b0ffcc182fadd16484d136c8df6c26a152449 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_peripheral_crossbar/.gitignore @@ -0,0 +1,2 @@ +# Ingore this file as it is generated by the config flow +config.tcl \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_vio/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_vio/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..753333782dfa749ce46c55f3e30369801353cd22 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/common/xlnx_vio/config.tcl @@ -0,0 +1,14 @@ +# Import IP by version +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $::env(IP_NAME) + +# Configure IP +set_property -dict [list CONFIG.C_NUM_PROBE_OUT {2} \ + CONFIG.C_PROBE_OUT0_WIDTH {1} \ + CONFIG.C_PROBE_OUT1_WIDTH {1} \ + CONFIG.C_PROBE_OUT1_INIT_VAL {0x0} \ + CONFIG.C_NUM_PROBE_IN {1} \ + CONFIG.C_PROBE_IN0_WIDTH {1} \ + ] [get_ips $::env(IP_NAME)] + +# Setup VIO_reset value (mapped on probe 0) +set_property CONFIG.C_PROBE_OUT0_INIT_VAL $::env(VIO_RESETN_DEFAULT) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/custom_hls_conv_hbus/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/custom_hls_conv_hbus/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..6dcc78333793047f17ba947643201881e6458a69 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/custom_hls_conv_hbus/config.tcl @@ -0,0 +1,34 @@ +# Author: Stefano Mercogliano +# Description: create a custom IP using rtl sources + +# Define the top_module name (NB: IP Name must be different from the top_module name) +set top_module custom_top_wrapper + +# Define directories +set dir_name $::env(HW_UNITS_ROOT)/$::env(IP_NAME) +set rtl_dir_name ${dir_name}/rtl +set unina_soc_dir $::env(XILINX_ROOT)/rtl + +# Define paths for the uninasoc files (and wrapper file) +set mem_macro_path ${unina_soc_dir}/uninasoc_mem.svh +set axi_macro_path ${unina_soc_dir}/uninasoc_axi.svh +set pkg_path ${unina_soc_dir}/uninasoc_pkg.sv +set top_module_path ${dir_name}/${top_module}.sv + +# Append svh files and top module +set src_file_list {} +lappend src_file_list ${mem_macro_path} +lappend src_file_list ${axi_macro_path} +lappend src_file_list ${pkg_path} +lappend src_file_list ${top_module_path} + +# Read file names from RTL dir into src file list +set ls_list [exec ls ${rtl_dir_name}] + +foreach item $ls_list { + lappend src_file_list ${rtl_dir_name}/$item +} + +# Package the IP with the specified file list and top module +source $::env(XILINX_SYNTH_TCL_ROOT)/package_ip.tcl + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_axi_dwidth_from512_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_axi_dwidth_from512_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..139db160ff70bb8d3856fb9d717fb446b3d4cd2a --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_axi_dwidth_from512_converter/config.tcl @@ -0,0 +1,12 @@ +# Author: Manuel Maddaluno +# Description: AXI Data Width Converter - Needed to link the AXI crossbar (in general the entire SoC 32 bits) to the DDR MIG (512 bit) + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.SI_DATA_WIDTH {512} \ +] [get_ips $::env(IP_NAME)] + +# Use envvars out of list +set_property CONFIG.SI_ID_WIDTH $::env(HBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.MI_DATA_WIDTH $::env(MBUS_DATA_WIDTH) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_axi_dwidth_to512_converter/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_axi_dwidth_to512_converter/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..60bc4aec90486eec140813815c8409ff15f5b7fb --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_axi_dwidth_to512_converter/config.tcl @@ -0,0 +1,12 @@ +# Author: Manuel Maddaluno +# Description: AXI Data Width Converter - Needed to link the AXI crossbar (in general the entire SoC 32 bits) to the DDR MIG (512 bit) + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.MI_DATA_WIDTH {512} \ +] [get_ips $::env(IP_NAME)] + +# Use envvars out of list +set_property CONFIG.SI_DATA_WIDTH $::env(MBUS_DATA_WIDTH) [get_ips $::env(IP_NAME)] +set_property CONFIG.SI_ID_WIDTH $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_clk_wiz_hpc/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_clk_wiz_hpc/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1c5271f515cc60884a73869c91ec4e94b7fc9424 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_clk_wiz_hpc/config.tcl @@ -0,0 +1,49 @@ +# Author: Manuel Maddaluno +# Description: HPC clock wizard. It takes the XDMA axi_aclk (250 MHz) and generates 5 clocks: +# - clk_10 @ 10MHz +# - clk_20 @ 20MHz +# - clk_50 @ 50MHz +# - clk_100 @ 100MHz +# - clk_250 @ 250MHz + +create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.CLKIN1_JITTER_PS {40.0} \ + CONFIG.CLKOUT1_JITTER {169.738} \ + CONFIG.CLKOUT1_PHASE_ERROR {85.928} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {10.000} \ + CONFIG.CLKOUT2_JITTER {148.005} \ + CONFIG.CLKOUT2_PHASE_ERROR {85.928} \ + CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {20.000} \ + CONFIG.CLKOUT2_USED {true} \ + CONFIG.CLKOUT3_JITTER {123.073} \ + CONFIG.CLKOUT3_PHASE_ERROR {85.928} \ + CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {50.000} \ + CONFIG.CLKOUT3_USED {true} \ + CONFIG.CLKOUT4_JITTER {107.111} \ + CONFIG.CLKOUT4_PHASE_ERROR {85.928} \ + CONFIG.CLKOUT4_USED {true} \ + CONFIG.CLKOUT5_JITTER {89.528} \ + CONFIG.CLKOUT5_PHASE_ERROR {85.928} \ + CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {250.000} \ + CONFIG.CLKOUT5_USED {true} \ + CONFIG.CLK_OUT1_PORT {clk_10} \ + CONFIG.CLK_OUT2_PORT {clk_20} \ + CONFIG.CLK_OUT3_PORT {clk_50} \ + CONFIG.CLK_OUT4_PORT {clk_100} \ + CONFIG.CLK_OUT5_PORT {clk_250} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \ + CONFIG.MMCM_CLKIN1_PERIOD {4.000} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {100.000} \ + CONFIG.MMCM_CLKOUT1_DIVIDE {50} \ + CONFIG.MMCM_CLKOUT2_DIVIDE {20} \ + CONFIG.MMCM_CLKOUT3_DIVIDE {10} \ + CONFIG.MMCM_CLKOUT4_DIVIDE {4} \ + CONFIG.MMCM_DIVCLK_DIVIDE {1} \ + CONFIG.NUM_OUT_CLKS {5} \ + CONFIG.PRIM_IN_FREQ {250.000} \ + CONFIG.RESET_PORT {resetn} \ + CONFIG.RESET_TYPE {ACTIVE_LOW} \ +] [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_ddr4/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_ddr4/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..29227b5fd66e9c483da876a5f328d81b5cf43d4c --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_ddr4/config.tcl @@ -0,0 +1,22 @@ +# Author: Manuel Maddaluno +# Description: DDR4 SDRAM (MIG) IP configuration file + +create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.System_Clock {Differential} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_AxiAddressWidth {34} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_Ecc {true} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_TimePeriod {833} \ +] [get_ips $::env(IP_NAME)] + +# Use envvars out of list +set_property CONFIG.C0.DDR4_AxiIDWidth $::env(MBUS_ID_WIDTH) [get_ips $::env(IP_NAME)] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_highperformance_crossbar/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_highperformance_crossbar/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..ce1b0ffcc182fadd16484d136c8df6c26a152449 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_highperformance_crossbar/.gitignore @@ -0,0 +1,2 @@ +# Ingore this file as it is generated by the config flow +config.tcl \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_system_cache_0/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_system_cache_0/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..9b917acb56df4bab7f2e12c0065027246c0297a4 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_system_cache_0/config.tcl @@ -0,0 +1,84 @@ +# Author: Valerio Di Domenico +# Description: AXI System Cache for DRAM channels. This IP also introduces support for AXI atomic operations +create_ip -name system_cache -vendor xilinx.com -library ip -version 5.0 -module_name $::env(IP_NAME) + +############## +# Interfaces # +############## +# - Enable AXI memory interface (S0 generic port, S0_AXI_GEN_*) +# - Data width: $::env(MBUS_DATA_WIDTH) +# - ID width: $::env(MBUS_ID_WIDTH) +# - Address width: $::env(MBUS_ADDR_WIDTH) +# - Enable AXI master interface (C_M0_AXI_*) +# - Data width: 512 bit (keep same as DDR for now) +# - Thread ID width: $::env(MBUS_ID_WIDTH) +# - Address width: $::env(MBUS_ADDR_WIDTH) +# - Exclusive access support enabled (C_ENABLE_EXCLUSIVE = 1) +# - Base address: Absolute address of start of cachable range +# - High address: Absolute address of end of cachable range +# - Cache line length: 32 bytes, constant for now +# - CCIX0 cache line size: 128 bytes, constant for now +# - Other optional interfaces (ACE, CHI, CCIX, snoop, coherency, etc.) disabled + +# Set the cache BASEADDR and HIGHADDR +# WARNING: Do not change the following line, it is modified by config-based script +set CACHE_BASEADDR {0x50000} +set CACHE_HIGHADDR {0x5ffff} + +set_property -dict [list \ + CONFIG.C_CACHE_LINE_LENGTH {32} \ + CONFIG.C_FREQ {250} \ + CONFIG.C_CACHE_SIZE {32768} \ + CONFIG.C_M0_AXI_DATA_WIDTH {512} \ + CONFIG.C_S0_AXI_GEN_DATA_WIDTH $::env(MBUS_DATA_WIDTH) \ + CONFIG.C_NUM_OPTIMIZED_PORTS {0} \ + CONFIG.C_NUM_GENERIC_PORTS {1} \ + CONFIG.C_S0_AXI_GEN_ID_WIDTH $::env(MBUS_ID_WIDTH) \ + CONFIG.C_S0_AXI_GEN_ADDR_WIDTH $::env(MBUS_ADDR_WIDTH) \ + CONFIG.C_BASEADDR $CACHE_BASEADDR \ + CONFIG.C_HIGHADDR $CACHE_HIGHADDR \ + CONFIG.C_ENABLE_EXCLUSIVE {1} \ + CONFIG.C_CCIX0_CACHE_LINE_SIZE {128} \ + CONFIG.C_M0_AXI_THREAD_ID_WIDTH $::env(MBUS_ID_WIDTH) \ + CONFIG.C_M0_AXI_ADDR_WIDTH $::env(MBUS_ADDR_WIDTH) \ + CONFIG.C_ENABLE_COHERENCY {0} \ + CONFIG.C_ENABLE_SLAVE_COHERENCY {0} \ + CONFIG.C_ENABLE_MASTER_COHERENCY {0} \ + CONFIG.C_ENABLE_ACE_PROTOCOL {0} \ + CONFIG.C_ENABLE_CCIX_PROTOCOL {0} \ + CONFIG.C_ENABLE_CHI_PROTOCOL {0} \ + CONFIG.C_ENABLE_INTEGRITY {0} \ + CONFIG.C_ENABLE_NON_SECURE {0} \ + CONFIG.C_ENABLE_ERROR_HANDLING {0} \ + CONFIG.C_ENABLE_CTRL {0} \ + CONFIG.C_ENABLE_STATISTICS {0} \ + CONFIG.C_ENABLE_VERSION_REGISTER {0} \ + CONFIG.C_ENABLE_INTERRUPT {0} \ + CONFIG.C_ENABLE_ADDRESS_TRANSLATION {0} \ + CONFIG.C_NUM_WAYS {2} \ + CONFIG.C_NUM_SLAVE_TRANSACTIONS {16} \ + CONFIG.C_NUM_MASTER_TRANSACTIONS {32} \ + CONFIG.C_NUM_SNOOP_TRANSACTIONS {16} \ + CONFIG.C_NUM_OOO_CHANNELS {0} \ + CONFIG.C_CACHE_DATA_WIDTH {512} \ + CONFIG.C_CACHE_TAG_MEMORY_TYPE {0} \ + CONFIG.C_CACHE_DATA_MEMORY_TYPE {0} \ + CONFIG.C_CACHE_LRU_MEMORY_TYPE {0} \ + CONFIG.C_Lx_CACHE_LINE_LENGTH {4} \ + CONFIG.C_Lx_CACHE_SIZE {8192} \ + CONFIG.C_SUPPORT_SNOOP_FILTER {0} \ + CONFIG.C_SNOOP_KEEP_READ_ONCE {1} \ + CONFIG.C_SNOOP_KEEP_READ_SHARED {0} \ + CONFIG.C_SNOOP_KEEP_READ_CLEAN {0} \ + CONFIG.C_SNOOP_KEEP_READ_NSD {0} \ + CONFIG.C_SNOOP_KEEP_CLEAN_SHARED {0} \ + CONFIG.C_SNOOP_KEEP_SNPTOSC {0} \ + CONFIG.C_SNOOP_PASS_READ_ONCE {0} \ + CONFIG.C_SNOOP_PASS_READ_SHARED {0} \ + CONFIG.C_SNOOP_PASS_READ_CLEAN {0} \ + CONFIG.C_SNOOP_PASS_READ_NSD {0} \ + CONFIG.C_DEFAULT_DOMAIN {0} \ +] [get_ips $::env(IP_NAME)] + +# TODO152: This does not exist for Vivado 2023.1 and au280. Make this version/board dependent. +# CONFIG.C_ENABLE_FAST_INIT_SIM {0} diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_xdma/config.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_xdma/config.tcl new file mode 100644 index 0000000000000000000000000000000000000000..cc74d481c3bde3445658c29cf5a37cddbd1555de --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/ips/hpc/xlnx_xdma/config.tcl @@ -0,0 +1,23 @@ +# Author: Manuel Maddaluno +# Description: XDMA configuration file +create_ip -name xdma -vendor xilinx.com -library ip -version 4.1 -module_name $::env(IP_NAME) + +set_property -dict [list \ + CONFIG.PCIE_BOARD_INTERFACE {Custom} \ + CONFIG.SYS_RST_N_BOARD_INTERFACE {Custom} \ + CONFIG.functional_mode {AXI_Bridge} \ + CONFIG.en_axi_slave_if {false} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {32} \ + CONFIG.axisten_freq {250} \ + CONFIG.axi_data_width {64_bit} \ + CONFIG.en_gt_selection {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.pl_link_cap_max_link_speed {2.5_GT/s} \ + CONFIG.pl_link_cap_max_link_width {X8} \ + CONFIG.ref_clk_freq {100_MHz} \ + CONFIG.pciebar2axibar_0 {0x000000000000000} \ +] [get_ips $::env(IP_NAME)] + +# NOTE: The safe (and adopted) maximum BAR size is 32 MB on the MSI Z590 PLUS (MS-7D11) motherboard, +# but it strictly depends on the motherboard. \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/build.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/build.mk new file mode 100644 index 0000000000000000000000000000000000000000..2f5a90e455dc4bbea14ad7ad36f81f449c7082cb --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/build.mk @@ -0,0 +1,39 @@ +# Author: Vincenzo Maisto +# Author: Stefano Mercogliano +# Description: Make target to build Xilinx IPs and bitstream + +# Build bitstream from scratch +bitstream: ips + mkdir -p ${XILINX_PROJECT_REPORTS_DIR} + cd ${XILINX_PROJECT_BUILD_DIR}; \ + ${XILINX_VIVADO} -source ${XILINX_SYNTH_TCL_ROOT}/build_bitstream.tcl + +# Generate ips +IP_NAMES ?= $(addprefix ips/, $(addsuffix .xci, ${IP_LIST})) +ips: ${IP_NAMES} + +# Common recipe for building IPs +define build_ip + mkdir -p ${IP_DIR}/build; \ + cd ${IP_DIR}/build; \ + export IP_DIR=${IP_DIR}; \ + export IP_NAME=$(patsubst ips/%.xci,%,$@); \ + export IP_PRJ_NAME=$${IP_NAME}_prj; \ + ${XILINX_VIVADO} \ + -source ${XILINX_IPS_ROOT}/common/tcl/pre_config.tcl \ + -source ${IP_DIR}/config.tcl \ + -source ${XILINX_IPS_ROOT}/common/tcl/post_config.tcl + touch $@ +endef + +# For Xilinx IPs +ips/xlnx_%.xci: IP_DIR=$(firstword $(shell find ${XILINX_IPS_ROOT} -name 'xlnx_$*')) +ips/xlnx_%.xci: ${XILINX_IPS_ROOT}/*/xlnx_%/config.tcl +# Call common recepie + $(build_ip) + +# For custom IPs, also depend on RTL wrapper +ips/custom_%.xci: IP_DIR=$(firstword $(shell find ${XILINX_IPS_ROOT} -name 'custom_$*')) +ips/custom_%.xci: ${XILINX_IPS_ROOT}/*/custom_%/config.tcl ${HW_UNITS_ROOT}/custom_%/custom_top_wrapper.sv +# Call common recepie + $(build_ip) diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/config.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/config.mk new file mode 100644 index 0000000000000000000000000000000000000000..5877a768927aa1429c2838fa2e72bb323e87b84d --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/config.mk @@ -0,0 +1,39 @@ +# Author: Vincenzo Maisto +# Author: Stefano Mercogliano +# Description: +# Hold all the configurable variables. +# This file is meant to be updated by the configuration flow. + +########## +# Values # +########## + +# System +XLEN ?= 32 +PHYSICAL_ADDR_WIDTH ?= 32 + +# MBUS +MBUS_NUM_SI ?= 5 +MBUS_NUM_MI ?= 5 +MBUS_ADDR_WIDTH ?= ${PHYSICAL_ADDR_WIDTH} +MBUS_DATA_WIDTH ?= ${XLEN} +MBUS_ID_WIDTH ?= 4 + +# PBUS +PBUS_NUM_MI ?= 5 +PBUS_ID_WIDTH ?= 4 + +# HBUS +HBUS_NUM_MI ?= 0 +HBUS_NUM_SI ?= 0 +HBUS_ID_WIDTH ?= 0 + +# RV core +CORE_SELECTOR ?= CORE_CV32E40P + +# VIO resetn +VIO_RESETN_DEFAULT ?= 1 + +# Clock domains +MAIN_CLOCK_FREQ_MHZ ?= 20 +RANGE_CLOCK_DOMAINS ?= MAIN_CLOCK_DOMAIN PBUS_HAS_CLOCK_DOMAIN \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/environment.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/environment.mk new file mode 100644 index 0000000000000000000000000000000000000000..a00670d4d1700bce9e3fbe4cfdc6b50550bc0aa1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/environment.mk @@ -0,0 +1,120 @@ +# Author: Vincenzo Maisto +# Author: Stefano Mercogliano +# Author: Manuel Maddaluno +# Description: +# Hold all the environment variables for Xilinx tools and PCIe offsets. + +# Basic variables for Vivado +XILINX_VIVADO_CMD ?= vivado +XILINX_VIVADO_MODE ?= batch +# Build directory +XILINX_PROJECT_BUILD_DIR ?= ${XILINX_ROOT}/build +# Vivado's compilation reports directory +XILINX_PROJECT_REPORTS_DIR ?= ${XILINX_PROJECT_BUILD_DIR}/reports +# Hardware server +XILINX_HW_SERVER ?= hw_server + +############## +# Vivado IPs # +############## + +# List of IP basenames to build and import in the design +# $(1): The directory path in which to search for subdirectories +define find_ip_dirs +$(shell find $(1) -maxdepth 1 -type d -regextype posix-extended -regex ".*/(xlnx_.*|custom_.*)" -exec basename {} \;) +endef +# Parsing from directory ips/ matching paths (common|hpc|embedded) and prefix (xlnx_*|custom_*) +# List of the Xilinx IPs +COMMON_IP_LIST = $(call find_ip_dirs, ${XILINX_IPS_ROOT}/common ) +HPC_IP_LIST = $(call find_ip_dirs, ${XILINX_IPS_ROOT}/hpc ) +EMBEDDED_IP_LIST = $(call find_ip_dirs, ${XILINX_IPS_ROOT}/embedded) + +# Concatenate/create the full IP lists +# Profile-independent IP lists +IP_LIST = ${COMMON_IP_LIST} +# Selecting profile: HPC or EMBEDDED +ifeq (${SOC_CONFIG}, hpc) +# Append HPC IPs + IP_LIST += ${HPC_IP_LIST} +else ifeq (${SOC_CONFIG}, embedded) +# Append embedded IPs + IP_LIST += ${EMBEDDED_IP_LIST} +else +$(error "Unsupported config ${SOC_CONFIG}") +endif + +# Remove Microblaze-V and Microblaze Debug Module V when building with Vivado < 2024 +# TODO55: quick workaround for PR 146, extend this for all selectable IPs +ifeq ($(shell [ ${XILINX_VIVADO_VERSION} -lt 2024 ] && echo true),true) + FILTER_IP = xlnx_microblazev_rv32 xlnx_microblazev_rv64 xlnx_microblaze_debug_module_v xlnx_dual_microblaze_debug_module_v + TMP_IP_LIST = ${IP_LIST} + IP_LIST = $(filter-out ${FILTER_IP},${TMP_IP_LIST}) +endif + +# List of IPs' xci files to import in main Vivado project +IP_LIST_XCI = $(foreach ip,${IP_LIST},$(shell find ${XILINX_IPS_ROOT} -type f -path "*/${ip}/build/${ip}_prj.srcs/sources_1/ip/${ip}/${ip}.xci")) + +######################### +# Vivado run strategies # +######################### +# Vivado defaults +# SYNTH_STRATEGY ?= "Vivado Synthesis Defaults" +# IMPL_STRATEGY ?= "Vivado Implementation Defaults" +# Runtime optimized (shorter runtime) +# SYNTH_STRATEGY ?= Flow_RuntimeOptimized +# IMPL_STRATEGY ?= Flow_RuntimeOptimized +# High-performace (longer runtime) +SYNTH_STRATEGY ?= "Flow_PerfOptimized_high" +IMPL_STRATEGY ?= "Performance_ExtraTimingOpt" + +# Implementation artifacts +XILINX_BITSTREAM ?= ${XILINX_PROJECT_BUILD_DIR}/${XILINX_PROJECT_NAME}.runs/impl_1/${XILINX_PROJECT_NAME}.bit +XILINX_PROBE_LTX ?= ${XILINX_PROJECT_BUILD_DIR}/${XILINX_PROJECT_NAME}.runs/impl_1/${XILINX_PROJECT_NAME}.ltx + +# Whether to use ILA probes (0|1) +XILINX_ILA ?= 0 +# Clock net for ILA probes: use main clock by default +XILINX_ILA_CLOCK ?= main_clk + +# Full environment variables list for Vivado +XILINX_VIVADO_ENV = \ + MBUS_DATA_WIDTH=${MBUS_DATA_WIDTH} \ + MBUS_ADDR_WIDTH=${MBUS_ADDR_WIDTH} \ + CORE_SELECTOR=${CORE_SELECTOR} \ + VIO_RESETN_DEFAULT=${VIO_RESETN_DEFAULT} \ + MBUS_NUM_SI=${MBUS_NUM_SI} \ + MBUS_NUM_MI=${MBUS_NUM_MI} \ + MBUS_ID_WIDTH=${MBUS_ID_WIDTH} \ + MAIN_CLOCK_FREQ_MHZ=${MAIN_CLOCK_FREQ_MHZ} \ + RANGE_CLOCK_DOMAINS="${RANGE_CLOCK_DOMAINS}" \ + PBUS_NUM_MI=${PBUS_NUM_MI} \ + PBUS_ID_WIDTH=${PBUS_ID_WIDTH} \ + HBUS_NUM_MI=${HBUS_NUM_MI} \ + HBUS_NUM_SI=${HBUS_NUM_SI} \ + HBUS_ID_WIDTH=${HBUS_ID_WIDTH} \ + XILINX_ILA=${XILINX_ILA} \ + XILINX_ILA_CLOCK=${XILINX_ILA_CLOCK} \ + SYNTH_STRATEGY=${SYNTH_STRATEGY} \ + IMPL_STRATEGY=${IMPL_STRATEGY} \ + XILINX_PART_NUMBER=${XILINX_PART_NUMBER} \ + XILINX_PROJECT_NAME=${XILINX_PROJECT_NAME} \ + SOC_CONFIG=${SOC_CONFIG} \ + XILINX_BOARD_PART=${XILINX_BOARD_PART} \ + XILINX_HW_SERVER_HOST=${XILINX_HW_SERVER_HOST} \ + XILINX_HW_SERVER_PORT=${XILINX_HW_SERVER_PORT} \ + XILINX_FPGA_DEVICE=${XILINX_FPGA_DEVICE} \ + XILINX_BITSTREAM=${XILINX_BITSTREAM} \ + XILINX_PROBE_LTX=${XILINX_PROBE_LTX} \ + IP_LIST_XCI="${IP_LIST_XCI}" \ + XILINX_ROOT=${XILINX_ROOT} \ + QUESTA_PATH=${QUESTA_PATH} \ + GCC_PATH=${GCC_PATH} \ + XILINX_SIMLIB_PATH=${XILINX_SIMLIB_PATH} + +# Package Vivado command in a single variable +XILINX_VIVADO = ${XILINX_VIVADO_ENV} ${XILINX_VIVADO_CMD} -mode ${XILINX_VIVADO_MODE} +XILINX_VIVADO_BATCH = ${XILINX_VIVADO_ENV} ${XILINX_VIVADO_CMD} -mode batch + +# PCIe device and address +PCIE_BDF ?= 01:00.0 # TODO: remove this and find the PCIE_BDF automatically +PCIE_BAR ?= 0x$(shell lspci -vv -s ${PCIE_BDF} | grep Region | awk '{print $$5}') diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/load_binary.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/load_binary.mk new file mode 100644 index 0000000000000000000000000000000000000000..c7366d6ca0950c2ea871ea876c2ff6addbdd7b3b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/load_binary.mk @@ -0,0 +1,91 @@ +# Author: Vincenzo Maisto +# Author: Stefano Mercogliano +# Description: Make target to load binaries to SoC memory and interact with debugger + +# Get XLEN for SoC Configuration +include ${XILINX_ROOT}/make/config.mk + +# Common scripts directory +XILINX_SCRIPTS_LOAD_ROOT := ${XILINX_SCRIPT_ROOT}/load_binary + +# Default example to run +EXAMPLE ?= hello_world + +############### +# Load Binary # +############### + +# For CPUs that does not support debuggers yet + +# Path to target binary +BIN_PATH ?= ${SW_ROOT}/SoC/examples/${EXAMPLE}/bin/${EXAMPLE}.bin +# BRAM base address +BASE_ADDRESS ?= 0x00000000 +# Whether to readback and check the loaded binary or not +LOAD_BINARY_READBACK ?= false + +# Load the binary into SoC memory (BRAM for now) +# Call the specific load script based on the SOC_CONFIG (HPC or EMBEDDED) +load_binary: load_binary_${SOC_CONFIG} + +# Write the binary to BRAM through jtag2axi +load_binary_embedded: ${BIN_PATH} + ${XILINX_VIVADO} \ + -source ${XILINX_SCRIPT_ROOT}/utils/open_hw_manager.tcl \ + -source ${XILINX_SCRIPTS_LOAD_ROOT}/jtag2axi_load_binary.tcl \ + -tclargs ${BIN_PATH} ${BASE_ADDRESS} ${LOAD_BINARY_READBACK} + +# Write the binary to BRAM/DDR through XDMA +load_binary_hpc: ${BIN_PATH} + @bash -c "source ${XILINX_SCRIPTS_LOAD_ROOT}/xdma_load_binary.sh + ${PCIE_BAR} ${BIN_PATH} ${BASE_ADDRESS} ${LOAD_BINARY_READBACK}" + +###################### +# Load ELF - Backend # +###################### + +# To load a program as an .elf, a Debug Module must be available +# Depending on the selected CPU, two backends flows are supported + +# Path to target elf +ELF_PATH ?= ${SW_ROOT}/SoC/examples/${EXAMPLE}/bin/${EXAMPLE}.elf + +# Use XSDB as a backend +XSDB ?= xsdb +# For MicroblazeV, Vivado HW Server exposes ports: +# - 3004 for 32-bit, +# - 3005 for 64-bit +# Although if one of the port has already been used, hw_server will not switch and use the active one for either 32 or 64 bits. +# If using OpenOCD, we always connect to port 3004 +GDB_HOST ?= localhost +GDB_PORT ?= 3004 + +xsdb_run: + ${XSDB} -interactive ${XILINX_SCRIPTS_LOAD_ROOT}/xsdb_backend.tcl + +# Use openOCD as a backed +OPENOCD ?= openocd +OPENOCD_SCRIPT ?= ${XILINX_SCRIPTS_LOAD_ROOT}/openocd.cfg + +openocd_run: + @echo "[INFO] Make sure to kill any instance of hw_server running on the target USB device" + ${OPENOCD} -f ${OPENOCD_SCRIPT} + +################################## +# Load ELF - Debugger and Loader # +################################## + +# Use GDB to load the ELF and run (open the backend in a shell before) + +gdb_run: + ${XILINX_SCRIPTS_LOAD_ROOT}/run_gdb.sh ${ELF_PATH} ${GDB_HOST}:${GDB_PORT} ${XLEN} + +# Run XSBD to load the ELF and run directly +xsdb_run_elf: + ${XSDB} ${XILINX_SCRIPTS_LOAD_ROOT}/xsdb_run_elf.tcl ${ELF_PATH} + +########### +# PHONIES # +########### + +.PHONY: load_binary load_binary_embedded load_binary_hpc xsdb_run openocd_run gdb_run diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/sim.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/sim.mk new file mode 100644 index 0000000000000000000000000000000000000000..faf24b749fd8e51980dffe9aa61ea75cb8b97e29 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/sim.mk @@ -0,0 +1,18 @@ +# Description: Make target for simulation +# TODO: The simulation flow is not yet supported, this file is just a placeholder + +sim_compile_simlib: + ${XILINX_VIVADO_BATCH} -source ${XILINX_SIM_TCL_ROOT}/compile_simlib.tcl + +sim_export_%: ${XILINX_IPS_ROOT}/%/questa/compile.do +${XILINX_IPS_ROOT}/%/questa/compile.do: ${XILINX_SIM_IP_ROOT} + cd ${XILINX_SIMLIB_PATH}; \ + VIVADO_PROJECT=${XILINX_IPS_ROOT}/$*/build/$*.xpr \ + ${XILINX_VIVADO_BATCH} -source ${XILINX_SIM_TCL_ROOT}/export_simulation.tcl + +${XILINX_SIM_IP_ROOT}/ips: + mkdir -p $@ + + +# PHONIES +.PHONY: sim_compile_simlib diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/utils.mk b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/utils.mk new file mode 100644 index 0000000000000000000000000000000000000000..cbfab99d9f35e62e997313680ffef62400955781 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/make/utils.mk @@ -0,0 +1,82 @@ +# Author: Vincenzo Maisto +# Description: Hold all the Xilinx-related utility targets + +# Common scripts directory +XILINX_SCRIPTS_UTILS_ROOT := ${XILINX_SCRIPT_ROOT}/utils + +# Open project in TCL mode +open_prj: + cd ${XILINX_PROJECT_BUILD_DIR}; \ + ${XILINX_VIVADO_ENV} ${XILINX_VIVADO_CMD} \ + -mode tcl ${XILINX_PROJECT_NAME}.xpr + +# Open project and GUI +open_gui: + cd ${XILINX_PROJECT_BUILD_DIR}; \ + ${XILINX_VIVADO_ENV} ${XILINX_VIVADO_CMD} \ + -mode gui ${XILINX_PROJECT_NAME}.xpr + +# Start hardware server +start_hw_server: + ${XILINX_HW_SERVER} -d -L- -stcp::${XILINX_HW_SERVER_PORT} + +# Open Vivado hardware manager in tcl mode +open_hw_manager: + ${XILINX_VIVADO_ENV} ${XILINX_VIVADO_CMD} -mode tcl \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/$@.tcl + +# Open ILA dashboard GUI +open_ila: + ${XILINX_VIVADO_ENV} ${XILINX_VIVADO_CMD} -mode gui \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/open_hw_manager.tcl \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/set_ila_trigger.tcl + +# Read back from address +OFFSET ?= 0x00000 +NUM_BYTES ?= 16 + +# Load the binary into SoC memory (BRAM for now) +# Call the specific load script based on the SOC_CONFIG (HPC or EMBEDDED) +readback: readback_${SOC_CONFIG} + +# Embedded profile +readback_embedded: + ${XILINX_VIVADO_ENV} ${XILINX_VIVADO} \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/open_hw_manager.tcl \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/readback_jtag2axi.tcl -tclargs ${OFFSET} ${NUM_BYTES} + +# HPC profile +readback_hpc: + @bash -c "source ${XILINX_SCRIPTS_UTILS_ROOT}/readback_xdma.sh \ + ${PCIE_BAR} ${OFFSET} ${NUM_BYTES}" + +# Trigger a reset pulse on VIO probes +vio_resetn: +vio_%: + ${XILINX_VIVADO_ENV} ${XILINX_VIVADO} \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/open_hw_manager.tcl \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/vio_reset.tcl -tclargs $@ + +# Program the bitstream based on the SoC profile +program_bitstream: program_bitstream_${SOC_CONFIG} + +# Program bitstream for embedded profile +program_bitstream_embedded: + ${XILINX_VIVADO} \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/open_hw_manager.tcl \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/program_bitstream.tcl + +# Program bitstream for HPC profile +program_bitstream_hpc: +# Kill pending virtual_uart instances (if any) +# TODO: This might be overkill, as only that one instance should cause problems + -killall virtual_uart +# Program + ${XILINX_VIVADO} \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/open_hw_manager.tcl \ + -source ${XILINX_SCRIPTS_UTILS_ROOT}/program_bitstream.tcl +# Rescan PCIe device + sudo ${XILINX_SCRIPTS_UTILS_ROOT}/pcie_hot_reset.sh ${PCIE_BDF} + +# PHONIES +.PHONY: open_prj open_gui start_hw_server open_hw_manager open_ila program_bitstream program_bitstream_embedded program_bitstream_hpc diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/axi_clock_converter_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/axi_clock_converter_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..dc0eb7f42d0cdea89cb62ba48304905553523f0b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/axi_clock_converter_wrapper.sv @@ -0,0 +1,312 @@ +// Author: Stefano Mercogliano +// Author: Manuel Maddaluno +// Author: Valerio Di Domenico +// Description: This module is a wrapper for a xlnx_clock_converter. +// It either instantiates a 32 or 64 or 512 bits clock converter + +`include "uninasoc_axi.svh" + +module axi_clock_converter_wrapper # ( + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 2 + ) ( + + // Master Interface + input logic m_axi_aclk, + input logic m_axi_aresetn, + + `DEFINE_AXI_MASTER_PORTS(m, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + + // Slave Interface + input logic s_axi_aclk, + input logic s_axi_aresetn, + + `DEFINE_AXI_SLAVE_PORTS(s, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + +); + + generate + case (LOCAL_DATA_WIDTH) + + 32: begin : gen_axi_32_clock_conv + xlnx_axi_d32_clock_converter axi_clk_conv_u ( + + .s_axi_aclk ( s_axi_aclk ), + .s_axi_aresetn ( s_axi_aresetn ), + + .m_axi_aclk ( m_axi_aclk ), + .m_axi_aresetn ( m_axi_aresetn ), + + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awregion ( s_axi_awregion ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arregion ( s_axi_arregion ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rid ( m_axi_rid ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + ); + end + + 64: begin : gen_axi_64_clock_conv + xlnx_axi_d64_clock_converter axi_clk_conv_u ( + + .s_axi_aclk ( s_axi_aclk ), + .s_axi_aresetn ( s_axi_aresetn ), + + .m_axi_aclk ( m_axi_aclk ), + .m_axi_aresetn ( m_axi_aresetn ), + + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awregion ( s_axi_awregion ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arregion ( s_axi_arregion ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rid ( m_axi_rid ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + ); + end + + 512: begin : gen_axi_512_clock_conv + xlnx_axi_d512_clock_converter axi_clk_conv_u ( + + .s_axi_aclk ( s_axi_aclk ), + .s_axi_aresetn ( s_axi_aresetn ), + + .m_axi_aclk ( m_axi_aclk ), + .m_axi_aresetn ( m_axi_aresetn ), + + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awregion ( s_axi_awregion ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arregion ( s_axi_arregion ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rid ( m_axi_rid ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + ); + end + + default: begin + initial $error("Unsupported LOCAL_DATA_WIDTH: %0d (only 32, 64, 512 are valid)", LOCAL_DATA_WIDTH); + end + + endcase + endgenerate + +endmodule \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/axilite_uart.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/axilite_uart.sv new file mode 100644 index 0000000000000000000000000000000000000000..4219bb1bfa8fa891ca1d0b11871227b52dd6d4e2 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/axilite_uart.sv @@ -0,0 +1,97 @@ +// Author: Manuel Maddaluno +// Description: AXI4 Uart - This module encapsulates the AXI lite uart. The uart is selected based on the SOC_CONFIG. +// EMBEDDED -> AXILITE UART +// HPC -> VIRTUAL UART + + +// Import packages +import uninasoc_pkg::*; + +// Import headers +`include "uninasoc_axi.svh" + + +module axilite_uart # ( + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 2 + ) ( + input logic clock_i, + input logic reset_ni, + + // Interrupts + output logic int_core_o, + output logic int_xdma_o, + input logic [1:0] int_ack_i, + + // AXI4 Slave interface + `DEFINE_AXILITE_SLAVE_PORTS(s, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + + // EMBEDDED ONLY + // RX and TX signas + output logic tx_o, + input logic rx_i + +); + + `ifdef HPC + virtual_uart virtual_uart_u ( + .clock_i ( clock_i ), + .reset_ni ( reset_ni ), + .int_core_o ( int_core_o ), + .int_xdma_o ( int_xdma_o ), + .int_ack_i ( 2'b00 ), + + .s_axilite_awaddr ( s_axilite_awaddr ), // output wire [31 : 0] s_axilite_awaddr + .s_axilite_awprot ( s_axilite_awprot ), // output wire [2 : 0] s_axilite_awprot + .s_axilite_awvalid ( s_axilite_awvalid ), // output wire s_axilite_awvalid + .s_axilite_awready ( s_axilite_awready ), // input wire s_axilite_awready + .s_axilite_wdata ( s_axilite_wdata ), // output wire [31 : 0] s_axilite_wdata + .s_axilite_wstrb ( s_axilite_wstrb ), // output wire [3 : 0] s_axilite_wstrb + .s_axilite_wvalid ( s_axilite_wvalid ), // output wire s_axilite_wvalid + .s_axilite_wready ( s_axilite_wready ), // input wire s_axilite_wready + .s_axilite_bresp ( s_axilite_bresp ), // input wire [1 : 0] s_axilite_bresp + .s_axilite_bvalid ( s_axilite_bvalid ), // input wire s_axilite_bvalid + .s_axilite_bready ( s_axilite_bready ), // output wire s_axilite_bready + .s_axilite_araddr ( s_axilite_araddr ), // output wire [31 : 0] s_axilite_araddr + .s_axilite_arprot ( s_axilite_arprot ), // output wire [2 : 0] s_axilite_arprot + .s_axilite_arvalid ( s_axilite_arvalid ), // output wire s_axilite_arvalid + .s_axilite_arready ( s_axilite_arready ), // input wire s_axilite_arready + .s_axilite_rdata ( s_axilite_rdata ), // input wire [31 : 0] s_axilite_rdata + .s_axilite_rresp ( s_axilite_rresp ), // input wire [1 : 0] s_axilite_rresp + .s_axilite_rvalid ( s_axilite_rvalid ), // input wire s_axilite_rvalid + .s_axilite_rready ( s_axilite_rready ) // output wire s_axi_rready + + ); + + `elsif EMBEDDED + xlnx_axi_uartlite uart_u ( + .s_axi_aclk ( clock_i ), // input wire s_axi_aclk + .s_axi_aresetn ( reset_ni ), // input wire s_axi_aresetn + .interrupt ( int_core_o ), // output wire interrupt + .s_axi_awaddr ( s_axilite_awaddr ), // input wire [3 : 0] s_axi_awaddr + .s_axi_awvalid ( s_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( s_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( s_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( s_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( s_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( s_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( s_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( s_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( s_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( s_axilite_araddr ), // input wire [3 : 0] s_axi_araddr + .s_axi_arvalid ( s_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( s_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( s_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( s_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( s_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( s_axilite_rready ), // input wire s_axi_rready + .rx ( rx_i ), // input wire rx + .tx ( tx_o ) // output wire tx + ); + + assign int_xdma_o = '0; + + `endif + +endmodule diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/ddr4_channel_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/ddr4_channel_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..f0d23fe47587c7dc1ad4b1a6ad4c2a610d251a51 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/ddr4_channel_wrapper.sv @@ -0,0 +1,465 @@ +// Author: Manuel Maddaluno +// Author: Valerio Di Domenico +// Description: This module is a wrapper for a single DDR4 channel. +// It includes : +// - A clock converter to increase the frequency to 300 MHz +// - An optional System Cache (enabled if ENABLE_CACHE=1) +// - A datawidth converter to increase the datawidth to 512 bit (enabled if ENABLE_CACHE=0) +// - A DDR4 (MIG) IP +// +// Depending on the ENABLE_CACHE parameter, the architecture +// instantiates either the System Cache (ENABLE_CACHE=1) or a +// direct Data Width Converter (ENABLE_CACHE=0) before connecting +// to the Clock Converter and DDR4 (MIG). +// +// It has the following sub-architecture: +// _____________ +// | System | +// Main Clock Domain /------------------>| Cache |---->| Main Clock Domain DDR4CH Clock Domain +// ADDR: MBUS_ADDR_WIDTH | ENABLE_CACHE = 1 |_____________| | ADDR: MBUS_ADDR_WIDTH ____________ ADDR: 34 bit ____________ +// DATA: MBUS_DATA_WIDTH | | DATA: 512 | Clock | DATA: 512 bit | | +// ------------------------ ->| |----------------------->| Converter |----------------->| DDR4 (MIG) | +// s_axi | _____________ | to_clk_conv |____________| clk_conv_to_ddr4 |____________| +// | ENABLE_CACHE = 0 | Dwidth | | +// \------------------->| Converter |--->| +// |_____________| + + +`include "uninasoc_pcie.svh" +`include "uninasoc_ddr4.svh" + +module ddr4_channel_wrapper # ( + parameter int unsigned ENABLE_CACHE = 0, + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 32 +) ( + // SoC clock and reset + input logic clock_i, + input logic reset_ni, + + // DDR4 CH clock and reset + input logic clk_300mhz_x_p_i, + input logic clk_300mhz_x_n_i, + + // DDR4 channel interface (to PHYs) + `DEFINE_DDR4_PORTS(x), + + // DDR4 output clk and rst + output logic ddr_clk_o, + output logic ddr_rst_o, + + // AXI-lite CSR interface + `DEFINE_AXILITE_SLAVE_PORTS(s_ctrl, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + + // AXI4 Slave interface + `DEFINE_AXI_SLAVE_PORTS(s, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + +); + + // DDR4 local parameters + localparam DDR4_CHANNEL_ADDRESS_WIDTH = 34; + localparam DDR4_CHANNEL_DATA_WIDTH = 512; + + // DDR4 sys reset - it is active high + logic ddr4_reset = 1'b1; + + always @(posedge clock_i or negedge reset_ni) begin + if (reset_ni == 1'b0) begin + ddr4_reset <= 1'b1; + end else begin + ddr4_reset <= 1'b0; + end + end + + // DDR4 34-bits address signals + logic [DDR4_CHANNEL_ADDRESS_WIDTH-1:0] ddr4_axi_awaddr; + logic [DDR4_CHANNEL_ADDRESS_WIDTH-1:0] ddr4_axi_araddr; + + // AXI bus from the cache to the clock converter + `DECLARE_AXI_BUS(to_clk_conv, DDR4_CHANNEL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + + // AXI bus from the clock converter to the dwidth converter + `DECLARE_AXI_BUS(clk_conv_to_dwidth_conv, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + + // AXI bus from the cache to the DDR4 + `DECLARE_AXI_BUS(clk_conv_to_ddr4, DDR4_CHANNEL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + + generate + if (ENABLE_CACHE == 1 ) begin : with_cache + + xlnx_system_cache_0 system_cache_u ( + + .ACLK ( clock_i ), // input wire ACLK + .ARESETN ( reset_ni ), // input wire ARESETN + .Initializing ( /* empty */ ), // output wire Initializing + .S0_AXI_GEN_AWID ( s_axi_awid ), // input wire [2 : 0] S0_AXI_GEN_AWID + .S0_AXI_GEN_AWADDR ( s_axi_awaddr ), // input wire [31 : 0] S0_AXI_GEN_AWADDR + .S0_AXI_GEN_AWLEN ( s_axi_awlen ), // input wire [7 : 0] S0_AXI_GEN_AWLEN + .S0_AXI_GEN_AWSIZE ( s_axi_awsize ), // input wire [2 : 0] S0_AXI_GEN_AWSIZE + .S0_AXI_GEN_AWBURST ( s_axi_awburst ), // input wire [1 : 0] S0_AXI_GEN_AWBURST + .S0_AXI_GEN_AWLOCK ( s_axi_awlock ), // input wire S0_AXI_GEN_AWLOCK + .S0_AXI_GEN_AWCACHE ( s_axi_awcache ), // input wire [3 : 0] S0_AXI_GEN_AWCACHE + .S0_AXI_GEN_AWPROT ( s_axi_awprot ), // input wire [2 : 0] S0_AXI_GEN_AWPROT + .S0_AXI_GEN_AWQOS ( s_axi_awqos ), // input wire [3 : 0] S0_AXI_GEN_AWQOS + .S0_AXI_GEN_AWVALID ( s_axi_awvalid ), // input wire S0_AXI_GEN_AWVALID + .S0_AXI_GEN_AWREADY ( s_axi_awready ), // output wire S0_AXI_GEN_AWREADY + .S0_AXI_GEN_AWUSER ( s_axi_awuser ), // input wire [31 : 0] S0_AXI_GEN_AWUSER + .S0_AXI_GEN_WDATA ( s_axi_wdata ), // input wire [511 : 0] S0_AXI_GEN_WDATA + .S0_AXI_GEN_WSTRB ( s_axi_wstrb ), // input wire [63 : 0] S0_AXI_GEN_WSTRB + .S0_AXI_GEN_WLAST ( s_axi_wlast ), // input wire S0_AXI_GEN_WLAST + .S0_AXI_GEN_WVALID ( s_axi_wvalid ), // input wire S0_AXI_GEN_WVALID + .S0_AXI_GEN_WREADY ( s_axi_wready ), // output wire S0_AXI_GEN_WREADY + .S0_AXI_GEN_BRESP ( s_axi_bresp ), // output wire [1 : 0] S0_AXI_GEN_BRESP + .S0_AXI_GEN_BID ( s_axi_bid ), // output wire [2 : 0] S0_AXI_GEN_BID + .S0_AXI_GEN_BVALID ( s_axi_bvalid ), // output wire S0_AXI_GEN_BVALID + .S0_AXI_GEN_BREADY ( s_axi_bready ), // input wire S0_AXI_GEN_BREADY + .S0_AXI_GEN_ARID ( s_axi_arid ), // input wire [2 : 0] S0_AXI_GEN_ARID + .S0_AXI_GEN_ARADDR ( s_axi_araddr ), // input wire [31 : 0] S0_AXI_GEN_ARADDR + .S0_AXI_GEN_ARLEN ( s_axi_arlen ), // input wire [7 : 0] S0_AXI_GEN_ARLEN + .S0_AXI_GEN_ARSIZE ( s_axi_arsize ), // input wire [2 : 0] S0_AXI_GEN_ARSIZE + .S0_AXI_GEN_ARBURST ( s_axi_arburst ), // input wire [1 : 0] S0_AXI_GEN_ARBURST + .S0_AXI_GEN_ARLOCK ( s_axi_arlock ), // input wire S0_AXI_GEN_ARLOCK + .S0_AXI_GEN_ARCACHE ( s_axi_arcache ), // input wire [3 : 0] S0_AXI_GEN_ARCACHE + .S0_AXI_GEN_ARPROT ( s_axi_arprot ), // input wire [2 : 0] S0_AXI_GEN_ARPROT + .S0_AXI_GEN_ARQOS ( s_axi_arqos ), // input wire [3 : 0] S0_AXI_GEN_ARQOS + .S0_AXI_GEN_ARVALID ( s_axi_arvalid ), // input wire S0_AXI_GEN_ARVALID + .S0_AXI_GEN_ARREADY ( s_axi_arready ), // output wire S0_AXI_GEN_ARREADY + .S0_AXI_GEN_ARUSER ( s_axi_aruser ), // input wire [31 : 0] S0_AXI_GEN_ARUSER + .S0_AXI_GEN_RID ( s_axi_rid ), // output wire [2 : 0] S0_AXI_GEN_RID + .S0_AXI_GEN_RDATA ( s_axi_rdata ), // output wire [511 : 0] S0_AXI_GEN_RDATA + .S0_AXI_GEN_RRESP ( s_axi_rresp ), // output wire [1 : 0] S0_AXI_GEN_RRESP + .S0_AXI_GEN_RLAST ( s_axi_rlast ), // output wire S0_AXI_GEN_RLAST + .S0_AXI_GEN_RVALID ( s_axi_rvalid ), // output wire S0_AXI_GEN_RVALID + .S0_AXI_GEN_RREADY ( s_axi_rready ), // input wire S0_AXI_GEN_RREADY + .M0_AXI_AWID ( to_clk_conv_axi_awid ), // output wire [0 : 0] M0_AXI_AWID + .M0_AXI_AWADDR ( to_clk_conv_axi_awaddr ), // output wire [31 : 0] M0_AXI_AWADDR + .M0_AXI_AWLEN ( to_clk_conv_axi_awlen ), // output wire [7 : 0] M0_AXI_AWLEN + .M0_AXI_AWSIZE ( to_clk_conv_axi_awsize ), // output wire [2 : 0] M0_AXI_AWSIZE + .M0_AXI_AWBURST ( to_clk_conv_axi_awburst ), // output wire [1 : 0] M0_AXI_AWBURST + .M0_AXI_AWLOCK ( to_clk_conv_axi_awlock ), // output wire M0_AXI_AWLOCK + .M0_AXI_AWCACHE ( to_clk_conv_axi_awcache ), // output wire [3 : 0] M0_AXI_AWCACHE + .M0_AXI_AWPROT ( to_clk_conv_axi_awprot ), // output wire [2 : 0] M0_AXI_AWPROT + .M0_AXI_AWQOS ( to_clk_conv_axi_awqos ), // output wire [3 : 0] M0_AXI_AWQOS + .M0_AXI_AWVALID ( to_clk_conv_axi_awvalid ), // output wire M0_AXI_AWVALID + .M0_AXI_AWREADY ( to_clk_conv_axi_awready ), // input wire M0_AXI_AWREADY + .M0_AXI_WDATA ( to_clk_conv_axi_wdata ), // output wire [511 : 0] M0_AXI_WDATA + .M0_AXI_WSTRB ( to_clk_conv_axi_wstrb ), // output wire [3 : 0] M0_AXI_WSTRB + .M0_AXI_WLAST ( to_clk_conv_axi_wlast ), // output wire M0_AXI_WLAST + .M0_AXI_WVALID ( to_clk_conv_axi_wvalid ), // output wire M0_AXI_WVALID + .M0_AXI_WREADY ( to_clk_conv_axi_wready ), // input wire M0_AXI_WREADY + .M0_AXI_BRESP ( to_clk_conv_axi_bresp ), // input wire [1 : 0] M0_AXI_BRESP + .M0_AXI_BID ( to_clk_conv_axi_bid ), // input wire [0 : 0] M0_AXI_BID + .M0_AXI_BVALID ( to_clk_conv_axi_bvalid ), // input wire M0_AXI_BVALID + .M0_AXI_BREADY ( to_clk_conv_axi_bready ), // output wire M0_AXI_BREADY + .M0_AXI_ARID ( to_clk_conv_axi_arid ), // output wire [0 : 0] M0_AXI_ARID + .M0_AXI_ARADDR ( to_clk_conv_axi_araddr ), // output wire [31 : 0] M0_AXI_ARADDR + .M0_AXI_ARLEN ( to_clk_conv_axi_arlen ), // output wire [7 : 0] M0_AXI_ARLEN + .M0_AXI_ARSIZE ( to_clk_conv_axi_arsize ), // output wire [2 : 0] M0_AXI_ARSIZE + .M0_AXI_ARBURST ( to_clk_conv_axi_arburst ), // output wire [1 : 0] M0_AXI_ARBURST + .M0_AXI_ARLOCK ( to_clk_conv_axi_arlock ), // output wire M0_AXI_ARLOCK + .M0_AXI_ARCACHE ( to_clk_conv_axi_arcache ), // output wire [3 : 0] M0_AXI_ARCACHE + .M0_AXI_ARPROT ( to_clk_conv_axi_arprot ), // output wire [2 : 0] M0_AXI_ARPROT + .M0_AXI_ARQOS ( to_clk_conv_axi_arqos ), // output wire [3 : 0] M0_AXI_ARQOS + .M0_AXI_ARVALID ( to_clk_conv_axi_arvalid ), // output wire M0_AXI_ARVALID + .M0_AXI_ARREADY ( to_clk_conv_axi_arready ), // input wire M0_AXI_ARREADY + .M0_AXI_RID ( to_clk_conv_axi_rid ), // input wire [0 : 0] M0_AXI_RID + .M0_AXI_RDATA ( to_clk_conv_axi_rdata ), // input wire [511 : 0] M0_AXI_RDATA + .M0_AXI_RRESP ( to_clk_conv_axi_rresp ), // input wire [1 : 0] M0_AXI_RRESP + .M0_AXI_RLAST ( to_clk_conv_axi_rlast ), // input wire M0_AXI_RLAST + .M0_AXI_RVALID ( to_clk_conv_axi_rvalid ), // input wire M0_AXI_RVALID + .M0_AXI_RREADY ( to_clk_conv_axi_rready ) // output wire M0_AXI_RREADY + ); + + end else begin : no_cache + + // Dwidth converter master ID signals assigned to 0 + // Since the AXI data width converter has a reordering depth of 1 it doesn't have ID in its master ports - for more details see the documentation + // Thus, we assign 0 to all these signals that go to the clock converter + assign to_clk_conv_axi_awid = '0; + assign to_clk_conv_axi_arid = '0; + + // AXI dwith converter from XLEN bit (global AXI data width) to 512 bit (AXI user interface DDR data width) + xlnx_axi_dwidth_to512_converter axi_dwidth_conv_u ( + .s_axi_aclk ( clock_i ), + .s_axi_aresetn ( reset_ni ), + + // Slave + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awregion ( s_axi_awregion ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arregion ( s_axi_arregion ), + + // Master to Clock Converter + //.m_axi_awid ( dwidth_conv_to_cache_axi_awid ), + .m_axi_awaddr ( to_clk_conv_axi_awaddr ), + .m_axi_awlen ( to_clk_conv_axi_awlen ), + .m_axi_awsize ( to_clk_conv_axi_awsize ), + .m_axi_awburst ( to_clk_conv_axi_awburst ), + .m_axi_awlock ( to_clk_conv_axi_awlock ), + .m_axi_awcache ( to_clk_conv_axi_awcache ), + .m_axi_awprot ( to_clk_conv_axi_awprot ), + .m_axi_awqos ( to_clk_conv_axi_awqos ), + .m_axi_awvalid ( to_clk_conv_axi_awvalid ), + .m_axi_awready ( to_clk_conv_axi_awready ), + .m_axi_wdata ( to_clk_conv_axi_wdata ), + .m_axi_wstrb ( to_clk_conv_axi_wstrb ), + .m_axi_wlast ( to_clk_conv_axi_wlast ), + .m_axi_wvalid ( to_clk_conv_axi_wvalid ), + .m_axi_wready ( to_clk_conv_axi_wready ), + //.m_axi_bid ( dwidth_conv_to_cache_axi_bid ), + .m_axi_bresp ( to_clk_conv_axi_bresp ), + .m_axi_bvalid ( to_clk_conv_axi_bvalid ), + .m_axi_bready ( to_clk_conv_axi_bready ), + //.m_axi_arid ( dwidth_conv_to_cache_axi_arid ), + .m_axi_araddr ( to_clk_conv_axi_araddr ), + .m_axi_arlen ( to_clk_conv_axi_arlen ), + .m_axi_arsize ( to_clk_conv_axi_arsize ), + .m_axi_arburst ( to_clk_conv_axi_arburst ), + .m_axi_arlock ( to_clk_conv_axi_arlock ), + .m_axi_arcache ( to_clk_conv_axi_arcache ), + .m_axi_arprot ( to_clk_conv_axi_arprot ), + .m_axi_arqos ( to_clk_conv_axi_arqos ), + .m_axi_arvalid ( to_clk_conv_axi_arvalid ), + .m_axi_arready ( to_clk_conv_axi_arready ), + //.m_axi_rid ( dwidth_conv_to_cache_axi_rid ), + .m_axi_rdata ( to_clk_conv_axi_rdata ), + .m_axi_rresp ( to_clk_conv_axi_rresp ), + .m_axi_rlast ( to_clk_conv_axi_rlast ), + .m_axi_rvalid ( to_clk_conv_axi_rvalid ), + .m_axi_rready ( to_clk_conv_axi_rready ) + ); + end + endgenerate + + // AXI Clock converter from 250 MHz (xdma global design clk) to 300 MHz (AXI user interface DDR clk) - the data width is XLEN + axi_clock_converter_wrapper # ( + .LOCAL_DATA_WIDTH ( DDR4_CHANNEL_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( LOCAL_ID_WIDTH ) + ) axi_clk_conv_u ( + + .s_axi_aclk ( clock_i ), + .s_axi_aresetn ( reset_ni ), + + .m_axi_aclk ( ddr_clk_o ), + .m_axi_aresetn ( ~ddr_rst_o ), + // Slave from Cache or Dwidth Converter + .s_axi_awid ( to_clk_conv_axi_awid ), + .s_axi_awaddr ( to_clk_conv_axi_awaddr ), + .s_axi_awlen ( to_clk_conv_axi_awlen ), + .s_axi_awsize ( to_clk_conv_axi_awsize ), + .s_axi_awburst ( to_clk_conv_axi_awburst ), + .s_axi_awlock ( to_clk_conv_axi_awlock ), + .s_axi_awcache ( to_clk_conv_axi_awcache ), + .s_axi_awprot ( to_clk_conv_axi_awprot ), + .s_axi_awqos ( to_clk_conv_axi_awqos ), + .s_axi_awvalid ( to_clk_conv_axi_awvalid ), + .s_axi_awready ( to_clk_conv_axi_awready ), + .s_axi_awregion ( to_clk_conv_axi_awregion ), + .s_axi_wdata ( to_clk_conv_axi_wdata ), + .s_axi_wstrb ( to_clk_conv_axi_wstrb ), + .s_axi_wlast ( to_clk_conv_axi_wlast ), + .s_axi_wvalid ( to_clk_conv_axi_wvalid ), + .s_axi_wready ( to_clk_conv_axi_wready ), + .s_axi_bid ( to_clk_conv_axi_bid ), + .s_axi_bresp ( to_clk_conv_axi_bresp ), + .s_axi_bvalid ( to_clk_conv_axi_bvalid ), + .s_axi_bready ( to_clk_conv_axi_bready ), + .s_axi_arid ( to_clk_conv_axi_arid ), + .s_axi_araddr ( to_clk_conv_axi_araddr ), + .s_axi_arlen ( to_clk_conv_axi_arlen ), + .s_axi_arsize ( to_clk_conv_axi_arsize ), + .s_axi_arburst ( to_clk_conv_axi_arburst ), + .s_axi_arlock ( to_clk_conv_axi_arlock ), + .s_axi_arregion ( to_clk_conv_axi_arregion ), + .s_axi_arcache ( to_clk_conv_axi_arcache ), + .s_axi_arprot ( to_clk_conv_axi_arprot ), + .s_axi_arqos ( to_clk_conv_axi_arqos ), + .s_axi_arvalid ( to_clk_conv_axi_arvalid ), + .s_axi_arready ( to_clk_conv_axi_arready ), + .s_axi_rid ( to_clk_conv_axi_rid ), + .s_axi_rdata ( to_clk_conv_axi_rdata ), + .s_axi_rresp ( to_clk_conv_axi_rresp ), + .s_axi_rlast ( to_clk_conv_axi_rlast ), + .s_axi_rvalid ( to_clk_conv_axi_rvalid ), + .s_axi_rready ( to_clk_conv_axi_rready ), + // Master to DDR + .m_axi_awid ( clk_conv_to_ddr4_axi_awid ), + .m_axi_awaddr ( clk_conv_to_ddr4_axi_awaddr ), + .m_axi_awlen ( clk_conv_to_ddr4_axi_awlen ), + .m_axi_awsize ( clk_conv_to_ddr4_axi_awsize ), + .m_axi_awburst ( clk_conv_to_ddr4_axi_awburst ), + .m_axi_awlock ( clk_conv_to_ddr4_axi_awlock ), + .m_axi_awcache ( clk_conv_to_ddr4_axi_awcache ), + .m_axi_awprot ( clk_conv_to_ddr4_axi_awprot ), + .m_axi_awregion ( clk_conv_to_ddr4_axi_awregion ), + .m_axi_awqos ( clk_conv_to_ddr4_axi_awqos ), + .m_axi_awvalid ( clk_conv_to_ddr4_axi_awvalid ), + .m_axi_awready ( clk_conv_to_ddr4_axi_awready ), + .m_axi_wdata ( clk_conv_to_ddr4_axi_wdata ), + .m_axi_wstrb ( clk_conv_to_ddr4_axi_wstrb ), + .m_axi_wlast ( clk_conv_to_ddr4_axi_wlast ), + .m_axi_wvalid ( clk_conv_to_ddr4_axi_wvalid ), + .m_axi_wready ( clk_conv_to_ddr4_axi_wready ), + .m_axi_bid ( clk_conv_to_ddr4_axi_bid ), + .m_axi_bresp ( clk_conv_to_ddr4_axi_bresp ), + .m_axi_bvalid ( clk_conv_to_ddr4_axi_bvalid ), + .m_axi_bready ( clk_conv_to_ddr4_axi_bready ), + .m_axi_arid ( clk_conv_to_ddr4_axi_arid ), + .m_axi_araddr ( clk_conv_to_ddr4_axi_araddr ), + .m_axi_arlen ( clk_conv_to_ddr4_axi_arlen ), + .m_axi_arsize ( clk_conv_to_ddr4_axi_arsize ), + .m_axi_arburst ( clk_conv_to_ddr4_axi_arburst ), + .m_axi_arlock ( clk_conv_to_ddr4_axi_arlock ), + .m_axi_arcache ( clk_conv_to_ddr4_axi_arcache ), + .m_axi_arprot ( clk_conv_to_ddr4_axi_arprot ), + .m_axi_arregion ( clk_conv_to_ddr4_axi_arregion ), + .m_axi_arqos ( clk_conv_to_ddr4_axi_arqos ), + .m_axi_arvalid ( clk_conv_to_ddr4_axi_arvalid ), + .m_axi_arready ( clk_conv_to_ddr4_axi_arready ), + .m_axi_rid ( clk_conv_to_ddr4_axi_rid ), + .m_axi_rdata ( clk_conv_to_ddr4_axi_rdata ), + .m_axi_rresp ( clk_conv_to_ddr4_axi_rresp ), + .m_axi_rlast ( clk_conv_to_ddr4_axi_rlast ), + .m_axi_rvalid ( clk_conv_to_ddr4_axi_rvalid ), + .m_axi_rready ( clk_conv_to_ddr4_axi_rready ) + + ); + + + // Map DDR4 address signals + // Zero extend them if the address width is 32, otherwise clip them down. + assign ddr4_axi_awaddr = (LOCAL_ADDR_WIDTH == 32) ? { 2'b00, clk_conv_to_ddr4_axi_awaddr } : clk_conv_to_ddr4_axi_awaddr[DDR4_CHANNEL_ADDRESS_WIDTH-1:0]; + assign ddr4_axi_araddr = (LOCAL_ADDR_WIDTH == 32) ? { 2'b00, clk_conv_to_ddr4_axi_araddr } : clk_conv_to_ddr4_axi_araddr[DDR4_CHANNEL_ADDRESS_WIDTH-1:0]; + + xlnx_ddr4 ddr4_u ( + .c0_sys_clk_n ( clk_300mhz_x_n_i ), + .c0_sys_clk_p ( clk_300mhz_x_p_i ), + + .sys_rst ( ddr4_reset ), + + // Output - Calibration complete, the memory controller waits for this + .c0_init_calib_complete ( /* empty */ ), + // Output - Interrupt about ECC + .c0_ddr4_interrupt ( /* empty */ ), + // Output - these two debug ports must be open, in the implementation phase Vivado connects these two properly + .dbg_clk ( /* empty */ ), + .dbg_bus ( /* empty */ ), + + // DDR4 interface - to the physical memory + .c0_ddr4_adr ( cx_ddr4_adr ), + .c0_ddr4_ba ( cx_ddr4_ba ), + .c0_ddr4_cke ( cx_ddr4_cke ), + .c0_ddr4_cs_n ( cx_ddr4_cs_n ), + .c0_ddr4_dq ( cx_ddr4_dq ), + .c0_ddr4_dqs_t ( cx_ddr4_dqs_t ), + .c0_ddr4_dqs_c ( cx_ddr4_dqs_c ), + .c0_ddr4_odt ( cx_ddr4_odt ), + .c0_ddr4_parity ( cx_ddr4_parity ), + .c0_ddr4_bg ( cx_ddr4_bg ), + .c0_ddr4_reset_n ( cx_ddr4_reset_n ), + .c0_ddr4_act_n ( cx_ddr4_act_n ), + .c0_ddr4_ck_t ( cx_ddr4_ck_t ), + .c0_ddr4_ck_c ( cx_ddr4_ck_c ), + + .c0_ddr4_ui_clk ( ddr_clk_o ), + .c0_ddr4_ui_clk_sync_rst ( ddr_rst_o ), + + .c0_ddr4_aresetn ( ~ddr_rst_o ), + + // AXILITE interface - for status and control + .c0_ddr4_s_axi_ctrl_awvalid ( s_ctrl_axilite_awvalid ), + .c0_ddr4_s_axi_ctrl_awready ( s_ctrl_axilite_awready ), + .c0_ddr4_s_axi_ctrl_awaddr ( s_ctrl_axilite_awaddr ), + .c0_ddr4_s_axi_ctrl_wvalid ( s_ctrl_axilite_wvalid ), + .c0_ddr4_s_axi_ctrl_wready ( s_ctrl_axilite_wready ), + .c0_ddr4_s_axi_ctrl_wdata ( s_ctrl_axilite_wdata ), + .c0_ddr4_s_axi_ctrl_bvalid ( s_ctrl_axilite_bvalid ), + .c0_ddr4_s_axi_ctrl_bready ( s_ctrl_axilite_bready ), + .c0_ddr4_s_axi_ctrl_bresp ( s_ctrl_axilite_bresp ), + .c0_ddr4_s_axi_ctrl_arvalid ( s_ctrl_axilite_arvalid ), + .c0_ddr4_s_axi_ctrl_arready ( s_ctrl_axilite_arready ), + .c0_ddr4_s_axi_ctrl_araddr ( s_ctrl_axilite_araddr ), + .c0_ddr4_s_axi_ctrl_rvalid ( s_ctrl_axilite_rvalid ), + .c0_ddr4_s_axi_ctrl_rready ( s_ctrl_axilite_rready ), + .c0_ddr4_s_axi_ctrl_rdata ( s_ctrl_axilite_rdata ), + .c0_ddr4_s_axi_ctrl_rresp ( s_ctrl_axilite_rresp ), + + + // AXI4 interface + .c0_ddr4_s_axi_awid ( clk_conv_to_ddr4_axi_awid ), + .c0_ddr4_s_axi_awaddr ( ddr4_axi_awaddr ), + .c0_ddr4_s_axi_awlen ( clk_conv_to_ddr4_axi_awlen ), + .c0_ddr4_s_axi_awsize ( clk_conv_to_ddr4_axi_awsize ), + .c0_ddr4_s_axi_awburst ( clk_conv_to_ddr4_axi_awburst ), + .c0_ddr4_s_axi_awlock ( clk_conv_to_ddr4_axi_awlock ), + .c0_ddr4_s_axi_awcache ( clk_conv_to_ddr4_axi_awcache ), + .c0_ddr4_s_axi_awprot ( clk_conv_to_ddr4_axi_awprot ), + .c0_ddr4_s_axi_awqos ( clk_conv_to_ddr4_axi_awqos ), + .c0_ddr4_s_axi_awvalid ( clk_conv_to_ddr4_axi_awvalid ), + .c0_ddr4_s_axi_awready ( clk_conv_to_ddr4_axi_awready ), + .c0_ddr4_s_axi_wdata ( clk_conv_to_ddr4_axi_wdata ), + .c0_ddr4_s_axi_wstrb ( clk_conv_to_ddr4_axi_wstrb ), + .c0_ddr4_s_axi_wlast ( clk_conv_to_ddr4_axi_wlast ), + .c0_ddr4_s_axi_wvalid ( clk_conv_to_ddr4_axi_wvalid ), + .c0_ddr4_s_axi_wready ( clk_conv_to_ddr4_axi_wready ), + .c0_ddr4_s_axi_bready ( clk_conv_to_ddr4_axi_bready ), + .c0_ddr4_s_axi_bid ( clk_conv_to_ddr4_axi_bid ), + .c0_ddr4_s_axi_bresp ( clk_conv_to_ddr4_axi_bresp ), + .c0_ddr4_s_axi_bvalid ( clk_conv_to_ddr4_axi_bvalid ), + .c0_ddr4_s_axi_arid ( clk_conv_to_ddr4_axi_arid ), + .c0_ddr4_s_axi_araddr ( ddr4_axi_araddr ), + .c0_ddr4_s_axi_arlen ( clk_conv_to_ddr4_axi_arlen ), + .c0_ddr4_s_axi_arsize ( clk_conv_to_ddr4_axi_arsize ), + .c0_ddr4_s_axi_arburst ( clk_conv_to_ddr4_axi_arburst ), + .c0_ddr4_s_axi_arlock ( clk_conv_to_ddr4_axi_arlock ), + .c0_ddr4_s_axi_arcache ( clk_conv_to_ddr4_axi_arcache ), + .c0_ddr4_s_axi_arprot ( clk_conv_to_ddr4_axi_arprot ), + .c0_ddr4_s_axi_arqos ( clk_conv_to_ddr4_axi_arqos ), + .c0_ddr4_s_axi_arvalid ( clk_conv_to_ddr4_axi_arvalid ), + .c0_ddr4_s_axi_arready ( clk_conv_to_ddr4_axi_arready ), + .c0_ddr4_s_axi_rready ( clk_conv_to_ddr4_axi_rready ), + .c0_ddr4_s_axi_rlast ( clk_conv_to_ddr4_axi_rlast ), + .c0_ddr4_s_axi_rvalid ( clk_conv_to_ddr4_axi_rvalid ), + .c0_ddr4_s_axi_rresp ( clk_conv_to_ddr4_axi_rresp ), + .c0_ddr4_s_axi_rid ( clk_conv_to_ddr4_axi_rid ), + .c0_ddr4_s_axi_rdata ( clk_conv_to_ddr4_axi_rdata ) + ); + +endmodule diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/hbus_buses.svinc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/hbus_buses.svinc new file mode 100644 index 0000000000000000000000000000000000000000..f803cea0feb81278c0f9e716c6c0e8312d02f814 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/hbus_buses.svinc @@ -0,0 +1,25 @@ +// This file is auto-generated with declare_and_concat_buses_rtl.py + +///////////////////////////////////////// +// Buses declaration and concatenation // +///////////////////////////////////////// + +///////////////// +// AXI Masters // +///////////////// + +///////////////// +// AXI Slaves // +///////////////// + +////////////////////////////////// +// Concatenate AXI master buses // +////////////////////////////////// +`DECLARE_AXI_BUS_ARRAY(HBUS_masters, HBUS_NUM_SI, HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH) +`CONCAT_AXI_MASTERS_ARRAY0(HBUS_masters) + +///////////////////////////////// +// Concatenate AXI slave buses // +///////////////////////////////// +`DECLARE_AXI_BUS_ARRAY(HBUS_slaves, HBUS_NUM_MI, HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH) +`CONCAT_AXI_SLAVES_ARRAY0(HBUS_slaves) diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/highperformance_bus.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/highperformance_bus.sv new file mode 100644 index 0000000000000000000000000000000000000000..34caa73f3eb6a560ca61fd2e2588a36036b1c7fd --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/highperformance_bus.sv @@ -0,0 +1,717 @@ +// Author: Vincenzo Maisto +// Description: +// Wrapper of the high-performance bus (HBUS) offering wide data interfaces, e.g. 512 bits. This bus offers several AXI interfaces: +// - masters: +// - to DDR channels (wide) +// - to HBM channels (wide) +// - m_MBUS: to MBUS (XLEN) +// - slaves: +// - s_MBUS: from MBUS (XLEN) +// - s_acc: from accelerators (wide) +// - Clocking +// - each DDR or HBM channel is clocked in its own physical clock domain +// - the core xbar is clocked on a high-speed clock from a physical DRAM domain, DDR channel 0 by default +// - the core xbar clock/reset are exposed externally, e.g. for accelerators +// - the MBUS interfaces (m_MBUS and s_MBUS) are already clock-bridged and data-width adapted +// +// Architecture: +// ___________ _____________ ______________ ______________ +// s_MBUS | | DATA: XLEN | | DATA: 512 | | | |_ +// ------------>| Clock |----------->| Dwidth |----------->| |---------->| DDR channels | | +// Main clock | Converter | HBUS | Converter | | High |---------->| (MIG) | | +// domain |___________| domain |_____________| | Performance | |______________| | +// | XBAR | |______________| +// s_acc | | ______________ +// ---------------------------------------------------------------->| | | |_ +// ---------------------------------------------------------------->| |---------->| HBM channels | | +// HBUS clock | |---------->| (TBD) | | +// domain | | |______________| | +// | | |_____________| +// | | +// | | _____________ ___________ +// | | DATA: 512 | | DATA: XLEN | | +// | |---------->| Dwidth |----------->| Clock |-------> m_MBUS +// | | | Converter | HBUS | Converter | Main +// |______________| |_____________| domain |___________| domain +// +// + +// Import packages +import uninasoc_pkg::*; + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_ddr4.svh" + +module highperformance_bus #( + // HBUS AXI parameters + parameter int unsigned HBUS_DATA_WIDTH = 512, // In bits + parameter int unsigned HBUS_ADDR_WIDTH = 34, // In bits + parameter int unsigned HBUS_ID_WIDTH = 4, // In bits + // MBUS AXI parameters + parameter int unsigned MBUS_DATA_WIDTH = 32, // In bits, XLEN + parameter int unsigned MBUS_ADDR_WIDTH = 32, // In bits, PHYSICAL_ADDR_WIDTH + parameter int unsigned MBUS_ID_WIDTH = 4, // In bits + // Lengths of port arrays + parameter int unsigned NUM_ACC_MASTERS = 1, // Number of accelerator masters to HBUS (TBD) + parameter int unsigned NUM_DDR_CHANNELS = 1, // Number of DDR channels under HBUS (TBD) + parameter int unsigned NUM_HBM_CHANNELS = 0 // Number of HBM channels under HBUS (TBD) +)( + + // MBUS clock and reset + input logic main_clock_i, + input logic main_reset_ni, + + // AXI4 Slave interface from MBUS + `DEFINE_AXI_SLAVE_PORTS(s_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH), + // AXI4 Master interface to MBUS + `DEFINE_AXI_MASTER_PORTS(m_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH), + + // TODO: expose an array of NUM_ACC_MASTERS interfaces + // AXI4 Slave interface from accelerators + `DEFINE_AXI_SLAVE_PORTS(s_acc, HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH), + + // TODO: expose an array of NUM_DDR_CHANNELS pins and interfaces + // DDR4 CH clock and reset + input logic clk_300mhz_x_p_i, + input logic clk_300mhz_x_n_i, + // DDR4 channel output clock and reset + output logic clk_300MHz_o, + output logic rstn_300MHz_o, + // DDR channel + `DEFINE_DDR4_PORTS(x), + // AXI-lite CSR interface + `DEFINE_AXILITE_SLAVE_PORTS(s_ctrl, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) + + // TODO: expose an array of NUM_HBM_CHANNELS pins and interfaces + // TBD +); + + // Ensure HBUS has clock domain + `ifndef HBUS_HAS_CLOCK_DOMAIN + $error("HBUS must be in have its own clock domain!"); + `endif + + // For simplicity + initial begin : assert_properties + assert( MBUS_ID_WIDTH == HBUS_ID_WIDTH ) + else $error("HBUS_ID_WIDTH (%d) must be the same as MBUS_ID_WIDTH (%d)", HBUS_ID_WIDTH, MBUS_ID_WIDTH); + end : assert_properties + + ///////////////// + // Assignments // + ///////////////// + assign clk_300MHz_o = ddr_clk; + assign rstn_300MHz_o = ~ddr_rst; + + ///////////////////////////////////////// + // Buses declaration and concatenation // + ///////////////////////////////////////// + `include "hbus_buses.svinc" + // MBUS_DATA_WIDTH + `DECLARE_AXI_BUS(s_MBUS_clock_conv_to_dwidth_conv, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) + `DECLARE_AXI_BUS(m_MBUS_dwidth_conv_to_clock_conv, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) + // HBUS_DATA_WIDTH, and MBUS address and id width + `DECLARE_AXI_BUS(dwidth_conv_to_HBUS , HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH) + `DECLARE_AXI_BUS(dwidth_conv_from_HBUS , HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH) + + // HBUS <-> MBUS interconnect + // - s_MBUS (slave from MBUS) + // (s_MBUS) -> xlnx_axi_clock_converter_s_MBUS_u -> (s_MBUS_clock_conv_to_dwidth_conv) -> axi_dwidth_conv_s_MBUS_u -> (dwidth_conv_to_HBUS) -> ASSIGN_AXI_BUS -> (MBUS_to_HBUS) + // - m_MBUS (master to MBUS) + // (HBUS_to_MBUS) -> ASSIGN_AXI_BUS -> (dwidth_conv_from_HBUS) -> axi_dwidth_conv_m_MBUS_u -> (m_MBUS_dwidth_conv_to_clock_conv) -> xlnx_axi_clock_converter_m_MBUS_u -> (m_MBUS) + + //////////////////// + // AXI Converters // + //////////////////// + + logic HBUS_clk ; + logic HBUS_rstn; + assign HBUS_clk = ddr_clk; + assign HBUS_rstn = ~ddr_rst; + + // Clock converter + // s_MBUS -> s_MBUS_clock_conv_to_dwidth_conv + axi_clock_converter_wrapper # ( + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ) + ) xlnx_axi_clock_converter_s_MBUS_u ( + // Slave from MBUS + .s_axi_aclk ( main_clock_i ), + .s_axi_aresetn ( main_reset_ni ), + .s_axi_awid ( s_MBUS_axi_awid ), + .s_axi_awaddr ( s_MBUS_axi_awaddr ), + .s_axi_awlen ( s_MBUS_axi_awlen ), + .s_axi_awsize ( s_MBUS_axi_awsize ), + .s_axi_awburst ( s_MBUS_axi_awburst ), + .s_axi_awlock ( s_MBUS_axi_awlock ), + .s_axi_awcache ( s_MBUS_axi_awcache ), + .s_axi_awprot ( s_MBUS_axi_awprot ), + .s_axi_awqos ( s_MBUS_axi_awqos ), + .s_axi_awvalid ( s_MBUS_axi_awvalid ), + .s_axi_awready ( s_MBUS_axi_awready ), + .s_axi_awregion ( s_MBUS_axi_awregion ), + .s_axi_wdata ( s_MBUS_axi_wdata ), + .s_axi_wstrb ( s_MBUS_axi_wstrb ), + .s_axi_wlast ( s_MBUS_axi_wlast ), + .s_axi_wvalid ( s_MBUS_axi_wvalid ), + .s_axi_wready ( s_MBUS_axi_wready ), + .s_axi_bid ( s_MBUS_axi_bid ), + .s_axi_bresp ( s_MBUS_axi_bresp ), + .s_axi_bvalid ( s_MBUS_axi_bvalid ), + .s_axi_bready ( s_MBUS_axi_bready ), + .s_axi_arid ( s_MBUS_axi_arid ), + .s_axi_araddr ( s_MBUS_axi_araddr ), + .s_axi_arlen ( s_MBUS_axi_arlen ), + .s_axi_arsize ( s_MBUS_axi_arsize ), + .s_axi_arburst ( s_MBUS_axi_arburst ), + .s_axi_arlock ( s_MBUS_axi_arlock ), + .s_axi_arregion ( s_MBUS_axi_arregion ), + .s_axi_arcache ( s_MBUS_axi_arcache ), + .s_axi_arprot ( s_MBUS_axi_arprot ), + .s_axi_arqos ( s_MBUS_axi_arqos ), + .s_axi_arvalid ( s_MBUS_axi_arvalid ), + .s_axi_arready ( s_MBUS_axi_arready ), + .s_axi_rid ( s_MBUS_axi_rid ), + .s_axi_rdata ( s_MBUS_axi_rdata ), + .s_axi_rresp ( s_MBUS_axi_rresp ), + .s_axi_rlast ( s_MBUS_axi_rlast ), + .s_axi_rvalid ( s_MBUS_axi_rvalid ), + .s_axi_rready ( s_MBUS_axi_rready ), + // Master to HBUS + .m_axi_aclk ( HBUS_clk ), + .m_axi_aresetn ( HBUS_rstn ), + .m_axi_awid ( s_MBUS_clock_conv_to_dwidth_conv_axi_awid ), + .m_axi_awaddr ( s_MBUS_clock_conv_to_dwidth_conv_axi_awaddr ), + .m_axi_awlen ( s_MBUS_clock_conv_to_dwidth_conv_axi_awlen ), + .m_axi_awsize ( s_MBUS_clock_conv_to_dwidth_conv_axi_awsize ), + .m_axi_awburst ( s_MBUS_clock_conv_to_dwidth_conv_axi_awburst ), + .m_axi_awlock ( s_MBUS_clock_conv_to_dwidth_conv_axi_awlock ), + .m_axi_awcache ( s_MBUS_clock_conv_to_dwidth_conv_axi_awcache ), + .m_axi_awprot ( s_MBUS_clock_conv_to_dwidth_conv_axi_awprot ), + .m_axi_awregion ( s_MBUS_clock_conv_to_dwidth_conv_axi_awregion ), // Open + .m_axi_awqos ( s_MBUS_clock_conv_to_dwidth_conv_axi_awqos ), // Open + .m_axi_awvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_awvalid ), + .m_axi_awready ( s_MBUS_clock_conv_to_dwidth_conv_axi_awready ), + .m_axi_wdata ( s_MBUS_clock_conv_to_dwidth_conv_axi_wdata ), + .m_axi_wstrb ( s_MBUS_clock_conv_to_dwidth_conv_axi_wstrb ), + .m_axi_wlast ( s_MBUS_clock_conv_to_dwidth_conv_axi_wlast ), + .m_axi_wvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_wvalid ), + .m_axi_wready ( s_MBUS_clock_conv_to_dwidth_conv_axi_wready ), + .m_axi_bid ( s_MBUS_clock_conv_to_dwidth_conv_axi_bid ), + .m_axi_bresp ( s_MBUS_clock_conv_to_dwidth_conv_axi_bresp ), + .m_axi_bvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_bvalid ), + .m_axi_bready ( s_MBUS_clock_conv_to_dwidth_conv_axi_bready ), + .m_axi_arid ( s_MBUS_clock_conv_to_dwidth_conv_axi_arid ), + .m_axi_araddr ( s_MBUS_clock_conv_to_dwidth_conv_axi_araddr ), + .m_axi_arlen ( s_MBUS_clock_conv_to_dwidth_conv_axi_arlen ), + .m_axi_arsize ( s_MBUS_clock_conv_to_dwidth_conv_axi_arsize ), + .m_axi_arburst ( s_MBUS_clock_conv_to_dwidth_conv_axi_arburst ), + .m_axi_arlock ( s_MBUS_clock_conv_to_dwidth_conv_axi_arlock ), + .m_axi_arcache ( s_MBUS_clock_conv_to_dwidth_conv_axi_arcache ), + .m_axi_arprot ( s_MBUS_clock_conv_to_dwidth_conv_axi_arprot ), + .m_axi_arregion ( s_MBUS_clock_conv_to_dwidth_conv_axi_arregion ), // Open + .m_axi_arqos ( s_MBUS_clock_conv_to_dwidth_conv_axi_arqos ), // Open + .m_axi_arvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_arvalid ), + .m_axi_arready ( s_MBUS_clock_conv_to_dwidth_conv_axi_arready ), + .m_axi_rid ( s_MBUS_clock_conv_to_dwidth_conv_axi_rid ), + .m_axi_rdata ( s_MBUS_clock_conv_to_dwidth_conv_axi_rdata ), + .m_axi_rresp ( s_MBUS_clock_conv_to_dwidth_conv_axi_rresp ), + .m_axi_rlast ( s_MBUS_clock_conv_to_dwidth_conv_axi_rlast ), + .m_axi_rvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_rvalid ), + .m_axi_rready ( s_MBUS_clock_conv_to_dwidth_conv_axi_rready ) + ); + + // AXI dwith converter from 32 bit (global AXI data width) to 512 bit (AXI user interface HBUS data width) + // Tie-off undriven nets + // s_MBUS_clock_conv_to_dwidth_conv -> dwidth_conv_to_HBUS + xlnx_axi_dwidth_to512_converter axi_dwidth_conv_s_MBUS_u ( + .s_axi_aclk ( HBUS_clk ), + .s_axi_aresetn ( HBUS_rstn ), + // Slave from clock conv + .s_axi_awid ( s_MBUS_clock_conv_to_dwidth_conv_axi_awid ), + .s_axi_awaddr ( s_MBUS_clock_conv_to_dwidth_conv_axi_awaddr ), + .s_axi_awlen ( s_MBUS_clock_conv_to_dwidth_conv_axi_awlen ), + .s_axi_awsize ( s_MBUS_clock_conv_to_dwidth_conv_axi_awsize ), + .s_axi_awburst ( s_MBUS_clock_conv_to_dwidth_conv_axi_awburst ), + .s_axi_awvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_awvalid ), + .s_axi_awready ( s_MBUS_clock_conv_to_dwidth_conv_axi_awready ), + .s_axi_wdata ( s_MBUS_clock_conv_to_dwidth_conv_axi_wdata ), + .s_axi_wstrb ( s_MBUS_clock_conv_to_dwidth_conv_axi_wstrb ), + .s_axi_wlast ( s_MBUS_clock_conv_to_dwidth_conv_axi_wlast ), + .s_axi_wvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_wvalid ), + .s_axi_wready ( s_MBUS_clock_conv_to_dwidth_conv_axi_wready ), + .s_axi_bid ( s_MBUS_clock_conv_to_dwidth_conv_axi_bid ), + .s_axi_bresp ( s_MBUS_clock_conv_to_dwidth_conv_axi_bresp ), + .s_axi_bvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_bvalid ), + .s_axi_bready ( s_MBUS_clock_conv_to_dwidth_conv_axi_bready ), + .s_axi_arid ( s_MBUS_clock_conv_to_dwidth_conv_axi_arid ), + .s_axi_araddr ( s_MBUS_clock_conv_to_dwidth_conv_axi_araddr ), + .s_axi_arlen ( s_MBUS_clock_conv_to_dwidth_conv_axi_arlen ), + .s_axi_arsize ( s_MBUS_clock_conv_to_dwidth_conv_axi_arsize ), + .s_axi_arburst ( s_MBUS_clock_conv_to_dwidth_conv_axi_arburst ), + .s_axi_arvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_arvalid ), + .s_axi_arready ( s_MBUS_clock_conv_to_dwidth_conv_axi_arready ), + .s_axi_rid ( s_MBUS_clock_conv_to_dwidth_conv_axi_rid ), + .s_axi_rdata ( s_MBUS_clock_conv_to_dwidth_conv_axi_rdata ), + .s_axi_rresp ( s_MBUS_clock_conv_to_dwidth_conv_axi_rresp ), + .s_axi_rlast ( s_MBUS_clock_conv_to_dwidth_conv_axi_rlast ), + .s_axi_rvalid ( s_MBUS_clock_conv_to_dwidth_conv_axi_rvalid ), + .s_axi_rready ( s_MBUS_clock_conv_to_dwidth_conv_axi_rready ), + .s_axi_awlock ( s_MBUS_clock_conv_to_dwidth_conv_axi_awlock ), + .s_axi_awcache ( s_MBUS_clock_conv_to_dwidth_conv_axi_awcache ), + .s_axi_awprot ( s_MBUS_clock_conv_to_dwidth_conv_axi_awprot ), + .s_axi_awqos ( s_MBUS_clock_conv_to_dwidth_conv_axi_awqos ), + .s_axi_awregion ( s_MBUS_clock_conv_to_dwidth_conv_axi_awregion), + .s_axi_arlock ( s_MBUS_clock_conv_to_dwidth_conv_axi_arlock ), + .s_axi_arcache ( s_MBUS_clock_conv_to_dwidth_conv_axi_arcache ), + .s_axi_arprot ( s_MBUS_clock_conv_to_dwidth_conv_axi_arprot ), + .s_axi_arqos ( s_MBUS_clock_conv_to_dwidth_conv_axi_arqos ), + .s_axi_arregion ( s_MBUS_clock_conv_to_dwidth_conv_axi_arregion), + // Master to DDR + // .m_axi_awid ( dwidth_conv_to_HBUS_axi_awid ), + .m_axi_awaddr ( dwidth_conv_to_HBUS_axi_awaddr ), + .m_axi_awlen ( dwidth_conv_to_HBUS_axi_awlen ), + .m_axi_awsize ( dwidth_conv_to_HBUS_axi_awsize ), + .m_axi_awburst ( dwidth_conv_to_HBUS_axi_awburst ), + .m_axi_awlock ( dwidth_conv_to_HBUS_axi_awlock ), + .m_axi_awcache ( dwidth_conv_to_HBUS_axi_awcache ), + .m_axi_awprot ( dwidth_conv_to_HBUS_axi_awprot ), + .m_axi_awqos ( dwidth_conv_to_HBUS_axi_awqos ), + .m_axi_awvalid ( dwidth_conv_to_HBUS_axi_awvalid ), + .m_axi_awready ( dwidth_conv_to_HBUS_axi_awready ), + .m_axi_wdata ( dwidth_conv_to_HBUS_axi_wdata ), + .m_axi_wstrb ( dwidth_conv_to_HBUS_axi_wstrb ), + .m_axi_wlast ( dwidth_conv_to_HBUS_axi_wlast ), + .m_axi_wvalid ( dwidth_conv_to_HBUS_axi_wvalid ), + .m_axi_wready ( dwidth_conv_to_HBUS_axi_wready ), + // .m_axi_bid ( dwidth_conv_to_HBUS_axi_bid ), + .m_axi_bresp ( dwidth_conv_to_HBUS_axi_bresp ), + .m_axi_bvalid ( dwidth_conv_to_HBUS_axi_bvalid ), + .m_axi_bready ( dwidth_conv_to_HBUS_axi_bready ), + // .m_axi_arid ( dwidth_conv_to_HBUS_axi_arid ), + .m_axi_araddr ( dwidth_conv_to_HBUS_axi_araddr ), + .m_axi_arlen ( dwidth_conv_to_HBUS_axi_arlen ), + .m_axi_arsize ( dwidth_conv_to_HBUS_axi_arsize ), + .m_axi_arburst ( dwidth_conv_to_HBUS_axi_arburst ), + .m_axi_arlock ( dwidth_conv_to_HBUS_axi_arlock ), + .m_axi_arcache ( dwidth_conv_to_HBUS_axi_arcache ), + .m_axi_arprot ( dwidth_conv_to_HBUS_axi_arprot ), + .m_axi_arqos ( dwidth_conv_to_HBUS_axi_arqos ), + .m_axi_arvalid ( dwidth_conv_to_HBUS_axi_arvalid ), + .m_axi_arready ( dwidth_conv_to_HBUS_axi_arready ), + // .m_axi_rid ( dwidth_conv_to_HBUS_axi_rid ), + .m_axi_rdata ( dwidth_conv_to_HBUS_axi_rdata ), + .m_axi_rresp ( dwidth_conv_to_HBUS_axi_rresp ), + .m_axi_rlast ( dwidth_conv_to_HBUS_axi_rlast ), + .m_axi_rvalid ( dwidth_conv_to_HBUS_axi_rvalid ), + .m_axi_rready ( dwidth_conv_to_HBUS_axi_rready ), + // Unconnected nets + .m_axi_awregion ( dwidth_conv_to_HBUS_axi_awregion ), + .m_axi_arregion ( dwidth_conv_to_HBUS_axi_arregion ) + ); + + // AXI dwith converter from 32 bit (global AXI data width) to 512 bit (AXI user interface HBUS data width) + // dwidth_conv_from_HBUS -> m_MBUS_dwidth_conv_to_clock_conv + xlnx_axi_dwidth_from512_converter axi_dwidth_conv_m_MBUS_u ( + // Clock and reset + .s_axi_aclk ( HBUS_clk ), + .s_axi_aresetn ( HBUS_rstn ), + + // Slave from clock conv + .s_axi_awid ( dwidth_conv_from_HBUS_axi_awid ), + .s_axi_awaddr ( dwidth_conv_from_HBUS_axi_awaddr ), + .s_axi_awlen ( dwidth_conv_from_HBUS_axi_awlen ), + .s_axi_awsize ( dwidth_conv_from_HBUS_axi_awsize ), + .s_axi_awburst ( dwidth_conv_from_HBUS_axi_awburst ), + .s_axi_awvalid ( dwidth_conv_from_HBUS_axi_awvalid ), + .s_axi_awready ( dwidth_conv_from_HBUS_axi_awready ), + .s_axi_wdata ( dwidth_conv_from_HBUS_axi_wdata ), + .s_axi_wstrb ( dwidth_conv_from_HBUS_axi_wstrb ), + .s_axi_wlast ( dwidth_conv_from_HBUS_axi_wlast ), + .s_axi_wvalid ( dwidth_conv_from_HBUS_axi_wvalid ), + .s_axi_wready ( dwidth_conv_from_HBUS_axi_wready ), + .s_axi_bid ( dwidth_conv_from_HBUS_axi_bid ), + .s_axi_bresp ( dwidth_conv_from_HBUS_axi_bresp ), + .s_axi_bvalid ( dwidth_conv_from_HBUS_axi_bvalid ), + .s_axi_bready ( dwidth_conv_from_HBUS_axi_bready ), + .s_axi_arid ( dwidth_conv_from_HBUS_axi_arid ), + .s_axi_araddr ( dwidth_conv_from_HBUS_axi_araddr ), + .s_axi_arlen ( dwidth_conv_from_HBUS_axi_arlen ), + .s_axi_arsize ( dwidth_conv_from_HBUS_axi_arsize ), + .s_axi_arburst ( dwidth_conv_from_HBUS_axi_arburst ), + .s_axi_arvalid ( dwidth_conv_from_HBUS_axi_arvalid ), + .s_axi_arready ( dwidth_conv_from_HBUS_axi_arready ), + .s_axi_rid ( dwidth_conv_from_HBUS_axi_rid ), + .s_axi_rdata ( dwidth_conv_from_HBUS_axi_rdata ), + .s_axi_rresp ( dwidth_conv_from_HBUS_axi_rresp ), + .s_axi_rlast ( dwidth_conv_from_HBUS_axi_rlast ), + .s_axi_rvalid ( dwidth_conv_from_HBUS_axi_rvalid ), + .s_axi_rready ( dwidth_conv_from_HBUS_axi_rready ), + .s_axi_awlock ( dwidth_conv_from_HBUS_axi_awlock ), + .s_axi_awcache ( dwidth_conv_from_HBUS_axi_awcache ), + .s_axi_awprot ( dwidth_conv_from_HBUS_axi_awprot ), + .s_axi_awqos ( dwidth_conv_from_HBUS_axi_awqos ), + .s_axi_awregion ( dwidth_conv_from_HBUS_axi_awregion), + .s_axi_arlock ( dwidth_conv_from_HBUS_axi_arlock ), + .s_axi_arcache ( dwidth_conv_from_HBUS_axi_arcache ), // Open + .s_axi_arprot ( dwidth_conv_from_HBUS_axi_arprot ), // Open + .s_axi_arqos ( dwidth_conv_from_HBUS_axi_arqos ), // Open + .s_axi_arregion ( dwidth_conv_from_HBUS_axi_arregion), // Open + // Master + // .m_axi_awid ( m_MBUS_dwidth_conv_to_clock_conv_axi_awid ), + .m_axi_awaddr ( m_MBUS_dwidth_conv_to_clock_conv_axi_awaddr ), + .m_axi_awlen ( m_MBUS_dwidth_conv_to_clock_conv_axi_awlen ), + .m_axi_awsize ( m_MBUS_dwidth_conv_to_clock_conv_axi_awsize ), + .m_axi_awburst ( m_MBUS_dwidth_conv_to_clock_conv_axi_awburst ), + .m_axi_awlock ( m_MBUS_dwidth_conv_to_clock_conv_axi_awlock ), + .m_axi_awcache ( m_MBUS_dwidth_conv_to_clock_conv_axi_awcache ), + .m_axi_awprot ( m_MBUS_dwidth_conv_to_clock_conv_axi_awprot ), + .m_axi_awqos ( m_MBUS_dwidth_conv_to_clock_conv_axi_awqos ), + .m_axi_awvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_awvalid ), + .m_axi_awready ( m_MBUS_dwidth_conv_to_clock_conv_axi_awready ), + .m_axi_wdata ( m_MBUS_dwidth_conv_to_clock_conv_axi_wdata ), + .m_axi_wstrb ( m_MBUS_dwidth_conv_to_clock_conv_axi_wstrb ), + .m_axi_wlast ( m_MBUS_dwidth_conv_to_clock_conv_axi_wlast ), + .m_axi_wvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_wvalid ), + .m_axi_wready ( m_MBUS_dwidth_conv_to_clock_conv_axi_wready ), + // .m_axi_bid ( m_MBUS_dwidth_conv_to_clock_conv_axi_bid ), + .m_axi_bresp ( m_MBUS_dwidth_conv_to_clock_conv_axi_bresp ), + .m_axi_bvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_bvalid ), + .m_axi_bready ( m_MBUS_dwidth_conv_to_clock_conv_axi_bready ), + // .m_axi_arid ( m_MBUS_dwidth_conv_to_clock_conv_axi_arid ), + .m_axi_araddr ( m_MBUS_dwidth_conv_to_clock_conv_axi_araddr ), + .m_axi_arlen ( m_MBUS_dwidth_conv_to_clock_conv_axi_arlen ), + .m_axi_arsize ( m_MBUS_dwidth_conv_to_clock_conv_axi_arsize ), + .m_axi_arburst ( m_MBUS_dwidth_conv_to_clock_conv_axi_arburst ), + .m_axi_arlock ( m_MBUS_dwidth_conv_to_clock_conv_axi_arlock ), + .m_axi_arcache ( m_MBUS_dwidth_conv_to_clock_conv_axi_arcache ), + .m_axi_arprot ( m_MBUS_dwidth_conv_to_clock_conv_axi_arprot ), + .m_axi_arqos ( m_MBUS_dwidth_conv_to_clock_conv_axi_arqos ), + .m_axi_arvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_arvalid ), + .m_axi_arready ( m_MBUS_dwidth_conv_to_clock_conv_axi_arready ), + // .m_axi_rid ( m_MBUS_dwidth_conv_to_clock_conv_axi_rid ), + .m_axi_rdata ( m_MBUS_dwidth_conv_to_clock_conv_axi_rdata ), + .m_axi_rresp ( m_MBUS_dwidth_conv_to_clock_conv_axi_rresp ), + .m_axi_rlast ( m_MBUS_dwidth_conv_to_clock_conv_axi_rlast ), + .m_axi_rvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_rvalid ), + .m_axi_rready ( m_MBUS_dwidth_conv_to_clock_conv_axi_rready ), + // Unconnected nets + .m_axi_awregion ( m_MBUS_dwidth_conv_to_clock_conv_axi_awregion ), + .m_axi_arregion ( m_MBUS_dwidth_conv_to_clock_conv_axi_arregion ) + ); + + // Clock converter + // s_MBUS_clock_conv_to_dwidth_conv -> m_MBUS + axi_clock_converter_wrapper # ( + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ) + ) xlnx_axi_clock_converter_m_MBUS_u ( + // Slave from BUS + .s_axi_aclk ( HBUS_clk ), + .s_axi_aresetn ( HBUS_rstn ), + .s_axi_awid ( m_MBUS_dwidth_conv_to_clock_conv_axi_awid ), + .s_axi_awaddr ( m_MBUS_dwidth_conv_to_clock_conv_axi_awaddr ), + .s_axi_awlen ( m_MBUS_dwidth_conv_to_clock_conv_axi_awlen ), + .s_axi_awsize ( m_MBUS_dwidth_conv_to_clock_conv_axi_awsize ), + .s_axi_awburst ( m_MBUS_dwidth_conv_to_clock_conv_axi_awburst ), + .s_axi_awlock ( m_MBUS_dwidth_conv_to_clock_conv_axi_awlock ), + .s_axi_awcache ( m_MBUS_dwidth_conv_to_clock_conv_axi_awcache ), + .s_axi_awprot ( m_MBUS_dwidth_conv_to_clock_conv_axi_awprot ), + .s_axi_awqos ( m_MBUS_dwidth_conv_to_clock_conv_axi_awqos ), + .s_axi_awvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_awvalid ), + .s_axi_awready ( m_MBUS_dwidth_conv_to_clock_conv_axi_awready ), + .s_axi_awregion ( m_MBUS_dwidth_conv_to_clock_conv_axi_awregion ), + .s_axi_wdata ( m_MBUS_dwidth_conv_to_clock_conv_axi_wdata ), + .s_axi_wstrb ( m_MBUS_dwidth_conv_to_clock_conv_axi_wstrb ), + .s_axi_wlast ( m_MBUS_dwidth_conv_to_clock_conv_axi_wlast ), + .s_axi_wvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_wvalid ), + .s_axi_wready ( m_MBUS_dwidth_conv_to_clock_conv_axi_wready ), + .s_axi_bid ( m_MBUS_dwidth_conv_to_clock_conv_axi_bid ), + .s_axi_bresp ( m_MBUS_dwidth_conv_to_clock_conv_axi_bresp ), + .s_axi_bvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_bvalid ), + .s_axi_bready ( m_MBUS_dwidth_conv_to_clock_conv_axi_bready ), + .s_axi_arid ( m_MBUS_dwidth_conv_to_clock_conv_axi_arid ), + .s_axi_araddr ( m_MBUS_dwidth_conv_to_clock_conv_axi_araddr ), + .s_axi_arlen ( m_MBUS_dwidth_conv_to_clock_conv_axi_arlen ), + .s_axi_arsize ( m_MBUS_dwidth_conv_to_clock_conv_axi_arsize ), + .s_axi_arburst ( m_MBUS_dwidth_conv_to_clock_conv_axi_arburst ), + .s_axi_arlock ( m_MBUS_dwidth_conv_to_clock_conv_axi_arlock ), + .s_axi_arregion ( m_MBUS_dwidth_conv_to_clock_conv_axi_arregion ), + .s_axi_arcache ( m_MBUS_dwidth_conv_to_clock_conv_axi_arcache ), + .s_axi_arprot ( m_MBUS_dwidth_conv_to_clock_conv_axi_arprot ), + .s_axi_arqos ( m_MBUS_dwidth_conv_to_clock_conv_axi_arqos ), + .s_axi_arvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_arvalid ), + .s_axi_arready ( m_MBUS_dwidth_conv_to_clock_conv_axi_arready ), + .s_axi_rid ( m_MBUS_dwidth_conv_to_clock_conv_axi_rid ), + .s_axi_rdata ( m_MBUS_dwidth_conv_to_clock_conv_axi_rdata ), + .s_axi_rresp ( m_MBUS_dwidth_conv_to_clock_conv_axi_rresp ), + .s_axi_rlast ( m_MBUS_dwidth_conv_to_clock_conv_axi_rlast ), + .s_axi_rvalid ( m_MBUS_dwidth_conv_to_clock_conv_axi_rvalid ), + .s_axi_rready ( m_MBUS_dwidth_conv_to_clock_conv_axi_rready ), + + // Master to MBUS + .m_axi_aclk ( main_clock_i ), + .m_axi_aresetn ( main_reset_ni ), + .m_axi_awid ( m_MBUS_axi_awid ), + .m_axi_awaddr ( m_MBUS_axi_awaddr ), + .m_axi_awlen ( m_MBUS_axi_awlen ), + .m_axi_awsize ( m_MBUS_axi_awsize ), + .m_axi_awburst ( m_MBUS_axi_awburst ), + .m_axi_awlock ( m_MBUS_axi_awlock ), + .m_axi_awcache ( m_MBUS_axi_awcache ), + .m_axi_awprot ( m_MBUS_axi_awprot ), + .m_axi_awregion ( m_MBUS_axi_awregion ), + .m_axi_awqos ( m_MBUS_axi_awqos ), + .m_axi_awvalid ( m_MBUS_axi_awvalid ), + .m_axi_awready ( m_MBUS_axi_awready ), + .m_axi_wdata ( m_MBUS_axi_wdata ), + .m_axi_wstrb ( m_MBUS_axi_wstrb ), + .m_axi_wlast ( m_MBUS_axi_wlast ), + .m_axi_wvalid ( m_MBUS_axi_wvalid ), + .m_axi_wready ( m_MBUS_axi_wready ), + .m_axi_bid ( m_MBUS_axi_bid ), + .m_axi_bresp ( m_MBUS_axi_bresp ), + .m_axi_bvalid ( m_MBUS_axi_bvalid ), + .m_axi_bready ( m_MBUS_axi_bready ), + .m_axi_arid ( m_MBUS_axi_arid ), + .m_axi_araddr ( m_MBUS_axi_araddr ), + .m_axi_arlen ( m_MBUS_axi_arlen ), + .m_axi_arsize ( m_MBUS_axi_arsize ), + .m_axi_arburst ( m_MBUS_axi_arburst ), + .m_axi_arlock ( m_MBUS_axi_arlock ), + .m_axi_arcache ( m_MBUS_axi_arcache ), + .m_axi_arprot ( m_MBUS_axi_arprot ), + .m_axi_arregion ( m_MBUS_axi_arregion ), + .m_axi_arqos ( m_MBUS_axi_arqos ), + .m_axi_arvalid ( m_MBUS_axi_arvalid ), + .m_axi_arready ( m_MBUS_axi_arready ), + .m_axi_rid ( m_MBUS_axi_rid ), + .m_axi_rdata ( m_MBUS_axi_rdata ), + .m_axi_rresp ( m_MBUS_axi_rresp ), + .m_axi_rlast ( m_MBUS_axi_rlast ), + .m_axi_rvalid ( m_MBUS_axi_rvalid ), + .m_axi_rready ( m_MBUS_axi_rready ) + ); + + /////////////////// + // AXI4 Crossbar // + /////////////////// + + // Connnect to config-generated buses + `ASSIGN_AXI_BUS(s_acc_to_HBUS, s_acc) + `ASSIGN_AXI_BUS(MBUS_to_HBUS, dwidth_conv_to_HBUS) + `ASSIGN_AXI_BUS(dwidth_conv_from_HBUS, HBUS_to_MBUS) + + // AXI4 crossbar + xlnx_highperformance_crossbar highperformance_xbar_u ( + .aclk ( HBUS_clk ), + .aresetn ( HBUS_rstn ), + .s_axi_awid ( HBUS_masters_axi_awid ), // input + .s_axi_awaddr ( HBUS_masters_axi_awaddr ), // input + .s_axi_awlen ( HBUS_masters_axi_awlen ), // input + .s_axi_awsize ( HBUS_masters_axi_awsize ), // input + .s_axi_awburst ( HBUS_masters_axi_awburst ), // input + .s_axi_awlock ( HBUS_masters_axi_awlock ), // input + .s_axi_awcache ( HBUS_masters_axi_awcache ), // input + .s_axi_awprot ( HBUS_masters_axi_awprot ), // input + .s_axi_awqos ( HBUS_masters_axi_awqos ), // input + .s_axi_awvalid ( HBUS_masters_axi_awvalid ), // input + .s_axi_awready ( HBUS_masters_axi_awready ), // output + .s_axi_wdata ( HBUS_masters_axi_wdata ), // input + .s_axi_wstrb ( HBUS_masters_axi_wstrb ), // input + .s_axi_wlast ( HBUS_masters_axi_wlast ), // input + .s_axi_wvalid ( HBUS_masters_axi_wvalid ), // input + .s_axi_wready ( HBUS_masters_axi_wready ), // output + .s_axi_bid ( HBUS_masters_axi_bid ), // output + .s_axi_bresp ( HBUS_masters_axi_bresp ), // output + .s_axi_bvalid ( HBUS_masters_axi_bvalid ), // output + .s_axi_bready ( HBUS_masters_axi_bready ), // input + .s_axi_arid ( HBUS_masters_axi_arid ), // output + .s_axi_araddr ( HBUS_masters_axi_araddr ), // input + .s_axi_arlen ( HBUS_masters_axi_arlen ), // input + .s_axi_arsize ( HBUS_masters_axi_arsize ), // input + .s_axi_arburst ( HBUS_masters_axi_arburst ), // input + .s_axi_arlock ( HBUS_masters_axi_arlock ), // input + .s_axi_arcache ( HBUS_masters_axi_arcache ), // input + .s_axi_arprot ( HBUS_masters_axi_arprot ), // input + .s_axi_arqos ( HBUS_masters_axi_arqos ), // input + .s_axi_arvalid ( HBUS_masters_axi_arvalid ), // input + .s_axi_arready ( HBUS_masters_axi_arready ), // output + .s_axi_rid ( HBUS_masters_axi_rid ), // output + .s_axi_rdata ( HBUS_masters_axi_rdata ), // output + .s_axi_rresp ( HBUS_masters_axi_rresp ), // output + .s_axi_rlast ( HBUS_masters_axi_rlast ), // output + .s_axi_rvalid ( HBUS_masters_axi_rvalid ), // output + .s_axi_rready ( HBUS_masters_axi_rready ), // input + .m_axi_awid ( HBUS_slaves_axi_awid ), // output + .m_axi_awaddr ( HBUS_slaves_axi_awaddr ), // output + .m_axi_awlen ( HBUS_slaves_axi_awlen ), // output + .m_axi_awsize ( HBUS_slaves_axi_awsize ), // output + .m_axi_awburst ( HBUS_slaves_axi_awburst ), // output + .m_axi_awlock ( HBUS_slaves_axi_awlock ), // output + .m_axi_awcache ( HBUS_slaves_axi_awcache ), // output + .m_axi_awprot ( HBUS_slaves_axi_awprot ), // output + .m_axi_awregion ( HBUS_slaves_axi_awregion ), // output + .m_axi_awqos ( HBUS_slaves_axi_awqos ), // output + .m_axi_awvalid ( HBUS_slaves_axi_awvalid ), // output + .m_axi_awready ( HBUS_slaves_axi_awready ), // input + .m_axi_wdata ( HBUS_slaves_axi_wdata ), // output + .m_axi_wstrb ( HBUS_slaves_axi_wstrb ), // output + .m_axi_wlast ( HBUS_slaves_axi_wlast ), // output + .m_axi_wvalid ( HBUS_slaves_axi_wvalid ), // output + .m_axi_wready ( HBUS_slaves_axi_wready ), // input + .m_axi_bid ( HBUS_slaves_axi_bid ), // input + .m_axi_bresp ( HBUS_slaves_axi_bresp ), // input + .m_axi_bvalid ( HBUS_slaves_axi_bvalid ), // input + .m_axi_bready ( HBUS_slaves_axi_bready ), // output + .m_axi_arid ( HBUS_slaves_axi_arid ), // output + .m_axi_araddr ( HBUS_slaves_axi_araddr ), // output + .m_axi_arlen ( HBUS_slaves_axi_arlen ), // output + .m_axi_arsize ( HBUS_slaves_axi_arsize ), // output + .m_axi_arburst ( HBUS_slaves_axi_arburst ), // output + .m_axi_arlock ( HBUS_slaves_axi_arlock ), // output + .m_axi_arcache ( HBUS_slaves_axi_arcache ), // output + .m_axi_arprot ( HBUS_slaves_axi_arprot ), // output + .m_axi_arregion ( HBUS_slaves_axi_arregion ), // output + .m_axi_arqos ( HBUS_slaves_axi_arqos ), // output + .m_axi_arvalid ( HBUS_slaves_axi_arvalid ), // output + .m_axi_arready ( HBUS_slaves_axi_arready ), // input + .m_axi_rid ( HBUS_slaves_axi_rid ), // input + .m_axi_rdata ( HBUS_slaves_axi_rdata ), // input + .m_axi_rresp ( HBUS_slaves_axi_rresp ), // input + .m_axi_rlast ( HBUS_slaves_axi_rlast ), // input + .m_axi_rvalid ( HBUS_slaves_axi_rvalid ), // input + .m_axi_rready ( HBUS_slaves_axi_rready ) // output + ); + + + ///////////////// + // AXI4 Slaves // + ///////////////// + + // TODO: this is just a single DDR4 channel for now + // TODO: generate over NUM_DDR_CHANNELS + // TODO: integrate HBM a well and generate over NUM_HBM_CHANNELS + + // Synch DDR4 sys reset - it is active high + logic ddr4_reset = 1'b1; + always @(posedge main_clock_i or negedge main_reset_ni) begin + if (main_reset_ni == 1'b0) begin + ddr4_reset <= 1'b1; + end else begin + ddr4_reset <= 1'b0; + end + end + + // Tie-off floaintg nets + assign dwidth_conv_to_HBUS_axi_arid = '0; + // assign dwidth_conv_to_HBUS_axi_arregion = '0; + assign dwidth_conv_to_HBUS_axi_awid = '0; + // assign dwidth_conv_to_HBUS_axi_awregion = '0; + assign m_MBUS_dwidth_conv_to_clock_conv_axi_arid = '0; + // assign m_MBUS_dwidth_conv_to_clock_conv_axi_arregion = '0; + assign m_MBUS_dwidth_conv_to_clock_conv_axi_awid = '0; + // assign m_MBUS_dwidth_conv_to_clock_conv_axi_awregion = '0; + + // DDR4 Channel 0 + xlnx_ddr4 ddr4_u ( + .c0_sys_clk_n ( clk_300mhz_x_n_i ), + .c0_sys_clk_p ( clk_300mhz_x_p_i ), + + .sys_rst ( ddr4_reset ), + + // Output - Calibration complete, the memory controller waits for this + .c0_init_calib_complete ( /* empty */ ), + // Output - Interrupt about ECC + .c0_ddr4_interrupt ( /* empty */ ), + // Output - these two debug ports must be open, in the implementation phase Vivado connects these two properly + .dbg_clk ( /* empty */ ), + .dbg_bus ( /* empty */ ), + + // DDR4 interface - to the physical memory + .c0_ddr4_adr ( cx_ddr4_adr ), + .c0_ddr4_ba ( cx_ddr4_ba ), + .c0_ddr4_cke ( cx_ddr4_cke ), + .c0_ddr4_cs_n ( cx_ddr4_cs_n ), + .c0_ddr4_dq ( cx_ddr4_dq ), + .c0_ddr4_dqs_t ( cx_ddr4_dqs_t ), + .c0_ddr4_dqs_c ( cx_ddr4_dqs_c ), + .c0_ddr4_odt ( cx_ddr4_odt ), + .c0_ddr4_parity ( cx_ddr4_parity ), + .c0_ddr4_bg ( cx_ddr4_bg ), + .c0_ddr4_reset_n ( cx_ddr4_reset_n ), + .c0_ddr4_act_n ( cx_ddr4_act_n ), + .c0_ddr4_ck_t ( cx_ddr4_ck_t ), + .c0_ddr4_ck_c ( cx_ddr4_ck_c ), + + .c0_ddr4_ui_clk ( ddr_clk ), + .c0_ddr4_ui_clk_sync_rst ( ddr_rst ), + + .c0_ddr4_aresetn ( ~ddr_rst ), // Feed-back as AXI reset + + // AXILITE interface - for status and control + .c0_ddr4_s_axi_ctrl_awvalid ( s_ctrl_axilite_awvalid ), + .c0_ddr4_s_axi_ctrl_awready ( s_ctrl_axilite_awready ), + .c0_ddr4_s_axi_ctrl_awaddr ( s_ctrl_axilite_awaddr ), + .c0_ddr4_s_axi_ctrl_wvalid ( s_ctrl_axilite_wvalid ), + .c0_ddr4_s_axi_ctrl_wready ( s_ctrl_axilite_wready ), + .c0_ddr4_s_axi_ctrl_wdata ( s_ctrl_axilite_wdata ), + .c0_ddr4_s_axi_ctrl_bvalid ( s_ctrl_axilite_bvalid ), + .c0_ddr4_s_axi_ctrl_bready ( s_ctrl_axilite_bready ), + .c0_ddr4_s_axi_ctrl_bresp ( s_ctrl_axilite_bresp ), + .c0_ddr4_s_axi_ctrl_arvalid ( s_ctrl_axilite_arvalid ), + .c0_ddr4_s_axi_ctrl_arready ( s_ctrl_axilite_arready ), + .c0_ddr4_s_axi_ctrl_araddr ( s_ctrl_axilite_araddr ), + .c0_ddr4_s_axi_ctrl_rvalid ( s_ctrl_axilite_rvalid ), + .c0_ddr4_s_axi_ctrl_rready ( s_ctrl_axilite_rready ), + .c0_ddr4_s_axi_ctrl_rdata ( s_ctrl_axilite_rdata ), + .c0_ddr4_s_axi_ctrl_rresp ( s_ctrl_axilite_rresp ), + // .c0_ddr4_s_axi_ctrl_arprot ( s_ctrl_axilite_arprot ), // Ports not implemented + // .c0_ddr4_s_axi_ctrl_awprot ( s_ctrl_axilite_awprot ), // Ports not implemented + // .c0_ddr4_s_axi_ctrl_wstrb ( s_ctrl_axilite_wstrb ), // Ports not implemented + + + // AXI4 interface + .c0_ddr4_s_axi_awid ( HBUS_to_DDR4CH0_axi_awid ), + .c0_ddr4_s_axi_awaddr ( { 2'b00, HBUS_to_DDR4CH0_axi_awaddr } ), // 34 bits + .c0_ddr4_s_axi_awlen ( HBUS_to_DDR4CH0_axi_awlen ), + .c0_ddr4_s_axi_awsize ( HBUS_to_DDR4CH0_axi_awsize ), + .c0_ddr4_s_axi_awburst ( HBUS_to_DDR4CH0_axi_awburst ), + .c0_ddr4_s_axi_awlock ( HBUS_to_DDR4CH0_axi_awlock ), + .c0_ddr4_s_axi_awcache ( HBUS_to_DDR4CH0_axi_awcache ), + .c0_ddr4_s_axi_awprot ( HBUS_to_DDR4CH0_axi_awprot ), + .c0_ddr4_s_axi_awqos ( HBUS_to_DDR4CH0_axi_awqos ), + .c0_ddr4_s_axi_awvalid ( HBUS_to_DDR4CH0_axi_awvalid ), + .c0_ddr4_s_axi_awready ( HBUS_to_DDR4CH0_axi_awready ), + .c0_ddr4_s_axi_wdata ( HBUS_to_DDR4CH0_axi_wdata ), + .c0_ddr4_s_axi_wstrb ( HBUS_to_DDR4CH0_axi_wstrb ), + .c0_ddr4_s_axi_wlast ( HBUS_to_DDR4CH0_axi_wlast ), + .c0_ddr4_s_axi_wvalid ( HBUS_to_DDR4CH0_axi_wvalid ), + .c0_ddr4_s_axi_wready ( HBUS_to_DDR4CH0_axi_wready ), + .c0_ddr4_s_axi_bready ( HBUS_to_DDR4CH0_axi_bready ), + .c0_ddr4_s_axi_bid ( HBUS_to_DDR4CH0_axi_bid ), + .c0_ddr4_s_axi_bresp ( HBUS_to_DDR4CH0_axi_bresp ), + .c0_ddr4_s_axi_bvalid ( HBUS_to_DDR4CH0_axi_bvalid ), + .c0_ddr4_s_axi_arid ( HBUS_to_DDR4CH0_axi_arid ), + .c0_ddr4_s_axi_araddr ( { 2'b00, HBUS_to_DDR4CH0_axi_araddr } ), // 34 bits + .c0_ddr4_s_axi_arlen ( HBUS_to_DDR4CH0_axi_arlen ), + .c0_ddr4_s_axi_arsize ( HBUS_to_DDR4CH0_axi_arsize ), + .c0_ddr4_s_axi_arburst ( HBUS_to_DDR4CH0_axi_arburst ), + .c0_ddr4_s_axi_arlock ( HBUS_to_DDR4CH0_axi_arlock ), + .c0_ddr4_s_axi_arcache ( HBUS_to_DDR4CH0_axi_arcache ), + .c0_ddr4_s_axi_arprot ( HBUS_to_DDR4CH0_axi_arprot ), + .c0_ddr4_s_axi_arqos ( HBUS_to_DDR4CH0_axi_arqos ), + .c0_ddr4_s_axi_arvalid ( HBUS_to_DDR4CH0_axi_arvalid ), + .c0_ddr4_s_axi_arready ( HBUS_to_DDR4CH0_axi_arready ), + .c0_ddr4_s_axi_rready ( HBUS_to_DDR4CH0_axi_rready ), + .c0_ddr4_s_axi_rlast ( HBUS_to_DDR4CH0_axi_rlast ), + .c0_ddr4_s_axi_rvalid ( HBUS_to_DDR4CH0_axi_rvalid ), + .c0_ddr4_s_axi_rresp ( HBUS_to_DDR4CH0_axi_rresp ), + .c0_ddr4_s_axi_rid ( HBUS_to_DDR4CH0_axi_rid ), + .c0_ddr4_s_axi_rdata ( HBUS_to_DDR4CH0_axi_rdata ) + ); + +endmodule : highperformance_bus diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/hls_conv2d_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/hls_conv2d_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..a3f55fd0f5c2a2f36556b1612d01bb8da8ff876b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/hls_conv2d_wrapper.sv @@ -0,0 +1,433 @@ +// Author: Vincenzo Maisto +// Description: +// Wrapper module for HLS CONV2D IP with clock bridges an AXI adapters. +// Note: +// This is static for now, but could be extended to a generic shell for HLS IP, with CDC support, multiple interfaces, etc. +// +// Architecture: HLS IP integration (with CDC) +// ____________________________ +// | | +// | axi_clock_converter_u |<-------------------- HLS_CONTROL (from MBUS) +// |____________________________| +// | +// | sync_HLS_CONTROL (HBUS clock domain) +// ____V_________________ +// | | +// | axi_dwidth_conv_u | +// | (XLEN == 64) | +// |______________________| +// | +// | d32_HLS_CONTROL (HBUS clock domain) +// ____v_______________________ +// | | +// | xlnx_axi4_to_axilite_u | +// |____________________________| +// | +// | HLS_CONTROL_axilite +// | ________ +// | | | HLS_gmem0_d512 +// \------->| |------------------------------------> HLS_gmem0_d512 (to HBUS) +// | HLS IP | ______________ +// | | interrupt | | (MBUS clock domain) +// | |----------------->| synchronizer |--> to PLIC +// |________| |______________| +// + +module hls_conv2d_wrapper # ( + // MBUS parameters + parameter MBUS_ADDR_WIDTH = 32, + parameter MBUS_DATA_WIDTH = 32, + parameter MBUS_ID_WIDTH = 4, + // HBUS parameters + parameter HBUS_DATA_WIDTH = 512, + parameter HBUS_ADDR_WIDTH = 32, + parameter HBUS_ID_WIDTH = 4 +) ( + // MBUS clock and reset + input logic main_clk_i, + input logic main_rstn_i, + + // HLS IP clock and reset (from HBUS) + input logic HLS_CONTROL_clk_i, + input logic HLS_CONTROL_rstn_i, + + // Slave for control + `DEFINE_AXI_SLAVE_PORTS(s_HLS_CONTROL, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH), + + // Master to HBUS + `DEFINE_AXI_MASTER_PORTS(m_HLS_gmem0_d512, HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH), + + // Interrupt + output logic hls_interrupt_o + +); + + ////////////////// + // Declarations // + ////////////////// + + // HLS interrupt line (not synchronized to MBUS) + logic hls_interrupt_async; + + // axi_clock_converter_u -> axi_dwidth_conv_u + `DECLARE_AXI_BUS(sync_HLS_CONTROL, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH); + + // axi_dwidth_conv_u -> xlnx_axi4_to_axilite_u + localparam int unsigned HLS_DATA_WIDTH = 32; + localparam int unsigned HLS_ADDR_WIDTH = 32; // NOTE: this is goig to clip + localparam int unsigned HLS_ID_WIDTH = MBUS_ID_WIDTH; + `DECLARE_AXI_BUS(to_prot_conv, HLS_DATA_WIDTH, HLS_ADDR_WIDTH, MBUS_ID_WIDTH); + + // HLS_DOTPROD_CONTROL AXI-lite + // xlnx_axi4_to_axilite_u -> custom_hls_conv_hbus_u + `DECLARE_AXILITE_BUS(HLS_CONTROL, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH); + + ///////////// + // Modules // + ///////////// + + // Add clock bridges for HLS_CONTROL + `ifdef HLS_CONTROL_HAS_CLOCK_DOMAIN + // s_HLS_CONTROL -> sync_HLS_CONTROL + axi_clock_converter_wrapper # ( + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ) + ) axi_clock_converter_u ( + // AXI4 Slave from MBUS + .s_axi_aclk ( main_clk_i ), + .s_axi_aresetn ( main_rstn_i ), + .s_axi_awid ( s_HLS_CONTROL_axi_awid ), + .s_axi_awaddr ( s_HLS_CONTROL_axi_awaddr ), + .s_axi_awlen ( s_HLS_CONTROL_axi_awlen ), + .s_axi_awsize ( s_HLS_CONTROL_axi_awsize ), + .s_axi_awburst ( s_HLS_CONTROL_axi_awburst ), + .s_axi_awlock ( s_HLS_CONTROL_axi_awlock ), + .s_axi_awcache ( s_HLS_CONTROL_axi_awcache ), + .s_axi_awprot ( s_HLS_CONTROL_axi_awprot ), + .s_axi_awqos ( s_HLS_CONTROL_axi_awqos ), + .s_axi_awvalid ( s_HLS_CONTROL_axi_awvalid ), + .s_axi_awready ( s_HLS_CONTROL_axi_awready ), + .s_axi_awregion ( s_HLS_CONTROL_axi_awregion ), + .s_axi_wdata ( s_HLS_CONTROL_axi_wdata ), + .s_axi_wstrb ( s_HLS_CONTROL_axi_wstrb ), + .s_axi_wlast ( s_HLS_CONTROL_axi_wlast ), + .s_axi_wvalid ( s_HLS_CONTROL_axi_wvalid ), + .s_axi_wready ( s_HLS_CONTROL_axi_wready ), + .s_axi_bid ( s_HLS_CONTROL_axi_bid ), + .s_axi_bresp ( s_HLS_CONTROL_axi_bresp ), + .s_axi_bvalid ( s_HLS_CONTROL_axi_bvalid ), + .s_axi_bready ( s_HLS_CONTROL_axi_bready ), + .s_axi_arid ( s_HLS_CONTROL_axi_arid ), + .s_axi_araddr ( s_HLS_CONTROL_axi_araddr ), + .s_axi_arlen ( s_HLS_CONTROL_axi_arlen ), + .s_axi_arsize ( s_HLS_CONTROL_axi_arsize ), + .s_axi_arburst ( s_HLS_CONTROL_axi_arburst ), + .s_axi_arlock ( s_HLS_CONTROL_axi_arlock ), + .s_axi_arregion ( s_HLS_CONTROL_axi_arregion ), + .s_axi_arcache ( s_HLS_CONTROL_axi_arcache ), + .s_axi_arprot ( s_HLS_CONTROL_axi_arprot ), + .s_axi_arqos ( s_HLS_CONTROL_axi_arqos ), + .s_axi_arvalid ( s_HLS_CONTROL_axi_arvalid ), + .s_axi_arready ( s_HLS_CONTROL_axi_arready ), + .s_axi_rid ( s_HLS_CONTROL_axi_rid ), + .s_axi_rdata ( s_HLS_CONTROL_axi_rdata ), + .s_axi_rresp ( s_HLS_CONTROL_axi_rresp ), + .s_axi_rlast ( s_HLS_CONTROL_axi_rlast ), + .s_axi_rvalid ( s_HLS_CONTROL_axi_rvalid ), + .s_axi_rready ( s_HLS_CONTROL_axi_rready ), + + // ALI-lite master to HLS IP + .m_axi_aclk ( HLS_CONTROL_clk_i ), + .m_axi_aresetn ( HLS_CONTROL_rstn_i ), + .m_axi_awid ( sync_HLS_CONTROL_axi_awid ), + .m_axi_awaddr ( sync_HLS_CONTROL_axi_awaddr ), + .m_axi_awlen ( sync_HLS_CONTROL_axi_awlen ), + .m_axi_awsize ( sync_HLS_CONTROL_axi_awsize ), + .m_axi_awburst ( sync_HLS_CONTROL_axi_awburst ), + .m_axi_awlock ( sync_HLS_CONTROL_axi_awlock ), + .m_axi_awcache ( sync_HLS_CONTROL_axi_awcache ), + .m_axi_awprot ( sync_HLS_CONTROL_axi_awprot ), + .m_axi_awregion ( sync_HLS_CONTROL_axi_awregion ), + .m_axi_awqos ( sync_HLS_CONTROL_axi_awqos ), + .m_axi_awvalid ( sync_HLS_CONTROL_axi_awvalid ), + .m_axi_awready ( sync_HLS_CONTROL_axi_awready ), + .m_axi_wdata ( sync_HLS_CONTROL_axi_wdata ), + .m_axi_wstrb ( sync_HLS_CONTROL_axi_wstrb ), + .m_axi_wlast ( sync_HLS_CONTROL_axi_wlast ), + .m_axi_wvalid ( sync_HLS_CONTROL_axi_wvalid ), + .m_axi_wready ( sync_HLS_CONTROL_axi_wready ), + .m_axi_bid ( sync_HLS_CONTROL_axi_bid ), + .m_axi_bresp ( sync_HLS_CONTROL_axi_bresp ), + .m_axi_bvalid ( sync_HLS_CONTROL_axi_bvalid ), + .m_axi_bready ( sync_HLS_CONTROL_axi_bready ), + .m_axi_arid ( sync_HLS_CONTROL_axi_arid ), + .m_axi_araddr ( sync_HLS_CONTROL_axi_araddr ), + .m_axi_arlen ( sync_HLS_CONTROL_axi_arlen ), + .m_axi_arsize ( sync_HLS_CONTROL_axi_arsize ), + .m_axi_arburst ( sync_HLS_CONTROL_axi_arburst ), + .m_axi_arlock ( sync_HLS_CONTROL_axi_arlock ), + .m_axi_arcache ( sync_HLS_CONTROL_axi_arcache ), + .m_axi_arprot ( sync_HLS_CONTROL_axi_arprot ), + .m_axi_arregion ( sync_HLS_CONTROL_axi_arregion ), + .m_axi_arqos ( sync_HLS_CONTROL_axi_arqos ), + .m_axi_arvalid ( sync_HLS_CONTROL_axi_arvalid ), + .m_axi_arready ( sync_HLS_CONTROL_axi_arready ), + .m_axi_rid ( sync_HLS_CONTROL_axi_rid ), + .m_axi_rdata ( sync_HLS_CONTROL_axi_rdata ), + .m_axi_rresp ( sync_HLS_CONTROL_axi_rresp ), + .m_axi_rlast ( sync_HLS_CONTROL_axi_rlast ), + .m_axi_rvalid ( sync_HLS_CONTROL_axi_rvalid ), + .m_axi_rready ( sync_HLS_CONTROL_axi_rready ) + ); + `else // notdefined(HLS_CONTROL_HAS_CLOCK_DOMAIN) + // Error out for now + $error("This version of HLS CONV2D IP must be in HBUS clock domain") + `endif + + // Use a Dwidth converter if System XLEN is 64-bits wide. + if ( MBUS_DATA_WIDTH == 64 ) begin : gen_dwidth_conv + + xlnx_axi_dwidth_64_to_32_converter axi_dwidth_conv_u ( + .s_axi_aclk ( HLS_CONTROL_clk_i ), + .s_axi_aresetn ( HLS_CONTROL_rstn_i ), + + // Slave from clock conv + .s_axi_awid ( sync_HLS_CONTROL_axi_awid ), + .s_axi_awaddr ( sync_HLS_CONTROL_axi_awaddr ), + .s_axi_awlen ( sync_HLS_CONTROL_axi_awlen ), + .s_axi_awsize ( sync_HLS_CONTROL_axi_awsize ), + .s_axi_awburst ( sync_HLS_CONTROL_axi_awburst ), + .s_axi_awvalid ( sync_HLS_CONTROL_axi_awvalid ), + .s_axi_awready ( sync_HLS_CONTROL_axi_awready ), + .s_axi_wdata ( sync_HLS_CONTROL_axi_wdata ), + .s_axi_wstrb ( sync_HLS_CONTROL_axi_wstrb ), + .s_axi_wlast ( sync_HLS_CONTROL_axi_wlast ), + .s_axi_wvalid ( sync_HLS_CONTROL_axi_wvalid ), + .s_axi_wready ( sync_HLS_CONTROL_axi_wready ), + .s_axi_bid ( sync_HLS_CONTROL_axi_bid ), + .s_axi_bresp ( sync_HLS_CONTROL_axi_bresp ), + .s_axi_bvalid ( sync_HLS_CONTROL_axi_bvalid ), + .s_axi_bready ( sync_HLS_CONTROL_axi_bready ), + .s_axi_arid ( sync_HLS_CONTROL_axi_arid ), + .s_axi_araddr ( sync_HLS_CONTROL_axi_araddr ), + .s_axi_arlen ( sync_HLS_CONTROL_axi_arlen ), + .s_axi_arsize ( sync_HLS_CONTROL_axi_arsize ), + .s_axi_arburst ( sync_HLS_CONTROL_axi_arburst ), + .s_axi_arvalid ( sync_HLS_CONTROL_axi_arvalid ), + .s_axi_arready ( sync_HLS_CONTROL_axi_arready ), + .s_axi_rid ( sync_HLS_CONTROL_axi_rid ), + .s_axi_rdata ( sync_HLS_CONTROL_axi_rdata ), + .s_axi_rresp ( sync_HLS_CONTROL_axi_rresp ), + .s_axi_rlast ( sync_HLS_CONTROL_axi_rlast ), + .s_axi_rvalid ( sync_HLS_CONTROL_axi_rvalid ), + .s_axi_rready ( sync_HLS_CONTROL_axi_rready ), + .s_axi_awlock ( sync_HLS_CONTROL_axi_awlock ), + .s_axi_awcache ( sync_HLS_CONTROL_axi_awcache ), + .s_axi_awprot ( sync_HLS_CONTROL_axi_awprot ), + .s_axi_awqos ( sync_HLS_CONTROL_axi_awqos ), + .s_axi_awregion ( sync_HLS_CONTROL_axi_awregion ), + .s_axi_arlock ( sync_HLS_CONTROL_axi_arlock ), + .s_axi_arcache ( sync_HLS_CONTROL_axi_arcache ), + .s_axi_arprot ( sync_HLS_CONTROL_axi_arprot ), + .s_axi_arqos ( sync_HLS_CONTROL_arqos ), + .s_axi_arregion ( sync_HLS_CONTROL_arregion ), + + // Master to Protocol Converter + .m_axi_awaddr ( to_prot_conv_axi_awaddr ), + .m_axi_awlen ( to_prot_conv_axi_awlen ), + .m_axi_awsize ( to_prot_conv_axi_awsize ), + .m_axi_awburst ( to_prot_conv_axi_awburst ), + .m_axi_awlock ( to_prot_conv_axi_awlock ), + .m_axi_awcache ( to_prot_conv_axi_awcache ), + .m_axi_awprot ( to_prot_conv_axi_awprot ), + .m_axi_awqos ( to_prot_conv_axi_awqos ), + .m_axi_awvalid ( to_prot_conv_axi_awvalid ), + .m_axi_awready ( to_prot_conv_axi_awready ), + .m_axi_wdata ( to_prot_conv_axi_wdata ), + .m_axi_wstrb ( to_prot_conv_axi_wstrb ), + .m_axi_wlast ( to_prot_conv_axi_wlast ), + .m_axi_wvalid ( to_prot_conv_axi_wvalid ), + .m_axi_wready ( to_prot_conv_axi_wready ), + .m_axi_bresp ( to_prot_conv_axi_bresp ), + .m_axi_bvalid ( to_prot_conv_axi_bvalid ), + .m_axi_bready ( to_prot_conv_axi_bready ), + .m_axi_araddr ( to_prot_conv_axi_araddr ), + .m_axi_arlen ( to_prot_conv_axi_arlen ), + .m_axi_arsize ( to_prot_conv_axi_arsize ), + .m_axi_arburst ( to_prot_conv_axi_arburst ), + .m_axi_arlock ( to_prot_conv_axi_arlock ), + .m_axi_arcache ( to_prot_conv_axi_arcache ), + .m_axi_arprot ( to_prot_conv_axi_arprot ), + .m_axi_arqos ( to_prot_conv_axi_arqos ), + .m_axi_arvalid ( to_prot_conv_axi_arvalid ), + .m_axi_arready ( to_prot_conv_axi_arready ), + .m_axi_rdata ( to_prot_conv_axi_rdata ), + .m_axi_rresp ( to_prot_conv_axi_rresp ), + .m_axi_rlast ( to_prot_conv_axi_rlast ), + .m_axi_rvalid ( to_prot_conv_axi_rvalid ), + .m_axi_rready ( to_prot_conv_axi_rready ) + + ); + + // Since the AXI data width converter has a reordering depth of 1 it doesn't have ID in its master ports - for more details see the documentation + assign to_prot_conv_axi_awid = '0; + assign to_prot_conv_axi_arid = '0; + + end : gen_dwidth_conv + else begin : no_dwidth_conv + + // Pass through + `ASSIGN_AXI_BUS (to_prot_conv, sync_HLS_CONTROL) + + end : no_dwidth_conv + + // AXI converter for HLS_DOTPROD_CONTROL + xlnx_axi4_to_axilite_d32_converter xlnx_axi4_to_axilite_u ( + // Clock and reset + .aclk ( HLS_CONTROL_clk_i ), // input wire s_aclk + .aresetn ( HLS_CONTROL_rstn_i ), // input wire s_aresetn + // Slave interface + .s_axi_awid ( to_prot_conv_axi_awid ), // input wire [1 : 0] s_axi_awid + .s_axi_awaddr ( to_prot_conv_axi_awaddr ), // input wire [31 : 0] s_axi_awaddr + .s_axi_awlen ( to_prot_conv_axi_awlen ), // input wire [7 : 0] s_axi_awlen + .s_axi_awsize ( to_prot_conv_axi_awsize ), // input wire [2 : 0] s_axi_awsize + .s_axi_awburst ( to_prot_conv_axi_awburst ), // input wire [1 : 0] s_axi_awburst + .s_axi_awlock ( to_prot_conv_axi_awlock ), // input wire [0 : 0] s_axi_awlock + .s_axi_awcache ( to_prot_conv_axi_awcache ), // input wire [3 : 0] s_axi_awcache + .s_axi_awprot ( to_prot_conv_axi_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awregion ( to_prot_conv_axi_awregion ), // input wire [3 : 0] s_axi_awregion + .s_axi_awqos ( to_prot_conv_axi_awqos ), // input wire [3 : 0] s_axi_awqos + .s_axi_awvalid ( to_prot_conv_axi_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( to_prot_conv_axi_awready ), // output wire s_axi_awready + .s_axi_wdata ( to_prot_conv_axi_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( to_prot_conv_axi_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wlast ( to_prot_conv_axi_wlast ), // input wire s_axi_wlast + .s_axi_wvalid ( to_prot_conv_axi_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( to_prot_conv_axi_wready ), // output wire s_axi_wready + .s_axi_bid ( to_prot_conv_axi_bid ), // output wire [1 : 0] s_axi_bid + .s_axi_bresp ( to_prot_conv_axi_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( to_prot_conv_axi_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( to_prot_conv_axi_bready ), // input wire s_axi_bready + .s_axi_arid ( to_prot_conv_axi_arid ), // input wire [1 : 0] s_axi_arid + .s_axi_araddr ( to_prot_conv_axi_araddr ), // input wire [31 : 0] s_axi_araddr + .s_axi_arlen ( to_prot_conv_axi_arlen ), // input wire [7 : 0] s_axi_arlen + .s_axi_arsize ( to_prot_conv_axi_arsize ), // input wire [2 : 0] s_axi_arsize + .s_axi_arburst ( to_prot_conv_axi_arburst ), // input wire [1 : 0] s_axi_arburst + .s_axi_arlock ( to_prot_conv_axi_arlock ), // input wire [0 : 0] s_axi_arlock + .s_axi_arcache ( to_prot_conv_axi_arcache ), // input wire [3 : 0] s_axi_arcache + .s_axi_arprot ( to_prot_conv_axi_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arregion ( to_prot_conv_axi_arregion ), // input wire [3 : 0] s_axi_arregion + .s_axi_arqos ( to_prot_conv_axi_arqos ), // input wire [3 : 0] s_axi_arqos + .s_axi_arvalid ( to_prot_conv_axi_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( to_prot_conv_axi_arready ), // output wire s_axi_arready + .s_axi_rid ( to_prot_conv_axi_rid ), // output wire [1 : 0] s_axi_rid + .s_axi_rdata ( to_prot_conv_axi_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( to_prot_conv_axi_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rlast ( to_prot_conv_axi_rlast ), // output wire s_axi_rlast + .s_axi_rvalid ( to_prot_conv_axi_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( to_prot_conv_axi_rready ), // input wire s_axi_rready + // Master interface + .m_axi_awaddr ( HLS_CONTROL_axilite_awaddr ), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot ( HLS_CONTROL_axilite_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid ( HLS_CONTROL_axilite_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( HLS_CONTROL_axilite_awready ), // input wire m_axi_awready + .m_axi_wdata ( HLS_CONTROL_axilite_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( HLS_CONTROL_axilite_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid ( HLS_CONTROL_axilite_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( HLS_CONTROL_axilite_wready ), // input wire m_axi_wready + .m_axi_bresp ( HLS_CONTROL_axilite_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( HLS_CONTROL_axilite_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( HLS_CONTROL_axilite_bready ), // output wire m_axi_bready + .m_axi_araddr ( HLS_CONTROL_axilite_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot ( HLS_CONTROL_axilite_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid ( HLS_CONTROL_axilite_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( HLS_CONTROL_axilite_arready ), // input wire m_axi_arready + .m_axi_rdata ( HLS_CONTROL_axilite_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( HLS_CONTROL_axilite_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid ( HLS_CONTROL_axilite_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( HLS_CONTROL_axilite_rready ) // output wire m_axi_rready + ); + + // Synchronize HLS interrupt line to MBUS + xpm_cdc_array_single #( + .DEST_SYNC_FF ( 4 ), // Number of sync flip-flops + .SRC_INPUT_REG ( 1 ), // Input register enable + .WIDTH ( 1 ) // Width of data to sync + ) + xpm_cdc_array_single_inst ( + .dest_out ( hls_interrupt_o ), + .dest_clk ( main_clk_i ), + .src_clk ( HLS_CONTROL_clk_i ), + .src_in ( hls_interrupt_async ) + ); + + // NOTE: AXI_DATA_WITDH=512 for this one, and should only be connected to HBUS + // HLS core instance + custom_hls_conv_hbus custom_hls_conv_hbus_u ( + .clk_i ( HLS_CONTROL_clk_i ), // input wire clk_i + .rst_ni ( HLS_CONTROL_rstn_i ), // input wire rst_ni + .interrupt_o ( hls_interrupt_async ), // output wire interrupt_o + // AXI4 Master + .gmem0_axi_awid ( m_HLS_gmem0_d512_axi_awid ), + .gmem0_axi_awaddr ( m_HLS_gmem0_d512_axi_awaddr ), + .gmem0_axi_awlen ( m_HLS_gmem0_d512_axi_awlen ), + .gmem0_axi_awsize ( m_HLS_gmem0_d512_axi_awsize ), + .gmem0_axi_awburst ( m_HLS_gmem0_d512_axi_awburst ), + .gmem0_axi_awlock ( m_HLS_gmem0_d512_axi_awlock ), + .gmem0_axi_awcache ( m_HLS_gmem0_d512_axi_awcache ), + .gmem0_axi_awprot ( m_HLS_gmem0_d512_axi_awprot ), + .gmem0_axi_awqos ( m_HLS_gmem0_d512_axi_awqos ), + .gmem0_axi_awvalid ( m_HLS_gmem0_d512_axi_awvalid ), + .gmem0_axi_awready ( m_HLS_gmem0_d512_axi_awready ), + .gmem0_axi_awregion ( m_HLS_gmem0_d512_axi_awregion ), + .gmem0_axi_wdata ( m_HLS_gmem0_d512_axi_wdata ), + .gmem0_axi_wstrb ( m_HLS_gmem0_d512_axi_wstrb ), + .gmem0_axi_wlast ( m_HLS_gmem0_d512_axi_wlast ), + .gmem0_axi_wvalid ( m_HLS_gmem0_d512_axi_wvalid ), + .gmem0_axi_wready ( m_HLS_gmem0_d512_axi_wready ), + .gmem0_axi_bid ( m_HLS_gmem0_d512_axi_bid ), + .gmem0_axi_bresp ( m_HLS_gmem0_d512_axi_bresp ), + .gmem0_axi_bvalid ( m_HLS_gmem0_d512_axi_bvalid ), + .gmem0_axi_bready ( m_HLS_gmem0_d512_axi_bready ), + .gmem0_axi_araddr ( m_HLS_gmem0_d512_axi_araddr ), + .gmem0_axi_arlen ( m_HLS_gmem0_d512_axi_arlen ), + .gmem0_axi_arsize ( m_HLS_gmem0_d512_axi_arsize ), + .gmem0_axi_arburst ( m_HLS_gmem0_d512_axi_arburst ), + .gmem0_axi_arlock ( m_HLS_gmem0_d512_axi_arlock ), + .gmem0_axi_arcache ( m_HLS_gmem0_d512_axi_arcache ), + .gmem0_axi_arprot ( m_HLS_gmem0_d512_axi_arprot ), + .gmem0_axi_arqos ( m_HLS_gmem0_d512_axi_arqos ), + .gmem0_axi_arvalid ( m_HLS_gmem0_d512_axi_arvalid ), + .gmem0_axi_arready ( m_HLS_gmem0_d512_axi_arready ), + .gmem0_axi_arid ( m_HLS_gmem0_d512_axi_arid ), + .gmem0_axi_arregion ( m_HLS_gmem0_d512_axi_arregion ), + .gmem0_axi_rid ( m_HLS_gmem0_d512_axi_rid ), + .gmem0_axi_rdata ( m_HLS_gmem0_d512_axi_rdata ), + .gmem0_axi_rresp ( m_HLS_gmem0_d512_axi_rresp ), + .gmem0_axi_rlast ( m_HLS_gmem0_d512_axi_rlast ), + .gmem0_axi_rvalid ( m_HLS_gmem0_d512_axi_rvalid ), + .gmem0_axi_rready ( m_HLS_gmem0_d512_axi_rready ), + // HLS_CONTROL AXI-lite slave + .control_axilite_awaddr ( HLS_CONTROL_axilite_awaddr ), // input wire [31 : 0] control_axilite_awaddr + .control_axilite_awprot ( HLS_CONTROL_axilite_awprot ), // input wire [2 : 0] control_axilite_awprot + .control_axilite_awvalid ( HLS_CONTROL_axilite_awvalid ), // input wire control_axilite_awvalid + .control_axilite_awready ( HLS_CONTROL_axilite_awready ), // output wire control_axilite_awready + .control_axilite_wdata ( HLS_CONTROL_axilite_wdata ), // input wire [31 : 0] control_axilite_wdata + .control_axilite_wstrb ( HLS_CONTROL_axilite_wstrb ), // input wire [3 : 0] control_axilite_wstrb + .control_axilite_wvalid ( HLS_CONTROL_axilite_wvalid ), // input wire control_axilite_wvalid + .control_axilite_wready ( HLS_CONTROL_axilite_wready ), // output wire control_axilite_wready + .control_axilite_bresp ( HLS_CONTROL_axilite_bresp ), // output wire [1 : 0] control_axilite_bresp + .control_axilite_bvalid ( HLS_CONTROL_axilite_bvalid ), // output wire control_axilite_bvalid + .control_axilite_bready ( HLS_CONTROL_axilite_bready ), // input wire control_axilite_bready + .control_axilite_araddr ( HLS_CONTROL_axilite_araddr ), // input wire [31 : 0] control_axilite_araddr + .control_axilite_arprot ( HLS_CONTROL_axilite_arprot ), // input wire [2 : 0] control_axilite_arprot + .control_axilite_arvalid ( HLS_CONTROL_axilite_arvalid ), // input wire control_axilite_arvalid + .control_axilite_arready ( HLS_CONTROL_axilite_arready ), // output wire control_axilite_arready + .control_axilite_rdata ( HLS_CONTROL_axilite_rdata ), // output wire [31 : 0] control_axilite_rdata + .control_axilite_rresp ( HLS_CONTROL_axilite_rresp ), // output wire [1 : 0] control_axilite_rresp + .control_axilite_rvalid ( HLS_CONTROL_axilite_rvalid ), // output wire control_axilite_rvalid + .control_axilite_rready ( HLS_CONTROL_axilite_rready ) // input wire control_axilite_rready + ); + +endmodule : hls_conv2d_wrapper \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/mbus_buses.svinc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/mbus_buses.svinc new file mode 100644 index 0000000000000000000000000000000000000000..037f2c87821467ed3f20b93c2bcf6769098b8c02 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/mbus_buses.svinc @@ -0,0 +1,35 @@ +// This file is auto-generated with declare_and_concat_buses_rtl.py + +///////////////////////////////////////// +// Buses declaration and concatenation // +///////////////////////////////////////// + +///////////////// +// AXI Masters // +///////////////// +`DECLARE_AXI_BUS(SYS_MASTER_to_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(RV_SOCKET_DATA_to_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(RV_SOCKET_INSTR_to_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(DBG_MASTER_to_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(CDMA_to_MBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) + +///////////////// +// AXI Slaves // +///////////////// +`DECLARE_AXI_BUS(MBUS_to_BRAM, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(MBUS_to_DM_mem, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(MBUS_to_PBUS, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(MBUS_to_CDMA, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`DECLARE_AXI_BUS(MBUS_to_PLIC, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) + +////////////////////////////////// +// Concatenate AXI master buses // +////////////////////////////////// +`DECLARE_AXI_BUS_ARRAY(MBUS_masters, MBUS_NUM_SI, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`CONCAT_AXI_MASTERS_ARRAY5(MBUS_masters, CDMA_to_MBUS, DBG_MASTER_to_MBUS, RV_SOCKET_INSTR_to_MBUS, RV_SOCKET_DATA_to_MBUS, SYS_MASTER_to_MBUS) + +///////////////////////////////// +// Concatenate AXI slave buses // +///////////////////////////////// +`DECLARE_AXI_BUS_ARRAY(MBUS_slaves, MBUS_NUM_MI, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) +`CONCAT_AXI_SLAVES_ARRAY5(MBUS_slaves, MBUS_to_PLIC, MBUS_to_CDMA, MBUS_to_PBUS, MBUS_to_DM_mem, MBUS_to_BRAM) diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/pbus_buses.svinc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/pbus_buses.svinc new file mode 100644 index 0000000000000000000000000000000000000000..0ee671c881d6cf2805265307eb0a274d3a92e153 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/pbus_buses.svinc @@ -0,0 +1,31 @@ +// This file is auto-generated with declare_and_concat_buses_rtl.py + +///////////////////////////////////////// +// Buses declaration and concatenation // +///////////////////////////////////////// + +///////////////// +// AXI Masters // +///////////////// +`DECLARE_AXILITE_BUS(PROT_CONV_to_PBUS, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) + +///////////////// +// AXI Slaves // +///////////////// +`DECLARE_AXILITE_BUS(PBUS_to_UART, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) +`DECLARE_AXILITE_BUS(PBUS_to_GPIO_out, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) +`DECLARE_AXILITE_BUS(PBUS_to_GPIO_in, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) +`DECLARE_AXILITE_BUS(PBUS_to_TIM0, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) +`DECLARE_AXILITE_BUS(PBUS_to_TIM1, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) + +////////////////////////////////// +// Concatenate AXI master buses // +////////////////////////////////// +`DECLARE_AXILITE_BUS_ARRAY(PBUS_masters, 1, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) +`CONCAT_AXILITE_MASTERS_ARRAY1(PBUS_masters, PROT_CONV_to_PBUS) + +///////////////////////////////// +// Concatenate AXI slave buses // +///////////////////////////////// +`DECLARE_AXILITE_BUS_ARRAY(PBUS_slaves, PBUS_NUM_MI, PBUS_DATA_WIDTH, PBUS_ADDR_WIDTH, PBUS_ID_WIDTH) +`CONCAT_AXILITE_SLAVES_ARRAY5(PBUS_slaves, PBUS_to_TIM1, PBUS_to_TIM0, PBUS_to_GPIO_in, PBUS_to_GPIO_out, PBUS_to_UART) diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/peripheral_bus.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/peripheral_bus.sv new file mode 100644 index 0000000000000000000000000000000000000000..128f8940b138cc6f9041fc4c0a8e4cfe57e9006e --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/peripheral_bus.sv @@ -0,0 +1,600 @@ +// Author: Manuel Maddaluno +// Author: Stefano Mercogliano +// Description: This module is the module wrapping the entire peripheral bus. +// This is a 32-bits bus, meaning a dwidth converter is required if the system XLEN is 64. +// It adds a AXI protocol converter before the axilite crossbar and all the peripherals connected to the axilite crossbar +// NOTE: Although, it would be more efficient to have the Clock Converter after the AXI Prot Converter, +// we keep things simple (since, for now, we do not have the AXI Lite Clock Converter) we leave it as follows. +// +// ___________ ____________ _______________ _____________ _______ +// | | AXI4 | | AXI4 | | AXI Lite | | | | +// | Clock | (XLEN) | Data Width | (32) | AXI Protocol | (32) | |---------->| UART | +// --->| Converter |------->| Converter |------>| Converter |------------->| Peripheral | |_______| +// | | | (Optional) | | | | XBAR | +// |___________| |____________| |_______________| | (axilite) | ___________ +// | | | | Interrupts +// | |---------->| GPIO_out |------| +// | | |___________| | +// | | ___________ | +// | | | | | +// | |---------->| GPIO_in |----| | +// | | |___________| | | +// | | ________ | | +// | | | | | | +// | |---------->| TIM0 |-----| | | +// | | |________| | | | +// | | ________ | | | +// | | | | | | | +// | |---------->| TIM1 |---| | | | +// __________________ |_____________| |________| | | | | +// | | NUM_IRQ interrupts | | | | +// <------| CDC Synchronizer |<----------------------------------------------------------------------------------------|-|-|-| +// |__________________| +// + +// Import packages +import uninasoc_pkg::*; + +// Import headers +`include "uninasoc_axi.svh" + +module peripheral_bus #( + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 2, + parameter int unsigned NUM_IRQ = 4 +)( + input logic main_clock_i, + input logic main_reset_ni, + input logic PBUS_clock_i, + input logic PBUS_reset_ni, + + // AXI4 Slave interface from the main xbar + `DEFINE_AXI_SLAVE_PORTS(s, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH), + + // EMBEDDED ONLY + // UART interface + input logic uart_rx_i, + output logic uart_tx_o, + + // GPIOs + input logic [GPIO_IN_WIDTH -1 : 0] gpio_in_i, + output logic [GPIO_OUT_WIDTH -1 : 0] gpio_out_o, + + // Interrupts + output logic [NUM_IRQ - 1 : 0] int_o + +); + + ///////////////////////////////////////// + // Buses declaration and concatenation // + ///////////////////////////////////////// + `include "pbus_buses.svinc" + `DECLARE_AXI_BUS(to_dwidth_conv, MBUS_DATA_WIDTH, MBUS_ADDR_WIDTH, MBUS_ID_WIDTH) + `DECLARE_AXI_BUS(to_prot_conv, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + + /////////////////////// + // Interrupt Signals // + /////////////////////// + + logic uart_int; + logic tim0_int; + logic tim1_int; + // EMBEDDED ONLY + logic gpio_in_int; + + ////////////////////// + // Clock Converters // + ////////////////////// + + // If the PBUS has a clock domain (the pbus has a clock different than main clock) + // Converter has the system size (i.e XLEN), which may be either 64 or 32 + `ifdef PBUS_HAS_CLOCK_DOMAIN + axi_clock_converter_wrapper # ( + .LOCAL_DATA_WIDTH (MBUS_DATA_WIDTH), + .LOCAL_ADDR_WIDTH (MBUS_ADDR_WIDTH), + .LOCAL_ID_WIDTH (MBUS_ID_WIDTH) + ) axi_clk_conv_u ( + + .s_axi_aclk ( main_clock_i ), + .s_axi_aresetn ( main_reset_ni ), + + .m_axi_aclk ( PBUS_clock_i ), + .m_axi_aresetn ( PBUS_reset_ni ), + + // Slave from MBUS + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awqos ( s_axi_awqos ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_awregion ( s_axi_awregion ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arregion ( s_axi_arregion ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arqos ( s_axi_arqos ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + + + // Master to datawdith converter + .m_axi_awid ( to_dwidth_conv_axi_awid ), + .m_axi_awaddr ( to_dwidth_conv_axi_awaddr ), + .m_axi_awlen ( to_dwidth_conv_axi_awlen ), + .m_axi_awsize ( to_dwidth_conv_axi_awsize ), + .m_axi_awburst ( to_dwidth_conv_axi_awburst ), + .m_axi_awlock ( to_dwidth_conv_axi_awlock ), + .m_axi_awcache ( to_dwidth_conv_axi_awcache ), + .m_axi_awprot ( to_dwidth_conv_axi_awprot ), + .m_axi_awregion ( to_dwidth_conv_axi_awregion ), + .m_axi_awqos ( to_dwidth_conv_axi_awqos ), + .m_axi_awvalid ( to_dwidth_conv_axi_awvalid ), + .m_axi_awready ( to_dwidth_conv_axi_awready ), + .m_axi_wdata ( to_dwidth_conv_axi_wdata ), + .m_axi_wstrb ( to_dwidth_conv_axi_wstrb ), + .m_axi_wlast ( to_dwidth_conv_axi_wlast ), + .m_axi_wvalid ( to_dwidth_conv_axi_wvalid ), + .m_axi_wready ( to_dwidth_conv_axi_wready ), + .m_axi_bid ( to_dwidth_conv_axi_bid ), + .m_axi_bresp ( to_dwidth_conv_axi_bresp ), + .m_axi_bvalid ( to_dwidth_conv_axi_bvalid ), + .m_axi_bready ( to_dwidth_conv_axi_bready ), + .m_axi_arid ( to_dwidth_conv_axi_arid ), + .m_axi_araddr ( to_dwidth_conv_axi_araddr ), + .m_axi_arlen ( to_dwidth_conv_axi_arlen ), + .m_axi_arsize ( to_dwidth_conv_axi_arsize ), + .m_axi_arburst ( to_dwidth_conv_axi_arburst ), + .m_axi_arlock ( to_dwidth_conv_axi_arlock ), + .m_axi_arcache ( to_dwidth_conv_axi_arcache ), + .m_axi_arprot ( to_dwidth_conv_axi_arprot ), + .m_axi_arregion ( to_dwidth_conv_axi_arregion ), + .m_axi_arqos ( to_dwidth_conv_axi_arqos ), + .m_axi_arvalid ( to_dwidth_conv_axi_arvalid ), + .m_axi_arready ( to_dwidth_conv_axi_arready ), + .m_axi_rid ( to_dwidth_conv_axi_rid ), + .m_axi_rdata ( to_dwidth_conv_axi_rdata ), + .m_axi_rresp ( to_dwidth_conv_axi_rresp ), + .m_axi_rlast ( to_dwidth_conv_axi_rlast ), + .m_axi_rvalid ( to_dwidth_conv_axi_rvalid ), + .m_axi_rready ( to_dwidth_conv_axi_rready ) + ); + + // Assign interrupt pins (input to the cdc) + logic [NUM_IRQ-1:0] cdc_src_in; + always_comb begin + cdc_src_in = '0; + cdc_src_in[PBUS_GPIOIN_INTERRUPT] = gpio_in_int; + cdc_src_in[PBUS_TIM0_INTERRUPT] = tim0_int; + cdc_src_in[PBUS_TIM1_INTERRUPT] = tim1_int; + cdc_src_in[PBUS_UART_INTERRUPT] = uart_int; + end + + + // Output clock converter - convert from PBUS_DOMAIN to MAIN_DOMAIN (mainly used for interrupts) + xpm_cdc_array_single #( + .DEST_SYNC_FF ( 8 ), // Number of sync flip-flops + .SRC_INPUT_REG ( 1 ), // Input register enable + .WIDTH ( NUM_IRQ ) // Width of data to sync + ) + xpm_cdc_array_single_inst ( + .dest_out ( int_o ), + .dest_clk ( main_clock_i ), // Destination clock domain (MAIN_DOMAIN) + .src_clk ( PBUS_clock_i ), // Source clock domain (PBUS_DOMAIN) + .src_in ( cdc_src_in ) + ); + + + `else // The PBUS has the same clock of main clock + // Passthrough slave interface + `ASSIGN_AXI_BUS (to_dwidth_conv, s) + + // Assign interrupt pins + always_comb begin + int_o = '0; + int_o[PBUS_GPIOIN_INTERRUPT] = gpio_in_int; + int_o[PBUS_TIM0_INTERRUPT] = tim0_int; + int_o[PBUS_TIM1_INTERRUPT] = tim1_int; + int_o[PBUS_UART_INTERRUPT] = uart_int; + end + `endif + + ////////////////////////// + // Data Width Converter // + ////////////////////////// + + // Use a Dwidth converter if System XLEN is 64-bits wide. + if ( MBUS_DATA_WIDTH == 64 ) begin : gen_dwidth_conv + + xlnx_axi_dwidth_64_to_32_converter axi_dwidth_conv_u ( + .s_axi_aclk ( PBUS_clock_i ), + .s_axi_aresetn ( PBUS_reset_ni ), + + // Slave from clock conv + .s_axi_awid ( to_dwidth_conv_axi_awid ), + .s_axi_awaddr ( to_dwidth_conv_axi_awaddr ), + .s_axi_awlen ( to_dwidth_conv_axi_awlen ), + .s_axi_awsize ( to_dwidth_conv_axi_awsize ), + .s_axi_awburst ( to_dwidth_conv_axi_awburst ), + .s_axi_awvalid ( to_dwidth_conv_axi_awvalid ), + .s_axi_awready ( to_dwidth_conv_axi_awready ), + .s_axi_wdata ( to_dwidth_conv_axi_wdata ), + .s_axi_wstrb ( to_dwidth_conv_axi_wstrb ), + .s_axi_wlast ( to_dwidth_conv_axi_wlast ), + .s_axi_wvalid ( to_dwidth_conv_axi_wvalid ), + .s_axi_wready ( to_dwidth_conv_axi_wready ), + .s_axi_bid ( to_dwidth_conv_axi_bid ), + .s_axi_bresp ( to_dwidth_conv_axi_bresp ), + .s_axi_bvalid ( to_dwidth_conv_axi_bvalid ), + .s_axi_bready ( to_dwidth_conv_axi_bready ), + .s_axi_arid ( to_dwidth_conv_axi_arid ), + .s_axi_araddr ( to_dwidth_conv_axi_araddr ), + .s_axi_arlen ( to_dwidth_conv_axi_arlen ), + .s_axi_arsize ( to_dwidth_conv_axi_arsize ), + .s_axi_arburst ( to_dwidth_conv_axi_arburst ), + .s_axi_arvalid ( to_dwidth_conv_axi_arvalid ), + .s_axi_arready ( to_dwidth_conv_axi_arready ), + .s_axi_rid ( to_dwidth_conv_axi_rid ), + .s_axi_rdata ( to_dwidth_conv_axi_rdata ), + .s_axi_rresp ( to_dwidth_conv_axi_rresp ), + .s_axi_rlast ( to_dwidth_conv_axi_rlast ), + .s_axi_rvalid ( to_dwidth_conv_axi_rvalid ), + .s_axi_rready ( to_dwidth_conv_axi_rready ), + .s_axi_awlock ( to_dwidth_conv_axi_awlock ), + .s_axi_awcache ( to_dwidth_conv_axi_awcache ), + .s_axi_awprot ( to_dwidth_conv_axi_awprot ), + .s_axi_awqos ( 0 ), + .s_axi_awregion ( 0 ), + .s_axi_arlock ( to_dwidth_conv_axi_arlock ), + .s_axi_arcache ( to_dwidth_conv_axi_arcache ), + .s_axi_arprot ( to_dwidth_conv_axi_arprot ), + .s_axi_arqos ( 0 ), + .s_axi_arregion ( 0 ), + + + // Master to Protocol Converter + .m_axi_awaddr ( to_prot_conv_axi_awaddr ), + .m_axi_awlen ( to_prot_conv_axi_awlen ), + .m_axi_awsize ( to_prot_conv_axi_awsize ), + .m_axi_awburst ( to_prot_conv_axi_awburst ), + .m_axi_awlock ( to_prot_conv_axi_awlock ), + .m_axi_awcache ( to_prot_conv_axi_awcache ), + .m_axi_awprot ( to_prot_conv_axi_awprot ), + .m_axi_awqos ( to_prot_conv_axi_awqos ), + .m_axi_awvalid ( to_prot_conv_axi_awvalid ), + .m_axi_awready ( to_prot_conv_axi_awready ), + .m_axi_wdata ( to_prot_conv_axi_wdata ), + .m_axi_wstrb ( to_prot_conv_axi_wstrb ), + .m_axi_wlast ( to_prot_conv_axi_wlast ), + .m_axi_wvalid ( to_prot_conv_axi_wvalid ), + .m_axi_wready ( to_prot_conv_axi_wready ), + .m_axi_bresp ( to_prot_conv_axi_bresp ), + .m_axi_bvalid ( to_prot_conv_axi_bvalid ), + .m_axi_bready ( to_prot_conv_axi_bready ), + .m_axi_araddr ( to_prot_conv_axi_araddr ), + .m_axi_arlen ( to_prot_conv_axi_arlen ), + .m_axi_arsize ( to_prot_conv_axi_arsize ), + .m_axi_arburst ( to_prot_conv_axi_arburst ), + .m_axi_arlock ( to_prot_conv_axi_arlock ), + .m_axi_arcache ( to_prot_conv_axi_arcache ), + .m_axi_arprot ( to_prot_conv_axi_arprot ), + .m_axi_arqos ( to_prot_conv_axi_arqos ), + .m_axi_arvalid ( to_prot_conv_axi_arvalid ), + .m_axi_arready ( to_prot_conv_axi_arready ), + .m_axi_rdata ( to_prot_conv_axi_rdata ), + .m_axi_rresp ( to_prot_conv_axi_rresp ), + .m_axi_rlast ( to_prot_conv_axi_rlast ), + .m_axi_rvalid ( to_prot_conv_axi_rvalid ), + .m_axi_rready ( to_prot_conv_axi_rready ) + + ); + + // Since the AXI data width converter has a reordering depth of 1 it doesn't have ID in its master ports - for more details see the documentation + assign to_prot_conv_axi_awid = '0; + assign to_prot_conv_axi_arid = '0; + end : gen_dwidth_conv + else begin : no_dwidth_conv + `ASSIGN_AXI_BUS (to_prot_conv, to_dwidth_conv) + end : no_dwidth_conv + + ///////////////////// + // AXI-lite Master // + ///////////////////// + + // AXI4 to AXI4-Lite protocol converter + xlnx_axi4_to_axilite_d32_converter axi4_to_axilite_u ( + .aclk ( PBUS_clock_i ), // input wire s_axi_aclk + .aresetn ( PBUS_reset_ni ), // input wire s_axi_aresetn + // AXI4 slave port (from main clock converter) + .s_axi_awid ( to_prot_conv_axi_awid ), // input wire [1 : 0] s_axi_awid + .s_axi_awaddr ( to_prot_conv_axi_awaddr ), // input wire [31 : 0] s_axi_awaddr + .s_axi_awlen ( to_prot_conv_axi_awlen ), // input wire [7 : 0] s_axi_awlen + .s_axi_awsize ( to_prot_conv_axi_awsize ), // input wire [2 : 0] s_axi_awsize + .s_axi_awburst ( to_prot_conv_axi_awburst ), // input wire [1 : 0] s_axi_awburst + .s_axi_awlock ( to_prot_conv_axi_awlock ), // input wire [0 : 0] s_axi_awlock + .s_axi_awcache ( to_prot_conv_axi_awcache ), // input wire [3 : 0] s_axi_awcache + .s_axi_awprot ( to_prot_conv_axi_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awregion ( to_prot_conv_axi_awregion ), // input wire [3 : 0] s_axi_awregion + .s_axi_awqos ( to_prot_conv_axi_awqos ), // input wire [3 : 0] s_axi_awqos + .s_axi_awvalid ( to_prot_conv_axi_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( to_prot_conv_axi_awready ), // output wire s_axi_awready + .s_axi_wdata ( to_prot_conv_axi_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( to_prot_conv_axi_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wlast ( to_prot_conv_axi_wlast ), // input wire s_axi_wlast + .s_axi_wvalid ( to_prot_conv_axi_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( to_prot_conv_axi_wready ), // output wire s_axi_wready + .s_axi_bid ( to_prot_conv_axi_bid ), // output wire [1 : 0] s_axi_bid + .s_axi_bresp ( to_prot_conv_axi_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( to_prot_conv_axi_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( to_prot_conv_axi_bready ), // input wire s_axi_bready + .s_axi_arid ( to_prot_conv_axi_arid ), // input wire [1 : 0] s_axi_arid + .s_axi_araddr ( to_prot_conv_axi_araddr ), // input wire [31 : 0] s_axi_araddr + .s_axi_arlen ( to_prot_conv_axi_arlen ), // input wire [7 : 0] s_axi_arlen + .s_axi_arsize ( to_prot_conv_axi_arsize ), // input wire [2 : 0] s_axi_arsize + .s_axi_arburst ( to_prot_conv_axi_arburst ), // input wire [1 : 0] s_axi_arburst + .s_axi_arlock ( to_prot_conv_axi_arlock ), // input wire [0 : 0] s_axi_arlock + .s_axi_arcache ( to_prot_conv_axi_arcache ), // input wire [3 : 0] s_axi_arcache + .s_axi_arprot ( to_prot_conv_axi_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arregion ( to_prot_conv_axi_arregion ), // input wire [3 : 0] s_axi_arregion + .s_axi_arqos ( to_prot_conv_axi_arqos ), // input wire [3 : 0] s_axi_arqos + .s_axi_arvalid ( to_prot_conv_axi_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( to_prot_conv_axi_arready ), // output wire s_axi_arready + .s_axi_rid ( to_prot_conv_axi_rid ), // output wire [1 : 0] s_axi_rid + .s_axi_rdata ( to_prot_conv_axi_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( to_prot_conv_axi_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rlast ( to_prot_conv_axi_rlast ), // output wire s_axi_rlast + .s_axi_rvalid ( to_prot_conv_axi_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( to_prot_conv_axi_rready ), // input wire s_axi_rready + // Master port (to AXI Lite crossbar) + .m_axi_awaddr ( PROT_CONV_to_PBUS_axilite_awaddr ), // output wire [31 : 0] m_axi_awaddr + .m_axi_awprot ( PROT_CONV_to_PBUS_axilite_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awvalid ( PROT_CONV_to_PBUS_axilite_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( PROT_CONV_to_PBUS_axilite_awready ), // input wire m_axi_awready + .m_axi_wdata ( PROT_CONV_to_PBUS_axilite_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( PROT_CONV_to_PBUS_axilite_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wvalid ( PROT_CONV_to_PBUS_axilite_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( PROT_CONV_to_PBUS_axilite_wready ), // input wire m_axi_wready + .m_axi_bresp ( PROT_CONV_to_PBUS_axilite_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( PROT_CONV_to_PBUS_axilite_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( PROT_CONV_to_PBUS_axilite_bready ), // output wire m_axi_bready + .m_axi_araddr ( PROT_CONV_to_PBUS_axilite_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arprot ( PROT_CONV_to_PBUS_axilite_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arvalid ( PROT_CONV_to_PBUS_axilite_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( PROT_CONV_to_PBUS_axilite_arready ), // input wire m_axi_arready + .m_axi_rdata ( PROT_CONV_to_PBUS_axilite_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( PROT_CONV_to_PBUS_axilite_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rvalid ( PROT_CONV_to_PBUS_axilite_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( PROT_CONV_to_PBUS_axilite_rready ) // output wire m_axi_rready + ); + + // AXI Lite crossbar + xlnx_peripheral_crossbar peripheral_xbar_u ( + .aclk ( PBUS_clock_i ), + .aresetn ( PBUS_reset_ni ), + + .s_axi_awaddr ( PBUS_masters_axilite_awaddr ), + .s_axi_awprot ( PBUS_masters_axilite_awprot ), + .s_axi_awvalid ( PBUS_masters_axilite_awvalid ), + .s_axi_awready ( PBUS_masters_axilite_awready ), + .s_axi_wdata ( PBUS_masters_axilite_wdata ), + .s_axi_wstrb ( PBUS_masters_axilite_wstrb ), + .s_axi_wvalid ( PBUS_masters_axilite_wvalid ), + .s_axi_wready ( PBUS_masters_axilite_wready ), + .s_axi_bresp ( PBUS_masters_axilite_bresp ), + .s_axi_bvalid ( PBUS_masters_axilite_bvalid ), + .s_axi_bready ( PBUS_masters_axilite_bready ), + .s_axi_araddr ( PBUS_masters_axilite_araddr ), + .s_axi_arprot ( PBUS_masters_axilite_arprot ), + .s_axi_arvalid ( PBUS_masters_axilite_arvalid ), + .s_axi_arready ( PBUS_masters_axilite_arready ), + .s_axi_rdata ( PBUS_masters_axilite_rdata ), + .s_axi_rresp ( PBUS_masters_axilite_rresp ), + .s_axi_rvalid ( PBUS_masters_axilite_rvalid ), + .s_axi_rready ( PBUS_masters_axilite_rready ), + + .m_axi_awaddr ( PBUS_slaves_axilite_awaddr ), + .m_axi_awprot ( PBUS_slaves_axilite_awprot ), + .m_axi_awvalid ( PBUS_slaves_axilite_awvalid ), + .m_axi_awready ( PBUS_slaves_axilite_awready ), + .m_axi_wdata ( PBUS_slaves_axilite_wdata ), + .m_axi_wstrb ( PBUS_slaves_axilite_wstrb ), + .m_axi_wvalid ( PBUS_slaves_axilite_wvalid ), + .m_axi_wready ( PBUS_slaves_axilite_wready ), + .m_axi_bresp ( PBUS_slaves_axilite_bresp ), + .m_axi_bvalid ( PBUS_slaves_axilite_bvalid ), + .m_axi_bready ( PBUS_slaves_axilite_bready ), + .m_axi_araddr ( PBUS_slaves_axilite_araddr ), + .m_axi_arprot ( PBUS_slaves_axilite_arprot ), + .m_axi_arvalid ( PBUS_slaves_axilite_arvalid ), + .m_axi_arready ( PBUS_slaves_axilite_arready ), + .m_axi_rdata ( PBUS_slaves_axilite_rdata ), + .m_axi_rresp ( PBUS_slaves_axilite_rresp ), + .m_axi_rvalid ( PBUS_slaves_axilite_rvalid ), + .m_axi_rready ( PBUS_slaves_axilite_rready ) + + ); + + ///////////////////// + // AXI-lite Slaves // + ///////////////////// + + // AXI4 Lite UART + axilite_uart # ( + .LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( LOCAL_ID_WIDTH ) + ) axilite_uart_u ( + .clock_i ( PBUS_clock_i ), // input wire s_axi_aclk + .reset_ni ( PBUS_reset_ni ), // input wire s_axi_aresetn + .int_core_o ( uart_int ), // Output interrupt + .int_xdma_o ( ), // TBD + .int_ack_i ( '0 ), // TBD + + // EMBEDDED ONLY + .tx_o ( uart_tx_o ), // Transmission signal (SoC output signal) + .rx_i ( uart_rx_i ), // Receive signal (SoC input signal) + + // AXI4 lite slave port (from xbar lite) + .s_axilite_awaddr ( PBUS_to_UART_axilite_awaddr ), + .s_axilite_awprot ( PBUS_to_UART_axilite_awprot ), + .s_axilite_awvalid ( PBUS_to_UART_axilite_awvalid ), + .s_axilite_awready ( PBUS_to_UART_axilite_awready ), + .s_axilite_wdata ( PBUS_to_UART_axilite_wdata ), + .s_axilite_wstrb ( PBUS_to_UART_axilite_wstrb ), + .s_axilite_wvalid ( PBUS_to_UART_axilite_wvalid ), + .s_axilite_wready ( PBUS_to_UART_axilite_wready ), + .s_axilite_bresp ( PBUS_to_UART_axilite_bresp ), + .s_axilite_bvalid ( PBUS_to_UART_axilite_bvalid ), + .s_axilite_bready ( PBUS_to_UART_axilite_bready ), + .s_axilite_araddr ( PBUS_to_UART_axilite_araddr ), + .s_axilite_arprot ( PBUS_to_UART_axilite_arprot ), + .s_axilite_arvalid ( PBUS_to_UART_axilite_arvalid ), + .s_axilite_arready ( PBUS_to_UART_axilite_arready ), + .s_axilite_rdata ( PBUS_to_UART_axilite_rdata ), + .s_axilite_rresp ( PBUS_to_UART_axilite_rresp ), + .s_axilite_rvalid ( PBUS_to_UART_axilite_rvalid ), + .s_axilite_rready ( PBUS_to_UART_axilite_rready ) + ); + + // AXI4 Lite Timers + + xlnx_axilite_timer tim0_u ( + .s_axi_aclk ( PBUS_clock_i ), // input wire s_axi_aclk + .s_axi_aresetn ( PBUS_reset_ni ), // input wire s_axi_aresetn + .s_axi_awaddr ( PBUS_to_TIM0_axilite_awaddr [8:0] ), // input wire [8 : 0] s_axi_awaddr + .s_axi_awvalid ( PBUS_to_TIM0_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( PBUS_to_TIM0_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( PBUS_to_TIM0_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( PBUS_to_TIM0_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( PBUS_to_TIM0_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( PBUS_to_TIM0_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( PBUS_to_TIM0_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( PBUS_to_TIM0_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( PBUS_to_TIM0_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( PBUS_to_TIM0_axilite_araddr [8:0] ), // input wire [8 : 0] s_axi_araddr + .s_axi_arvalid ( PBUS_to_TIM0_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( PBUS_to_TIM0_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( PBUS_to_TIM0_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( PBUS_to_TIM0_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( PBUS_to_TIM0_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( PBUS_to_TIM0_axilite_rready ), // input wire s_axi_rready + + .capturetrig0 ( '0 ), // input [0:0] + .capturetrig1 ( '0 ), // input [0:0] + .freeze ( '0 ), // input [0:0] + .generateout0 ( ), // output [0:0] + .generateout1 ( ), // output [0:0] + .interrupt ( tim0_int ), // output [0:0] + .pwm0 ( ) // output [0:0] + ); + + xlnx_axilite_timer tim1_u ( + .s_axi_aclk ( PBUS_clock_i ), // input wire s_axi_aclk + .s_axi_aresetn ( PBUS_reset_ni ), // input wire s_axi_aresetn + .s_axi_awaddr ( PBUS_to_TIM1_axilite_awaddr [8:0] ), // input wire [8 : 0] s_axi_awaddr + .s_axi_awvalid ( PBUS_to_TIM1_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( PBUS_to_TIM1_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( PBUS_to_TIM1_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( PBUS_to_TIM1_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( PBUS_to_TIM1_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( PBUS_to_TIM1_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( PBUS_to_TIM1_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( PBUS_to_TIM1_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( PBUS_to_TIM1_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( PBUS_to_TIM1_axilite_araddr [8:0] ), // input wire [8 : 0] s_axi_araddr + .s_axi_arvalid ( PBUS_to_TIM1_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( PBUS_to_TIM1_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( PBUS_to_TIM1_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( PBUS_to_TIM1_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( PBUS_to_TIM1_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( PBUS_to_TIM1_axilite_rready ), // input wire s_axi_rready + + .capturetrig0 ( '0 ), // input [0:0] + .capturetrig1 ( '0 ), // input [0:0] + .freeze ( '0 ), // input [0:0] + .generateout0 ( ), // output [0:0] + .generateout1 ( ), // output [0:0] + .interrupt ( tim1_int ), // output [0:0] + .pwm0 ( ) // output [0:0] + ); + +`ifdef EMBEDDED + + // GPIO OUT instance + xlnx_axi_gpio_out gpio_out_u ( + .s_axi_aclk ( PBUS_clock_i ), // input wire s_axi_aclk + .s_axi_aresetn ( PBUS_reset_ni ), // input wire s_axi_aresetn + .s_axi_awaddr ( PBUS_to_GPIO_out_axilite_awaddr [8:0] ), // input wire [8 : 0] s_axi_awaddr + .s_axi_awvalid ( PBUS_to_GPIO_out_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( PBUS_to_GPIO_out_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( PBUS_to_GPIO_out_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( PBUS_to_GPIO_out_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( PBUS_to_GPIO_out_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( PBUS_to_GPIO_out_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( PBUS_to_GPIO_out_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( PBUS_to_GPIO_out_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( PBUS_to_GPIO_out_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( PBUS_to_GPIO_out_axilite_araddr [8:0] ), // input wire [8 : 0] s_axi_araddr + .s_axi_arvalid ( PBUS_to_GPIO_out_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( PBUS_to_GPIO_out_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( PBUS_to_GPIO_out_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( PBUS_to_GPIO_out_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( PBUS_to_GPIO_out_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( PBUS_to_GPIO_out_axilite_rready ), // input wire s_axi_rready + .gpio_io_o ( gpio_out_o ) // input wire [0 : 0] gpio_io_o + ); + + // GPIO IN instance + xlnx_axi_gpio_in gpio_in_u ( + .s_axi_aclk ( PBUS_clock_i ), // input wire s_axi_aclk + .s_axi_aresetn ( PBUS_reset_ni ), // input wire s_axi_aresetn + .s_axi_awaddr ( PBUS_to_GPIO_in_axilite_awaddr [8:0] ), // input wire [8 : 0] s_axi_awaddr + .s_axi_awvalid ( PBUS_to_GPIO_in_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( PBUS_to_GPIO_in_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( PBUS_to_GPIO_in_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( PBUS_to_GPIO_in_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( PBUS_to_GPIO_in_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( PBUS_to_GPIO_in_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( PBUS_to_GPIO_in_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( PBUS_to_GPIO_in_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( PBUS_to_GPIO_in_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( PBUS_to_GPIO_in_axilite_araddr [8:0] ), // input wire [8 : 0] s_axi_araddr + .s_axi_arvalid ( PBUS_to_GPIO_in_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( PBUS_to_GPIO_in_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( PBUS_to_GPIO_in_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( PBUS_to_GPIO_in_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( PBUS_to_GPIO_in_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( PBUS_to_GPIO_in_axilite_rready ), // input wire s_axi_rready + .gpio_io_i ( gpio_in_i ), + .ip2intc_irpt ( gpio_in_int ) // output wire [0:0] (interrupt) + ); + +`endif + +endmodule : peripheral_bus diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/plic_wrapper.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/plic_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..b2b3acc0e4b8308140ff8e89610619d4085b29ea --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/plic_wrapper.sv @@ -0,0 +1,186 @@ +// Author: Stefano Mercogliano +// Description: +// This module is a wrapper for the RISC-V PLIC hosting both the PLIC and an optional +// Data width converter. It is required as RISC-V PLIC is a 32-bits IP by default. +// Therefore, if the MBUS is 64-bits wide, a converter is required. + +`include "uninasoc_axi.svh" + +module plic_wrapper # ( + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 2 +) ( + // Clock and reset + input logic clk_i, + input logic rst_ni, + + // Interrupt Sources + input logic [31:0] intr_src_i, + + // Interrupt notification to targets (One Hart, Two Contextes (M and S)) + output logic irq_o, + + // AXI Slave Interface + `DEFINE_AXI_SLAVE_PORTS(s, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) +); + + // Declare internal 32-bit bus to PLIC interface + `DECLARE_AXI_BUS(to_plic, 32, 32, LOCAL_ID_WIDTH) + + ////////////////////////// + // Data Width Converter // + ////////////////////////// + + // the PLIC is always a 32-bits peripheral, + // therefore a dwidth converter is required if XLEN = 64 + if (LOCAL_DATA_WIDTH == 64) begin : gen_axi_32_dwidth_conv + + xlnx_axi_dwidth_64_to_32_converter axi_dwidth_conv_u ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + + // Slave from clock conv + .s_axi_awid ( s_axi_awid ), + .s_axi_awaddr ( s_axi_awaddr ), + .s_axi_awlen ( s_axi_awlen ), + .s_axi_awsize ( s_axi_awsize ), + .s_axi_awburst ( s_axi_awburst ), + .s_axi_awvalid ( s_axi_awvalid ), + .s_axi_awready ( s_axi_awready ), + .s_axi_wdata ( s_axi_wdata ), + .s_axi_wstrb ( s_axi_wstrb ), + .s_axi_wlast ( s_axi_wlast ), + .s_axi_wvalid ( s_axi_wvalid ), + .s_axi_wready ( s_axi_wready ), + .s_axi_bid ( s_axi_bid ), + .s_axi_bresp ( s_axi_bresp ), + .s_axi_bvalid ( s_axi_bvalid ), + .s_axi_bready ( s_axi_bready ), + .s_axi_arid ( s_axi_arid ), + .s_axi_araddr ( s_axi_araddr ), + .s_axi_arlen ( s_axi_arlen ), + .s_axi_arsize ( s_axi_arsize ), + .s_axi_arburst ( s_axi_arburst ), + .s_axi_arvalid ( s_axi_arvalid ), + .s_axi_arready ( s_axi_arready ), + .s_axi_rid ( s_axi_rid ), + .s_axi_rdata ( s_axi_rdata ), + .s_axi_rresp ( s_axi_rresp ), + .s_axi_rlast ( s_axi_rlast ), + .s_axi_rvalid ( s_axi_rvalid ), + .s_axi_rready ( s_axi_rready ), + .s_axi_awlock ( s_axi_awlock ), + .s_axi_awcache ( s_axi_awcache ), + .s_axi_awprot ( s_axi_awprot ), + .s_axi_awqos ( 0 ), + .s_axi_awregion ( 0 ), + .s_axi_arlock ( s_axi_arlock ), + .s_axi_arcache ( s_axi_arcache ), + .s_axi_arprot ( s_axi_arprot ), + .s_axi_arqos ( 0 ), + .s_axi_arregion ( 0 ), + + // Master to Protocol Converter + .m_axi_awaddr ( to_plic_axi_awaddr ), + .m_axi_awlen ( to_plic_axi_awlen ), + .m_axi_awsize ( to_plic_axi_awsize ), + .m_axi_awburst ( to_plic_axi_awburst ), + .m_axi_awlock ( to_plic_axi_awlock ), + .m_axi_awcache ( to_plic_axi_awcache ), + .m_axi_awprot ( to_plic_axi_awprot ), + .m_axi_awqos ( to_plic_axi_awqos ), + .m_axi_awvalid ( to_plic_axi_awvalid ), + .m_axi_awready ( to_plic_axi_awready ), + .m_axi_wdata ( to_plic_axi_wdata ), + .m_axi_wstrb ( to_plic_axi_wstrb ), + .m_axi_wlast ( to_plic_axi_wlast ), + .m_axi_wvalid ( to_plic_axi_wvalid ), + .m_axi_wready ( to_plic_axi_wready ), + .m_axi_bresp ( to_plic_axi_bresp ), + .m_axi_bvalid ( to_plic_axi_bvalid ), + .m_axi_bready ( to_plic_axi_bready ), + .m_axi_araddr ( to_plic_axi_araddr ), + .m_axi_arlen ( to_plic_axi_arlen ), + .m_axi_arsize ( to_plic_axi_arsize ), + .m_axi_arburst ( to_plic_axi_arburst ), + .m_axi_arlock ( to_plic_axi_arlock ), + .m_axi_arcache ( to_plic_axi_arcache ), + .m_axi_arprot ( to_plic_axi_arprot ), + .m_axi_arqos ( to_plic_axi_arqos ), + .m_axi_arvalid ( to_plic_axi_arvalid ), + .m_axi_arready ( to_plic_axi_arready ), + .m_axi_rdata ( to_plic_axi_rdata ), + .m_axi_rresp ( to_plic_axi_rresp ), + .m_axi_rlast ( to_plic_axi_rlast ), + .m_axi_rvalid ( to_plic_axi_rvalid ), + .m_axi_rready ( to_plic_axi_rready ) + ); + + // Since the AXI data width converter has a reordering depth of 1 it doesn't have ID in its master ports - for more details see the documentation + assign to_plic_axi_awid = '0; + assign to_plic_axi_arid = '0; + + end : gen_axi_32_dwidth_conv + else begin : no_conv + `ASSIGN_AXI_BUS (to_plic, s) + end : no_conv + + //////////////////////////////////////////////// + // Platform-Level Interrupt Controller (PLIC) // + //////////////////////////////////////////////// + + custom_rv_plic custom_rv_plic_u ( + .clk_i ( clk_i ), // input wire s_axi_aclk + .rst_ni ( rst_ni ), // input wire s_axi_aresetn + // AXI4 slave port (from xbar) + .intr_src_i ( intr_src_i ), // Input interrupt lines (Sources) + .irq_o ( irq_o ), // Output Interrupts (Targets -> Socket) + .irq_id_o ( ), // Unused (non standard signal) + .msip_o ( ), // Unused (non standard signal) + .s_axi_awid ( to_plic_axi_awid ), // input wire [1 : 0] s_axi_awid + .s_axi_awaddr ( to_plic_axi_awaddr ), // input wire [25 : 0] s_axi_awaddr + .s_axi_awlen ( to_plic_axi_awlen ), // input wire [7 : 0] s_axi_awlen + .s_axi_awsize ( to_plic_axi_awsize ), // input wire [2 : 0] s_axi_awsize + .s_axi_awburst ( to_plic_axi_awburst ), // input wire [1 : 0] s_axi_awburst + .s_axi_awlock ( to_plic_axi_awlock ), // input wire [0 : 0] s_axi_awlock + .s_axi_awcache ( to_plic_axi_awcache ), // input wire [3 : 0] s_axi_awcache + .s_axi_awprot ( to_plic_axi_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awregion ( to_plic_axi_awregion ), // input wire [3 : 0] s_axi_awregion + .s_axi_awqos ( to_plic_axi_awqos ), // input wire [3 : 0] s_axi_awqos + .s_axi_awvalid ( to_plic_axi_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( to_plic_axi_awready ), // output wire s_axi_awready + .s_axi_wdata ( to_plic_axi_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( to_plic_axi_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wlast ( to_plic_axi_wlast ), // input wire s_axi_wlast + .s_axi_wvalid ( to_plic_axi_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( to_plic_axi_wready ), // output wire s_axi_wready + .s_axi_bid ( to_plic_axi_bid ), // output wire [1 : 0] s_axi_bid + .s_axi_bresp ( to_plic_axi_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( to_plic_axi_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( to_plic_axi_bready ), // input wire s_axi_bready + .s_axi_arid ( to_plic_axi_arid ), // input wire [1 : 0] s_axi_arid + .s_axi_araddr ( to_plic_axi_araddr ), // input wire [25 : 0] s_axi_araddr + .s_axi_arlen ( to_plic_axi_arlen ), // input wire [7 : 0] s_axi_arlen + .s_axi_arsize ( to_plic_axi_arsize ), // input wire [2 : 0] s_axi_arsize + .s_axi_arburst ( to_plic_axi_arburst ), // input wire [1 : 0] s_axi_arburst + .s_axi_arlock ( to_plic_axi_arlock ), // input wire [0 : 0] s_axi_arlock + .s_axi_arcache ( to_plic_axi_arcache ), // input wire [3 : 0] s_axi_arcache + .s_axi_arprot ( to_plic_axi_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arregion ( to_plic_axi_arregion ), // input wire [3 : 0] s_axi_arregion + .s_axi_arqos ( to_plic_axi_arqos ), // input wire [3 : 0] s_axi_arqos + .s_axi_arvalid ( to_plic_axi_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( to_plic_axi_arready ), // output wire s_axi_arready + .s_axi_rid ( to_plic_axi_rid ), // output wire [1 : 0] s_axi_rid + .s_axi_rdata ( to_plic_axi_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( to_plic_axi_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rlast ( to_plic_axi_rlast ), // output wire s_axi_rlast + .s_axi_rvalid ( to_plic_axi_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( to_plic_axi_rready ) + ); + + +endmodule + + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/rv_socket.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/rv_socket.sv new file mode 100644 index 0000000000000000000000000000000000000000..c4690a9ef14233948baff4c7517a5c7920bc4228 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/rv_socket.sv @@ -0,0 +1,1647 @@ +// Author: Stefano Mercogliano +// Author: Vincenzo Maisto +// Author: Cesare Pulcrano +// Author: Salvatore Santoro +// Author: Alessandra Maraia +// Description: Wrapper module for RISC-V CPUs and Debuggers + +// Import packages +import uninasoc_pkg::*; + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_mem.svh" + +module rv_socket # ( + parameter core_selector_t CORE_SELECTOR = CORE_CV32E40P, + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 2, + parameter int unsigned NUM_IRQ = 32 +) ( + input logic clk_i, + input logic rst_ni, // System-wide reset (also resets core) + input logic core_resetn_i, // Core-only reset (does not reset DM and other modules) + input logic [LOCAL_ADDR_WIDTH -1 : 0 ] bootaddr_i, + input logic [NUM_IRQ -1 : 0 ] irq_i, + + // Core 0 + `DEFINE_AXI_MASTER_PORTS(rv_socket_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + `DEFINE_AXI_MASTER_PORTS(rv_socket_data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + + // Core 1 + `DEFINE_AXI_MASTER_PORTS(rv_socket_instr1, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + `DEFINE_AXI_MASTER_PORTS(rv_socket_data1, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + + // Debug module + `DEFINE_AXI_MASTER_PORTS(rv_socket_dbg_master, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH), + `DEFINE_AXI_SLAVE_PORTS(rv_socket_dbg_slave, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) + +); + + ////////////////////////////////////////////////////// + // ___ _ // + // | _ \__ _ _ _ __ _ _ __ ___| |_ ___ _ _ ___ // + // | _/ _` | '_/ _` | ' \/ -_) _/ -_) '_(_-< // + // |_| \__,_|_| \__,_|_|_|_\___|\__\___|_| /__/ // + // // + ////////////////////////////////////////////////////// + + // Let's assume single core + localparam logic [LOCAL_DATA_WIDTH-1:0] hart_id = '0; + localparam logic [LOCAL_ADDR_WIDTH-1:0] DEBUG_START = 'h10000; // From config + + // From dm_pkg + localparam logic [LOCAL_ADDR_WIDTH-1:0] dm_HaltAddress = 'h800; + localparam logic [LOCAL_ADDR_WIDTH-1:0] dm_ExceptionAddress = dm_HaltAddress + 16; + + ////////////////////////////////////// + // ___ _ _ // + // / __(_)__ _ _ _ __ _| |___ // + // \__ | / _` | ' \/ _` | (_-< // + // |___|_\__, |_||_\__,_|_/__/ // + // |___/ // + ////////////////////////////////////// + + // Core reset + logic core_resetn_internal; + assign core_resetn_internal = rst_ni & core_resetn_i; + + // Declare AXI interfaces for instruction memory port and data memory port + `DECLARE_AXI_BUS(core_instr_to_socket_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXI_BUS(core_data_to_socket_data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // Declare MEM ports + `DECLARE_MEM_BUS(core_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH); + `DECLARE_MEM_BUS(core_data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH); + + // Debug request DM -> RV core + logic debug_req_core; + + ////////////////////////////////////////////////////// + // ___ ___ _ // + // / __|___ _ _ ___ | _ \___ __ _(_)___ _ _ // + // | (__/ _ \ '_/ -_) | / -_) _` | / _ \ ' \ // + // \___\___/_| \___| |_|_\___\__, |_\___/_||_| // + // |___/ // + ////////////////////////////////////////////////////// + + //////////////////////////// + // Core validity checking // + //////////////////////////// + + // Check if the selected Core is compatible with the system XLEN + if ( LOCAL_DATA_WIDTH == 64 && CORE_SELECTOR inside {CORE_PICORV32,CORE_CV32E40P,CORE_IBEX,CORE_MICROBLAZEV_RV32,CORE_DUAL_MICROBLAZEV_RV32} || + LOCAL_DATA_WIDTH == 32 && CORE_SELECTOR inside {CORE_CV64A6, CORE_MICROBLAZEV_RV64} ) begin : xlen_core_error + $error($sformatf("[Socket] Illegal CORE (%s) for the selected XLEN (%0d)", + core_selector_to_string(CORE_SELECTOR), LOCAL_DATA_WIDTH)); + end : xlen_core_error + + //////////////////////// + // Core Instantiation // + //////////////////////// + + generate + if (CORE_SELECTOR == CORE_PICORV32) begin: core_picorv32 + + ////////////////////////// + // PicoRV32 // + ////////////////////////// + + // Tie-off unused signals + assign core_instr_mem_wdata = '0; + assign core_instr_mem_we = '0; + assign core_instr_mem_be = '0; + + /////////////////////////////////////////////////////////////////////////// + // Pico has a custom interrupt handling mechanisms. I am not sure if // + // it is just an alternative to standard risc-v interrupt handling, // + // or if it is incompatible. Therefore, beware of it and use Pico // + // only for interrupt-less applications. // + /////////////////////////////////////////////////////////////////////////// + + custom_picorv32 picorv32_core ( + .clk_i ( clk_i ), + .rst_ni ( core_resetn_internal ), + .trap_o ( ), + + .instr_mem_req ( core_instr_mem_req ), + .instr_mem_gnt ( core_instr_mem_gnt ), + .instr_mem_valid ( core_instr_mem_valid ), + .instr_mem_addr ( core_instr_mem_addr ), + .instr_mem_rdata ( core_instr_mem_rdata ), + .instr_mem_error ( core_instr_mem_error ), // Although unused + + .data_mem_req ( core_data_mem_req ), + .data_mem_valid ( core_data_mem_valid ), + .data_mem_gnt ( core_data_mem_gnt ), + .data_mem_we ( core_data_mem_we ), + .data_mem_be ( core_data_mem_be ), + .data_mem_addr ( core_data_mem_addr ), + .data_mem_wdata ( core_data_mem_wdata ), + .data_mem_rdata ( core_data_mem_rdata ), + .data_mem_error ( core_data_mem_error ), // Although unused + + .irq_i ( irq_i ), + + `ifdef RISCV_FORMAL + .rvfi_valid ( ), + .rvfi_order ( ), + .rvfi_insn ( ), + .rvfi_trap ( ), + .rvfi_halt ( ), + .rvfi_intr ( ), + .rvfi_rs1_addr ( ), + .rvfi_rs2_addr ( ), + .rvfi_rs1_rdata ( ), + .rvfi_rs2_rdata ( ), + .rvfi_rd_addr ( ), + .rvfi_rd_wdata ( ), + .rvfi_pc_rdata ( ), + .rvfi_pc_wdata ( ), + .rvfi_mem_addr ( ), + .rvfi_mem_rmask ( ), + .rvfi_mem_wmask ( ), + .rvfi_mem_rdata ( ), + .rvfi_mem_wdata ( ), + `endif + + .trace_valid_o ( ), // Unmapped atm + .trace_data_o ( ) // Unmapped atm + ); + + end + else if (CORE_SELECTOR == CORE_CV32E40P) begin: core_cv32e40p + + ////////////////////////// + // CV32E40P // + ////////////////////////// + + custom_cv32e40p cv32e40p_core ( + // Clock and Reset + .clk_i ( clk_i ), + .rst_ni ( core_resetn_internal ), + + .pulp_clock_en_i ( '0 ), // PULP clock enable (only used if COREV_CLUSTER = 1) + .scan_cg_en_i ( '0 ), // Enable all clock gates for testing + + // Core ID, Cluster ID, debug mode halt address and boot address are considered more or less static + .boot_addr_i ( bootaddr_i ), + .hart_id_i ( hart_id ), + .mtvec_addr_i ( '0 ), // TBD + .dm_halt_addr_i ( DEBUG_START + dm_HaltAddress[31:0] ), // TBD + .dm_exception_addr_i ( DEBUG_START + dm_ExceptionAddress[31:0] ), // TBD + + // Instruction memory interface + .instr_mem_req ( core_instr_mem_req ), + .instr_mem_gnt ( core_instr_mem_gnt ), + .instr_mem_valid ( core_instr_mem_valid ), + .instr_mem_addr ( core_instr_mem_addr ), + .instr_mem_be ( core_instr_mem_be ), + .instr_mem_we ( core_instr_mem_we ), + .instr_mem_wdata ( core_instr_mem_wdata ), + .instr_mem_rdata ( core_instr_mem_rdata ), + .instr_mem_error ( core_instr_mem_error ), // Although unused + + // Data memory interface + .data_mem_req ( core_data_mem_req ), + .data_mem_valid ( core_data_mem_valid ), + .data_mem_gnt ( core_data_mem_gnt ), + .data_mem_we ( core_data_mem_we ), + .data_mem_be ( core_data_mem_be ), + .data_mem_addr ( core_data_mem_addr ), + .data_mem_wdata ( core_data_mem_wdata ), + .data_mem_rdata ( core_data_mem_rdata ), + .data_mem_error ( core_data_mem_error ), // Although unused + + // Interrupt inputs + .irq_i ( irq_i ), // CLINT interrupts + CLINT extension interrupts + .irq_ack_o ( ), // TBD + .irq_id_o ( ), // TBD + + // Debug Interface + .debug_req_i ( debug_req_core ), // From Debug Module + .debug_havereset_o ( debug_havereset_o ), // Open + .debug_running_o ( debug_running_o ), // Open + .debug_halted_o ( debug_halted_o ), // Open + + // CPU Control Signals + .fetch_enable_i ( 1'b1 ), + .core_sleep_o ( ) // TBD + ); + + end + else if (CORE_SELECTOR == CORE_IBEX) begin : core_ibex + + ////////////////////// + // Ibex // + ////////////////////// + + custom_ibex ibex_core ( + // Clock and Reset + .clk_i ( clk_i ), + .rst_ni ( core_resetn_internal ), + .hart_id_i ( hart_id ), + // First instruction executed is going to be at boot_addr_i + 0x80 (i.e. right after the vector table) + .boot_addr_i ( bootaddr_i ), + + // Instruction memory interface + .instr_mem_req ( core_instr_mem_req ), + .instr_mem_gnt ( core_instr_mem_gnt ), + .instr_mem_valid ( core_instr_mem_valid ), + .instr_mem_addr ( core_instr_mem_addr ), + .instr_mem_be ( core_instr_mem_be ), + .instr_mem_we ( core_instr_mem_we ), + .instr_mem_wdata ( core_instr_mem_wdata ), + .instr_mem_rdata ( core_instr_mem_rdata ), + .instr_mem_error ( core_instr_mem_error ), // Although unused + + // Data memory interface + .data_mem_req ( core_data_mem_req ), + .data_mem_valid ( core_data_mem_valid ), + .data_mem_gnt ( core_data_mem_gnt ), + .data_mem_we ( core_data_mem_we ), + .data_mem_be ( core_data_mem_be ), + .data_mem_addr ( core_data_mem_addr ), + .data_mem_wdata ( core_data_mem_wdata ), + .data_mem_rdata ( core_data_mem_rdata ), + .data_mem_error ( core_data_mem_error ), // Although unused + + .irq_software_i ( irq_i[CORE_SW_INTERRUPT] ), + .irq_timer_i ( irq_i[CORE_TIM_INTERRUPT] ), + .irq_external_i ( irq_i[CORE_EXT_INTERRUPT] ), + .irq_fast_i ( '0 ), + .irq_nm_i ( '0 ), + + .debug_req_i ( debug_req_core ) + + ); + end + else if (CORE_SELECTOR == CORE_MICROBLAZEV_RV32) begin : xlnx_microblazev_rv32 + + // Tie-off unused signals + assign core_instr_mem_wdata = '0; + assign core_instr_mem_we = '0; + assign core_instr_mem_be = '0; + + ////////////////////////// + // MICROBLAZE RV32 // + ////////////////////////// + + // Debug interface connections definition + logic dbg_sys_rst; + logic Dbg_Clk; // wire Dbg_Clk_0 + logic Dbg_TDI; // wire Dbg_TDI_0 + logic Dbg_TDO; // wire Dbg_TDO_0 + logic [0:7] Dbg_Reg_En; // wire [0 : 7] Dbg_Reg_En_0 + logic Dbg_Capture; // wire Dbg_Capture_0 + logic Dbg_Shift; // wire Dbg_Shift_0 + logic Dbg_Update; // wire Dbg_Update_0 + logic Dbg_Rst; // wire Dbg_Rst_0 + logic Dbg_Disable; // wire Dbg_Disable_0 + + + // Declare AXI interfaces for instruction memory port and data memory port for MicroblazeV + `DECLARE_AXI_BUS(microblaze_data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXILITE_BUS(microblaze_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // Declare AXI interface for Protocol Converter + `DECLARE_AXI_BUS(converter_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // MICROBLAZE-V RV32 instance + xlnx_microblazev_rv32 microblazev_u ( + // Clock and reset + .Clk ( clk_i ), // input wire Clk + .Reset ( dbg_sys_rst ), // input wire Reset + + // Interrupts + // Ublaze can only take one external interrupt, which we tie to EXT interrupt (from the PLIC) + .Interrupt ( irq_i[CORE_EXT_INTERRUPT] ), // input wire Interrupt + .Interrupt_Address ('0 ), // input wire [0 : 31] Interrupt_Address + .Interrupt_Ack ( ), // output wire [0 : 1] Interrupt_Ack + + // Debug port to MDMV + .Dbg_Clk ( Dbg_Clk ), // input wire Dbg_Clk + .Dbg_TDI ( Dbg_TDI ), // input wire Dbg_TDI + .Dbg_TDO ( Dbg_TDO ), // output wire Dbg_TDO + .Dbg_Reg_En ( Dbg_Reg_En ), // input wire [0 : 7] Dbg_Reg_En + .Dbg_Shift ( Dbg_Shift ), // input wire Dbg_Shift + .Dbg_Capture ( Dbg_Capture ), // input wire Dbg_Capture + .Dbg_Update ( Dbg_Update ), // input wire Dbg_Update + .Debug_Rst ( Dbg_Rst ), // input wire Debug_Rst + .Dbg_Disable ( Dbg_Disable ), // input wire Dbg_Disable + + // Data port (AXI) + .M_AXI_DP_AWADDR ( microblaze_data_axi_awaddr ), // output wire [31 : 0] M_AXI_DP_AWADDR + .M_AXI_DP_AWLEN ( microblaze_data_axi_awlen ), // output wire [7 : 0] M_AXI_DP_AWLEN + .M_AXI_DP_AWSIZE ( microblaze_data_axi_awsize ), // output wire [2 : 0] M_AXI_DP_AWSIZE + .M_AXI_DP_AWBURST ( microblaze_data_axi_awburst ), // output wire [1 : 0] M_AXI_DP_AWBURST + .M_AXI_DP_AWLOCK ( microblaze_data_axi_awlock ), // output wire M_AXI_DP_AWLOCK + .M_AXI_DP_AWCACHE ( microblaze_data_axi_awcache ), // output wire [3 : 0] M_AXI_DP_AWCACHE + .M_AXI_DP_AWPROT ( microblaze_data_axi_awprot ), // output wire [2 : 0] M_AXI_DP_AWPROT + .M_AXI_DP_AWQOS ( microblaze_data_axi_awqos ), // output wire [3 : 0] M_AXI_DP_AWQOS + .M_AXI_DP_AWVALID ( microblaze_data_axi_awvalid ), // output wire M_AXI_DP_AWVALID + .M_AXI_DP_AWREADY ( microblaze_data_axi_awready ), // input wire M_AXI_DP_AWREADY + .M_AXI_DP_WDATA ( microblaze_data_axi_wdata ), // output wire [31 : 0] M_AXI_DP_WDATA + .M_AXI_DP_WSTRB ( microblaze_data_axi_wstrb ), // output wire [3 : 0] M_AXI_DP_WSTRB + .M_AXI_DP_WLAST ( microblaze_data_axi_wlast ), // output wire M_AXI_DP_WLAST + .M_AXI_DP_WVALID ( microblaze_data_axi_wvalid ), // output wire M_AXI_DP_WVALID + .M_AXI_DP_WREADY ( microblaze_data_axi_wready ), // input wire M_AXI_DP_WREADY + .M_AXI_DP_BRESP ( microblaze_data_axi_bresp ), // input wire [1 : 0] M_AXI_DP_BRESP + .M_AXI_DP_BVALID ( microblaze_data_axi_bvalid ), // input wire M_AXI_DP_BVALID + .M_AXI_DP_BREADY ( microblaze_data_axi_bready ), // output wire M_AXI_DP_BREADY + .M_AXI_DP_ARADDR ( microblaze_data_axi_araddr ), // output wire [31 : 0] M_AXI_DP_ARADDR + .M_AXI_DP_ARLEN ( microblaze_data_axi_arlen ), // output wire [7 : 0] M_AXI_DP_ARLEN + .M_AXI_DP_ARSIZE ( microblaze_data_axi_arsize ), // output wire [2 : 0] M_AXI_DP_ARSIZE + .M_AXI_DP_ARBURST ( microblaze_data_axi_arburst ), // output wire [1 : 0] M_AXI_DP_ARBURST + .M_AXI_DP_ARLOCK ( microblaze_data_axi_arlock ), // output wire M_AXI_DP_ARLOCK + .M_AXI_DP_ARCACHE ( microblaze_data_axi_arcache ), // output wire [3 : 0] M_AXI_DP_ARCACHE + .M_AXI_DP_ARPROT ( microblaze_data_axi_arprot ), // output wire [2 : 0] M_AXI_DP_ARPROT + .M_AXI_DP_ARQOS ( microblaze_data_axi_arqos ), // output wire [3 : 0] M_AXI_DP_ARQOS + .M_AXI_DP_ARVALID ( microblaze_data_axi_arvalid ), // output wire M_AXI_DP_ARVALID + .M_AXI_DP_ARREADY ( microblaze_data_axi_arready ), // input wire M_AXI_DP_ARREADY + .M_AXI_DP_RDATA ( microblaze_data_axi_rdata ), // input wire [31 : 0] M_AXI_DP_RDATA + .M_AXI_DP_RRESP ( microblaze_data_axi_rresp ), // input wire [1 : 0] M_AXI_DP_RRESP + .M_AXI_DP_RLAST ( microblaze_data_axi_rlast ), // input wire M_AXI_DP_RLAST + .M_AXI_DP_RVALID ( microblaze_data_axi_rvalid ), // input wire M_AXI_DP_RVALID + .M_AXI_DP_RREADY ( microblaze_data_axi_rready ), // output wire M_AXI_DP_RREADY + + // Instruction port (AXI-lite) + .M_AXI_IP_AWADDR ( microblaze_instr_axilite_awaddr ), // output wire [31 : 0] M_AXI_IP_AWADDR + .M_AXI_IP_AWPROT ( microblaze_instr_axilite_awprot ), // output wire [2 : 0] M_AXI_IP_AWPROT + .M_AXI_IP_AWVALID ( microblaze_instr_axilite_awvalid ), // output wire M_AXI_IP_AWVALID + .M_AXI_IP_AWREADY ( microblaze_instr_axilite_awready ), // input wire M_AXI_IP_AWREADY + .M_AXI_IP_WDATA ( microblaze_instr_axilite_wdata ), // output wire [31 : 0] M_AXI_IP_WDATA + .M_AXI_IP_WSTRB ( microblaze_instr_axilite_wstrb ), // output wire [3 : 0] M_AXI_IP_WSTRB + .M_AXI_IP_WVALID ( microblaze_instr_axilite_wvalid ), // output wire M_AXI_IP_WVALID + .M_AXI_IP_WREADY ( microblaze_instr_axilite_wready ), // input wire M_AXI_IP_WREADY + .M_AXI_IP_BRESP ( microblaze_instr_axilite_bresp ), // input wire [1 : 0] M_AXI_IP_BRESP + .M_AXI_IP_BVALID ( microblaze_instr_axilite_bvalid ), // input wire M_AXI_IP_BVALID + .M_AXI_IP_BREADY ( microblaze_instr_axilite_bready ), // output wire M_AXI_IP_BREADY + .M_AXI_IP_ARADDR ( microblaze_instr_axilite_araddr ), // output wire [31 : 0] M_AXI_IP_ARADDR + .M_AXI_IP_ARPROT ( microblaze_instr_axilite_arprot ), // output wire [2 : 0] M_AXI_IP_ARPROT + .M_AXI_IP_ARVALID ( microblaze_instr_axilite_arvalid ), // output wire M_AXI_IP_ARVALID + .M_AXI_IP_ARREADY ( microblaze_instr_axilite_arready ), // input wire M_AXI_IP_ARREADY + .M_AXI_IP_RDATA ( microblaze_instr_axilite_rdata ), // input wire [31 : 0] M_AXI_IP_RDATA + .M_AXI_IP_RRESP ( microblaze_instr_axilite_rresp ), // input wire [1 : 0] M_AXI_IP_RRESP + .M_AXI_IP_RVALID ( microblaze_instr_axilite_rvalid ), // input wire M_AXI_IP_RVALID + .M_AXI_IP_RREADY ( microblaze_instr_axilite_rready ) // output wire M_AXI_IP_RREADY + ); + + // Microblaze Debug Module V + xlnx_microblaze_debug_module_v mdmv_u ( + .Debug_SYS_Rst ( dbg_sys_rst ), // output wire Debug_SYS_Rst + .Dbg_Clk_0 ( Dbg_Clk ), // output wire Dbg_Clk_0 + .Dbg_TDI_0 ( Dbg_TDI ), // output wire Dbg_TDI_0 + .Dbg_TDO_0 ( Dbg_TDO ), // input wire Dbg_TDO_0 + .Dbg_Reg_En_0 ( Dbg_Reg_En ), // output wire [0 : 7] Dbg_Reg_En_0 + .Dbg_Capture_0 ( Dbg_Capture ), // output wire Dbg_Capture_0 + .Dbg_Shift_0 ( Dbg_Shift ), // output wire Dbg_Shift_0 + .Dbg_Update_0 ( Dbg_Update ), // output wire Dbg_Update_0 + .Dbg_Rst_0 ( Dbg_Rst ), // output wire Dbg_Rst_0 + .Dbg_Disable_0 ( Dbg_Disable ) // output wire Dbg_Disable_0 + ); + + + // Attach to socket + `ASSIGN_AXI_BUS(rv_socket_data , microblaze_data); + `ASSIGN_AXI_BUS(rv_socket_instr , converter_instr); + + // Tie-off undriven ID signals + // ID's are set to zero since they are not present in microblaze, while the crossbar have ID's of size 2. + // Instruction + assign converter_instr_axi_awid = '0; + assign converter_instr_axi_arid = '0; + // Data + assign microblaze_data_axi_awid = '0; + assign microblaze_data_axi_arid = '0; + + // Regions are not present in microblaze data implementation so they are set to 0. + assign microblaze_data_axi_awregion ='0; + assign microblaze_data_axi_arregion ='0; + + // Convert from MICROBLAZE-V (AXI-lite) to socket (AXI) + // Only instruction port (AXI-lite), data port is socket compliant (AXI) + xlnx_axilite_to_axi4_d32_converter axilite_to_axi4_converter_u ( + .aclk ( clk_i ), // input wire aclk + .aresetn ( rst_ni ), // input wire aresetn + // From Microblaze (AXI-lite) + .s_axi_awaddr ( microblaze_instr_axilite_awaddr ), // input wire [31 : 0] s_axi_awaddr + .s_axi_awprot ( microblaze_instr_axilite_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awvalid ( microblaze_instr_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( microblaze_instr_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( microblaze_instr_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( microblaze_instr_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( microblaze_instr_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( microblaze_instr_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( microblaze_instr_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( microblaze_instr_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( microblaze_instr_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( microblaze_instr_axilite_araddr ), // input wire [31 : 0] s_axi_araddr + .s_axi_arprot ( microblaze_instr_axilite_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arvalid ( microblaze_instr_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( microblaze_instr_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( microblaze_instr_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( microblaze_instr_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( microblaze_instr_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( microblaze_instr_axilite_rready ), // input wire s_axi_rready + // To socket (AXI) + .m_axi_awaddr ( converter_instr_axi_awaddr ), // output wire [31 : 0] m_axi_awaddr + .m_axi_awlen ( converter_instr_axi_awlen ), // output wire [7 : 0] m_axi_awlen + .m_axi_awsize ( converter_instr_axi_awsize ), // output wire [2 : 0] m_axi_awsize + .m_axi_awburst ( converter_instr_axi_awburst ), // output wire [1 : 0] m_axi_awburst + .m_axi_awlock ( converter_instr_axi_awlock ), // output wire [0 : 0] m_axi_awlock + .m_axi_awcache ( converter_instr_axi_awcache ), // output wire [3 : 0] m_axi_awcache + .m_axi_awprot ( converter_instr_axi_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awregion ( converter_instr_axi_awregion ), // output wire [3 : 0] m_axi_awregion + .m_axi_awqos ( converter_instr_axi_awqos ), // output wire [3 : 0] m_axi_awqos + .m_axi_awvalid ( converter_instr_axi_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( converter_instr_axi_awready ), // input wire m_axi_awready + .m_axi_wdata ( converter_instr_axi_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( converter_instr_axi_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wlast ( converter_instr_axi_wlast ), // output wire m_axi_wlast + .m_axi_wvalid ( converter_instr_axi_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( converter_instr_axi_wready ), // input wire m_axi_wready + .m_axi_bresp ( converter_instr_axi_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( converter_instr_axi_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( converter_instr_axi_bready ), // output wire m_axi_bready + .m_axi_araddr ( converter_instr_axi_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arlen ( converter_instr_axi_arlen ), // output wire [7 : 0] m_axi_arlen + .m_axi_arsize ( converter_instr_axi_arsize ), // output wire [2 : 0] m_axi_arsize + .m_axi_arburst ( converter_instr_axi_arburst ), // output wire [1 : 0] m_axi_arburst + .m_axi_arlock ( converter_instr_axi_arlock ), // output wire [0 : 0] m_axi_arlock + .m_axi_arcache ( converter_instr_axi_arcache ), // output wire [3 : 0] m_axi_arcache + .m_axi_arprot ( converter_instr_axi_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arregion ( converter_instr_axi_arregion ), // output wire [3 : 0] m_axi_arregion + .m_axi_arqos ( converter_instr_axi_arqos ), // output wire [3 : 0] m_axi_arqos + .m_axi_arvalid ( converter_instr_axi_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( converter_instr_axi_arready ), // input wire m_axi_arready + .m_axi_rdata ( converter_instr_axi_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( converter_instr_axi_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rlast ( converter_instr_axi_rlast ), // input wire m_axi_rlast + .m_axi_rvalid ( converter_instr_axi_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( converter_instr_axi_rready ) // output wire m_axi_rready + ); + end : xlnx_microblazev_rv32 + else if (CORE_SELECTOR == CORE_DUAL_MICROBLAZEV_RV32) begin : xlnx_dual_microblazev_rv32 + + // Tie-off unused signals + assign core_instr_mem_wdata = '0; + assign core_instr_mem_we = '0; + assign core_instr_mem_be = '0; + + ////////////////////////// + // DUAL MICROBLAZE RV32 // + ////////////////////////// + // TODO: export this eventually + localparam int unsigned NUM_CORES = 2; + + // Debug interface connections definition + logic [NUM_CORES-1 : 0] dbg_sys_rst; + logic [NUM_CORES-1 : 0] Dbg_Clk; // wire Dbg_Clk_0 + logic [NUM_CORES-1 : 0] Dbg_TDI; // wire Dbg_TDI_0 + logic [NUM_CORES-1 : 0] Dbg_TDO; // wire Dbg_TDO_0 + logic [NUM_CORES-1 : 0][0:7] Dbg_Reg_En; // wire [0 : 7] Dbg_Reg_En_0 + logic [NUM_CORES-1 : 0] Dbg_Capture; // wire Dbg_Capture_0 + logic [NUM_CORES-1 : 0] Dbg_Shift; // wire Dbg_Shift_0 + logic [NUM_CORES-1 : 0] Dbg_Update; // wire Dbg_Update_0 + logic [NUM_CORES-1 : 0] Dbg_Rst; // wire Dbg_Rst_0 + logic [NUM_CORES-1 : 0] Dbg_Disable; // wire Dbg_Disable_0 + + // Declare AXI interfaces for instruction memory port and data memory port for MicroblazeV + `DECLARE_AXI_BUS(microblaze0_data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXI_BUS(microblaze1_data, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXILITE_BUS(microblaze0_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXILITE_BUS(microblaze1_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + // Declare AXI interface for Protocol Converter + `DECLARE_AXI_BUS(converter0_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXI_BUS(converter1_instr, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // MICROBLAZE-V RV32 instance + xlnx_microblazev_rv32 microblazev_u0 ( + // Clock and reset + .Clk ( clk_i ), // input wire Clk + .Reset ( dbg_sys_rst ), // input wire Reset + // Interrupts + // Ublaze can only take one external interrupt, which we tie to EXT interrupt (from the PLIC) + .Interrupt ( irq_i[CORE_EXT_INTERRUPT] ), // input wire Interrupt + .Interrupt_Address ('0 ), // input wire [0 : 31] Interrupt_Address + .Interrupt_Ack ( ), // output wire [0 : 1] Interrupt_Ack + // Debug port to MDM-V (core 0) + .Dbg_Clk ( Dbg_Clk [0] ), // input wire Dbg_Clk + .Dbg_TDI ( Dbg_TDI [0] ), // input wire Dbg_TDI + .Dbg_TDO ( Dbg_TDO [0] ), // output wire Dbg_TDO + .Dbg_Reg_En ( Dbg_Reg_En [0] ), // input wire [0 : 7] Dbg_Reg_En + .Dbg_Shift ( Dbg_Shift [0] ), // input wire Dbg_Shift + .Dbg_Capture ( Dbg_Capture [0] ), // input wire Dbg_Capture + .Dbg_Update ( Dbg_Update [0] ), // input wire Dbg_Update + .Debug_Rst ( Dbg_Rst [0] ), // input wire Debug_Rst + .Dbg_Disable ( Dbg_Disable [0] ), // input wire Dbg_Disable + // Data port (AXI) + .M_AXI_DP_AWADDR ( microblaze0_data_axi_awaddr ), // output wire [31 : 0] M_AXI_DP_AWADDR + .M_AXI_DP_AWLEN ( microblaze0_data_axi_awlen ), // output wire [7 : 0] M_AXI_DP_AWLEN + .M_AXI_DP_AWSIZE ( microblaze0_data_axi_awsize ), // output wire [2 : 0] M_AXI_DP_AWSIZE + .M_AXI_DP_AWBURST ( microblaze0_data_axi_awburst ), // output wire [1 : 0] M_AXI_DP_AWBURST + .M_AXI_DP_AWLOCK ( microblaze0_data_axi_awlock ), // output wire M_AXI_DP_AWLOCK + .M_AXI_DP_AWCACHE ( microblaze0_data_axi_awcache ), // output wire [3 : 0] M_AXI_DP_AWCACHE + .M_AXI_DP_AWPROT ( microblaze0_data_axi_awprot ), // output wire [2 : 0] M_AXI_DP_AWPROT + .M_AXI_DP_AWQOS ( microblaze0_data_axi_awqos ), // output wire [3 : 0] M_AXI_DP_AWQOS + .M_AXI_DP_AWVALID ( microblaze0_data_axi_awvalid ), // output wire M_AXI_DP_AWVALID + .M_AXI_DP_AWREADY ( microblaze0_data_axi_awready ), // input wire M_AXI_DP_AWREADY + .M_AXI_DP_WDATA ( microblaze0_data_axi_wdata ), // output wire [31 : 0] M_AXI_DP_WDATA + .M_AXI_DP_WSTRB ( microblaze0_data_axi_wstrb ), // output wire [3 : 0] M_AXI_DP_WSTRB + .M_AXI_DP_WLAST ( microblaze0_data_axi_wlast ), // output wire M_AXI_DP_WLAST + .M_AXI_DP_WVALID ( microblaze0_data_axi_wvalid ), // output wire M_AXI_DP_WVALID + .M_AXI_DP_WREADY ( microblaze0_data_axi_wready ), // input wire M_AXI_DP_WREADY + .M_AXI_DP_BRESP ( microblaze0_data_axi_bresp ), // input wire [1 : 0] M_AXI_DP_BRESP + .M_AXI_DP_BVALID ( microblaze0_data_axi_bvalid ), // input wire M_AXI_DP_BVALID + .M_AXI_DP_BREADY ( microblaze0_data_axi_bready ), // output wire M_AXI_DP_BREADY + .M_AXI_DP_ARADDR ( microblaze0_data_axi_araddr ), // output wire [31 : 0] M_AXI_DP_ARADDR + .M_AXI_DP_ARLEN ( microblaze0_data_axi_arlen ), // output wire [7 : 0] M_AXI_DP_ARLEN + .M_AXI_DP_ARSIZE ( microblaze0_data_axi_arsize ), // output wire [2 : 0] M_AXI_DP_ARSIZE + .M_AXI_DP_ARBURST ( microblaze0_data_axi_arburst ), // output wire [1 : 0] M_AXI_DP_ARBURST + .M_AXI_DP_ARLOCK ( microblaze0_data_axi_arlock ), // output wire M_AXI_DP_ARLOCK + .M_AXI_DP_ARCACHE ( microblaze0_data_axi_arcache ), // output wire [3 : 0] M_AXI_DP_ARCACHE + .M_AXI_DP_ARPROT ( microblaze0_data_axi_arprot ), // output wire [2 : 0] M_AXI_DP_ARPROT + .M_AXI_DP_ARQOS ( microblaze0_data_axi_arqos ), // output wire [3 : 0] M_AXI_DP_ARQOS + .M_AXI_DP_ARVALID ( microblaze0_data_axi_arvalid ), // output wire M_AXI_DP_ARVALID + .M_AXI_DP_ARREADY ( microblaze0_data_axi_arready ), // input wire M_AXI_DP_ARREADY + .M_AXI_DP_RDATA ( microblaze0_data_axi_rdata ), // input wire [31 : 0] M_AXI_DP_RDATA + .M_AXI_DP_RRESP ( microblaze0_data_axi_rresp ), // input wire [1 : 0] M_AXI_DP_RRESP + .M_AXI_DP_RLAST ( microblaze0_data_axi_rlast ), // input wire M_AXI_DP_RLAST + .M_AXI_DP_RVALID ( microblaze0_data_axi_rvalid ), // input wire M_AXI_DP_RVALID + .M_AXI_DP_RREADY ( microblaze0_data_axi_rready ), // output wire M_AXI_DP_RREADY + // Instruction port (AXI-lite) + .M_AXI_IP_AWADDR ( microblaze0_instr_axilite_awaddr ), // output wire [31 : 0] M_AXI_IP_AWADDR + .M_AXI_IP_AWPROT ( microblaze0_instr_axilite_awprot ), // output wire [2 : 0] M_AXI_IP_AWPROT + .M_AXI_IP_AWVALID ( microblaze0_instr_axilite_awvalid ), // output wire M_AXI_IP_AWVALID + .M_AXI_IP_AWREADY ( microblaze0_instr_axilite_awready ), // input wire M_AXI_IP_AWREADY + .M_AXI_IP_WDATA ( microblaze0_instr_axilite_wdata ), // output wire [31 : 0] M_AXI_IP_WDATA + .M_AXI_IP_WSTRB ( microblaze0_instr_axilite_wstrb ), // output wire [3 : 0] M_AXI_IP_WSTRB + .M_AXI_IP_WVALID ( microblaze0_instr_axilite_wvalid ), // output wire M_AXI_IP_WVALID + .M_AXI_IP_WREADY ( microblaze0_instr_axilite_wready ), // input wire M_AXI_IP_WREADY + .M_AXI_IP_BRESP ( microblaze0_instr_axilite_bresp ), // input wire [1 : 0] M_AXI_IP_BRESP + .M_AXI_IP_BVALID ( microblaze0_instr_axilite_bvalid ), // input wire M_AXI_IP_BVALID + .M_AXI_IP_BREADY ( microblaze0_instr_axilite_bready ), // output wire M_AXI_IP_BREADY + .M_AXI_IP_ARADDR ( microblaze0_instr_axilite_araddr ), // output wire [31 : 0] M_AXI_IP_ARADDR + .M_AXI_IP_ARPROT ( microblaze0_instr_axilite_arprot ), // output wire [2 : 0] M_AXI_IP_ARPROT + .M_AXI_IP_ARVALID ( microblaze0_instr_axilite_arvalid ), // output wire M_AXI_IP_ARVALID + .M_AXI_IP_ARREADY ( microblaze0_instr_axilite_arready ), // input wire M_AXI_IP_ARREADY + .M_AXI_IP_RDATA ( microblaze0_instr_axilite_rdata ), // input wire [31 : 0] M_AXI_IP_RDATA + .M_AXI_IP_RRESP ( microblaze0_instr_axilite_rresp ), // input wire [1 : 0] M_AXI_IP_RRESP + .M_AXI_IP_RVALID ( microblaze0_instr_axilite_rvalid ), // input wire M_AXI_IP_RVALID + .M_AXI_IP_RREADY ( microblaze0_instr_axilite_rready ) // output wire M_AXI_IP_RREADY + ); + // MICROBLAZE-V RV32 instance - CORE 1 + xlnx_microblazev_rv32 microblazev_u1 ( + // Clock and reset + .Clk ( clk_i ), // input wire Clk + .Reset ( dbg_sys_rst ), // input wire Reset + // Interrupts + .Interrupt ( irq_i[CORE_EXT_INTERRUPT] ), // input wire Interrupt + .Interrupt_Address ('0 ), // input wire [0 : 31] Interrupt_Address + .Interrupt_Ack ( ), // output wire [0 : 1] Interrupt_Ack + // Debug port to MDM-V (core 1) + .Dbg_Clk ( Dbg_Clk [1] ), // input wire Dbg_Clk + .Dbg_TDI ( Dbg_TDI [1] ), // input wire Dbg_TDI + .Dbg_TDO ( Dbg_TDO [1] ), // output wire Dbg_TDO + .Dbg_Reg_En ( Dbg_Reg_En [1] ), // input wire [0 : 7] Dbg_Reg_En + .Dbg_Shift ( Dbg_Shift [1] ), // input wire Dbg_Shift + .Dbg_Capture ( Dbg_Capture [1] ), // input wire Dbg_Capture + .Dbg_Update ( Dbg_Update [1] ), // input wire Dbg_Update + .Debug_Rst ( Dbg_Rst [1] ), // input wire Debug_Rst + .Dbg_Disable ( Dbg_Disable [1] ), // input wire Dbg_Disable + // Data port (AXI) + .M_AXI_DP_AWADDR ( microblaze1_data_axi_awaddr ), + .M_AXI_DP_AWLEN ( microblaze1_data_axi_awlen ), + .M_AXI_DP_AWSIZE ( microblaze1_data_axi_awsize ), + .M_AXI_DP_AWBURST ( microblaze1_data_axi_awburst ), + .M_AXI_DP_AWLOCK ( microblaze1_data_axi_awlock ), + .M_AXI_DP_AWCACHE ( microblaze1_data_axi_awcache ), + .M_AXI_DP_AWPROT ( microblaze1_data_axi_awprot ), + .M_AXI_DP_AWQOS ( microblaze1_data_axi_awqos ), + .M_AXI_DP_AWVALID ( microblaze1_data_axi_awvalid ), + .M_AXI_DP_AWREADY ( microblaze1_data_axi_awready ), + .M_AXI_DP_WDATA ( microblaze1_data_axi_wdata ), + .M_AXI_DP_WSTRB ( microblaze1_data_axi_wstrb ), + .M_AXI_DP_WLAST ( microblaze1_data_axi_wlast ), + .M_AXI_DP_WVALID ( microblaze1_data_axi_wvalid ), + .M_AXI_DP_WREADY ( microblaze1_data_axi_wready ), + .M_AXI_DP_BRESP ( microblaze1_data_axi_bresp ), + .M_AXI_DP_BVALID ( microblaze1_data_axi_bvalid ), + .M_AXI_DP_BREADY ( microblaze1_data_axi_bready ), + .M_AXI_DP_ARADDR ( microblaze1_data_axi_araddr ), + .M_AXI_DP_ARLEN ( microblaze1_data_axi_arlen ), + .M_AXI_DP_ARSIZE ( microblaze1_data_axi_arsize ), + .M_AXI_DP_ARBURST ( microblaze1_data_axi_arburst ), + .M_AXI_DP_ARLOCK ( microblaze1_data_axi_arlock ), + .M_AXI_DP_ARCACHE ( microblaze1_data_axi_arcache ), + .M_AXI_DP_ARPROT ( microblaze1_data_axi_arprot ), + .M_AXI_DP_ARQOS ( microblaze1_data_axi_arqos ), + .M_AXI_DP_ARVALID ( microblaze1_data_axi_arvalid ), + .M_AXI_DP_ARREADY ( microblaze1_data_axi_arready ), + .M_AXI_DP_RDATA ( microblaze1_data_axi_rdata ), + .M_AXI_DP_RRESP ( microblaze1_data_axi_rresp ), + .M_AXI_DP_RLAST ( microblaze1_data_axi_rlast ), + .M_AXI_DP_RVALID ( microblaze1_data_axi_rvalid ), + .M_AXI_DP_RREADY ( microblaze1_data_axi_rready ), + // Instruction port (AXI-lite) + .M_AXI_IP_AWADDR ( microblaze1_instr_axilite_awaddr ), + .M_AXI_IP_AWPROT ( microblaze1_instr_axilite_awprot ), + .M_AXI_IP_AWVALID ( microblaze1_instr_axilite_awvalid ), + .M_AXI_IP_AWREADY ( microblaze1_instr_axilite_awready ), + .M_AXI_IP_WDATA ( microblaze1_instr_axilite_wdata ), + .M_AXI_IP_WSTRB ( microblaze1_instr_axilite_wstrb ), + .M_AXI_IP_WVALID ( microblaze1_instr_axilite_wvalid ), + .M_AXI_IP_WREADY ( microblaze1_instr_axilite_wready ), + .M_AXI_IP_BRESP ( microblaze1_instr_axilite_bresp ), + .M_AXI_IP_BVALID ( microblaze1_instr_axilite_bvalid ), + .M_AXI_IP_BREADY ( microblaze1_instr_axilite_bready ), + .M_AXI_IP_ARADDR ( microblaze1_instr_axilite_araddr ), + .M_AXI_IP_ARPROT ( microblaze1_instr_axilite_arprot ), + .M_AXI_IP_ARVALID ( microblaze1_instr_axilite_arvalid ), + .M_AXI_IP_ARREADY ( microblaze1_instr_axilite_arready ), + .M_AXI_IP_RDATA ( microblaze1_instr_axilite_rdata ), + .M_AXI_IP_RRESP ( microblaze1_instr_axilite_rresp ), + .M_AXI_IP_RVALID ( microblaze1_instr_axilite_rvalid ), + .M_AXI_IP_RREADY ( microblaze1_instr_axilite_rready ) + ); + + // Microblaze Debug Module V + xlnx_dual_microblaze_debug_module_v mdmv_u ( + .Debug_SYS_Rst ( dbg_sys_rst ), // output wire Debug_SYS_Rst + // Port CORE 0 + .Dbg_Clk_0 ( Dbg_Clk [0] ), // output wire Dbg_Clk_0 + .Dbg_TDI_0 ( Dbg_TDI [0] ), // output wire Dbg_TDI_0 + .Dbg_TDO_0 ( Dbg_TDO [0] ), // input wire Dbg_TDO_0 + .Dbg_Reg_En_0 ( Dbg_Reg_En [0] ), // output wire [0 : 7] Dbg_Reg_En_0 + .Dbg_Capture_0 ( Dbg_Capture [0] ), // output wire Dbg_Capture_0 + .Dbg_Shift_0 ( Dbg_Shift [0] ), // output wire Dbg_Shift_0 + .Dbg_Update_0 ( Dbg_Update [0] ), // output wire Dbg_Update_0 + .Dbg_Rst_0 ( Dbg_Rst [0] ), // output wire Dbg_Rst_0 + .Dbg_Disable_0 ( Dbg_Disable [0] ), // output wire Dbg_Disable_0 + // Port CORE 1 + .Dbg_Clk_1 ( Dbg_Clk [1] ), // output wire Dbg_Clk_1 + .Dbg_TDI_1 ( Dbg_TDI [1] ), // output wire Dbg_TDI_1 + .Dbg_TDO_1 ( Dbg_TDO [1] ), // input wire Dbg_TDO_1 + .Dbg_Reg_En_1 ( Dbg_Reg_En [1] ), // output wire [0 : 7] Dbg_Reg_En_ + .Dbg_Capture_1 ( Dbg_Capture [1] ), // output wire Dbg_Capture_1 + .Dbg_Shift_1 ( Dbg_Shift [1] ), // output wire Dbg_Shift_1 + .Dbg_Update_1 ( Dbg_Update [1] ), // output wire Dbg_Update_1 + .Dbg_Rst_1 ( Dbg_Rst [1] ), // output wire Dbg_Rst_1 + .Dbg_Disable_1 ( Dbg_Disable [1] ) // output wire Dbg_Disable_1 + ); + + + // Attach to socket + // Core 0 + `ASSIGN_AXI_BUS(rv_socket_data , microblaze0_data); + `ASSIGN_AXI_BUS(rv_socket_instr , converter0_instr); + // Core 1 + `ASSIGN_AXI_BUS(rv_socket_data1 , microblaze1_data); + `ASSIGN_AXI_BUS(rv_socket_instr1 , converter1_instr); + + // Tie-off undriven ID signals + // ID's are set to zero since they are not present in microblaze, while the crossbar have ID's of size 2. + // Instruction + assign converter0_instr_axi_awid = '0; + assign converter0_instr_axi_arid = '0; + assign converter1_instr_axi_awid = '0; + assign converter1_instr_axi_arid = '0; + // Data + assign microblaze0_data_axi_awid = '0; + assign microblaze0_data_axi_arid = '0; + assign microblaze1_data_axi_awid = '0; + assign microblaze1_data_axi_arid = '0; + // Regions are not present in microblaze data implementation so they are set to 0. + assign microblaze0_data_axi_awregion ='0; + assign microblaze0_data_axi_arregion ='0; + assign microblaze1_data_axi_awregion = '0; + assign microblaze1_data_axi_arregion = '0; + + // Convert from MICROBLAZE-V (AXI-lite) to socket (AXI) + // Only instruction port (AXI-lite), data port is socket compliant (AXI) + xlnx_axilite_to_axi4_d32_converter axilite_to_axi4_converter_u0 ( + .aclk ( clk_i ), // input wire aclk + .aresetn ( rst_ni ), // input wire aresetn + // From Microblaze (AXI-lite) + .s_axi_awaddr ( microblaze0_instr_axilite_awaddr ), // input wire [31 : 0] s_axi_awaddr + .s_axi_awprot ( microblaze0_instr_axilite_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awvalid ( microblaze0_instr_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( microblaze0_instr_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( microblaze0_instr_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( microblaze0_instr_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( microblaze0_instr_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( microblaze0_instr_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( microblaze0_instr_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( microblaze0_instr_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( microblaze0_instr_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( microblaze0_instr_axilite_araddr ), // input wire [31 : 0] s_axi_araddr + .s_axi_arprot ( microblaze0_instr_axilite_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arvalid ( microblaze0_instr_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( microblaze0_instr_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( microblaze0_instr_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( microblaze0_instr_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( microblaze0_instr_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( microblaze0_instr_axilite_rready ), // input wire s_axi_rready + // To socket (AXI) + .m_axi_awaddr ( converter0_instr_axi_awaddr ), // output wire [31 : 0] m_axi_awaddr + .m_axi_awlen ( converter0_instr_axi_awlen ), // output wire [7 : 0] m_axi_awlen + .m_axi_awsize ( converter0_instr_axi_awsize ), // output wire [2 : 0] m_axi_awsize + .m_axi_awburst ( converter0_instr_axi_awburst ), // output wire [1 : 0] m_axi_awburst + .m_axi_awlock ( converter0_instr_axi_awlock ), // output wire [0 : 0] m_axi_awlock + .m_axi_awcache ( converter0_instr_axi_awcache ), // output wire [3 : 0] m_axi_awcache + .m_axi_awprot ( converter0_instr_axi_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awregion ( converter0_instr_axi_awregion ), // output wire [3 : 0] m_axi_awregion + .m_axi_awqos ( converter0_instr_axi_awqos ), // output wire [3 : 0] m_axi_awqos + .m_axi_awvalid ( converter0_instr_axi_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( converter0_instr_axi_awready ), // input wire m_axi_awready + .m_axi_wdata ( converter0_instr_axi_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( converter0_instr_axi_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wlast ( converter0_instr_axi_wlast ), // output wire m_axi_wlast + .m_axi_wvalid ( converter0_instr_axi_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( converter0_instr_axi_wready ), // input wire m_axi_wready + .m_axi_bresp ( converter0_instr_axi_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( converter0_instr_axi_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( converter0_instr_axi_bready ), // output wire m_axi_bready + .m_axi_araddr ( converter0_instr_axi_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arlen ( converter0_instr_axi_arlen ), // output wire [7 : 0] m_axi_arlen + .m_axi_arsize ( converter0_instr_axi_arsize ), // output wire [2 : 0] m_axi_arsize + .m_axi_arburst ( converter0_instr_axi_arburst ), // output wire [1 : 0] m_axi_arburst + .m_axi_arlock ( converter0_instr_axi_arlock ), // output wire [0 : 0] m_axi_arlock + .m_axi_arcache ( converter0_instr_axi_arcache ), // output wire [3 : 0] m_axi_arcache + .m_axi_arprot ( converter0_instr_axi_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arregion ( converter0_instr_axi_arregion ), // output wire [3 : 0] m_axi_arregion + .m_axi_arqos ( converter0_instr_axi_arqos ), // output wire [3 : 0] m_axi_arqos + .m_axi_arvalid ( converter0_instr_axi_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( converter0_instr_axi_arready ), // input wire m_axi_arready + .m_axi_rdata ( converter0_instr_axi_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( converter0_instr_axi_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rlast ( converter0_instr_axi_rlast ), // input wire m_axi_rlast + .m_axi_rvalid ( converter0_instr_axi_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( converter0_instr_axi_rready ) // output wire m_axi_rready + ); + + // Convert from MICROBLAZE-V CORE 1 (AXI-lite) to socket (AXI) + xlnx_axilite_to_axi4_d32_converter axilite_to_axi4_converter_u1 ( + .aclk ( clk_i ), + .aresetn ( rst_ni ), + // From Microblaze 1 (AXI-lite) + .s_axi_awaddr ( microblaze1_instr_axilite_awaddr ), + .s_axi_awprot ( microblaze1_instr_axilite_awprot ), + .s_axi_awvalid ( microblaze1_instr_axilite_awvalid ), + .s_axi_awready ( microblaze1_instr_axilite_awready ), + .s_axi_wdata ( microblaze1_instr_axilite_wdata ), + .s_axi_wstrb ( microblaze1_instr_axilite_wstrb ), + .s_axi_wvalid ( microblaze1_instr_axilite_wvalid ), + .s_axi_wready ( microblaze1_instr_axilite_wready ), + .s_axi_bresp ( microblaze1_instr_axilite_bresp ), + .s_axi_bvalid ( microblaze1_instr_axilite_bvalid ), + .s_axi_bready ( microblaze1_instr_axilite_bready ), + .s_axi_araddr ( microblaze1_instr_axilite_araddr ), + .s_axi_arprot ( microblaze1_instr_axilite_arprot ), + .s_axi_arvalid ( microblaze1_instr_axilite_arvalid ), + .s_axi_arready ( microblaze1_instr_axilite_arready ), + .s_axi_rdata ( microblaze1_instr_axilite_rdata ), + .s_axi_rresp ( microblaze1_instr_axilite_rresp ), + .s_axi_rvalid ( microblaze1_instr_axilite_rvalid ), + .s_axi_rready ( microblaze1_instr_axilite_rready ), + // To socket (AXI) – CORE 1 + .m_axi_awaddr ( converter1_instr_axi_awaddr ), + .m_axi_awlen ( converter1_instr_axi_awlen ), + .m_axi_awsize ( converter1_instr_axi_awsize ), + .m_axi_awburst ( converter1_instr_axi_awburst ), + .m_axi_awlock ( converter1_instr_axi_awlock ), + .m_axi_awcache ( converter1_instr_axi_awcache ), + .m_axi_awprot ( converter1_instr_axi_awprot ), + .m_axi_awregion ( converter1_instr_axi_awregion ), + .m_axi_awqos ( converter1_instr_axi_awqos ), + .m_axi_awvalid ( converter1_instr_axi_awvalid ), + .m_axi_awready ( converter1_instr_axi_awready ), + .m_axi_wdata ( converter1_instr_axi_wdata ), + .m_axi_wstrb ( converter1_instr_axi_wstrb ), + .m_axi_wlast ( converter1_instr_axi_wlast ), + .m_axi_wvalid ( converter1_instr_axi_wvalid ), + .m_axi_wready ( converter1_instr_axi_wready ), + .m_axi_bresp ( converter1_instr_axi_bresp ), + .m_axi_bvalid ( converter1_instr_axi_bvalid ), + .m_axi_bready ( converter1_instr_axi_bready ), + .m_axi_araddr ( converter1_instr_axi_araddr ), + .m_axi_arlen ( converter1_instr_axi_arlen ), + .m_axi_arsize ( converter1_instr_axi_arsize ), + .m_axi_arburst ( converter1_instr_axi_arburst ), + .m_axi_arlock ( converter1_instr_axi_arlock ), + .m_axi_arcache ( converter1_instr_axi_arcache ), + .m_axi_arprot ( converter1_instr_axi_arprot ), + .m_axi_arregion ( converter1_instr_axi_arregion ), + .m_axi_arqos ( converter1_instr_axi_arqos ), + .m_axi_arvalid ( converter1_instr_axi_arvalid ), + .m_axi_arready ( converter1_instr_axi_arready ), + .m_axi_rdata ( converter1_instr_axi_rdata ), + .m_axi_rresp ( converter1_instr_axi_rresp ), + .m_axi_rlast ( converter1_instr_axi_rlast ), + .m_axi_rvalid ( converter1_instr_axi_rvalid ), + .m_axi_rready ( converter1_instr_axi_rready ) + ); + + end : xlnx_dual_microblazev_rv32 + else if (CORE_SELECTOR == CORE_MICROBLAZEV_RV64) begin : xlnx_microblazev_rv64 + + // Tie-off unused signals + assign core_instr_mem_wdata = '0; + assign core_instr_mem_we = '0; + assign core_instr_mem_be = '0; + + ////////////////////////// + // MICROBLAZE-V RV64 // + ////////////////////////// + + // Debug interface connections definition + logic dbg_sys_rst; + logic Dbg_Clk; // wire Dbg_Clk_0 + logic Dbg_TDI; // wire Dbg_TDI_0 + logic Dbg_TDO; // wire Dbg_TDO_0 + logic [0:7] Dbg_Reg_En; // wire [0 : 7] Dbg_Reg_En_0 + logic Dbg_Capture; // wire Dbg_Capture_0 + logic Dbg_Shift; // wire Dbg_Shift_0 + logic Dbg_Update; // wire Dbg_Update_0 + logic Dbg_Rst; // wire Dbg_Rst_0 + logic Dbg_Disable; // wire Dbg_Disable_0 + + + // Declare AXI interfaces for instruction memory port and data memory port for MicroblazeV + `DECLARE_AXI_BUS(microblaze_data, 32, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXILITE_BUS(microblaze_instr, 32, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // Declare AXI dwith 32-64 adapters + `DECLARE_AXI_BUS(dwidth_conv_to_d64_data, 64, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXI_BUS(dwidth_conv_from_d32_instr, 32, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXI_BUS(dwidth_conv_to_d64_instr, 64, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // Microblaze-V 64 instance + xlnx_microblazev_rv64 microblazev_u ( + // Clock and reset + .Clk ( clk_i ), // input wire Clk + .Reset ( dbg_sys_rst ), // input wire Reset + + // Interrupts + // Ublaze can only take one external interrupt, which we tie to EXT interrupt (from the PLIC) + .Interrupt ( irq_i[CORE_EXT_INTERRUPT] ), // input wire Interrupt + .Interrupt_Address ('0 ), // input wire [0 : 31] Interrupt_Address + .Interrupt_Ack ( ), // output wire [0 : 1] Interrupt_Ack + + // Debug port to MDMV + .Dbg_Clk ( Dbg_Clk ), // input wire Dbg_Clk + .Dbg_TDI ( Dbg_TDI ), // input wire Dbg_TDI + .Dbg_TDO ( Dbg_TDO ), // output wire Dbg_TDO + .Dbg_Reg_En ( Dbg_Reg_En ), // input wire [0 : 7] Dbg_Reg_En + .Dbg_Shift ( Dbg_Shift ), // input wire Dbg_Shift + .Dbg_Capture ( Dbg_Capture ), // input wire Dbg_Capture + .Dbg_Update ( Dbg_Update ), // input wire Dbg_Update + .Debug_Rst ( Dbg_Rst ), // input wire Debug_Rst + .Dbg_Disable ( Dbg_Disable ), // input wire Dbg_Disable + + // Data port (AXI) + .M_AXI_DP_AWADDR ( microblaze_data_axi_awaddr ), // output wire [31 : 0] M_AXI_DP_AWADDR + .M_AXI_DP_AWLEN ( microblaze_data_axi_awlen ), // output wire [7 : 0] M_AXI_DP_AWLEN + .M_AXI_DP_AWSIZE ( microblaze_data_axi_awsize ), // output wire [2 : 0] M_AXI_DP_AWSIZE + .M_AXI_DP_AWBURST ( microblaze_data_axi_awburst ), // output wire [1 : 0] M_AXI_DP_AWBURST + .M_AXI_DP_AWLOCK ( microblaze_data_axi_awlock ), // output wire M_AXI_DP_AWLOCK + .M_AXI_DP_AWCACHE ( microblaze_data_axi_awcache ), // output wire [3 : 0] M_AXI_DP_AWCACHE + .M_AXI_DP_AWPROT ( microblaze_data_axi_awprot ), // output wire [2 : 0] M_AXI_DP_AWPROT + .M_AXI_DP_AWQOS ( microblaze_data_axi_awqos ), // output wire [3 : 0] M_AXI_DP_AWQOS + .M_AXI_DP_AWVALID ( microblaze_data_axi_awvalid ), // output wire M_AXI_DP_AWVALID + .M_AXI_DP_AWREADY ( microblaze_data_axi_awready ), // input wire M_AXI_DP_AWREADY + .M_AXI_DP_WDATA ( microblaze_data_axi_wdata ), // output wire [31 : 0] M_AXI_DP_WDATA + .M_AXI_DP_WSTRB ( microblaze_data_axi_wstrb ), // output wire [3 : 0] M_AXI_DP_WSTRB + .M_AXI_DP_WLAST ( microblaze_data_axi_wlast ), // output wire M_AXI_DP_WLAST + .M_AXI_DP_WVALID ( microblaze_data_axi_wvalid ), // output wire M_AXI_DP_WVALID + .M_AXI_DP_WREADY ( microblaze_data_axi_wready ), // input wire M_AXI_DP_WREADY + .M_AXI_DP_BRESP ( microblaze_data_axi_bresp ), // input wire [1 : 0] M_AXI_DP_BRESP + .M_AXI_DP_BVALID ( microblaze_data_axi_bvalid ), // input wire M_AXI_DP_BVALID + .M_AXI_DP_BREADY ( microblaze_data_axi_bready ), // output wire M_AXI_DP_BREADY + .M_AXI_DP_ARADDR ( microblaze_data_axi_araddr ), // output wire [31 : 0] M_AXI_DP_ARADDR + .M_AXI_DP_ARLEN ( microblaze_data_axi_arlen ), // output wire [7 : 0] M_AXI_DP_ARLEN + .M_AXI_DP_ARSIZE ( microblaze_data_axi_arsize ), // output wire [2 : 0] M_AXI_DP_ARSIZE + .M_AXI_DP_ARBURST ( microblaze_data_axi_arburst ), // output wire [1 : 0] M_AXI_DP_ARBURST + .M_AXI_DP_ARLOCK ( microblaze_data_axi_arlock ), // output wire M_AXI_DP_ARLOCK + .M_AXI_DP_ARCACHE ( microblaze_data_axi_arcache ), // output wire [3 : 0] M_AXI_DP_ARCACHE + .M_AXI_DP_ARPROT ( microblaze_data_axi_arprot ), // output wire [2 : 0] M_AXI_DP_ARPROT + .M_AXI_DP_ARQOS ( microblaze_data_axi_arqos ), // output wire [3 : 0] M_AXI_DP_ARQOS + .M_AXI_DP_ARVALID ( microblaze_data_axi_arvalid ), // output wire M_AXI_DP_ARVALID + .M_AXI_DP_ARREADY ( microblaze_data_axi_arready ), // input wire M_AXI_DP_ARREADY + .M_AXI_DP_RDATA ( microblaze_data_axi_rdata ), // input wire [31 : 0] M_AXI_DP_RDATA + .M_AXI_DP_RRESP ( microblaze_data_axi_rresp ), // input wire [1 : 0] M_AXI_DP_RRESP + .M_AXI_DP_RLAST ( microblaze_data_axi_rlast ), // input wire M_AXI_DP_RLAST + .M_AXI_DP_RVALID ( microblaze_data_axi_rvalid ), // input wire M_AXI_DP_RVALID + .M_AXI_DP_RREADY ( microblaze_data_axi_rready ), // output wire M_AXI_DP_RREADY + + // Instruction port (AXI-lite) + .M_AXI_IP_AWADDR ( microblaze_instr_axilite_awaddr ), // output wire [31 : 0] M_AXI_IP_AWADDR + .M_AXI_IP_AWPROT ( microblaze_instr_axilite_awprot ), // output wire [2 : 0] M_AXI_IP_AWPROT + .M_AXI_IP_AWVALID ( microblaze_instr_axilite_awvalid ), // output wire M_AXI_IP_AWVALID + .M_AXI_IP_AWREADY ( microblaze_instr_axilite_awready ), // input wire M_AXI_IP_AWREADY + .M_AXI_IP_WDATA ( microblaze_instr_axilite_wdata ), // output wire [31 : 0] M_AXI_IP_WDATA + .M_AXI_IP_WSTRB ( microblaze_instr_axilite_wstrb ), // output wire [3 : 0] M_AXI_IP_WSTRB + .M_AXI_IP_WVALID ( microblaze_instr_axilite_wvalid ), // output wire M_AXI_IP_WVALID + .M_AXI_IP_WREADY ( microblaze_instr_axilite_wready ), // input wire M_AXI_IP_WREADY + .M_AXI_IP_BRESP ( microblaze_instr_axilite_bresp ), // input wire [1 : 0] M_AXI_IP_BRESP + .M_AXI_IP_BVALID ( microblaze_instr_axilite_bvalid ), // input wire M_AXI_IP_BVALID + .M_AXI_IP_BREADY ( microblaze_instr_axilite_bready ), // output wire M_AXI_IP_BREADY + .M_AXI_IP_ARADDR ( microblaze_instr_axilite_araddr ), // output wire [31 : 0] M_AXI_IP_ARADDR + .M_AXI_IP_ARPROT ( microblaze_instr_axilite_arprot ), // output wire [2 : 0] M_AXI_IP_ARPROT + .M_AXI_IP_ARVALID ( microblaze_instr_axilite_arvalid ), // output wire M_AXI_IP_ARVALID + .M_AXI_IP_ARREADY ( microblaze_instr_axilite_arready ), // input wire M_AXI_IP_ARREADY + .M_AXI_IP_RDATA ( microblaze_instr_axilite_rdata ), // input wire [31 : 0] M_AXI_IP_RDATA + .M_AXI_IP_RRESP ( microblaze_instr_axilite_rresp ), // input wire [1 : 0] M_AXI_IP_RRESP + .M_AXI_IP_RVALID ( microblaze_instr_axilite_rvalid ), // input wire M_AXI_IP_RVALID + .M_AXI_IP_RREADY ( microblaze_instr_axilite_rready ) // output wire M_AXI_IP_RREADY + ); + + xlnx_axi_dwidth_32_to_64_converter data_dwidth_conv_u ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + + // Slave + .s_axi_awid ( microblaze_data_axi_awid ), + .s_axi_awaddr ( microblaze_data_axi_awaddr ), + .s_axi_awlen ( microblaze_data_axi_awlen ), + .s_axi_awsize ( microblaze_data_axi_awsize ), + .s_axi_awburst ( microblaze_data_axi_awburst ), + .s_axi_awvalid ( microblaze_data_axi_awvalid ), + .s_axi_awready ( microblaze_data_axi_awready ), + .s_axi_wdata ( microblaze_data_axi_wdata ), + .s_axi_wstrb ( microblaze_data_axi_wstrb ), + .s_axi_wlast ( microblaze_data_axi_wlast ), + .s_axi_wvalid ( microblaze_data_axi_wvalid ), + .s_axi_wready ( microblaze_data_axi_wready ), + .s_axi_bid ( microblaze_data_axi_bid ), + .s_axi_bresp ( microblaze_data_axi_bresp ), + .s_axi_bvalid ( microblaze_data_axi_bvalid ), + .s_axi_bready ( microblaze_data_axi_bready ), + .s_axi_arid ( microblaze_data_axi_arid ), + .s_axi_araddr ( microblaze_data_axi_araddr ), + .s_axi_arlen ( microblaze_data_axi_arlen ), + .s_axi_arsize ( microblaze_data_axi_arsize ), + .s_axi_arburst ( microblaze_data_axi_arburst ), + .s_axi_arvalid ( microblaze_data_axi_arvalid ), + .s_axi_arready ( microblaze_data_axi_arready ), + .s_axi_rid ( microblaze_data_axi_rid ), + .s_axi_rdata ( microblaze_data_axi_rdata ), + .s_axi_rresp ( microblaze_data_axi_rresp ), + .s_axi_rlast ( microblaze_data_axi_rlast ), + .s_axi_rvalid ( microblaze_data_axi_rvalid ), + .s_axi_rready ( microblaze_data_axi_rready ), + .s_axi_awlock ( microblaze_data_axi_awlock ), + .s_axi_awcache ( microblaze_data_axi_awcache ), + .s_axi_awprot ( microblaze_data_axi_awprot ), + .s_axi_awqos ( microblaze_data_axi_awqos ), + .s_axi_awregion ( microblaze_data_axi_awregion ), + .s_axi_arlock ( microblaze_data_axi_arlock ), + .s_axi_arcache ( microblaze_data_axi_arcache ), + .s_axi_arprot ( microblaze_data_axi_arprot ), + .s_axi_arqos ( microblaze_data_axi_arqos ), + .s_axi_arregion ( microblaze_data_axi_arregion ), + + // Master + .m_axi_awaddr ( dwidth_conv_to_d64_data_axi_awaddr ), + .m_axi_awlen ( dwidth_conv_to_d64_data_axi_awlen ), + .m_axi_awsize ( dwidth_conv_to_d64_data_axi_awsize ), + .m_axi_awburst ( dwidth_conv_to_d64_data_axi_awburst ), + .m_axi_awlock ( dwidth_conv_to_d64_data_axi_awlock ), + .m_axi_awcache ( dwidth_conv_to_d64_data_axi_awcache ), + .m_axi_awprot ( dwidth_conv_to_d64_data_axi_awprot ), + .m_axi_awqos ( dwidth_conv_to_d64_data_axi_awqos ), + .m_axi_awvalid ( dwidth_conv_to_d64_data_axi_awvalid ), + .m_axi_awready ( dwidth_conv_to_d64_data_axi_awready ), + .m_axi_awregion ( dwidth_conv_to_d64_data_axi_awregion ), + .m_axi_wdata ( dwidth_conv_to_d64_data_axi_wdata ), + .m_axi_wstrb ( dwidth_conv_to_d64_data_axi_wstrb ), + .m_axi_wlast ( dwidth_conv_to_d64_data_axi_wlast ), + .m_axi_wvalid ( dwidth_conv_to_d64_data_axi_wvalid ), + .m_axi_wready ( dwidth_conv_to_d64_data_axi_wready ), + .m_axi_bresp ( dwidth_conv_to_d64_data_axi_bresp ), + .m_axi_bvalid ( dwidth_conv_to_d64_data_axi_bvalid ), + .m_axi_bready ( dwidth_conv_to_d64_data_axi_bready ), + .m_axi_arregion ( dwidth_conv_to_d64_data_axi_arregion ), + .m_axi_araddr ( dwidth_conv_to_d64_data_axi_araddr ), + .m_axi_arlen ( dwidth_conv_to_d64_data_axi_arlen ), + .m_axi_arsize ( dwidth_conv_to_d64_data_axi_arsize ), + .m_axi_arburst ( dwidth_conv_to_d64_data_axi_arburst ), + .m_axi_arlock ( dwidth_conv_to_d64_data_axi_arlock ), + .m_axi_arcache ( dwidth_conv_to_d64_data_axi_arcache ), + .m_axi_arprot ( dwidth_conv_to_d64_data_axi_arprot ), + .m_axi_arqos ( dwidth_conv_to_d64_data_axi_arqos ), + .m_axi_arvalid ( dwidth_conv_to_d64_data_axi_arvalid ), + .m_axi_arready ( dwidth_conv_to_d64_data_axi_arready ), + .m_axi_rdata ( dwidth_conv_to_d64_data_axi_rdata ), + .m_axi_rresp ( dwidth_conv_to_d64_data_axi_rresp ), + .m_axi_rlast ( dwidth_conv_to_d64_data_axi_rlast ), + .m_axi_rvalid ( dwidth_conv_to_d64_data_axi_rvalid ), + .m_axi_rready ( dwidth_conv_to_d64_data_axi_rready ) + ); + + xlnx_axi_dwidth_32_to_64_converter instr_dwidth_conv_u ( + .s_axi_aclk ( clk_i ), + .s_axi_aresetn ( rst_ni ), + + // Slave + .s_axi_awid ( dwidth_conv_from_d32_instr_axi_awid ), + .s_axi_awaddr ( dwidth_conv_from_d32_instr_axi_awaddr ), + .s_axi_awlen ( dwidth_conv_from_d32_instr_axi_awlen ), + .s_axi_awsize ( dwidth_conv_from_d32_instr_axi_awsize ), + .s_axi_awburst ( dwidth_conv_from_d32_instr_axi_awburst ), + .s_axi_awvalid ( dwidth_conv_from_d32_instr_axi_awvalid ), + .s_axi_awready ( dwidth_conv_from_d32_instr_axi_awready ), + .s_axi_wdata ( dwidth_conv_from_d32_instr_axi_wdata ), + .s_axi_wstrb ( dwidth_conv_from_d32_instr_axi_wstrb ), + .s_axi_wlast ( dwidth_conv_from_d32_instr_axi_wlast ), + .s_axi_wvalid ( dwidth_conv_from_d32_instr_axi_wvalid ), + .s_axi_wready ( dwidth_conv_from_d32_instr_axi_wready ), + .s_axi_bid ( dwidth_conv_from_d32_instr_axi_bid ), + .s_axi_bresp ( dwidth_conv_from_d32_instr_axi_bresp ), + .s_axi_bvalid ( dwidth_conv_from_d32_instr_axi_bvalid ), + .s_axi_bready ( dwidth_conv_from_d32_instr_axi_bready ), + .s_axi_arid ( dwidth_conv_from_d32_instr_axi_arid ), + .s_axi_araddr ( dwidth_conv_from_d32_instr_axi_araddr ), + .s_axi_arlen ( dwidth_conv_from_d32_instr_axi_arlen ), + .s_axi_arsize ( dwidth_conv_from_d32_instr_axi_arsize ), + .s_axi_arburst ( dwidth_conv_from_d32_instr_axi_arburst ), + .s_axi_arvalid ( dwidth_conv_from_d32_instr_axi_arvalid ), + .s_axi_arready ( dwidth_conv_from_d32_instr_axi_arready ), + .s_axi_rid ( dwidth_conv_from_d32_instr_axi_rid ), + .s_axi_rdata ( dwidth_conv_from_d32_instr_axi_rdata ), + .s_axi_rresp ( dwidth_conv_from_d32_instr_axi_rresp ), + .s_axi_rlast ( dwidth_conv_from_d32_instr_axi_rlast ), + .s_axi_rvalid ( dwidth_conv_from_d32_instr_axi_rvalid ), + .s_axi_rready ( dwidth_conv_from_d32_instr_axi_rready ), + .s_axi_awlock ( dwidth_conv_from_d32_instr_axi_awlock ), + .s_axi_awcache ( dwidth_conv_from_d32_instr_axi_awcache ), + .s_axi_awprot ( dwidth_conv_from_d32_instr_axi_awprot ), + .s_axi_awqos ( dwidth_conv_from_d32_instr_axi_awqos ), + .s_axi_awregion ( dwidth_conv_from_d32_instr_axi_awregion ), + .s_axi_arlock ( dwidth_conv_from_d32_instr_axi_arlock ), + .s_axi_arcache ( dwidth_conv_from_d32_instr_axi_arcache ), + .s_axi_arprot ( dwidth_conv_from_d32_instr_axi_arprot ), + .s_axi_arqos ( dwidth_conv_from_d32_instr_axi_arqos ), + .s_axi_arregion ( dwidth_conv_from_d32_instr_axi_arregion ), + + // Master + .m_axi_awaddr ( dwidth_conv_to_d64_instr_axi_awaddr ), + .m_axi_awlen ( dwidth_conv_to_d64_instr_axi_awlen ), + .m_axi_awsize ( dwidth_conv_to_d64_instr_axi_awsize ), + .m_axi_awburst ( dwidth_conv_to_d64_instr_axi_awburst ), + .m_axi_awlock ( dwidth_conv_to_d64_instr_axi_awlock ), + .m_axi_awcache ( dwidth_conv_to_d64_instr_axi_awcache ), + .m_axi_awprot ( dwidth_conv_to_d64_instr_axi_awprot ), + .m_axi_awqos ( dwidth_conv_to_d64_instr_axi_awqos ), + .m_axi_awvalid ( dwidth_conv_to_d64_instr_axi_awvalid ), + .m_axi_awready ( dwidth_conv_to_d64_instr_axi_awready ), + .m_axi_awregion ( dwidth_conv_to_d64_instr_axi_awregion ), + .m_axi_wdata ( dwidth_conv_to_d64_instr_axi_wdata ), + .m_axi_wstrb ( dwidth_conv_to_d64_instr_axi_wstrb ), + .m_axi_wlast ( dwidth_conv_to_d64_instr_axi_wlast ), + .m_axi_wvalid ( dwidth_conv_to_d64_instr_axi_wvalid ), + .m_axi_wready ( dwidth_conv_to_d64_instr_axi_wready ), + .m_axi_bresp ( dwidth_conv_to_d64_instr_axi_bresp ), + .m_axi_bvalid ( dwidth_conv_to_d64_instr_axi_bvalid ), + .m_axi_bready ( dwidth_conv_to_d64_instr_axi_bready ), + .m_axi_araddr ( dwidth_conv_to_d64_instr_axi_araddr ), + .m_axi_arlen ( dwidth_conv_to_d64_instr_axi_arlen ), + .m_axi_arsize ( dwidth_conv_to_d64_instr_axi_arsize ), + .m_axi_arburst ( dwidth_conv_to_d64_instr_axi_arburst ), + .m_axi_arlock ( dwidth_conv_to_d64_instr_axi_arlock ), + .m_axi_arcache ( dwidth_conv_to_d64_instr_axi_arcache ), + .m_axi_arprot ( dwidth_conv_to_d64_instr_axi_arprot ), + .m_axi_arqos ( dwidth_conv_to_d64_instr_axi_arqos ), + .m_axi_arvalid ( dwidth_conv_to_d64_instr_axi_arvalid ), + .m_axi_arready ( dwidth_conv_to_d64_instr_axi_arready ), + .m_axi_arregion ( dwidth_conv_to_d64_instr_axi_arregion ), + .m_axi_rdata ( dwidth_conv_to_d64_instr_axi_rdata ), + .m_axi_rresp ( dwidth_conv_to_d64_instr_axi_rresp ), + .m_axi_rlast ( dwidth_conv_to_d64_instr_axi_rlast ), + .m_axi_rvalid ( dwidth_conv_to_d64_instr_axi_rvalid ), + .m_axi_rready ( dwidth_conv_to_d64_instr_axi_rready ) + ); + + // Convert from MICROBLAZE-V (AXI-lite) to socket (AXI) + // Only instruction port (AXI-lite), data port is socket compliant (AXI) + xlnx_axilite_to_axi4_d32_converter axilite_to_axi4_converter_u ( + .aclk ( clk_i ), // input wire aclk + .aresetn ( rst_ni ), // input wire aresetn + // From Microblaze (AXI-lite) + .s_axi_awaddr ( microblaze_instr_axilite_awaddr ), // input wire [31 : 0] s_axi_awaddr + .s_axi_awprot ( microblaze_instr_axilite_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awvalid ( microblaze_instr_axilite_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( microblaze_instr_axilite_awready ), // output wire s_axi_awready + .s_axi_wdata ( microblaze_instr_axilite_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( microblaze_instr_axilite_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wvalid ( microblaze_instr_axilite_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( microblaze_instr_axilite_wready ), // output wire s_axi_wready + .s_axi_bresp ( microblaze_instr_axilite_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( microblaze_instr_axilite_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( microblaze_instr_axilite_bready ), // input wire s_axi_bready + .s_axi_araddr ( microblaze_instr_axilite_araddr ), // input wire [31 : 0] s_axi_araddr + .s_axi_arprot ( microblaze_instr_axilite_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arvalid ( microblaze_instr_axilite_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( microblaze_instr_axilite_arready ), // output wire s_axi_arready + .s_axi_rdata ( microblaze_instr_axilite_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( microblaze_instr_axilite_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rvalid ( microblaze_instr_axilite_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( microblaze_instr_axilite_rready ), // input wire s_axi_rready + // To socket (AXI) + .m_axi_awaddr ( dwidth_conv_from_d32_instr_axi_awaddr ), // output wire [31 : 0] m_axi_awaddr + .m_axi_awlen ( dwidth_conv_from_d32_instr_axi_awlen ), // output wire [7 : 0] m_axi_awlen + .m_axi_awsize ( dwidth_conv_from_d32_instr_axi_awsize ), // output wire [2 : 0] m_axi_awsize + .m_axi_awburst ( dwidth_conv_from_d32_instr_axi_awburst ), // output wire [1 : 0] m_axi_awburst + .m_axi_awlock ( dwidth_conv_from_d32_instr_axi_awlock ), // output wire [0 : 0] m_axi_awlock + .m_axi_awcache ( dwidth_conv_from_d32_instr_axi_awcache ), // output wire [3 : 0] m_axi_awcache + .m_axi_awprot ( dwidth_conv_from_d32_instr_axi_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awregion ( dwidth_conv_from_d32_instr_axi_awregion ), // output wire [3 : 0] m_axi_awregion + .m_axi_awqos ( dwidth_conv_from_d32_instr_axi_awqos ), // output wire [3 : 0] m_axi_awqos + .m_axi_awvalid ( dwidth_conv_from_d32_instr_axi_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( dwidth_conv_from_d32_instr_axi_awready ), // input wire m_axi_awready + .m_axi_wdata ( dwidth_conv_from_d32_instr_axi_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( dwidth_conv_from_d32_instr_axi_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wlast ( dwidth_conv_from_d32_instr_axi_wlast ), // output wire m_axi_wlast + .m_axi_wvalid ( dwidth_conv_from_d32_instr_axi_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( dwidth_conv_from_d32_instr_axi_wready ), // input wire m_axi_wready + .m_axi_bresp ( dwidth_conv_from_d32_instr_axi_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( dwidth_conv_from_d32_instr_axi_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( dwidth_conv_from_d32_instr_axi_bready ), // output wire m_axi_bready + .m_axi_araddr ( dwidth_conv_from_d32_instr_axi_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arlen ( dwidth_conv_from_d32_instr_axi_arlen ), // output wire [7 : 0] m_axi_arlen + .m_axi_arsize ( dwidth_conv_from_d32_instr_axi_arsize ), // output wire [2 : 0] m_axi_arsize + .m_axi_arburst ( dwidth_conv_from_d32_instr_axi_arburst ), // output wire [1 : 0] m_axi_arburst + .m_axi_arlock ( dwidth_conv_from_d32_instr_axi_arlock ), // output wire [0 : 0] m_axi_arlock + .m_axi_arcache ( dwidth_conv_from_d32_instr_axi_arcache ), // output wire [3 : 0] m_axi_arcache + .m_axi_arprot ( dwidth_conv_from_d32_instr_axi_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arregion ( dwidth_conv_from_d32_instr_axi_arregion ), // output wire [3 : 0] m_axi_arregion + .m_axi_arqos ( dwidth_conv_from_d32_instr_axi_arqos ), // output wire [3 : 0] m_axi_arqos + .m_axi_arvalid ( dwidth_conv_from_d32_instr_axi_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( dwidth_conv_from_d32_instr_axi_arready ), // input wire m_axi_arready + .m_axi_rdata ( dwidth_conv_from_d32_instr_axi_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( dwidth_conv_from_d32_instr_axi_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rlast ( dwidth_conv_from_d32_instr_axi_rlast ), // input wire m_axi_rlast + .m_axi_rvalid ( dwidth_conv_from_d32_instr_axi_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( dwidth_conv_from_d32_instr_axi_rready ) // output wire m_axi_rready + ); + + + // Microblaze Debug Module V + xlnx_microblaze_debug_module_v mdmv_u ( + .Debug_SYS_Rst ( dbg_sys_rst ), // output wire Debug_SYS_Rst + .Dbg_Clk_0 ( Dbg_Clk ), // output wire Dbg_Clk_0 + .Dbg_TDI_0 ( Dbg_TDI ), // output wire Dbg_TDI_0 + .Dbg_TDO_0 ( Dbg_TDO ), // input wire Dbg_TDO_0 + .Dbg_Reg_En_0 ( Dbg_Reg_En ), // output wire [0 : 7] Dbg_Reg_En_0 + .Dbg_Capture_0 ( Dbg_Capture ), // output wire Dbg_Capture_0 + .Dbg_Shift_0 ( Dbg_Shift ), // output wire Dbg_Shift_0 + .Dbg_Update_0 ( Dbg_Update ), // output wire Dbg_Update_0 + .Dbg_Rst_0 ( Dbg_Rst ), // output wire Dbg_Rst_0 + .Dbg_Disable_0 ( Dbg_Disable ) // output wire Dbg_Disable_0 + ); + + // Attach to socket + `ASSIGN_AXI_BUS(rv_socket_data , dwidth_conv_to_d64_data); + `ASSIGN_AXI_BUS(rv_socket_instr , dwidth_conv_to_d64_instr); + + // Tie-off undriven ID signals + // ID's are set to zero since they are not present in microblaze, while the crossbar have ID's of size 2. + // Instruction + assign dwidth_conv_to_d64_instr_axi_awid = '0; + assign dwidth_conv_to_d64_instr_axi_arid = '0; + + // Data + assign dwidth_conv_to_d64_data_axi_awid = '0; + assign dwidth_conv_to_d64_data_axi_arid = '0; + end : xlnx_microblazev_rv64 + + else if (CORE_SELECTOR == CORE_CV64A6) begin: core_cv64a6 + + //////////////////////// + // CV32A6 // + //////////////////////// + + // CVA6 only has one Master port (for both data and instruction) + `DECLARE_AXI_BUS(cv64a6, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + custom_cv64a6 cv64a6_core ( + + .clk_i ( clk_i ), + .rst_ni ( core_resetn_internal ), + .boot_addr_i ( bootaddr_i ), + .hart_id_i ( hart_id ), + .irq_i ( {0,irq_i[CORE_EXT_INTERRUPT]} ), // Should be EXT interrupt. Bit zero is for M-mode, bit one is for S-mode + .ipi_i ( irq_i[CORE_SW_INTERRUPT] ), // Shoult be SW interrupt + .time_irq_i ( irq_i[CORE_TIM_INTERRUPT] ), // Should be TIM interrupt + .debug_req_i ( debug_req_core ), + + .m_axi_awaddr ( cv64a6_axi_awaddr ), // output wire [31 : 0] m_axi_awaddr + .m_axi_awlen ( cv64a6_axi_awlen ), // output wire [7 : 0] m_axi_awlen + .m_axi_awsize ( cv64a6_axi_awsize ), // output wire [2 : 0] m_axi_awsize + .m_axi_awburst ( cv64a6_axi_awburst ), // output wire [1 : 0] m_axi_awburst + .m_axi_awlock ( cv64a6_axi_awlock ), // output wire [0 : 0] m_axi_awlock + .m_axi_awcache ( cv64a6_axi_awcache ), // output wire [3 : 0] m_axi_awcache + .m_axi_awprot ( cv64a6_axi_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awregion ( cv64a6_axi_awregion ), // output wire [3 : 0] m_axi_awregion + .m_axi_awqos ( cv64a6_axi_awqos ), // output wire [3 : 0] m_axi_awqos + .m_axi_awvalid ( cv64a6_axi_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( cv64a6_axi_awready ), // input wire m_axi_awready + .m_axi_awid ( cv64a6_axi_awid ), + .m_axi_wdata ( cv64a6_axi_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( cv64a6_axi_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wlast ( cv64a6_axi_wlast ), // output wire m_axi_wlast + .m_axi_wvalid ( cv64a6_axi_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( cv64a6_axi_wready ), // input wire m_axi_wready + .m_axi_bresp ( cv64a6_axi_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( cv64a6_axi_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( cv64a6_axi_bready ), // output wire m_axi_bready + .m_axi_bid ( cv64a6_axi_bid ), // output wire m_axi_bready + .m_axi_araddr ( cv64a6_axi_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arlen ( cv64a6_axi_arlen ), // output wire [7 : 0] m_axi_arlen + .m_axi_arsize ( cv64a6_axi_arsize ), // output wire [2 : 0] m_axi_arsize + .m_axi_arburst ( cv64a6_axi_arburst ), // output wire [1 : 0] m_axi_arburst + .m_axi_arlock ( cv64a6_axi_arlock ), // output wire [0 : 0] m_axi_arlock + .m_axi_arcache ( cv64a6_axi_arcache ), // output wire [3 : 0] m_axi_arcache + .m_axi_arprot ( cv64a6_axi_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arregion ( cv64a6_axi_arregion ), // output wire [3 : 0] m_axi_arregion + .m_axi_arqos ( cv64a6_axi_arqos ), // output wire [3 : 0] m_axi_arqos + .m_axi_arvalid ( cv64a6_axi_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( cv64a6_axi_arready ), // input wire m_axi_arready + .m_axi_arid ( cv64a6_axi_arid ), + .m_axi_rdata ( cv64a6_axi_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( cv64a6_axi_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rlast ( cv64a6_axi_rlast ), // input wire m_axi_rlast + .m_axi_rvalid ( cv64a6_axi_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( cv64a6_axi_rready ), // output wire m_axi_rready + .m_axi_rid ( cv64a6_axi_rid ) // output wire m_axi_rready + + ); + + // Attach to socket (we only use data port) + `ASSIGN_AXI_BUS( rv_socket_data , cv64a6 ); + `SINK_AXI_MASTER_INTERFACE(rv_socket_instr); + + end + + + endgenerate + + + ////////////////////////////////////////// + // ___ // + // / __|___ _ __ _ __ ___ _ _ // + // | (__/ _ | ' \| ' \/ _ | ' \ // + // \___\___|_|_|_|_|_|_\___|_||_| // + // // + ////////////////////////////////////////// + + ////////////////////////////////////////////////////////////////////////// + // Here we are allocating commong module and signals. // + ////////////////////////////////////////////////////////////////////////// + + /////////////////////////////////////////////////////////////////////////// + // Cores (mem) to socket (AXI-Full) converters (Instruction and Data) // + /////////////////////////////////////////////////////////////////////////// + + // Few exceptions: + // - MICROBLAZE-V have their own interfaces and debug module + // - CVA6 Already has an AXI interface + // - TODO: Rocket + if ( !( CORE_SELECTOR inside {CORE_MICROBLAZEV_RV32, CORE_DUAL_MICROBLAZEV_RV32, CORE_MICROBLAZEV_RV64, CORE_CV64A6} ) ) begin : mem_convert + + // Connect memory interfaces to socket output memory ports + `ASSIGN_AXI_BUS( rv_socket_instr, core_instr_to_socket_instr ); + `ASSIGN_AXI_BUS( rv_socket_data, core_data_to_socket_data ); + + // Convert instructions socket (AXI) to core (MEM) + custom_axi_from_mem axi_from_mem_instr_u ( + // AXI side + .m_axi_awid ( core_instr_to_socket_instr_axi_awid ), + .m_axi_awaddr ( core_instr_to_socket_instr_axi_awaddr ), + .m_axi_awlen ( core_instr_to_socket_instr_axi_awlen ), + .m_axi_awsize ( core_instr_to_socket_instr_axi_awsize ), + .m_axi_awburst ( core_instr_to_socket_instr_axi_awburst ), + .m_axi_awlock ( core_instr_to_socket_instr_axi_awlock ), + .m_axi_awcache ( core_instr_to_socket_instr_axi_awcache ), + .m_axi_awprot ( core_instr_to_socket_instr_axi_awprot ), + .m_axi_awqos ( core_instr_to_socket_instr_axi_awqos ), + .m_axi_awregion ( core_instr_to_socket_instr_axi_awregion ), + .m_axi_awvalid ( core_instr_to_socket_instr_axi_awvalid ), + .m_axi_awready ( core_instr_to_socket_instr_axi_awready ), + .m_axi_wdata ( core_instr_to_socket_instr_axi_wdata ), + .m_axi_wstrb ( core_instr_to_socket_instr_axi_wstrb ), + .m_axi_wlast ( core_instr_to_socket_instr_axi_wlast ), + .m_axi_wvalid ( core_instr_to_socket_instr_axi_wvalid ), + .m_axi_wready ( core_instr_to_socket_instr_axi_wready ), + .m_axi_bid ( core_instr_to_socket_instr_axi_bid ), + .m_axi_bresp ( core_instr_to_socket_instr_axi_bresp ), + .m_axi_bvalid ( core_instr_to_socket_instr_axi_bvalid ), + .m_axi_bready ( core_instr_to_socket_instr_axi_bready ), + .m_axi_araddr ( core_instr_to_socket_instr_axi_araddr ), + .m_axi_arlen ( core_instr_to_socket_instr_axi_arlen ), + .m_axi_arsize ( core_instr_to_socket_instr_axi_arsize ), + .m_axi_arburst ( core_instr_to_socket_instr_axi_arburst ), + .m_axi_arlock ( core_instr_to_socket_instr_axi_arlock ), + .m_axi_arcache ( core_instr_to_socket_instr_axi_arcache ), + .m_axi_arprot ( core_instr_to_socket_instr_axi_arprot ), + .m_axi_arqos ( core_instr_to_socket_instr_axi_arqos ), + .m_axi_arregion ( core_instr_to_socket_instr_axi_arregion ), + .m_axi_arvalid ( core_instr_to_socket_instr_axi_arvalid ), + .m_axi_arready ( core_instr_to_socket_instr_axi_arready ), + .m_axi_arid ( core_instr_to_socket_instr_axi_arid ), + .m_axi_rid ( core_instr_to_socket_instr_axi_rid ), + .m_axi_rdata ( core_instr_to_socket_instr_axi_rdata ), + .m_axi_rresp ( core_instr_to_socket_instr_axi_rresp ), + .m_axi_rlast ( core_instr_to_socket_instr_axi_rlast ), + .m_axi_rvalid ( core_instr_to_socket_instr_axi_rvalid ), + .m_axi_rready ( core_instr_to_socket_instr_axi_rready ), + + // MEM side + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .s_mem_req ( core_instr_mem_req ), + .s_mem_addr ( core_instr_mem_addr ), + .s_mem_we ( core_instr_mem_we ), // RO Interface + .s_mem_wdata ( core_instr_mem_wdata ), // RO Interface + .s_mem_be ( core_instr_mem_be ), // RO Interface + .s_mem_gnt ( core_instr_mem_gnt ), + .s_mem_valid ( core_instr_mem_valid ), + .s_mem_rdata ( core_instr_mem_rdata ), + .s_mem_error ( core_instr_mem_error ) + ); + + // Convert instructions socket (AXI) to core (MEM) + custom_axi_from_mem axi_from_mem_data_u ( + // AXI side + .m_axi_awid ( core_data_to_socket_data_axi_awid ), + .m_axi_awaddr ( core_data_to_socket_data_axi_awaddr ), + .m_axi_awlen ( core_data_to_socket_data_axi_awlen ), + .m_axi_awsize ( core_data_to_socket_data_axi_awsize ), + .m_axi_awburst ( core_data_to_socket_data_axi_awburst ), + .m_axi_awlock ( core_data_to_socket_data_axi_awlock ), + .m_axi_awcache ( core_data_to_socket_data_axi_awcache ), + .m_axi_awprot ( core_data_to_socket_data_axi_awprot ), + .m_axi_awqos ( core_data_to_socket_data_axi_awqos ), + .m_axi_awregion ( core_data_to_socket_data_axi_awregion ), + .m_axi_awvalid ( core_data_to_socket_data_axi_awvalid ), + .m_axi_awready ( core_data_to_socket_data_axi_awready ), + .m_axi_wdata ( core_data_to_socket_data_axi_wdata ), + .m_axi_wstrb ( core_data_to_socket_data_axi_wstrb ), + .m_axi_wlast ( core_data_to_socket_data_axi_wlast ), + .m_axi_wvalid ( core_data_to_socket_data_axi_wvalid ), + .m_axi_wready ( core_data_to_socket_data_axi_wready ), + .m_axi_bid ( core_data_to_socket_data_axi_bid ), + .m_axi_bresp ( core_data_to_socket_data_axi_bresp ), + .m_axi_bvalid ( core_data_to_socket_data_axi_bvalid ), + .m_axi_bready ( core_data_to_socket_data_axi_bready ), + .m_axi_araddr ( core_data_to_socket_data_axi_araddr ), + .m_axi_arlen ( core_data_to_socket_data_axi_arlen ), + .m_axi_arsize ( core_data_to_socket_data_axi_arsize ), + .m_axi_arburst ( core_data_to_socket_data_axi_arburst ), + .m_axi_arlock ( core_data_to_socket_data_axi_arlock ), + .m_axi_arcache ( core_data_to_socket_data_axi_arcache ), + .m_axi_arprot ( core_data_to_socket_data_axi_arprot ), + .m_axi_arqos ( core_data_to_socket_data_axi_arqos ), + .m_axi_arregion ( core_data_to_socket_data_axi_arregion ), + .m_axi_arvalid ( core_data_to_socket_data_axi_arvalid ), + .m_axi_arready ( core_data_to_socket_data_axi_arready ), + .m_axi_arid ( core_data_to_socket_data_axi_arid ), + .m_axi_rid ( core_data_to_socket_data_axi_rid ), + .m_axi_rdata ( core_data_to_socket_data_axi_rdata ), + .m_axi_rresp ( core_data_to_socket_data_axi_rresp ), + .m_axi_rlast ( core_data_to_socket_data_axi_rlast ), + .m_axi_rvalid ( core_data_to_socket_data_axi_rvalid ), + .m_axi_rready ( core_data_to_socket_data_axi_rready ), + + // MEM side + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .s_mem_req ( core_data_mem_req ), + .s_mem_addr ( core_data_mem_addr ), + .s_mem_we ( core_data_mem_we ), + .s_mem_wdata ( core_data_mem_wdata ), + .s_mem_be ( core_data_mem_be ), + .s_mem_gnt ( core_data_mem_gnt ), + .s_mem_valid ( core_data_mem_valid ), + .s_mem_rdata ( core_data_mem_rdata ), + .s_mem_error ( core_data_mem_error ) + ); + end + + /////////////////////////////////// + // ___ ___ ___ _ _ ___ // + // | \| __| _ ) | | |/ __| // + // | |) | _|| _ \ |_| | (_ | // + // |___/|___|___/\___/ \___| // + // // + /////////////////////////////////// + + // This is only for PULP cores, that share a common debug module + // Other cores are required to instatiate their own DM + if ( CORE_SELECTOR inside {CORE_CV32E40P, CORE_IBEX} ) begin : dm_rv32_gen + + /////////////////////////// + // Debug Module Instance // + /////////////////////////// + + // BSCANE2 tap + (* keep_hierarchy = "yes" *) // DEBUG + custom_rv32_dbg_bscane riscv_dbg_u ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .unavailable_i ( '0 ), + .ndmreset_o ( ndmreset_o ), // Open + .dmactive_o ( dmactive_o ), // Open + // AXI Slave + .dbg_slave_axi_awid ( rv_socket_dbg_slave_axi_awid ), + .dbg_slave_axi_awaddr ( rv_socket_dbg_slave_axi_awaddr ), + .dbg_slave_axi_awlen ( rv_socket_dbg_slave_axi_awlen ), + .dbg_slave_axi_awsize ( rv_socket_dbg_slave_axi_awsize ), + .dbg_slave_axi_awburst ( rv_socket_dbg_slave_axi_awburst ), + .dbg_slave_axi_awlock ( rv_socket_dbg_slave_axi_awlock ), + .dbg_slave_axi_awcache ( rv_socket_dbg_slave_axi_awcache ), + .dbg_slave_axi_awprot ( rv_socket_dbg_slave_axi_awprot ), + .dbg_slave_axi_awqos ( rv_socket_dbg_slave_axi_awqos ), + .dbg_slave_axi_awvalid ( rv_socket_dbg_slave_axi_awvalid ), + .dbg_slave_axi_awready ( rv_socket_dbg_slave_axi_awready ), + .dbg_slave_axi_wdata ( rv_socket_dbg_slave_axi_wdata ), + .dbg_slave_axi_wstrb ( rv_socket_dbg_slave_axi_wstrb ), + .dbg_slave_axi_wlast ( rv_socket_dbg_slave_axi_wlast ), + .dbg_slave_axi_wvalid ( rv_socket_dbg_slave_axi_wvalid ), + .dbg_slave_axi_wready ( rv_socket_dbg_slave_axi_wready ), + .dbg_slave_axi_bid ( rv_socket_dbg_slave_axi_bid ), + .dbg_slave_axi_bresp ( rv_socket_dbg_slave_axi_bresp ), + .dbg_slave_axi_bvalid ( rv_socket_dbg_slave_axi_bvalid ), + .dbg_slave_axi_bready ( rv_socket_dbg_slave_axi_bready ), + .dbg_slave_axi_arid ( rv_socket_dbg_slave_axi_arid ), + .dbg_slave_axi_araddr ( rv_socket_dbg_slave_axi_araddr ), + .dbg_slave_axi_arlen ( rv_socket_dbg_slave_axi_arlen ), + .dbg_slave_axi_arsize ( rv_socket_dbg_slave_axi_arsize ), + .dbg_slave_axi_arburst ( rv_socket_dbg_slave_axi_arburst ), + .dbg_slave_axi_arlock ( rv_socket_dbg_slave_axi_arlock ), + .dbg_slave_axi_arcache ( rv_socket_dbg_slave_axi_arcache ), + .dbg_slave_axi_arprot ( rv_socket_dbg_slave_axi_arprot ), + .dbg_slave_axi_arqos ( rv_socket_dbg_slave_axi_arqos ), + .dbg_slave_axi_arvalid ( rv_socket_dbg_slave_axi_arvalid ), + .dbg_slave_axi_arready ( rv_socket_dbg_slave_axi_arready ), + .dbg_slave_axi_rid ( rv_socket_dbg_slave_axi_rid ), + .dbg_slave_axi_rdata ( rv_socket_dbg_slave_axi_rdata ), + .dbg_slave_axi_rresp ( rv_socket_dbg_slave_axi_rresp ), + .dbg_slave_axi_rlast ( rv_socket_dbg_slave_axi_rlast ), + .dbg_slave_axi_rvalid ( rv_socket_dbg_slave_axi_rvalid ), + .dbg_slave_axi_rready ( rv_socket_dbg_slave_axi_rready ), + // AXI Master + .dbg_master_axi_awid ( rv_socket_dbg_master_axi_awid ), + .dbg_master_axi_awaddr ( rv_socket_dbg_master_axi_awaddr ), + .dbg_master_axi_awlen ( rv_socket_dbg_master_axi_awlen ), + .dbg_master_axi_awsize ( rv_socket_dbg_master_axi_awsize ), + .dbg_master_axi_awburst ( rv_socket_dbg_master_axi_awburst ), + .dbg_master_axi_awlock ( rv_socket_dbg_master_axi_awlock ), + .dbg_master_axi_awcache ( rv_socket_dbg_master_axi_awcache ), + .dbg_master_axi_awprot ( rv_socket_dbg_master_axi_awprot ), + .dbg_master_axi_awregion ( rv_socket_dbg_master_axi_awregion ), + .dbg_master_axi_awqos ( rv_socket_dbg_master_axi_awqos ), + .dbg_master_axi_awvalid ( rv_socket_dbg_master_axi_awvalid ), + .dbg_master_axi_awready ( rv_socket_dbg_master_axi_awready ), + .dbg_master_axi_wdata ( rv_socket_dbg_master_axi_wdata ), + .dbg_master_axi_wstrb ( rv_socket_dbg_master_axi_wstrb ), + .dbg_master_axi_wlast ( rv_socket_dbg_master_axi_wlast ), + .dbg_master_axi_wvalid ( rv_socket_dbg_master_axi_wvalid ), + .dbg_master_axi_wready ( rv_socket_dbg_master_axi_wready ), + .dbg_master_axi_bid ( rv_socket_dbg_master_axi_bid ), + .dbg_master_axi_bresp ( rv_socket_dbg_master_axi_bresp ), + .dbg_master_axi_bvalid ( rv_socket_dbg_master_axi_bvalid ), + .dbg_master_axi_bready ( rv_socket_dbg_master_axi_bready ), + .dbg_master_axi_arid ( rv_socket_dbg_master_axi_arid ), + .dbg_master_axi_araddr ( rv_socket_dbg_master_axi_araddr ), + .dbg_master_axi_arlen ( rv_socket_dbg_master_axi_arlen ), + .dbg_master_axi_arsize ( rv_socket_dbg_master_axi_arsize ), + .dbg_master_axi_arburst ( rv_socket_dbg_master_axi_arburst ), + .dbg_master_axi_arlock ( rv_socket_dbg_master_axi_arlock ), + .dbg_master_axi_arcache ( rv_socket_dbg_master_axi_arcache ), + .dbg_master_axi_arprot ( rv_socket_dbg_master_axi_arprot ), + .dbg_master_axi_arregion ( rv_socket_dbg_master_axi_arregion ), + .dbg_master_axi_arqos ( rv_socket_dbg_master_axi_arqos ), + .dbg_master_axi_arvalid ( rv_socket_dbg_master_axi_arvalid ), + .dbg_master_axi_arready ( rv_socket_dbg_master_axi_arready ), + .dbg_master_axi_rid ( rv_socket_dbg_master_axi_rid ), + .dbg_master_axi_rdata ( rv_socket_dbg_master_axi_rdata ), + .dbg_master_axi_rresp ( rv_socket_dbg_master_axi_rresp ), + .dbg_master_axi_rlast ( rv_socket_dbg_master_axi_rlast ), + .dbg_master_axi_rvalid ( rv_socket_dbg_master_axi_rvalid ), + .dbg_master_axi_rready ( rv_socket_dbg_master_axi_rready ), + // To PULP core + .debug_req_o ( debug_req_core ) + ); + + end : dm_rv32_gen + else if ( CORE_SELECTOR inside {CORE_CV64A6} ) begin : dm_rv64_gen + + // Debug Core built to use 64-bits interface. + // It is technically compatible with all execution-based debug-mode cores. + // In practice, it has only been used with CVA6 + // BSCANE2 tap + (* keep_hierarchy = "yes" *) // DEBUG + custom_rv64_dbg_bscane riscv_dbg_u ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .unavailable_i ( '0 ), + .ndmreset_o ( ndmreset_o ), // Open + .dmactive_o ( dmactive_o ), // Open + // AXI Slave + .dbg_slave_axi_awid ( rv_socket_dbg_slave_axi_awid ), + .dbg_slave_axi_awaddr ( rv_socket_dbg_slave_axi_awaddr ), + .dbg_slave_axi_awlen ( rv_socket_dbg_slave_axi_awlen ), + .dbg_slave_axi_awsize ( rv_socket_dbg_slave_axi_awsize ), + .dbg_slave_axi_awburst ( rv_socket_dbg_slave_axi_awburst ), + .dbg_slave_axi_awlock ( rv_socket_dbg_slave_axi_awlock ), + .dbg_slave_axi_awcache ( rv_socket_dbg_slave_axi_awcache ), + .dbg_slave_axi_awprot ( rv_socket_dbg_slave_axi_awprot ), + .dbg_slave_axi_awqos ( rv_socket_dbg_slave_axi_awqos ), + .dbg_slave_axi_awvalid ( rv_socket_dbg_slave_axi_awvalid ), + .dbg_slave_axi_awready ( rv_socket_dbg_slave_axi_awready ), + .dbg_slave_axi_wdata ( rv_socket_dbg_slave_axi_wdata ), + .dbg_slave_axi_wstrb ( rv_socket_dbg_slave_axi_wstrb ), + .dbg_slave_axi_wlast ( rv_socket_dbg_slave_axi_wlast ), + .dbg_slave_axi_wvalid ( rv_socket_dbg_slave_axi_wvalid ), + .dbg_slave_axi_wready ( rv_socket_dbg_slave_axi_wready ), + .dbg_slave_axi_bid ( rv_socket_dbg_slave_axi_bid ), + .dbg_slave_axi_bresp ( rv_socket_dbg_slave_axi_bresp ), + .dbg_slave_axi_bvalid ( rv_socket_dbg_slave_axi_bvalid ), + .dbg_slave_axi_bready ( rv_socket_dbg_slave_axi_bready ), + .dbg_slave_axi_arid ( rv_socket_dbg_slave_axi_arid ), + .dbg_slave_axi_araddr ( rv_socket_dbg_slave_axi_araddr ), + .dbg_slave_axi_arlen ( rv_socket_dbg_slave_axi_arlen ), + .dbg_slave_axi_arsize ( rv_socket_dbg_slave_axi_arsize ), + .dbg_slave_axi_arburst ( rv_socket_dbg_slave_axi_arburst ), + .dbg_slave_axi_arlock ( rv_socket_dbg_slave_axi_arlock ), + .dbg_slave_axi_arcache ( rv_socket_dbg_slave_axi_arcache ), + .dbg_slave_axi_arprot ( rv_socket_dbg_slave_axi_arprot ), + .dbg_slave_axi_arqos ( rv_socket_dbg_slave_axi_arqos ), + .dbg_slave_axi_arvalid ( rv_socket_dbg_slave_axi_arvalid ), + .dbg_slave_axi_arready ( rv_socket_dbg_slave_axi_arready ), + .dbg_slave_axi_rid ( rv_socket_dbg_slave_axi_rid ), + .dbg_slave_axi_rdata ( rv_socket_dbg_slave_axi_rdata ), + .dbg_slave_axi_rresp ( rv_socket_dbg_slave_axi_rresp ), + .dbg_slave_axi_rlast ( rv_socket_dbg_slave_axi_rlast ), + .dbg_slave_axi_rvalid ( rv_socket_dbg_slave_axi_rvalid ), + .dbg_slave_axi_rready ( rv_socket_dbg_slave_axi_rready ), + // AXI Master + .dbg_master_axi_awid ( rv_socket_dbg_master_axi_awid ), + .dbg_master_axi_awaddr ( rv_socket_dbg_master_axi_awaddr ), + .dbg_master_axi_awlen ( rv_socket_dbg_master_axi_awlen ), + .dbg_master_axi_awsize ( rv_socket_dbg_master_axi_awsize ), + .dbg_master_axi_awburst ( rv_socket_dbg_master_axi_awburst ), + .dbg_master_axi_awlock ( rv_socket_dbg_master_axi_awlock ), + .dbg_master_axi_awcache ( rv_socket_dbg_master_axi_awcache ), + .dbg_master_axi_awprot ( rv_socket_dbg_master_axi_awprot ), + .dbg_master_axi_awregion ( rv_socket_dbg_master_axi_awregion ), + .dbg_master_axi_awqos ( rv_socket_dbg_master_axi_awqos ), + .dbg_master_axi_awvalid ( rv_socket_dbg_master_axi_awvalid ), + .dbg_master_axi_awready ( rv_socket_dbg_master_axi_awready ), + .dbg_master_axi_wdata ( rv_socket_dbg_master_axi_wdata ), + .dbg_master_axi_wstrb ( rv_socket_dbg_master_axi_wstrb ), + .dbg_master_axi_wlast ( rv_socket_dbg_master_axi_wlast ), + .dbg_master_axi_wvalid ( rv_socket_dbg_master_axi_wvalid ), + .dbg_master_axi_wready ( rv_socket_dbg_master_axi_wready ), + .dbg_master_axi_bid ( rv_socket_dbg_master_axi_bid ), + .dbg_master_axi_bresp ( rv_socket_dbg_master_axi_bresp ), + .dbg_master_axi_bvalid ( rv_socket_dbg_master_axi_bvalid ), + .dbg_master_axi_bready ( rv_socket_dbg_master_axi_bready ), + .dbg_master_axi_arid ( rv_socket_dbg_master_axi_arid ), + .dbg_master_axi_araddr ( rv_socket_dbg_master_axi_araddr ), + .dbg_master_axi_arlen ( rv_socket_dbg_master_axi_arlen ), + .dbg_master_axi_arsize ( rv_socket_dbg_master_axi_arsize ), + .dbg_master_axi_arburst ( rv_socket_dbg_master_axi_arburst ), + .dbg_master_axi_arlock ( rv_socket_dbg_master_axi_arlock ), + .dbg_master_axi_arcache ( rv_socket_dbg_master_axi_arcache ), + .dbg_master_axi_arprot ( rv_socket_dbg_master_axi_arprot ), + .dbg_master_axi_arregion ( rv_socket_dbg_master_axi_arregion ), + .dbg_master_axi_arqos ( rv_socket_dbg_master_axi_arqos ), + .dbg_master_axi_arvalid ( rv_socket_dbg_master_axi_arvalid ), + .dbg_master_axi_arready ( rv_socket_dbg_master_axi_arready ), + .dbg_master_axi_rid ( rv_socket_dbg_master_axi_rid ), + .dbg_master_axi_rdata ( rv_socket_dbg_master_axi_rdata ), + .dbg_master_axi_rresp ( rv_socket_dbg_master_axi_rresp ), + .dbg_master_axi_rlast ( rv_socket_dbg_master_axi_rlast ), + .dbg_master_axi_rvalid ( rv_socket_dbg_master_axi_rvalid ), + .dbg_master_axi_rready ( rv_socket_dbg_master_axi_rready ), + // To PULP core + .debug_req_o ( debug_req_core ) + ); + + end : dm_rv64_gen + else begin : dm_not_gen + + // Tie-off debug request signal to cores + assign debug_req_core = '0; + + // Sink unused interafces + `SINK_AXI_MASTER_INTERFACE(rv_socket_dbg_master); + `SINK_AXI_SLAVE_INTERFACE(rv_socket_dbg_slave); + + end : dm_not_gen + +endmodule : rv_socket diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/sys_master.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/sys_master.sv new file mode 100644 index 0000000000000000000000000000000000000000..71e869bcfa949b5fb05e968212405e4b3f80e805 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/sys_master.sv @@ -0,0 +1,648 @@ +// Author: Manuel Maddaluno +// Author: Stefano Mercogliano +// Description: Sys master - Instantiates the right masetr AXI based on the SoC profile and gives the clk and rst to the soc +// EMBEDDED -> Jtag2Axi +// HPC -> XDMA +// +// +//----------------------------------------------------------- EMBEDDED ----------------------------------------------------------------------------- +// +// ______________ __________ _____________ +// sys_clock | | soc_clock | | data [32b] | | data[MBUS_DATA_WIDTH] +// ----------->| Clock Wizard |------------>| Jtag2Axi |--------------| Dwidth Conv |--------------------------------------------------> +// |______________| | |__________| |_____________| +// | +// | soc_clock [10, 20, 50, 100 (MHz)] +// |--------------------------------------------------------------------------------------------------> +// +// +//-------------------------------------------------------------- HPC ------------------------------------------------------------------------------- +// +// _____________ ____________ +// pcie_refclk_p _____________ ______ | | XLEN | | +// -------------->| | | |---------------------->| Dwidth Conv |------------------->| Clock Conv |------------------> +// pcie_refclk_n | IBUFDS GTE4 |---->| XDMA | |--->| (optional) | |-------------->|____________|<----| +// | | | | | |_____________| | ______________ | +// -------------->|_____________| | | axi_aclk[250MHz] | | | | | soc_clock [10, 20, 50, 100, 250 (MHz)] +// | |--------------------------------------------------------->| Clock Wizard |-----------------> +// |______| |______________| +// +// +// +// +// + + +// Import packages +import uninasoc_pkg::*; + +// Import headers +`include "uninasoc_axi.svh" +`include "uninasoc_pcie.svh" + +module sys_master # ( + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 2 +) ( + + // EMBEDDED ONLY + // Input clock and reset + input logic sys_clock_i, + input logic sys_reset_i, + + // HPC ONLY + // Input clock and reset + input logic pcie_refclk_p_i, + input logic pcie_refclk_n_i, + input logic pcie_resetn_i, + // PCIe interface + `DEFINE_PCIE_PORTS, + + // Output clks + output logic clk_10MHz_o, + output logic clk_20MHz_o, + output logic clk_50MHz_o, + output logic clk_100MHz_o, + output logic clk_250MHz_o, // HPC ONLY + + // Output rsts for each clock domain (sync to the respective clock) + output logic rstn_10MHz_o, + output logic rstn_20MHz_o, + output logic rstn_50MHz_o, + output logic rstn_100MHz_o, + output logic rstn_250MHz_o, // HPC ONLY + + // AXI Master interface + `DEFINE_AXI_MASTER_PORTS(m, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) +); + + //////////////////////////////////// + // Main clock and reset selection // + //////////////////////////////////// + + // Main clock and main reset + logic main_clk; + logic main_rstn; + logic locked; + + // Main clock and reset assignment + generate + case (`MAIN_CLOCK_FREQ_MHZ) + 10 : begin + assign main_clk = clk_10MHz_o; + assign main_rstn = rstn_10MHz_o; + end + 20 : begin + assign main_clk = clk_20MHz_o; + assign main_rstn = rstn_20MHz_o; + end + 50 : begin + assign main_clk = clk_50MHz_o; + assign main_rstn = rstn_50MHz_o; + end + 100 : begin + assign main_clk = clk_100MHz_o; + assign main_rstn = rstn_100MHz_o; + end + 250 : begin // HPC only + assign main_clk = clk_250MHz_o; + assign main_rstn = rstn_250MHz_o; + end + default : begin + $fatal(1, "The given clock domain frequency (%d MHz) is not supported", `MAIN_CLOCK_FREQ_MHZ); + end + endcase + endgenerate + + ////////////////////////// + // Resets synchronizers // + ////////////////////////// + // Use locked signal as resets generator + // NOTE: this is temporary until we introduce a reset generation logic here + + // Reset sync for 10 MHz clock + xpm_cdc_async_rst #( + .DEST_SYNC_FF ( 4 ), // Use 4 sync registers + .RST_ACTIVE_HIGH ( 0 ) // Use active low reset + ) xpm_cdc_async_rst_10MHz_u ( + .src_arst ( locked ), + .dest_clk ( clk_10MHz_o ), + .dest_arst ( rstn_10MHz_o ) + ); + + // Reset sync for 20 MHz clock + xpm_cdc_async_rst #( + .DEST_SYNC_FF ( 4 ), // Use 4 sync registers + .RST_ACTIVE_HIGH ( 0 ) // Use active low reset + ) xpm_cdc_async_rst_20MHz_u ( + .src_arst ( locked ), + .dest_clk ( clk_20MHz_o ), + .dest_arst ( rstn_20MHz_o ) + ); + + // Reset sync for 50 MHz clock + xpm_cdc_async_rst #( + .DEST_SYNC_FF ( 4 ), // Use 4 sync registers + .RST_ACTIVE_HIGH ( 0 ) // Use active low reset + ) xpm_cdc_async_rst_50MHz_u ( + .src_arst ( locked ), + .dest_clk ( clk_50MHz_o ), + .dest_arst ( rstn_50MHz_o ) + ); + + // Reset sync for 100 MHz clock + xpm_cdc_async_rst #( + .DEST_SYNC_FF ( 4 ), // Use 4 sync registers + .RST_ACTIVE_HIGH ( 0 ) // Use active low reset + ) xpm_cdc_async_rst_100MHz_u ( + .src_arst ( locked ), + .dest_clk ( clk_100MHz_o ), + .dest_arst ( rstn_100MHz_o ) + ); + + // Reset sync for 250M Hz clock + xpm_cdc_async_rst #( + .DEST_SYNC_FF ( 4 ), // Use 4 sync registers + .RST_ACTIVE_HIGH ( 0 ) // Use active low reset + ) xpm_cdc_async_rst_250MHz_u ( + .src_arst ( locked ), + .dest_clk ( clk_250MHz_o ), + .dest_arst ( rstn_250MHz_o ) + ); + +`ifdef HPC + // ALVEO + + localparam int unsigned XDMA_DATA_WIDTH = 64; + + logic ibuf_out; + logic ibuf_os_odiv2; + + IBUFDS_GTE4 IBUFDS_GTE4_u ( + .O(ibuf_out), + .ODIV2(ibuf_os_odiv2), + .CEB(1'b0), + .I(pcie_refclk_p_i), + .IB(pcie_refclk_n_i) + ); + + logic axi_aclk; + logic axi_aresetn; + + `DECLARE_AXI_BUS(xdma_to_axi_dwidth_converter, XDMA_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + `DECLARE_AXI_BUS(axi_dwidth_converter_to_clock_converter, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // Clock Wizard + xlnx_clk_wiz_hpc clkwiz_u ( + .clk_in1 ( axi_aclk ), + .resetn ( axi_aresetn ), + .locked ( locked ), + .clk_250 ( clk_250MHz_o ), + .clk_100 ( clk_100MHz_o ), + .clk_50 ( clk_50MHz_o ), + .clk_20 ( clk_20MHz_o ), + .clk_10 ( clk_10MHz_o ) + ); + + // XDMA Master + xlnx_xdma xlnx_xdma_u ( + // Input clock and reset + .sys_clk ( ibuf_os_odiv2 ), + .sys_clk_gt ( ibuf_out ), + .sys_rst_n ( pcie_resetn_i ), + + // Output clock + .axi_aclk ( axi_aclk ), + .axi_aresetn ( axi_aresetn ), + + // PCI interface + .pci_exp_rxn ( pci_exp_rxn_i ), + .pci_exp_rxp ( pci_exp_rxp_i ), + .pci_exp_txn ( pci_exp_txn_o ), + .pci_exp_txp ( pci_exp_txp_o ), + + // Interrupts interface + .usr_irq_req ( 0 ), + + // AXI Master + .m_axib_awid ( xdma_to_axi_dwidth_converter_axi_awid ), + .m_axib_awaddr ( xdma_to_axi_dwidth_converter_axi_awaddr ), + .m_axib_awlen ( xdma_to_axi_dwidth_converter_axi_awlen ), + .m_axib_awsize ( xdma_to_axi_dwidth_converter_axi_awsize ), + .m_axib_awburst ( xdma_to_axi_dwidth_converter_axi_awburst ), + .m_axib_awlock ( xdma_to_axi_dwidth_converter_axi_awlock ), + .m_axib_awcache ( xdma_to_axi_dwidth_converter_axi_awcache ), + .m_axib_awprot ( xdma_to_axi_dwidth_converter_axi_awprot ), + // .m_axib_awqos ( xdma_to_axi_dwidth_converter_axi_awqos ), + .m_axib_awvalid ( xdma_to_axi_dwidth_converter_axi_awvalid ), + .m_axib_awready ( xdma_to_axi_dwidth_converter_axi_awready ), + .m_axib_wdata ( xdma_to_axi_dwidth_converter_axi_wdata ), + .m_axib_wstrb ( xdma_to_axi_dwidth_converter_axi_wstrb ), + .m_axib_wlast ( xdma_to_axi_dwidth_converter_axi_wlast ), + .m_axib_wvalid ( xdma_to_axi_dwidth_converter_axi_wvalid ), + .m_axib_wready ( xdma_to_axi_dwidth_converter_axi_wready ), + .m_axib_bid ( xdma_to_axi_dwidth_converter_axi_bid ), + .m_axib_bresp ( xdma_to_axi_dwidth_converter_axi_bresp ), + .m_axib_bvalid ( xdma_to_axi_dwidth_converter_axi_bvalid ), + .m_axib_bready ( xdma_to_axi_dwidth_converter_axi_bready ), + .m_axib_arid ( xdma_to_axi_dwidth_converter_axi_arid ), + .m_axib_araddr ( xdma_to_axi_dwidth_converter_axi_araddr ), + .m_axib_arlen ( xdma_to_axi_dwidth_converter_axi_arlen ), + .m_axib_arsize ( xdma_to_axi_dwidth_converter_axi_arsize ), + .m_axib_arburst ( xdma_to_axi_dwidth_converter_axi_arburst ), + .m_axib_arlock ( xdma_to_axi_dwidth_converter_axi_arlock ), + .m_axib_arcache ( xdma_to_axi_dwidth_converter_axi_arcache ), + .m_axib_arprot ( xdma_to_axi_dwidth_converter_axi_arprot ), + // .m_axib_arqos ( xdma_to_axi_dwidth_converter_axi_arqos ), + .m_axib_arvalid ( xdma_to_axi_dwidth_converter_axi_arvalid ), + .m_axib_arready ( xdma_to_axi_dwidth_converter_axi_arready ), + .m_axib_rid ( xdma_to_axi_dwidth_converter_axi_rid ), + .m_axib_rdata ( xdma_to_axi_dwidth_converter_axi_rdata ), + .m_axib_rresp ( xdma_to_axi_dwidth_converter_axi_rresp ), + .m_axib_rlast ( xdma_to_axi_dwidth_converter_axi_rlast ), + .m_axib_rvalid ( xdma_to_axi_dwidth_converter_axi_rvalid ), + .m_axib_rready ( xdma_to_axi_dwidth_converter_axi_rready ), + + // AXI lite (configuration channel) + .s_axil_awaddr (12'b0), + .s_axil_awvalid (1'b0), + .s_axil_awready (), + .s_axil_wdata (32'b0), + .s_axil_wstrb (4'b0), + .s_axil_wvalid (1'b0), + .s_axil_wready (), + .s_axil_bresp (), + .s_axil_bvalid (), + .s_axil_bready (1'b0), + .s_axil_araddr (12'b0), + .s_axil_arvalid (1'b0), + .s_axil_arready (), + .s_axil_rdata (), + .s_axil_rresp (), + .s_axil_rvalid (), + .s_axil_rready (1'b0), + .s_axil_awprot (3'b0), + .s_axil_arprot (3'b0) + ); + + // Use a Dwidth converter if System XLEN is 32-bits wide. + // As we need to adapt from 64-bits XDMA interface. + if ( MBUS_DATA_WIDTH != 64 ) begin : gen_dwidth_conv + xlnx_axi_dwidth_64_to_32_converter xlnx_axi_dwidth_64_to_32_converter_u ( + .s_axi_aclk ( axi_aclk ), + .s_axi_aresetn ( axi_aresetn ), + + // Slave from XDMA + .s_axi_awid ( xdma_to_axi_dwidth_converter_axi_awid ), + .s_axi_awaddr ( xdma_to_axi_dwidth_converter_axi_awaddr ), + .s_axi_awlen ( xdma_to_axi_dwidth_converter_axi_awlen ), + .s_axi_awsize ( xdma_to_axi_dwidth_converter_axi_awsize ), + .s_axi_awburst ( xdma_to_axi_dwidth_converter_axi_awburst ), + .s_axi_awvalid ( xdma_to_axi_dwidth_converter_axi_awvalid ), + .s_axi_awready ( xdma_to_axi_dwidth_converter_axi_awready ), + .s_axi_wdata ( xdma_to_axi_dwidth_converter_axi_wdata ), + .s_axi_wstrb ( xdma_to_axi_dwidth_converter_axi_wstrb ), + .s_axi_wlast ( xdma_to_axi_dwidth_converter_axi_wlast ), + .s_axi_wvalid ( xdma_to_axi_dwidth_converter_axi_wvalid ), + .s_axi_wready ( xdma_to_axi_dwidth_converter_axi_wready ), + .s_axi_bid ( xdma_to_axi_dwidth_converter_axi_bid ), + .s_axi_bresp ( xdma_to_axi_dwidth_converter_axi_bresp ), + .s_axi_bvalid ( xdma_to_axi_dwidth_converter_axi_bvalid ), + .s_axi_bready ( xdma_to_axi_dwidth_converter_axi_bready ), + .s_axi_arid ( xdma_to_axi_dwidth_converter_axi_arid ), + .s_axi_araddr ( xdma_to_axi_dwidth_converter_axi_araddr ), + .s_axi_arlen ( xdma_to_axi_dwidth_converter_axi_arlen ), + .s_axi_arsize ( xdma_to_axi_dwidth_converter_axi_arsize ), + .s_axi_arburst ( xdma_to_axi_dwidth_converter_axi_arburst ), + .s_axi_arvalid ( xdma_to_axi_dwidth_converter_axi_arvalid ), + .s_axi_arready ( xdma_to_axi_dwidth_converter_axi_arready ), + .s_axi_rid ( xdma_to_axi_dwidth_converter_axi_rid ), + .s_axi_rdata ( xdma_to_axi_dwidth_converter_axi_rdata ), + .s_axi_rresp ( xdma_to_axi_dwidth_converter_axi_rresp ), + .s_axi_rlast ( xdma_to_axi_dwidth_converter_axi_rlast ), + .s_axi_rvalid ( xdma_to_axi_dwidth_converter_axi_rvalid ), + .s_axi_rready ( xdma_to_axi_dwidth_converter_axi_rready ), + .s_axi_awlock ( xdma_to_axi_dwidth_converter_axi_awlock ), + .s_axi_awcache ( xdma_to_axi_dwidth_converter_axi_awcache ), + .s_axi_awprot ( xdma_to_axi_dwidth_converter_axi_awprot ), + .s_axi_awqos ( 0 ), + .s_axi_awregion ( 0 ), + .s_axi_arlock ( xdma_to_axi_dwidth_converter_axi_arlock ), + .s_axi_arcache ( xdma_to_axi_dwidth_converter_axi_arcache ), + .s_axi_arprot ( xdma_to_axi_dwidth_converter_axi_arprot ), + .s_axi_arqos ( 0 ), + .s_axi_arregion ( 0 ), + + + // Master to clock_converter + // .m_axi_awid ( dwidth_converter_to_clock_converter_axi_awid ), + .m_axi_awaddr ( axi_dwidth_converter_to_clock_converter_axi_awaddr ), + .m_axi_awlen ( axi_dwidth_converter_to_clock_converter_axi_awlen ), + .m_axi_awsize ( axi_dwidth_converter_to_clock_converter_axi_awsize ), + .m_axi_awburst ( axi_dwidth_converter_to_clock_converter_axi_awburst ), + .m_axi_awlock ( axi_dwidth_converter_to_clock_converter_axi_awlock ), + .m_axi_awcache ( axi_dwidth_converter_to_clock_converter_axi_awcache ), + .m_axi_awprot ( axi_dwidth_converter_to_clock_converter_axi_awprot ), + .m_axi_awqos ( axi_dwidth_converter_to_clock_converter_axi_awqos ), + .m_axi_awvalid ( axi_dwidth_converter_to_clock_converter_axi_awvalid ), + .m_axi_awready ( axi_dwidth_converter_to_clock_converter_axi_awready ), + .m_axi_wdata ( axi_dwidth_converter_to_clock_converter_axi_wdata ), + .m_axi_wstrb ( axi_dwidth_converter_to_clock_converter_axi_wstrb ), + .m_axi_wlast ( axi_dwidth_converter_to_clock_converter_axi_wlast ), + .m_axi_wvalid ( axi_dwidth_converter_to_clock_converter_axi_wvalid ), + .m_axi_wready ( axi_dwidth_converter_to_clock_converter_axi_wready ), + // .m_axi_bid ( axi_dwidth_converter_to_clock_converter_axi_bid ), + .m_axi_bresp ( axi_dwidth_converter_to_clock_converter_axi_bresp ), + .m_axi_bvalid ( axi_dwidth_converter_to_clock_converter_axi_bvalid ), + .m_axi_bready ( axi_dwidth_converter_to_clock_converter_axi_bready ), + // .m_axi_arid ( axi_dwidth_converter_to_clock_converter_axi_arid ), + .m_axi_araddr ( axi_dwidth_converter_to_clock_converter_axi_araddr ), + .m_axi_arlen ( axi_dwidth_converter_to_clock_converter_axi_arlen ), + .m_axi_arsize ( axi_dwidth_converter_to_clock_converter_axi_arsize ), + .m_axi_arburst ( axi_dwidth_converter_to_clock_converter_axi_arburst ), + .m_axi_arlock ( axi_dwidth_converter_to_clock_converter_axi_arlock ), + .m_axi_arcache ( axi_dwidth_converter_to_clock_converter_axi_arcache ), + .m_axi_arprot ( axi_dwidth_converter_to_clock_converter_axi_arprot ), + .m_axi_arqos ( axi_dwidth_converter_to_clock_converter_axi_arqos ), + .m_axi_arvalid ( axi_dwidth_converter_to_clock_converter_axi_arvalid ), + .m_axi_arready ( axi_dwidth_converter_to_clock_converter_axi_arready ), + // .m_axi_rid ( axi_dwidth_converter_to_clock_converter_axi_rid ), + .m_axi_rdata ( axi_dwidth_converter_to_clock_converter_axi_rdata ), + .m_axi_rresp ( axi_dwidth_converter_to_clock_converter_axi_rresp ), + .m_axi_rlast ( axi_dwidth_converter_to_clock_converter_axi_rlast ), + .m_axi_rvalid ( axi_dwidth_converter_to_clock_converter_axi_rvalid ), + .m_axi_rready ( axi_dwidth_converter_to_clock_converter_axi_rready ) + ); + + assign axi_dwidth_converter_to_clock_converter_axi_awid = '0; + assign axi_dwidth_converter_to_clock_converter_axi_arid = '0; + assign axi_dwidth_converter_to_clock_converter_axi_awregion = '0; + assign axi_dwidth_converter_to_clock_converter_axi_arregion = '0; + end : gen_dwidth_conv + else begin : no_dwidth_conv + `ASSIGN_AXI_BUS (axi_dwidth_converter_to_clock_converter, xdma_to_axi_dwidth_converter); + end : no_dwidth_conv + + // Clock converter + axi_clock_converter_wrapper # ( + .LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( LOCAL_ID_WIDTH ) + ) axi_clock_converter_u ( + .s_axi_aclk ( axi_aclk ), + .s_axi_aresetn ( axi_aresetn ), + + .m_axi_aclk ( main_clk ), + .m_axi_aresetn ( main_rstn ), + + .s_axi_awid ( axi_dwidth_converter_to_clock_converter_axi_awid ), + .s_axi_awaddr ( axi_dwidth_converter_to_clock_converter_axi_awaddr ), + .s_axi_awlen ( axi_dwidth_converter_to_clock_converter_axi_awlen ), + .s_axi_awsize ( axi_dwidth_converter_to_clock_converter_axi_awsize ), + .s_axi_awburst ( axi_dwidth_converter_to_clock_converter_axi_awburst ), + .s_axi_awlock ( axi_dwidth_converter_to_clock_converter_axi_awlock ), + .s_axi_awcache ( axi_dwidth_converter_to_clock_converter_axi_awcache ), + .s_axi_awprot ( axi_dwidth_converter_to_clock_converter_axi_awprot ), + .s_axi_awqos ( axi_dwidth_converter_to_clock_converter_axi_awqos ), + .s_axi_awvalid ( axi_dwidth_converter_to_clock_converter_axi_awvalid ), + .s_axi_awready ( axi_dwidth_converter_to_clock_converter_axi_awready ), + .s_axi_awregion ( axi_dwidth_converter_to_clock_converter_axi_awregion ), + .s_axi_wdata ( axi_dwidth_converter_to_clock_converter_axi_wdata ), + .s_axi_wstrb ( axi_dwidth_converter_to_clock_converter_axi_wstrb ), + .s_axi_wlast ( axi_dwidth_converter_to_clock_converter_axi_wlast ), + .s_axi_wvalid ( axi_dwidth_converter_to_clock_converter_axi_wvalid ), + .s_axi_wready ( axi_dwidth_converter_to_clock_converter_axi_wready ), + .s_axi_bid ( axi_dwidth_converter_to_clock_converter_axi_bid ), + .s_axi_bresp ( axi_dwidth_converter_to_clock_converter_axi_bresp ), + .s_axi_bvalid ( axi_dwidth_converter_to_clock_converter_axi_bvalid ), + .s_axi_bready ( axi_dwidth_converter_to_clock_converter_axi_bready ), + .s_axi_arid ( axi_dwidth_converter_to_clock_converter_axi_arid ), + .s_axi_araddr ( axi_dwidth_converter_to_clock_converter_axi_araddr ), + .s_axi_arlen ( axi_dwidth_converter_to_clock_converter_axi_arlen ), + .s_axi_arsize ( axi_dwidth_converter_to_clock_converter_axi_arsize ), + .s_axi_arburst ( axi_dwidth_converter_to_clock_converter_axi_arburst ), + .s_axi_arlock ( axi_dwidth_converter_to_clock_converter_axi_arlock ), + .s_axi_arregion ( axi_dwidth_converter_to_clock_converter_axi_arregion ), + .s_axi_arcache ( axi_dwidth_converter_to_clock_converter_axi_arcache ), + .s_axi_arprot ( axi_dwidth_converter_to_clock_converter_axi_arprot ), + .s_axi_arqos ( axi_dwidth_converter_to_clock_converter_axi_arqos ), + .s_axi_arvalid ( axi_dwidth_converter_to_clock_converter_axi_arvalid ), + .s_axi_arready ( axi_dwidth_converter_to_clock_converter_axi_arready ), + .s_axi_rid ( axi_dwidth_converter_to_clock_converter_axi_rid ), + .s_axi_rdata ( axi_dwidth_converter_to_clock_converter_axi_rdata ), + .s_axi_rresp ( axi_dwidth_converter_to_clock_converter_axi_rresp ), + .s_axi_rlast ( axi_dwidth_converter_to_clock_converter_axi_rlast ), + .s_axi_rvalid ( axi_dwidth_converter_to_clock_converter_axi_rvalid ), + .s_axi_rready ( axi_dwidth_converter_to_clock_converter_axi_rready ), + + + // Master to output port + .m_axi_awid ( m_axi_awid ), + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awregion ( m_axi_awregion ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bid ( m_axi_bid ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_arid ( m_axi_arid ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arregion ( m_axi_arregion ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rid ( m_axi_rid ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + ); + +`elsif EMBEDDED + // EMBEDDED + + // Drive unused signals + assign pci_exp_txn_o = '0; + assign pci_exp_txp_o = '0; + + assign m_axi_awregion = '0; + assign m_axi_arregion = '0; + + // PLL + xlnx_clk_wiz clkwiz_u ( + .clk_in1 ( sys_clock_i ), + .resetn ( ~sys_reset_i ), + .locked ( locked ), + .clk_100 ( clk_100MHz_o ), + .clk_50 ( clk_50MHz_o ), + .clk_20 ( clk_20MHz_o ), + .clk_10 ( clk_10MHz_o ) + ); + + // The JTAG2AXI ip is always built with a 32-bits DWIDTH. We use a DWIDTH + // converter if the SoC is built at 64 bits. While it is possible to build + // JTAG2AXI as a 64-bits ip, it would also require a change to the load_binary + // script, which we want to avoid. + `DECLARE_AXI_BUS(jtag_to_axi_dwidth_converter, 32, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH); + + // JTAG2AXI Master + xlnx_jtag_axi jtag_axi_u ( + .aclk ( main_clk ), // input wire aclk + .aresetn ( main_rstn ), // input wire aresetn + .m_axi_awid ( jtag_to_axi_dwidth_converter_axi_awid ), // output wire [1 : 0] m_axi_awid + .m_axi_awaddr ( jtag_to_axi_dwidth_converter_axi_awaddr ), // output wire [31 : 0] m_axi_awid + .m_axi_awlen ( jtag_to_axi_dwidth_converter_axi_awlen ), // output wire [7 : 0] m_axi_awlen + .m_axi_awsize ( jtag_to_axi_dwidth_converter_axi_awsize ), // output wire [2 : 0] m_axi_awsize + .m_axi_awburst ( jtag_to_axi_dwidth_converter_axi_awburst ), // output wire [1 : 0] m_axi_awburst + .m_axi_awlock ( jtag_to_axi_dwidth_converter_axi_awlock ), // output wire m_axi_awlock + .m_axi_awcache ( jtag_to_axi_dwidth_converter_axi_awcache ), // output wire [3 : 0] m_axi_awcache + .m_axi_awprot ( jtag_to_axi_dwidth_converter_axi_awprot ), // output wire [2 : 0] m_axi_awprot + .m_axi_awqos ( jtag_to_axi_dwidth_converter_axi_awqos ), // output wire [3 : 0] m_axi_awqos + .m_axi_awvalid ( jtag_to_axi_dwidth_converter_axi_awvalid ), // output wire m_axi_awvalid + .m_axi_awready ( jtag_to_axi_dwidth_converter_axi_awready ), // input wire m_axi_awready + .m_axi_wdata ( jtag_to_axi_dwidth_converter_axi_wdata ), // output wire [31 : 0] m_axi_wdata + .m_axi_wstrb ( jtag_to_axi_dwidth_converter_axi_wstrb ), // output wire [3 : 0] m_axi_wstrb + .m_axi_wlast ( jtag_to_axi_dwidth_converter_axi_wlast ), // output wire m_axi_wlast + .m_axi_wvalid ( jtag_to_axi_dwidth_converter_axi_wvalid ), // output wire m_axi_wvalid + .m_axi_wready ( jtag_to_axi_dwidth_converter_axi_wready ), // input wire m_axi_wready + .m_axi_bid ( jtag_to_axi_dwidth_converter_axi_bid ), // input wire [0 : 0] m_axi_bid + .m_axi_bresp ( jtag_to_axi_dwidth_converter_axi_bresp ), // input wire [1 : 0] m_axi_bresp + .m_axi_bvalid ( jtag_to_axi_dwidth_converter_axi_bvalid ), // input wire m_axi_bvalid + .m_axi_bready ( jtag_to_axi_dwidth_converter_axi_bready ), // output wire m_axi_bready + .m_axi_arid ( jtag_to_axi_dwidth_converter_axi_arid ), // output wire [0 : 0] m_axi_arid + .m_axi_araddr ( jtag_to_axi_dwidth_converter_axi_araddr ), // output wire [31 : 0] m_axi_araddr + .m_axi_arlen ( jtag_to_axi_dwidth_converter_axi_arlen ), // output wire [7 : 0] m_axi_arlen + .m_axi_arsize ( jtag_to_axi_dwidth_converter_axi_arsize ), // output wire [2 : 0] m_axi_arsize + .m_axi_arburst ( jtag_to_axi_dwidth_converter_axi_arburst ), // output wire [1 : 0] m_axi_arburst + .m_axi_arlock ( jtag_to_axi_dwidth_converter_axi_arlock ), // output wire m_axi_arlock + .m_axi_arcache ( jtag_to_axi_dwidth_converter_axi_arcache ), // output wire [3 : 0] m_axi_arcache + .m_axi_arprot ( jtag_to_axi_dwidth_converter_axi_arprot ), // output wire [2 : 0] m_axi_arprot + .m_axi_arqos ( jtag_to_axi_dwidth_converter_axi_arqos ), // output wire [3 : 0] m_axi_arqos + .m_axi_arvalid ( jtag_to_axi_dwidth_converter_axi_arvalid ), // output wire m_axi_arvalid + .m_axi_arready ( jtag_to_axi_dwidth_converter_axi_arready ), // input wire m_axi_arready + .m_axi_rid ( jtag_to_axi_dwidth_converter_axi_rid ), // input wire [1 : 0] m_axi_rid + .m_axi_rdata ( jtag_to_axi_dwidth_converter_axi_rdata ), // input wire [31 : 0] m_axi_rdata + .m_axi_rresp ( jtag_to_axi_dwidth_converter_axi_rresp ), // input wire [1 : 0] m_axi_rresp + .m_axi_rlast ( jtag_to_axi_dwidth_converter_axi_rlast ), // input wire m_axi_rlast + .m_axi_rvalid ( jtag_to_axi_dwidth_converter_axi_rvalid ), // input wire m_axi_rvalid + .m_axi_rready ( jtag_to_axi_dwidth_converter_axi_rready ) // output wire m_axi_rready + ); + + // In order to comply with the load binary script, we need a 32 to 64 dwidth converter + if( MBUS_DATA_WIDTH == 64 ) begin: dwidth_converter + + xlnx_axi_dwidth_32_to_64_converter xlnx_axi_dwidth_32_to_64_converter_u ( + .s_axi_aclk ( main_clk ), + .s_axi_aresetn ( main_rstn ), + + // Slave from XDMA + .s_axi_awid ( jtag_to_axi_dwidth_converter_axi_awid ), + .s_axi_awaddr ( jtag_to_axi_dwidth_converter_axi_awaddr ), + .s_axi_awlen ( jtag_to_axi_dwidth_converter_axi_awlen ), + .s_axi_awsize ( jtag_to_axi_dwidth_converter_axi_awsize ), + .s_axi_awburst ( jtag_to_axi_dwidth_converter_axi_awburst ), + .s_axi_awvalid ( jtag_to_axi_dwidth_converter_axi_awvalid ), + .s_axi_awready ( jtag_to_axi_dwidth_converter_axi_awready ), + .s_axi_wdata ( jtag_to_axi_dwidth_converter_axi_wdata ), + .s_axi_wstrb ( jtag_to_axi_dwidth_converter_axi_wstrb ), + .s_axi_wlast ( jtag_to_axi_dwidth_converter_axi_wlast ), + .s_axi_wvalid ( jtag_to_axi_dwidth_converter_axi_wvalid ), + .s_axi_wready ( jtag_to_axi_dwidth_converter_axi_wready ), + .s_axi_bid ( jtag_to_axi_dwidth_converter_axi_bid ), + .s_axi_bresp ( jtag_to_axi_dwidth_converter_axi_bresp ), + .s_axi_bvalid ( jtag_to_axi_dwidth_converter_axi_bvalid ), + .s_axi_bready ( jtag_to_axi_dwidth_converter_axi_bready ), + .s_axi_arid ( jtag_to_axi_dwidth_converter_axi_arid ), + .s_axi_araddr ( jtag_to_axi_dwidth_converter_axi_araddr ), + .s_axi_arlen ( jtag_to_axi_dwidth_converter_axi_arlen ), + .s_axi_arsize ( jtag_to_axi_dwidth_converter_axi_arsize ), + .s_axi_arburst ( jtag_to_axi_dwidth_converter_axi_arburst ), + .s_axi_arvalid ( jtag_to_axi_dwidth_converter_axi_arvalid ), + .s_axi_arready ( jtag_to_axi_dwidth_converter_axi_arready ), + .s_axi_rid ( jtag_to_axi_dwidth_converter_axi_rid ), + .s_axi_rdata ( jtag_to_axi_dwidth_converter_axi_rdata ), + .s_axi_rresp ( jtag_to_axi_dwidth_converter_axi_rresp ), + .s_axi_rlast ( jtag_to_axi_dwidth_converter_axi_rlast ), + .s_axi_rvalid ( jtag_to_axi_dwidth_converter_axi_rvalid ), + .s_axi_rready ( jtag_to_axi_dwidth_converter_axi_rready ), + .s_axi_awlock ( jtag_to_axi_dwidth_converter_axi_awlock ), + .s_axi_awcache ( jtag_to_axi_dwidth_converter_axi_awcache ), + .s_axi_awprot ( jtag_to_axi_dwidth_converter_axi_awprot ), + .s_axi_awqos ( 0 ), + .s_axi_awregion ( 0 ), + .s_axi_arlock ( jtag_to_axi_dwidth_converter_axi_arlock ), + .s_axi_arcache ( jtag_to_axi_dwidth_converter_axi_arcache ), + .s_axi_arprot ( jtag_to_axi_dwidth_converter_axi_arprot ), + .s_axi_arqos ( 0 ), + .s_axi_arregion ( 0 ), + + // Master to clock_converter + .m_axi_awaddr ( m_axi_awaddr ), + .m_axi_awlen ( m_axi_awlen ), + .m_axi_awsize ( m_axi_awsize ), + .m_axi_awburst ( m_axi_awburst ), + .m_axi_awlock ( m_axi_awlock ), + .m_axi_awcache ( m_axi_awcache ), + .m_axi_awprot ( m_axi_awprot ), + .m_axi_awqos ( m_axi_awqos ), + .m_axi_awvalid ( m_axi_awvalid ), + .m_axi_awready ( m_axi_awready ), + .m_axi_wdata ( m_axi_wdata ), + .m_axi_wstrb ( m_axi_wstrb ), + .m_axi_wlast ( m_axi_wlast ), + .m_axi_wvalid ( m_axi_wvalid ), + .m_axi_wready ( m_axi_wready ), + .m_axi_bresp ( m_axi_bresp ), + .m_axi_bvalid ( m_axi_bvalid ), + .m_axi_bready ( m_axi_bready ), + .m_axi_araddr ( m_axi_araddr ), + .m_axi_arlen ( m_axi_arlen ), + .m_axi_arsize ( m_axi_arsize ), + .m_axi_arburst ( m_axi_arburst ), + .m_axi_arlock ( m_axi_arlock ), + .m_axi_arcache ( m_axi_arcache ), + .m_axi_arprot ( m_axi_arprot ), + .m_axi_arqos ( m_axi_arqos ), + .m_axi_arvalid ( m_axi_arvalid ), + .m_axi_arready ( m_axi_arready ), + .m_axi_rdata ( m_axi_rdata ), + .m_axi_rresp ( m_axi_rresp ), + .m_axi_rlast ( m_axi_rlast ), + .m_axi_rvalid ( m_axi_rvalid ), + .m_axi_rready ( m_axi_rready ) + ); + + assign m_axi_awid = '0; + assign m_axi_arid = '0; + + end: dwidth_converter + else begin: no_dwidth_conversion + + `ASSIGN_AXI_BUS (m, jtag_to_axi_dwidth_converter); + + end: no_dwidth_conversion + +`endif + +endmodule : sys_master diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc.sv new file mode 100644 index 0000000000000000000000000000000000000000..25713959db9346ce960e05fac99acf9ed373d649 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc.sv @@ -0,0 +1,1330 @@ +// Author: Vincenzo Maisto +// Author: Stefano Mercogliano +// Author: Manuel Maddaluno +// Author: Zaira Abdel Majid +// Author: Valerio Di Domenico +// Description: FPGA-ready top-level soft-SoC module for both hpc and embedded profiles. + +// System architecture: +// +// __________ ________ +// ____________ | | | | +// | | | |------------------>| BRAM | +// | sys_master |----------------------------------->| | |________| +// |____________| | | ___________ +// ______________ | | | | +// | |--------------------------------->| |------------------>| DDR4CH1 | +// | Debug Module | | Main | |___________| +// |______________|<---------------------------------| Bus | __________________ +// | (MBUS) | | | +// | |------------------>| High-performance | +// | | | bus |<------\ +// | |<------------------| (HBUS) | | +// | | |__________________| | +// | | ______________ | +// | | | |-----------/ +// | |------------------>| HLS CONV2D | +// | | |______________|-----------\ +// | | ________________ | +// | | | | v +// | |------------------>| Peripheral bus |---------\ +// | | | (PBUS) | | +// | | |________________| | peripheral +// _________ ____________ | | ________________ | interrupts +// | | | | | | | | | +// | vio |----------->| rv_socket |------------>| |------------------>| PLIC |<--------/ +// |_________| |____________| | | |________________| +// ^ | | | +// | |__________| | +// | | +// \___________________________________________________________/ +// platform interrupt + +///////////////////// +// Import packages // +///////////////////// + +import uninasoc_pkg::*; + +//////////////////// +// Import headers // +//////////////////// + +`include "uninasoc_axi.svh" + +`ifdef HPC + `include "uninasoc_pcie.svh" + `include "uninasoc_ddr4.svh" +`endif + +/////////////////////// +// Module definition // +/////////////////////// + +module uninasoc ( + + `ifdef EMBEDDED + // Clock and reset + input logic sys_clock_i, + input logic sys_reset_i, + + // UART interface + input logic uart_rx_i, + output logic uart_tx_o, + + // GPIOs + input logic [GPIO_IN_WIDTH -1 : 0] gpio_in_i, + output logic [GPIO_OUT_WIDTH -1 : 0] gpio_out_o + `elsif HPC + // DDR4 Channel 0 differential clock + input logic clk_300mhz_0_p_i, + input logic clk_300mhz_0_n_i, + // DDR4 Channel 0 interface + `DEFINE_DDR4_PORTS(0), + + // DDR4 Channel 1 differential clock + input logic clk_300mhz_1_p_i, + input logic clk_300mhz_1_n_i, + // DDR4 Channel 1 interface + `DEFINE_DDR4_PORTS(1), + + // // DDR4 Channel 2 differential clock + // input logic clk_300mhz_2_p_i, + // input logic clk_300mhz_2_n_i, + // // DDR4 Channel 2 interface + // `DEFINE_DDR4_PORTS(2), + + // PCIe clock and reset + input logic pcie_refclk_p_i, + input logic pcie_refclk_n_i, + input logic pcie_resetn_i, + + // PCIe interface + `DEFINE_PCIE_PORTS + `endif + +); + + ///////////////////// + // Local variables // + ///////////////////// + + localparam peripherals_interrupts_num = 4; + localparam HBUS_AXI_DATAWIDTH = 512; + + /////////////////// + // Local Signals // + ////////////////// + + // CLOCKS + logic main_clk; + logic clk_10MHz; + logic clk_20MHz; + logic clk_50MHz; + logic clk_100MHz; + logic clk_250MHz; // HPC ONLY + + // RESETS + logic main_rstn; + logic rstn_10MHz; + logic rstn_20MHz; + logic rstn_50MHz; + logic rstn_100MHz; + logic rstn_250MHz; // HPC ONLY + + // VIO Signals + logic vio_resetn; + + // Socket interrupts + logic [31:0] rv_socket_interrupt_line; + + // Peripheral bus interrupts + logic [peripherals_interrupts_num-1:0] pbus_int_line; + + ///////////////////////////////////////// + // Buses declaration and concatenation // + ///////////////////////////////////////// + `include "mbus_buses.svinc" + + /////////////////////// + // Clock assignments // + /////////////////////// + `include "uninasoc_clk_assignments.svinc" + + /////////////////////// + // Local assignments // + /////////////////////// + + ///////////// + // Modules // + ///////////// + + // Virtual I/O + + xlnx_vio vio_inst ( + .clk ( main_clk ), + .probe_out0 ( vio_resetn ), + .probe_out1 ( ), + .probe_in0 ( ) + ); + + // Axi Crossbar + xlnx_main_crossbar main_xbar_u ( + .aclk ( main_clk ), // input + .aresetn ( main_rstn ), // input + .s_axi_awid ( MBUS_masters_axi_awid ), // input + .s_axi_awaddr ( MBUS_masters_axi_awaddr ), // input + .s_axi_awlen ( MBUS_masters_axi_awlen ), // input + .s_axi_awsize ( MBUS_masters_axi_awsize ), // input + .s_axi_awburst ( MBUS_masters_axi_awburst ), // input + .s_axi_awlock ( MBUS_masters_axi_awlock ), // input + .s_axi_awcache ( MBUS_masters_axi_awcache ), // input + .s_axi_awprot ( MBUS_masters_axi_awprot ), // input + .s_axi_awqos ( MBUS_masters_axi_awqos ), // input + .s_axi_awvalid ( MBUS_masters_axi_awvalid ), // input + .s_axi_awready ( MBUS_masters_axi_awready ), // output + .s_axi_wdata ( MBUS_masters_axi_wdata ), // input + .s_axi_wstrb ( MBUS_masters_axi_wstrb ), // input + .s_axi_wlast ( MBUS_masters_axi_wlast ), // input + .s_axi_wvalid ( MBUS_masters_axi_wvalid ), // input + .s_axi_wready ( MBUS_masters_axi_wready ), // output + .s_axi_bid ( MBUS_masters_axi_bid ), // output + .s_axi_bresp ( MBUS_masters_axi_bresp ), // output + .s_axi_bvalid ( MBUS_masters_axi_bvalid ), // output + .s_axi_bready ( MBUS_masters_axi_bready ), // input + .s_axi_arid ( MBUS_masters_axi_arid ), // output + .s_axi_araddr ( MBUS_masters_axi_araddr ), // input + .s_axi_arlen ( MBUS_masters_axi_arlen ), // input + .s_axi_arsize ( MBUS_masters_axi_arsize ), // input + .s_axi_arburst ( MBUS_masters_axi_arburst ), // input + .s_axi_arlock ( MBUS_masters_axi_arlock ), // input + .s_axi_arcache ( MBUS_masters_axi_arcache ), // input + .s_axi_arprot ( MBUS_masters_axi_arprot ), // input + .s_axi_arqos ( MBUS_masters_axi_arqos ), // input + .s_axi_arvalid ( MBUS_masters_axi_arvalid ), // input + .s_axi_arready ( MBUS_masters_axi_arready ), // output + .s_axi_rid ( MBUS_masters_axi_rid ), // output + .s_axi_rdata ( MBUS_masters_axi_rdata ), // output + .s_axi_rresp ( MBUS_masters_axi_rresp ), // output + .s_axi_rlast ( MBUS_masters_axi_rlast ), // output + .s_axi_rvalid ( MBUS_masters_axi_rvalid ), // output + .s_axi_rready ( MBUS_masters_axi_rready ), // input + .m_axi_awid ( MBUS_slaves_axi_awid ), // output + .m_axi_awaddr ( MBUS_slaves_axi_awaddr ), // output + .m_axi_awlen ( MBUS_slaves_axi_awlen ), // output + .m_axi_awsize ( MBUS_slaves_axi_awsize ), // output + .m_axi_awburst ( MBUS_slaves_axi_awburst ), // output + .m_axi_awlock ( MBUS_slaves_axi_awlock ), // output + .m_axi_awcache ( MBUS_slaves_axi_awcache ), // output + .m_axi_awprot ( MBUS_slaves_axi_awprot ), // output + .m_axi_awregion ( MBUS_slaves_axi_awregion ), // output + .m_axi_awqos ( MBUS_slaves_axi_awqos ), // output + .m_axi_awvalid ( MBUS_slaves_axi_awvalid ), // output + .m_axi_awready ( MBUS_slaves_axi_awready ), // input + .m_axi_wdata ( MBUS_slaves_axi_wdata ), // output + .m_axi_wstrb ( MBUS_slaves_axi_wstrb ), // output + .m_axi_wlast ( MBUS_slaves_axi_wlast ), // output + .m_axi_wvalid ( MBUS_slaves_axi_wvalid ), // output + .m_axi_wready ( MBUS_slaves_axi_wready ), // input + .m_axi_bid ( MBUS_slaves_axi_bid ), // input + .m_axi_bresp ( MBUS_slaves_axi_bresp ), // input + .m_axi_bvalid ( MBUS_slaves_axi_bvalid ), // input + .m_axi_bready ( MBUS_slaves_axi_bready ), // output + .m_axi_arid ( MBUS_slaves_axi_arid ), // output + .m_axi_araddr ( MBUS_slaves_axi_araddr ), // output + .m_axi_arlen ( MBUS_slaves_axi_arlen ), // output + .m_axi_arsize ( MBUS_slaves_axi_arsize ), // output + .m_axi_arburst ( MBUS_slaves_axi_arburst ), // output + .m_axi_arlock ( MBUS_slaves_axi_arlock ), // output + .m_axi_arcache ( MBUS_slaves_axi_arcache ), // output + .m_axi_arprot ( MBUS_slaves_axi_arprot ), // output + .m_axi_arregion ( MBUS_slaves_axi_arregion ), // output + .m_axi_arqos ( MBUS_slaves_axi_arqos ), // output + .m_axi_arvalid ( MBUS_slaves_axi_arvalid ), // output + .m_axi_arready ( MBUS_slaves_axi_arready ), // input + .m_axi_rid ( MBUS_slaves_axi_rid ), // input + .m_axi_rdata ( MBUS_slaves_axi_rdata ), // input + .m_axi_rresp ( MBUS_slaves_axi_rresp ), // input + .m_axi_rlast ( MBUS_slaves_axi_rlast ), // input + .m_axi_rvalid ( MBUS_slaves_axi_rvalid ), // input + .m_axi_rready ( MBUS_slaves_axi_rready ) // output + ); + + ///////////////// + // AXI masters // + ///////////////// + + sys_master # ( + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ) + ) sys_master_u ( + + // EMBEDDED ONLY + .sys_clock_i(sys_clock_i), + .sys_reset_i(sys_reset_i), + + // HPC ONLY + .pcie_refclk_p_i(pcie_refclk_p_i), + .pcie_refclk_n_i(pcie_refclk_n_i), + .pcie_resetn_i(pcie_resetn_i), + // PCI interface + .pci_exp_rxn_i(pci_exp_rxn_i), + .pci_exp_rxp_i(pci_exp_rxp_i), + .pci_exp_txn_o(pci_exp_txn_o), + .pci_exp_txp_o(pci_exp_txp_o), + + // Output clocks + .clk_10MHz_o(clk_10MHz), + .clk_20MHz_o(clk_20MHz), + .clk_50MHz_o(clk_50MHz), + .clk_100MHz_o(clk_100MHz), + .clk_250MHz_o(clk_250MHz), // HPC ONLY + + // Output resets + .rstn_10MHz_o(rstn_10MHz), + .rstn_20MHz_o(rstn_20MHz), + .rstn_50MHz_o(rstn_50MHz), + .rstn_100MHz_o(rstn_100MHz), + .rstn_250MHz_o(rstn_250MHz), // HPC ONLY + + // AXI Master + .m_axi_awid ( SYS_MASTER_to_MBUS_axi_awid ), + .m_axi_awaddr ( SYS_MASTER_to_MBUS_axi_awaddr ), + .m_axi_awlen ( SYS_MASTER_to_MBUS_axi_awlen ), + .m_axi_awsize ( SYS_MASTER_to_MBUS_axi_awsize ), + .m_axi_awburst ( SYS_MASTER_to_MBUS_axi_awburst ), + .m_axi_awlock ( SYS_MASTER_to_MBUS_axi_awlock ), + .m_axi_awcache ( SYS_MASTER_to_MBUS_axi_awcache ), + .m_axi_awprot ( SYS_MASTER_to_MBUS_axi_awprot ), + .m_axi_awqos ( SYS_MASTER_to_MBUS_axi_awqos ), + .m_axi_awvalid ( SYS_MASTER_to_MBUS_axi_awvalid ), + .m_axi_awready ( SYS_MASTER_to_MBUS_axi_awready ), + .m_axi_awregion ( SYS_MASTER_to_MBUS_axi_awregion ), + .m_axi_wdata ( SYS_MASTER_to_MBUS_axi_wdata ), + .m_axi_wstrb ( SYS_MASTER_to_MBUS_axi_wstrb ), + .m_axi_wlast ( SYS_MASTER_to_MBUS_axi_wlast ), + .m_axi_wvalid ( SYS_MASTER_to_MBUS_axi_wvalid ), + .m_axi_wready ( SYS_MASTER_to_MBUS_axi_wready ), + .m_axi_bid ( SYS_MASTER_to_MBUS_axi_bid ), + .m_axi_bresp ( SYS_MASTER_to_MBUS_axi_bresp ), + .m_axi_bvalid ( SYS_MASTER_to_MBUS_axi_bvalid ), + .m_axi_bready ( SYS_MASTER_to_MBUS_axi_bready ), + .m_axi_arid ( SYS_MASTER_to_MBUS_axi_arid ), + .m_axi_araddr ( SYS_MASTER_to_MBUS_axi_araddr ), + .m_axi_arlen ( SYS_MASTER_to_MBUS_axi_arlen ), + .m_axi_arsize ( SYS_MASTER_to_MBUS_axi_arsize ), + .m_axi_arburst ( SYS_MASTER_to_MBUS_axi_arburst ), + .m_axi_arlock ( SYS_MASTER_to_MBUS_axi_arlock ), + .m_axi_arcache ( SYS_MASTER_to_MBUS_axi_arcache ), + .m_axi_arprot ( SYS_MASTER_to_MBUS_axi_arprot ), + .m_axi_arqos ( SYS_MASTER_to_MBUS_axi_arqos ), + .m_axi_arvalid ( SYS_MASTER_to_MBUS_axi_arvalid ), + .m_axi_arready ( SYS_MASTER_to_MBUS_axi_arready ), + .m_axi_arregion ( SYS_MASTER_to_MBUS_axi_arregion ), + .m_axi_rid ( SYS_MASTER_to_MBUS_axi_rid ), + .m_axi_rdata ( SYS_MASTER_to_MBUS_axi_rdata ), + .m_axi_rresp ( SYS_MASTER_to_MBUS_axi_rresp ), + .m_axi_rlast ( SYS_MASTER_to_MBUS_axi_rlast ), + .m_axi_rvalid ( SYS_MASTER_to_MBUS_axi_rvalid ), + .m_axi_rready ( SYS_MASTER_to_MBUS_axi_rready ) + ); + + // RV Socket + rv_socket # ( + + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ), + .CORE_SELECTOR ( CORE_SELECTOR ) + + ) rv_socket_u ( + .clk_i ( main_clk ), + .rst_ni ( main_rstn ), + .core_resetn_i ( vio_resetn ), + .bootaddr_i ( '0 ), + .irq_i ( rv_socket_interrupt_line ), + + // Instruction AXI Port + .rv_socket_instr_axi_awid ( RV_SOCKET_INSTR_to_MBUS_axi_awid ), + .rv_socket_instr_axi_awaddr ( RV_SOCKET_INSTR_to_MBUS_axi_awaddr ), + .rv_socket_instr_axi_awlen ( RV_SOCKET_INSTR_to_MBUS_axi_awlen ), + .rv_socket_instr_axi_awsize ( RV_SOCKET_INSTR_to_MBUS_axi_awsize ), + .rv_socket_instr_axi_awburst ( RV_SOCKET_INSTR_to_MBUS_axi_awburst ), + .rv_socket_instr_axi_awlock ( RV_SOCKET_INSTR_to_MBUS_axi_awlock ), + .rv_socket_instr_axi_awcache ( RV_SOCKET_INSTR_to_MBUS_axi_awcache ), + .rv_socket_instr_axi_awprot ( RV_SOCKET_INSTR_to_MBUS_axi_awprot ), + .rv_socket_instr_axi_awqos ( RV_SOCKET_INSTR_to_MBUS_axi_awqos ), + .rv_socket_instr_axi_awvalid ( RV_SOCKET_INSTR_to_MBUS_axi_awvalid ), + .rv_socket_instr_axi_awready ( RV_SOCKET_INSTR_to_MBUS_axi_awready ), + .rv_socket_instr_axi_awregion ( RV_SOCKET_INSTR_to_MBUS_axi_awregion ), + .rv_socket_instr_axi_wdata ( RV_SOCKET_INSTR_to_MBUS_axi_wdata ), + .rv_socket_instr_axi_wstrb ( RV_SOCKET_INSTR_to_MBUS_axi_wstrb ), + .rv_socket_instr_axi_wlast ( RV_SOCKET_INSTR_to_MBUS_axi_wlast ), + .rv_socket_instr_axi_wvalid ( RV_SOCKET_INSTR_to_MBUS_axi_wvalid ), + .rv_socket_instr_axi_wready ( RV_SOCKET_INSTR_to_MBUS_axi_wready ), + .rv_socket_instr_axi_bid ( RV_SOCKET_INSTR_to_MBUS_axi_bid ), + .rv_socket_instr_axi_bresp ( RV_SOCKET_INSTR_to_MBUS_axi_bresp ), + .rv_socket_instr_axi_bvalid ( RV_SOCKET_INSTR_to_MBUS_axi_bvalid ), + .rv_socket_instr_axi_bready ( RV_SOCKET_INSTR_to_MBUS_axi_bready ), + .rv_socket_instr_axi_arid ( RV_SOCKET_INSTR_to_MBUS_axi_arid ), + .rv_socket_instr_axi_araddr ( RV_SOCKET_INSTR_to_MBUS_axi_araddr ), + .rv_socket_instr_axi_arlen ( RV_SOCKET_INSTR_to_MBUS_axi_arlen ), + .rv_socket_instr_axi_arsize ( RV_SOCKET_INSTR_to_MBUS_axi_arsize ), + .rv_socket_instr_axi_arburst ( RV_SOCKET_INSTR_to_MBUS_axi_arburst ), + .rv_socket_instr_axi_arlock ( RV_SOCKET_INSTR_to_MBUS_axi_arlock ), + .rv_socket_instr_axi_arcache ( RV_SOCKET_INSTR_to_MBUS_axi_arcache ), + .rv_socket_instr_axi_arprot ( RV_SOCKET_INSTR_to_MBUS_axi_arprot ), + .rv_socket_instr_axi_arqos ( RV_SOCKET_INSTR_to_MBUS_axi_arqos ), + .rv_socket_instr_axi_arvalid ( RV_SOCKET_INSTR_to_MBUS_axi_arvalid ), + .rv_socket_instr_axi_arready ( RV_SOCKET_INSTR_to_MBUS_axi_arready ), + .rv_socket_instr_axi_arregion ( RV_SOCKET_INSTR_to_MBUS_axi_arregion ), + .rv_socket_instr_axi_rid ( RV_SOCKET_INSTR_to_MBUS_axi_rid ), + .rv_socket_instr_axi_rdata ( RV_SOCKET_INSTR_to_MBUS_axi_rdata ), + .rv_socket_instr_axi_rresp ( RV_SOCKET_INSTR_to_MBUS_axi_rresp ), + .rv_socket_instr_axi_rlast ( RV_SOCKET_INSTR_to_MBUS_axi_rlast ), + .rv_socket_instr_axi_rvalid ( RV_SOCKET_INSTR_to_MBUS_axi_rvalid ), + .rv_socket_instr_axi_rready ( RV_SOCKET_INSTR_to_MBUS_axi_rready ), + + // Instruction AXI Port - CORE 1 + .rv_socket_instr1_axi_awid ( RV_SOCKET_INSTR1_to_MBUS_axi_awid ), + .rv_socket_instr1_axi_awaddr ( RV_SOCKET_INSTR1_to_MBUS_axi_awaddr ), + .rv_socket_instr1_axi_awlen ( RV_SOCKET_INSTR1_to_MBUS_axi_awlen ), + .rv_socket_instr1_axi_awsize ( RV_SOCKET_INSTR1_to_MBUS_axi_awsize ), + .rv_socket_instr1_axi_awburst ( RV_SOCKET_INSTR1_to_MBUS_axi_awburst ), + .rv_socket_instr1_axi_awlock ( RV_SOCKET_INSTR1_to_MBUS_axi_awlock ), + .rv_socket_instr1_axi_awcache ( RV_SOCKET_INSTR1_to_MBUS_axi_awcache ), + .rv_socket_instr1_axi_awprot ( RV_SOCKET_INSTR1_to_MBUS_axi_awprot ), + .rv_socket_instr1_axi_awqos ( RV_SOCKET_INSTR1_to_MBUS_axi_awqos ), + .rv_socket_instr1_axi_awvalid ( RV_SOCKET_INSTR1_to_MBUS_axi_awvalid ), + .rv_socket_instr1_axi_awready ( RV_SOCKET_INSTR1_to_MBUS_axi_awready ), + .rv_socket_instr1_axi_awregion ( RV_SOCKET_INSTR1_to_MBUS_axi_awregion ), + .rv_socket_instr1_axi_wdata ( RV_SOCKET_INSTR1_to_MBUS_axi_wdata ), + .rv_socket_instr1_axi_wstrb ( RV_SOCKET_INSTR1_to_MBUS_axi_wstrb ), + .rv_socket_instr1_axi_wlast ( RV_SOCKET_INSTR1_to_MBUS_axi_wlast ), + .rv_socket_instr1_axi_wvalid ( RV_SOCKET_INSTR1_to_MBUS_axi_wvalid ), + .rv_socket_instr1_axi_wready ( RV_SOCKET_INSTR1_to_MBUS_axi_wready ), + .rv_socket_instr1_axi_bid ( RV_SOCKET_INSTR1_to_MBUS_axi_bid ), + .rv_socket_instr1_axi_bresp ( RV_SOCKET_INSTR1_to_MBUS_axi_bresp ), + .rv_socket_instr1_axi_bvalid ( RV_SOCKET_INSTR1_to_MBUS_axi_bvalid ), + .rv_socket_instr1_axi_bready ( RV_SOCKET_INSTR1_to_MBUS_axi_bready ), + .rv_socket_instr1_axi_arid ( RV_SOCKET_INSTR1_to_MBUS_axi_arid ), + .rv_socket_instr1_axi_araddr ( RV_SOCKET_INSTR1_to_MBUS_axi_araddr ), + .rv_socket_instr1_axi_arlen ( RV_SOCKET_INSTR1_to_MBUS_axi_arlen ), + .rv_socket_instr1_axi_arsize ( RV_SOCKET_INSTR1_to_MBUS_axi_arsize ), + .rv_socket_instr1_axi_arburst ( RV_SOCKET_INSTR1_to_MBUS_axi_arburst ), + .rv_socket_instr1_axi_arlock ( RV_SOCKET_INSTR1_to_MBUS_axi_arlock ), + .rv_socket_instr1_axi_arcache ( RV_SOCKET_INSTR1_to_MBUS_axi_arcache ), + .rv_socket_instr1_axi_arprot ( RV_SOCKET_INSTR1_to_MBUS_axi_arprot ), + .rv_socket_instr1_axi_arqos ( RV_SOCKET_INSTR1_to_MBUS_axi_arqos ), + .rv_socket_instr1_axi_arvalid ( RV_SOCKET_INSTR1_to_MBUS_axi_arvalid ), + .rv_socket_instr1_axi_arready ( RV_SOCKET_INSTR1_to_MBUS_axi_arready ), + .rv_socket_instr1_axi_arregion ( RV_SOCKET_INSTR1_to_MBUS_axi_arregion ), + .rv_socket_instr1_axi_rid ( RV_SOCKET_INSTR1_to_MBUS_axi_rid ), + .rv_socket_instr1_axi_rdata ( RV_SOCKET_INSTR1_to_MBUS_axi_rdata ), + .rv_socket_instr1_axi_rresp ( RV_SOCKET_INSTR1_to_MBUS_axi_rresp ), + .rv_socket_instr1_axi_rlast ( RV_SOCKET_INSTR1_to_MBUS_axi_rlast ), + .rv_socket_instr1_axi_rvalid ( RV_SOCKET_INSTR1_to_MBUS_axi_rvalid ), + .rv_socket_instr1_axi_rready ( RV_SOCKET_INSTR1_to_MBUS_axi_rready ), + + // Data AXI Port + .rv_socket_data_axi_awid ( RV_SOCKET_DATA_to_MBUS_axi_awid ), + .rv_socket_data_axi_awaddr ( RV_SOCKET_DATA_to_MBUS_axi_awaddr ), + .rv_socket_data_axi_awlen ( RV_SOCKET_DATA_to_MBUS_axi_awlen ), + .rv_socket_data_axi_awsize ( RV_SOCKET_DATA_to_MBUS_axi_awsize ), + .rv_socket_data_axi_awburst ( RV_SOCKET_DATA_to_MBUS_axi_awburst ), + .rv_socket_data_axi_awlock ( RV_SOCKET_DATA_to_MBUS_axi_awlock ), + .rv_socket_data_axi_awcache ( RV_SOCKET_DATA_to_MBUS_axi_awcache ), + .rv_socket_data_axi_awprot ( RV_SOCKET_DATA_to_MBUS_axi_awprot ), + .rv_socket_data_axi_awqos ( RV_SOCKET_DATA_to_MBUS_axi_awqos ), + .rv_socket_data_axi_awvalid ( RV_SOCKET_DATA_to_MBUS_axi_awvalid ), + .rv_socket_data_axi_awready ( RV_SOCKET_DATA_to_MBUS_axi_awready ), + .rv_socket_data_axi_awregion ( RV_SOCKET_DATA_to_MBUS_axi_awregion ), + .rv_socket_data_axi_wdata ( RV_SOCKET_DATA_to_MBUS_axi_wdata ), + .rv_socket_data_axi_wstrb ( RV_SOCKET_DATA_to_MBUS_axi_wstrb ), + .rv_socket_data_axi_wlast ( RV_SOCKET_DATA_to_MBUS_axi_wlast ), + .rv_socket_data_axi_wvalid ( RV_SOCKET_DATA_to_MBUS_axi_wvalid ), + .rv_socket_data_axi_wready ( RV_SOCKET_DATA_to_MBUS_axi_wready ), + .rv_socket_data_axi_bid ( RV_SOCKET_DATA_to_MBUS_axi_bid ), + .rv_socket_data_axi_bresp ( RV_SOCKET_DATA_to_MBUS_axi_bresp ), + .rv_socket_data_axi_bvalid ( RV_SOCKET_DATA_to_MBUS_axi_bvalid ), + .rv_socket_data_axi_bready ( RV_SOCKET_DATA_to_MBUS_axi_bready ), + .rv_socket_data_axi_arid ( RV_SOCKET_DATA_to_MBUS_axi_arid ), + .rv_socket_data_axi_araddr ( RV_SOCKET_DATA_to_MBUS_axi_araddr ), + .rv_socket_data_axi_arlen ( RV_SOCKET_DATA_to_MBUS_axi_arlen ), + .rv_socket_data_axi_arsize ( RV_SOCKET_DATA_to_MBUS_axi_arsize ), + .rv_socket_data_axi_arburst ( RV_SOCKET_DATA_to_MBUS_axi_arburst ), + .rv_socket_data_axi_arlock ( RV_SOCKET_DATA_to_MBUS_axi_arlock ), + .rv_socket_data_axi_arcache ( RV_SOCKET_DATA_to_MBUS_axi_arcache ), + .rv_socket_data_axi_arprot ( RV_SOCKET_DATA_to_MBUS_axi_arprot ), + .rv_socket_data_axi_arqos ( RV_SOCKET_DATA_to_MBUS_axi_arqos ), + .rv_socket_data_axi_arvalid ( RV_SOCKET_DATA_to_MBUS_axi_arvalid ), + .rv_socket_data_axi_arready ( RV_SOCKET_DATA_to_MBUS_axi_arready ), + .rv_socket_data_axi_arregion ( RV_SOCKET_DATA_to_MBUS_axi_arregion ), + .rv_socket_data_axi_rid ( RV_SOCKET_DATA_to_MBUS_axi_rid ), + .rv_socket_data_axi_rdata ( RV_SOCKET_DATA_to_MBUS_axi_rdata ), + .rv_socket_data_axi_rresp ( RV_SOCKET_DATA_to_MBUS_axi_rresp ), + .rv_socket_data_axi_rlast ( RV_SOCKET_DATA_to_MBUS_axi_rlast ), + .rv_socket_data_axi_rvalid ( RV_SOCKET_DATA_to_MBUS_axi_rvalid ), + .rv_socket_data_axi_rready ( RV_SOCKET_DATA_to_MBUS_axi_rready ), + + // Data AXI Port - CORE 1 + .rv_socket_data1_axi_awid ( RV_SOCKET_DATA1_to_MBUS_axi_awid ), + .rv_socket_data1_axi_awaddr ( RV_SOCKET_DATA1_to_MBUS_axi_awaddr ), + .rv_socket_data1_axi_awlen ( RV_SOCKET_DATA1_to_MBUS_axi_awlen ), + .rv_socket_data1_axi_awsize ( RV_SOCKET_DATA1_to_MBUS_axi_awsize ), + .rv_socket_data1_axi_awburst ( RV_SOCKET_DATA1_to_MBUS_axi_awburst ), + .rv_socket_data1_axi_awlock ( RV_SOCKET_DATA1_to_MBUS_axi_awlock ), + .rv_socket_data1_axi_awcache ( RV_SOCKET_DATA1_to_MBUS_axi_awcache ), + .rv_socket_data1_axi_awprot ( RV_SOCKET_DATA1_to_MBUS_axi_awprot ), + .rv_socket_data1_axi_awqos ( RV_SOCKET_DATA1_to_MBUS_axi_awqos ), + .rv_socket_data1_axi_awvalid ( RV_SOCKET_DATA1_to_MBUS_axi_awvalid ), + .rv_socket_data1_axi_awready ( RV_SOCKET_DATA1_to_MBUS_axi_awready ), + .rv_socket_data1_axi_awregion ( RV_SOCKET_DATA1_to_MBUS_axi_awregion ), + .rv_socket_data1_axi_wdata ( RV_SOCKET_DATA1_to_MBUS_axi_wdata ), + .rv_socket_data1_axi_wstrb ( RV_SOCKET_DATA1_to_MBUS_axi_wstrb ), + .rv_socket_data1_axi_wlast ( RV_SOCKET_DATA1_to_MBUS_axi_wlast ), + .rv_socket_data1_axi_wvalid ( RV_SOCKET_DATA1_to_MBUS_axi_wvalid ), + .rv_socket_data1_axi_wready ( RV_SOCKET_DATA1_to_MBUS_axi_wready ), + .rv_socket_data1_axi_bid ( RV_SOCKET_DATA1_to_MBUS_axi_bid ), + .rv_socket_data1_axi_bresp ( RV_SOCKET_DATA1_to_MBUS_axi_bresp ), + .rv_socket_data1_axi_bvalid ( RV_SOCKET_DATA1_to_MBUS_axi_bvalid ), + .rv_socket_data1_axi_bready ( RV_SOCKET_DATA1_to_MBUS_axi_bready ), + .rv_socket_data1_axi_arid ( RV_SOCKET_DATA1_to_MBUS_axi_arid ), + .rv_socket_data1_axi_araddr ( RV_SOCKET_DATA1_to_MBUS_axi_araddr ), + .rv_socket_data1_axi_arlen ( RV_SOCKET_DATA1_to_MBUS_axi_arlen ), + .rv_socket_data1_axi_arsize ( RV_SOCKET_DATA1_to_MBUS_axi_arsize ), + .rv_socket_data1_axi_arburst ( RV_SOCKET_DATA1_to_MBUS_axi_arburst ), + .rv_socket_data1_axi_arlock ( RV_SOCKET_DATA1_to_MBUS_axi_arlock ), + .rv_socket_data1_axi_arcache ( RV_SOCKET_DATA1_to_MBUS_axi_arcache ), + .rv_socket_data1_axi_arprot ( RV_SOCKET_DATA1_to_MBUS_axi_arprot ), + .rv_socket_data1_axi_arqos ( RV_SOCKET_DATA1_to_MBUS_axi_arqos ), + .rv_socket_data1_axi_arvalid ( RV_SOCKET_DATA1_to_MBUS_axi_arvalid ), + .rv_socket_data1_axi_arready ( RV_SOCKET_DATA1_to_MBUS_axi_arready ), + .rv_socket_data1_axi_arregion ( RV_SOCKET_DATA1_to_MBUS_axi_arregion ), + .rv_socket_data1_axi_rid ( RV_SOCKET_DATA1_to_MBUS_axi_rid ), + .rv_socket_data1_axi_rdata ( RV_SOCKET_DATA1_to_MBUS_axi_rdata ), + .rv_socket_data1_axi_rresp ( RV_SOCKET_DATA1_to_MBUS_axi_rresp ), + .rv_socket_data1_axi_rlast ( RV_SOCKET_DATA1_to_MBUS_axi_rlast ), + .rv_socket_data1_axi_rvalid ( RV_SOCKET_DATA1_to_MBUS_axi_rvalid ), + .rv_socket_data1_axi_rready ( RV_SOCKET_DATA1_to_MBUS_axi_rready ), + + + // Debug AXI master + .rv_socket_dbg_master_axi_awid ( DBG_MASTER_to_MBUS_axi_awid ), + .rv_socket_dbg_master_axi_awaddr ( DBG_MASTER_to_MBUS_axi_awaddr ), + .rv_socket_dbg_master_axi_awlen ( DBG_MASTER_to_MBUS_axi_awlen ), + .rv_socket_dbg_master_axi_awsize ( DBG_MASTER_to_MBUS_axi_awsize ), + .rv_socket_dbg_master_axi_awburst ( DBG_MASTER_to_MBUS_axi_awburst ), + .rv_socket_dbg_master_axi_awlock ( DBG_MASTER_to_MBUS_axi_awlock ), + .rv_socket_dbg_master_axi_awcache ( DBG_MASTER_to_MBUS_axi_awcache ), + .rv_socket_dbg_master_axi_awprot ( DBG_MASTER_to_MBUS_axi_awprot ), + .rv_socket_dbg_master_axi_awqos ( DBG_MASTER_to_MBUS_axi_awqos ), + .rv_socket_dbg_master_axi_awvalid ( DBG_MASTER_to_MBUS_axi_awvalid ), + .rv_socket_dbg_master_axi_awready ( DBG_MASTER_to_MBUS_axi_awready ), + .rv_socket_dbg_master_axi_awregion ( DBG_MASTER_to_MBUS_axi_awregion ), + .rv_socket_dbg_master_axi_wdata ( DBG_MASTER_to_MBUS_axi_wdata ), + .rv_socket_dbg_master_axi_wstrb ( DBG_MASTER_to_MBUS_axi_wstrb ), + .rv_socket_dbg_master_axi_wlast ( DBG_MASTER_to_MBUS_axi_wlast ), + .rv_socket_dbg_master_axi_wvalid ( DBG_MASTER_to_MBUS_axi_wvalid ), + .rv_socket_dbg_master_axi_wready ( DBG_MASTER_to_MBUS_axi_wready ), + .rv_socket_dbg_master_axi_bid ( DBG_MASTER_to_MBUS_axi_bid ), + .rv_socket_dbg_master_axi_bresp ( DBG_MASTER_to_MBUS_axi_bresp ), + .rv_socket_dbg_master_axi_bvalid ( DBG_MASTER_to_MBUS_axi_bvalid ), + .rv_socket_dbg_master_axi_bready ( DBG_MASTER_to_MBUS_axi_bready ), + .rv_socket_dbg_master_axi_arid ( DBG_MASTER_to_MBUS_axi_arid ), + .rv_socket_dbg_master_axi_araddr ( DBG_MASTER_to_MBUS_axi_araddr ), + .rv_socket_dbg_master_axi_arlen ( DBG_MASTER_to_MBUS_axi_arlen ), + .rv_socket_dbg_master_axi_arsize ( DBG_MASTER_to_MBUS_axi_arsize ), + .rv_socket_dbg_master_axi_arburst ( DBG_MASTER_to_MBUS_axi_arburst ), + .rv_socket_dbg_master_axi_arlock ( DBG_MASTER_to_MBUS_axi_arlock ), + .rv_socket_dbg_master_axi_arcache ( DBG_MASTER_to_MBUS_axi_arcache ), + .rv_socket_dbg_master_axi_arprot ( DBG_MASTER_to_MBUS_axi_arprot ), + .rv_socket_dbg_master_axi_arqos ( DBG_MASTER_to_MBUS_axi_arqos ), + .rv_socket_dbg_master_axi_arvalid ( DBG_MASTER_to_MBUS_axi_arvalid ), + .rv_socket_dbg_master_axi_arready ( DBG_MASTER_to_MBUS_axi_arready ), + .rv_socket_dbg_master_axi_arregion ( DBG_MASTER_to_MBUS_axi_arregion ), + .rv_socket_dbg_master_axi_rid ( DBG_MASTER_to_MBUS_axi_rid ), + .rv_socket_dbg_master_axi_rdata ( DBG_MASTER_to_MBUS_axi_rdata ), + .rv_socket_dbg_master_axi_rresp ( DBG_MASTER_to_MBUS_axi_rresp ), + .rv_socket_dbg_master_axi_rlast ( DBG_MASTER_to_MBUS_axi_rlast ), + .rv_socket_dbg_master_axi_rvalid ( DBG_MASTER_to_MBUS_axi_rvalid ), + .rv_socket_dbg_master_axi_rready ( DBG_MASTER_to_MBUS_axi_rready ), + + // Debug AXI slave + .rv_socket_dbg_slave_axi_awid ( MBUS_to_DM_mem_axi_awid ), + .rv_socket_dbg_slave_axi_awaddr ( MBUS_to_DM_mem_axi_awaddr ), + .rv_socket_dbg_slave_axi_awlen ( MBUS_to_DM_mem_axi_awlen ), + .rv_socket_dbg_slave_axi_awsize ( MBUS_to_DM_mem_axi_awsize ), + .rv_socket_dbg_slave_axi_awburst ( MBUS_to_DM_mem_axi_awburst ), + .rv_socket_dbg_slave_axi_awlock ( MBUS_to_DM_mem_axi_awlock ), + .rv_socket_dbg_slave_axi_awcache ( MBUS_to_DM_mem_axi_awcache ), + .rv_socket_dbg_slave_axi_awprot ( MBUS_to_DM_mem_axi_awprot ), + .rv_socket_dbg_slave_axi_awqos ( MBUS_to_DM_mem_axi_awqos ), + .rv_socket_dbg_slave_axi_awvalid ( MBUS_to_DM_mem_axi_awvalid ), + .rv_socket_dbg_slave_axi_awready ( MBUS_to_DM_mem_axi_awready ), + .rv_socket_dbg_slave_axi_awregion ( MBUS_to_DM_mem_axi_awregion ), + .rv_socket_dbg_slave_axi_wdata ( MBUS_to_DM_mem_axi_wdata ), + .rv_socket_dbg_slave_axi_wstrb ( MBUS_to_DM_mem_axi_wstrb ), + .rv_socket_dbg_slave_axi_wlast ( MBUS_to_DM_mem_axi_wlast ), + .rv_socket_dbg_slave_axi_wvalid ( MBUS_to_DM_mem_axi_wvalid ), + .rv_socket_dbg_slave_axi_wready ( MBUS_to_DM_mem_axi_wready ), + .rv_socket_dbg_slave_axi_bid ( MBUS_to_DM_mem_axi_bid ), + .rv_socket_dbg_slave_axi_bresp ( MBUS_to_DM_mem_axi_bresp ), + .rv_socket_dbg_slave_axi_bvalid ( MBUS_to_DM_mem_axi_bvalid ), + .rv_socket_dbg_slave_axi_bready ( MBUS_to_DM_mem_axi_bready ), + .rv_socket_dbg_slave_axi_arid ( MBUS_to_DM_mem_axi_arid ), + .rv_socket_dbg_slave_axi_araddr ( MBUS_to_DM_mem_axi_araddr ), + .rv_socket_dbg_slave_axi_arlen ( MBUS_to_DM_mem_axi_arlen ), + .rv_socket_dbg_slave_axi_arsize ( MBUS_to_DM_mem_axi_arsize ), + .rv_socket_dbg_slave_axi_arburst ( MBUS_to_DM_mem_axi_arburst ), + .rv_socket_dbg_slave_axi_arlock ( MBUS_to_DM_mem_axi_arlock ), + .rv_socket_dbg_slave_axi_arcache ( MBUS_to_DM_mem_axi_arcache ), + .rv_socket_dbg_slave_axi_arprot ( MBUS_to_DM_mem_axi_arprot ), + .rv_socket_dbg_slave_axi_arqos ( MBUS_to_DM_mem_axi_arqos ), + .rv_socket_dbg_slave_axi_arvalid ( MBUS_to_DM_mem_axi_arvalid ), + .rv_socket_dbg_slave_axi_arready ( MBUS_to_DM_mem_axi_arready ), + .rv_socket_dbg_slave_axi_arregion ( MBUS_to_DM_mem_axi_arregion ), + .rv_socket_dbg_slave_axi_rid ( MBUS_to_DM_mem_axi_rid ), + .rv_socket_dbg_slave_axi_rdata ( MBUS_to_DM_mem_axi_rdata ), + .rv_socket_dbg_slave_axi_rresp ( MBUS_to_DM_mem_axi_rresp ), + .rv_socket_dbg_slave_axi_rlast ( MBUS_to_DM_mem_axi_rlast ), + .rv_socket_dbg_slave_axi_rvalid ( MBUS_to_DM_mem_axi_rvalid ), + .rv_socket_dbg_slave_axi_rready ( MBUS_to_DM_mem_axi_rready ) + ); + + //////////////// + // AXI slaves // + //////////////// + + // Main memory + xlnx_blk_mem_gen_0 bram_u ( + .rsta_busy ( /* open */ ), // output wire rsta_busy + .rstb_busy ( /* open */ ), // output wire rstb_busy + .s_aclk ( BRAM_clk ), // input wire s_aclk + .s_aresetn ( BRAM_rstn ), // input wire s_aresetn + .s_axi_awid ( MBUS_to_BRAM_axi_awid ), // input wire [3 : 0] s_axi_awid + .s_axi_awaddr ( MBUS_to_BRAM_axi_awaddr ), // input wire [31 : 0] s_axi_awaddr + .s_axi_awlen ( MBUS_to_BRAM_axi_awlen ), // input wire [7 : 0] s_axi_awlen + .s_axi_awsize ( MBUS_to_BRAM_axi_awsize ), // input wire [2 : 0] s_axi_awsize + .s_axi_awburst ( MBUS_to_BRAM_axi_awburst ), // input wire [1 : 0] s_axi_awburst + .s_axi_awvalid ( MBUS_to_BRAM_axi_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( MBUS_to_BRAM_axi_awready ), // output wire s_axi_awready + .s_axi_wdata ( MBUS_to_BRAM_axi_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( MBUS_to_BRAM_axi_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wlast ( MBUS_to_BRAM_axi_wlast ), // input wire s_axi_wlast + .s_axi_wvalid ( MBUS_to_BRAM_axi_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( MBUS_to_BRAM_axi_wready ), // output wire s_axi_wready + .s_axi_bid ( MBUS_to_BRAM_axi_bid ), // output wire [3 : 0] s_axi_bid + .s_axi_bresp ( MBUS_to_BRAM_axi_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( MBUS_to_BRAM_axi_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( MBUS_to_BRAM_axi_bready ), // input wire s_axi_bready + .s_axi_arid ( MBUS_to_BRAM_axi_arid ), // input wire [3 : 0] s_axi_arid + .s_axi_araddr ( MBUS_to_BRAM_axi_araddr ), // input wire [31 : 0] s_axi_araddr + .s_axi_arlen ( MBUS_to_BRAM_axi_arlen ), // input wire [7 : 0] s_axi_arlen + .s_axi_arsize ( MBUS_to_BRAM_axi_arsize ), // input wire [2 : 0] s_axi_arsize + .s_axi_arburst ( MBUS_to_BRAM_axi_arburst ), // input wire [1 : 0] s_axi_arburst + .s_axi_arvalid ( MBUS_to_BRAM_axi_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( MBUS_to_BRAM_axi_arready ), // output wire s_axi_arready + .s_axi_rid ( MBUS_to_BRAM_axi_rid ), // output wire [3 : 0] s_axi_rid + .s_axi_rdata ( MBUS_to_BRAM_axi_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( MBUS_to_BRAM_axi_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rlast ( MBUS_to_BRAM_axi_rlast ), // output wire s_axi_rlast + .s_axi_rvalid ( MBUS_to_BRAM_axi_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( MBUS_to_BRAM_axi_rready ) // input wire s_axi_rready + ); + + // Platform-Level Interrupt Controller (PLIC) + logic [31:0] plic_int_line; + logic plic_int_irq_o; + logic hls_interrupt_to_plic; + logic irq_cdma_to_plic; + + always_comb begin : system_interrupts + + // Default non-assigned lines + plic_int_line = '0; + rv_socket_interrupt_line = '0; + + // Mapping PLIC input interrupts (only from pbus at the moment) + // Mapping is static (refer to uninasoc_pkg.sv) + // TODO154: generate by config + plic_int_line[PLIC_RESERVED_INTERRUPT] = 1'b0; + plic_int_line[PLIC_GPIOIN_INTERRUPT] = pbus_int_line[PBUS_GPIOIN_INTERRUPT]; + plic_int_line[PLIC_TIM0_INTERRUPT] = pbus_int_line[PBUS_TIM0_INTERRUPT]; + plic_int_line[PLIC_TIM1_INTERRUPT] = pbus_int_line[PBUS_TIM1_INTERRUPT]; + plic_int_line[PLIC_UART_INTERRUPT] = pbus_int_line[PBUS_UART_INTERRUPT]; + plic_int_line[PLIC_HLS_INTERRUPT] = hls_interrupt_to_plic; + plic_int_line[PLIC_CDMA_INTERRUPT] = irq_cdma_to_plic; + // Map system-interrupts pins to socket interrupts + rv_socket_interrupt_line[CORE_EXT_INTERRUPT] = plic_int_irq_o; + + end : system_interrupts + + plic_wrapper #( + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ) + ) plic_wrapper_u ( + .clk_i ( main_clk ), // input wire s_axi_aclk + .rst_ni ( main_rstn ), // input wire s_axi_aresetn + // AXI4 slave port (from xbar) + .intr_src_i ( plic_int_line ), // Input interrupt lines (Sources) + .irq_o ( plic_int_irq_o ), // Output Interrupts (Targets -> Socket) + .s_axi_awid ( MBUS_to_PLIC_axi_awid ), // input wire [1 : 0] s_axi_awid + .s_axi_awaddr ( MBUS_to_PLIC_axi_awaddr ), // input wire [25 : 0] s_axi_awaddr + .s_axi_awlen ( MBUS_to_PLIC_axi_awlen ), // input wire [7 : 0] s_axi_awlen + .s_axi_awsize ( MBUS_to_PLIC_axi_awsize ), // input wire [2 : 0] s_axi_awsize + .s_axi_awburst ( MBUS_to_PLIC_axi_awburst ), // input wire [1 : 0] s_axi_awburst + .s_axi_awlock ( MBUS_to_PLIC_axi_awlock ), // input wire [0 : 0] s_axi_awlock + .s_axi_awcache ( MBUS_to_PLIC_axi_awcache ), // input wire [3 : 0] s_axi_awcache + .s_axi_awprot ( MBUS_to_PLIC_axi_awprot ), // input wire [2 : 0] s_axi_awprot + .s_axi_awregion ( MBUS_to_PLIC_axi_awregion ), // input wire [3 : 0] s_axi_awregion + .s_axi_awqos ( MBUS_to_PLIC_axi_awqos ), // input wire [3 : 0] s_axi_awqos + .s_axi_awvalid ( MBUS_to_PLIC_axi_awvalid ), // input wire s_axi_awvalid + .s_axi_awready ( MBUS_to_PLIC_axi_awready ), // output wire s_axi_awready + .s_axi_wdata ( MBUS_to_PLIC_axi_wdata ), // input wire [31 : 0] s_axi_wdata + .s_axi_wstrb ( MBUS_to_PLIC_axi_wstrb ), // input wire [3 : 0] s_axi_wstrb + .s_axi_wlast ( MBUS_to_PLIC_axi_wlast ), // input wire s_axi_wlast + .s_axi_wvalid ( MBUS_to_PLIC_axi_wvalid ), // input wire s_axi_wvalid + .s_axi_wready ( MBUS_to_PLIC_axi_wready ), // output wire s_axi_wready + .s_axi_bid ( MBUS_to_PLIC_axi_bid ), // output wire [1 : 0] s_axi_bid + .s_axi_bresp ( MBUS_to_PLIC_axi_bresp ), // output wire [1 : 0] s_axi_bresp + .s_axi_bvalid ( MBUS_to_PLIC_axi_bvalid ), // output wire s_axi_bvalid + .s_axi_bready ( MBUS_to_PLIC_axi_bready ), // input wire s_axi_bready + .s_axi_arid ( MBUS_to_PLIC_axi_arid ), // input wire [1 : 0] s_axi_arid + .s_axi_araddr ( MBUS_to_PLIC_axi_araddr ), // input wire [25 : 0] s_axi_araddr + .s_axi_arlen ( MBUS_to_PLIC_axi_arlen ), // input wire [7 : 0] s_axi_arlen + .s_axi_arsize ( MBUS_to_PLIC_axi_arsize ), // input wire [2 : 0] s_axi_arsize + .s_axi_arburst ( MBUS_to_PLIC_axi_arburst ), // input wire [1 : 0] s_axi_arburst + .s_axi_arlock ( MBUS_to_PLIC_axi_arlock ), // input wire [0 : 0] s_axi_arlock + .s_axi_arcache ( MBUS_to_PLIC_axi_arcache ), // input wire [3 : 0] s_axi_arcache + .s_axi_arprot ( MBUS_to_PLIC_axi_arprot ), // input wire [2 : 0] s_axi_arprot + .s_axi_arregion ( MBUS_to_PLIC_axi_arregion ), // input wire [3 : 0] s_axi_arregion + .s_axi_arqos ( MBUS_to_PLIC_axi_arqos ), // input wire [3 : 0] s_axi_arqos + .s_axi_arvalid ( MBUS_to_PLIC_axi_arvalid ), // input wire s_axi_arvalid + .s_axi_arready ( MBUS_to_PLIC_axi_arready ), // output wire s_axi_arready + .s_axi_rid ( MBUS_to_PLIC_axi_rid ), // output wire [1 : 0] s_axi_rid + .s_axi_rdata ( MBUS_to_PLIC_axi_rdata ), // output wire [31 : 0] s_axi_rdata + .s_axi_rresp ( MBUS_to_PLIC_axi_rresp ), // output wire [1 : 0] s_axi_rresp + .s_axi_rlast ( MBUS_to_PLIC_axi_rlast ), // output wire s_axi_rlast + .s_axi_rvalid ( MBUS_to_PLIC_axi_rvalid ), // output wire s_axi_rvalid + .s_axi_rready ( MBUS_to_PLIC_axi_rready ) + ); + + //////////////////// + // PERIPHERAL BUS // + //////////////////// + + peripheral_bus # ( + + .LOCAL_DATA_WIDTH ( PBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( PBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( PBUS_ID_WIDTH ) + + ) peripheral_bus_u ( + + .main_clock_i ( main_clk ), + .main_reset_ni ( main_rstn ), + .PBUS_clock_i ( PBUS_clk ), + .PBUS_reset_ni ( PBUS_rstn ), + + // EMBEDDED ONLY + .uart_rx_i ( uart_rx_i ), + .uart_tx_o ( uart_tx_o ), + .gpio_out_o ( gpio_out_o ), + .gpio_in_i ( gpio_in_i ), + + .int_o ( pbus_int_line ), + + .s_axi_awid ( MBUS_to_PBUS_axi_awid ), + .s_axi_awaddr ( MBUS_to_PBUS_axi_awaddr ), + .s_axi_awlen ( MBUS_to_PBUS_axi_awlen ), + .s_axi_awsize ( MBUS_to_PBUS_axi_awsize ), + .s_axi_awburst ( MBUS_to_PBUS_axi_awburst ), + .s_axi_awlock ( MBUS_to_PBUS_axi_awlock ), + .s_axi_awcache ( MBUS_to_PBUS_axi_awcache ), + .s_axi_awprot ( MBUS_to_PBUS_axi_awprot ), + .s_axi_awregion ( MBUS_to_PBUS_axi_awregion ), + .s_axi_awqos ( MBUS_to_PBUS_axi_awqos ), + .s_axi_awvalid ( MBUS_to_PBUS_axi_awvalid ), + .s_axi_awready ( MBUS_to_PBUS_axi_awready ), + .s_axi_wdata ( MBUS_to_PBUS_axi_wdata ), + .s_axi_wstrb ( MBUS_to_PBUS_axi_wstrb ), + .s_axi_wlast ( MBUS_to_PBUS_axi_wlast ), + .s_axi_wvalid ( MBUS_to_PBUS_axi_wvalid ), + .s_axi_wready ( MBUS_to_PBUS_axi_wready ), + .s_axi_bid ( MBUS_to_PBUS_axi_bid ), + .s_axi_bresp ( MBUS_to_PBUS_axi_bresp ), + .s_axi_bvalid ( MBUS_to_PBUS_axi_bvalid ), + .s_axi_bready ( MBUS_to_PBUS_axi_bready ), + .s_axi_arid ( MBUS_to_PBUS_axi_arid ), + .s_axi_araddr ( MBUS_to_PBUS_axi_araddr ), + .s_axi_arlen ( MBUS_to_PBUS_axi_arlen ), + .s_axi_arsize ( MBUS_to_PBUS_axi_arsize ), + .s_axi_arburst ( MBUS_to_PBUS_axi_arburst ), + .s_axi_arlock ( MBUS_to_PBUS_axi_arlock ), + .s_axi_arcache ( MBUS_to_PBUS_axi_arcache ), + .s_axi_arprot ( MBUS_to_PBUS_axi_arprot ), + .s_axi_arregion ( MBUS_to_PBUS_axi_arregion ), + .s_axi_arqos ( MBUS_to_PBUS_axi_arqos ), + .s_axi_arvalid ( MBUS_to_PBUS_axi_arvalid ), + .s_axi_arready ( MBUS_to_PBUS_axi_arready ), + .s_axi_rid ( MBUS_to_PBUS_axi_rid ), + .s_axi_rdata ( MBUS_to_PBUS_axi_rdata ), + .s_axi_rresp ( MBUS_to_PBUS_axi_rresp ), + .s_axi_rlast ( MBUS_to_PBUS_axi_rlast ), + .s_axi_rvalid ( MBUS_to_PBUS_axi_rvalid ), + .s_axi_rready ( MBUS_to_PBUS_axi_rready ) + ); + + ///////////////////// + // AXI Central DMA // + ///////////////////// + + // AXI-Lite bus from adapter to CDMA control interface + `DECLARE_AXILITE_BUS(AXILITE_to_CDMA, 32, 32, MBUS_ID_WIDTH) + + // AXI-lite converter + xlnx_axi4_to_axilite_d32_converter axi4_to_axilite_cdma_u ( + .aclk ( main_clk ), + .aresetn ( main_rstn ), + // AXI4 slave (from MBUS) + .s_axi_awid ( MBUS_to_CDMA_axi_awid ), + .s_axi_awaddr ( MBUS_to_CDMA_axi_awaddr ), + .s_axi_awlen ( MBUS_to_CDMA_axi_awlen ), + .s_axi_awsize ( MBUS_to_CDMA_axi_awsize ), + .s_axi_awburst ( MBUS_to_CDMA_axi_awburst ), + .s_axi_awlock ( MBUS_to_CDMA_axi_awlock ), + .s_axi_awcache ( MBUS_to_CDMA_axi_awcache ), + .s_axi_awprot ( MBUS_to_CDMA_axi_awprot ), + .s_axi_awregion ( MBUS_to_CDMA_axi_awregion ), + .s_axi_awqos ( MBUS_to_CDMA_axi_awqos ), + .s_axi_awvalid ( MBUS_to_CDMA_axi_awvalid ), + .s_axi_awready ( MBUS_to_CDMA_axi_awready ), + .s_axi_wdata ( MBUS_to_CDMA_axi_wdata ), + .s_axi_wstrb ( MBUS_to_CDMA_axi_wstrb ), + .s_axi_wlast ( MBUS_to_CDMA_axi_wlast ), + .s_axi_wvalid ( MBUS_to_CDMA_axi_wvalid ), + .s_axi_wready ( MBUS_to_CDMA_axi_wready ), + .s_axi_bid ( MBUS_to_CDMA_axi_bid ), + .s_axi_bresp ( MBUS_to_CDMA_axi_bresp ), + .s_axi_bvalid ( MBUS_to_CDMA_axi_bvalid ), + .s_axi_bready ( MBUS_to_CDMA_axi_bready ), + .s_axi_arid ( MBUS_to_CDMA_axi_arid ), + .s_axi_araddr ( MBUS_to_CDMA_axi_araddr ), + .s_axi_arlen ( MBUS_to_CDMA_axi_arlen ), + .s_axi_arsize ( MBUS_to_CDMA_axi_arsize ), + .s_axi_arburst ( MBUS_to_CDMA_axi_arburst ), + .s_axi_arlock ( MBUS_to_CDMA_axi_arlock ), + .s_axi_arcache ( MBUS_to_CDMA_axi_arcache ), + .s_axi_arprot ( MBUS_to_CDMA_axi_arprot ), + .s_axi_arregion ( MBUS_to_CDMA_axi_arregion ), + .s_axi_arqos ( MBUS_to_CDMA_axi_arqos ), + .s_axi_arvalid ( MBUS_to_CDMA_axi_arvalid ), + .s_axi_arready ( MBUS_to_CDMA_axi_arready ), + .s_axi_rid ( MBUS_to_CDMA_axi_rid ), + .s_axi_rdata ( MBUS_to_CDMA_axi_rdata ), + .s_axi_rresp ( MBUS_to_CDMA_axi_rresp ), + .s_axi_rlast ( MBUS_to_CDMA_axi_rlast ), + .s_axi_rvalid ( MBUS_to_CDMA_axi_rvalid ), + .s_axi_rready ( MBUS_to_CDMA_axi_rready ), + // AXI4-Lite master (to CDMA control interface) + .m_axi_awaddr ( AXILITE_to_CDMA_axilite_awaddr ), + .m_axi_awprot ( AXILITE_to_CDMA_axilite_awprot ), + .m_axi_awvalid ( AXILITE_to_CDMA_axilite_awvalid ), + .m_axi_awready ( AXILITE_to_CDMA_axilite_awready ), + .m_axi_wdata ( AXILITE_to_CDMA_axilite_wdata ), + .m_axi_wstrb ( AXILITE_to_CDMA_axilite_wstrb ), + .m_axi_wvalid ( AXILITE_to_CDMA_axilite_wvalid ), + .m_axi_wready ( AXILITE_to_CDMA_axilite_wready ), + .m_axi_bresp ( AXILITE_to_CDMA_axilite_bresp ), + .m_axi_bvalid ( AXILITE_to_CDMA_axilite_bvalid ), + .m_axi_bready ( AXILITE_to_CDMA_axilite_bready ), + .m_axi_araddr ( AXILITE_to_CDMA_axilite_araddr ), + .m_axi_arprot ( AXILITE_to_CDMA_axilite_arprot ), + .m_axi_arvalid ( AXILITE_to_CDMA_axilite_arvalid ), + .m_axi_arready ( AXILITE_to_CDMA_axilite_arready ), + .m_axi_rdata ( AXILITE_to_CDMA_axilite_rdata ), + .m_axi_rresp ( AXILITE_to_CDMA_axilite_rresp ), + .m_axi_rvalid ( AXILITE_to_CDMA_axilite_rvalid ), + .m_axi_rready ( AXILITE_to_CDMA_axilite_rready ) + ); + + // Tie-off unused signals + assign CDMA_to_MBUS_axi_awid = '0; + assign CDMA_to_MBUS_axi_awlock = '0; + assign CDMA_to_MBUS_axi_awqos = '0; + assign CDMA_to_MBUS_axi_arid = '0; + assign CDMA_to_MBUS_axi_arlock = '0; + assign CDMA_to_MBUS_axi_arqos = '0; + assign CDMA_to_MBUS_axi_awregion = '0; + + // AXI CDMA + xlnx_axi_cdma cdma_u ( + // Clocks & Reset + .s_axi_lite_aclk ( CDMA_clk ), + .s_axi_lite_aresetn ( CDMA_rstn ), + // Assume master on MBUS domain + // TODO: config for HBUS as well + .m_axi_aclk ( main_clk ), + // Interrupt + .cdma_introut ( irq_cdma_to_plic ), + // AXI-Lite Control Interface (from converter) + .s_axi_lite_awvalid ( AXILITE_to_CDMA_axilite_awvalid ), + .s_axi_lite_awready ( AXILITE_to_CDMA_axilite_awready ), + .s_axi_lite_awaddr ( AXILITE_to_CDMA_axilite_awaddr[5:0] ), + .s_axi_lite_wvalid ( AXILITE_to_CDMA_axilite_wvalid ), + .s_axi_lite_wready ( AXILITE_to_CDMA_axilite_wready ), + .s_axi_lite_wdata ( AXILITE_to_CDMA_axilite_wdata[31:0] ), + // .s_axi_lite_wstrb ( ), // not present + .s_axi_lite_bvalid ( AXILITE_to_CDMA_axilite_bvalid ), + .s_axi_lite_bready ( AXILITE_to_CDMA_axilite_bready ), + .s_axi_lite_bresp ( AXILITE_to_CDMA_axilite_bresp ), + .s_axi_lite_arvalid ( AXILITE_to_CDMA_axilite_arvalid ), + .s_axi_lite_arready ( AXILITE_to_CDMA_axilite_arready ), + .s_axi_lite_araddr ( AXILITE_to_CDMA_axilite_araddr[5:0] ), + .s_axi_lite_rvalid ( AXILITE_to_CDMA_axilite_rvalid ), + .s_axi_lite_rready ( AXILITE_to_CDMA_axilite_rready ), + .s_axi_lite_rdata ( AXILITE_to_CDMA_axilite_rdata[31:0] ), + .s_axi_lite_rresp ( AXILITE_to_CDMA_axilite_rresp ), + // AXI4 Master + .m_axi_awaddr ( CDMA_to_MBUS_axi_awaddr ), + .m_axi_awlen ( CDMA_to_MBUS_axi_awlen ), + .m_axi_awsize ( CDMA_to_MBUS_axi_awsize ), + .m_axi_awburst ( CDMA_to_MBUS_axi_awburst ), + .m_axi_awprot ( CDMA_to_MBUS_axi_awprot ), + .m_axi_awcache ( CDMA_to_MBUS_axi_awcache ), + .m_axi_awvalid ( CDMA_to_MBUS_axi_awvalid ), + .m_axi_awready ( CDMA_to_MBUS_axi_awready ), + .m_axi_wdata ( CDMA_to_MBUS_axi_wdata ), + .m_axi_wstrb ( CDMA_to_MBUS_axi_wstrb ), + .m_axi_wlast ( CDMA_to_MBUS_axi_wlast ), + .m_axi_wvalid ( CDMA_to_MBUS_axi_wvalid ), + .m_axi_wready ( CDMA_to_MBUS_axi_wready ), + .m_axi_bvalid ( CDMA_to_MBUS_axi_bvalid ), + .m_axi_bready ( CDMA_to_MBUS_axi_bready ), + .m_axi_bresp ( CDMA_to_MBUS_axi_bresp ), + .m_axi_araddr ( CDMA_to_MBUS_axi_araddr ), + .m_axi_arlen ( CDMA_to_MBUS_axi_arlen ), + .m_axi_arsize ( CDMA_to_MBUS_axi_arsize ), + .m_axi_arburst ( CDMA_to_MBUS_axi_arburst ), + .m_axi_arprot ( CDMA_to_MBUS_axi_arprot ), + .m_axi_arcache ( CDMA_to_MBUS_axi_arcache ), + .m_axi_arvalid ( CDMA_to_MBUS_axi_arvalid ), + .m_axi_arready ( CDMA_to_MBUS_axi_arready ), + .m_axi_rdata ( CDMA_to_MBUS_axi_rdata ), + .m_axi_rresp ( CDMA_to_MBUS_axi_rresp ), + .m_axi_rlast ( CDMA_to_MBUS_axi_rlast ), + .m_axi_rvalid ( CDMA_to_MBUS_axi_rvalid ), + .m_axi_rready ( CDMA_to_MBUS_axi_rready ), + // Scatter-Gather interface not used + .cdma_tvect_out () + ); + +// In HPC profile +`ifdef HPC + + //////////////////// + // DDR4 Channel 1 // + //////////////////// + + // TODO127: export these to config + logic ddr4ch1_clk300MHz; + logic ddr4ch1_rst300MHz; + + // DDR channel 1 on MBUS + ddr4_channel_wrapper # ( + .ENABLE_CACHE ( 1 ), // Always enabled for DDR4CH1 + .LOCAL_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .LOCAL_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .LOCAL_ID_WIDTH ( MBUS_ID_WIDTH ) + ) ddr4_channel_1_wrapper_u ( + .clock_i ( main_clk ), + .reset_ni ( main_rstn ), + // DDR4 differential clock + .clk_300mhz_x_p_i ( clk_300mhz_1_p_i ), + .clk_300mhz_x_n_i ( clk_300mhz_1_n_i ), + + // Output clock and reset + .ddr_clk_o ( ddr4ch1_clk300MHz ), + .ddr_rst_o ( ddr4ch1_rst300MHz ), + + // Connect DDR4 channel 1 + .cx_ddr4_adr ( c1_ddr4_adr ), + .cx_ddr4_ba ( c1_ddr4_ba ), + .cx_ddr4_cke ( c1_ddr4_cke ), + .cx_ddr4_cs_n ( c1_ddr4_cs_n ), + .cx_ddr4_dq ( c1_ddr4_dq ), + .cx_ddr4_dqs_t ( c1_ddr4_dqs_t ), + .cx_ddr4_dqs_c ( c1_ddr4_dqs_c ), + .cx_ddr4_odt ( c1_ddr4_odt ), + .cx_ddr4_parity ( c1_ddr4_parity ), + .cx_ddr4_bg ( c1_ddr4_bg ), + .cx_ddr4_act_n ( c1_ddr4_act_n ), + .cx_ddr4_reset_n ( c1_ddr4_reset_n ), + .cx_ddr4_ck_t ( c1_ddr4_ck_t ), + .cx_ddr4_ck_c ( c1_ddr4_ck_c ), + + // AXILITE interface - for ECC status and control - not connected + .s_ctrl_axilite_awvalid ( 1'b0 ), + .s_ctrl_axilite_awready ( ), + .s_ctrl_axilite_awaddr ( 32'd0 ), + .s_ctrl_axilite_wvalid ( 1'b0 ), + .s_ctrl_axilite_wready ( ), + .s_ctrl_axilite_wdata ( 32'd0 ), + .s_ctrl_axilite_bvalid ( ), + .s_ctrl_axilite_bready ( 1'b1 ), + .s_ctrl_axilite_bresp ( ), + .s_ctrl_axilite_arvalid ( 1'b0 ), + .s_ctrl_axilite_arready ( ), + .s_ctrl_axilite_araddr ( 31'd0 ), + .s_ctrl_axilite_rvalid ( ), + .s_ctrl_axilite_rready ( 1'b1 ), + .s_ctrl_axilite_rdata ( ), + .s_ctrl_axilite_rresp ( ), + + // Slave interface + .s_axi_awid ( MBUS_to_DDR4CH1_axi_awid ), + .s_axi_awaddr ( MBUS_to_DDR4CH1_axi_awaddr ), + .s_axi_awlen ( MBUS_to_DDR4CH1_axi_awlen ), + .s_axi_awsize ( MBUS_to_DDR4CH1_axi_awsize ), + .s_axi_awburst ( MBUS_to_DDR4CH1_axi_awburst ), + .s_axi_awlock ( MBUS_to_DDR4CH1_axi_awlock ), + .s_axi_awcache ( MBUS_to_DDR4CH1_axi_awcache ), + .s_axi_awprot ( MBUS_to_DDR4CH1_axi_awprot ), + .s_axi_awregion ( MBUS_to_DDR4CH1_axi_awregion ), + .s_axi_awqos ( MBUS_to_DDR4CH1_axi_awqos ), + .s_axi_awvalid ( MBUS_to_DDR4CH1_axi_awvalid ), + .s_axi_awready ( MBUS_to_DDR4CH1_axi_awready ), + .s_axi_wdata ( MBUS_to_DDR4CH1_axi_wdata ), + .s_axi_wstrb ( MBUS_to_DDR4CH1_axi_wstrb ), + .s_axi_wlast ( MBUS_to_DDR4CH1_axi_wlast ), + .s_axi_wvalid ( MBUS_to_DDR4CH1_axi_wvalid ), + .s_axi_wready ( MBUS_to_DDR4CH1_axi_wready ), + .s_axi_bid ( MBUS_to_DDR4CH1_axi_bid ), + .s_axi_bresp ( MBUS_to_DDR4CH1_axi_bresp ), + .s_axi_bvalid ( MBUS_to_DDR4CH1_axi_bvalid ), + .s_axi_bready ( MBUS_to_DDR4CH1_axi_bready ), + .s_axi_arid ( MBUS_to_DDR4CH1_axi_arid ), + .s_axi_araddr ( MBUS_to_DDR4CH1_axi_araddr ), + .s_axi_arlen ( MBUS_to_DDR4CH1_axi_arlen ), + .s_axi_arsize ( MBUS_to_DDR4CH1_axi_arsize ), + .s_axi_arburst ( MBUS_to_DDR4CH1_axi_arburst ), + .s_axi_arlock ( MBUS_to_DDR4CH1_axi_arlock ), + .s_axi_arcache ( MBUS_to_DDR4CH1_axi_arcache ), + .s_axi_arprot ( MBUS_to_DDR4CH1_axi_arprot ), + .s_axi_arregion ( MBUS_to_DDR4CH1_axi_arregion ), + .s_axi_arqos ( MBUS_to_DDR4CH1_axi_arqos ), + .s_axi_arvalid ( MBUS_to_DDR4CH1_axi_arvalid ), + .s_axi_arready ( MBUS_to_DDR4CH1_axi_arready ), + .s_axi_rid ( MBUS_to_DDR4CH1_axi_rid ), + .s_axi_rdata ( MBUS_to_DDR4CH1_axi_rdata ), + .s_axi_rresp ( MBUS_to_DDR4CH1_axi_rresp ), + .s_axi_rlast ( MBUS_to_DDR4CH1_axi_rlast ), + .s_axi_rvalid ( MBUS_to_DDR4CH1_axi_rvalid ), + .s_axi_rready ( MBUS_to_DDR4CH1_axi_rready ) + ); + + /////////////////// + // HLS CONV2D IP // + /////////////////// + + // HLS CONV2D -> HBUS + `DECLARE_AXI_BUS(HLS_gmem0_d512, HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH) + // TODO: Only one HBUS accelerator for now + `DECLARE_AXI_BUS(s_acc_HBUS, HBUS_DATA_WIDTH, HBUS_ADDR_WIDTH, HBUS_ID_WIDTH) + // Just pass through the interface + `ASSIGN_AXI_BUS(s_acc_HBUS, HLS_gmem0_d512) + + hls_conv2d_wrapper # ( + // MBUS parameters + .MBUS_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .MBUS_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .MBUS_ID_WIDTH ( MBUS_ID_WIDTH ), + // HBUS parameters + .HBUS_DATA_WIDTH ( HBUS_DATA_WIDTH ), + .HBUS_ADDR_WIDTH ( HBUS_ADDR_WIDTH ), + .HBUS_ID_WIDTH ( HBUS_ID_WIDTH ) + ) hls_conv2d_wrapper_u ( + // MBUS clock and reset + .main_clk_i ( main_clk ), + .main_rstn_i ( main_rstn ), + // HLS IP clock and reset (from HBUS) + .HLS_CONTROL_clk_i ( HLS_CONTROL_clk ), + .HLS_CONTROL_rstn_i ( HLS_CONTROL_rstn ), + // Slave for control + .s_HLS_CONTROL_axi_awid ( MBUS_to_HLS_CONTROL_axi_awid ), + .s_HLS_CONTROL_axi_awaddr ( MBUS_to_HLS_CONTROL_axi_awaddr ), + .s_HLS_CONTROL_axi_awlen ( MBUS_to_HLS_CONTROL_axi_awlen ), + .s_HLS_CONTROL_axi_awsize ( MBUS_to_HLS_CONTROL_axi_awsize ), + .s_HLS_CONTROL_axi_awburst ( MBUS_to_HLS_CONTROL_axi_awburst ), + .s_HLS_CONTROL_axi_awlock ( MBUS_to_HLS_CONTROL_axi_awlock ), + .s_HLS_CONTROL_axi_awcache ( MBUS_to_HLS_CONTROL_axi_awcache ), + .s_HLS_CONTROL_axi_awprot ( MBUS_to_HLS_CONTROL_axi_awprot ), + .s_HLS_CONTROL_axi_awregion ( MBUS_to_HLS_CONTROL_axi_awregion ), + .s_HLS_CONTROL_axi_awqos ( MBUS_to_HLS_CONTROL_axi_awqos ), + .s_HLS_CONTROL_axi_awvalid ( MBUS_to_HLS_CONTROL_axi_awvalid ), + .s_HLS_CONTROL_axi_awready ( MBUS_to_HLS_CONTROL_axi_awready ), + .s_HLS_CONTROL_axi_wdata ( MBUS_to_HLS_CONTROL_axi_wdata ), + .s_HLS_CONTROL_axi_wstrb ( MBUS_to_HLS_CONTROL_axi_wstrb ), + .s_HLS_CONTROL_axi_wlast ( MBUS_to_HLS_CONTROL_axi_wlast ), + .s_HLS_CONTROL_axi_wvalid ( MBUS_to_HLS_CONTROL_axi_wvalid ), + .s_HLS_CONTROL_axi_wready ( MBUS_to_HLS_CONTROL_axi_wready ), + .s_HLS_CONTROL_axi_bid ( MBUS_to_HLS_CONTROL_axi_bid ), + .s_HLS_CONTROL_axi_bresp ( MBUS_to_HLS_CONTROL_axi_bresp ), + .s_HLS_CONTROL_axi_bvalid ( MBUS_to_HLS_CONTROL_axi_bvalid ), + .s_HLS_CONTROL_axi_bready ( MBUS_to_HLS_CONTROL_axi_bready ), + .s_HLS_CONTROL_axi_arid ( MBUS_to_HLS_CONTROL_axi_arid ), + .s_HLS_CONTROL_axi_araddr ( MBUS_to_HLS_CONTROL_axi_araddr ), + .s_HLS_CONTROL_axi_arlen ( MBUS_to_HLS_CONTROL_axi_arlen ), + .s_HLS_CONTROL_axi_arsize ( MBUS_to_HLS_CONTROL_axi_arsize ), + .s_HLS_CONTROL_axi_arburst ( MBUS_to_HLS_CONTROL_axi_arburst ), + .s_HLS_CONTROL_axi_arlock ( MBUS_to_HLS_CONTROL_axi_arlock ), + .s_HLS_CONTROL_axi_arcache ( MBUS_to_HLS_CONTROL_axi_arcache ), + .s_HLS_CONTROL_axi_arprot ( MBUS_to_HLS_CONTROL_axi_arprot ), + .s_HLS_CONTROL_axi_arregion ( MBUS_to_HLS_CONTROL_axi_arregion ), + .s_HLS_CONTROL_axi_arqos ( MBUS_to_HLS_CONTROL_axi_arqos ), + .s_HLS_CONTROL_axi_arvalid ( MBUS_to_HLS_CONTROL_axi_arvalid ), + .s_HLS_CONTROL_axi_arready ( MBUS_to_HLS_CONTROL_axi_arready ), + .s_HLS_CONTROL_axi_rid ( MBUS_to_HLS_CONTROL_axi_rid ), + .s_HLS_CONTROL_axi_rdata ( MBUS_to_HLS_CONTROL_axi_rdata ), + .s_HLS_CONTROL_axi_rresp ( MBUS_to_HLS_CONTROL_axi_rresp ), + .s_HLS_CONTROL_axi_rlast ( MBUS_to_HLS_CONTROL_axi_rlast ), + .s_HLS_CONTROL_axi_rvalid ( MBUS_to_HLS_CONTROL_axi_rvalid ), + .s_HLS_CONTROL_axi_rready ( MBUS_to_HLS_CONTROL_axi_rready ), + // Master to HBUS + .m_HLS_gmem0_d512_axi_awid ( HLS_gmem0_d512_axi_awid ), + .m_HLS_gmem0_d512_axi_awaddr ( HLS_gmem0_d512_axi_awaddr ), + .m_HLS_gmem0_d512_axi_awlen ( HLS_gmem0_d512_axi_awlen ), + .m_HLS_gmem0_d512_axi_awsize ( HLS_gmem0_d512_axi_awsize ), + .m_HLS_gmem0_d512_axi_awburst ( HLS_gmem0_d512_axi_awburst ), + .m_HLS_gmem0_d512_axi_awlock ( HLS_gmem0_d512_axi_awlock ), + .m_HLS_gmem0_d512_axi_awcache ( HLS_gmem0_d512_axi_awcache ), + .m_HLS_gmem0_d512_axi_awprot ( HLS_gmem0_d512_axi_awprot ), + .m_HLS_gmem0_d512_axi_awqos ( HLS_gmem0_d512_axi_awqos ), + .m_HLS_gmem0_d512_axi_awvalid ( HLS_gmem0_d512_axi_awvalid ), + .m_HLS_gmem0_d512_axi_awready ( HLS_gmem0_d512_axi_awready ), + .m_HLS_gmem0_d512_axi_awregion ( HLS_gmem0_d512_axi_awregion ), + .m_HLS_gmem0_d512_axi_wdata ( HLS_gmem0_d512_axi_wdata ), + .m_HLS_gmem0_d512_axi_wstrb ( HLS_gmem0_d512_axi_wstrb ), + .m_HLS_gmem0_d512_axi_wlast ( HLS_gmem0_d512_axi_wlast ), + .m_HLS_gmem0_d512_axi_wvalid ( HLS_gmem0_d512_axi_wvalid ), + .m_HLS_gmem0_d512_axi_wready ( HLS_gmem0_d512_axi_wready ), + .m_HLS_gmem0_d512_axi_bid ( HLS_gmem0_d512_axi_bid ), + .m_HLS_gmem0_d512_axi_bresp ( HLS_gmem0_d512_axi_bresp ), + .m_HLS_gmem0_d512_axi_bvalid ( HLS_gmem0_d512_axi_bvalid ), + .m_HLS_gmem0_d512_axi_bready ( HLS_gmem0_d512_axi_bready ), + .m_HLS_gmem0_d512_axi_arid ( HLS_gmem0_d512_axi_arid ), + .m_HLS_gmem0_d512_axi_araddr ( HLS_gmem0_d512_axi_araddr ), + .m_HLS_gmem0_d512_axi_arlen ( HLS_gmem0_d512_axi_arlen ), + .m_HLS_gmem0_d512_axi_arsize ( HLS_gmem0_d512_axi_arsize ), + .m_HLS_gmem0_d512_axi_arburst ( HLS_gmem0_d512_axi_arburst ), + .m_HLS_gmem0_d512_axi_arlock ( HLS_gmem0_d512_axi_arlock ), + .m_HLS_gmem0_d512_axi_arcache ( HLS_gmem0_d512_axi_arcache ), + .m_HLS_gmem0_d512_axi_arprot ( HLS_gmem0_d512_axi_arprot ), + .m_HLS_gmem0_d512_axi_arqos ( HLS_gmem0_d512_axi_arqos ), + .m_HLS_gmem0_d512_axi_arvalid ( HLS_gmem0_d512_axi_arvalid ), + .m_HLS_gmem0_d512_axi_arready ( HLS_gmem0_d512_axi_arready ), + .m_HLS_gmem0_d512_axi_arregion ( HLS_gmem0_d512_axi_arregion ), + .m_HLS_gmem0_d512_axi_rid ( HLS_gmem0_d512_axi_rid ), + .m_HLS_gmem0_d512_axi_rdata ( HLS_gmem0_d512_axi_rdata ), + .m_HLS_gmem0_d512_axi_rresp ( HLS_gmem0_d512_axi_rresp ), + .m_HLS_gmem0_d512_axi_rlast ( HLS_gmem0_d512_axi_rlast ), + .m_HLS_gmem0_d512_axi_rvalid ( HLS_gmem0_d512_axi_rvalid ), + .m_HLS_gmem0_d512_axi_rready ( HLS_gmem0_d512_axi_rready ), + // Interrupt + .hls_interrupt_o ( hls_interrupt_to_plic ) + ); + + ////////// + // HBUS // + ////////// + + highperformance_bus # ( + .HBUS_DATA_WIDTH ( HBUS_DATA_WIDTH ), + .HBUS_ADDR_WIDTH ( HBUS_ADDR_WIDTH ), + .HBUS_ID_WIDTH ( HBUS_ID_WIDTH ), + .MBUS_DATA_WIDTH ( MBUS_DATA_WIDTH ), + .MBUS_ADDR_WIDTH ( MBUS_ADDR_WIDTH ), + .MBUS_ID_WIDTH ( MBUS_ID_WIDTH ), + // TODO: these are fixed for now + .NUM_ACC_MASTERS ( 1 ), + .NUM_DDR_CHANNELS ( 1 ), + .NUM_HBM_CHANNELS ( 0 ) + ) highperformance_bus_u ( + // MBUS domain clock and reset + .main_clock_i ( main_clk ), + .main_reset_ni ( main_rstn ), + // From MBUS + .s_MBUS_axi_awid ( MBUS_to_HBUS_axi_awid ), + .s_MBUS_axi_awaddr ( MBUS_to_HBUS_axi_awaddr ), + .s_MBUS_axi_awlen ( MBUS_to_HBUS_axi_awlen ), + .s_MBUS_axi_awsize ( MBUS_to_HBUS_axi_awsize ), + .s_MBUS_axi_awburst ( MBUS_to_HBUS_axi_awburst ), + .s_MBUS_axi_awlock ( MBUS_to_HBUS_axi_awlock ), + .s_MBUS_axi_awcache ( MBUS_to_HBUS_axi_awcache ), + .s_MBUS_axi_awprot ( MBUS_to_HBUS_axi_awprot ), + .s_MBUS_axi_awregion ( MBUS_to_HBUS_axi_awregion ), + .s_MBUS_axi_awqos ( MBUS_to_HBUS_axi_awqos ), + .s_MBUS_axi_awvalid ( MBUS_to_HBUS_axi_awvalid ), + .s_MBUS_axi_awready ( MBUS_to_HBUS_axi_awready ), + .s_MBUS_axi_wdata ( MBUS_to_HBUS_axi_wdata ), + .s_MBUS_axi_wstrb ( MBUS_to_HBUS_axi_wstrb ), + .s_MBUS_axi_wlast ( MBUS_to_HBUS_axi_wlast ), + .s_MBUS_axi_wvalid ( MBUS_to_HBUS_axi_wvalid ), + .s_MBUS_axi_wready ( MBUS_to_HBUS_axi_wready ), + .s_MBUS_axi_bid ( MBUS_to_HBUS_axi_bid ), + .s_MBUS_axi_bresp ( MBUS_to_HBUS_axi_bresp ), + .s_MBUS_axi_bvalid ( MBUS_to_HBUS_axi_bvalid ), + .s_MBUS_axi_bready ( MBUS_to_HBUS_axi_bready ), + .s_MBUS_axi_arid ( MBUS_to_HBUS_axi_arid ), + .s_MBUS_axi_araddr ( MBUS_to_HBUS_axi_araddr ), + .s_MBUS_axi_arlen ( MBUS_to_HBUS_axi_arlen ), + .s_MBUS_axi_arsize ( MBUS_to_HBUS_axi_arsize ), + .s_MBUS_axi_arburst ( MBUS_to_HBUS_axi_arburst ), + .s_MBUS_axi_arlock ( MBUS_to_HBUS_axi_arlock ), + .s_MBUS_axi_arcache ( MBUS_to_HBUS_axi_arcache ), + .s_MBUS_axi_arprot ( MBUS_to_HBUS_axi_arprot ), + .s_MBUS_axi_arregion ( MBUS_to_HBUS_axi_arregion ), + .s_MBUS_axi_arqos ( MBUS_to_HBUS_axi_arqos ), + .s_MBUS_axi_arvalid ( MBUS_to_HBUS_axi_arvalid ), + .s_MBUS_axi_arready ( MBUS_to_HBUS_axi_arready ), + .s_MBUS_axi_rid ( MBUS_to_HBUS_axi_rid ), + .s_MBUS_axi_rdata ( MBUS_to_HBUS_axi_rdata ), + .s_MBUS_axi_rresp ( MBUS_to_HBUS_axi_rresp ), + .s_MBUS_axi_rlast ( MBUS_to_HBUS_axi_rlast ), + .s_MBUS_axi_rvalid ( MBUS_to_HBUS_axi_rvalid ), + .s_MBUS_axi_rready ( MBUS_to_HBUS_axi_rready ), + // To MBUS + .m_MBUS_axi_awid ( HBUS_to_MBUS_axi_awid ), + .m_MBUS_axi_awaddr ( HBUS_to_MBUS_axi_awaddr ), + .m_MBUS_axi_awlen ( HBUS_to_MBUS_axi_awlen ), + .m_MBUS_axi_awsize ( HBUS_to_MBUS_axi_awsize ), + .m_MBUS_axi_awburst ( HBUS_to_MBUS_axi_awburst ), + .m_MBUS_axi_awlock ( HBUS_to_MBUS_axi_awlock ), + .m_MBUS_axi_awcache ( HBUS_to_MBUS_axi_awcache ), + .m_MBUS_axi_awprot ( HBUS_to_MBUS_axi_awprot ), + .m_MBUS_axi_awregion ( HBUS_to_MBUS_axi_awregion ), + .m_MBUS_axi_awqos ( HBUS_to_MBUS_axi_awqos ), + .m_MBUS_axi_awvalid ( HBUS_to_MBUS_axi_awvalid ), + .m_MBUS_axi_awready ( HBUS_to_MBUS_axi_awready ), + .m_MBUS_axi_wdata ( HBUS_to_MBUS_axi_wdata ), + .m_MBUS_axi_wstrb ( HBUS_to_MBUS_axi_wstrb ), + .m_MBUS_axi_wlast ( HBUS_to_MBUS_axi_wlast ), + .m_MBUS_axi_wvalid ( HBUS_to_MBUS_axi_wvalid ), + .m_MBUS_axi_wready ( HBUS_to_MBUS_axi_wready ), + .m_MBUS_axi_bid ( HBUS_to_MBUS_axi_bid ), + .m_MBUS_axi_bresp ( HBUS_to_MBUS_axi_bresp ), + .m_MBUS_axi_bvalid ( HBUS_to_MBUS_axi_bvalid ), + .m_MBUS_axi_bready ( HBUS_to_MBUS_axi_bready ), + .m_MBUS_axi_arid ( HBUS_to_MBUS_axi_arid ), + .m_MBUS_axi_araddr ( HBUS_to_MBUS_axi_araddr ), + .m_MBUS_axi_arlen ( HBUS_to_MBUS_axi_arlen ), + .m_MBUS_axi_arsize ( HBUS_to_MBUS_axi_arsize ), + .m_MBUS_axi_arburst ( HBUS_to_MBUS_axi_arburst ), + .m_MBUS_axi_arlock ( HBUS_to_MBUS_axi_arlock ), + .m_MBUS_axi_arcache ( HBUS_to_MBUS_axi_arcache ), + .m_MBUS_axi_arprot ( HBUS_to_MBUS_axi_arprot ), + .m_MBUS_axi_arregion ( HBUS_to_MBUS_axi_arregion ), + .m_MBUS_axi_arqos ( HBUS_to_MBUS_axi_arqos ), + .m_MBUS_axi_arvalid ( HBUS_to_MBUS_axi_arvalid ), + .m_MBUS_axi_arready ( HBUS_to_MBUS_axi_arready ), + .m_MBUS_axi_rid ( HBUS_to_MBUS_axi_rid ), + .m_MBUS_axi_rdata ( HBUS_to_MBUS_axi_rdata ), + .m_MBUS_axi_rresp ( HBUS_to_MBUS_axi_rresp ), + .m_MBUS_axi_rlast ( HBUS_to_MBUS_axi_rlast ), + .m_MBUS_axi_rvalid ( HBUS_to_MBUS_axi_rvalid ), + .m_MBUS_axi_rready ( HBUS_to_MBUS_axi_rready ), + // From Accelerator(s) + // NOTE: just one for now + // TODO: add a CONCAT to support multiple ports + .s_acc_axi_awid ( s_acc_HBUS_axi_awid ), + .s_acc_axi_awaddr ( s_acc_HBUS_axi_awaddr ), + .s_acc_axi_awlen ( s_acc_HBUS_axi_awlen ), + .s_acc_axi_awsize ( s_acc_HBUS_axi_awsize ), + .s_acc_axi_awburst ( s_acc_HBUS_axi_awburst ), + .s_acc_axi_awlock ( s_acc_HBUS_axi_awlock ), + .s_acc_axi_awcache ( s_acc_HBUS_axi_awcache ), + .s_acc_axi_awprot ( s_acc_HBUS_axi_awprot ), + .s_acc_axi_awregion ( s_acc_HBUS_axi_awregion ), + .s_acc_axi_awqos ( s_acc_HBUS_axi_awqos ), + .s_acc_axi_awvalid ( s_acc_HBUS_axi_awvalid ), + .s_acc_axi_awready ( s_acc_HBUS_axi_awready ), + .s_acc_axi_wdata ( s_acc_HBUS_axi_wdata ), + .s_acc_axi_wstrb ( s_acc_HBUS_axi_wstrb ), + .s_acc_axi_wlast ( s_acc_HBUS_axi_wlast ), + .s_acc_axi_wvalid ( s_acc_HBUS_axi_wvalid ), + .s_acc_axi_wready ( s_acc_HBUS_axi_wready ), + .s_acc_axi_bid ( s_acc_HBUS_axi_bid ), + .s_acc_axi_bresp ( s_acc_HBUS_axi_bresp ), + .s_acc_axi_bvalid ( s_acc_HBUS_axi_bvalid ), + .s_acc_axi_bready ( s_acc_HBUS_axi_bready ), + .s_acc_axi_arid ( s_acc_HBUS_axi_arid ), + .s_acc_axi_araddr ( s_acc_HBUS_axi_araddr ), + .s_acc_axi_arlen ( s_acc_HBUS_axi_arlen ), + .s_acc_axi_arsize ( s_acc_HBUS_axi_arsize ), + .s_acc_axi_arburst ( s_acc_HBUS_axi_arburst ), + .s_acc_axi_arlock ( s_acc_HBUS_axi_arlock ), + .s_acc_axi_arcache ( s_acc_HBUS_axi_arcache ), + .s_acc_axi_arprot ( s_acc_HBUS_axi_arprot ), + .s_acc_axi_arregion ( s_acc_HBUS_axi_arregion ), + .s_acc_axi_arqos ( s_acc_HBUS_axi_arqos ), + .s_acc_axi_arvalid ( s_acc_HBUS_axi_arvalid ), + .s_acc_axi_arready ( s_acc_HBUS_axi_arready ), + .s_acc_axi_rid ( s_acc_HBUS_axi_rid ), + .s_acc_axi_rdata ( s_acc_HBUS_axi_rdata ), + .s_acc_axi_rresp ( s_acc_HBUS_axi_rresp ), + .s_acc_axi_rlast ( s_acc_HBUS_axi_rlast ), + .s_acc_axi_rvalid ( s_acc_HBUS_axi_rvalid ), + .s_acc_axi_rready ( s_acc_HBUS_axi_rready ), + + // DDR channel 0 on MBUS + // DDR4 differential clock + .clk_300mhz_x_p_i ( clk_300mhz_0_p_i ), + .clk_300mhz_x_n_i ( clk_300mhz_0_n_i ), + // DDR4 user clock and reset + .clk_300MHz_o ( clk_300MHz ), + .rstn_300MHz_o ( rstn_300MHz ), + // Connect DDR4 channel 0 + .cx_ddr4_adr ( c0_ddr4_adr ), + .cx_ddr4_ba ( c0_ddr4_ba ), + .cx_ddr4_cke ( c0_ddr4_cke ), + .cx_ddr4_cs_n ( c0_ddr4_cs_n ), + .cx_ddr4_dq ( c0_ddr4_dq ), + .cx_ddr4_dqs_t ( c0_ddr4_dqs_t ), + .cx_ddr4_dqs_c ( c0_ddr4_dqs_c ), + .cx_ddr4_odt ( c0_ddr4_odt ), + .cx_ddr4_parity ( c0_ddr4_parity ), + .cx_ddr4_bg ( c0_ddr4_bg ), + .cx_ddr4_act_n ( c0_ddr4_act_n ), + .cx_ddr4_reset_n ( c0_ddr4_reset_n ), + .cx_ddr4_ck_t ( c0_ddr4_ck_t ), + .cx_ddr4_ck_c ( c0_ddr4_ck_c ), + + // AXILITE interface - for ECC status and control - not connected + .s_ctrl_axilite_awvalid ( 1'b0 ), + .s_ctrl_axilite_awready ( ), + .s_ctrl_axilite_awaddr ( '0 ), + .s_ctrl_axilite_wvalid ( 1'b0 ), + .s_ctrl_axilite_wready ( ), + .s_ctrl_axilite_wdata ( '0 ), + .s_ctrl_axilite_bvalid ( ), + .s_ctrl_axilite_bready ( 1'b1 ), + .s_ctrl_axilite_bresp ( ), + .s_ctrl_axilite_arvalid ( 1'b0 ), + .s_ctrl_axilite_arready ( ), + .s_ctrl_axilite_araddr ( '0 ), + .s_ctrl_axilite_rvalid ( ), + .s_ctrl_axilite_rready ( 1'b1 ), + .s_ctrl_axilite_rdata ( ), + .s_ctrl_axilite_rresp ( ), + .s_ctrl_axilite_arprot ( '0 ), + .s_ctrl_axilite_wstrb ( '0 ), + .s_ctrl_axilite_awprot ( '0 ) + ); + +`endif // HPC + + +endmodule : uninasoc diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_axi.svh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_axi.svh new file mode 100644 index 0000000000000000000000000000000000000000..cdddfbd9282494ea6611be994de79ea0811032f8 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_axi.svh @@ -0,0 +1,1281 @@ +// Author: Vincenzo Maisto +// Author: Stefano Mercogliano +// Author: Manuel Maddaluno +// Description: Utility variables and macros for AXI interconnections in UninaSoC +// Note: The main rationale behind this macro is to avoid the usage of structs and +// macros for the widest possible syntax compatibility. + + +`ifndef UNINASOC_AXI_SVH__ +`define UNINASOC_AXI_SVH__ + +////////////////////////////////////////////////////// +// ___ _ // +// | _ \__ _ _ _ __ _ _ __ ___| |_ ___ _ _ ___ // +// | _/ _` | '_/ _` | ' \/ -_) _/ -_) '_(_-< // +// |_| \__,_|_| \__,_|_|_|_\___|\__\___|_| /__/ // +// // +////////////////////////////////////////////////////// + +// AXI4 bus parameters +// NOTE: these cannot be macro-based because of Vivado IP packege constraints +localparam int unsigned AXI_LEN_WIDTH = 8; +localparam int unsigned AXI_SIZE_WIDTH = 3; +localparam int unsigned AXI_BURST_WIDTH = 2; +localparam int unsigned AXI_LOCK_WIDTH = 1; +localparam int unsigned AXI_CACHE_WIDTH = 4; +localparam int unsigned AXI_PROT_WIDTH = 3; +localparam int unsigned AXI_QOS_WIDTH = 4; +localparam int unsigned AXI_VALID_WIDTH = 1; +localparam int unsigned AXI_READY_WIDTH = 1; +localparam int unsigned AXI_LAST_WIDTH = 1; +localparam int unsigned AXI_RESP_WIDTH = 2; +localparam int unsigned AXI_REGION_WIDTH = 4; + +////////////////////////////////// +// _____ // +// |_ _| _ _ __ ___ ___ // +// | || || | '_ \/ -_|_-< // +// |_| \_, | .__/\___/__/ // +// |__/|_| // +////////////////////////////////// + +// AXI signal types +typedef logic [AXI_LEN_WIDTH -1 : 0] axi_len_t; +typedef logic [AXI_SIZE_WIDTH -1 : 0] axi_size_t; +typedef logic [AXI_BURST_WIDTH -1 : 0] axi_burst_t; +typedef logic [AXI_LOCK_WIDTH -1 : 0] axi_lock_t; +typedef logic [AXI_CACHE_WIDTH -1 : 0] axi_cache_t; +typedef logic [AXI_PROT_WIDTH -1 : 0] axi_prot_t; +typedef logic [AXI_QOS_WIDTH -1 : 0] axi_qos_t; +typedef logic [AXI_VALID_WIDTH -1 : 0] axi_valid_t; +typedef logic [AXI_READY_WIDTH -1 : 0] axi_ready_t; +typedef logic [AXI_LAST_WIDTH -1 : 0] axi_last_t; +typedef logic [AXI_RESP_WIDTH -1 : 0] axi_resp_t; +typedef logic [AXI_REGION_WIDTH -1 : 0] axi_region_t; + +//////////////////////////////////////// +// __ __ _ ___ ___ ___ // +// | \/ | /_\ / __| _ \/ _ \ ___ // +// | |\/| |/ _ \ (__| / (_) (_-< // +// |_| |_/_/ \_\___|_|_\\___//__/ // +// // +//////////////////////////////////////// + +//////////////////////// +// Bus Declaration // +//////////////////////// + +// Declare AXI bus specifying the DATA_WIDTH +`define DECLARE_AXI_BUS(bus_name, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + logic [ID_WIDTH-1 : 0] ``bus_name``_axi_awid; \ + logic [ADDR_WIDTH-1 : 0] ``bus_name``_axi_awaddr; \ + axi_len_t ``bus_name``_axi_awlen; \ + axi_size_t ``bus_name``_axi_awsize; \ + axi_burst_t ``bus_name``_axi_awburst; \ + axi_lock_t ``bus_name``_axi_awlock; \ + axi_cache_t ``bus_name``_axi_awcache; \ + axi_prot_t ``bus_name``_axi_awprot; \ + axi_qos_t ``bus_name``_axi_awqos; \ + axi_valid_t ``bus_name``_axi_awvalid; \ + axi_ready_t ``bus_name``_axi_awready; \ + axi_region_t ``bus_name``_axi_awregion; \ + // W channel \ + logic [DATA_WIDTH-1 : 0] ``bus_name``_axi_wdata; \ + logic [(DATA_WIDTH/8)-1 : 0] ``bus_name``_axi_wstrb; \ + axi_last_t ``bus_name``_axi_wlast; \ + axi_valid_t ``bus_name``_axi_wvalid; \ + axi_ready_t ``bus_name``_axi_wready; \ + // B channel \ + logic [ID_WIDTH-1 : 0] ``bus_name``_axi_bid; \ + axi_resp_t ``bus_name``_axi_bresp; \ + axi_valid_t ``bus_name``_axi_bvalid; \ + axi_ready_t ``bus_name``_axi_bready; \ + // AR channel \ + logic [ADDR_WIDTH-1 : 0] ``bus_name``_axi_araddr; \ + axi_len_t ``bus_name``_axi_arlen; \ + axi_size_t ``bus_name``_axi_arsize; \ + axi_burst_t ``bus_name``_axi_arburst; \ + axi_lock_t ``bus_name``_axi_arlock; \ + axi_cache_t ``bus_name``_axi_arcache; \ + axi_prot_t ``bus_name``_axi_arprot; \ + axi_qos_t ``bus_name``_axi_arqos; \ + axi_valid_t ``bus_name``_axi_arvalid; \ + axi_ready_t ``bus_name``_axi_arready; \ + logic [ID_WIDTH-1 : 0] ``bus_name``_axi_arid; \ + axi_region_t ``bus_name``_axi_arregion; \ + // R channel \ + logic [ID_WIDTH-1 : 0] ``bus_name``_axi_rid; \ + logic [DATA_WIDTH-1 : 0] ``bus_name``_axi_rdata; \ + axi_resp_t ``bus_name``_axi_rresp; \ + axi_last_t ``bus_name``_axi_rlast; \ + axi_valid_t ``bus_name``_axi_rvalid; \ + axi_ready_t ``bus_name``_axi_rready; + +// Single define for whole AXI4-LITE bus +`define DECLARE_AXILITE_BUS(bus_name, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + logic [ADDR_WIDTH-1 : 0] ``bus_name``_axilite_awaddr; \ + axi_prot_t ``bus_name``_axilite_awprot; \ + axi_valid_t ``bus_name``_axilite_awvalid; \ + axi_ready_t ``bus_name``_axilite_awready; \ + // W channel \ + logic [DATA_WIDTH-1 : 0] ``bus_name``_axilite_wdata; \ + logic [(DATA_WIDTH/8)-1 : 0] ``bus_name``_axilite_wstrb; \ + axi_valid_t ``bus_name``_axilite_wvalid; \ + axi_ready_t ``bus_name``_axilite_wready; \ + // B channel \ + axi_resp_t ``bus_name``_axilite_bresp; \ + axi_valid_t ``bus_name``_axilite_bvalid; \ + axi_ready_t ``bus_name``_axilite_bready; \ + // AR channel \ + logic [ADDR_WIDTH-1 : 0] ``bus_name``_axilite_araddr; \ + axi_prot_t ``bus_name``_axilite_arprot; \ + axi_valid_t ``bus_name``_axilite_arvalid; \ + axi_ready_t ``bus_name``_axilite_arready; \ + // R channel \ + logic [DATA_WIDTH-1 : 0] ``bus_name``_axilite_rdata; \ + axi_resp_t ``bus_name``_axilite_rresp; \ + axi_valid_t ``bus_name``_axilite_rvalid; \ + axi_ready_t ``bus_name``_axilite_rready; + +// Declare AXI array +`define DECLARE_AXI_BUS_ARRAY(array_name, size, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + logic [ID_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_awid ; \ + logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_awaddr ; \ + axi_len_t [``size`` -1 : 0] ``array_name``_axi_awlen ; \ + axi_size_t [``size`` -1 : 0] ``array_name``_axi_awsize ; \ + axi_burst_t [``size`` -1 : 0] ``array_name``_axi_awburst ; \ + axi_lock_t [``size`` -1 : 0] ``array_name``_axi_awlock ; \ + axi_cache_t [``size`` -1 : 0] ``array_name``_axi_awcache ; \ + axi_prot_t [``size`` -1 : 0] ``array_name``_axi_awprot ; \ + axi_qos_t [``size`` -1 : 0] ``array_name``_axi_awqos ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axi_awvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axi_awready ; \ + axi_region_t [``size`` -1 : 0] ``array_name``_axi_awregion ; \ + logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_wdata ; \ + logic [(DATA_WIDTH/8)-1 : 0] [``size`` -1 : 0] ``array_name``_axi_wstrb ; \ + axi_last_t [``size`` -1 : 0] ``array_name``_axi_wlast ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axi_wvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axi_wready ; \ + logic [ID_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_bid ; \ + axi_resp_t [``size`` -1 : 0] ``array_name``_axi_bresp ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axi_bvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axi_bready ; \ + logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_araddr ; \ + axi_len_t [``size`` -1 : 0] ``array_name``_axi_arlen ; \ + axi_size_t [``size`` -1 : 0] ``array_name``_axi_arsize ; \ + axi_burst_t [``size`` -1 : 0] ``array_name``_axi_arburst ; \ + axi_lock_t [``size`` -1 : 0] ``array_name``_axi_arlock ; \ + axi_cache_t [``size`` -1 : 0] ``array_name``_axi_arcache ; \ + axi_prot_t [``size`` -1 : 0] ``array_name``_axi_arprot ; \ + axi_qos_t [``size`` -1 : 0] ``array_name``_axi_arqos ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axi_arvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axi_arready ; \ + logic [ID_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_arid ; \ + axi_region_t [``size`` -1 : 0] ``array_name``_axi_arregion ; \ + logic [ID_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_rid ; \ + logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axi_rdata ; \ + axi_resp_t [``size`` -1 : 0] ``array_name``_axi_rresp ; \ + axi_last_t [``size`` -1 : 0] ``array_name``_axi_rlast ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axi_rvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axi_rready ; + +// Declare AXI4 LITE array +`define DECLARE_AXILITE_BUS_ARRAY(array_name, size, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axilite_awaddr ; \ + axi_prot_t [``size`` -1 : 0] ``array_name``_axilite_awprot ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axilite_awvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axilite_awready ; \ + logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axilite_wdata ; \ + logic [(DATA_WIDTH/8)-1 : 0] [``size`` -1 : 0] ``array_name``_axilite_wstrb ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axilite_wvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axilite_wready ; \ + axi_resp_t [``size`` -1 : 0] ``array_name``_axilite_bresp ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axilite_bvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axilite_bready ; \ + logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axilite_araddr ; \ + axi_prot_t [``size`` -1 : 0] ``array_name``_axilite_arprot ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axilite_arvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axilite_arready ; \ + logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``array_name``_axilite_rdata ; \ + axi_resp_t [``size`` -1 : 0] ``array_name``_axilite_rresp ; \ + axi_valid_t [``size`` -1 : 0] ``array_name``_axilite_rvalid ; \ + axi_ready_t [``size`` -1 : 0] ``array_name``_axilite_rready ; + +/////////////////////// +// Bus Assignment // +/////////////////////// + +// Assign srce to dest signals +`define ASSIGN_AXI_BUS(dest, src) \ + assign ``dest``_axi_awid = ``src``_axi_awid ; \ + assign ``dest``_axi_awaddr = ``src``_axi_awaddr ; \ + assign ``dest``_axi_awlen = ``src``_axi_awlen ; \ + assign ``dest``_axi_awsize = ``src``_axi_awsize ; \ + assign ``dest``_axi_awburst = ``src``_axi_awburst ; \ + assign ``dest``_axi_awlock = ``src``_axi_awlock ; \ + assign ``dest``_axi_awcache = ``src``_axi_awcache ; \ + assign ``dest``_axi_awprot = ``src``_axi_awprot ; \ + assign ``dest``_axi_awqos = ``src``_axi_awqos ; \ + assign ``dest``_axi_awvalid = ``src``_axi_awvalid ; \ + assign ``dest``_axi_awregion = ``src``_axi_awregion ; \ + assign ``dest``_axi_wdata = ``src``_axi_wdata ; \ + assign ``dest``_axi_wstrb = ``src``_axi_wstrb ; \ + assign ``dest``_axi_wlast = ``src``_axi_wlast ; \ + assign ``dest``_axi_wvalid = ``src``_axi_wvalid ; \ + assign ``dest``_axi_araddr = ``src``_axi_araddr ; \ + assign ``dest``_axi_arlen = ``src``_axi_arlen ; \ + assign ``dest``_axi_arsize = ``src``_axi_arsize ; \ + assign ``dest``_axi_arburst = ``src``_axi_arburst ; \ + assign ``dest``_axi_arlock = ``src``_axi_arlock ; \ + assign ``dest``_axi_arcache = ``src``_axi_arcache ; \ + assign ``dest``_axi_arprot = ``src``_axi_arprot ; \ + assign ``dest``_axi_arqos = ``src``_axi_arqos ; \ + assign ``dest``_axi_arvalid = ``src``_axi_arvalid ; \ + assign ``dest``_axi_arid = ``src``_axi_arid ; \ + assign ``dest``_axi_arregion = ``src``_axi_arregion ; \ + assign ``dest``_axi_rready = ``src``_axi_rready ; \ + assign ``dest``_axi_bready = ``src``_axi_bready ; \ + assign ``src``_axi_awready = ``dest``_axi_awready ; \ + assign ``src``_axi_wready = ``dest``_axi_wready ; \ + assign ``src``_axi_bid = ``dest``_axi_bid ; \ + assign ``src``_axi_bresp = ``dest``_axi_bresp ; \ + assign ``src``_axi_bvalid = ``dest``_axi_bvalid ; \ + assign ``src``_axi_arready = ``dest``_axi_arready ; \ + assign ``src``_axi_rid = ``dest``_axi_rid ; \ + assign ``src``_axi_rdata = ``dest``_axi_rdata ; \ + assign ``src``_axi_rresp = ``dest``_axi_rresp ; \ + assign ``src``_axi_rlast = ``dest``_axi_rlast ; \ + assign ``src``_axi_rvalid = ``dest``_axi_rvalid ; + +// Assign srce to dest signals AXILITE +`define ASSIGN_AXILITE_BUS(dest, src) \ + assign ``dest``_axilite_awaddr = ``src``_axilite_awaddr ; \ + assign ``dest``_axilite_awprot = ``src``_axilite_awprot ; \ + assign ``dest``_axilite_awvalid = ``src``_axilite_awvalid ; \ + assign ``dest``_axilite_wdata = ``src``_axilite_wdata ; \ + assign ``dest``_axilite_wstrb = ``src``_axilite_wstrb ; \ + assign ``dest``_axilite_wvalid = ``src``_axilite_wvalid ; \ + assign ``dest``_axilite_araddr = ``src``_axilite_araddr ; \ + assign ``dest``_axilite_arprot = ``src``_axilite_arprot ; \ + assign ``dest``_axilite_arvalid = ``src``_axilite_arvalid ; \ + assign ``dest``_axilite_rready = ``src``_axilite_rready ; \ + assign ``dest``_axilite_bready = ``src``_axilite_bready ; \ + assign ``src``_axilite_awready = ``dest``_axilite_awready ; \ + assign ``src``_axilite_wready = ``dest``_axilite_wready ; \ + assign ``src``_axilite_bresp = ``dest``_axilite_bresp ; \ + assign ``src``_axilite_bvalid = ``dest``_axilite_bvalid ; \ + assign ``src``_axilite_arready = ``dest``_axilite_arready ; \ + assign ``src``_axilite_rdata = ``dest``_axilite_rdata ; \ + assign ``src``_axilite_rresp = ``dest``_axilite_rresp ; \ + assign ``src``_axilite_rvalid = ``dest``_axilite_rvalid ; + +//////////////////////// +// Bus Concatenation // +//////////////////////// + +// NOTE: these macro are just enumerating, without variadic args +// I don't see a better way to do this, for now + +// Mock macro for one bus for compatibility +// Effectively, just renaming the signals +`define CONCAT_AXI_MASTERS_ARRAY1(array_name, bus_name0) \ + `ASSIGN_AXI_BUS(``array_name``, ``bus_name0``) + +`define CONCAT_AXI_SLAVES_ARRAY1(array_name, bus_name0) \ + `ASSIGN_AXI_BUS(``bus_name0``, ``array_name``) + +// Concatenate 2 master buses +`define CONCAT_AXI_MASTERS_ARRAY2(array_name, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 2 slave buses +`define CONCAT_AXI_SLAVES_ARRAY2(array_name, bus_name1, bus_name0) \ + assign {``bus_name1``_axi_awid , ``bus_name0``_axi_awid } = ``array_name``_axi_awid ; \ + assign {``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr } = ``array_name``_axi_awaddr ; \ + assign {``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen } = ``array_name``_axi_awlen ; \ + assign {``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize } = ``array_name``_axi_awsize ; \ + assign {``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst } = ``array_name``_axi_awburst ; \ + assign {``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock } = ``array_name``_axi_awlock ; \ + assign {``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache } = ``array_name``_axi_awcache ; \ + assign {``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot } = ``array_name``_axi_awprot ; \ + assign {``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos } = ``array_name``_axi_awqos ; \ + assign {``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid } = ``array_name``_axi_awvalid ; \ + assign {``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion } = ``array_name``_axi_awregion; \ + assign {``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata } = ``array_name``_axi_wdata ; \ + assign {``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb } = ``array_name``_axi_wstrb ; \ + assign {``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast } = ``array_name``_axi_wlast ; \ + assign {``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid } = ``array_name``_axi_wvalid ; \ + assign {``bus_name1``_axi_bready , ``bus_name0``_axi_bready } = ``array_name``_axi_bready ; \ + assign {``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr } = ``array_name``_axi_araddr ; \ + assign {``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen } = ``array_name``_axi_arlen ; \ + assign {``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize } = ``array_name``_axi_arsize ; \ + assign {``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst } = ``array_name``_axi_arburst ; \ + assign {``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock } = ``array_name``_axi_arlock ; \ + assign {``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache } = ``array_name``_axi_arcache ; \ + assign {``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot } = ``array_name``_axi_arprot ; \ + assign {``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos } = ``array_name``_axi_arqos ; \ + assign {``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid } = ``array_name``_axi_arvalid ; \ + assign {``bus_name1``_axi_arid , ``bus_name0``_axi_arid } = ``array_name``_axi_arid ; \ + assign {``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion } = ``array_name``_axi_arregion; \ + assign {``bus_name1``_axi_rready , ``bus_name0``_axi_rready } = ``array_name``_axi_rready ; \ + assign ``array_name``_axi_awready = {``bus_name1``_axi_awready , ``bus_name0``_axi_awready }; \ + assign ``array_name``_axi_wready = {``bus_name1``_axi_wready , ``bus_name0``_axi_wready }; \ + assign ``array_name``_axi_bid = {``bus_name1``_axi_bid , ``bus_name0``_axi_bid }; \ + assign ``array_name``_axi_bresp = {``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp }; \ + assign ``array_name``_axi_bvalid = {``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid }; \ + assign ``array_name``_axi_arready = {``bus_name1``_axi_arready , ``bus_name0``_axi_arready }; \ + assign ``array_name``_axi_rid = {``bus_name1``_axi_rid , ``bus_name0``_axi_rid }; \ + assign ``array_name``_axi_rdata = {``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata }; \ + assign ``array_name``_axi_rresp = {``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp }; \ + assign ``array_name``_axi_rlast = {``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast }; \ + assign ``array_name``_axi_rvalid = {``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid }; + +// Concatenate 3 master buses +`define CONCAT_AXI_MASTERS_ARRAY3(array_name, bus_name2, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 3 slave buses +`define CONCAT_AXI_SLAVES_ARRAY3(array_name, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid } = ``array_name``_axi_awid ; \ + assign {``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr } = ``array_name``_axi_awaddr ; \ + assign {``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen } = ``array_name``_axi_awlen ; \ + assign {``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize } = ``array_name``_axi_awsize ; \ + assign {``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst } = ``array_name``_axi_awburst ; \ + assign {``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock } = ``array_name``_axi_awlock ; \ + assign {``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache } = ``array_name``_axi_awcache ; \ + assign {``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot } = ``array_name``_axi_awprot ; \ + assign {``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos } = ``array_name``_axi_awqos ; \ + assign {``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid } = ``array_name``_axi_awvalid ; \ + assign {``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion } = ``array_name``_axi_awregion; \ + assign {``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata } = ``array_name``_axi_wdata ; \ + assign {``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb } = ``array_name``_axi_wstrb ; \ + assign {``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast } = ``array_name``_axi_wlast ; \ + assign {``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid } = ``array_name``_axi_wvalid ; \ + assign {``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready } = ``array_name``_axi_bready ; \ + assign {``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr } = ``array_name``_axi_araddr ; \ + assign {``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen } = ``array_name``_axi_arlen ; \ + assign {``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize } = ``array_name``_axi_arsize ; \ + assign {``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst } = ``array_name``_axi_arburst ; \ + assign {``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock } = ``array_name``_axi_arlock ; \ + assign {``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache } = ``array_name``_axi_arcache ; \ + assign {``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot } = ``array_name``_axi_arprot ; \ + assign {``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos } = ``array_name``_axi_arqos ; \ + assign {``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid } = ``array_name``_axi_arvalid ; \ + assign {``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid } = ``array_name``_axi_arid ; \ + assign {``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion } = ``array_name``_axi_arregion; \ + assign {``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready } = ``array_name``_axi_rready ; \ + assign ``array_name``_axi_awready = {``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready }; \ + assign ``array_name``_axi_wready = {``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready }; \ + assign ``array_name``_axi_bid = {``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid }; \ + assign ``array_name``_axi_bresp = {``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp }; \ + assign ``array_name``_axi_bvalid = {``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid }; \ + assign ``array_name``_axi_arready = {``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready }; \ + assign ``array_name``_axi_rid = {``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid }; \ + assign ``array_name``_axi_rdata = {``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata }; \ + assign ``array_name``_axi_rresp = {``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp }; \ + assign ``array_name``_axi_rlast = {``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast }; \ + assign ``array_name``_axi_rvalid = {``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid }; + + +// Concatenate 4 master buses +`define CONCAT_AXI_MASTERS_ARRAY4(array_name, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name3``_axi_awready , ``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name3``_axi_wready , ``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name3``_axi_bid , ``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name3``_axi_bresp , ``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name3``_axi_bvalid , ``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name3``_axi_arready , ``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name3``_axi_rid , ``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name3``_axi_rdata , ``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name3``_axi_rresp , ``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name3``_axi_rlast , ``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name3``_axi_rvalid , ``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 4 slave buses +`define CONCAT_AXI_SLAVES_ARRAY4(array_name, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name3``_axi_awid ,``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid } = ``array_name``_axi_awid ; \ + assign {``bus_name3``_axi_awaddr ,``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr } = ``array_name``_axi_awaddr ; \ + assign {``bus_name3``_axi_awlen ,``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen } = ``array_name``_axi_awlen ; \ + assign {``bus_name3``_axi_awsize ,``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize } = ``array_name``_axi_awsize ; \ + assign {``bus_name3``_axi_awburst ,``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst } = ``array_name``_axi_awburst ; \ + assign {``bus_name3``_axi_awlock ,``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock } = ``array_name``_axi_awlock ; \ + assign {``bus_name3``_axi_awcache ,``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache } = ``array_name``_axi_awcache ; \ + assign {``bus_name3``_axi_awprot ,``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot } = ``array_name``_axi_awprot ; \ + assign {``bus_name3``_axi_awqos ,``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos } = ``array_name``_axi_awqos ; \ + assign {``bus_name3``_axi_awvalid ,``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid } = ``array_name``_axi_awvalid ; \ + assign {``bus_name3``_axi_awregion ,``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion } = ``array_name``_axi_awregion; \ + assign {``bus_name3``_axi_wdata ,``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata } = ``array_name``_axi_wdata ; \ + assign {``bus_name3``_axi_wstrb ,``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb } = ``array_name``_axi_wstrb ; \ + assign {``bus_name3``_axi_wlast ,``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast } = ``array_name``_axi_wlast ; \ + assign {``bus_name3``_axi_wvalid ,``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid } = ``array_name``_axi_wvalid ; \ + assign {``bus_name3``_axi_bready ,``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready } = ``array_name``_axi_bready ; \ + assign {``bus_name3``_axi_araddr ,``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr } = ``array_name``_axi_araddr ; \ + assign {``bus_name3``_axi_arlen ,``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen } = ``array_name``_axi_arlen ; \ + assign {``bus_name3``_axi_arsize ,``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize } = ``array_name``_axi_arsize ; \ + assign {``bus_name3``_axi_arburst ,``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst } = ``array_name``_axi_arburst ; \ + assign {``bus_name3``_axi_arlock ,``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock } = ``array_name``_axi_arlock ; \ + assign {``bus_name3``_axi_arcache ,``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache } = ``array_name``_axi_arcache ; \ + assign {``bus_name3``_axi_arprot ,``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot } = ``array_name``_axi_arprot ; \ + assign {``bus_name3``_axi_arqos ,``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos } = ``array_name``_axi_arqos ; \ + assign {``bus_name3``_axi_arvalid ,``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid } = ``array_name``_axi_arvalid ; \ + assign {``bus_name3``_axi_arid ,``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid } = ``array_name``_axi_arid ; \ + assign {``bus_name3``_axi_arregion ,``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion } = ``array_name``_axi_arregion; \ + assign {``bus_name3``_axi_rready ,``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready } = ``array_name``_axi_rready ; \ + assign ``array_name``_axi_awready = {``bus_name3``_axi_awready ,``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready }; \ + assign ``array_name``_axi_wready = {``bus_name3``_axi_wready ,``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready }; \ + assign ``array_name``_axi_bid = {``bus_name3``_axi_bid ,``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid }; \ + assign ``array_name``_axi_bresp = {``bus_name3``_axi_bresp ,``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp }; \ + assign ``array_name``_axi_bvalid = {``bus_name3``_axi_bvalid ,``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid }; \ + assign ``array_name``_axi_arready = {``bus_name3``_axi_arready ,``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready }; \ + assign ``array_name``_axi_rid = {``bus_name3``_axi_rid ,``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid }; \ + assign ``array_name``_axi_rdata = {``bus_name3``_axi_rdata ,``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata }; \ + assign ``array_name``_axi_rresp = {``bus_name3``_axi_rresp ,``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp }; \ + assign ``array_name``_axi_rlast = {``bus_name3``_axi_rlast ,``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast }; \ + assign ``array_name``_axi_rvalid = {``bus_name3``_axi_rvalid ,``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid }; + +// Concatenate 5 master buses +`define CONCAT_AXI_MASTERS_ARRAY5(array_name, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name4``_axi_awid , ``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name4``_axi_awaddr , ``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name4``_axi_awlen , ``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name4``_axi_awsize , ``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name4``_axi_awburst , ``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name4``_axi_awlock , ``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name4``_axi_awcache , ``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name4``_axi_awprot , ``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name4``_axi_awqos , ``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name4``_axi_awvalid , ``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name4``_axi_awregion , ``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name4``_axi_wdata , ``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name4``_axi_wstrb , ``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name4``_axi_wlast , ``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name4``_axi_wvalid , ``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name4``_axi_bready , ``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name4``_axi_araddr , ``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name4``_axi_arlen , ``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name4``_axi_arsize , ``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name4``_axi_arburst , ``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name4``_axi_arlock , ``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name4``_axi_arcache , ``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name4``_axi_arprot , ``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name4``_axi_arqos , ``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name4``_axi_arvalid , ``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name4``_axi_arid , ``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name4``_axi_arregion , ``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name4``_axi_rready , ``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name4``_axi_awready , ``bus_name3``_axi_awready , ``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name4``_axi_wready , ``bus_name3``_axi_wready , ``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name4``_axi_bid , ``bus_name3``_axi_bid , ``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name4``_axi_bresp , ``bus_name3``_axi_bresp , ``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name4``_axi_bvalid , ``bus_name3``_axi_bvalid , ``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name4``_axi_arready , ``bus_name3``_axi_arready , ``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name4``_axi_rid , ``bus_name3``_axi_rid , ``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name4``_axi_rdata , ``bus_name3``_axi_rdata , ``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name4``_axi_rresp , ``bus_name3``_axi_rresp , ``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name4``_axi_rlast , ``bus_name3``_axi_rlast , ``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name4``_axi_rvalid , ``bus_name3``_axi_rvalid , ``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 5 slave buses +`define CONCAT_AXI_SLAVES_ARRAY5(array_name, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name4``_axi_awid ,``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid } = ``array_name``_axi_awid ; \ + assign {``bus_name4``_axi_awaddr ,``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr } = ``array_name``_axi_awaddr ; \ + assign {``bus_name4``_axi_awlen ,``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen } = ``array_name``_axi_awlen ; \ + assign {``bus_name4``_axi_awsize ,``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize } = ``array_name``_axi_awsize ; \ + assign {``bus_name4``_axi_awburst ,``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst } = ``array_name``_axi_awburst ; \ + assign {``bus_name4``_axi_awlock ,``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock } = ``array_name``_axi_awlock ; \ + assign {``bus_name4``_axi_awcache ,``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache } = ``array_name``_axi_awcache ; \ + assign {``bus_name4``_axi_awprot ,``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot } = ``array_name``_axi_awprot ; \ + assign {``bus_name4``_axi_awqos ,``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos } = ``array_name``_axi_awqos ; \ + assign {``bus_name4``_axi_awvalid ,``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid } = ``array_name``_axi_awvalid ; \ + assign {``bus_name4``_axi_awregion ,``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion } = ``array_name``_axi_awregion; \ + assign {``bus_name4``_axi_wdata ,``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata } = ``array_name``_axi_wdata ; \ + assign {``bus_name4``_axi_wstrb ,``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb } = ``array_name``_axi_wstrb ; \ + assign {``bus_name4``_axi_wlast ,``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast } = ``array_name``_axi_wlast ; \ + assign {``bus_name4``_axi_wvalid ,``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid } = ``array_name``_axi_wvalid ; \ + assign {``bus_name4``_axi_bready ,``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready } = ``array_name``_axi_bready ; \ + assign {``bus_name4``_axi_araddr ,``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr } = ``array_name``_axi_araddr ; \ + assign {``bus_name4``_axi_arlen ,``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen } = ``array_name``_axi_arlen ; \ + assign {``bus_name4``_axi_arsize ,``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize } = ``array_name``_axi_arsize ; \ + assign {``bus_name4``_axi_arburst ,``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst } = ``array_name``_axi_arburst ; \ + assign {``bus_name4``_axi_arlock ,``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock } = ``array_name``_axi_arlock ; \ + assign {``bus_name4``_axi_arcache ,``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache } = ``array_name``_axi_arcache ; \ + assign {``bus_name4``_axi_arprot ,``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot } = ``array_name``_axi_arprot ; \ + assign {``bus_name4``_axi_arqos ,``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos } = ``array_name``_axi_arqos ; \ + assign {``bus_name4``_axi_arvalid ,``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid } = ``array_name``_axi_arvalid ; \ + assign {``bus_name4``_axi_arid ,``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid } = ``array_name``_axi_arid ; \ + assign {``bus_name4``_axi_arregion ,``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion } = ``array_name``_axi_arregion; \ + assign {``bus_name4``_axi_rready ,``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready } = ``array_name``_axi_rready ; \ + assign ``array_name``_axi_awready = {``bus_name4``_axi_awready ,``bus_name3``_axi_awready ,``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready }; \ + assign ``array_name``_axi_wready = {``bus_name4``_axi_wready ,``bus_name3``_axi_wready ,``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready }; \ + assign ``array_name``_axi_bid = {``bus_name4``_axi_bid ,``bus_name3``_axi_bid ,``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid }; \ + assign ``array_name``_axi_bresp = {``bus_name4``_axi_bresp ,``bus_name3``_axi_bresp ,``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp }; \ + assign ``array_name``_axi_bvalid = {``bus_name4``_axi_bvalid ,``bus_name3``_axi_bvalid ,``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid }; \ + assign ``array_name``_axi_arready = {``bus_name4``_axi_arready ,``bus_name3``_axi_arready ,``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready }; \ + assign ``array_name``_axi_rid = {``bus_name4``_axi_rid ,``bus_name3``_axi_rid ,``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid }; \ + assign ``array_name``_axi_rdata = {``bus_name4``_axi_rdata ,``bus_name3``_axi_rdata ,``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata }; \ + assign ``array_name``_axi_rresp = {``bus_name4``_axi_rresp ,``bus_name3``_axi_rresp ,``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp }; \ + assign ``array_name``_axi_rlast = {``bus_name4``_axi_rlast ,``bus_name3``_axi_rlast ,``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast }; \ + assign ``array_name``_axi_rvalid = {``bus_name4``_axi_rvalid ,``bus_name3``_axi_rvalid ,``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid }; + +// Concatenate 6 master buses +`define CONCAT_AXI_MASTERS_ARRAY6(array_name, bus_name5, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name5``_axi_awid , ``bus_name4``_axi_awid , ``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name5``_axi_awaddr , ``bus_name4``_axi_awaddr , ``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name5``_axi_awlen , ``bus_name4``_axi_awlen , ``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name5``_axi_awsize , ``bus_name4``_axi_awsize , ``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name5``_axi_awburst , ``bus_name4``_axi_awburst , ``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name5``_axi_awlock , ``bus_name4``_axi_awlock , ``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name5``_axi_awcache , ``bus_name4``_axi_awcache , ``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name5``_axi_awprot , ``bus_name4``_axi_awprot , ``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name5``_axi_awqos , ``bus_name4``_axi_awqos , ``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name5``_axi_awvalid , ``bus_name4``_axi_awvalid , ``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name5``_axi_awregion , ``bus_name4``_axi_awregion , ``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name5``_axi_wdata , ``bus_name4``_axi_wdata , ``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name5``_axi_wstrb , ``bus_name4``_axi_wstrb , ``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name5``_axi_wlast , ``bus_name4``_axi_wlast , ``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name5``_axi_wvalid , ``bus_name4``_axi_wvalid , ``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name5``_axi_bready , ``bus_name4``_axi_bready , ``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name5``_axi_araddr , ``bus_name4``_axi_araddr , ``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name5``_axi_arlen , ``bus_name4``_axi_arlen , ``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name5``_axi_arsize , ``bus_name4``_axi_arsize , ``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name5``_axi_arburst , ``bus_name4``_axi_arburst , ``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name5``_axi_arlock , ``bus_name4``_axi_arlock , ``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name5``_axi_arcache , ``bus_name4``_axi_arcache , ``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name5``_axi_arprot , ``bus_name4``_axi_arprot , ``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name5``_axi_arqos , ``bus_name4``_axi_arqos , ``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name5``_axi_arvalid , ``bus_name4``_axi_arvalid , ``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name5``_axi_arid , ``bus_name4``_axi_arid , ``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name5``_axi_arregion , ``bus_name4``_axi_arregion , ``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name5``_axi_rready , ``bus_name4``_axi_rready , ``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name5``_axi_awready , ``bus_name4``_axi_awready , ``bus_name3``_axi_awready , ``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name5``_axi_wready , ``bus_name4``_axi_wready , ``bus_name3``_axi_wready , ``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name5``_axi_bid , ``bus_name4``_axi_bid , ``bus_name3``_axi_bid , ``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name5``_axi_bresp , ``bus_name4``_axi_bresp , ``bus_name3``_axi_bresp , ``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name5``_axi_bvalid , ``bus_name4``_axi_bvalid , ``bus_name3``_axi_bvalid , ``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name5``_axi_arready , ``bus_name4``_axi_arready , ``bus_name3``_axi_arready , ``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name5``_axi_rid , ``bus_name4``_axi_rid , ``bus_name3``_axi_rid , ``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name5``_axi_rdata , ``bus_name4``_axi_rdata , ``bus_name3``_axi_rdata , ``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name5``_axi_rresp , ``bus_name4``_axi_rresp , ``bus_name3``_axi_rresp , ``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name5``_axi_rlast , ``bus_name4``_axi_rlast , ``bus_name3``_axi_rlast , ``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name5``_axi_rvalid , ``bus_name4``_axi_rvalid , ``bus_name3``_axi_rvalid , ``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 6 slave buses +`define CONCAT_AXI_SLAVES_ARRAY6(array_name, bus_name5, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name5``_axi_awid , ``bus_name4``_axi_awid ,``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid } = ``array_name``_axi_awid ; \ + assign {``bus_name5``_axi_awaddr , ``bus_name4``_axi_awaddr ,``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr } = ``array_name``_axi_awaddr ; \ + assign {``bus_name5``_axi_awlen , ``bus_name4``_axi_awlen ,``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen } = ``array_name``_axi_awlen ; \ + assign {``bus_name5``_axi_awsize , ``bus_name4``_axi_awsize ,``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize } = ``array_name``_axi_awsize ; \ + assign {``bus_name5``_axi_awburst , ``bus_name4``_axi_awburst ,``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst } = ``array_name``_axi_awburst ; \ + assign {``bus_name5``_axi_awlock , ``bus_name4``_axi_awlock ,``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock } = ``array_name``_axi_awlock ; \ + assign {``bus_name5``_axi_awcache , ``bus_name4``_axi_awcache ,``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache } = ``array_name``_axi_awcache ; \ + assign {``bus_name5``_axi_awprot , ``bus_name4``_axi_awprot ,``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot } = ``array_name``_axi_awprot ; \ + assign {``bus_name5``_axi_awqos , ``bus_name4``_axi_awqos ,``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos } = ``array_name``_axi_awqos ; \ + assign {``bus_name5``_axi_awvalid , ``bus_name4``_axi_awvalid ,``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid } = ``array_name``_axi_awvalid ; \ + assign {``bus_name5``_axi_awregion , ``bus_name4``_axi_awregion ,``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion } = ``array_name``_axi_awregion; \ + assign {``bus_name5``_axi_wdata , ``bus_name4``_axi_wdata ,``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata } = ``array_name``_axi_wdata ; \ + assign {``bus_name5``_axi_wstrb , ``bus_name4``_axi_wstrb ,``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb } = ``array_name``_axi_wstrb ; \ + assign {``bus_name5``_axi_wlast , ``bus_name4``_axi_wlast ,``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast } = ``array_name``_axi_wlast ; \ + assign {``bus_name5``_axi_wvalid , ``bus_name4``_axi_wvalid ,``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid } = ``array_name``_axi_wvalid ; \ + assign {``bus_name5``_axi_bready , ``bus_name4``_axi_bready ,``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready } = ``array_name``_axi_bready ; \ + assign {``bus_name5``_axi_araddr , ``bus_name4``_axi_araddr ,``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr } = ``array_name``_axi_araddr ; \ + assign {``bus_name5``_axi_arlen , ``bus_name4``_axi_arlen ,``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen } = ``array_name``_axi_arlen ; \ + assign {``bus_name5``_axi_arsize , ``bus_name4``_axi_arsize ,``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize } = ``array_name``_axi_arsize ; \ + assign {``bus_name5``_axi_arburst , ``bus_name4``_axi_arburst ,``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst } = ``array_name``_axi_arburst ; \ + assign {``bus_name5``_axi_arlock , ``bus_name4``_axi_arlock ,``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock } = ``array_name``_axi_arlock ; \ + assign {``bus_name5``_axi_arcache , ``bus_name4``_axi_arcache ,``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache } = ``array_name``_axi_arcache ; \ + assign {``bus_name5``_axi_arprot , ``bus_name4``_axi_arprot ,``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot } = ``array_name``_axi_arprot ; \ + assign {``bus_name5``_axi_arqos , ``bus_name4``_axi_arqos ,``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos } = ``array_name``_axi_arqos ; \ + assign {``bus_name5``_axi_arvalid , ``bus_name4``_axi_arvalid ,``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid } = ``array_name``_axi_arvalid ; \ + assign {``bus_name5``_axi_arid , ``bus_name4``_axi_arid ,``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid } = ``array_name``_axi_arid ; \ + assign {``bus_name5``_axi_arregion , ``bus_name4``_axi_arregion ,``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion } = ``array_name``_axi_arregion; \ + assign {``bus_name5``_axi_rready , ``bus_name4``_axi_rready ,``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready } = ``array_name``_axi_rready ; \ + assign ``array_name``_axi_awready = {``bus_name5``_axi_awready ,``bus_name4``_axi_awready ,``bus_name3``_axi_awready ,``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready }; \ + assign ``array_name``_axi_wready = {``bus_name5``_axi_wready ,``bus_name4``_axi_wready ,``bus_name3``_axi_wready ,``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready }; \ + assign ``array_name``_axi_bid = {``bus_name5``_axi_bid ,``bus_name4``_axi_bid ,``bus_name3``_axi_bid ,``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid }; \ + assign ``array_name``_axi_bresp = {``bus_name5``_axi_bresp ,``bus_name4``_axi_bresp ,``bus_name3``_axi_bresp ,``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp }; \ + assign ``array_name``_axi_bvalid = {``bus_name5``_axi_bvalid ,``bus_name4``_axi_bvalid ,``bus_name3``_axi_bvalid ,``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid }; \ + assign ``array_name``_axi_arready = {``bus_name5``_axi_arready ,``bus_name4``_axi_arready ,``bus_name3``_axi_arready ,``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready }; \ + assign ``array_name``_axi_rid = {``bus_name5``_axi_rid ,``bus_name4``_axi_rid ,``bus_name3``_axi_rid ,``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid }; \ + assign ``array_name``_axi_rdata = {``bus_name5``_axi_rdata ,``bus_name4``_axi_rdata ,``bus_name3``_axi_rdata ,``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata }; \ + assign ``array_name``_axi_rresp = {``bus_name5``_axi_rresp ,``bus_name4``_axi_rresp ,``bus_name3``_axi_rresp ,``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp }; \ + assign ``array_name``_axi_rlast = {``bus_name5``_axi_rlast ,``bus_name4``_axi_rlast ,``bus_name3``_axi_rlast ,``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast }; \ + assign ``array_name``_axi_rvalid = {``bus_name5``_axi_rvalid ,``bus_name4``_axi_rvalid ,``bus_name3``_axi_rvalid ,``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid }; + +// Concatenate 7 master buses +`define CONCAT_AXI_MASTERS_ARRAY7(array_name, bus_name6, bus_name5, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name6``_axi_awid , ``bus_name5``_axi_awid , ``bus_name4``_axi_awid , ``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name6``_axi_awaddr , ``bus_name5``_axi_awaddr , ``bus_name4``_axi_awaddr , ``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name6``_axi_awlen , ``bus_name5``_axi_awlen , ``bus_name4``_axi_awlen , ``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name6``_axi_awsize , ``bus_name5``_axi_awsize , ``bus_name4``_axi_awsize , ``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name6``_axi_awburst , ``bus_name5``_axi_awburst , ``bus_name4``_axi_awburst , ``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name6``_axi_awlock , ``bus_name5``_axi_awlock , ``bus_name4``_axi_awlock , ``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name6``_axi_awcache , ``bus_name5``_axi_awcache , ``bus_name4``_axi_awcache , ``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name6``_axi_awprot , ``bus_name5``_axi_awprot , ``bus_name4``_axi_awprot , ``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name6``_axi_awqos , ``bus_name5``_axi_awqos , ``bus_name4``_axi_awqos , ``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name6``_axi_awvalid , ``bus_name5``_axi_awvalid , ``bus_name4``_axi_awvalid , ``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name6``_axi_awregion , ``bus_name5``_axi_awregion , ``bus_name4``_axi_awregion , ``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name6``_axi_wdata , ``bus_name5``_axi_wdata , ``bus_name4``_axi_wdata , ``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name6``_axi_wstrb , ``bus_name5``_axi_wstrb , ``bus_name4``_axi_wstrb , ``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name6``_axi_wlast , ``bus_name5``_axi_wlast , ``bus_name4``_axi_wlast , ``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name6``_axi_wvalid , ``bus_name5``_axi_wvalid , ``bus_name4``_axi_wvalid , ``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name6``_axi_bready , ``bus_name5``_axi_bready , ``bus_name4``_axi_bready , ``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name6``_axi_araddr , ``bus_name5``_axi_araddr , ``bus_name4``_axi_araddr , ``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name6``_axi_arlen , ``bus_name5``_axi_arlen , ``bus_name4``_axi_arlen , ``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name6``_axi_arsize , ``bus_name5``_axi_arsize , ``bus_name4``_axi_arsize , ``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name6``_axi_arburst , ``bus_name5``_axi_arburst , ``bus_name4``_axi_arburst , ``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name6``_axi_arlock , ``bus_name5``_axi_arlock , ``bus_name4``_axi_arlock , ``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name6``_axi_arcache , ``bus_name5``_axi_arcache , ``bus_name4``_axi_arcache , ``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name6``_axi_arprot , ``bus_name5``_axi_arprot , ``bus_name4``_axi_arprot , ``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name6``_axi_arqos , ``bus_name5``_axi_arqos , ``bus_name4``_axi_arqos , ``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name6``_axi_arvalid , ``bus_name5``_axi_arvalid , ``bus_name4``_axi_arvalid , ``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name6``_axi_arid , ``bus_name5``_axi_arid , ``bus_name4``_axi_arid , ``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name6``_axi_arregion , ``bus_name5``_axi_arregion , ``bus_name4``_axi_arregion , ``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name6``_axi_rready , ``bus_name5``_axi_rready , ``bus_name4``_axi_rready , ``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name6``_axi_awready , ``bus_name5``_axi_awready , ``bus_name4``_axi_awready , ``bus_name3``_axi_awready , ``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name6``_axi_wready , ``bus_name5``_axi_wready , ``bus_name4``_axi_wready , ``bus_name3``_axi_wready , ``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name6``_axi_bid , ``bus_name5``_axi_bid , ``bus_name4``_axi_bid , ``bus_name3``_axi_bid , ``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name6``_axi_bresp , ``bus_name5``_axi_bresp , ``bus_name4``_axi_bresp , ``bus_name3``_axi_bresp , ``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name6``_axi_bvalid , ``bus_name5``_axi_bvalid , ``bus_name4``_axi_bvalid , ``bus_name3``_axi_bvalid , ``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name6``_axi_arready , ``bus_name5``_axi_arready , ``bus_name4``_axi_arready , ``bus_name3``_axi_arready , ``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name6``_axi_rid , ``bus_name5``_axi_rid , ``bus_name4``_axi_rid , ``bus_name3``_axi_rid , ``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name6``_axi_rdata , ``bus_name5``_axi_rdata , ``bus_name4``_axi_rdata , ``bus_name3``_axi_rdata , ``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name6``_axi_rresp , ``bus_name5``_axi_rresp , ``bus_name4``_axi_rresp , ``bus_name3``_axi_rresp , ``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name6``_axi_rlast , ``bus_name5``_axi_rlast , ``bus_name4``_axi_rlast , ``bus_name3``_axi_rlast , ``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name6``_axi_rvalid , ``bus_name5``_axi_rvalid , ``bus_name4``_axi_rvalid , ``bus_name3``_axi_rvalid , ``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 7 slave buses +`define CONCAT_AXI_SLAVES_ARRAY7(array_name, bus_name6, bus_name5, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name6``_axi_awid , ``bus_name5``_axi_awid , ``bus_name4``_axi_awid ,``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid } = ``array_name``_axi_awid ; \ + assign {``bus_name6``_axi_awaddr , ``bus_name5``_axi_awaddr , ``bus_name4``_axi_awaddr ,``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr } = ``array_name``_axi_awaddr ; \ + assign {``bus_name6``_axi_awlen , ``bus_name5``_axi_awlen , ``bus_name4``_axi_awlen ,``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen } = ``array_name``_axi_awlen ; \ + assign {``bus_name6``_axi_awsize , ``bus_name5``_axi_awsize , ``bus_name4``_axi_awsize ,``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize } = ``array_name``_axi_awsize ; \ + assign {``bus_name6``_axi_awburst , ``bus_name5``_axi_awburst , ``bus_name4``_axi_awburst ,``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst } = ``array_name``_axi_awburst ; \ + assign {``bus_name6``_axi_awlock , ``bus_name5``_axi_awlock , ``bus_name4``_axi_awlock ,``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock } = ``array_name``_axi_awlock ; \ + assign {``bus_name6``_axi_awcache , ``bus_name5``_axi_awcache , ``bus_name4``_axi_awcache ,``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache } = ``array_name``_axi_awcache ; \ + assign {``bus_name6``_axi_awprot , ``bus_name5``_axi_awprot , ``bus_name4``_axi_awprot ,``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot } = ``array_name``_axi_awprot ; \ + assign {``bus_name6``_axi_awqos , ``bus_name5``_axi_awqos , ``bus_name4``_axi_awqos ,``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos } = ``array_name``_axi_awqos ; \ + assign {``bus_name6``_axi_awvalid , ``bus_name5``_axi_awvalid , ``bus_name4``_axi_awvalid ,``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid } = ``array_name``_axi_awvalid ; \ + assign {``bus_name6``_axi_awregion , ``bus_name5``_axi_awregion , ``bus_name4``_axi_awregion ,``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion } = ``array_name``_axi_awregion; \ + assign {``bus_name6``_axi_wdata , ``bus_name5``_axi_wdata , ``bus_name4``_axi_wdata ,``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata } = ``array_name``_axi_wdata ; \ + assign {``bus_name6``_axi_wstrb , ``bus_name5``_axi_wstrb , ``bus_name4``_axi_wstrb ,``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb } = ``array_name``_axi_wstrb ; \ + assign {``bus_name6``_axi_wlast , ``bus_name5``_axi_wlast , ``bus_name4``_axi_wlast ,``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast } = ``array_name``_axi_wlast ; \ + assign {``bus_name6``_axi_wvalid , ``bus_name5``_axi_wvalid , ``bus_name4``_axi_wvalid ,``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid } = ``array_name``_axi_wvalid ; \ + assign {``bus_name6``_axi_bready , ``bus_name5``_axi_bready , ``bus_name4``_axi_bready ,``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready } = ``array_name``_axi_bready ; \ + assign {``bus_name6``_axi_araddr , ``bus_name5``_axi_araddr , ``bus_name4``_axi_araddr ,``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr } = ``array_name``_axi_araddr ; \ + assign {``bus_name6``_axi_arlen , ``bus_name5``_axi_arlen , ``bus_name4``_axi_arlen ,``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen } = ``array_name``_axi_arlen ; \ + assign {``bus_name6``_axi_arsize , ``bus_name5``_axi_arsize , ``bus_name4``_axi_arsize ,``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize } = ``array_name``_axi_arsize ; \ + assign {``bus_name6``_axi_arburst , ``bus_name5``_axi_arburst , ``bus_name4``_axi_arburst ,``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst } = ``array_name``_axi_arburst ; \ + assign {``bus_name6``_axi_arlock , ``bus_name5``_axi_arlock , ``bus_name4``_axi_arlock ,``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock } = ``array_name``_axi_arlock ; \ + assign {``bus_name6``_axi_arcache , ``bus_name5``_axi_arcache , ``bus_name4``_axi_arcache ,``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache } = ``array_name``_axi_arcache ; \ + assign {``bus_name6``_axi_arprot , ``bus_name5``_axi_arprot , ``bus_name4``_axi_arprot ,``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot } = ``array_name``_axi_arprot ; \ + assign {``bus_name6``_axi_arqos , ``bus_name5``_axi_arqos , ``bus_name4``_axi_arqos ,``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos } = ``array_name``_axi_arqos ; \ + assign {``bus_name6``_axi_arvalid , ``bus_name5``_axi_arvalid , ``bus_name4``_axi_arvalid ,``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid } = ``array_name``_axi_arvalid ; \ + assign {``bus_name6``_axi_arid , ``bus_name5``_axi_arid , ``bus_name4``_axi_arid ,``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid } = ``array_name``_axi_arid ; \ + assign {``bus_name6``_axi_arregion , ``bus_name5``_axi_arregion , ``bus_name4``_axi_arregion ,``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion } = ``array_name``_axi_arregion; \ + assign {``bus_name6``_axi_rready , ``bus_name5``_axi_rready , ``bus_name4``_axi_rready ,``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready } = ``array_name``_axi_rready ; \ + assign ``array_name``_axi_awready = {``bus_name6``_axi_awready ,``bus_name5``_axi_awready ,``bus_name4``_axi_awready ,``bus_name3``_axi_awready ,``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready }; \ + assign ``array_name``_axi_wready = {``bus_name6``_axi_wready ,``bus_name5``_axi_wready ,``bus_name4``_axi_wready ,``bus_name3``_axi_wready ,``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready }; \ + assign ``array_name``_axi_bid = {``bus_name6``_axi_bid ,``bus_name5``_axi_bid ,``bus_name4``_axi_bid ,``bus_name3``_axi_bid ,``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid }; \ + assign ``array_name``_axi_bresp = {``bus_name6``_axi_bresp ,``bus_name5``_axi_bresp ,``bus_name4``_axi_bresp ,``bus_name3``_axi_bresp ,``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp }; \ + assign ``array_name``_axi_bvalid = {``bus_name6``_axi_bvalid ,``bus_name5``_axi_bvalid ,``bus_name4``_axi_bvalid ,``bus_name3``_axi_bvalid ,``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid }; \ + assign ``array_name``_axi_arready = {``bus_name6``_axi_arready ,``bus_name5``_axi_arready ,``bus_name4``_axi_arready ,``bus_name3``_axi_arready ,``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready }; \ + assign ``array_name``_axi_rid = {``bus_name6``_axi_rid ,``bus_name5``_axi_rid ,``bus_name4``_axi_rid ,``bus_name3``_axi_rid ,``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid }; \ + assign ``array_name``_axi_rdata = {``bus_name6``_axi_rdata ,``bus_name5``_axi_rdata ,``bus_name4``_axi_rdata ,``bus_name3``_axi_rdata ,``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata }; \ + assign ``array_name``_axi_rresp = {``bus_name6``_axi_rresp ,``bus_name5``_axi_rresp ,``bus_name4``_axi_rresp ,``bus_name3``_axi_rresp ,``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp }; \ + assign ``array_name``_axi_rlast = {``bus_name6``_axi_rlast ,``bus_name5``_axi_rlast ,``bus_name4``_axi_rlast ,``bus_name3``_axi_rlast ,``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast }; \ + assign ``array_name``_axi_rvalid = {``bus_name6``_axi_rvalid ,``bus_name5``_axi_rvalid ,``bus_name4``_axi_rvalid ,``bus_name3``_axi_rvalid ,``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid }; + +// Concatenate 8 masters buses +`define CONCAT_AXI_MASTERS_ARRAY8(array_name, bus_name7, bus_name6, bus_name5, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign ``array_name``_axi_awid = {``bus_name7``_axi_awid , ``bus_name6``_axi_awid , ``bus_name5``_axi_awid , ``bus_name4``_axi_awid , ``bus_name3``_axi_awid , ``bus_name2``_axi_awid , ``bus_name1``_axi_awid , ``bus_name0``_axi_awid }; \ + assign ``array_name``_axi_awaddr = {``bus_name7``_axi_awaddr , ``bus_name6``_axi_awaddr , ``bus_name5``_axi_awaddr , ``bus_name4``_axi_awaddr , ``bus_name3``_axi_awaddr , ``bus_name2``_axi_awaddr , ``bus_name1``_axi_awaddr , ``bus_name0``_axi_awaddr }; \ + assign ``array_name``_axi_awlen = {``bus_name7``_axi_awlen , ``bus_name6``_axi_awlen , ``bus_name5``_axi_awlen , ``bus_name4``_axi_awlen , ``bus_name3``_axi_awlen , ``bus_name2``_axi_awlen , ``bus_name1``_axi_awlen , ``bus_name0``_axi_awlen }; \ + assign ``array_name``_axi_awsize = {``bus_name7``_axi_awsize , ``bus_name6``_axi_awsize , ``bus_name5``_axi_awsize , ``bus_name4``_axi_awsize , ``bus_name3``_axi_awsize , ``bus_name2``_axi_awsize , ``bus_name1``_axi_awsize , ``bus_name0``_axi_awsize }; \ + assign ``array_name``_axi_awburst = {``bus_name7``_axi_awburst , ``bus_name6``_axi_awburst , ``bus_name5``_axi_awburst , ``bus_name4``_axi_awburst , ``bus_name3``_axi_awburst , ``bus_name2``_axi_awburst , ``bus_name1``_axi_awburst , ``bus_name0``_axi_awburst }; \ + assign ``array_name``_axi_awlock = {``bus_name7``_axi_awlock , ``bus_name6``_axi_awlock , ``bus_name5``_axi_awlock , ``bus_name4``_axi_awlock , ``bus_name3``_axi_awlock , ``bus_name2``_axi_awlock , ``bus_name1``_axi_awlock , ``bus_name0``_axi_awlock }; \ + assign ``array_name``_axi_awcache = {``bus_name7``_axi_awcache , ``bus_name6``_axi_awcache , ``bus_name5``_axi_awcache , ``bus_name4``_axi_awcache , ``bus_name3``_axi_awcache , ``bus_name2``_axi_awcache , ``bus_name1``_axi_awcache , ``bus_name0``_axi_awcache }; \ + assign ``array_name``_axi_awprot = {``bus_name7``_axi_awprot , ``bus_name6``_axi_awprot , ``bus_name5``_axi_awprot , ``bus_name4``_axi_awprot , ``bus_name3``_axi_awprot , ``bus_name2``_axi_awprot , ``bus_name1``_axi_awprot , ``bus_name0``_axi_awprot }; \ + assign ``array_name``_axi_awqos = {``bus_name7``_axi_awqos , ``bus_name6``_axi_awqos , ``bus_name5``_axi_awqos , ``bus_name4``_axi_awqos , ``bus_name3``_axi_awqos , ``bus_name2``_axi_awqos , ``bus_name1``_axi_awqos , ``bus_name0``_axi_awqos }; \ + assign ``array_name``_axi_awvalid = {``bus_name7``_axi_awvalid , ``bus_name6``_axi_awvalid , ``bus_name5``_axi_awvalid , ``bus_name4``_axi_awvalid , ``bus_name3``_axi_awvalid , ``bus_name2``_axi_awvalid , ``bus_name1``_axi_awvalid , ``bus_name0``_axi_awvalid }; \ + assign ``array_name``_axi_awregion = {``bus_name7``_axi_awregion , ``bus_name6``_axi_awregion , ``bus_name5``_axi_awregion , ``bus_name4``_axi_awregion , ``bus_name3``_axi_awregion , ``bus_name2``_axi_awregion , ``bus_name1``_axi_awregion , ``bus_name0``_axi_awregion }; \ + assign ``array_name``_axi_wdata = {``bus_name7``_axi_wdata , ``bus_name6``_axi_wdata , ``bus_name5``_axi_wdata , ``bus_name4``_axi_wdata , ``bus_name3``_axi_wdata , ``bus_name2``_axi_wdata , ``bus_name1``_axi_wdata , ``bus_name0``_axi_wdata }; \ + assign ``array_name``_axi_wstrb = {``bus_name7``_axi_wstrb , ``bus_name6``_axi_wstrb , ``bus_name5``_axi_wstrb , ``bus_name4``_axi_wstrb , ``bus_name3``_axi_wstrb , ``bus_name2``_axi_wstrb , ``bus_name1``_axi_wstrb , ``bus_name0``_axi_wstrb }; \ + assign ``array_name``_axi_wlast = {``bus_name7``_axi_wlast , ``bus_name6``_axi_wlast , ``bus_name5``_axi_wlast , ``bus_name4``_axi_wlast , ``bus_name3``_axi_wlast , ``bus_name2``_axi_wlast , ``bus_name1``_axi_wlast , ``bus_name0``_axi_wlast }; \ + assign ``array_name``_axi_wvalid = {``bus_name7``_axi_wvalid , ``bus_name6``_axi_wvalid , ``bus_name5``_axi_wvalid , ``bus_name4``_axi_wvalid , ``bus_name3``_axi_wvalid , ``bus_name2``_axi_wvalid , ``bus_name1``_axi_wvalid , ``bus_name0``_axi_wvalid }; \ + assign ``array_name``_axi_bready = {``bus_name7``_axi_bready , ``bus_name6``_axi_bready , ``bus_name5``_axi_bready , ``bus_name4``_axi_bready , ``bus_name3``_axi_bready , ``bus_name2``_axi_bready , ``bus_name1``_axi_bready , ``bus_name0``_axi_bready }; \ + assign ``array_name``_axi_araddr = {``bus_name7``_axi_araddr , ``bus_name6``_axi_araddr , ``bus_name5``_axi_araddr , ``bus_name4``_axi_araddr , ``bus_name3``_axi_araddr , ``bus_name2``_axi_araddr , ``bus_name1``_axi_araddr , ``bus_name0``_axi_araddr }; \ + assign ``array_name``_axi_arlen = {``bus_name7``_axi_arlen , ``bus_name6``_axi_arlen , ``bus_name5``_axi_arlen , ``bus_name4``_axi_arlen , ``bus_name3``_axi_arlen , ``bus_name2``_axi_arlen , ``bus_name1``_axi_arlen , ``bus_name0``_axi_arlen }; \ + assign ``array_name``_axi_arsize = {``bus_name7``_axi_arsize , ``bus_name6``_axi_arsize , ``bus_name5``_axi_arsize , ``bus_name4``_axi_arsize , ``bus_name3``_axi_arsize , ``bus_name2``_axi_arsize , ``bus_name1``_axi_arsize , ``bus_name0``_axi_arsize }; \ + assign ``array_name``_axi_arburst = {``bus_name7``_axi_arburst , ``bus_name6``_axi_arburst , ``bus_name5``_axi_arburst , ``bus_name4``_axi_arburst , ``bus_name3``_axi_arburst , ``bus_name2``_axi_arburst , ``bus_name1``_axi_arburst , ``bus_name0``_axi_arburst }; \ + assign ``array_name``_axi_arlock = {``bus_name7``_axi_arlock , ``bus_name6``_axi_arlock , ``bus_name5``_axi_arlock , ``bus_name4``_axi_arlock , ``bus_name3``_axi_arlock , ``bus_name2``_axi_arlock , ``bus_name1``_axi_arlock , ``bus_name0``_axi_arlock }; \ + assign ``array_name``_axi_arcache = {``bus_name7``_axi_arcache , ``bus_name6``_axi_arcache , ``bus_name5``_axi_arcache , ``bus_name4``_axi_arcache , ``bus_name3``_axi_arcache , ``bus_name2``_axi_arcache , ``bus_name1``_axi_arcache , ``bus_name0``_axi_arcache }; \ + assign ``array_name``_axi_arprot = {``bus_name7``_axi_arprot , ``bus_name6``_axi_arprot , ``bus_name5``_axi_arprot , ``bus_name4``_axi_arprot , ``bus_name3``_axi_arprot , ``bus_name2``_axi_arprot , ``bus_name1``_axi_arprot , ``bus_name0``_axi_arprot }; \ + assign ``array_name``_axi_arqos = {``bus_name7``_axi_arqos , ``bus_name6``_axi_arqos , ``bus_name5``_axi_arqos , ``bus_name4``_axi_arqos , ``bus_name3``_axi_arqos , ``bus_name2``_axi_arqos , ``bus_name1``_axi_arqos , ``bus_name0``_axi_arqos }; \ + assign ``array_name``_axi_arvalid = {``bus_name7``_axi_arvalid , ``bus_name6``_axi_arvalid , ``bus_name5``_axi_arvalid , ``bus_name4``_axi_arvalid , ``bus_name3``_axi_arvalid , ``bus_name2``_axi_arvalid , ``bus_name1``_axi_arvalid , ``bus_name0``_axi_arvalid }; \ + assign ``array_name``_axi_arid = {``bus_name7``_axi_arid , ``bus_name6``_axi_arid , ``bus_name5``_axi_arid , ``bus_name4``_axi_arid , ``bus_name3``_axi_arid , ``bus_name2``_axi_arid , ``bus_name1``_axi_arid , ``bus_name0``_axi_arid }; \ + assign ``array_name``_axi_arregion = {``bus_name7``_axi_arregion , ``bus_name6``_axi_arregion , ``bus_name5``_axi_arregion , ``bus_name4``_axi_arregion , ``bus_name3``_axi_arregion , ``bus_name2``_axi_arregion , ``bus_name1``_axi_arregion , ``bus_name0``_axi_arregion }; \ + assign ``array_name``_axi_rready = {``bus_name7``_axi_rready , ``bus_name6``_axi_rready , ``bus_name5``_axi_rready , ``bus_name4``_axi_rready , ``bus_name3``_axi_rready , ``bus_name2``_axi_rready , ``bus_name1``_axi_rready , ``bus_name0``_axi_rready }; \ + assign {``bus_name7``_axi_awready , ``bus_name6``_axi_awready , ``bus_name5``_axi_awready , ``bus_name4``_axi_awready , ``bus_name3``_axi_awready , ``bus_name2``_axi_awready , ``bus_name1``_axi_awready , ``bus_name0``_axi_awready } = ``array_name``_axi_awready ; \ + assign {``bus_name7``_axi_wready , ``bus_name6``_axi_wready , ``bus_name5``_axi_wready , ``bus_name4``_axi_wready , ``bus_name3``_axi_wready , ``bus_name2``_axi_wready , ``bus_name1``_axi_wready , ``bus_name0``_axi_wready } = ``array_name``_axi_wready ; \ + assign {``bus_name7``_axi_bid , ``bus_name6``_axi_bid , ``bus_name5``_axi_bid , ``bus_name4``_axi_bid , ``bus_name3``_axi_bid , ``bus_name2``_axi_bid , ``bus_name1``_axi_bid , ``bus_name0``_axi_bid } = ``array_name``_axi_bid ; \ + assign {``bus_name7``_axi_bresp , ``bus_name6``_axi_bresp , ``bus_name5``_axi_bresp , ``bus_name4``_axi_bresp , ``bus_name3``_axi_bresp , ``bus_name2``_axi_bresp , ``bus_name1``_axi_bresp , ``bus_name0``_axi_bresp } = ``array_name``_axi_bresp ; \ + assign {``bus_name7``_axi_bvalid , ``bus_name6``_axi_bvalid , ``bus_name5``_axi_bvalid , ``bus_name4``_axi_bvalid , ``bus_name3``_axi_bvalid , ``bus_name2``_axi_bvalid , ``bus_name1``_axi_bvalid , ``bus_name0``_axi_bvalid } = ``array_name``_axi_bvalid ; \ + assign {``bus_name7``_axi_arready , ``bus_name6``_axi_arready , ``bus_name5``_axi_arready , ``bus_name4``_axi_arready , ``bus_name3``_axi_arready , ``bus_name2``_axi_arready , ``bus_name1``_axi_arready , ``bus_name0``_axi_arready } = ``array_name``_axi_arready ; \ + assign {``bus_name7``_axi_rid , ``bus_name6``_axi_rid , ``bus_name5``_axi_rid , ``bus_name4``_axi_rid , ``bus_name3``_axi_rid , ``bus_name2``_axi_rid , ``bus_name1``_axi_rid , ``bus_name0``_axi_rid } = ``array_name``_axi_rid ; \ + assign {``bus_name7``_axi_rdata , ``bus_name6``_axi_rdata , ``bus_name5``_axi_rdata , ``bus_name4``_axi_rdata , ``bus_name3``_axi_rdata , ``bus_name2``_axi_rdata , ``bus_name1``_axi_rdata , ``bus_name0``_axi_rdata } = ``array_name``_axi_rdata ; \ + assign {``bus_name7``_axi_rresp , ``bus_name6``_axi_rresp , ``bus_name5``_axi_rresp , ``bus_name4``_axi_rresp , ``bus_name3``_axi_rresp , ``bus_name2``_axi_rresp , ``bus_name1``_axi_rresp , ``bus_name0``_axi_rresp } = ``array_name``_axi_rresp ; \ + assign {``bus_name7``_axi_rlast , ``bus_name6``_axi_rlast , ``bus_name5``_axi_rlast , ``bus_name4``_axi_rlast , ``bus_name3``_axi_rlast , ``bus_name2``_axi_rlast , ``bus_name1``_axi_rlast , ``bus_name0``_axi_rlast } = ``array_name``_axi_rlast ; \ + assign {``bus_name7``_axi_rvalid , ``bus_name6``_axi_rvalid , ``bus_name5``_axi_rvalid , ``bus_name4``_axi_rvalid , ``bus_name3``_axi_rvalid , ``bus_name2``_axi_rvalid , ``bus_name1``_axi_rvalid , ``bus_name0``_axi_rvalid } = ``array_name``_axi_rvalid ; + +// Concatenate 8 slave buses +`define CONCAT_AXI_SLAVES_ARRAY8(array_name, bus_name7, bus_name6, bus_name5, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name7``_axi_awid, ``bus_name6``_axi_awid, ``bus_name5``_axi_awid, ``bus_name4``_axi_awid, ``bus_name3``_axi_awid, ``bus_name2``_axi_awid, ``bus_name1``_axi_awid, ``bus_name0``_axi_awid} = ``array_name``_axi_awid; \ + assign {``bus_name7``_axi_awaddr, ``bus_name6``_axi_awaddr, ``bus_name5``_axi_awaddr, ``bus_name4``_axi_awaddr, ``bus_name3``_axi_awaddr, ``bus_name2``_axi_awaddr, ``bus_name1``_axi_awaddr, ``bus_name0``_axi_awaddr} = ``array_name``_axi_awaddr; \ + assign {``bus_name7``_axi_awlen, ``bus_name6``_axi_awlen, ``bus_name5``_axi_awlen, ``bus_name4``_axi_awlen, ``bus_name3``_axi_awlen, ``bus_name2``_axi_awlen, ``bus_name1``_axi_awlen, ``bus_name0``_axi_awlen} = ``array_name``_axi_awlen; \ + assign {``bus_name7``_axi_awsize, ``bus_name6``_axi_awsize, ``bus_name5``_axi_awsize, ``bus_name4``_axi_awsize, ``bus_name3``_axi_awsize, ``bus_name2``_axi_awsize, ``bus_name1``_axi_awsize, ``bus_name0``_axi_awsize} = ``array_name``_axi_awsize; \ + assign {``bus_name7``_axi_awburst, ``bus_name6``_axi_awburst, ``bus_name5``_axi_awburst, ``bus_name4``_axi_awburst, ``bus_name3``_axi_awburst, ``bus_name2``_axi_awburst, ``bus_name1``_axi_awburst, ``bus_name0``_axi_awburst} = ``array_name``_axi_awburst; \ + assign {``bus_name7``_axi_awlock, ``bus_name6``_axi_awlock, ``bus_name5``_axi_awlock, ``bus_name4``_axi_awlock, ``bus_name3``_axi_awlock, ``bus_name2``_axi_awlock, ``bus_name1``_axi_awlock, ``bus_name0``_axi_awlock} = ``array_name``_axi_awlock; \ + assign {``bus_name7``_axi_awcache, ``bus_name6``_axi_awcache, ``bus_name5``_axi_awcache, ``bus_name4``_axi_awcache, ``bus_name3``_axi_awcache, ``bus_name2``_axi_awcache, ``bus_name1``_axi_awcache, ``bus_name0``_axi_awcache} = ``array_name``_axi_awcache; \ + assign {``bus_name7``_axi_awprot, ``bus_name6``_axi_awprot, ``bus_name5``_axi_awprot, ``bus_name4``_axi_awprot, ``bus_name3``_axi_awprot, ``bus_name2``_axi_awprot, ``bus_name1``_axi_awprot, ``bus_name0``_axi_awprot} = ``array_name``_axi_awprot; \ + assign {``bus_name7``_axi_awqos, ``bus_name6``_axi_awqos, ``bus_name5``_axi_awqos, ``bus_name4``_axi_awqos, ``bus_name3``_axi_awqos, ``bus_name2``_axi_awqos, ``bus_name1``_axi_awqos, ``bus_name0``_axi_awqos} = ``array_name``_axi_awqos; \ + assign {``bus_name7``_axi_awvalid, ``bus_name6``_axi_awvalid, ``bus_name5``_axi_awvalid, ``bus_name4``_axi_awvalid, ``bus_name3``_axi_awvalid, ``bus_name2``_axi_awvalid, ``bus_name1``_axi_awvalid, ``bus_name0``_axi_awvalid} = ``array_name``_axi_awvalid; \ + assign {``bus_name7``_axi_awregion, ``bus_name6``_axi_awregion, ``bus_name5``_axi_awregion, ``bus_name4``_axi_awregion, ``bus_name3``_axi_awregion, ``bus_name2``_axi_awregion, ``bus_name1``_axi_awregion, ``bus_name0``_axi_awregion} = ``array_name``_axi_awregion; \ + assign {``bus_name7``_axi_wdata, ``bus_name6``_axi_wdata, ``bus_name5``_axi_wdata, ``bus_name4``_axi_wdata, ``bus_name3``_axi_wdata, ``bus_name2``_axi_wdata, ``bus_name1``_axi_wdata, ``bus_name0``_axi_wdata} = ``array_name``_axi_wdata; \ + assign {``bus_name7``_axi_wstrb, ``bus_name6``_axi_wstrb, ``bus_name5``_axi_wstrb, ``bus_name4``_axi_wstrb, ``bus_name3``_axi_wstrb, ``bus_name2``_axi_wstrb, ``bus_name1``_axi_wstrb, ``bus_name0``_axi_wstrb} = ``array_name``_axi_wstrb; \ + assign {``bus_name7``_axi_wlast, ``bus_name6``_axi_wlast, ``bus_name5``_axi_wlast, ``bus_name4``_axi_wlast, ``bus_name3``_axi_wlast, ``bus_name2``_axi_wlast, ``bus_name1``_axi_wlast, ``bus_name0``_axi_wlast} = ``array_name``_axi_wlast; \ + assign {``bus_name7``_axi_wvalid, ``bus_name6``_axi_wvalid, ``bus_name5``_axi_wvalid, ``bus_name4``_axi_wvalid, ``bus_name3``_axi_wvalid, ``bus_name2``_axi_wvalid, ``bus_name1``_axi_wvalid, ``bus_name0``_axi_wvalid} = ``array_name``_axi_wvalid; \ + assign {``bus_name7``_axi_bready, ``bus_name6``_axi_bready, ``bus_name5``_axi_bready, ``bus_name4``_axi_bready, ``bus_name3``_axi_bready, ``bus_name2``_axi_bready, ``bus_name1``_axi_bready, ``bus_name0``_axi_bready} = ``array_name``_axi_bready; \ + assign {``bus_name7``_axi_araddr, ``bus_name6``_axi_araddr, ``bus_name5``_axi_araddr, ``bus_name4``_axi_araddr, ``bus_name3``_axi_araddr, ``bus_name2``_axi_araddr, ``bus_name1``_axi_araddr, ``bus_name0``_axi_araddr} = ``array_name``_axi_araddr; \ + assign {``bus_name7``_axi_arlen, ``bus_name6``_axi_arlen, ``bus_name5``_axi_arlen, ``bus_name4``_axi_arlen, ``bus_name3``_axi_arlen, ``bus_name2``_axi_arlen, ``bus_name1``_axi_arlen, ``bus_name0``_axi_arlen} = ``array_name``_axi_arlen; \ + assign {``bus_name7``_axi_arsize, ``bus_name6``_axi_arsize, ``bus_name5``_axi_arsize, ``bus_name4``_axi_arsize, ``bus_name3``_axi_arsize, ``bus_name2``_axi_arsize, ``bus_name1``_axi_arsize, ``bus_name0``_axi_arsize} = ``array_name``_axi_arsize; \ + assign {``bus_name7``_axi_arburst, ``bus_name6``_axi_arburst, ``bus_name5``_axi_arburst, ``bus_name4``_axi_arburst, ``bus_name3``_axi_arburst, ``bus_name2``_axi_arburst, ``bus_name1``_axi_arburst, ``bus_name0``_axi_arburst} = ``array_name``_axi_arburst; \ + assign {``bus_name7``_axi_arlock, ``bus_name6``_axi_arlock, ``bus_name5``_axi_arlock, ``bus_name4``_axi_arlock, ``bus_name3``_axi_arlock, ``bus_name2``_axi_arlock, ``bus_name1``_axi_arlock, ``bus_name0``_axi_arlock} = ``array_name``_axi_arlock; \ + assign {``bus_name7``_axi_arcache, ``bus_name6``_axi_arcache, ``bus_name5``_axi_arcache, ``bus_name4``_axi_arcache, ``bus_name3``_axi_arcache, ``bus_name2``_axi_arcache, ``bus_name1``_axi_arcache, ``bus_name0``_axi_arcache} = ``array_name``_axi_arcache; \ + assign {``bus_name7``_axi_arprot, ``bus_name6``_axi_arprot, ``bus_name5``_axi_arprot, ``bus_name4``_axi_arprot, ``bus_name3``_axi_arprot, ``bus_name2``_axi_arprot, ``bus_name1``_axi_arprot, ``bus_name0``_axi_arprot} = ``array_name``_axi_arprot; \ + assign {``bus_name7``_axi_arqos, ``bus_name6``_axi_arqos, ``bus_name5``_axi_arqos, ``bus_name4``_axi_arqos, ``bus_name3``_axi_arqos, ``bus_name2``_axi_arqos, ``bus_name1``_axi_arqos, ``bus_name0``_axi_arqos} = ``array_name``_axi_arqos; \ + assign {``bus_name7``_axi_arvalid, ``bus_name6``_axi_arvalid, ``bus_name5``_axi_arvalid, ``bus_name4``_axi_arvalid, ``bus_name3``_axi_arvalid, ``bus_name2``_axi_arvalid, ``bus_name1``_axi_arvalid, ``bus_name0``_axi_arvalid} = ``array_name``_axi_arvalid; \ + assign {``bus_name7``_axi_arid, ``bus_name6``_axi_arid, ``bus_name5``_axi_arid, ``bus_name4``_axi_arid, ``bus_name3``_axi_arid, ``bus_name2``_axi_arid, ``bus_name1``_axi_arid, ``bus_name0``_axi_arid} = ``array_name``_axi_arid; \ + assign {``bus_name7``_axi_arregion, ``bus_name6``_axi_arregion, ``bus_name5``_axi_arregion, ``bus_name4``_axi_arregion, ``bus_name3``_axi_arregion, ``bus_name2``_axi_arregion, ``bus_name1``_axi_arregion, ``bus_name0``_axi_arregion} = ``array_name``_axi_arregion; \ + assign {``bus_name7``_axi_rready, ``bus_name6``_axi_rready, ``bus_name5``_axi_rready, ``bus_name4``_axi_rready, ``bus_name3``_axi_rready, ``bus_name2``_axi_rready, ``bus_name1``_axi_rready, ``bus_name0``_axi_rready} = ``array_name``_axi_rready; \ + assign ``array_name``_axi_awready = {``bus_name7``_axi_awready, ``bus_name6``_axi_awready, ``bus_name5``_axi_awready, ``bus_name4``_axi_awready, ``bus_name3``_axi_awready, ``bus_name2``_axi_awready, ``bus_name1``_axi_awready, ``bus_name0``_axi_awready}; \ + assign ``array_name``_axi_wready = {``bus_name7``_axi_wready, ``bus_name6``_axi_wready, ``bus_name5``_axi_wready, ``bus_name4``_axi_wready, ``bus_name3``_axi_wready, ``bus_name2``_axi_wready, ``bus_name1``_axi_wready, ``bus_name0``_axi_wready}; \ + assign ``array_name``_axi_bid = {``bus_name7``_axi_bid, ``bus_name6``_axi_bid, ``bus_name5``_axi_bid, ``bus_name4``_axi_bid, ``bus_name3``_axi_bid, ``bus_name2``_axi_bid, ``bus_name1``_axi_bid, ``bus_name0``_axi_bid}; \ + assign ``array_name``_axi_bresp = {``bus_name7``_axi_bresp, ``bus_name6``_axi_bresp, ``bus_name5``_axi_bresp, ``bus_name4``_axi_bresp, ``bus_name3``_axi_bresp, ``bus_name2``_axi_bresp, ``bus_name1``_axi_bresp, ``bus_name0``_axi_bresp}; \ + assign ``array_name``_axi_bvalid = {``bus_name7``_axi_bvalid, ``bus_name6``_axi_bvalid, ``bus_name5``_axi_bvalid, ``bus_name4``_axi_bvalid, ``bus_name3``_axi_bvalid, ``bus_name2``_axi_bvalid, ``bus_name1``_axi_bvalid, ``bus_name0``_axi_bvalid}; \ + assign ``array_name``_axi_arready = {``bus_name7``_axi_arready, ``bus_name6``_axi_arready, ``bus_name5``_axi_arready, ``bus_name4``_axi_arready, ``bus_name3``_axi_arready, ``bus_name2``_axi_arready, ``bus_name1``_axi_arready, ``bus_name0``_axi_arready}; \ + assign ``array_name``_axi_rid = {``bus_name7``_axi_rid, ``bus_name6``_axi_rid, ``bus_name5``_axi_rid, ``bus_name4``_axi_rid, ``bus_name3``_axi_rid, ``bus_name2``_axi_rid, ``bus_name1``_axi_rid, ``bus_name0``_axi_rid}; \ + assign ``array_name``_axi_rdata = {``bus_name7``_axi_rdata, ``bus_name6``_axi_rdata, ``bus_name5``_axi_rdata, ``bus_name4``_axi_rdata, ``bus_name3``_axi_rdata, ``bus_name2``_axi_rdata, ``bus_name1``_axi_rdata, ``bus_name0``_axi_rdata}; \ + assign ``array_name``_axi_rresp = {``bus_name7``_axi_rresp, ``bus_name6``_axi_rresp, ``bus_name5``_axi_rresp, ``bus_name4``_axi_rresp, ``bus_name3``_axi_rresp, ``bus_name2``_axi_rresp, ``bus_name1``_axi_rresp, ``bus_name0``_axi_rresp}; \ + assign ``array_name``_axi_rlast = {``bus_name7``_axi_rlast, ``bus_name6``_axi_rlast, ``bus_name5``_axi_rlast, ``bus_name4``_axi_rlast, ``bus_name3``_axi_rlast, ``bus_name2``_axi_rlast, ``bus_name1``_axi_rlast, ``bus_name0``_axi_rlast}; \ + assign ``array_name``_axi_rvalid = {``bus_name7``_axi_rvalid, ``bus_name6``_axi_rvalid, ``bus_name5``_axi_rvalid, ``bus_name4``_axi_rvalid, ``bus_name3``_axi_rvalid, ``bus_name2``_axi_rvalid, ``bus_name1``_axi_rvalid, ``bus_name0``_axi_rvalid}; + + +// Concatenate 1 master axilite buses +`define CONCAT_AXILITE_MASTERS_ARRAY1(array_name, bus_name0) \ + `ASSIGN_AXILITE_BUS(``array_name``, ``bus_name0``) + +// Concatenate 2 master axilite buses +`define CONCAT_AXILITE_MASTERS_ARRAY2(array_name, bus_name1, bus_name0) \ + assign ``array_name``_axilite_awaddr = {``bus_name1``_axilite_awaddr , ``bus_name0``_axilite_awaddr }; \ + assign ``array_name``_axilite_awprot = {``bus_name1``_axilite_awprot , ``bus_name0``_axilite_awprot }; \ + assign ``array_name``_axilite_awvalid = {``bus_name1``_axilite_awvalid , ``bus_name0``_axilite_awvalid }; \ + assign ``array_name``_axilite_wdata = {``bus_name1``_axilite_wdata , ``bus_name0``_axilite_wdata }; \ + assign ``array_name``_axilite_wstrb = {``bus_name1``_axilite_wstrb , ``bus_name0``_axilite_wstrb }; \ + assign ``array_name``_axilite_wvalid = {``bus_name1``_axilite_wvalid , ``bus_name0``_axilite_wvalid }; \ + assign ``array_name``_axilite_bready = {``bus_name1``_axilite_bready , ``bus_name0``_axilite_bready }; \ + assign ``array_name``_axilite_araddr = {``bus_name1``_axilite_araddr , ``bus_name0``_axilite_araddr }; \ + assign ``array_name``_axilite_arprot = {``bus_name1``_axilite_arprot , ``bus_name0``_axilite_arprot }; \ + assign ``array_name``_axilite_arvalid = {``bus_name1``_axilite_arvalid , ``bus_name0``_axilite_arvalid }; \ + assign ``array_name``_axilite_rready = {``bus_name1``_axilite_rready , ``bus_name0``_axilite_rready }; \ + assign {``bus_name1``_axilite_awready , ``bus_name0``_axilite_awready } = ``array_name``_axilite_awready ; \ + assign {``bus_name1``_axilite_wready , ``bus_name0``_axilite_wready } = ``array_name``_axilite_wready ; \ + assign {``bus_name1``_axilite_bresp , ``bus_name0``_axilite_bresp } = ``array_name``_axilite_bresp ; \ + assign {``bus_name1``_axilite_bvalid , ``bus_name0``_axilite_bvalid } = ``array_name``_axilite_bvalid ; \ + assign {``bus_name1``_axilite_arready , ``bus_name0``_axilite_arready } = ``array_name``_axilite_arready ; \ + assign {``bus_name1``_axilite_rdata , ``bus_name0``_axilite_rdata } = ``array_name``_axilite_rdata ; \ + assign {``bus_name1``_axilite_rresp , ``bus_name0``_axilite_rresp } = ``array_name``_axilite_rresp ; \ + assign {``bus_name1``_axilite_rvalid , ``bus_name0``_axilite_rvalid } = ``array_name``_axilite_rvalid ; + +// Concatenate 2 slave axilite buses +`define CONCAT_AXILITE_SLAVES_ARRAY2(array_name, bus_name1, bus_name0) \ + assign {``bus_name1``_axilite_awaddr , ``bus_name0``_axilite_awaddr } = ``array_name``_axilite_awaddr ; \ + assign {``bus_name1``_axilite_awprot , ``bus_name0``_axilite_awprot } = ``array_name``_axilite_awprot ; \ + assign {``bus_name1``_axilite_awvalid , ``bus_name0``_axilite_awvalid } = ``array_name``_axilite_awvalid ; \ + assign {``bus_name1``_axilite_wdata , ``bus_name0``_axilite_wdata } = ``array_name``_axilite_wdata ; \ + assign {``bus_name1``_axilite_wstrb , ``bus_name0``_axilite_wstrb } = ``array_name``_axilite_wstrb ; \ + assign {``bus_name1``_axilite_wvalid , ``bus_name0``_axilite_wvalid } = ``array_name``_axilite_wvalid ; \ + assign {``bus_name1``_axilite_bready , ``bus_name0``_axilite_bready } = ``array_name``_axilite_bready ; \ + assign {``bus_name1``_axilite_araddr , ``bus_name0``_axilite_araddr } = ``array_name``_axilite_araddr ; \ + assign {``bus_name1``_axilite_arprot , ``bus_name0``_axilite_arprot } = ``array_name``_axilite_arprot ; \ + assign {``bus_name1``_axilite_arvalid , ``bus_name0``_axilite_arvalid } = ``array_name``_axilite_arvalid ; \ + assign {``bus_name1``_axilite_rready , ``bus_name0``_axilite_rready } = ``array_name``_axilite_rready ; \ + assign ``array_name``_axilite_awready = {``bus_name1``_axilite_awready , ``bus_name0``_axilite_awready }; \ + assign ``array_name``_axilite_wready = {``bus_name1``_axilite_wready , ``bus_name0``_axilite_wready }; \ + assign ``array_name``_axilite_bresp = {``bus_name1``_axilite_bresp , ``bus_name0``_axilite_bresp }; \ + assign ``array_name``_axilite_bvalid = {``bus_name1``_axilite_bvalid , ``bus_name0``_axilite_bvalid }; \ + assign ``array_name``_axilite_arready = {``bus_name1``_axilite_arready , ``bus_name0``_axilite_arready }; \ + assign ``array_name``_axilite_rdata = {``bus_name1``_axilite_rdata , ``bus_name0``_axilite_rdata }; \ + assign ``array_name``_axilite_rresp = {``bus_name1``_axilite_rresp , ``bus_name0``_axilite_rresp }; \ + assign ``array_name``_axilite_rvalid = {``bus_name1``_axilite_rvalid , ``bus_name0``_axilite_rvalid }; + +// Concatenate 3 slave axilite buses +`define CONCAT_AXILITE_SLAVES_ARRAY3(array_name, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name2``_axilite_awaddr , ``bus_name1``_axilite_awaddr , ``bus_name0``_axilite_awaddr } = ``array_name``_axilite_awaddr ; \ + assign {``bus_name2``_axilite_awprot , ``bus_name1``_axilite_awprot , ``bus_name0``_axilite_awprot } = ``array_name``_axilite_awprot ; \ + assign {``bus_name2``_axilite_awvalid , ``bus_name1``_axilite_awvalid , ``bus_name0``_axilite_awvalid } = ``array_name``_axilite_awvalid ; \ + assign {``bus_name2``_axilite_wdata , ``bus_name1``_axilite_wdata , ``bus_name0``_axilite_wdata } = ``array_name``_axilite_wdata ; \ + assign {``bus_name2``_axilite_wstrb , ``bus_name1``_axilite_wstrb , ``bus_name0``_axilite_wstrb } = ``array_name``_axilite_wstrb ; \ + assign {``bus_name2``_axilite_wvalid , ``bus_name1``_axilite_wvalid , ``bus_name0``_axilite_wvalid } = ``array_name``_axilite_wvalid ; \ + assign {``bus_name2``_axilite_bready , ``bus_name1``_axilite_bready , ``bus_name0``_axilite_bready } = ``array_name``_axilite_bready ; \ + assign {``bus_name2``_axilite_araddr , ``bus_name1``_axilite_araddr , ``bus_name0``_axilite_araddr } = ``array_name``_axilite_araddr ; \ + assign {``bus_name2``_axilite_arprot , ``bus_name1``_axilite_arprot , ``bus_name0``_axilite_arprot } = ``array_name``_axilite_arprot ; \ + assign {``bus_name2``_axilite_arvalid , ``bus_name1``_axilite_arvalid , ``bus_name0``_axilite_arvalid } = ``array_name``_axilite_arvalid ; \ + assign {``bus_name2``_axilite_rready , ``bus_name1``_axilite_rready , ``bus_name0``_axilite_rready } = ``array_name``_axilite_rready ; \ + assign ``array_name``_axilite_awready = {``bus_name2``_axilite_awready , ``bus_name1``_axilite_awready , ``bus_name0``_axilite_awready }; \ + assign ``array_name``_axilite_wready = {``bus_name2``_axilite_wready , ``bus_name1``_axilite_wready , ``bus_name0``_axilite_wready }; \ + assign ``array_name``_axilite_bresp = {``bus_name2``_axilite_bresp , ``bus_name1``_axilite_bresp , ``bus_name0``_axilite_bresp }; \ + assign ``array_name``_axilite_bvalid = {``bus_name2``_axilite_bvalid , ``bus_name1``_axilite_bvalid , ``bus_name0``_axilite_bvalid }; \ + assign ``array_name``_axilite_arready = {``bus_name2``_axilite_arready , ``bus_name1``_axilite_arready , ``bus_name0``_axilite_arready }; \ + assign ``array_name``_axilite_rdata = {``bus_name2``_axilite_rdata , ``bus_name1``_axilite_rdata , ``bus_name0``_axilite_rdata }; \ + assign ``array_name``_axilite_rresp = {``bus_name2``_axilite_rresp , ``bus_name1``_axilite_rresp , ``bus_name0``_axilite_rresp }; \ + assign ``array_name``_axilite_rvalid = {``bus_name2``_axilite_rvalid , ``bus_name1``_axilite_rvalid , ``bus_name0``_axilite_rvalid }; + +// Concatenate 4 slave axilite buses +`define CONCAT_AXILITE_SLAVES_ARRAY4(array_name, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name3``_axilite_awaddr , ``bus_name2``_axilite_awaddr , ``bus_name1``_axilite_awaddr , ``bus_name0``_axilite_awaddr } = ``array_name``_axilite_awaddr ; \ + assign {``bus_name3``_axilite_awprot , ``bus_name2``_axilite_awprot , ``bus_name1``_axilite_awprot , ``bus_name0``_axilite_awprot } = ``array_name``_axilite_awprot ; \ + assign {``bus_name3``_axilite_awvalid , ``bus_name2``_axilite_awvalid , ``bus_name1``_axilite_awvalid , ``bus_name0``_axilite_awvalid } = ``array_name``_axilite_awvalid ; \ + assign {``bus_name3``_axilite_wdata , ``bus_name2``_axilite_wdata , ``bus_name1``_axilite_wdata , ``bus_name0``_axilite_wdata } = ``array_name``_axilite_wdata ; \ + assign {``bus_name3``_axilite_wstrb , ``bus_name2``_axilite_wstrb , ``bus_name1``_axilite_wstrb , ``bus_name0``_axilite_wstrb } = ``array_name``_axilite_wstrb ; \ + assign {``bus_name3``_axilite_wvalid , ``bus_name2``_axilite_wvalid , ``bus_name1``_axilite_wvalid , ``bus_name0``_axilite_wvalid } = ``array_name``_axilite_wvalid ; \ + assign {``bus_name3``_axilite_bready , ``bus_name2``_axilite_bready , ``bus_name1``_axilite_bready , ``bus_name0``_axilite_bready } = ``array_name``_axilite_bready ; \ + assign {``bus_name3``_axilite_araddr , ``bus_name2``_axilite_araddr , ``bus_name1``_axilite_araddr , ``bus_name0``_axilite_araddr } = ``array_name``_axilite_araddr ; \ + assign {``bus_name3``_axilite_arprot , ``bus_name2``_axilite_arprot , ``bus_name1``_axilite_arprot , ``bus_name0``_axilite_arprot } = ``array_name``_axilite_arprot ; \ + assign {``bus_name3``_axilite_arvalid , ``bus_name2``_axilite_arvalid , ``bus_name1``_axilite_arvalid , ``bus_name0``_axilite_arvalid } = ``array_name``_axilite_arvalid ; \ + assign {``bus_name3``_axilite_rready , ``bus_name2``_axilite_rready , ``bus_name1``_axilite_rready , ``bus_name0``_axilite_rready } = ``array_name``_axilite_rready ; \ + assign ``array_name``_axilite_awready = {``bus_name3``_axilite_awready , ``bus_name2``_axilite_awready , ``bus_name1``_axilite_awready , ``bus_name0``_axilite_awready }; \ + assign ``array_name``_axilite_wready = {``bus_name3``_axilite_wready , ``bus_name2``_axilite_wready , ``bus_name1``_axilite_wready , ``bus_name0``_axilite_wready }; \ + assign ``array_name``_axilite_bresp = {``bus_name3``_axilite_bresp , ``bus_name2``_axilite_bresp , ``bus_name1``_axilite_bresp , ``bus_name0``_axilite_bresp }; \ + assign ``array_name``_axilite_bvalid = {``bus_name3``_axilite_bvalid , ``bus_name2``_axilite_bvalid , ``bus_name1``_axilite_bvalid , ``bus_name0``_axilite_bvalid }; \ + assign ``array_name``_axilite_arready = {``bus_name3``_axilite_arready , ``bus_name2``_axilite_arready , ``bus_name1``_axilite_arready , ``bus_name0``_axilite_arready }; \ + assign ``array_name``_axilite_rdata = {``bus_name3``_axilite_rdata , ``bus_name2``_axilite_rdata , ``bus_name1``_axilite_rdata , ``bus_name0``_axilite_rdata }; \ + assign ``array_name``_axilite_rresp = {``bus_name3``_axilite_rresp , ``bus_name2``_axilite_rresp , ``bus_name1``_axilite_rresp , ``bus_name0``_axilite_rresp }; \ + assign ``array_name``_axilite_rvalid = {``bus_name3``_axilite_rvalid , ``bus_name2``_axilite_rvalid , ``bus_name1``_axilite_rvalid , ``bus_name0``_axilite_rvalid }; + +// Concatenate 5 slave axilite buses +`define CONCAT_AXILITE_SLAVES_ARRAY5(array_name, bus_name4, bus_name3, bus_name2, bus_name1, bus_name0) \ + assign {``bus_name4``_axilite_awaddr , ``bus_name3``_axilite_awaddr , ``bus_name2``_axilite_awaddr , ``bus_name1``_axilite_awaddr , ``bus_name0``_axilite_awaddr } = ``array_name``_axilite_awaddr ; \ + assign {``bus_name4``_axilite_awprot , ``bus_name3``_axilite_awprot , ``bus_name2``_axilite_awprot , ``bus_name1``_axilite_awprot , ``bus_name0``_axilite_awprot } = ``array_name``_axilite_awprot ; \ + assign {``bus_name4``_axilite_awvalid , ``bus_name3``_axilite_awvalid , ``bus_name2``_axilite_awvalid , ``bus_name1``_axilite_awvalid , ``bus_name0``_axilite_awvalid } = ``array_name``_axilite_awvalid ; \ + assign {``bus_name4``_axilite_wdata , ``bus_name3``_axilite_wdata , ``bus_name2``_axilite_wdata , ``bus_name1``_axilite_wdata , ``bus_name0``_axilite_wdata } = ``array_name``_axilite_wdata ; \ + assign {``bus_name4``_axilite_wstrb , ``bus_name3``_axilite_wstrb , ``bus_name2``_axilite_wstrb , ``bus_name1``_axilite_wstrb , ``bus_name0``_axilite_wstrb } = ``array_name``_axilite_wstrb ; \ + assign {``bus_name4``_axilite_wvalid , ``bus_name3``_axilite_wvalid , ``bus_name2``_axilite_wvalid , ``bus_name1``_axilite_wvalid , ``bus_name0``_axilite_wvalid } = ``array_name``_axilite_wvalid ; \ + assign {``bus_name4``_axilite_bready , ``bus_name3``_axilite_bready , ``bus_name2``_axilite_bready , ``bus_name1``_axilite_bready , ``bus_name0``_axilite_bready } = ``array_name``_axilite_bready ; \ + assign {``bus_name4``_axilite_araddr , ``bus_name3``_axilite_araddr , ``bus_name2``_axilite_araddr , ``bus_name1``_axilite_araddr , ``bus_name0``_axilite_araddr } = ``array_name``_axilite_araddr ; \ + assign {``bus_name4``_axilite_arprot , ``bus_name3``_axilite_arprot , ``bus_name2``_axilite_arprot , ``bus_name1``_axilite_arprot , ``bus_name0``_axilite_arprot } = ``array_name``_axilite_arprot ; \ + assign {``bus_name4``_axilite_arvalid , ``bus_name3``_axilite_arvalid , ``bus_name2``_axilite_arvalid , ``bus_name1``_axilite_arvalid , ``bus_name0``_axilite_arvalid } = ``array_name``_axilite_arvalid ; \ + assign {``bus_name4``_axilite_rready , ``bus_name3``_axilite_rready , ``bus_name2``_axilite_rready , ``bus_name1``_axilite_rready , ``bus_name0``_axilite_rready } = ``array_name``_axilite_rready ; \ + assign ``array_name``_axilite_awready = {``bus_name4``_axilite_awready , ``bus_name3``_axilite_awready , ``bus_name2``_axilite_awready , ``bus_name1``_axilite_awready , ``bus_name0``_axilite_awready }; \ + assign ``array_name``_axilite_wready = {``bus_name4``_axilite_wready , ``bus_name3``_axilite_wready , ``bus_name2``_axilite_wready , ``bus_name1``_axilite_wready , ``bus_name0``_axilite_wready }; \ + assign ``array_name``_axilite_bresp = {``bus_name4``_axilite_bresp , ``bus_name3``_axilite_bresp , ``bus_name2``_axilite_bresp , ``bus_name1``_axilite_bresp , ``bus_name0``_axilite_bresp }; \ + assign ``array_name``_axilite_bvalid = {``bus_name4``_axilite_bvalid , ``bus_name3``_axilite_bvalid , ``bus_name2``_axilite_bvalid , ``bus_name1``_axilite_bvalid , ``bus_name0``_axilite_bvalid }; \ + assign ``array_name``_axilite_arready = {``bus_name4``_axilite_arready , ``bus_name3``_axilite_arready , ``bus_name2``_axilite_arready , ``bus_name1``_axilite_arready , ``bus_name0``_axilite_arready }; \ + assign ``array_name``_axilite_rdata = {``bus_name4``_axilite_rdata , ``bus_name3``_axilite_rdata , ``bus_name2``_axilite_rdata , ``bus_name1``_axilite_rdata , ``bus_name0``_axilite_rdata }; \ + assign ``array_name``_axilite_rresp = {``bus_name4``_axilite_rresp , ``bus_name3``_axilite_rresp , ``bus_name2``_axilite_rresp , ``bus_name1``_axilite_rresp , ``bus_name0``_axilite_rresp }; \ + assign ``array_name``_axilite_rvalid = {``bus_name4``_axilite_rvalid , ``bus_name3``_axilite_rvalid , ``bus_name2``_axilite_rvalid , ``bus_name1``_axilite_rvalid , ``bus_name0``_axilite_rvalid }; + + +////////////////// +// Bus Ports // +////////////////// + +// AXI4 MASTER PORTS +`define DEFINE_AXI_MASTER_PORTS(master_name, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + output logic [ID_WIDTH-1 : 0] ``master_name``_axi_awid, \ + output logic [ADDR_WIDTH-1 : 0] ``master_name``_axi_awaddr, \ + output axi_len_t ``master_name``_axi_awlen, \ + output axi_size_t ``master_name``_axi_awsize, \ + output axi_burst_t ``master_name``_axi_awburst, \ + output axi_lock_t ``master_name``_axi_awlock, \ + output axi_cache_t ``master_name``_axi_awcache, \ + output axi_prot_t ``master_name``_axi_awprot, \ + output axi_qos_t ``master_name``_axi_awqos, \ + output axi_valid_t ``master_name``_axi_awvalid, \ + input axi_ready_t ``master_name``_axi_awready, \ + output axi_region_t ``master_name``_axi_awregion, \ + // W channel \ + output logic [DATA_WIDTH-1 : 0] ``master_name``_axi_wdata, \ + output logic [(DATA_WIDTH/8)-1 : 0] ``master_name``_axi_wstrb, \ + output axi_last_t ``master_name``_axi_wlast, \ + output axi_valid_t ``master_name``_axi_wvalid, \ + input axi_ready_t ``master_name``_axi_wready, \ + // B channel \ + input logic [ID_WIDTH-1 : 0] ``master_name``_axi_bid, \ + input axi_resp_t ``master_name``_axi_bresp, \ + input axi_valid_t ``master_name``_axi_bvalid, \ + output axi_ready_t ``master_name``_axi_bready, \ + // AR channel \ + output logic [ADDR_WIDTH-1 : 0] ``master_name``_axi_araddr, \ + output axi_len_t ``master_name``_axi_arlen, \ + output axi_size_t ``master_name``_axi_arsize, \ + output axi_burst_t ``master_name``_axi_arburst, \ + output axi_lock_t ``master_name``_axi_arlock, \ + output axi_cache_t ``master_name``_axi_arcache, \ + output axi_prot_t ``master_name``_axi_arprot, \ + output axi_qos_t ``master_name``_axi_arqos, \ + output axi_valid_t ``master_name``_axi_arvalid, \ + input axi_ready_t ``master_name``_axi_arready, \ + output logic [ID_WIDTH-1 : 0] ``master_name``_axi_arid, \ + output axi_region_t ``master_name``_axi_arregion, \ + // R channel \ + input logic [ID_WIDTH-1 : 0] ``master_name``_axi_rid, \ + input logic [DATA_WIDTH-1 : 0] ``master_name``_axi_rdata, \ + input axi_resp_t ``master_name``_axi_rresp, \ + input axi_last_t ``master_name``_axi_rlast, \ + input axi_valid_t ``master_name``_axi_rvalid, \ + output axi_ready_t ``master_name``_axi_rready + +// AXI4 SLAVE PORTS +`define DEFINE_AXI_SLAVE_PORTS(slave_name, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + input logic [ID_WIDTH-1 : 0] ``slave_name``_axi_awid, \ + input logic [ADDR_WIDTH-1 : 0] ``slave_name``_axi_awaddr, \ + input axi_len_t ``slave_name``_axi_awlen, \ + input axi_size_t ``slave_name``_axi_awsize, \ + input axi_burst_t ``slave_name``_axi_awburst, \ + input axi_lock_t ``slave_name``_axi_awlock, \ + input axi_cache_t ``slave_name``_axi_awcache, \ + input axi_prot_t ``slave_name``_axi_awprot, \ + input axi_qos_t ``slave_name``_axi_awqos, \ + input axi_valid_t ``slave_name``_axi_awvalid, \ + output axi_ready_t ``slave_name``_axi_awready, \ + input axi_region_t ``slave_name``_axi_awregion, \ + // W channel \ + input logic [DATA_WIDTH-1 : 0] ``slave_name``_axi_wdata, \ + input logic [(DATA_WIDTH/8)-1 : 0] ``slave_name``_axi_wstrb, \ + input axi_last_t ``slave_name``_axi_wlast, \ + input axi_valid_t ``slave_name``_axi_wvalid, \ + output axi_ready_t ``slave_name``_axi_wready, \ + // B channel \ + output logic [ID_WIDTH-1 : 0] ``slave_name``_axi_bid, \ + output axi_resp_t ``slave_name``_axi_bresp, \ + output axi_valid_t ``slave_name``_axi_bvalid, \ + input axi_ready_t ``slave_name``_axi_bready, \ + // AR channel \ + input logic [ADDR_WIDTH-1 : 0] ``slave_name``_axi_araddr, \ + input axi_len_t ``slave_name``_axi_arlen, \ + input axi_size_t ``slave_name``_axi_arsize, \ + input axi_burst_t ``slave_name``_axi_arburst, \ + input axi_lock_t ``slave_name``_axi_arlock, \ + input axi_cache_t ``slave_name``_axi_arcache, \ + input axi_prot_t ``slave_name``_axi_arprot, \ + input axi_qos_t ``slave_name``_axi_arqos, \ + input axi_valid_t ``slave_name``_axi_arvalid, \ + output axi_ready_t ``slave_name``_axi_arready, \ + input logic [ID_WIDTH-1 : 0] ``slave_name``_axi_arid, \ + input axi_region_t ``slave_name``_axi_arregion, \ + // R channel \ + output logic [ID_WIDTH-1 : 0] ``slave_name``_axi_rid, \ + output logic [DATA_WIDTH-1 : 0] ``slave_name``_axi_rdata, \ + output axi_resp_t ``slave_name``_axi_rresp, \ + output axi_last_t ``slave_name``_axi_rlast, \ + output axi_valid_t ``slave_name``_axi_rvalid, \ + input axi_ready_t ``slave_name``_axi_rready + +// AXI4 LITE MASTER PORTS +`define DEFINE_AXILITE_MASTER_PORTS(master_name, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + output logic [ADDR_WIDTH-1 : 0] ``master_name``_axilite_awaddr, \ + output axi_prot_t ``master_name``_axilite_awprot, \ + output axi_valid_t ``master_name``_axilite_awvalid, \ + input axi_ready_t ``master_name``_axilite_awready, \ + // W channel \ + output logic [DATA_WIDTH-1 : 0] ``master_name``_axilite_wdata, \ + output logic [(DATA_WIDTH/8)-1 : 0] ``master_name``_axilite_wstrb, \ + output axi_valid_t ``master_name``_axilite_wvalid, \ + input axi_ready_t ``master_name``_axilite_wready, \ + // B channel \ + input axi_resp_t ``master_name``_axilite_bresp, \ + input axi_valid_t ``master_name``_axilite_bvalid, \ + output axi_ready_t ``master_name``_axilite_bready, \ + // AR channel \ + output logic [ADDR_WIDTH-1 : 0] ``master_name``_axilite_araddr, \ + output axi_prot_t ``master_name``_axilite_arprot, \ + output axi_valid_t ``master_name``_axilite_arvalid, \ + input axi_ready_t ``master_name``_axilite_arready, \ + // R channel \ + input logic [DATA_WIDTH-1 : 0] ``master_name``_axilite_rdata, \ + input axi_resp_t ``master_name``_axilite_rresp, \ + input axi_valid_t ``master_name``_axilite_rvalid, \ + output axi_ready_t ``master_name``_axilite_rready + +// AXI4 LITE SLAVE PORTS +`define DEFINE_AXILITE_SLAVE_PORTS(slave_name, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + input logic [ADDR_WIDTH-1 : 0] ``slave_name``_axilite_awaddr, \ + input axi_prot_t ``slave_name``_axilite_awprot, \ + input axi_valid_t ``slave_name``_axilite_awvalid, \ + output axi_ready_t ``slave_name``_axilite_awready, \ + // W channel \ + input logic [DATA_WIDTH-1 : 0] ``slave_name``_axilite_wdata, \ + input logic [(DATA_WIDTH/8)-1 : 0] ``slave_name``_axilite_wstrb, \ + input axi_valid_t ``slave_name``_axilite_wvalid, \ + output axi_ready_t ``slave_name``_axilite_wready, \ + // B channel \ + output axi_resp_t ``slave_name``_axilite_bresp, \ + output axi_valid_t ``slave_name``_axilite_bvalid, \ + input axi_ready_t ``slave_name``_axilite_bready, \ + // AR channel \ + input logic [ADDR_WIDTH-1 : 0] ``slave_name``_axilite_araddr, \ + input axi_prot_t ``slave_name``_axilite_arprot, \ + input axi_valid_t ``slave_name``_axilite_arvalid, \ + output axi_ready_t ``slave_name``_axilite_arready, \ + // R channel \ + output logic [DATA_WIDTH-1 : 0] ``slave_name``_axilite_rdata, \ + output axi_resp_t ``slave_name``_axilite_rresp, \ + output axi_valid_t ``slave_name``_axilite_rvalid, \ + input axi_ready_t ``slave_name``_axilite_rready + + +// AXI4 LITE SLAVE PORTS ARRAY +`define DEFINE_AXILITE_SLAVE_PORTS_ARRAY(slave_array_name, size, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + input logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``slave_array_name``_axilite_awaddr, \ + input axi_prot_t [``size`` -1 : 0] ``slave_array_name``_axilite_awprot, \ + input axi_valid_t [``size`` -1 : 0] ``slave_array_name``_axilite_awvalid, \ + output axi_ready_t [``size`` -1 : 0] ``slave_array_name``_axilite_awready, \ + // W channel \ + input logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``slave_array_name``_axilite_wdata, \ + input logic [(DATA_WIDTH/8)-1 : 0] [``size`` -1 : 0] ``slave_array_name``_axilite_wstrb, \ + input axi_valid_t [``size`` -1 : 0] ``slave_array_name``_axilite_wvalid, \ + output axi_ready_t [``size`` -1 : 0] ``slave_array_name``_axilite_wready, \ + // B channel \ + output axi_resp_t [``size`` -1 : 0] ``slave_array_name``_axilite_bresp, \ + output axi_valid_t [``size`` -1 : 0] ``slave_array_name``_axilite_bvalid, \ + input axi_ready_t [``size`` -1 : 0] ``slave_array_name``_axilite_bready, \ + // AR channel \ + input logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``slave_array_name``_axilite_araddr, \ + input axi_prot_t [``size`` -1 : 0] ``slave_array_name``_axilite_arprot, \ + input axi_valid_t [``size`` -1 : 0] ``slave_array_name``_axilite_arvalid, \ + output axi_ready_t [``size`` -1 : 0] ``slave_array_name``_axilite_arready, \ + // R channel \ + output logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``slave_array_name``_axilite_rdata, \ + output axi_resp_t [``size`` -1 : 0] ``slave_array_name``_axilite_rresp, \ + output axi_valid_t [``size`` -1 : 0] ``slave_array_name``_axilite_rvalid, \ + input axi_ready_t [``size`` -1 : 0] ``slave_array_name``_axilite_rready + + +// AXI4 LITE MASTER PORTS ARRAY +`define DEFINE_AXILITE_MASTER_PORTS_ARRAY(master_array_name, size, DATA_WIDTH, ADDR_WIDTH, ID_WIDTH) \ + // AW channel \ + output logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``master_array_name``_axilite_awaddr, \ + output axi_prot_t [``size`` -1 : 0] ``master_array_name``_axilite_awprot, \ + output axi_valid_t [``size`` -1 : 0] ``master_array_name``_axilite_awvalid, \ + input axi_ready_t [``size`` -1 : 0] ``master_array_name``_axilite_awready, \ + // W channel \ + output logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``master_array_name``_axilite_wdata, \ + output logic [(DATA_WIDTH/8)-1 : 0] [``size`` -1 : 0] ``master_array_name``_axilite_wstrb, \ + output axi_valid_t [``size`` -1 : 0] ``master_array_name``_axilite_wvalid, \ + input axi_ready_t [``size`` -1 : 0] ``master_array_name``_axilite_wready, \ + // B channel \ + input axi_resp_t [``size`` -1 : 0] ``master_array_name``_axilite_bresp, \ + input axi_valid_t [``size`` -1 : 0] ``master_array_name``_axilite_bvalid, \ + output axi_ready_t [``size`` -1 : 0] ``master_array_name``_axilite_bready, \ + // AR channel \ + output logic [ADDR_WIDTH-1 : 0] [``size`` -1 : 0] ``master_array_name``_axilite_araddr, \ + output axi_prot_t [``size`` -1 : 0] ``master_array_name``_axilite_arprot, \ + output axi_valid_t [``size`` -1 : 0] ``master_array_name``_axilite_arvalid, \ + input axi_ready_t [``size`` -1 : 0] ``master_array_name``_axilite_arready, \ + // R channel \ + input logic [DATA_WIDTH-1 : 0] [``size`` -1 : 0] ``master_array_name``_axilite_rdata, \ + input axi_resp_t [``size`` -1 : 0] ``master_array_name``_axilite_rresp, \ + input axi_valid_t [``size`` -1 : 0] ``master_array_name``_axilite_rvalid, \ + output axi_ready_t [``size`` -1 : 0] ``master_array_name``_axilite_rready + +///////////////////// +// Sink interfaces // +///////////////////// + +// These macros are meant to emulate a stub master or slave, +// never really doing anything. This way, we avoid to leave +// floating signals around. + +// Sink AXI master interface +`define SINK_AXI_MASTER_INTERFACE(bus_name) \ + assign ``bus_name``_axi_awid = '0; \ + assign ``bus_name``_axi_awaddr = '0; \ + assign ``bus_name``_axi_awlen = '0; \ + assign ``bus_name``_axi_awsize = '0; \ + assign ``bus_name``_axi_awburst = '0; \ + assign ``bus_name``_axi_awlock = '0; \ + assign ``bus_name``_axi_awcache = '0; \ + assign ``bus_name``_axi_awprot = '0; \ + assign ``bus_name``_axi_awqos = '0; \ + assign ``bus_name``_axi_awvalid = '0; \ + assign ``bus_name``_axi_awregion = '0; \ + assign ``bus_name``_axi_wdata = '0; \ + assign ``bus_name``_axi_wstrb = '0; \ + assign ``bus_name``_axi_wlast = '0; \ + assign ``bus_name``_axi_wvalid = '0; \ + assign ``bus_name``_axi_bready = '1; \ + assign ``bus_name``_axi_araddr = '0; \ + assign ``bus_name``_axi_arlen = '0; \ + assign ``bus_name``_axi_arsize = '0; \ + assign ``bus_name``_axi_arburst = '0; \ + assign ``bus_name``_axi_arlock = '0; \ + assign ``bus_name``_axi_arcache = '0; \ + assign ``bus_name``_axi_arprot = '0; \ + assign ``bus_name``_axi_arqos = '0; \ + assign ``bus_name``_axi_arvalid = '0; \ + assign ``bus_name``_axi_arid = '0; \ + assign ``bus_name``_axi_arregion = '0; \ + assign ``bus_name``_axi_rready = '1; + +// Sink AXI slave interface +`define SINK_AXI_SLAVE_INTERFACE(bus_name) \ + assign ``bus_name``_axi_awready = '1; \ + assign ``bus_name``_axi_wready = '1; \ + assign ``bus_name``_axi_bid = '0; \ + assign ``bus_name``_axi_bresp = '0; \ + assign ``bus_name``_axi_bvalid = '0; \ + assign ``bus_name``_axi_arready = '1; \ + assign ``bus_name``_axi_rid = '0; \ + assign ``bus_name``_axi_rdata = '0; \ + assign ``bus_name``_axi_rresp = '0; \ + assign ``bus_name``_axi_rlast = '0; \ + assign ``bus_name``_axi_rvalid = '0; + +// Sink AXI-lite master interface +`define SINK_AXILITE_MASTER_INTERFACE(bus_name) \ + assign ``bus_name``_axilite_awaddr = '0; \ + assign ``bus_name``_axilite_awprot = '0; \ + assign ``bus_name``_axilite_awvalid = '0; \ + assign ``bus_name``_axilite_wdata = '0; \ + assign ``bus_name``_axilite_wstrb = '0; \ + assign ``bus_name``_axilite_wvalid = '0; \ + assign ``bus_name``_axilite_bready = '1; \ + assign ``bus_name``_axilite_araddr = '0; \ + assign ``bus_name``_axilite_arprot = '0; \ + assign ``bus_name``_axilite_arvalid = '0; \ + assign ``bus_name``_axilite_rready = '1; + +// Sink AXI-lite slave interface +`define SINK_AXILITE_SLAVE_INTERFACE(bus_name) \ + assign ``bus_name`_axilite_awready = '1; \ + assign ``bus_name`_axilite_wready = '1; \ + assign ``bus_name`_axilite_bvalid = '0; \ + assign ``bus_name`_axilite_bresp = '0; \ + assign ``bus_name`_axilite_arready = '1; \ + assign ``bus_name`_axilite_rdata = '0; \ + assign ``bus_name`_axilite_rvalid = '0; \ + assign ``bus_name`_axilite_rresp = '0; + +`endif // UNINASOC_AXI_SVH__ diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_clk_assignments.svinc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_clk_assignments.svinc new file mode 100644 index 0000000000000000000000000000000000000000..5bb3298fe69f11599267750d0c28e921b3fab7cf --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_clk_assignments.svinc @@ -0,0 +1,29 @@ +// This file is auto-generated with declare_and_assign_clocks_rtl.py + +///////////////////////////////////////// +// Clocks declaration and assignments // +///////////////////////////////////////// +assign main_clk = clk_20MHz; +assign main_rstn = rstn_20MHz; +logic clk_300MHz; +logic rstn_300MHz; +logic BRAM_clk; +assign BRAM_clk = clk_20MHz; +logic BRAM_rstn; +assign BRAM_rstn = rstn_20MHz; +logic DM_mem_clk; +assign DM_mem_clk = clk_20MHz; +logic DM_mem_rstn; +assign DM_mem_rstn = rstn_20MHz; +logic PBUS_clk; +assign PBUS_clk = clk_10MHz; +logic PBUS_rstn; +assign PBUS_rstn = rstn_10MHz; +logic CDMA_clk; +assign CDMA_clk = clk_20MHz; +logic CDMA_rstn; +assign CDMA_rstn = rstn_20MHz; +logic PLIC_clk; +assign PLIC_clk = clk_20MHz; +logic PLIC_rstn; +assign PLIC_rstn = rstn_20MHz; diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_ddr4.svh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_ddr4.svh new file mode 100644 index 0000000000000000000000000000000000000000..684ac611165544582a94e17d76da24ce7caa2733 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_ddr4.svh @@ -0,0 +1,29 @@ +// Author: Manuel Maddaluno +// Description: Utility variables and macros for DDR4 interface + +`ifndef UNINASOC_DDR4_SVH__ +`define UNINASOC_DDR4_SVH__ + + +// DDR4 Ports +// ch admitted values: 0, 1, 2, 3 + +`define DEFINE_DDR4_PORTS(channel) \ + output logic [16:0] c``channel``_ddr4_adr, \ + output logic [1:0] c``channel``_ddr4_ba, \ + output logic [1:0] c``channel``_ddr4_bg, \ + output logic [0:0] c``channel``_ddr4_ck_t, \ + output logic [0:0] c``channel``_ddr4_ck_c, \ + output logic [0:0] c``channel``_ddr4_cke, \ + output logic [0:0] c``channel``_ddr4_cs_n, \ + output logic c``channel``_ddr4_act_n, \ + output logic [0:0] c``channel``_ddr4_odt, \ + output logic c``channel``_ddr4_parity, \ + output logic c``channel``_ddr4_reset_n, \ + inout logic [71:0] c``channel``_ddr4_dq, \ + inout logic [17:0] c``channel``_ddr4_dqs_t, \ + inout logic [17:0] c``channel``_ddr4_dqs_c + + + +`endif \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_mem.svh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_mem.svh new file mode 100644 index 0000000000000000000000000000000000000000..260e415a424ef851ce1510d1a412aed0316f7342 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_mem.svh @@ -0,0 +1,147 @@ +// Author: Stefano Mercogliano +// Description: Utility variables and macros for MEMb (SRAM) protocols +// Note: The main rationale behind this macro is to avoid the usage of structs and +// macros for the widest possible syntax compatibility. + +`ifndef UNINASOC_MEM_SVH__ +`define UNINASOC_MEM_SVH__ + +////////////////////////////////////////////////////// +// ___ _ // +// | _ \__ _ _ _ __ _ _ __ ___| |_ ___ _ _ ___ // +// | _/ _` | '_/ _` | ' \/ -_) _/ -_) '_(_-< // +// |_| \__,_|_| \__,_|_|_|_\___|\__\___|_| /__/ // +// // +////////////////////////////////////////////////////// + +// MEM parameters, such as strobe, data and address width, +// must be compatible with AXI, therefore we directly reuse them. + +//////////////////////////////////////// +// __ __ _ ___ ___ ___ // +// | \/ | /_\ / __| _ \/ _ \ ___ // +// | |\/| |/ _ \ (__| / (_) (_-< // +// |_| |_/_/ \_\___|_|_\\___//__/ // +// // +//////////////////////////////////////// + +//////////////////////// +// Bus Declaration // +//////////////////////// + +// Declare MEM bus specifying the DATA_WIDTH +`define DECLARE_MEM_BUS(bus_name, DATA_WIDTH, ADDR_WIDTH) \ + logic ``bus_name``_mem_req; \ + logic ``bus_name``_mem_gnt; \ + logic ``bus_name``_mem_valid; \ + logic [ADDR_WIDTH-1 : 0] ``bus_name``_mem_addr; \ + logic [DATA_WIDTH-1 : 0] ``bus_name``_mem_rdata; \ + logic [DATA_WIDTH-1 : 0] ``bus_name``_mem_wdata; \ + logic ``bus_name``_mem_we; \ + logic [(DATA_WIDTH)/8-1 : 0] ``bus_name``_mem_be; \ + logic ``bus_name``_mem_error; + +// Declare MEM array +`define DECLARE_MEM_BUS_ARRAY(array_name, size, DATA_WIDTH, ADDR_WIDTH) \ + logic [``size`` -1 : 0] ``bus_name``_mem_req; \ + logic [``size`` -1 : 0] ``bus_name``_mem_gnt; \ + logic [``size`` -1 : 0] ``bus_name``_mem_valid; \ + logic [ADDR_WIDTH-1 : 0][``size`` -1 : 0] ``bus_name``_mem_addr; \ + logic [DATA_WIDTH-1 : 0][``size`` -1 : 0] ``bus_name``_mem_rdata; \ + logic [DATA_WIDTH-1 : 0][``size`` -1 : 0] ``bus_name``_mem_wdata; \ + logic [``size`` -1 : 0] ``bus_name``_mem_we; \ + logic [(DATA_WIDTH)/8-1 : 0][``size`` -1 : 0] ``bus_name``_mem_be; \ + logic [``size`` -1 : 0] ``bus_name``_mem_error; + +/////////////////////// +// Bus Assignment // +/////////////////////// + +// Assign srce to dest signals +`define ASSIGN_MEM_BUS(dest, src) \ + assign ``dest``_mem_req = ``src``_mem_req ; \ + assign ``dest``_mem_gnt = ``src``_mem_gnt ; \ + assign ``dest``_mem_valid = ``src``_mem_valid ; \ + assign ``dest``_mem_addr = ``src``_mem_addr ; \ + assign ``dest``_mem_rdata = ``src``_mem_rdata ; \ + assign ``dest``_mem_wdata = ``src``_mem_wdata ; \ + assign ``dest``_mem_we = ``src``_mem_we ; \ + assign ``dest``_mem_be = ``src``_mem_be ; \ + assign ``dest``_mem_error = ``src``_mem_error ; + + +//////////////////////// +// Bus Concatenation // +//////////////////////// + +// NOTE: these macro are just enumerating, without variadic args +// I don't see a better way to do this, for now + +// Mock macro for one bus for compatibility +// Effectively, just renaming the signals +`define CONCAT_MEM_MASTERS_ARRAY1(array_name, bus_name0) \ + `ASSIGN_MEM_BUS(``array_name``, ``bus_name0``) + +// Concatenate 2 master buses +`define CONCAT_MEM_MASTERS_ARRAY2(array_name, bus_name1, bus_name0) \ + assign ``array_name``_mem_req = {``bus_name1``_mem_req , ``bus_name0``_mem_req }; \ + assign ``array_name``_mem_gnt = {``bus_name1``_mem_gnt , ``bus_name0``_mem_gnt }; \ + assign ``array_name``_mem_valid = {``bus_name1``_mem_valid , ``bus_name0``_mem_valid }; \ + assign ``array_name``_mem_addr = {``bus_name1``_mem_addr , ``bus_name0``_mem_addr }; \ + assign ``array_name``_mem_rdata = {``bus_name1``_mem_rdata , ``bus_name0``_mem_rdata }; \ + assign ``array_name``_mem_wdata = {``bus_name1``_mem_wdata , ``bus_name0``_mem_wdata }; \ + assign ``array_name``_mem_we = {``bus_name1``_mem_we , ``bus_name0``_mem_we }; \ + assign ``array_name``_mem_be = {``bus_name1``_mem_be , ``bus_name0``_mem_be }; \ + assign ``array_name``_mem_error = {``bus_name1``_mem_error , ``bus_name0``_mem_error }; + +////////////////// +// Bus Ports // +////////////////// + +// MEM MASTER PORTS +`define DEFINE_MEM_MASTER_PORTS(bus_name, DATA_WIDTH, ADDR_WIDTH) \ + output logic ``bus_name``_mem_req, \ + input logic ``bus_name``_mem_gnt, \ + input logic ``bus_name``_mem_valid, \ + output logic [ADDR_WIDTH-1 : 0] ``bus_name``_mem_addr, \ + input logic [DATA_WIDTH-1 : 0] ``bus_name``_mem_rdata, \ + output logic [DATA_WIDTH-1 : 0] ``bus_name``_mem_wdata, \ + output logic ``bus_name``_mem_we, \ + output logic [(DATA_WIDTH)/8-1 : 0] ``bus_name``_mem_be, \ + input logic ``bus_name``_mem_error + +`define DEFINE_MEM_SLAVE_PORTS(bus_name, DATA_WIDTH, ADDR_WIDTH) \ + input logic ``bus_name``_mem_req, \ + output logic ``bus_name``_mem_gnt, \ + output logic ``bus_name``_mem_valid, \ + input logic [ADDR_WIDTH-1 : 0] ``bus_name``_mem_addr, \ + output logic [DATA_WIDTH-1 : 0] ``bus_name``_mem_rdata, \ + input logic [DATA_WIDTH-1 : 0] ``bus_name``_mem_wdata, \ + input logic ``bus_name``_mem_we, \ + input logic [(DATA_WIDTH)/8-1 : 0] ``bus_name``_mem_be, \ + output logic ``bus_name``_mem_error + +///////////////////// +// Sink interfaces // +///////////////////// + +// These macros are meant to emulate a stub master or slave, +// never really doing anything. This way, we avoid to leave +// floating signals around. + +// Sink MEM master interface +`define SINK_MEM_MASTER_INTERFACE(bus_name) \ + assign ``bus_name``_mem_gnt = '0; \ + assign ``bus_name``_mem_valid = '0; \ + assign ``bus_name``_mem_rdata = '0; \ + assign ``bus_name``_mem_error = '0; + +// Sink MEM slave interface +`define SINK_MEM_SLAVE_INTERFACE(bus_name) \ + assign ``bus_name``_mem_req = '0; \ + assign ``bus_name``_mem_addr = '0; \ + assign ``bus_name``_mem_wdata = '0; \ + assign ``bus_name``_mem_we = '0; \ + assign ``bus_name``_mem_be = '0; + +`endif // UNINASOC_MEM_SVH__ \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_pcie.svh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_pcie.svh new file mode 100644 index 0000000000000000000000000000000000000000..74c9989a100d3c4f667e62f60efd7be47d0abd6f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_pcie.svh @@ -0,0 +1,19 @@ +// Author: Manuel Maddaluno +// Description: Utility variables and macros for PCIe interface + +`ifndef UNINASOC_PCIE_SVH__ +`define UNINASOC_PCIE_SVH__ + +////////////////// +// PCIe defines // +////////////////// +localparam int unsigned NUM_PCIE_LANES = 8; + +// PCIe define ports +`define DEFINE_PCIE_PORTS() \ + input logic [NUM_PCIE_LANES-1:0] pci_exp_rxn_i, \ + input logic [NUM_PCIE_LANES-1:0] pci_exp_rxp_i, \ + output logic [NUM_PCIE_LANES-1:0] pci_exp_txn_o, \ + output logic [NUM_PCIE_LANES-1:0] pci_exp_txp_o + +`endif \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_pkg.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..1029a5b6efadeb72605d8496b66c067fa7cf22f1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/uninasoc_pkg.sv @@ -0,0 +1,120 @@ +// Author: Vincenzo Maisto +// Author: Stefano Mercogliano +// Description: Basic system variables for UninaSoC + +package uninasoc_pkg; + + /////////////////////// + // SoC-level defines // + /////////////////////// + + // GPIO widths + localparam int unsigned GPIO_IN_WIDTH = 16; + localparam int unsigned GPIO_OUT_WIDTH = 16; + + // MBUS widths + localparam MBUS_DATA_WIDTH = `MBUS_DATA_WIDTH; // From SoC config + localparam MBUS_ADDR_WIDTH = `MBUS_ADDR_WIDTH; // From SoC config + localparam MBUS_ID_WIDTH = `MBUS_ID_WIDTH; // From MBUS config + + // PBUS widths + localparam PBUS_DATA_WIDTH = 32; // Fixed 32-bits + localparam PBUS_ADDR_WIDTH = 32; // Fixed 32-bits + localparam PBUS_ID_WIDTH = `PBUS_ID_WIDTH; // From PBUS config + + // HBUS widths + localparam int unsigned HBUS_DATA_WIDTH = 512; // Same as DRAM channels + localparam int unsigned HBUS_ADDR_WIDTH = `MBUS_ADDR_WIDTH; // Same as MBUS + localparam int unsigned HBUS_ID_WIDTH = `HBUS_ID_WIDTH; // From HBUS config + + /////////////////////// + // AXI main crossbar // + /////////////////////// + + // Main Crosbar masters + localparam int unsigned MBUS_NUM_SI = `MBUS_NUM_SI; + // Main Crosbar slaves + localparam int unsigned MBUS_NUM_MI = `MBUS_NUM_MI; + + ///////////////////////////// + // AXI Lite peripheral bus // + ///////////////////////////// + + // Always assume 1 master + // Peripheral bus slaves + localparam int unsigned PBUS_NUM_MI = `PBUS_NUM_MI; + + ////////////////////////// + // High-performance bus // + ////////////////////////// + localparam int unsigned HBUS_NUM_SI = `HBUS_NUM_SI; + localparam int unsigned HBUS_NUM_MI = `HBUS_NUM_MI; + + + ////////////////////////// + // Supported Processors // + ////////////////////////// + + typedef enum int unsigned { + // 32-bits Cores + CORE_PICORV32, + CORE_CV32E40P, + CORE_IBEX, + CORE_MICROBLAZEV_RV32, + CORE_DUAL_MICROBLAZEV_RV32, + // 64-bits Cores + CORE_MICROBLAZEV_RV64, + CORE_CV64A6 + } core_selector_t; + + // Select core from macro + localparam core_selector_t CORE_SELECTOR = `CORE_SELECTOR; + + /////////////////////// + // System Interrupts // + /////////////////////// + + // Masters and Buses (Slves) can generate interrupts, which are forwarded to the PLIC (Platform interrupts). + // The PLIC forwards interrupts to the Masters (e.g. the Socket) + + // RISC-V cores standard interrupts + localparam int unsigned CORE_SW_INTERRUPT = 3; // Inter Processor Interrupts + localparam int unsigned CORE_TIM_INTERRUPT = 7; // Real-time Clock Timer + localparam int unsigned CORE_EXT_INTERRUPT = 11; // PLIC-to-hart interrupts + + // Peripheral Bus interrupts + localparam int unsigned PBUS_GPIOIN_INTERRUPT = 0; // GPIO In [embedded only] + localparam int unsigned PBUS_TIM0_INTERRUPT = 1; // Timer 0 + localparam int unsigned PBUS_TIM1_INTERRUPT = 2; // Timer 1 + localparam int unsigned PBUS_UART_INTERRUPT = 3; // UART + + // PLIC Interrupts mapping + // We support 32 possible sources of platform interrupts, which are statically mapped + // regardless of the configuration. + // TODO154: this is static for now, must generate by config + localparam int unsigned PLIC_RESERVED_INTERRUPT = 0; // PLIC line 0 is reserved + localparam int unsigned PLIC_GPIOIN_INTERRUPT = 1; // GPIO In (From PBUS)[embedded only] + localparam int unsigned PLIC_TIM0_INTERRUPT = 2; // Timer 0 (From PBUS) + localparam int unsigned PLIC_TIM1_INTERRUPT = 3; // Timer 1 (From PBUS) + localparam int unsigned PLIC_UART_INTERRUPT = 4; // UART (From PBUS) + localparam int unsigned PLIC_HLS_INTERRUPT = 5; // HLS (From HLS core) [HPC only] + localparam int unsigned PLIC_CDMA_INTERRUPT = 6; // CDMA (From DMA IP) + + /////////////// + // Functions // + /////////////// + + // This function is used to turn a core_selector id into the corresponding core name string + function string core_selector_to_string(input int core_sel); + case (core_sel) + CORE_PICORV32: return "CORE_PICORV32"; + CORE_CV32E40P: return "CORE_CV32E40P"; + CORE_IBEX: return "CORE_IBEX"; + CORE_MICROBLAZEV_RV32: return "CORE_MICROBLAZEV_RV32"; + CORE_MICROBLAZEV_RV64: return "CORE_MICROBLAZEV_RV64"; + CORE_DUAL_MICROBLAZEV_RV32: return "CORE_DUAL_MICROBLAZEV_RV32"; + default: return $sformatf("UNKNOWN_CORE_%0d", core_sel); + endcase + endfunction + +endpackage : uninasoc_pkg diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/virtual_uart.sv b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/virtual_uart.sv new file mode 100644 index 0000000000000000000000000000000000000000..c45abb33512bec4ace670be0304a86092b97efaf --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/rtl/virtual_uart.sv @@ -0,0 +1,215 @@ +// Author: Manuel Maddaluno +// Description: Virtual Uart - This module simulates the physical uart connected to XDMA through AXI lite + + +// Import packages +import uninasoc_pkg::*; + +// Import headers +`include "uninasoc_axi.svh" + + +module virtual_uart # ( + parameter int unsigned LOCAL_DATA_WIDTH = 32, + parameter int unsigned LOCAL_ADDR_WIDTH = 32, + parameter int unsigned LOCAL_ID_WIDTH = 32 +) ( + input logic clock_i, + input logic reset_ni, + + // Interrupts + // 0 - to the Core + // 1 - to the XDMA + output logic int_core_o, + output logic int_xdma_o, + input logic [1:0] int_ack_i, + + // AXILITE Slave interface + `DEFINE_AXILITE_SLAVE_PORTS(s, LOCAL_DATA_WIDTH, LOCAL_ADDR_WIDTH, LOCAL_ID_WIDTH) +); + + + // Uart CSR - for more details see PG142 + // 0 - 00h - RX register + // 1 - 04h - TX register + // 2 - 08h - Status register + // 3 - 0Ch - Control register + // 4 - 10h - ACK from the host interrupt + localparam RX_REG = 0; + localparam TX_REG = 1; + localparam STATUS_REG = 2; + localparam CONTROL_REG = 3; + localparam HOST_INT_ACK_REG = 4; + + // Control/status register bit position + localparam CTRL_RST_TX_BIT = 0; // Control - Reset TX register + localparam CTRL_RST_RX_BIT = 0; // Control - Reset RX register + localparam CTRL_STS_INT_BIT = 4; // Control and status - Interrupt enable + localparam STS_RX_VALID_BIT = 0; // Status - RX register valid + localparam STS_RX_FULL_BIT = 1; // Status - RX register full + localparam STS_TX_EMPTY_BIT = 2; // Status - TX register empty + localparam STS_TX_FULL_BIT = 3; // Status - TX register full + + logic [LOCAL_DATA_WIDTH-1:0] uart_csr [0:4]; + + + /* AXILITE Write logic */ + always_ff @( posedge clock_i or negedge reset_ni ) begin + if ( !reset_ni ) begin + s_axilite_awready <= 1'b0; + end + else begin + s_axilite_awready <= (s_axilite_awvalid && !s_axilite_awready); + end + end + + always_ff @( posedge clock_i or negedge reset_ni ) begin + if ( !reset_ni ) begin + s_axilite_wready <= 1'b0; + s_axilite_bvalid <= 1'b0; + s_axilite_bresp <= 2'b00; + end + else begin + if ( s_axilite_wvalid && s_axilite_wready && s_axilite_awvalid && s_axilite_awready ) begin + s_axilite_bvalid <= 1'b1; + s_axilite_bresp <= 2'b00; + + end + if ( s_axilite_bvalid && s_axilite_bready ) begin + s_axilite_bvalid <= 1'b0; + end + + s_axilite_wready <= (s_axilite_wvalid && s_axilite_awvalid && !s_axilite_awready); + end + end + + + /* AXILITE Read logic */ + always_ff @( posedge clock_i or negedge reset_ni ) begin + if ( !reset_ni ) begin + s_axilite_arready <= 1'b0; + s_axilite_rvalid <= 1'b0; + s_axilite_rdata <= 0; + s_axilite_rresp <= 2'b00; + end else begin + + if (s_axilite_arvalid && !s_axilite_arready) begin + s_axilite_arready <= 1'b1; + end else begin + s_axilite_arready <= 1'b0; + end + + if (s_axilite_arvalid && s_axilite_arready) begin + s_axilite_rdata <= uart_csr[s_axilite_araddr[4:2]]; + s_axilite_rvalid <= 1'b1; + s_axilite_rresp <= 2'b00; + end + if (s_axilite_rvalid && s_axilite_rready) begin + s_axilite_rvalid <= 1'b0; + end + end + end + + // Control/Status register logic + always_ff @( posedge clock_i or negedge reset_ni ) begin + if ( !reset_ni ) begin + foreach(uart_csr[i]) uart_csr[i] <= 0; + end + else begin + if ( s_axilite_wvalid && s_axilite_wready && s_axilite_awvalid && s_axilite_awready ) begin + // If there is a write on the control register + if ( s_axilite_awaddr[4:2] == CONTROL_REG /*&& s_axilite_wstrb[0]*/ ) begin + + // RST TX register + if (s_axilite_wdata[CTRL_RST_TX_BIT]) begin + uart_csr[TX_REG] <= 0; + // TX register empty + uart_csr[STATUS_REG][STS_TX_EMPTY_BIT] <= 1'b1; + // TX register full + uart_csr[STATUS_REG][STS_TX_FULL_BIT] <= 1'b0; + end + + // RST RX register + if (s_axilite_wdata[CTRL_RST_RX_BIT]) begin + uart_csr[RX_REG] <= 0; + // RX register valid + uart_csr[STATUS_REG][STS_RX_VALID_BIT] <= 1'b0; + // RX register full + uart_csr[STATUS_REG][STS_RX_FULL_BIT] <= 1'b0; + end + + // Propagate the interrupt enable/disable on the status register + uart_csr[STATUS_REG][CTRL_STS_INT_BIT] <= s_axilite_wdata[CTRL_STS_INT_BIT]; + end + + // There is a write on the RX register + else if ( s_axilite_awaddr[4:2] == RX_REG /*&& s_axilite_wstrb[0]*/ ) begin + // save data + uart_csr[RX_REG][7:0] <= s_axilite_wdata[7:0]; + // RX register valid + uart_csr[STATUS_REG][STS_RX_VALID_BIT] <= 1'b1; + // RX register full + uart_csr[STATUS_REG][STS_RX_FULL_BIT] <= 1'b1; + end + + // There is a write on the TX register + else if ( s_axilite_awaddr[4:2] == TX_REG /*&& s_axilite_wstrb[0]*/ ) begin + // save data + uart_csr[TX_REG][7:0] <= s_axilite_wdata[7:0]; + // TX register empty + uart_csr[STATUS_REG][STS_TX_EMPTY_BIT] <= 1'b0; + // TX register full + uart_csr[STATUS_REG][STS_TX_FULL_BIT] <= 1'b1; + end + + end + + if ( s_axilite_arvalid && s_axilite_arready ) begin + + // There is a read on the RX register + if ( s_axilite_araddr[4:2] == RX_REG ) begin + // RX register valid + uart_csr[STATUS_REG][STS_RX_VALID_BIT] <= 1'b0; + // RX register full + uart_csr[STATUS_REG][STS_RX_FULL_BIT] <= 1'b0; + end + + // There is a read on the TX register + else if ( s_axilite_araddr[4:2] == TX_REG ) begin + // TX register empty + uart_csr[STATUS_REG][STS_TX_EMPTY_BIT] <= 1'b1; + // TX register full + uart_csr[STATUS_REG][STS_TX_FULL_BIT] <= 1'b0; + end + end + + + end + end + + // Interrupts logic + // THIS IS A STUB - TO DO + always_ff @( posedge clock_i or negedge reset_ni ) begin + if ( !reset_ni ) begin + int_core_o <= '0; + int_xdma_o <= '0; + end + else begin + if ( s_axilite_wvalid && s_axilite_wready && s_axilite_awvalid && s_axilite_awready ) begin + + // There is a write on TX reg, need to interrupt the XDMA + if ( s_axilite_awaddr[4:2] == TX_REG /*&& s_axilite_wstrb[0]*/ ) begin + int_xdma_o <= 1'b1; + end + + // There is a write on HOST ACK register reset the interrupt to the XDMA + else if ( s_axilite_awaddr[4:2] == HOST_INT_ACK_REG /*&& s_axilite_wstrb[0]*/ ) begin + int_xdma_o <= 1'b0; + end + + + end + end + end + +endmodule \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/jtag2axi_load_binary.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/jtag2axi_load_binary.tcl new file mode 100644 index 0000000000000000000000000000000000000000..17cb9cc1b5758ca430217052459f73c7e8c11c96 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/jtag2axi_load_binary.tcl @@ -0,0 +1,140 @@ +# Author: Zaira Abdel Majid +# Author: Vincenzo Maisto +# Description: tcl script used to transfer a .bin file in a BRAM memory using jtag2axi IP and axi transactions +# Input args: +# -argv0: absolute path to bin file to transfer +# -argv1: base address of BRAM +# -argv2: whether to read-back data after writing + +######### +# Utils # +######### + +# Utility function to read binary file +proc read_file_to_words {filename fsize} { + # Open file + set fp [open $filename r] + + # Translate file to binary + fconfigure $fp -translation binary + + # Read data + set file_data [read $fp $fsize] + + # Close file + close $fp + + # Return + return $file_data +} + +############## +# Parse args # +############## +if { $argc != 3 } { + puts "Usage " + puts "filename : path to bin file to transfer" + puts "base_address : base address of BRAM" + puts "read_back : whether to read-back data after writing" + return +} else { + set filename [lindex $argv 0] + set base_address [lindex $argv 1] + set read_back [lindex $argv 2] +} + +######## +# Init # +######## + +# Disable message limit +set_msg_config -id {Labtoolstcl 44-481} -limit 99999 + +# File size in bytes +set fsize [file size $filename] + +# AXI transaction names +set gpio_wr_txn gpio_wr_txn +set gpio_rd_txn gpio_rd_txn + +# Internal variables: +# -data_list: binary file read at absolute path +# -num_bursts: size of each "burst" (data sent) in each transaction in bytes (4 -> 32 bits). This parameter is architecture dependent. +# -remaining bytes: reminder in terms of bytes that will handled with padding. +# -segment: chunk of $burst_size bytes extracted from data_lists and converted in hexadecimal + +# Read file +set data_list [read_file_to_words $filename $fsize] +# Burst size in bytes +set burst_size 4 +# Number of $burst_size-bytes transaction +set num_bursts [expr {int( $fsize / $burst_size)}] +# Remining bytes +set remaining_bytes [expr {$fsize % $burst_size}] + +# Print warning +if { $remaining_bytes != 0 } { + # Padding size + set pad_size [expr $burst_size - $remaining_bytes ] + # Warning message + puts stderr "\[WARINING\] Binary has non $burst_size-aligned size ($fsize), padding with $pad_size zero-bytes" + # Pad with zeros + for {set i 0} {$i < $pad_size} {incr i} { + set data_list "$data_list\0" + } + # Add one burst + incr num_bursts +} + +################### +# Write to memory # +################### +# Run burst-based transactions +for {set i 0} {$i < $num_bursts} {incr i} { + # Select $burst_size-wide segment to read + set segment [string range $data_list [expr {$i * $burst_size}] [expr {($i + 1) * $burst_size} -1]] + + # Invert endiannes from string (0x01234567 -> 0x67543201) + set str_tmp "" + for {set j 0} {$j < $burst_size} {incr j} { + set str_tmp [string index $segment $j]$str_tmp + } + set segment $str_tmp + + # Convert to binary + binary scan $segment H* Memword + + # Calculate address + set address [format 0x%x [expr {$base_address + $i * $burst_size}]] + + # Create and run transaction + create_hw_axi_txn $gpio_wr_txn [get_hw_axis hw_axi_1] -type write -force -address $address -data $Memword -len $burst_size + run_hw_axi [get_hw_axi_txns $gpio_wr_txn] + + # Debug + # puts "Writing to address $address" +} + +######################### +# Read-back from memory # +######################### + +if { $read_back == "true" } { + for {set i 0} {$i < $num_bursts} {incr i} { + # Compose address + set address [format 0x%x [expr {$base_address + $i * $burst_size}]] + + # Create and run transaction + create_hw_axi_txn $gpio_rd_txn [get_hw_axis hw_axi_1] -type read -force -address $address + run_hw_axi [get_hw_axi_txns $gpio_rd_txn] + + # Debug + # puts "Reading from to address $address" + } +} + +############ +# Clean up # +############ +# Restore message limit +reset_msg_config -id {Labtoolstcl 44-481} -limit \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/openocd.cfg b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/openocd.cfg new file mode 100644 index 0000000000000000000000000000000000000000..0b3226cb43fb1272055c45507ca1ae355a6d6279 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/openocd.cfg @@ -0,0 +1,174 @@ +# Author: Vincenzo Maisto +# Author: Manuel Maddaluno +# Description: OpenOCD config file. It starts the OpenOCD backend based on the board adopted + +######### +# BOARD # +######### +set board $::env(BOARD) +puts "Starting openoncd with $board board" + +# Select the right variables based on the board adopted +switch $board { + "Nexys-A7-50T-Master" { + # Nexys A7 50T + # FTDI Device Description + set _DEVIDE_DESC "Digilent USB Device" + # FTDI VID + set _VID 0x0403 + # FTDI PID + set _PID 0x6010 + # JTAG expected ID + set _EXPECTED_ID 0x0362c093 + # IRLEN + set _IRLEN 6 + # PULP BSCAN tunnel + # IDECODE + set _IDCODE 0x09 + # DTMCS + set _DTMCS 0x22 + # DMI + set _DMI 0x23 + } + "Nexys-A7-100T-Master" { + # Nexys A7 100T + # FTDI Device Description + set _DEVIDE_DESC "Digilent USB Device" + # FTDI VID + set _VID 0x0403 + # FTDI PID + set _PID 0x6010 + # JTAG expected ID + set _EXPECTED_ID 0x13631093 + # IRLEN + set _IRLEN 6 + # PULP BSCAN tunnel + # IDECODE + set _IDCODE 0x09 + # DTMCS + set _DTMCS 0x22 + # DMI + set _DMI 0x23 + } + "au250" { + # Alveo U250 + # FTDI Device Description + set _DEVIDE_DESC "A-U250-A64G" + # FTDI VID + set _VID 0x0403 + # FTDI PID + set _PID 0x6011 + # JTAG expected ID + set _EXPECTED_ID 0x04b57093 + # IRLEN + set _IRLEN 24 + # PULP BSCAN tunnel + # IDECODE + set _IDCODE 0x249249 + # DTMCS + set _DTMCS 0x8a4924 + # DMI + set _DMI 0x8e4924 + } + "au280" { + # Alveo U280 + # FTDI Device Description + set _DEVIDE_DESC "A-U280-A32G" + # FTDI VID + set _VID 0x0403 + # FTDI PID + set _PID 0x6011 + # JTAG expected ID + set _EXPECTED_ID 0x04b57093 + # IRLEN + set _IRLEN 24 + # PULP BSCAN tunnel + # IDECODE + set _IDCODE 0x249249 + # DTMCS + set _DTMCS 0x8a4924 + # DMI + set _DMI 0x8e4924 + } + + default { + puts stderr "The board specified ($board) is not supported" + exit 1 + } +} + +# TODO: extend for ZCU (PULP BSCAN tunnel) +# # ZCU102 +# riscv set_ir idcode 0x249 +# riscv set_ir dtmcs 0x922 +# riscv set_ir dmi 0x923 + + +########### +# Adapter # +########### + +adapter driver ftdi +adapter speed 1000 + +######## +# FTDI # +######## + +ftdi device_desc $_DEVIDE_DESC +ftdi vid_pid $_VID $_PID +ftdi channel 0 +ftdi layout_init 0x0088 0x008b +ftdi tdo_sample_edge falling +transport select jtag + +# Reset +reset_config none + +############ +# JTAG TAP # +############ +# Configure JTAG chain and the target processor +set _CHIPNAME riscv + +jtag newtap $_CHIPNAME cpu -irlen $_IRLEN -expected-id $_EXPECTED_ID -ignore-version +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME + +########## +# RISC-V # +########## + +# SiFive BSCAN tunnel (specific to SiFive IP). +# See doc at https://openocd.org/doc/html/Architecture-and-Core-Commands.html +# riscv use_bscan_tunnel value + +# PULP BSCAN tunnel +riscv set_ir idcode $_IDCODE +riscv set_ir dtmcs $_DTMCS +riscv set_ir dmi $_DMI + +# Timeouts +riscv set_command_timeout_sec 10 +riscv set_command_timeout_sec 10 + +######### +# Ports # +######### + +# Disable +telnet port disabled +tcl port disabled + +# Same as XSDB for RV32 +gdb port 3004 + +######## +# Exit # +######## +# Conclude OpenOCD configuration +init + +# Halt the target +halt + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/run_gdb.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/run_gdb.sh new file mode 100644 index 0000000000000000000000000000000000000000..df94c50e96780aeb2faa554c24020292025bcf64 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/run_gdb.sh @@ -0,0 +1,43 @@ +#!/bin/bash +# Author: Stefano Mercogliano +# Description: Launch GDB with a target ELF file and connecting to a specific backend port + + +EXPECTED_ARGC=3; +ARGC=$#; + +# Print the right usage +help (){ + echo "Usage: source ${BASH_SOURCE[0]} "; + echo " elf_name : path to the elf file"; + echo " backend [ip:port] : port backend (We use 3004 for both vivado hw_server (32-bits) and openocd. Port 3005 for vivado hw_server riscv 64 bits)"; + echo " xlen : system xlen (32 or 64 bits)"; + return; +} + +# Check the argc +if [ $ARGC -ne $EXPECTED_ARGC ]; +then + echo "Invalid number of arguments, please check the inputs and try again"; + help; + return 1; +fi + +# Get the args +ELF_NAME=$1; +BACKEND_IP_PORT=$2; +XLEN=$3 + +echo "Running GDB $XLEN-bits version"; +echo "Loading ELF $ELF_NAME"; +echo "Connecting to $BACKEND_IP_PORT"; + +# Run GDB +riscv$XLEN-unknown-elf-gdb $ELF_NAME \ + -ex 'set architecture riscv:rv'$XLEN \ + -ex 'target extended-remote '$BACKEND_IP_PORT \ + -ex "file $ELF_NAME" \ + -ex 'load ' \ + -ex "b _exit_wfi" \ + -ex "c" \ + -ex "quit" diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xdma_load_binary.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xdma_load_binary.sh new file mode 100644 index 0000000000000000000000000000000000000000..84cca12365875a955cba6f782127d9c80b127618 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xdma_load_binary.sh @@ -0,0 +1,126 @@ +#!/bin/bash +# Author: Manuel Maddaluno +# Description: Load a binary into the SoC memory through the XDMA and PCIe +# This is a bash script in the "tcl" directory ... + +EXPECTED_ARGC=4; +ARGC=$#; + +# Print the right usage +help (){ + echo "Usage: source ${BASH_SOURCE[0]} "; + echo " PCIe BAR : target BAR of PCIe device"; + echo " binary_file : path to bin file to transfer"; + echo " offset : offset in SoC"; + echo " read_back : whether to read-back data after writing"; + return; +} + +# Check the argc +if [ $ARGC -ne $EXPECTED_ARGC ]; +then + echo "Invalid number of arguments, please check the inputs and try again"; + help; + return 1; +fi + +# Get the args +PCIE_BAR=$1 +FILE_NAME=$2; +OFFSET=$3; +READBACK=$4; + +# Get the file size in bytes +FILE_SIZE=$(stat -c%s "$FILE_NAME"); + +# Read the entire file in hexadecimal +# We need the -u flag for the devmem-based read-back check +hex_file=$(xxd -p -u -c 9999999999 $FILE_NAME); + +# Set the transaction size in bytes +trans_size=8; # Host-side BAR space supports 8-bytes transactions + +# Compute number of transactions +num_trans=$(($FILE_SIZE/$trans_size)); +remaining_bytes=$(($FILE_SIZE%$trans_size)); + +# Print warning +if [ $remaining_bytes -ne 0 ]; then + # Padding size + pad_size=$(( $trans_size - $remaining_bytes )) + # Warning message + echo "[WARINING] Binary has non $trans_size-aligned size ($FILE_SIZE), padding with $pad_size zero-bytes" >&2 + # Pad with zeros + for((i=0; i<$pad_size; i=i+1)); + do + hex_file="$hex_file""00" + done + # Add one burst + num_trans=$(($num_trans +1)) +fi + +# Golden result for later readback check +golden_hex="" + +# Write the binary +addr=$(($PCIE_BAR + $OFFSET)) +echo "Start writing..."; +# For each transaction +for i in $(seq 1 $num_trans); +do + # Clear accumulator + hex_data=""; + + # Flip endiannes from string (0x01234567 -> 0x67452301) + # For each byte (2 nibbles) in $trans_size + for((j=$i*2*$trans_size-2; j>$(($i-1))*2*$trans_size-2; j=j-2)); + do + # Append a single byte (2 nibbles slice) + hex_data=${hex_data}${hex_file:$((j)):$((2))} + done + + # Write to BAR-mapped address + hex_addr=$(printf "%x" $addr); + sudo busybox devmem 0x$hex_addr $(($trans_size*8)) 0x$hex_data + + # Increment address + addr=$(($addr + $trans_size)); + + # Save for readback + if [[ ${READBACK} == "true" ]]; + then + # Append to old + golden_hex=${golden_hex}${hex_data} + fi +done + +echo "Write complete!"; + +# Readback +if [[ ${READBACK} == "true" ]]; +then + echo "Start readback..."; + addr=$(($PCIE_BAR + $OFFSET)) + readback_data=""; + for i in $(seq 0 $(($num_trans-1))); + do + hex_addr=$(printf "%x" $addr); + tmp_data=$( sudo busybox devmem 0x$hex_addr $(($trans_size*8))); + readback_data=${readback_data}${tmp_data:2:$trans_size*2}; # Slice to remove the 'hex prefix' ( 0x ) + addr=$(($addr+$trans_size)); + done + + echo "Readback complete!"; + echo "Golden hexadecimal binary:"; + echo $golden_hex; + echo "Readback hexadecimal data:"; + echo $readback_data; + + # Check they are the same + if [[ ${golden_hex} == ${readback_data} ]]; + then + echo "Test passed :)"; + else + echo "Test failed :("; + fi +fi diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xsdb_backend.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xsdb_backend.tcl new file mode 100644 index 0000000000000000000000000000000000000000..458e9df3a37d857166f9aea408b8fd63316b3364 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xsdb_backend.tcl @@ -0,0 +1,22 @@ +# Author: Stefano Mercogliano +# Description: +# Open XSDB and connect to RISC-V hart 0 +# The goal is to use XSDB as a backend for GDB + +# Connect to hw_server +connect -host $::env(XILINX_HW_SERVER_HOST) -port $::env(XILINX_HW_SERVER_PORT) + +puts "\[INFO\] Initiate connection" +connect + +after 500 + +# Filter and set target +puts "\[INFO\] Selecting target Hart #0" +targets -set -filter {name =~ "*Hart #0*"} + +# Reset target core +puts "\[INFO\] Resetting target" +rst -processor + +puts "\[INFO\] XSDB backend running, open GDB" \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xsdb_run_elf.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xsdb_run_elf.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f7e6c74174836e70a53d371b8ec876ff7bf9267c --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/load_binary/xsdb_run_elf.tcl @@ -0,0 +1,55 @@ +# Author: Vincenzo Maisto +# Args: +# $1: Path to target ELF +# $2: Path to target bitstream (optional) +# Description: +# Basic XSDB script to load and run an ELF file. +# Optionally, it can also configure the FPGA with a new bitstream. + +############## +# Parse args # +############## +if { $argc < 1 } { + puts "Usage " + puts "elf_file : path to elf file to transfer" + puts "bitstream : path to bitstream file (optional)" + return +} + +# Set target elf +set ELF_FILE [lindex $argv 0] + +# Set bitstream, if any +set program_bitstream 0 +if { $argc == 2 } { + set program_bitstream 1 + set BITSTREAM [lindex $argv 1] +} + +######## +# Init # +######## + +# Connect to hw_server +connect -host $::env(XILINX_HW_SERVER_HOST) -port $::env(XILINX_HW_SERVER_PORT) + +# Configure FPGA +if { $program_bitstream == 1 } { + puts "\[INFO\] Programming bistream $BITSTREAM" + fpga $BITSTREAM +} + +# Filter and set target +puts "\[INFO\] Selecting target Hart #0" +targets -set -filter {name =~ "*Hart #0*"} +# Reset target core +puts "\[INFO\] Resetting target" +rst -processor +# Load elf into memory +puts "\[INFO\] Downloading elf $ELF_FILE" +dow $ELF_FILE +# Wait 0.5 seconds +after 500 +# Start execution +puts "\[INFO\] Starting execution" +con diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/open_hw_manager.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/open_hw_manager.tcl new file mode 100644 index 0000000000000000000000000000000000000000..4629cc683dd996a4e5b53e84f3cc418cdc4caaf2 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/open_hw_manager.tcl @@ -0,0 +1,42 @@ +# Author: Vincenzo Maisto +# Description: Open Vivado Hardware Manager and set probe file + +# Connect to hw server +open_hw_manager +set url $::env(XILINX_HW_SERVER_HOST):$::env(XILINX_HW_SERVER_PORT) +if {[catch {connect_hw_server -url $url} 0]} { + puts stderr "WARNING: Another connection is already up, proceeding using the existing connection instead" +} +set target_path $::env(XILINX_HW_SERVER_HOST):$::env(XILINX_HW_SERVER_PORT)/$::env(XILINX_HW_SERVER_FPGA_PATH) +set hw_target [lindex [get_hw_target $target_path] 0] +# Device at index zero +open_hw_target $hw_target +# Let's keep JTAG frequency to 5000000 so that it works with all supported SoC frequencies +set_property PARAM.FREQUENCY 5000000 [get_hw_targets $hw_target] + +# Set hw_device +set hw_device [get_hw_devices $::env(XILINX_HW_DEVICE)] +# Select hw device +current_hw_device $hw_device + +# Set bitstream path +set_property PROGRAM.FILE $::env(XILINX_BITSTREAM) $hw_device + +############## +# Probe file # +############## + +# Add probe file +puts "\[ILA\] Using probe file $::env(XILINX_PROBE_LTX)" +if {[catch { exec ls $::env(XILINX_PROBE_LTX) } 0]} { + puts "\[INFO\] Probe $::env(XILINX_PROBE_LTX) file not found" +} else { + set_property PROBES.FILE $::env(XILINX_PROBE_LTX) $hw_device + set_property FULL_PROBES.FILE $::env(XILINX_PROBE_LTX) $hw_device +} +current_hw_device $hw_device + +################### +# Get debug cores # +################### +refresh_hw_device [lindex $hw_device 0] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/pcie_hot_reset.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/pcie_hot_reset.sh new file mode 100644 index 0000000000000000000000000000000000000000..4b1304fabce6c5ac19326369254bbade6e0be330 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/pcie_hot_reset.sh @@ -0,0 +1,50 @@ +#!/bin/bash + +# This script is inspired by corundum https://github.com/corundum/corundum/blob/master/fpga/lib/pcie/scripts/pcie_hot_reset.sh + +# TODO: find the dev automatically in the script +dev=$1 + +if [ -z "$dev" ]; then + echo "Error: no device specified" + exit 1 +fi + +if [ ! -e "/sys/bus/pci/devices/$dev" ]; then + dev="0000:$dev" +fi + +if [ ! -e "/sys/bus/pci/devices/$dev" ]; then + echo "Error: device $dev not found" + exit 1 +fi + +port=$(basename $(dirname $(readlink "/sys/bus/pci/devices/$dev"))) + +if [ ! -e "/sys/bus/pci/devices/$port" ]; then + echo "Error: device $port not found" + exit 1 +fi + +echo "Removing $dev..." + +echo 1 > "/sys/bus/pci/devices/$dev/remove" + +echo "Performing hot reset of port $port..." + +echo "Bridge control:" $(setpci -s $port BRIDGE_CONTROL) + +setpci -s $port BRIDGE_CONTROL=40:40 +sleep 0.5 +setpci -s $port BRIDGE_CONTROL=00:40 +sleep 0.5 + +echo "Rescanning bus..." + +if [ -e "/sys/bus/pci/devices/$port/dev_rescan" ]; then + echo 1 > "/sys/bus/pci/devices/$port/dev_rescan" +else + echo 1 > "/sys/bus/pci/devices/$port/rescan" +fi + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/program_bitstream.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/program_bitstream.tcl new file mode 100644 index 0000000000000000000000000000000000000000..c4f508e350c5a202dea4cb2cef2d8a9010f9e27f --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/program_bitstream.tcl @@ -0,0 +1,13 @@ +# Author: Vincenzo Maisto +# Description: Program bitstream, assuming an open connection to a device + +# Set programming files +set_property PROGRAM.FILE $::env(XILINX_BITSTREAM) $hw_device +program_hw_devices $hw_device +refresh_hw_device $hw_device + +puts "Query the design" +# Debug +report_property -all [get_hw_targets $hw_target] +# Search for hw probes +refresh_hw_device -update_hw_probes false [lindex [get_hw_devices $::env(XILINX_FPGA_DEVICE)] 0] \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/readback_jtag2axi.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/readback_jtag2axi.tcl new file mode 100644 index 0000000000000000000000000000000000000000..2ce35664f7111b39b78761f8c3c1567f46349b0d --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/readback_jtag2axi.tcl @@ -0,0 +1,81 @@ +# Author: Vincenzo Maisto +# Description: tcl script used to read back from AXI +# Input args: +# -argv0: base address +# -argv1: number of transactions + +######### +# Utils # +######### + +# Utility function to read binary file +proc read_file_to_words {filename fsize} { + # Open file + set fp [open $filename r] + + # Translate file to binary + fconfigure $fp -translation binary + + # Read data + set file_data [read $fp $fsize] + + # Close file + close $fp + + # Return + return $file_data +} + +############## +# Parse args # +############## +puts "Usage " +puts "base_address : base address" +puts "num_bytes : number of bytes" +if { $argc != 2 } { + # Default + set base_address 0x0000 + set num_bytes 16 +} else { + set base_address [lindex $argv 0] + set num_bytes [lindex $argv 1] +} + +######## +# Init # +######## + +# Disable message limit +set_msg_config -id {Labtoolstcl 44-481} -limit 99999 + +# AXI transaction names +set gpio_wr_txn gpio_wr_txn +set gpio_rd_txn gpio_rd_txn + +# Bytes per burst +set burst_size 4 +# Number of $burst_size-bytes transaction +set num_bursts [expr {int( $num_bytes / $burst_size)}] + +######################### +# Read-back from memory # +######################### + +for {set i 0} {$i < $num_bursts} {incr i} { + # Compose address + set address [format 0x%x [expr {$base_address + $i * $burst_size}]] + + # Debug + puts "Reading from address $address" + + # Create and run transaction + create_hw_axi_txn $gpio_rd_txn [get_hw_axis hw_axi_1] -type read -force -address $address + run_hw_axi [get_hw_axi_txns $gpio_rd_txn] + +} + +############ +# Clean up # +############ +# Restore message limit +reset_msg_config -id {Labtoolstcl 44-481} -limit \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/readback_xdma.sh b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/readback_xdma.sh new file mode 100644 index 0000000000000000000000000000000000000000..35f852860e32aa4f7eca92187f6b90ed16802590 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/readback_xdma.sh @@ -0,0 +1,52 @@ +#!/bin/sh +# Author: Vincenzo Maisto +# Description: Bash script to read back from AXI using busybox devmem +# Arguments: +# $1: PCIe BAR +# $2: Offset in SoC +# $2: Number of bytes to read + +# -------------------------- +# Usage and argument parsing +# -------------------------- +if [ "$#" -ne 3 ]; then + echo "Usage: $0 " + echo "Example: $0 0x92000000 0x40000 64" + OFFSET=0x0000 + NUM_BYTES=16 +else + PCIE_BAR=$1 + OFFSET=$2 + NUM_BYTES=$3 +fi + +# -------------------------- +# Constants and setup +# -------------------------- +BURST_SIZE=4 # bytes per read +READ_SIZE_BITS=$(($BURST_SIZE * 8)) # bits per read +NUM_BURSTS=$((NUM_BYTES / BURST_SIZE)) + +echo "PCIe BAR: $PCIE_BAR" +echo "Base address: $OFFSET" +echo "Number of bytes to read: $NUM_BYTES" +echo "Reading $NUM_BURSTS bursts of $BURST_SIZE bytes each" +echo "-------------------------------------------" + +# -------------------------- +# Convert hex to decimal for arithmetic +# -------------------------- +base_dec=$(($OFFSET + $PCIE_BAR)) + +# -------------------------- +# Read loop +# -------------------------- +for ((i=0; i +# Description: Set ILA triggers, control and arm +# Note: Assuming a single ILA IP in the design and hw_server already connected + +##################### +# ILA configuration # +##################### +puts "\[ILA\] Setting triggers" + +# Set trigger control +set_property CONTROL.TRIGGER_MODE BASIC_ONLY [get_hw_ilas] +set_property CONTROL.TRIGGER_CONDITION OR [get_hw_ilas] +set_property CONTROL.TRIGGER_POSITION 4096 [get_hw_ilas] + +# Set triggers +set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes sys_master_to_xbar_axi_arvalid -of_objects [get_hw_ilas]] +set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes sys_master_to_xbar_axi_awvalid -of_objects [get_hw_ilas]] +set_property TRIGGER_COMPARE_VALUE eq1'b1 [get_hw_probes sys_master_to_xbar_axi_wvalid -of_objects [get_hw_ilas]] + +########### +# Arm ILA # +########### + +# Display (empty) waveforms -> run immediate trigger +display_hw_ila_data [upload_hw_ila_data [get_hw_ilas]] + +# Arm ILA +# puts "\[ILA\] Arming ILA" +# run_hw_ila [get_hw_ilas] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/vio_reset.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/vio_reset.tcl new file mode 100644 index 0000000000000000000000000000000000000000..59b61eab563d6af4144dd9a554553da6fc192b23 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/scripts/utils/vio_reset.tcl @@ -0,0 +1,60 @@ +# Author: Vincenzo Maisto +# Description: Utility script to toggle (0-> 1-> 0) VIO probe +# Args: +# $1: VIO probe name + +############## +# Parse args # +############## +if { $argc != 1 } { + puts "Usage: vio_reset.tcl " + puts "probe_name : name of probe to toggle" + return +} +set probe_name [lindex $argv 0] + +############## +# VIO toggle # +############## + +# Select VIO instance +set vio_name "vio_inst" +puts "\[INFO\] Searching for VIO $vio_name" +set hw_vio [get_hw_vios -of_objects [get_hw_devices $hw_device] -filter {CELL_NAME=~vio_inst}] +if {$hw_vio == "" } { + error "\[ERROR\] VIO $vio_name not found!" + return +} +puts $hw_vio + +# Select probe +puts "\[INFO\] Searching for probe $probe_name" +set hw_probe [get_hw_probes $probe_name -of_objects [get_hw_vios $hw_vio]] +if { $hw_probe == "" } { + error "\[ERROR\] Probe $probe_name not found!" + return +} +puts $hw_probe + +# Set 0 +puts "\[INFO\] Setting probe $probe_name to 0" +set_property OUTPUT_VALUE 0 [get_hw_probes $hw_probe] +commit_hw_vio [get_hw_probes $hw_probe] + +# Wait 0.5s +puts "\[INFO\] Waiting 0.5 seconds..." +after 500 + +# Set 1 +puts "\[INFO\] Setting probe $probe_name to 0" +set_property OUTPUT_VALUE 1 [get_hw_probes $hw_probe] +commit_hw_vio [get_hw_probes $hw_probe] + +# Wait 0.5s +puts "\[INFO\] Waiting 0.5 seconds..." +after 500 + +# Set 1 +puts "\[INFO\] Setting probe $probe_name to 1" +set_property OUTPUT_VALUE 1 [get_hw_probes $hw_probe] +commit_hw_vio [get_hw_probes $hw_probe] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..c54fee8283541fb67454a0a5d3b383a2d73dd828 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/.gitignore @@ -0,0 +1 @@ +simlib/* \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/README.md b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/README.md new file mode 100644 index 0000000000000000000000000000000000000000..435e46d9c5d1ac1af9539f5872fc8105512d88f8 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/README.md @@ -0,0 +1,3 @@ +# SoC Simulation (Questa) + +> TBD: this is just a placeholder for future developments. \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/add_sim_sources.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/add_sim_sources.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1f7ef07a7d81e732c839355fdf960e491b36b992 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/add_sim_sources.tcl @@ -0,0 +1,3 @@ +TODO: ++ add base sources from hw/rtl/sources.txt ++ add sim-only sources diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/add_waves.do b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/add_waves.do new file mode 100644 index 0000000000000000000000000000000000000000..2fd9f9570028dac87fd50b6dd37124d915c8b441 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/add_waves.do @@ -0,0 +1 @@ +TBD \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/compile_simlib.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/compile_simlib.tcl new file mode 100644 index 0000000000000000000000000000000000000000..bcb46403b05d778831c73de29076fc1d3d311d12 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/compile_simlib.tcl @@ -0,0 +1,17 @@ +# Author: Vincenzo Maisto +# Description: Compile simulation librarires in Vivado + +# set command "compile_simlib -simulator questa -simulator_exec_path {$::env(SIMULATOR_PATH)} \ +# -gcc_exec_path {$::env(GCC_PATH)} -family all -language verilog -library all -dir {$::env(XILINX_SIMLIB_PATH)} -force" +# # For some reason this command does not work well when not eval from the string +# eval $command + +compile_simlib \ + -simulator questa \ + -simulator_exec_path "$::env(QUESTA_PATH)" \ + -gcc_exec_path "$::env(GCC_PATH)" \ + -family all \ + -language verilog \ + -library all \ + -dir "$::env(XILINX_SIMLIB_PATH)" \ + -force \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/export_simulation.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/export_simulation.tcl new file mode 100644 index 0000000000000000000000000000000000000000..72f78032ddffc04b56f9059dbab7f48a0a127cd5 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/export_simulation.tcl @@ -0,0 +1,14 @@ +# Author: Vincenzo Maisto +# Description: Create simulation model for a Xilix IP + +# Open a project containing the target IP +open_project $::env(VIVADO_PROJECT) + +# Export simulation +export_simulation \ + -simulator questa \ + -directory "$::env(XILINX_SIM_IP_ROOT)" \ + -lib_map_path "$::env(XILINX_SIMLIB_PATH)" \ + -absolute_path \ + -force \ + -of_objects [get_ips *] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/mig_export_simulation.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/mig_export_simulation.tcl new file mode 100644 index 0000000000000000000000000000000000000000..76335accfa97a2be42fc23f6cf08e7522609d45b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/sim/tcl/mig_export_simulation.tcl @@ -0,0 +1,2 @@ +# TBD +# this is expected to require more sophistication than other IPs \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/Nexys-A7-100T-Master.xdc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/Nexys-A7-100T-Master.xdc new file mode 100644 index 0000000000000000000000000000000000000000..a9a98b97accb5d15e82e2ca0efb9ce3301464b00 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/Nexys-A7-100T-Master.xdc @@ -0,0 +1,254 @@ +## This file is a general .xdc for the Nexys A7 +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal (let's set 50Mhz) +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports sys_clock_i] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock_i] + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { gpio_in_i[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { gpio_in_i[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[0] }] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[1] }] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { SEG[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { SEG[1] }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { SEG[2] }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { SEG[3] }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SEG[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { SEG[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { SEG[6] }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports sys_reset_i] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] +set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_L6P_T0_35 Sch=jc[7] +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }]; #IO_L15P_T2_DQS_35 Sch=jd[7] +#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }]; #IO_L20P_T3_35 Sch=jd[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] + +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] + +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + + + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/Nexys-A7-50T-Master.xdc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/Nexys-A7-50T-Master.xdc new file mode 100644 index 0000000000000000000000000000000000000000..fc92689649df4d3c77d173461f2d96ee92f0ac0c --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/Nexys-A7-50T-Master.xdc @@ -0,0 +1,255 @@ +## This file is a general .xdc for the Nexys A7 +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +## Clock signal (let's set 50Mhz) +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports sys_clock_i] +create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock_i] + +##Switches + +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { gpio_in_i[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { gpio_in_i[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { gpio_in_i[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] + + +## LEDs + +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[0] }] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[1] }] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { gpio_out_o[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] + +#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b +#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g +#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r +#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b +#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G }]; #IO_0_14 Sch=led17_g +#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r + + +##7 segment display + +#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { SEG[0] }]; #IO_L24N_T3_A00_D16_14 Sch=ca +#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { SEG[1] }]; #IO_25_14 Sch=cb +#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { SEG[2] }]; #IO_25_15 Sch=cc +#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { SEG[3] }]; #IO_L17P_T2_A26_15 Sch=cd +#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { SEG[4] }]; #IO_L13P_T2_MRCC_14 Sch=ce +#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { SEG[5] }]; #IO_L19P_T3_A10_D26_14 Sch=cf +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { SEG[6] }]; #IO_L4P_T0_D04_14 Sch=cg + +#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp + +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] +#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] + + +##Buttons + +#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn + +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports sys_reset_i] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd + + +##Pmod Headers + + +##Pmod Header JA + +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }]; #IO_L20N_T3_A19_15 Sch=ja[1] +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=ja[2] +#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }]; #IO_L21P_T3_DQS_15 Sch=ja[3] +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }]; #IO_L18N_T2_A23_15 Sch=ja[4] +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }]; #IO_L16N_T2_A27_15 Sch=ja[7] +#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }]; #IO_L16P_T2_A28_15 Sch=ja[8] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }]; #IO_L22N_T3_A16_15 Sch=ja[9] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }]; #IO_L22P_T3_A17_15 Sch=ja[10] + + +##Pmod Header JB + +#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }]; #IO_L1P_T0_AD0P_15 Sch=jb[1] +#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }]; #IO_L14N_T2_SRCC_15 Sch=jb[2] +#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }]; #IO_L13N_T2_MRCC_15 Sch=jb[3] +#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }]; #IO_L15P_T2_DQS_15 Sch=jb[4] +#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }]; #IO_L11N_T1_SRCC_15 Sch=jb[7] +#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }]; #IO_L5P_T0_AD9P_15 Sch=jb[8] +#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }]; #IO_0_15 Sch=jb[9] +#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }]; #IO_L13P_T2_MRCC_15 Sch=jb[10] + + +##Pmod Header JC + +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }]; #IO_L23N_T3_35 Sch=jc[1] +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }]; #IO_L19N_T3_VREF_35 Sch=jc[2] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }]; #IO_L22N_T3_35 Sch=jc[3] +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }]; #IO_L19P_T3_35 Sch=jc[4] +#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_L6P_T0_35 Sch=jc[7] +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }]; #IO_L21P_T3_DQS_35 Sch=jc[9] +#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }]; #IO_L5P_T0_AD13P_35 Sch=jc[10] + + +##Pmod Header JD + +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }]; #IO_L21N_T3_DQS_35 Sch=jd[1] +#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }]; #IO_L17P_T2_35 Sch=jd[2] +#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }]; #IO_L17N_T2_35 Sch=jd[3] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }]; #IO_L20N_T3_35 Sch=jd[4] +set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }]; #IO_L6P_T0_35 Sch=jc[7] +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { uart_tx_o }]; #IO_L22P_T3_35 Sch=jc[8] +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }]; #IO_L15N_T2_DQS_35 Sch=jd[9] +#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }]; #IO_L13N_T2_MRCC_35 Sch=jd[10] + + +##Pmod Header JXADC + +#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }]; #IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1] +#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }]; #IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1] +#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }]; #IO_L8N_T1_AD10N_15 Sch=xa_n[2] +#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }]; #IO_L8P_T1_AD10P_15 Sch=xa_p[2] +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }]; #IO_L7N_T1_AD2N_15 Sch=xa_n[3] +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }]; #IO_L7P_T1_AD2P_15 Sch=xa_p[3] +#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }]; #IO_L10N_T1_AD11N_15 Sch=xa_n[4] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }]; #IO_L10P_T1_AD11P_15 Sch=xa_p[4] + + +##VGA Connector + +#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0] +#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1] +#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2] +#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3] + +#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0] +#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1] +#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2] +#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3] + +#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0] +#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; #IO_L4N_T0_35 Sch=vga_b[1] +#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; #IO_L6N_T0_VREF_35 Sch=vga_b[2] +#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; #IO_L4P_T0_35 Sch=vga_b[3] + +#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS }]; #IO_L4P_T0_15 Sch=vga_hs +#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS }]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs + + +##Micro SD Connector + +#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET }]; #IO_L14P_T2_SRCC_35 Sch=sd_reset +#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }]; #IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd +#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }]; #IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck +#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD }]; #IO_L16N_T2_35 Sch=sd_cmd +#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0] }]; #IO_L16P_T2_35 Sch=sd_dat[0] +#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1] }]; #IO_L18N_T2_35 Sch=sd_dat[1] +#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2] }]; #IO_L18P_T2_35 Sch=sd_dat[2] +#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3] }]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3] + + +##Accelerometer + +#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO }]; #IO_L11P_T1_SRCC_15 Sch=acl_miso +#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI }]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi +#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK }]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk +#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN }]; #IO_L12P_T1_MRCC_15 Sch=acl_csn +#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1] +#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2] + + +##Temperature Sensor + +#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL }]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl +#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA }]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda +#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT }]; #IO_L6N_T0_VREF_15 Sch=tmp_int +#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT }]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct + +##Omnidirectional Microphone + +#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }]; #IO_25_35 Sch=m_clk +#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA }]; #IO_L24N_T3_35 Sch=m_data +#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL }]; #IO_0_35 Sch=m_lrsel + + +##PWM Audio Amplifier + +#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm +#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD }]; #IO_L6P_T0_15 Sch=aud_sd + + +##USB-RS232 Interface + +#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in +#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { UART_TXD }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L12N_T1_MRCC_35 Sch=uart_cts +#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_L5N_T0_AD13N_35 Sch=uart_rts + +##USB HID (PS/2) + +#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK }]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk +#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA }]; #IO_L10N_T1_AD15N_35 Sch=ps2_data + + +##SMSC Ethernet PHY + +#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC }]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc +#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO }]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio +#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN }]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn +#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv +#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr +#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0] +#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1] +#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN }]; #IO_L11N_T1_SRCC_16 Sch=eth_txen +#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0] +#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1] +#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk +#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN }]; #IO_L12P_T1_MRCC_16 Sch=eth_intn + + +##Quad SPI Flash + +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn + + + + diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/au250.xdc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/au250.xdc new file mode 100644 index 0000000000000000000000000000000000000000..54fd6694175d89d1ce4a521b210cf3f7c6035df1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/au250.xdc @@ -0,0 +1,1058 @@ +############################################################################ +# DISCLAIMER: +# XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, +# SCHEMATIC, AND/OR SPECIFICATION (THE “DOCUMENTATION”)TO YOU SOLELY +# FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX +# HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, +# DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM +# OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC, +# MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE +# PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY +# LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION. +# XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE +# DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO +# OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, +# OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY +# DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR +# ASSISTANCETHAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE +# DOCUMENTATION. +# THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF +# ANY OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR +# NONINFRINGEMENT STATUTORY, REGARDING THEDOCUMENTATION, INCLUDING +# ANY WARRANTIES OF KIND. +# XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR THE +# DOCUMENTATION. INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING +# FROM YOUR USE OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR +# INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, +# ARISING FROM YOUR USE OF THE DOCUMENTATION. +# +# +# AU200/250 - Master XDC +# +# FPGA PIN reference are with respect to the U200 FPGA Bank naming +# The FPGA A200 and A250 are pin for pin compatible devices. +# +----------------+---------------+---------------+---------------+ +# | A250 Bank | A200 Bank | Usage | Voltage | +# +----------------+---------------+---------------+---------------+ +# | Bank 61,62,63 | Bank 40,41,42 | DDR4 C0 Int. | 1.2V | +# +----------------+---------------+---------------+---------------+ +# | Bank 65,66,67 | Bank 65,66,67 | DDR4 C1 Int. | 1.2V | +# +----------------+---------------+---------------+---------------+ +# | Bank 69,70,71 | Bank 46,47,48 | DDR4 C2 Int. | 1.2V | +# +----------------+---------------+---------------+---------------+ +# | Bank 72,73,74 | Bank 70,71,72 | DDR4 C3 Int. | 1.2V | +# +----------------+---------------+---------------+---------------+ +# | Bank 64 | Bank 64 | Misc. IO | 1.2V | +# +----------------+---------------+---------------+---------------+ +# | Bank 231 | Bank 231 | QSFP0 | NA | +# +----------------+---------------+---------------+---------------+ +# | Bank 230 | Bank 230 | QSFP1 | NA | +# +----------------+---------------+---------------+---------------+ +# | Bank 224-227 | Bank 224-227 | PCIE | NA | +# +----------------+---------------+---------------+---------------+ +# +# +# Key Notes: +# 1) Power warning constraint set to warn user if design exceeds 160 Watts +# 3) Refer to XAPP1321 for DDR4 Self refresh and fast calibration. +# +# Clock Trees +# +# 1) SI570 - SiLabs 570BAB000544DG @ 156.250Mhz Programmable Oscillator (Re-programming I2C access via Bank 64 I2C ) +# +# - OUT---> SI570_OUTPUT_P/SI570_OUTPUT_N @ 156.250Mhz LVDS +# | +# |--> SI53340-B-GM --> OUT0 USER_SI570_CLOCK_P/USER_SI570_CLOCK_N 156.250Mhz - General Perpose System Clock. +# | PINS: IO_L12P_T1U_N10_GC_64_AU19/IO_L12N_T1U_N11_GC_64_AV19 +# | +# |-> OUT1 Not Connected +# | PINS: NA +# | +# |-> OUT2 MGT_SI570_CLOCK0_C_P/MGT_SI570_CLOCK0_C_N 156.250Mhz - QSFP0 REFCLK0 +# | PINS: MGTREFCLK0P_231_M11/MGTREFCLK0N_231_M10 +# | +# |-> OUT3 MGT_SI570_CLOCK1_C_P/MGT_SI570_CLOCK1_C_N 156.250Mhz - QSFP0 REFCLK1 +# PINS: MGTREFCLK0P_230_T11/MGTREFCLK0N_230_T10 +# +# 2) SI335A - SiLabs SI5335A-B06201-GM Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP0 REFCLK1 +# +# - FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups) +# FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS +# PINS: "QSFP0_FS[0]" - IO_L10P_T1U_N6_QBC_AD4P_64_AT20 +# PINS: "QSFP0_FS[1]" - IO_L9N_T1L_N5_AD12N_64_AU22 +# +# - RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. +# PINS: "QSFP0_RECLK_RESET" - IO_L9P_T1L_N4_AD12P_64_AT22 +# +# - OUT0--> SYSCLK_300_P/SYSCLK_300_N @ 300.0000Mhz to 1-to-4 Clock buffer (Fixed and Unchanged by FS[1:0]) +# | +# |--> SI53340-B-GM --> OUT0 SYSCLK0_300_P/SYSCLK0_300_N 300.000Mhz - System Clock for first DDR4 MIG interface +# | PINS: IO_L13P_T2L_N0_GC_QBC_63_AY37/IO_L13N_T2L_N1_GC_QBC_63_AY38 +# | +# |-> OUT1 SYSCLK1_300_P/SYSCLK1_300_N 300.000Mhz - System Clock for second DDR4 MIG interface. +# | PINS: IO_L11P_T1U_N8_GC_64_AW20/IO_L11N_T1U_N9_GC_64_AW19 +# | +# |-> OUT2 SYSCLK2_300_P/SYSCLK2_300_N 300.000Mhz - System Clock for third DDR4 MIG interface. +# | PINS: IO_L13P_T2L_N0_GC_QBC_70_F32/IO_L13N_T2L_N1_GC_QBC_70_E32 +# | +# |-> OUT3 SYSCLK3_300_P/SYSCLK3_300_N 300.000Mhz - System Clock for fourth DDR4 MIG interface. +# PINS: IO_L13P_T2L_N0_GC_QBC_72_J16/IO_L13N_T2L_N1_GC_QBC_72_H16 +# +# +# - OUT1--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 161.1328125Mhz (Selectable based on state of FS[1:0]) +# PINS: MGTREFCLK1P_231_K11/MGTREFCLK1N_231_K10 +# +# - OUT2--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 90.0000Mhz (Fixed and Unchanged by FS[1:0]) +# PINS: Not Connected +# +# - OUT3--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 33.0000Mhz (Fixed and Unchanged by FS[1:0]) +# PINS: Not Connected +# +# 3) SI335A - SiLabs SI5335A-B06201-GM Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP1 REFCLK1 +# +# - FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups) +# FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS +# PINS: "QSFP1_FS[0]" - IO_L8P_T1L_N2_AD5P_64_AR22 +# PINS: "QSFP1_FS[1]" - IO_L7N_T1L_N1_QBC_AD13N_64_AU20 +# +# - RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. +# PINS: "QSFP1_RECLK_RESET" - IO_L8N_T1L_N3_AD5N_64_AR21 +# +# - OUT0--> 300.0000Mhz (Fixed and Unchanged by FS[1:0]) +# PINS: Not Connected +# +# - OUT1--> QSFP1_CLOCK_P/QSFP1_CLOCK_N @ 161.1328125Mhz (Selectable based on state of FS[1:0]) +# PINS: MGTREFCLK1P_230_P11/MGTREFCLK1N_230_P10 +# +# - OUT2--> 90.0000Mhz (Fixed and Unchanged by FS[1:0]) +# PINS: Not Connected +# +# - OUT3--> 33.0000Mhz (Fixed and Unchanged by FS[1:0]) +# PINS: Not Connected +# +# 4) PCIE Fingers PEX_REFCLK_P/PEX_REFCLK_P 100.000Mhz +# PINS: MGTREFCLK0P_226_AM11/MGTREFCLK0N_226_AM10 +# +# Revision 1.00 - Intial Release for AU200/250 +# Revision 2.00 - Updated XDC with card details. +# Revision 2.01 - Fixed modified QSFP1 IO Standards from POD12_DCI to LVCMOS18 +# Added Configuration Constraints +# Revision 2.02 - Fixed Bank 64 IOstandards from LVCMOS18 to LVCMOS12. +# Revision 2.03 - Fixed pins E38 and F38 IOstandards from DIFF_SSTL12_DCI to POD12_DC. +# Revision 2.04 - Removed SPI_OPCODE setting +# +################################################################################# + +# Bitstream Generation for QSPI +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] + +# +# Power Constraint to warn User if Design will possibly be over cards power limit, this assume the 2x4 PCIe AUX power is connected to the board. +# +set_operating_conditions -design_power_budget 160 +# +# LVDS Input SYSTEM CLOCKS for Memory Interfaces +# +# System clocks +# 300 MHz (DDR CH0) +set_property -dict {PACKAGE_PIN AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports clk_300mhz_0_n_i]; # Bank 42 VCCO - VCC1V2 Net "SYSCLK0_300_N" - IO_L13N_T2L_N1_GC_QBC_42 +set_property -dict {PACKAGE_PIN AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports clk_300mhz_0_p_i]; # Bank 42 VCCO - VCC1V2 Net "SYSCLK0_300_P" - IO_L13P_T2L_N0_GC_QBC_42 +# create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p_i] + +# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk_300mhz_0_int] + +set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVDS } [get_ports clk_300mhz_1_n_i ]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_N" - IO_L11N_T1U_N9_GC_64 +set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVDS } [get_ports clk_300mhz_1_p_i ]; # Bank 64 VCCO - VCC1V2 Net "SYSCLK1_300_P" - IO_L11P_T1U_N8_GC_64 + +# 300 MHz (DDR CH2) +# set_property -dict {PACKAGE_PIN E32 IOSTANDARD DIFF_POD12_DCI } [get_ports clk_300mhz_2_n_i ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_N" - IO_L13N_T2L_N1_GC_QBC_47 +# set_property -dict {PACKAGE_PIN F32 IOSTANDARD DIFF_POD12_DCI } [get_ports clk_300mhz_2_p_i ]; # Bank 47 VCCO - VCC1V2 Net "SYSCLK2_300_P" - IO_L13P_T2L_N0_GC_QBC_47 +# set_property -dict {PACKAGE_PIN H16 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK3_300_N ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_N" - IO_L13N_T2L_N1_GC_QBC_70 +# set_property -dict {PACKAGE_PIN J16 IOSTANDARD DIFF_POD12_DCI } [get_ports SYSCLK3_300_P ]; # Bank 70 VCCO - VCC1V2 Net "SYSCLK3_300_P" - IO_L13P_T2L_N0_GC_QBC_70 +# +# LVDS Input SYSTEM CLOCKS (1.8V bank 64) General Purpose +# +# set_property -dict {PACKAGE_PIN AV19 IOSTANDARD LVDS } [get_ports USER_SI570_CLOCK_N]; # Bank 64 VCCO - VCC1V2 Net "USER_SI570_CLOCK_N" - IO_L12N_T1U_N11_GC_64 +# set_property -dict {PACKAGE_PIN AU19 IOSTANDARD LVDS } [get_ports USER_SI570_CLOCK_P]; # Bank 64 VCCO - VCC1V2 Net "USER_SI570_CLOCK_P" - IO_L12P_T1U_N10_GC_64 +# +# MGT Clocks +# +# PCIe Clocks +# +# Input Clocks for Gen3 x16 +# PCIE_REFCLK -> PCIe 100Mhz Host clock +set_property PACKAGE_PIN AM10 [get_ports pcie_refclk_n_i ]; # Bank 226 Net "PEX_REFCLK_C_N" - MGTREFCLK0N_226 +set_property PACKAGE_PIN AM11 [get_ports pcie_refclk_p_i ]; # Bank 226 Net "PEX_REFCLK_C_P" - MGTREFCLK0P_226 +# +create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p_i] +# +set_false_path -from [get_ports pcie_resetn_i] +set_input_delay 0 [get_ports pcie_resetn_i] +# +# Input Clocks and Controls for QSFP28 Port 0 +# +# MGT_SI570_CLOCK0 -> MGT Ref Clock 0 156.25MHz Default (User re-programmable) +# QSFP0_CLOCK -> MGT Ref Clock 1 User selectable by QSFP0_FS +# +# set_property PACKAGE_PIN M10 [get_ports MGT_SI570_CLOCK0_N]; # Bank 231 Net "MGT_SI570_CLOCK0_C_N" - MGTREFCLK0N_231 +# set_property PACKAGE_PIN M11 [get_ports MGT_SI570_CLOCK0_P]; # Bank 231 Net "MGT_SI570_CLOCK0_C_P" - MGTREFCLK0P_231 +# set_property PACKAGE_PIN K10 [get_ports QSFP0_CLOCK_N ]; # Bank 231 Net "QSFP0_CLOCK_N" - MGTREFCLK1N_231 +# set_property PACKAGE_PIN K11 [get_ports QSFP0_CLOCK_P ]; # Bank 231 Net "QSFP0_CLOCK_P" - MGTREFCLK1P_231 +# +# QSFP0 Control Signals +# RESETL - Active Low Reset output from FPGA to QSFP Module +# MODPRSL - Active Low Module Present input from QSFP to FPGA +# INTL - Active Low Interrupt input from QSFP to FPGA +# LPMODE - Active High Control output from FPGA to QSFP Module to put the device in low power mode (Optics Off) +# MODSEL - Active Low Enable output from FPGA to QSFP Module to select device for I2C Sideband Communication +# +# set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS12 } [get_ports QSFP0_RESETL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_RESETL_LS" - IO_L22P_T3U_N6_DBC_AD0P_64 +# set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS12 } [get_ports QSFP0_MODPRSL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_MODPRSL_LS" - IO_L21N_T3L_N5_AD8N_64 +# set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS12 } [get_ports QSFP0_INTL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_INTL_LS" - IO_L21P_T3L_N4_AD8P_64 +# set_property -dict {PACKAGE_PIN BD18 IOSTANDARD LVCMOS12 } [get_ports QSFP0_LPMODE ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_LPMODE_LS" - IO_L20N_T3L_N3_AD1N_64 +# set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS12 } [get_ports QSFP0_MODSELL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_MODSELL_LS" - IO_L22N_T3U_N7_DBC_AD0N_64 +# # +# # QSFP0 Clock Control Signals +# # FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups) +# # FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS +# # RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. +# # +# set_property -dict {PACKAGE_PIN AT20 IOSTANDARD LVCMOS12 } [get_ports QSFP0_FS[0] ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_FS0" - IO_L10P_T1U_N6_QBC_AD4P_64 +# set_property -dict {PACKAGE_PIN AU22 IOSTANDARD LVCMOS12 } [get_ports QSFP0_FS[1] ]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_FS1" - IO_L9N_T1L_N5_AD12N_64 +# set_property -dict {PACKAGE_PIN AT22 IOSTANDARD LVCMOS12 } [get_ports QSFP0_REFCLK_RESET]; # Bank 64 VCCO - VCC1V2 Net "QSFP0_REFCLK_RESET" - IO_L9P_T1L_N4_AD12P_64 +# # +# # Input Clocks and Controls for QSFP28 Port 1 +# # +# # MGT_SI570_CLOCK1 -> MGT Ref Clock 0 156.25MHz Default (User re-programmable) +# # QSFP1_CLOCK -> MGT Ref Clock 1 User selectable by QSFP0_FS +# # +# set_property PACKAGE_PIN T10 [get_ports MGT_SI570_CLOCK1_N ]; # Bank 230 Net "MGT_SI570_CLOCK1_C_N" - MGTREFCLK0N_230 +# set_property PACKAGE_PIN T11 [get_ports MGT_SI570_CLOCK1_P ]; # Bank 230 Net "MGT_SI570_CLOCK1_C_P" - MGTREFCLK0P_230 +# set_property PACKAGE_PIN P10 [get_ports QSFP1_CLOCK_N ]; # Bank 230 Net "QSFP1_CLOCK_N" - MGTREFCLK1N_230 +# set_property PACKAGE_PIN P11 [get_ports QSFP1_CLOCK_P ]; # Bank 230 Net "QSFP1_CLOCK_P" - MGTREFCLK1P_230 +# # +# # QSFP1 Control Signals +# # RESETL - Active Low Reset output from FPGA to QSFP Module +# # MODPRSL - Active Low Module Present input from QSFP to FPGA +# # INTL - Active Low Interrupt input from QSFP to FPGA +# # LPMODE - Active High Control output from FPGA to QSFP Module to put the device in low power mode (Optics Off) +# # MODSEL - Active Low Enable output from FPGA to QSFP Module to select device for I2C Sideband Communication +# # +# set_property -dict {PACKAGE_PIN BC18 IOSTANDARD LVCMOS12 } [get_ports QSFP1_RESETL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_RESETL_LS" - IO_L15N_T2L_N5_AD11N_64 +# set_property -dict {PACKAGE_PIN BC19 IOSTANDARD LVCMOS12 } [get_ports QSFP1_MODPRSL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_MODPRSL_LS" - IO_L15P_T2L_N4_AD11P_64 +# set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS12 } [get_ports QSFP1_INTL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_INTL_LS" - IO_L14N_T2L_N3_GC_64 +# set_property -dict {PACKAGE_PIN AV22 IOSTANDARD LVCMOS12 } [get_ports QSFP1_LPMODE ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_LPMODE_LS" - IO_L14P_T2L_N2_GC_64 +# set_property -dict {PACKAGE_PIN AY20 IOSTANDARD LVCMOS12 } [get_ports QSFP1_MODSELL ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_MODSELL_LS" - IO_L16P_T2U_N6_QBC_AD3P_64 +# # +# # +# # QSFP1 Clock Control Signals +# # - FS[1:0] <-- Clock Select Pin FS[1:0] = 1X -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z due to 10K pullups) +# # FS[1:0] = 01 -> 156.250000 MHz 1.8V LVDS +# # - RESET <-- Device Reset - Asserting this pin (driving high) is required to change FS1,FS0 pin setting. +# # PINS: "QSFP1_RECLK_RESET" - IO_L8N_T1L_N3_AD5N_64_AR21 +# # +# set_property -dict {PACKAGE_PIN AR22 IOSTANDARD LVCMOS12 } [get_ports QSFP1_FS[0] ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_FS0" - IO_L8P_T1L_N2_AD5P_64 +# set_property -dict {PACKAGE_PIN AU20 IOSTANDARD LVCMOS12 } [get_ports QSFP1_FS[1] ]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_FS1" - IO_L7N_T1L_N1_QBC_AD13N_64 +# set_property -dict {PACKAGE_PIN AR21 IOSTANDARD LVCMOS12 } [get_ports QSFP1_REFCLK_RESET]; # Bank 64 VCCO - VCC1V2 Net "QSFP1_REFCLK_RESET" - IO_L8N_T1L_N3_AD5N_64 +# # +# # PCIe Connections Bank 64 +# # PCIE_PERSTN Active low input from PCIe Connector to Ultrascale+ Device to detect presence. +# # +set_property -dict {PACKAGE_PIN BD21 IOSTANDARD LVCMOS12 } [get_ports pcie_resetn_i ]; # Bank 64 VCCO - VCC1V2 Net "PCIE_PERST_LS" - IO_L23P_T3U_N8_64 +# # +# # Bank 65 Ultrascale+ Device SYSMON I2C Slave Interface to Satellite Controller to monitor Ultrascale+ Device Temperatures and Voltages. +# # SYSMON_SCL Slave I2C clock connection from Satellite Controller to Ultrascale+ Device +# # SYSMON_SDA Slave I2C data connection from Satellite Controller to Ultrascale+ Device +# # +# set_property -dict {PACKAGE_PIN AR26 IOSTANDARD LVCMOS12 } [get_ports SYSMON_SDA ]; # Bank 65 - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +# set_property -dict {PACKAGE_PIN AR25 IOSTANDARD LVCMOS12 } [get_ports SYSMON_SCL ]; # Bank 65 - IO_L23P_T3U_N8_I2C_SCLK_65 +# # +# # Bank 64 Ultrascale+ Device I2C Slave Interface to Satellite Controller. +# # I2C_FPGA_SCL Slave I2C clock connection from Satellite Controller to Ultrascale+ Device +# # I2C_FPGA_SDA Slave I2C data connection from Satellite Controller to Ultrascale+ Device +# # I2C_MAIN_INT_B Slave I2C active low system interrupt output from Ultrascale+ Device to Satellite Controller +# # +# set_property -dict {PACKAGE_PIN BF19 IOSTANDARD LVCMOS12 } [get_ports I2C_MAIN_RESETN ]; # Bank 64 VCCO - VCC1V2 Net "I2C_MAIN_RESET_B_LS" - IO_L19N_T3L_N1_DBC_AD9N_64 +# set_property -dict {PACKAGE_PIN BF20 IOSTANDARD LVCMOS12 } [get_ports I2C_FPGA_SCL ]; # Bank 64 VCCO - VCC1V2 Net "I2C_FPGA_SCL_LS" - IO_L19P_T3L_N0_DBC_AD9P_64 +# set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS12 } [get_ports I2C_FPGA_SDA ]; # Bank 64 VCCO - VCC1V2 Net "I2C_FPGA_SDA_LS" - IO_T2U_N12_64 + +# # +# # Bank 65 FPGA UART Interface to FTDI FT4232 Port 3 of 4 (User selectable Baud) +# # USB_UART_RX Input from FT4232 UART to FPGA +# # USB_UART_TX Output from FPGA to FT4232 UART +# # +# set_property -dict {PACKAGE_PIN BB20 IOSTANDARD LVCMOS12 } [get_ports USB_UART_RX ]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_RX" - IO_T3U_N12_64 +# set_property -dict {PACKAGE_PIN BF18 IOSTANDARD LVCMOS12 } [get_ports USB_UART_TX ]; # Bank 64 VCCO - VCC1V2 Net "USB_UART_TX" - IO_L24N_T3U_N11_64 +# # +# # Bank 65 Ultrascale+ Device to Satellite Controller CMS UART Interface (115200, No parity, 8 bits, 1 stop bit) +# # FPGA_RXD_MSP Input from Satellite Controller UART to Ultrascale+ Device +# # FPGA_TXD_MSP Output from Ultrascale+ Device to Satellite Controller UART +# # This interface is used for the CMS command path, refer to https://www.xilinx.com/products/intellectual-property/cms-subsystem.html and Xilinx PG348 +# # +# set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 } [get_ports FPGA_TXD_MSP ]; # Bank 64 VCCO - VCC1V2 Net "FPGA_TXD_MSP" - IO_L18N_T2U_N11_AD2N_64 +# set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12 } [get_ports FPGA_RXD_MSP ]; # Bank 64 VCCO - VCC1V2 Net "FPGA_RXD_MSP" - IO_L18P_T2U_N10_AD2P_64 +# # +# # DDR4_RESET_GATE Active High Output from Ultrascale+ Device to hold all External DDR4 interfaces in Self refresh. +# # This Output disconnects the Memory interface reset and holds it in active and pulls the Clock Enables signal on the Memory Interfaces. +# # Refer to XAPP1321 for details on Save Restore and Self refresh mode. +# # +# set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS12 } [get_ports DDR4_RESET_GATE ]; # Bank 64 VCCO - VCC1V2 Net "DDR4_RESET_GATE" - IO_L7P_T1L_N0_QBC_AD13P_64 +# # +# # GPIO_MSP0/1/2/3 General purpose IO interconnects between Ultrascale+ Device and Satellite Controller. Currently not used. +# # +# set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12 } [get_ports GPIO_MSP[0] ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP0" - IO_T0U_N12_VRP_64 +# set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12 } [get_ports GPIO_MSP[1] ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP1" - IO_L6N_T0U_N11_AD6N_64 +# set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12 } [get_ports GPIO_MSP[2] ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP2" - IO_L6P_T0U_N10_AD6P_64 +# set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12 } [get_ports GPIO_MSP[3] ]; # Bank 64 VCCO - VCC1V2 Net "GPIO_MSP3" - IO_L5N_T0U_N9_AD14N_64 +# # +# # SW_DP0/1/2/3 General purpose IO interconnects between Ultrascale+ Device and Satellite Controller. Currently not used. +# # +# set_property -dict {PACKAGE_PIN AN22 IOSTANDARD LVCMOS12 } [get_ports SW_DP[0] ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP0" - IO_L5P_T0U_N8_AD14P_64 +# set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS12 } [get_ports SW_DP[1] ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP1" - IO_L4N_T0U_N7_DBC_AD7N_64 +# set_property -dict {PACKAGE_PIN AL19 IOSTANDARD LVCMOS12 } [get_ports SW_DP[2] ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP2" - IO_L4P_T0U_N6_DBC_AD7P_64 +# set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS12 } [get_ports SW_DP[3] ]; # Bank 64 VCCO - VCC1V2 Net "SW_DP3" - IO_L3N_T0L_N5_AD15N_64 +# # +# # CPU_RESET_FPGA Connects to SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Controller +# # Designed to be a active low reset input to the FPGA. +# # +# # set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVCMOS12 } [get_ports CPU_RESET_FPGA ]; # Bank 64 VCCO - VCC1V2 Net "CPU_RESET_FPGA" - IO_L2N_T0L_N3_64_AL20 +# # +# # Test point inaccessable to user due to Heatsink. +# # +# # set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS12 } [get_ports TESTCLK_OUT ]; # Bank 64 VCCO - VCC1V2 Net "TESTCLK_OUT" - IO_L1P_T0L_N0_DBC_64 +# # +# # +# # Leave Un-instantiated for proper Card operation or signal contention with Satellite Controller +# # +# set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS12 } [get_ports MSP_RSTn ]; # Bank 64 VCCO - VCC1V2 Net "N32064223" - IO_L3P_T0L_N4_AD15P_64 +# set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS12 } [get_ports SW_SET1_FPGA ]; # Bank 64 VCCO - VCC1V2 Net "SW_SET1_FPGA" - IO_L2P_T0L_N2_64 +# set_property -dict {PACKAGE_PIN BC21 IOSTANDARD LVCMOS12 } [get_ports STATUS_LED0_FPGA ]; # Bank 64 VCCO - VCC1V2 Net "STATUS_LED0_FPGA" - IO_L17N_T2U_N9_AD10N_64 +# set_property -dict {PACKAGE_PIN BB21 IOSTANDARD LVCMOS12 } [get_ports STATUS_LED1_FPGA ]; # Bank 64 VCCO - VCC1V2 Net "STATUS_LED1_FPGA" - IO_L17P_T2U_N8_AD10P_64 +# set_property -dict {PACKAGE_PIN BA20 IOSTANDARD LVCMOS12 } [get_ports STATUS_LED2_FPGA ]; # Bank 64 VCCO - VCC1V2 Net "STATUS_LED2_FPGA" - IO_L16N_T2U_N7_QBC_AD3N_64 +# # +# # DDR4 RDIMM Controller 3, 72-bit Data Interface, x4 Componets, Single Rank +# # <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# # JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# # Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# # +# set_property -dict {PACKAGE_PIN B24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[34] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ34" - IO_L23N_T3U_N9_72 +# set_property -dict {PACKAGE_PIN B25 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[35] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ35" - IO_L23P_T3U_N8_72 +# set_property -dict {PACKAGE_PIN A24 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[8] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C4" - IO_L22N_T3U_N7_DBC_AD0N_72 +# set_property -dict {PACKAGE_PIN A25 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[8] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T4" - IO_L22P_T3U_N6_DBC_AD0P_72 +# set_property -dict {PACKAGE_PIN A22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[33] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ33" - IO_L24N_T3U_N11_72 +# set_property -dict {PACKAGE_PIN A23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[32] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ32" - IO_L24P_T3U_N10_72 +# set_property -dict {PACKAGE_PIN C23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[39] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ39" - IO_L21N_T3L_N5_AD8N_72 +# set_property -dict {PACKAGE_PIN C24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[38] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ38" - IO_L21P_T3L_N4_AD8P_72 +# set_property -dict {PACKAGE_PIN B22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[36] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ36" - IO_L20N_T3L_N3_AD1N_72 +# set_property -dict {PACKAGE_PIN C22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[37] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ37" - IO_L20P_T3L_N2_AD1P_72 +# set_property -dict {PACKAGE_PIN D23 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[9] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C13" - IO_L19N_T3L_N1_DBC_AD9N_72 +# set_property -dict {PACKAGE_PIN D24 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[9] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T13" - IO_L19P_T3L_N0_DBC_AD9P_72 +# set_property -dict {PACKAGE_PIN E22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[57] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ57" - IO_L17N_T2U_N9_AD10N_72 +# set_property -dict {PACKAGE_PIN F22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[56] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ56" - IO_L17P_T2U_N8_AD10P_72 +# set_property -dict {PACKAGE_PIN E23 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[14]]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C7" - IO_L16N_T2U_N7_QBC_AD3N_72 +# set_property -dict {PACKAGE_PIN F23 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[14]]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T7" - IO_L16P_T2U_N6_QBC_AD3P_72 +# set_property -dict {PACKAGE_PIN G21 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[59] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ59" - IO_L18N_T2U_N11_AD2N_72 +# set_property -dict {PACKAGE_PIN G22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[58] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ58" - IO_L18P_T2U_N10_AD2P_72 +# set_property -dict {PACKAGE_PIN E25 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[61] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ61" - IO_L15N_T2L_N5_AD11N_72 +# set_property -dict {PACKAGE_PIN F25 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[62] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ62" - IO_L15P_T2L_N4_AD11P_72 +# set_property -dict {PACKAGE_PIN F24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[60] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ60" - IO_L14N_T2L_N3_GC_72 +# set_property -dict {PACKAGE_PIN G25 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[63] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ63" - IO_L14P_T2L_N2_GC_72 +# set_property -dict {PACKAGE_PIN H22 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[15]]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C16" - IO_L13N_T2L_N1_GC_QBC_72 +# set_property -dict {PACKAGE_PIN H23 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[15]]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T16" - IO_L13P_T2L_N0_GC_QBC_72 +# set_property -dict {PACKAGE_PIN J23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[9] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ9" - IO_L11N_T1U_N9_GC_72 +# set_property -dict {PACKAGE_PIN J24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[8] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ8" - IO_L11P_T1U_N8_GC_72 +# set_property -dict {PACKAGE_PIN H21 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[2] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C1" - IO_L10N_T1U_N7_QBC_AD4N_72 +# set_property -dict {PACKAGE_PIN J21 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[2] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T1" - IO_L10P_T1U_N6_QBC_AD4P_72 +# set_property -dict {PACKAGE_PIN G24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[11] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ11" - IO_L12N_T1U_N11_GC_72 +# set_property -dict {PACKAGE_PIN H24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[10] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ10" - IO_L12P_T1U_N10_GC_72 +# set_property -dict {PACKAGE_PIN L23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[13] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ13" - IO_L9N_T1L_N5_AD12N_72 +# set_property -dict {PACKAGE_PIN L24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[12] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ12" - IO_L9P_T1L_N4_AD12P_72 +# set_property -dict {PACKAGE_PIN K21 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[15] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ15" - IO_L8N_T1L_N3_AD5N_72 +# set_property -dict {PACKAGE_PIN K22 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[14] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ14" - IO_L8P_T1L_N2_AD5P_72 +# set_property -dict {PACKAGE_PIN L22 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[3] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C10" - IO_L7N_T1L_N1_QBC_AD13N_72 +# set_property -dict {PACKAGE_PIN M22 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[3] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T10" - IO_L7P_T1L_N0_QBC_AD13P_72 +# set_property -dict {PACKAGE_PIN N24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[1] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ1" - IO_L5N_T0U_N9_AD14N_72 +# set_property -dict {PACKAGE_PIN P24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[0] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ0" - IO_L5P_T0U_N8_AD14P_72 +# set_property -dict {PACKAGE_PIN R22 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[0] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_72 +# set_property -dict {PACKAGE_PIN T22 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[0] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_72 +# set_property -dict {PACKAGE_PIN R23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[3] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ3" - IO_L6N_T0U_N11_AD6N_72 +# set_property -dict {PACKAGE_PIN T24 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[2] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ2" - IO_L6P_T0U_N10_AD6P_72 +# set_property -dict {PACKAGE_PIN N23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[4] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ4" - IO_L3N_T0L_N5_AD15N_72 +# set_property -dict {PACKAGE_PIN P23 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[6] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ6" - IO_L3P_T0L_N4_AD15P_72 +# set_property -dict {PACKAGE_PIN P21 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[5] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ5" - IO_L2N_T0L_N3_72 +# set_property -dict {PACKAGE_PIN R21 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[7] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQ7" - IO_L2P_T0L_N2_72 +# set_property -dict {PACKAGE_PIN N21 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[1] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_C9" - IO_L1N_T0L_N1_DBC_72 +# set_property -dict {PACKAGE_PIN N22 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[1] ]; # Bank 72 VCCO - VCC1V2 Net "DDR4_C3_DQS_T9" - IO_L1P_T0L_N0_DBC_72 +# set_property -dict {PACKAGE_PIN B21 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[43] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ43" - IO_L23N_T3U_N9_71 +# set_property -dict {PACKAGE_PIN C21 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[42] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ42" - IO_L23P_T3U_N8_71 +# set_property -dict {PACKAGE_PIN B17 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[10]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_71 +# set_property -dict {PACKAGE_PIN C17 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[10]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_71 +# #set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS12 } [get_ports c3_ddr4_event_n ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_EVENT_B" - IO_T3U_N12_71 +# set_property -dict {PACKAGE_PIN C18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[41] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ41" - IO_L24N_T3U_N11_71 +# set_property -dict {PACKAGE_PIN C19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[40] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ40" - IO_L24P_T3U_N10_71 +# set_property -dict {PACKAGE_PIN A20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[46] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ46" - IO_L21N_T3L_N5_AD8N_71 +# set_property -dict {PACKAGE_PIN B20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[47] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ47" - IO_L21P_T3L_N4_AD8P_71 +# set_property -dict {PACKAGE_PIN A17 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[45] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ45" - IO_L20N_T3L_N3_AD1N_71 +# set_property -dict {PACKAGE_PIN A18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[44] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ44" - IO_L20P_T3L_N2_AD1P_71 +# set_property -dict {PACKAGE_PIN A19 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[11]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_71 +# set_property -dict {PACKAGE_PIN B19 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[11]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_71 +# set_property -dict {PACKAGE_PIN E20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[51] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ51" - IO_L17N_T2U_N9_AD10N_71 +# set_property -dict {PACKAGE_PIN F20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[49] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ49" - IO_L17P_T2U_N8_AD10P_71 +# set_property -dict {PACKAGE_PIN F17 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[12]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C6" - IO_L16N_T2U_N7_QBC_AD3N_71 +# set_property -dict {PACKAGE_PIN F18 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[12]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T6" - IO_L16P_T2U_N6_QBC_AD3P_71 +# set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS12 } [get_ports c3_ddr4_reset_n ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_RESET_N" - IO_T2U_N12_71 +# set_property -dict {PACKAGE_PIN E17 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[48] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ48" - IO_L18N_T2U_N11_AD2N_71 +# set_property -dict {PACKAGE_PIN E18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[50] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ50" - IO_L18P_T2U_N10_AD2P_71 +# set_property -dict {PACKAGE_PIN D19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[52] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ52" - IO_L15N_T2L_N5_AD11N_71 +# set_property -dict {PACKAGE_PIN D20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[53] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ53" - IO_L15P_T2L_N4_AD11P_71 +# set_property -dict {PACKAGE_PIN H18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[54] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ54" - IO_L14N_T2L_N3_GC_71 +# set_property -dict {PACKAGE_PIN J18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[55] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ55" - IO_L14P_T2L_N2_GC_71 +# set_property -dict {PACKAGE_PIN G19 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[13]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C15" - IO_L13N_T2L_N1_GC_QBC_71 +# set_property -dict {PACKAGE_PIN H19 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[13]]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T15" - IO_L13P_T2L_N0_GC_QBC_71 +# set_property -dict {PACKAGE_PIN F19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[18] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ18" - IO_L11N_T1U_N9_GC_71 +# set_property -dict {PACKAGE_PIN G20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[16] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ16" - IO_L11P_T1U_N8_GC_71 +# set_property -dict {PACKAGE_PIN K20 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[4] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_71 +# set_property -dict {PACKAGE_PIN L20 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[4] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_71 +# set_property -dict {PACKAGE_PIN G17 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[19] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ19" - IO_L12N_T1U_N11_GC_71 +# set_property -dict {PACKAGE_PIN H17 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[17] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ17" - IO_L12P_T1U_N10_GC_71 +# set_property -dict {PACKAGE_PIN J19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[23] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ23" - IO_L9N_T1L_N5_AD12N_71 +# set_property -dict {PACKAGE_PIN J20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[20] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ20" - IO_L9P_T1L_N4_AD12P_71 +# set_property -dict {PACKAGE_PIN L18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[22] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ22" - IO_L8N_T1L_N3_AD5N_71 +# set_property -dict {PACKAGE_PIN L19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[21] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ21" - IO_L8P_T1L_N2_AD5P_71 +# set_property -dict {PACKAGE_PIN K17 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[5] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_71 +# set_property -dict {PACKAGE_PIN K18 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[5] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_71 +# set_property -dict {PACKAGE_PIN M19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[24] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ24" - IO_L5N_T0U_N9_AD14N_71 +# set_property -dict {PACKAGE_PIN M20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[25] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ25" - IO_L5P_T0U_N8_AD14P_71 +# set_property -dict {PACKAGE_PIN P18 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[6] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C3" - IO_L4N_T0U_N7_DBC_AD7N_71 +# set_property -dict {PACKAGE_PIN P19 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[6] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T3" - IO_L4P_T0U_N6_DBC_AD7P_71 +# set_property -dict {PACKAGE_PIN R17 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[27] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ27" - IO_L6N_T0U_N11_AD6N_71 +# set_property -dict {PACKAGE_PIN R18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[26] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ26" - IO_L6P_T0U_N10_AD6P_71 +# set_property -dict {PACKAGE_PIN N18 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[30] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ30" - IO_L3N_T0L_N5_AD15N_71 +# set_property -dict {PACKAGE_PIN N19 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[31] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ31" - IO_L3P_T0L_N4_AD15P_71 +# set_property -dict {PACKAGE_PIN R20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[28] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ28" - IO_L2N_T0L_N3_71 +# set_property -dict {PACKAGE_PIN T20 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[29] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQ29" - IO_L2P_T0L_N2_71 +# set_property -dict {PACKAGE_PIN M17 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[7] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_C12" - IO_L1N_T0L_N1_DBC_71 +# set_property -dict {PACKAGE_PIN N17 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[7] ]; # Bank 71 VCCO - VCC1V2 Net "DDR4_C3_DQS_T12" - IO_L1P_T0L_N0_DBC_71 +# set_property -dict {PACKAGE_PIN B16 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_cs_n[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CS_B0" - IO_L23N_T3U_N9_70 +# set_property -dict {PACKAGE_PIN C16 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_odt[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ODT0" - IO_L23P_T3U_N8_70 +# set_property -dict {PACKAGE_PIN C13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[11] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR11" - IO_L22N_T3U_N7_DBC_AD0N_70 +# set_property -dict {PACKAGE_PIN D13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_bg[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_BG0" - IO_L22P_T3U_N6_DBC_AD0P_70 +# #set_property -dict {PACKAGE_PIN D16 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_cs_n[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CS_B1" - IO_T3U_N12_70 +# set_property -dict {PACKAGE_PIN A13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[9] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR9" - IO_L24N_T3U_N11_70 +# set_property -dict {PACKAGE_PIN B13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[12] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR12" - IO_L24P_T3U_N10_70 +# set_property -dict {PACKAGE_PIN A15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[3] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR3" - IO_L21N_T3L_N5_AD8N_70 +# set_property -dict {PACKAGE_PIN B15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR1" - IO_L21P_T3L_N4_AD8P_70 +# set_property -dict {PACKAGE_PIN C14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[4] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR4" - IO_L20N_T3L_N3_AD1N_70 +# set_property -dict {PACKAGE_PIN D14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[10] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR10" - IO_L20P_T3L_N2_AD1P_70 +# set_property -dict {PACKAGE_PIN A14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[5] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR5" - IO_L19N_T3L_N1_DBC_AD9N_70 +# set_property -dict {PACKAGE_PIN B14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[6] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR6" - IO_L19P_T3L_N0_DBC_AD9P_70 +# set_property -dict {PACKAGE_PIN E15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[15] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR15" - IO_L17N_T2U_N9_AD10N_70 +# #set_property -dict {PACKAGE_PIN E16 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_odt[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ODT1" - IO_L17P_T2U_N8_AD10P_70 +# #set_property -dict {PACKAGE_PIN G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_70 +# #set_property -dict {PACKAGE_PIN G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_70 +# set_property -dict {PACKAGE_PIN D15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[14] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR14" - IO_T2U_N12_70 +# set_property -dict {PACKAGE_PIN F14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[2] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR2" - IO_L18N_T2U_N11_AD2N_70 +# set_property -dict {PACKAGE_PIN F15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[16] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR16" - IO_L18P_T2U_N10_AD2P_70 +# set_property -dict {PACKAGE_PIN E13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[7] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR7" - IO_L15N_T2L_N5_AD11N_70 +# set_property -dict {PACKAGE_PIN F13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[8] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR8" - IO_L15P_T2L_N4_AD11P_70 +# set_property -dict {PACKAGE_PIN H13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_act_n ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ACT_B" - IO_L14N_T2L_N3_GC_70 +# set_property -dict {PACKAGE_PIN H14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_ba[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_BA1" - IO_L14P_T2L_N2_GC_70 +# set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS12 } [get_ports c3_ddr4_alert_n ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ALERT_B" - IO_L11N_T1U_N9_GC_70 +# #set_property -dict {PACKAGE_PIN G16 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[17] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR17" - IO_L11P_T1U_N8_GC_70 +# set_property -dict {PACKAGE_PIN L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_c[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CK_C0" - IO_L10N_T1U_N7_QBC_AD4N_70 +# set_property -dict {PACKAGE_PIN L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c3_ddr4_ck_t[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CK_T0" - IO_L10P_T1U_N6_QBC_AD4P_70 +# set_property -dict {PACKAGE_PIN K13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_cke[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CKE0" - IO_T1U_N12_70 +# set_property -dict {PACKAGE_PIN J13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_bg[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_BG1" - IO_L12N_T1U_N11_GC_70 +# set_property -dict {PACKAGE_PIN J14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_parity ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_PAR" - IO_L12P_T1U_N10_GC_70 +# set_property -dict {PACKAGE_PIN J15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_ba[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_BA0" - IO_L9N_T1L_N5_AD12N_70 +# set_property -dict {PACKAGE_PIN K16 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[13] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR13" - IO_L9P_T1L_N4_AD12P_70 +# #set_property -dict {PACKAGE_PIN M13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_cs_n[3] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CS_B3" - IO_L8N_T1L_N3_AD5N_70 +# #set_property -dict {PACKAGE_PIN M14 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_cs_n[2] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CS_B2" - IO_L8P_T1L_N2_AD5P_70 +# set_property -dict {PACKAGE_PIN K15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_adr[0] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_ADR0" - IO_L7N_T1L_N1_QBC_AD13N_70 +# #set_property -dict {PACKAGE_PIN L15 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_cke[1] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_CKE1" - IO_L7P_T1L_N0_QBC_AD13P_70 +# set_property -dict {PACKAGE_PIN N13 IOSTANDARD SSTL12_DCI } [get_ports c3_ddr4_dq[66] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ66" - IO_L5N_T0U_N9_AD14N_70 +# set_property -dict {PACKAGE_PIN N14 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[67] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ67" - IO_L5P_T0U_N8_AD14P_70 +# set_property -dict {PACKAGE_PIN P15 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[16]]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQS_C8" - IO_L4N_T0U_N7_DBC_AD7N_70 +# set_property -dict {PACKAGE_PIN R16 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[16]]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQS_T8" - IO_L4P_T0U_N6_DBC_AD7P_70 +# set_property -dict {PACKAGE_PIN M16 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[64] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ64" - IO_L6N_T0U_N11_AD6N_70 +# set_property -dict {PACKAGE_PIN N16 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[65] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ65" - IO_L6P_T0U_N10_AD6P_70 +# set_property -dict {PACKAGE_PIN P13 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[70] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ70" - IO_L3N_T0L_N5_AD15N_70 +# set_property -dict {PACKAGE_PIN P14 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[71] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ71" - IO_L3P_T0L_N4_AD15P_70 +# set_property -dict {PACKAGE_PIN R15 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[69] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ69" - IO_L2N_T0L_N3_70 +# set_property -dict {PACKAGE_PIN T15 IOSTANDARD POD12_DCI } [get_ports c3_ddr4_dq[68] ]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQ68" - IO_L2P_T0L_N2_70 +# set_property -dict {PACKAGE_PIN R13 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_c[17]]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQS_C17" - IO_L1N_T0L_N1_DBC_70 +# set_property -dict {PACKAGE_PIN T13 IOSTANDARD DIFF_POD12_DCI } [get_ports c3_ddr4_dqs_t[17]]; # Bank 70 VCCO - VCC1V2 Net "DDR4_C3_DQS_T17" - IO_L1P_T0L_N0_DBC_70 +# # +# # DDR4 RDIMM Controller 1, 72-bit Data Interface, x4 Componets, Single Rank +# # <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# # JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# # Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# # + +set_property -dict {PACKAGE_PIN AN13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[24] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ24" - IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN AM13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[26] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ26" - IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C3" - IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T3" - IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN AR13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[25] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ25" - IO_L24N_T3U_N11_67 +set_property -dict {PACKAGE_PIN AP13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[27] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ27" - IO_L24P_T3U_N10_67 +set_property -dict {PACKAGE_PIN AM14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[28] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ28" - IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN AL14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[30] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ30" - IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN AT15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[31] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ31" - IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN AR15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[29] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ29" - IO_L20P_T3L_N2_AD1P_67 +set_property -dict {PACKAGE_PIN AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C12" - IO_L19N_T3L_N1_DBC_AD9N_67 +set_property -dict {PACKAGE_PIN AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T12" - IO_L19P_T3L_N0_DBC_AD9P_67 +set_property -dict {PACKAGE_PIN AV13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[9] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ9" - IO_L17N_T2U_N9_AD10N_67 +set_property -dict {PACKAGE_PIN AU13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[8] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ8" - IO_L17P_T2U_N8_AD10P_67 +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C1" - IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T1" - IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN AW13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[10] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ10" - IO_L18N_T2U_N11_AD2N_67 +set_property -dict {PACKAGE_PIN AW14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[11] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ11" - IO_L18P_T2U_N10_AD2P_67 +set_property -dict {PACKAGE_PIN AV14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[14] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ14" - IO_L15N_T2L_N5_AD11N_67 +set_property -dict {PACKAGE_PIN AU14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[12] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ12" - IO_L15P_T2L_N4_AD11P_67 +set_property -dict {PACKAGE_PIN BA11 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[15] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ15" - IO_L14N_T2L_N3_GC_67 +set_property -dict {PACKAGE_PIN AY11 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[13] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ13" - IO_L14P_T2L_N2_GC_67 +set_property -dict {PACKAGE_PIN AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C10" - IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T10" - IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN BA13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[18] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ18" - IO_L11N_T1U_N9_GC_67 +set_property -dict {PACKAGE_PIN BA14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[19] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ19" - IO_L11P_T1U_N8_GC_67 +set_property -dict {PACKAGE_PIN BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_67 +set_property -dict {PACKAGE_PIN BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_67 +set_property -dict {PACKAGE_PIN BB12 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[17] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ17" - IO_L12N_T1U_N11_GC_67 +set_property -dict {PACKAGE_PIN BA12 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[16] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ16" - IO_L12P_T1U_N10_GC_67 +set_property -dict {PACKAGE_PIN BA7 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[22] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ22" - IO_L9N_T1L_N5_AD12N_67 +set_property -dict {PACKAGE_PIN BA8 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[23] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ23" - IO_L9P_T1L_N4_AD12P_67 +set_property -dict {PACKAGE_PIN BC9 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[20] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ20" - IO_L8N_T1L_N3_AD5N_67 +set_property -dict {PACKAGE_PIN BB9 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[21] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ21" - IO_L8P_T1L_N2_AD5P_67 +set_property -dict {PACKAGE_PIN BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_67 +set_property -dict {PACKAGE_PIN BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_67 +set_property -dict {PACKAGE_PIN BD7 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ1" - IO_L5N_T0U_N9_AD14N_67 +set_property -dict {PACKAGE_PIN BC7 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[2] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ2" - IO_L5P_T0U_N8_AD14P_67 +set_property -dict {PACKAGE_PIN BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_67 +set_property -dict {PACKAGE_PIN BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_67 +set_property -dict {PACKAGE_PIN BD8 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[3] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ3" - IO_L6N_T0U_N11_AD6N_67 +set_property -dict {PACKAGE_PIN BD9 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[0] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ0" - IO_L6P_T0U_N10_AD6P_67 +set_property -dict {PACKAGE_PIN BF7 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[7] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ7" - IO_L3N_T0L_N5_AD15N_67 +set_property -dict {PACKAGE_PIN BE7 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[6] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ6" - IO_L3P_T0L_N4_AD15P_67 +set_property -dict {PACKAGE_PIN BE10 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[5] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ5" - IO_L2N_T0L_N3_67 +set_property -dict {PACKAGE_PIN BD10 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[4] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQ4" - IO_L2P_T0L_N2_67 +set_property -dict {PACKAGE_PIN BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_C9" - IO_L1N_T0L_N1_DBC_67 +set_property -dict {PACKAGE_PIN BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[1] ]; # Bank 67 VCCO - VCC1V2 Net "DDR4_C1_DQS_T9" - IO_L1P_T0L_N0_DBC_67 +set_property -dict {PACKAGE_PIN AM15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[56] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ56" - IO_L23N_T3U_N9_66 +set_property -dict {PACKAGE_PIN AL15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[57] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ57" - IO_L23P_T3U_N8_66 +set_property -dict {PACKAGE_PIN AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[14]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C7" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -dict {PACKAGE_PIN AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[14]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T7" - IO_L22P_T3U_N6_DBC_AD0P_66 +#set_property -dict {PACKAGE_PIN AN18 IOSTANDARD LVCMOS12 } [get_ports c1_ddr4_event_n ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_EVENT_B" - IO_T3U_N12_66 +set_property -dict {PACKAGE_PIN AN16 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[59] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ59" - IO_L24N_T3U_N11_66 +set_property -dict {PACKAGE_PIN AN17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[58] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ58" - IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN AL16 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[63] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ63" - IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN AL17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[62] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ62" - IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AR18 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[60] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ60" - IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AP18 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[61] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ61" - IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[15]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C16" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -dict {PACKAGE_PIN AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[15]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T16" - IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN AU16 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[50] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ50" - IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN AU17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[51] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ51" - IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[12]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C6" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -dict {PACKAGE_PIN AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[12]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T6" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVCMOS12 } [get_ports c1_ddr4_reset_n ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_RESET_N" - IO_T2U_N12_66 +set_property -dict {PACKAGE_PIN AV16 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[48] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ48" - IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN AV17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[49] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ49" - IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN AT17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[55] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ55" - IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN AT18 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[54] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ54" - IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[53] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ53" - IO_L14N_T2L_N3_GC_66 +set_property -dict {PACKAGE_PIN BB17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[52] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ52" - IO_L14P_T2L_N2_GC_66 +set_property -dict {PACKAGE_PIN AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[13]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C15" - IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[13]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T15" - IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN AY17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[40] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ40" - IO_L11N_T1U_N9_GC_66 +set_property -dict {PACKAGE_PIN AY18 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[42] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ42" - IO_L11P_T1U_N8_GC_66 +set_property -dict {PACKAGE_PIN BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[10]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C5" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[10]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T5" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN BA17 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[41] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ41" - IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN BA18 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[43] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ43" - IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN BB15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[45] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ45" - IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN BA15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[44] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ44" - IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN BD11 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[47] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ47" - IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN BC11 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[46] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ46" - IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[11]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C14" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[11]]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T14" - IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN BD13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[35] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ35" - IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN BD14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[33] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ33" - IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[8] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property -dict {PACKAGE_PIN BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[8] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property -dict {PACKAGE_PIN BF12 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[34] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ34" - IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN BE13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[32] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ32" - IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN BD15 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[36] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ36" - IO_L3N_T0L_N5_AD15N_66 +set_property -dict {PACKAGE_PIN BD16 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[37] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ37" - IO_L3P_T0L_N4_AD15P_66 +set_property -dict {PACKAGE_PIN BF13 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[39] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ39" - IO_L2N_T0L_N3_66 +set_property -dict {PACKAGE_PIN BF14 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[38] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQ38" - IO_L2P_T0L_N2_66 +set_property -dict {PACKAGE_PIN BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[9] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property -dict {PACKAGE_PIN BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[9] ]; # Bank 66 VCCO - VCC1V2 Net "DDR4_C1_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +set_property -dict {PACKAGE_PIN AM25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[15] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR15" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +set_property -dict {PACKAGE_PIN AL25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[14] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR14" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +set_property -dict {PACKAGE_PIN AP26 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_ba[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BA1" - IO_T3U_N12_PERSTN0_65 +set_property -dict {PACKAGE_PIN AN26 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[3] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR3" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property -dict {PACKAGE_PIN AM26 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[10] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR10" - IO_L24P_T3U_N10_EMCCLK_65 +#set_property -dict {PACKAGE_PIN AP24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_odt[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ODT1" - IO_L21N_T3L_N5_AD8N_D07_65 +#set_property -dict {PACKAGE_PIN AP23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_cs_n[3] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B3" - IO_L21P_T3L_N4_AD8P_D06_65 +#set_property -dict {PACKAGE_PIN AM24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[17] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR17" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property -dict {PACKAGE_PIN AL24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[13] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR13" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property -dict {PACKAGE_PIN AN24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR0" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property -dict {PACKAGE_PIN AN23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[16] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR16" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +#set_property -dict {PACKAGE_PIN AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_c[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_C1" - IO_L17N_T2U_N9_AD10N_D15_65 +#set_property -dict {PACKAGE_PIN AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_t[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_T1" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property -dict {PACKAGE_PIN AT23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_parity]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_PAR" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +#set_property -dict {PACKAGE_PIN AR23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_cs_n[2] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B2" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property -dict {PACKAGE_PIN AP25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_cs_n[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B1" - IO_T2U_N12_CSI_ADV_B_65 +set_property -dict {PACKAGE_PIN AU24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_ba[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BA0" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property -dict {PACKAGE_PIN AT24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR1" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property -dict {PACKAGE_PIN AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_c[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_C0" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +set_property -dict {PACKAGE_PIN AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c1_ddr4_ck_t[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CK_T0" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property -dict {PACKAGE_PIN AV24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[6] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR6" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property -dict {PACKAGE_PIN AV23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_cs_n[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CS_B0" - IO_L14P_T2L_N2_GC_A04_D20_65 +set_property -dict {PACKAGE_PIN AW26 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_bg[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BG1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property -dict {PACKAGE_PIN AW25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_act_n ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ACT_B" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +set_property -dict {PACKAGE_PIN AY26 IOSTANDARD LVCMOS12 } [get_ports c1_ddr4_alert_n ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ALERT_B" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property -dict {PACKAGE_PIN AY25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[8] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property -dict {PACKAGE_PIN AY23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[5] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR5" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property -dict {PACKAGE_PIN AY22 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[4] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR4" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property -dict {PACKAGE_PIN BA25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[11] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR11" - IO_T1U_N12_SMBALERT_65 +set_property -dict {PACKAGE_PIN AW24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[2] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR2" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property -dict {PACKAGE_PIN AW23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_odt[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ODT0" - IO_L12P_T1U_N10_GC_A08_D24_65 +set_property -dict {PACKAGE_PIN BB25 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_cke[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CKE0" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +#set_property -dict {PACKAGE_PIN BB24 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_cke[1] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_CKE1" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property -dict {PACKAGE_PIN BA23 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[9] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR9" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property -dict {PACKAGE_PIN BA22 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[7] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR7" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property -dict {PACKAGE_PIN BC22 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_bg[0] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_BG0" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +set_property -dict {PACKAGE_PIN BB22 IOSTANDARD SSTL12_DCI } [get_ports c1_ddr4_adr[12] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_ADR12" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property -dict {PACKAGE_PIN BF25 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[64] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ64" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property -dict {PACKAGE_PIN BF24 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[65] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ65" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property -dict {PACKAGE_PIN BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[16]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_C8" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property -dict {PACKAGE_PIN BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[16]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_T8" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property -dict {PACKAGE_PIN BE25 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[67] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ67" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property -dict {PACKAGE_PIN BD25 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[66] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ66" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property -dict {PACKAGE_PIN BF23 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[70] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ70" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property -dict {PACKAGE_PIN BE23 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[71] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ71" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property -dict {PACKAGE_PIN BD23 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[68] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ68" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property -dict {PACKAGE_PIN BC23 IOSTANDARD POD12_DCI } [get_ports c1_ddr4_dq[69] ]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQ69" - IO_L2P_T0L_N2_FOE_B_65 +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_c[17]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_C17" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property -dict {PACKAGE_PIN BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports c1_ddr4_dqs_t[17]]; # Bank 65 VCCO - VCC1V2 Net "DDR4_C1_DQS_T17" - IO_L1P_T0L_N0_DBC_RS0_65 + + +# # +# # DDR4 RDIMM Controller 2, 72-bit Data Interface, x4 Componets, Single Rank +# # <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# # JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# # Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# # + +# set_property -dict {PACKAGE_PIN C26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[25] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ25" - IO_L23N_T3U_N9_48 +# set_property -dict {PACKAGE_PIN D26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[24] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ24" - IO_L23P_T3U_N8_48 +# set_property -dict {PACKAGE_PIN A28 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[6] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C3" - IO_L22N_T3U_N7_DBC_AD0N_48 +# set_property -dict {PACKAGE_PIN A27 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[6] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T3" - IO_L22P_T3U_N6_DBC_AD0P_48 +# set_property -dict {PACKAGE_PIN B27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[26] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ26" - IO_L24N_T3U_N11_48 +# set_property -dict {PACKAGE_PIN B26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[27] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ27" - IO_L24P_T3U_N10_48 +# set_property -dict {PACKAGE_PIN C28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[31] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ31" - IO_L21N_T3L_N5_AD8N_48 +# set_property -dict {PACKAGE_PIN C27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[30] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ30" - IO_L21P_T3L_N4_AD8P_48 +# set_property -dict {PACKAGE_PIN A30 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[29] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ29" - IO_L20N_T3L_N3_AD1N_48 +# set_property -dict {PACKAGE_PIN A29 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[28] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ28" - IO_L20P_T3L_N2_AD1P_48 +# set_property -dict {PACKAGE_PIN B29 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[7] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C12" - IO_L19N_T3L_N1_DBC_AD9N_48 +# set_property -dict {PACKAGE_PIN C29 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[7] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T12" - IO_L19P_T3L_N0_DBC_AD9P_48 +# set_property -dict {PACKAGE_PIN E27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[17] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ17" - IO_L17N_T2U_N9_AD10N_48 +# set_property -dict {PACKAGE_PIN F27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[16] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ16" - IO_L17P_T2U_N8_AD10P_48 +# set_property -dict {PACKAGE_PIN D30 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[4] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C2" - IO_L16N_T2U_N7_QBC_AD3N_48 +# set_property -dict {PACKAGE_PIN D29 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[4] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T2" - IO_L16P_T2U_N6_QBC_AD3P_48 +# set_property -dict {PACKAGE_PIN D28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[19] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ19" - IO_L18N_T2U_N11_AD2N_48 +# set_property -dict {PACKAGE_PIN E28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[18] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ18" - IO_L18P_T2U_N10_AD2P_48 +# set_property -dict {PACKAGE_PIN F29 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[23] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ23" - IO_L15N_T2L_N5_AD11N_48 +# set_property -dict {PACKAGE_PIN F28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[22] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ22" - IO_L15P_T2L_N4_AD11P_48 +# set_property -dict {PACKAGE_PIN G27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[20] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ20" - IO_L14N_T2L_N3_GC_48 +# set_property -dict {PACKAGE_PIN G26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[21] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ21" - IO_L14P_T2L_N2_GC_48 +# set_property -dict {PACKAGE_PIN H27 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[5] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C11" - IO_L13N_T2L_N1_GC_QBC_48 +# set_property -dict {PACKAGE_PIN H26 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[5] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T11" - IO_L13P_T2L_N0_GC_QBC_48 +# set_property -dict {PACKAGE_PIN H28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[10] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ10" - IO_L11N_T1U_N9_GC_48 +# set_property -dict {PACKAGE_PIN J28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[8] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ8" - IO_L11P_T1U_N8_GC_48 +# set_property -dict {PACKAGE_PIN J26 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[2] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C1" - IO_L10N_T1U_N7_QBC_AD4N_48 +# set_property -dict {PACKAGE_PIN J25 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[2] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T1" - IO_L10P_T1U_N6_QBC_AD4P_48 +# set_property -dict {PACKAGE_PIN G29 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[11] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ11" - IO_L12N_T1U_N11_GC_48 +# set_property -dict {PACKAGE_PIN H29 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[9] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ9" - IO_L12P_T1U_N10_GC_48 +# set_property -dict {PACKAGE_PIN K27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[15] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ15" - IO_L9N_T1L_N5_AD12N_48 +# set_property -dict {PACKAGE_PIN L27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[13] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ13" - IO_L9P_T1L_N4_AD12P_48 +# set_property -dict {PACKAGE_PIN K26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[14] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ14" - IO_L8N_T1L_N3_AD5N_48 +# set_property -dict {PACKAGE_PIN K25 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[12] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ12" - IO_L8P_T1L_N2_AD5P_48 +# set_property -dict {PACKAGE_PIN L28 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[3] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C10" - IO_L7N_T1L_N1_QBC_AD13N_48 +# set_property -dict {PACKAGE_PIN M27 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[3] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T10" - IO_L7P_T1L_N0_QBC_AD13P_48 +# set_property -dict {PACKAGE_PIN P25 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[1] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ1" - IO_L5N_T0U_N9_AD14N_48 +# set_property -dict {PACKAGE_PIN R25 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[0] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ0" - IO_L5P_T0U_N8_AD14P_48 +# set_property -dict {PACKAGE_PIN M26 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[0] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_48 +# set_property -dict {PACKAGE_PIN N26 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[0] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_48 +# set_property -dict {PACKAGE_PIN L25 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[3] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ3" - IO_L6N_T0U_N11_AD6N_48 +# set_property -dict {PACKAGE_PIN M25 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[2] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ2" - IO_L6P_T0U_N10_AD6P_48 +# set_property -dict {PACKAGE_PIN P26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[4] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ4" - IO_L3N_T0L_N5_AD15N_48 +# set_property -dict {PACKAGE_PIN R26 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[5] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ5" - IO_L3P_T0L_N4_AD15P_48 +# set_property -dict {PACKAGE_PIN N28 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[7] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ7" - IO_L2N_T0L_N3_48 +# set_property -dict {PACKAGE_PIN N27 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[6] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQ6" - IO_L2P_T0L_N2_48 +# set_property -dict {PACKAGE_PIN P28 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[1] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_C9" - IO_L1N_T0L_N1_DBC_48 +# set_property -dict {PACKAGE_PIN R28 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[1] ]; # Bank 48 VCCO - VCC1V2 Net "DDR4_C2_DQS_T9" - IO_L1P_T0L_N0_DBC_48 +# set_property -dict {PACKAGE_PIN B32 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[7] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR7" - IO_L23N_T3U_N9_47 +# set_property -dict {PACKAGE_PIN B31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_act_n ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ACT_B" - IO_L23P_T3U_N8_47 +# set_property -dict {PACKAGE_PIN A35 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[14] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR14" - IO_L22N_T3U_N7_DBC_AD0N_47 +# set_property -dict {PACKAGE_PIN A34 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[10] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR10" - IO_L22P_T3U_N6_DBC_AD0P_47 +# set_property -dict {PACKAGE_PIN C31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_bg[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BG0" - IO_T3U_N12_47 +# set_property -dict {PACKAGE_PIN A33 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR1" - IO_L24N_T3U_N11_47 +# set_property -dict {PACKAGE_PIN A32 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[8] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR8" - IO_L24P_T3U_N10_47 +# set_property -dict {PACKAGE_PIN C33 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[2] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR2" - IO_L21N_T3L_N5_AD8N_47 +# set_property -dict {PACKAGE_PIN C32 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[6] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR6" - IO_L21P_T3L_N4_AD8P_47 +# set_property -dict {PACKAGE_PIN B36 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_ba[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BA1" - IO_L20N_T3L_N3_AD1N_47 +# set_property -dict {PACKAGE_PIN B35 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_cs_n[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B0" - IO_L20P_T3L_N2_AD1P_47 +# set_property -dict {PACKAGE_PIN B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_c[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_C0" - IO_L19N_T3L_N1_DBC_AD9N_47 +# set_property -dict {PACKAGE_PIN C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_t[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_T0" - IO_L19P_T3L_N0_DBC_AD9P_47 +# set_property -dict {PACKAGE_PIN J30 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_bg[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BG1" - IO_L17N_T2U_N9_AD10N_47 +# set_property -dict {PACKAGE_PIN J29 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[3] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR3" - IO_L17P_T2U_N8_AD10P_47 +# #set_property -dict {PACKAGE_PIN D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_c[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_47 +# #set_property -dict {PACKAGE_PIN D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c2_ddr4_ck_t[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_47 +# #set_property -dict {PACKAGE_PIN E30 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_cke[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CKE1" - IO_T2U_N12_47 +# set_property -dict {PACKAGE_PIN D31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[9] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR9" - IO_L18N_T2U_N11_AD2N_47 +# set_property -dict {PACKAGE_PIN E31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[11] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR11" - IO_L18P_T2U_N10_AD2P_47 +# #set_property -dict {PACKAGE_PIN K31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_cs_n[3] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B3" - IO_L15N_T2L_N5_AD11N_47 +# set_property -dict {PACKAGE_PIN K30 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[16] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR16" - IO_L15P_T2L_N4_AD11P_47 +# set_property -dict {PACKAGE_PIN D33 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_ba[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_BA0" - IO_L14N_T2L_N3_GC_47 +# set_property -dict {PACKAGE_PIN E33 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_odt[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ODT0" - IO_L14P_T2L_N2_GC_47 +# #set_property -dict {PACKAGE_PIN F30 IOSTANDARD LVCMOS12 } [get_ports c2_ddr4_alert_n ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ALERT_B" - IO_L11N_T1U_N9_GC_47 +# set_property -dict {PACKAGE_PIN G30 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_cke[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CKE0" - IO_L11P_T1U_N8_GC_47 +# set_property -dict {PACKAGE_PIN G32 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[15] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR15" - IO_L10N_T1U_N7_QBC_AD4N_47 +# set_property -dict {PACKAGE_PIN G31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[5] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR5" - IO_L10P_T1U_N6_QBC_AD4P_47 +# #set_property -dict {PACKAGE_PIN J31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_cs_n[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B1" - IO_T1U_N12_47 +# #set_property -dict {PACKAGE_PIN F34 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_odt[1] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ODT1" - IO_L12N_T1U_N11_GC_47 +# set_property -dict {PACKAGE_PIN F33 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[13] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR13" - IO_L12P_T1U_N10_GC_47 +# #set_property -dict {PACKAGE_PIN L30 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_cs_n[2] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_CS_B2" - IO_L9N_T1L_N5_AD12N_47 +# set_property -dict {PACKAGE_PIN L29 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[0] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR0" - IO_L9P_T1L_N4_AD12P_47 +# #set_property -dict {PACKAGE_PIN H32 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[17] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR17" - IO_L8N_T1L_N3_AD5N_47 +# set_property -dict {PACKAGE_PIN H31 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[4] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR4" - IO_L8P_T1L_N2_AD5P_47 +# set_property -dict {PACKAGE_PIN M30 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_adr[12] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_ADR12" - IO_L7N_T1L_N1_QBC_AD13N_47 +# set_property -dict {PACKAGE_PIN M29 IOSTANDARD SSTL12_DCI } [get_ports c2_ddr4_parity ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_PAR" - IO_L7P_T1L_N0_QBC_AD13P_47 +# set_property -dict {PACKAGE_PIN P30 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[40] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ40" - IO_L5N_T0U_N9_AD14N_47 +# set_property -dict {PACKAGE_PIN R30 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[41] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ41" - IO_L5P_T0U_N8_AD14P_47 +# set_property -dict {PACKAGE_PIN M31 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[10]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_C5" - IO_L4N_T0U_N7_DBC_AD7N_47 +# set_property -dict {PACKAGE_PIN N31 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[10]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_T5" - IO_L4P_T0U_N6_DBC_AD7P_47 +# set_property -dict {PACKAGE_PIN N29 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[43] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ43" - IO_L6N_T0U_N11_AD6N_47 +# set_property -dict {PACKAGE_PIN P29 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[42] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ42" - IO_L6P_T0U_N10_AD6P_47 +# set_property -dict {PACKAGE_PIN N32 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[47] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ47" - IO_L3N_T0L_N5_AD15N_47 +# set_property -dict {PACKAGE_PIN P31 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[46] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ46" - IO_L3P_T0L_N4_AD15P_47 +# set_property -dict {PACKAGE_PIN L32 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[44] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ44" - IO_L2N_T0L_N3_47 +# set_property -dict {PACKAGE_PIN M32 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[45] ]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQ45" - IO_L2P_T0L_N2_47 +# set_property -dict {PACKAGE_PIN R31 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[11]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_C14" - IO_L1N_T0L_N1_DBC_47 +# set_property -dict {PACKAGE_PIN T30 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[11]]; # Bank 47 VCCO - VCC1V2 Net "DDR4_C2_DQS_T14" - IO_L1P_T0L_N0_DBC_47 +# set_property -dict {PACKAGE_PIN B37 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[65] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ65" - IO_L23N_T3U_N9_46 +# set_property -dict {PACKAGE_PIN C36 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[64] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ64" - IO_L23P_T3U_N8_46 +# set_property -dict {PACKAGE_PIN A39 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[16]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C8" - IO_L22N_T3U_N7_DBC_AD0N_46 +# set_property -dict {PACKAGE_PIN B39 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[16]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T8" - IO_L22P_T3U_N6_DBC_AD0P_46 +# #set_property -dict {PACKAGE_PIN D40 IOSTANDARD LVCMOS12 } [get_ports c2_ddr4_event_n ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_EVENT_B" - IO_T3U_N12_46 +# set_property -dict {PACKAGE_PIN A38 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[67] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ67" - IO_L24N_T3U_N11_46 +# set_property -dict {PACKAGE_PIN A37 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[66] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ66" - IO_L24P_T3U_N10_46 +# set_property -dict {PACKAGE_PIN C39 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[68] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ68" - IO_L21N_T3L_N5_AD8N_46 +# set_property -dict {PACKAGE_PIN D39 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[69] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ69" - IO_L21P_T3L_N4_AD8P_46 +# set_property -dict {PACKAGE_PIN A40 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[70] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ70" - IO_L20N_T3L_N3_AD1N_46 +# set_property -dict {PACKAGE_PIN B40 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[71] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ71" - IO_L20P_T3L_N2_AD1P_46 +# set_property -dict {PACKAGE_PIN C38 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[17]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C17" - IO_L19N_T3L_N1_DBC_AD9N_46 +# set_property -dict {PACKAGE_PIN C37 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[17]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T17" - IO_L19P_T3L_N0_DBC_AD9P_46 +# set_property -dict {PACKAGE_PIN E35 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[35] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ35" - IO_L17N_T2U_N9_AD10N_46 +# set_property -dict {PACKAGE_PIN F35 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[32] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ32" - IO_L17P_T2U_N8_AD10P_46 +# set_property -dict {PACKAGE_PIN E40 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[8] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C4" - IO_L16N_T2U_N7_QBC_AD3N_46 +# set_property -dict {PACKAGE_PIN E39 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[8] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T4" - IO_L16P_T2U_N6_QBC_AD3P_46 +# set_property -dict {PACKAGE_PIN D36 IOSTANDARD LVCMOS12 } [get_ports c2_ddr4_reset_n ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_RESET_N" - IO_T2U_N12_46 +# set_property -dict {PACKAGE_PIN D38 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[34] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ34" - IO_L18N_T2U_N11_AD2N_46 +# set_property -dict {PACKAGE_PIN E38 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[33] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ33" - IO_L18P_T2U_N10_AD2P_46 +# set_property -dict {PACKAGE_PIN F38 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[38] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ38" - IO_L15N_T2L_N5_AD11N_46 +# set_property -dict {PACKAGE_PIN G38 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[39] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ39" - IO_L15P_T2L_N4_AD11P_46 +# set_property -dict {PACKAGE_PIN E37 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[37] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ37" - IO_L14N_T2L_N3_GC_46 +# set_property -dict {PACKAGE_PIN E36 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[36] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ36" - IO_L14P_T2L_N2_GC_46 +# set_property -dict {PACKAGE_PIN F37 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[9] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C13" - IO_L13N_T2L_N1_GC_QBC_46 +# set_property -dict {PACKAGE_PIN G37 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[9] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T13" - IO_L13P_T2L_N0_GC_QBC_46 +# set_property -dict {PACKAGE_PIN G36 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[57] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ57" - IO_L11N_T1U_N9_GC_46 +# set_property -dict {PACKAGE_PIN H36 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[56] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ56" - IO_L11P_T1U_N8_GC_46 +# set_property -dict {PACKAGE_PIN H38 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[14]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C7" - IO_L10N_T1U_N7_QBC_AD4N_46 +# set_property -dict {PACKAGE_PIN J38 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[14]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T7" - IO_L10P_T1U_N6_QBC_AD4P_46 +# set_property -dict {PACKAGE_PIN H37 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[58] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ58" - IO_L12N_T1U_N11_GC_46 +# set_property -dict {PACKAGE_PIN J36 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[59] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ59" - IO_L12P_T1U_N10_GC_46 +# set_property -dict {PACKAGE_PIN G35 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[62] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ62" - IO_L9N_T1L_N5_AD12N_46 +# set_property -dict {PACKAGE_PIN G34 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[63] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ63" - IO_L9P_T1L_N4_AD12P_46 +# set_property -dict {PACKAGE_PIN K38 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[61] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ61" - IO_L8N_T1L_N3_AD5N_46 +# set_property -dict {PACKAGE_PIN K37 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[60] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ60" - IO_L8P_T1L_N2_AD5P_46 +# set_property -dict {PACKAGE_PIN H34 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[15]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C16" - IO_L7N_T1L_N1_QBC_AD13N_46 +# set_property -dict {PACKAGE_PIN H33 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[15]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T16" - IO_L7P_T1L_N0_QBC_AD13P_46 +# set_property -dict {PACKAGE_PIN K33 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[51] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ51" - IO_L5N_T0U_N9_AD14N_46 +# set_property -dict {PACKAGE_PIN L33 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[50] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ50" - IO_L5P_T0U_N8_AD14P_46 +# set_property -dict {PACKAGE_PIN L36 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[12]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C6" - IO_L4N_T0U_N7_DBC_AD7N_46 +# set_property -dict {PACKAGE_PIN L35 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[12]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T6" - IO_L4P_T0U_N6_DBC_AD7P_46 +# set_property -dict {PACKAGE_PIN J35 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[48] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ48" - IO_L6N_T0U_N11_AD6N_46 +# set_property -dict {PACKAGE_PIN K35 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[49] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ49" - IO_L6P_T0U_N10_AD6P_46 +# set_property -dict {PACKAGE_PIN J34 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[52] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ52" - IO_L3N_T0L_N5_AD15N_46 +# set_property -dict {PACKAGE_PIN J33 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[53] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ53" - IO_L3P_T0L_N4_AD15P_46 +# set_property -dict {PACKAGE_PIN N34 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[54] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ54" - IO_L2N_T0L_N3_46 +# set_property -dict {PACKAGE_PIN P34 IOSTANDARD POD12_DCI } [get_ports c2_ddr4_dq[55] ]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQ55" - IO_L2P_T0L_N2_46 +# set_property -dict {PACKAGE_PIN L34 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_c[13]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_C15" - IO_L1N_T0L_N1_DBC_46 +# set_property -dict {PACKAGE_PIN M34 IOSTANDARD DIFF_POD12_DCI } [get_ports c2_ddr4_dqs_t[13]]; # Bank 46 VCCO - VCC1V2 Net "DDR4_C2_DQS_T15" - IO_L1P_T0L_N0_DBC_46 +# # +# # DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank +# # <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# # JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# # Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# # +set_property -dict {PACKAGE_PIN AR36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[16] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L23N_T3U_N9_42 +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[15] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L23P_T3U_N8_42 +#set_property -dict {PACKAGE_PIN AN34 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_odt[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_42 +#set_property -dict {PACKAGE_PIN AM34 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_cs_n[3] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L22P_T3U_N6_DBC_AD0P_42 +set_property -dict {PACKAGE_PIN AR33 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_cs_n[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_T3U_N12_42 +set_property -dict {PACKAGE_PIN AN36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[13] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_42 +#set_property -dict {PACKAGE_PIN AN35 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[17] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L24P_T3U_N10_42 +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[14] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L21N_T3L_N5_AD8N_42 +set_property -dict {PACKAGE_PIN AP34 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_odt[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L21P_T3L_N4_AD8P_42 +#set_property -dict {PACKAGE_PIN AP33 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_cs_n[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L20N_T3L_N3_AD1N_42 +#set_property -dict {PACKAGE_PIN AN33 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_cs_n[2] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L20P_T3L_N2_AD1P_42 +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_ba[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L19N_T3L_N1_DBC_AD9N_42 +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[10] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L19P_T3L_N0_DBC_AD9P_42 +set_property -dict {PACKAGE_PIN AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L17N_T2U_N9_AD10N_42 +set_property -dict {PACKAGE_PIN AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L17P_T2U_N8_AD10P_42 +#set_property -dict {PACKAGE_PIN AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_c[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_42 +#set_property -dict {PACKAGE_PIN AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports c0_ddr4_ck_t[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_42 +set_property -dict {PACKAGE_PIN AT34 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_ba[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_T2U_N12_42 +set_property -dict {PACKAGE_PIN AU36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_parity ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L18N_T2U_N11_AD2N_42 +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L18P_T2U_N10_AD2P_42 +set_property -dict {PACKAGE_PIN AV37 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[2] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L15N_T2L_N5_AD11N_42 +set_property -dict {PACKAGE_PIN AV36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L15P_T2L_N4_AD11P_42 +set_property -dict {PACKAGE_PIN AW36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[4] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L14N_T2L_N3_GC_42 +set_property -dict {PACKAGE_PIN AW35 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[3] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L14P_T2L_N2_GC_42 +# set_property -dict {PACKAGE_PIN BA38 IOSTANDARD LVCMOS12 } [get_ports c0_ddr4_alert_n ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L11N_T1U_N9_GC_42 +set_property -dict {PACKAGE_PIN BA37 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[8] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_42 +set_property -dict {PACKAGE_PIN BA40 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[7] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L10N_T1U_N7_QBC_AD4N_42 +set_property -dict {PACKAGE_PIN BA39 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[11] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L10P_T1U_N6_QBC_AD4P_42 +set_property -dict {PACKAGE_PIN BB37 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[9] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_42 +set_property -dict {PACKAGE_PIN AY36 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[5] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L12N_T1U_N11_GC_42 +set_property -dict {PACKAGE_PIN AY35 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[6] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L12P_T1U_N10_GC_42 +#set_property -dict {PACKAGE_PIN BC40 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_cke[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L9N_T1L_N5_AD12N_42 +set_property -dict {PACKAGE_PIN BC39 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_bg[1] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L9P_T1L_N4_AD12P_42 +set_property -dict {PACKAGE_PIN BB40 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_adr[12] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L8N_T1L_N3_AD5N_42 +set_property -dict {PACKAGE_PIN BB39 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_act_n ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_L8P_T1L_N2_AD5P_42 +set_property -dict {PACKAGE_PIN BC38 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_cke[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L7N_T1L_N1_QBC_AD13N_42 +set_property -dict {PACKAGE_PIN BC37 IOSTANDARD SSTL12_DCI } [get_ports c0_ddr4_bg[0] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_L7P_T1L_N0_QBC_AD13P_42 +set_property -dict {PACKAGE_PIN BF43 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[66] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L5N_T0U_N9_AD14N_42 +set_property -dict {PACKAGE_PIN BF42 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[67] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L5P_T0U_N8_AD14P_42 +set_property -dict {PACKAGE_PIN BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[16]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L4N_T0U_N7_DBC_AD7N_42 +set_property -dict {PACKAGE_PIN BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[16]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L4P_T0U_N6_DBC_AD7P_42 +set_property -dict {PACKAGE_PIN BD40 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[64] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L6N_T0U_N11_AD6N_42 +set_property -dict {PACKAGE_PIN BD39 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[65] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L6P_T0U_N10_AD6P_42 +set_property -dict {PACKAGE_PIN BF41 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[71] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L3N_T0L_N5_AD15N_42 +set_property -dict {PACKAGE_PIN BE40 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[70] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L3P_T0L_N4_AD15P_42 +set_property -dict {PACKAGE_PIN BF37 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[68] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L2N_T0L_N3_42 +set_property -dict {PACKAGE_PIN BE37 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[69] ]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L2P_T0L_N2_42 +set_property -dict {PACKAGE_PIN BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[17]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L1N_T0L_N1_DBC_42 +set_property -dict {PACKAGE_PIN BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[17]]; # Bank 42 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L1P_T0L_N0_DBC_42 +set_property -dict {PACKAGE_PIN AU32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[34] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L23N_T3U_N9_41 +set_property -dict {PACKAGE_PIN AT32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[35] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L23P_T3U_N8_41 +set_property -dict {PACKAGE_PIN AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[8] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L22N_T3U_N7_DBC_AD0N_41 +set_property -dict {PACKAGE_PIN AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[8] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L22P_T3U_N6_DBC_AD0P_41 +#set_property -dict {PACKAGE_PIN AT33 IOSTANDARD LVCMOS12 } [get_ports c0_ddr4_event_n ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_41 +set_property -dict {PACKAGE_PIN AM30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[33] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L24N_T3U_N11_41 +set_property -dict {PACKAGE_PIN AL30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[32] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L24P_T3U_N10_41 +set_property -dict {PACKAGE_PIN AR32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[38] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L21N_T3L_N5_AD8N_41 +set_property -dict {PACKAGE_PIN AR31 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[39] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L21P_T3L_N4_AD8P_41 +set_property -dict {PACKAGE_PIN AN32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[37] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L20N_T3L_N3_AD1N_41 +set_property -dict {PACKAGE_PIN AN31 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[36] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L20P_T3L_N2_AD1P_41 +set_property -dict {PACKAGE_PIN AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[9] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L19N_T3L_N1_DBC_AD9N_41 +set_property -dict {PACKAGE_PIN AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[9] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L19P_T3L_N0_DBC_AD9P_41 +set_property -dict {PACKAGE_PIN AV32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[25] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L17N_T2U_N9_AD10N_41 +set_property -dict {PACKAGE_PIN AV31 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[24] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L17P_T2U_N8_AD10P_41 +set_property -dict {PACKAGE_PIN AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[6] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_41 +set_property -dict {PACKAGE_PIN AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[6] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_41 +set_property -dict {PACKAGE_PIN AU31 IOSTANDARD LVCMOS12 } [get_ports c0_ddr4_reset_n ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_41 +set_property -dict {PACKAGE_PIN AW34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[27] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L18N_T2U_N11_AD2N_41 +set_property -dict {PACKAGE_PIN AV34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[26] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L18P_T2U_N10_AD2P_41 +set_property -dict {PACKAGE_PIN AY31 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[29] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L15N_T2L_N5_AD11N_41 +set_property -dict {PACKAGE_PIN AW31 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[28] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L15P_T2L_N4_AD11P_41 +set_property -dict {PACKAGE_PIN BA35 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[30] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L14N_T2L_N3_GC_41 +set_property -dict {PACKAGE_PIN BA34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[31] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L14P_T2L_N2_GC_41 +set_property -dict {PACKAGE_PIN BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[7] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_41 +set_property -dict {PACKAGE_PIN BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[7] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_41 +set_property -dict {PACKAGE_PIN BB32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[17] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_41 +set_property -dict {PACKAGE_PIN BB31 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[16] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_41 +set_property -dict {PACKAGE_PIN BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[4] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_41 +set_property -dict {PACKAGE_PIN BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[4] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_41 +set_property -dict {PACKAGE_PIN AY33 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[19] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_41 +set_property -dict {PACKAGE_PIN AY32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[18] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_41 +set_property -dict {PACKAGE_PIN BC33 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[21] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_41 +set_property -dict {PACKAGE_PIN BC32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[20] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_41 +set_property -dict {PACKAGE_PIN BC34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[23] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_41 +set_property -dict {PACKAGE_PIN BB34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[22] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_41 +set_property -dict {PACKAGE_PIN BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[5] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_41 +set_property -dict {PACKAGE_PIN BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[5] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_41 +set_property -dict {PACKAGE_PIN BE33 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[58] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5N_T0U_N9_AD14N_41 +set_property -dict {PACKAGE_PIN BD33 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[57] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L5P_T0U_N8_AD14P_41 +set_property -dict {PACKAGE_PIN BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[14]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_41 +set_property -dict {PACKAGE_PIN BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[14]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_41 +set_property -dict {PACKAGE_PIN BD35 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[59] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6N_T0U_N11_AD6N_41 +set_property -dict {PACKAGE_PIN BD34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[56] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L6P_T0U_N10_AD6P_41 +set_property -dict {PACKAGE_PIN BF33 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[61] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_41 +set_property -dict {PACKAGE_PIN BF32 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[60] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_41 +set_property -dict {PACKAGE_PIN BF35 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[63] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_41 +set_property -dict {PACKAGE_PIN BF34 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[62] ]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_41 +set_property -dict {PACKAGE_PIN BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[15]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_41 +set_property -dict {PACKAGE_PIN BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[15]]; # Bank 41 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_41 +set_property -dict {PACKAGE_PIN AP29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[40] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_40 +set_property -dict {PACKAGE_PIN AP28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[41] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_40 +set_property -dict {PACKAGE_PIN AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[10]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_40 +set_property -dict {PACKAGE_PIN AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[10]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_40 +set_property -dict {PACKAGE_PIN AN27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[42] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_40 +set_property -dict {PACKAGE_PIN AM27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[43] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_40 +set_property -dict {PACKAGE_PIN AR28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[47] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L21N_T3L_N5_AD8N_40 +set_property -dict {PACKAGE_PIN AR27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[46] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L21P_T3L_N4_AD8P_40 +set_property -dict {PACKAGE_PIN AN29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[44] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L20N_T3L_N3_AD1N_40 +set_property -dict {PACKAGE_PIN AM29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[45] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - IO_L20P_T3L_N2_AD1P_40 +set_property -dict {PACKAGE_PIN AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[11]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_40 +set_property -dict {PACKAGE_PIN AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[11]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_40 +set_property -dict {PACKAGE_PIN AV27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[49] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L17N_T2U_N9_AD10N_40 +set_property -dict {PACKAGE_PIN AU27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[50] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L17P_T2U_N8_AD10P_40 +set_property -dict {PACKAGE_PIN AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[12]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L16N_T2U_N7_QBC_AD3N_40 +set_property -dict {PACKAGE_PIN AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[12]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L16P_T2U_N6_QBC_AD3P_40 +set_property -dict {PACKAGE_PIN AT28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[48] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L18N_T2U_N11_AD2N_40 +set_property -dict {PACKAGE_PIN AT27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[51] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L18P_T2U_N10_AD2P_40 +set_property -dict {PACKAGE_PIN AV29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[52] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L15N_T2L_N5_AD11N_40 +set_property -dict {PACKAGE_PIN AV28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[55] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L15P_T2L_N4_AD11P_40 +set_property -dict {PACKAGE_PIN AY30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[53] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L14N_T2L_N3_GC_40 +set_property -dict {PACKAGE_PIN AW30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[54] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L14P_T2L_N2_GC_40 +set_property -dict {PACKAGE_PIN AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[13]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L13N_T2L_N1_GC_QBC_40 +set_property -dict {PACKAGE_PIN AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[13]]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L13P_T2L_N0_GC_QBC_40 +set_property -dict {PACKAGE_PIN BA28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[2] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L11N_T1U_N9_GC_40 +set_property -dict {PACKAGE_PIN BA27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[3] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L11P_T1U_N8_GC_40 +set_property -dict {PACKAGE_PIN BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[0] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L10N_T1U_N7_QBC_AD4N_40 +set_property -dict {PACKAGE_PIN BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[0] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L10P_T1U_N6_QBC_AD4P_40 +set_property -dict {PACKAGE_PIN AW29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[1] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L12N_T1U_N11_GC_40 +set_property -dict {PACKAGE_PIN AW28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[0] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L12P_T1U_N10_GC_40 +set_property -dict {PACKAGE_PIN BC27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[6] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L9N_T1L_N5_AD12N_40 +set_property -dict {PACKAGE_PIN BB27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[7] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L9P_T1L_N4_AD12P_40 +set_property -dict {PACKAGE_PIN BB29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[4] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L8N_T1L_N3_AD5N_40 +set_property -dict {PACKAGE_PIN BA29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[5] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L8P_T1L_N2_AD5P_40 +set_property -dict {PACKAGE_PIN BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[1] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L7N_T1L_N1_QBC_AD13N_40 +set_property -dict {PACKAGE_PIN BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[1] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L7P_T1L_N0_QBC_AD13P_40 +set_property -dict {PACKAGE_PIN BF28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[9] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L5N_T0U_N9_AD14N_40 +set_property -dict {PACKAGE_PIN BE28 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[8] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L5P_T0U_N8_AD14P_40 +set_property -dict {PACKAGE_PIN BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[2] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L4N_T0U_N7_DBC_AD7N_40 +set_property -dict {PACKAGE_PIN BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[2] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L4P_T0U_N6_DBC_AD7P_40 +set_property -dict {PACKAGE_PIN BE30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[10] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L6N_T0U_N11_AD6N_40 +set_property -dict {PACKAGE_PIN BD30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[11] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L6P_T0U_N10_AD6P_40 +set_property -dict {PACKAGE_PIN BF27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[12] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L3N_T0L_N5_AD15N_40 +set_property -dict {PACKAGE_PIN BE27 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[13] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L3P_T0L_N4_AD15P_40 +set_property -dict {PACKAGE_PIN BF30 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[14] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L2N_T0L_N3_40 +set_property -dict {PACKAGE_PIN BF29 IOSTANDARD POD12_DCI } [get_ports c0_ddr4_dq[15] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L2P_T0L_N2_40 +set_property -dict {PACKAGE_PIN BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_c[3] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L1N_T0L_N1_DBC_40 +set_property -dict {PACKAGE_PIN BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports c0_ddr4_dqs_t[3] ]; # Bank 40 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L1P_T0L_N0_DBC_40 +# +# MGT Connections +# +#set_property PACKAGE_PIN N3 [get_ports QSFP0_RX1_N]; # Bank 231 - MGTYRXN0_231 +#set_property PACKAGE_PIN N4 [get_ports QSFP0_RX1_P]; # Bank 231 - MGTYRXP0_231 +#set_property PACKAGE_PIN M1 [get_ports QSFP0_RX2_N]; # Bank 231 - MGTYRXN1_231 +#set_property PACKAGE_PIN M2 [get_ports QSFP0_RX2_P]; # Bank 231 - MGTYRXP1_231 +#set_property PACKAGE_PIN L3 [get_ports QSFP0_RX3_N]; # Bank 231 - MGTYRXN2_231 +#set_property PACKAGE_PIN L4 [get_ports QSFP0_RX3_P]; # Bank 231 - MGTYRXP2_231 +#set_property PACKAGE_PIN K1 [get_ports QSFP0_RX4_N]; # Bank 231 - MGTYRXN3_231 +#set_property PACKAGE_PIN K2 [get_ports QSFP0_RX4_P]; # Bank 231 - MGTYRXP3_231 +#set_property PACKAGE_PIN N8 [get_ports QSFP0_TX1_N]; # Bank 231 - MGTYTXN0_231 +#set_property PACKAGE_PIN N9 [get_ports QSFP0_TX1_P]; # Bank 231 - MGTYTXP0_231 +#set_property PACKAGE_PIN M6 [get_ports QSFP0_TX2_N]; # Bank 231 - MGTYTXN1_231 +#set_property PACKAGE_PIN M7 [get_ports QSFP0_TX2_P]; # Bank 231 - MGTYTXP1_231 +#set_property PACKAGE_PIN L8 [get_ports QSFP0_TX3_N]; # Bank 231 - MGTYTXN2_231 +#set_property PACKAGE_PIN L9 [get_ports QSFP0_TX3_P]; # Bank 231 - MGTYTXP2_231 +#set_property PACKAGE_PIN K6 [get_ports QSFP0_TX4_N]; # Bank 231 - MGTYTXN3_231 +#set_property PACKAGE_PIN K7 [get_ports QSFP0_TX4_P]; # Bank 231 - MGTYTXP3_231 +#set_property PACKAGE_PIN U3 [get_ports QSFP1_RX1_N]; # Bank 230 - MGTYRXN0_230 +#set_property PACKAGE_PIN U4 [get_ports QSFP1_RX1_P]; # Bank 230 - MGTYRXP0_230 +#set_property PACKAGE_PIN T1 [get_ports QSFP1_RX2_N]; # Bank 230 - MGTYRXN1_230 +#set_property PACKAGE_PIN T2 [get_ports QSFP1_RX2_P]; # Bank 230 - MGTYRXP1_230 +#set_property PACKAGE_PIN R3 [get_ports QSFP1_RX3_N]; # Bank 230 - MGTYRXN2_230 +#set_property PACKAGE_PIN R4 [get_ports QSFP1_RX3_P]; # Bank 230 - MGTYRXP2_230 +#set_property PACKAGE_PIN P1 [get_ports QSFP1_RX4_N]; # Bank 230 - MGTYRXN3_230 +#set_property PACKAGE_PIN P2 [get_ports QSFP1_RX4_P]; # Bank 230 - MGTYRXP3_230 +#set_property PACKAGE_PIN U8 [get_ports QSFP1_TX1_N]; # Bank 230 - MGTYTXN0_230 +#set_property PACKAGE_PIN U9 [get_ports QSFP1_TX1_P]; # Bank 230 - MGTYTXP0_230 +#set_property PACKAGE_PIN T6 [get_ports QSFP1_TX2_N]; # Bank 230 - MGTYTXN1_230 +#set_property PACKAGE_PIN T7 [get_ports QSFP1_TX2_P]; # Bank 230 - MGTYTXP1_230 +#set_property PACKAGE_PIN R8 [get_ports QSFP1_TX3_N]; # Bank 230 - MGTYTXN2_230 +#set_property PACKAGE_PIN R9 [get_ports QSFP1_TX3_P]; # Bank 230 - MGTYTXP2_230 +#set_property PACKAGE_PIN P6 [get_ports QSFP1_TX4_N]; # Bank 230 - MGTYTXN3_230 +#set_property PACKAGE_PIN P7 [get_ports QSFP1_TX4_P]; # Bank 230 - MGTYTXP3_230 + +# PCIe I/O +set_property PACKAGE_PIN AF1 [get_ports pci_exp_rxn_i[0] ]; # Bank 227 - MGTYRXN3_227 +set_property PACKAGE_PIN AF2 [get_ports pci_exp_rxp_i[0] ]; # Bank 227 - MGTYRXP3_227 +set_property PACKAGE_PIN AG3 [get_ports pci_exp_rxn_i[1] ]; # Bank 227 - MGTYRXN2_227 +set_property PACKAGE_PIN AG4 [get_ports pci_exp_rxp_i[1] ]; # Bank 227 - MGTYRXP2_227 +set_property PACKAGE_PIN AH1 [get_ports pci_exp_rxn_i[2] ]; # Bank 227 - MGTYRXN1_227 +set_property PACKAGE_PIN AH2 [get_ports pci_exp_rxp_i[2] ]; # Bank 227 - MGTYRXP1_227 +set_property PACKAGE_PIN AJ3 [get_ports pci_exp_rxn_i[3] ]; # Bank 227 - MGTYRXN0_227 +set_property PACKAGE_PIN AJ4 [get_ports pci_exp_rxp_i[3] ]; # Bank 227 - MGTYRXP0_227 +set_property PACKAGE_PIN AF6 [get_ports pci_exp_txn_o[0] ]; # Bank 227 - MGTYTXN3_227 +set_property PACKAGE_PIN AF7 [get_ports pci_exp_txp_o[0] ]; # Bank 227 - MGTYTXP3_227 +set_property PACKAGE_PIN AG8 [get_ports pci_exp_txn_o[1] ]; # Bank 227 - MGTYTXN2_227 +set_property PACKAGE_PIN AG9 [get_ports pci_exp_txp_o[1] ]; # Bank 227 - MGTYTXP2_227 +set_property PACKAGE_PIN AH6 [get_ports pci_exp_txn_o[2] ]; # Bank 227 - MGTYTXN1_227 +set_property PACKAGE_PIN AH7 [get_ports pci_exp_txp_o[2] ]; # Bank 227 - MGTYTXP1_227 +set_property PACKAGE_PIN AJ8 [get_ports pci_exp_txn_o[3] ]; # Bank 227 - MGTYTXN0_227 +set_property PACKAGE_PIN AJ9 [get_ports pci_exp_txp_o[3] ]; # Bank 227 - MGTYTXP0_227 +set_property PACKAGE_PIN AK1 [get_ports pci_exp_rxn_i[4] ]; # Bank 226 - MGTYRXN3_226 +set_property PACKAGE_PIN AK2 [get_ports pci_exp_rxp_i[4] ]; # Bank 226 - MGTYRXP3_226 +set_property PACKAGE_PIN AL3 [get_ports pci_exp_rxn_i[5] ]; # Bank 226 - MGTYRXN2_226 +set_property PACKAGE_PIN AL4 [get_ports pci_exp_rxp_i[5] ]; # Bank 226 - MGTYRXP2_226 +set_property PACKAGE_PIN AM1 [get_ports pci_exp_rxn_i[6] ]; # Bank 226 - MGTYRXN1_226 +set_property PACKAGE_PIN AM2 [get_ports pci_exp_rxp_i[6] ]; # Bank 226 - MGTYRXP1_226 +set_property PACKAGE_PIN AN3 [get_ports pci_exp_rxn_i[7] ]; # Bank 226 - MGTYRXN0_226 +set_property PACKAGE_PIN AN4 [get_ports pci_exp_rxp_i[7] ]; # Bank 226 - MGTYRXP0_226 +set_property PACKAGE_PIN AK6 [get_ports pci_exp_txn_o[4] ]; # Bank 226 - MGTYTXN3_226 +set_property PACKAGE_PIN AK7 [get_ports pci_exp_txp_o[4] ]; # Bank 226 - MGTYTXP3_226 +set_property PACKAGE_PIN AL8 [get_ports pci_exp_txn_o[5] ]; # Bank 226 - MGTYTXN2_226 +set_property PACKAGE_PIN AL9 [get_ports pci_exp_txp_o[5] ]; # Bank 226 - MGTYTXP2_226 +set_property PACKAGE_PIN AM6 [get_ports pci_exp_txn_o[6] ]; # Bank 226 - MGTYTXN1_226 +set_property PACKAGE_PIN AM7 [get_ports pci_exp_txp_o[6] ]; # Bank 226 - MGTYTXP1_226 +set_property PACKAGE_PIN AN8 [get_ports pci_exp_txn_o[7] ]; # Bank 226 - MGTYTXN0_226 +set_property PACKAGE_PIN AN9 [get_ports pci_exp_txp_o[7] ]; # Bank 226 - MGTYTXP0_226 +# set_property PACKAGE_PIN AT1 [get_ports pci_exp_rxn_i[10]]; # Bank 225 - MGTYRXN1_225 +# set_property PACKAGE_PIN AT2 [get_ports pci_exp_rxp_i[10]]; # Bank 225 - MGTYRXP1_225 +# set_property PACKAGE_PIN AU3 [get_ports pci_exp_rxn_i[11]]; # Bank 225 - MGTYRXN0_225 +# set_property PACKAGE_PIN AU4 [get_ports pci_exp_rxp_i[11]]; # Bank 225 - MGTYRXP0_225 +# set_property PACKAGE_PIN AP1 [get_ports pci_exp_rxn_i[8] ]; # Bank 225 - MGTYRXN3_225 +# set_property PACKAGE_PIN AP2 [get_ports pci_exp_rxp_i[8] ]; # Bank 225 - MGTYRXP3_225 +# set_property PACKAGE_PIN AR3 [get_ports pci_exp_rxn_i[9] ]; # Bank 225 - MGTYRXN2_225 +# set_property PACKAGE_PIN AR4 [get_ports pci_exp_rxp_i[9] ]; # Bank 225 - MGTYRXP2_225 +# set_property PACKAGE_PIN AT6 [get_ports pci_exp_txn_o[10]]; # Bank 225 - MGTYTXN1_225 +# set_property PACKAGE_PIN AT7 [get_ports pci_exp_txp_o[10]]; # Bank 225 - MGTYTXP1_225 +# set_property PACKAGE_PIN AU8 [get_ports pci_exp_txn_o[11]]; # Bank 225 - MGTYTXN0_225 +# set_property PACKAGE_PIN AU9 [get_ports pci_exp_txp_o[11]]; # Bank 225 - MGTYTXP0_225 +# set_property PACKAGE_PIN AP6 [get_ports pci_exp_txn_o[8] ]; # Bank 225 - MGTYTXN3_225 +# set_property PACKAGE_PIN AP7 [get_ports pci_exp_txp_o[8] ]; # Bank 225 - MGTYTXP3_225 +# set_property PACKAGE_PIN AR8 [get_ports pci_exp_txn_o[9] ]; # Bank 225 - MGTYTXN2_225 +# set_property PACKAGE_PIN AR9 [get_ports pci_exp_txp_o[9] ]; # Bank 225 - MGTYTXP2_225 +# set_property PACKAGE_PIN AV1 [get_ports pci_exp_rxn_i[12]]; # Bank 224 - MGTYRXN3_224 +# set_property PACKAGE_PIN AV2 [get_ports pci_exp_rxp_i[12]]; # Bank 224 - MGTYRXP3_224 +# set_property PACKAGE_PIN AW3 [get_ports pci_exp_rxn_i[13]]; # Bank 224 - MGTYRXN2_224 +# set_property PACKAGE_PIN AW4 [get_ports pci_exp_rxp_i[13]]; # Bank 224 - MGTYRXP2_224 +# set_property PACKAGE_PIN BA1 [get_ports pci_exp_rxn_i[14]]; # Bank 224 - MGTYRXN1_224 +# set_property PACKAGE_PIN BA2 [get_ports pci_exp_rxp_i[14]]; # Bank 224 - MGTYRXP1_224 +# set_property PACKAGE_PIN BC1 [get_ports pci_exp_rxn_i[15]]; # Bank 224 - MGTYRXN0_224 +# set_property PACKAGE_PIN BC2 [get_ports pci_exp_rxp_i[15]]; # Bank 224 - MGTYRXP0_224 +# set_property PACKAGE_PIN AV6 [get_ports pci_exp_txn_o[12]]; # Bank 224 - MGTYTXN3_224 +# set_property PACKAGE_PIN AV7 [get_ports pci_exp_txp_o[12]]; # Bank 224 - MGTYTXP3_224 +# set_property PACKAGE_PIN BB4 [get_ports pci_exp_txn_o[13]]; # Bank 224 - MGTYTXN2_224 +# set_property PACKAGE_PIN BB5 [get_ports pci_exp_txp_o[13]]; # Bank 224 - MGTYTXP2_224 +# set_property PACKAGE_PIN BD4 [get_ports pci_exp_txn_o[14]]; # Bank 224 - MGTYTXN1_224 +# set_property PACKAGE_PIN BD5 [get_ports pci_exp_txp_o[14]]; # Bank 224 - MGTYTXP1_224 +# set_property PACKAGE_PIN BF4 [get_ports pci_exp_txn_o[15]]; # Bank 224 - MGTYTXN0_224 +# set_property PACKAGE_PIN BF5 [get_ports pci_exp_txp_o[15]]; # Bank 224 - MGTYTXP0_224 \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/au280.xdc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/au280.xdc new file mode 100644 index 0000000000000000000000000000000000000000..ae3472be7133e95e37f51c40b0c79493e1a3ce04 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/au280.xdc @@ -0,0 +1,2024 @@ +############################################################################ +# DISCLAIMER: +# XILINX IS DISCLOSING THIS USER GUIDE, MANUAL, RELEASE NOTE, +# SCHEMATIC, AND/OR SPECIFICATION (THE “DOCUMENTATION”)TO YOU SOLELY +# FOR USE IN THE DEVELOPMENT OF DESIGNS TO OPERATE WITH XILINX +# HARDWARE DEVICES. YOU MAY NOT REPRODUCE, DISTRIBUTE, REPUBLISH, +# DOWNLOAD, DISPLAY, POST, OR TRANSMIT THE DOCUMENTATION IN ANY FORM +# OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC, +# MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE +# PRIOR WRITTEN CONSENT OF XILINX. XILINX EXPRESSLY DISCLAIMS ANY +# LIABILITY ARISING OUT OF YOUR USE OF THE DOCUMENTATION. +# XILINX RESERVES THE RIGHT, AT ITS SOLE DISCRETION, TO CHANGE THE +# DOCUMENTATION WITHOUT NOTICE AT ANY TIME. XILINX ASSUMES NO +# OBLIGATION TO CORRECT ANY ERRORS CONTAINED IN THE DOCUMENTATION, +# OR TO ADVISE YOU OF ANY CORRECTIONS OR UPDATES. XILINX EXPRESSLY +# DISCLAIMS ANY LIABILITY IN CONNECTION WITH TECHNICAL SUPPORT OR +# ASSISTANCETHAT MAY BE PROVIDED TO YOU IN CONNECTION WITH THE +# DOCUMENTATION. +# THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF +# ANY OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINXBE LIABLE FOR ANY +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR +# NONINFRINGEMENT STATUTORY, REGARDING THEDOCUMENTATION, INCLUDING +# ANY WARRANTIES OF KIND. +# XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR THE +# DOCUMENTATION. INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING +# FROM YOUR USE OF CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR +# INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, +# ARISING FROM YOUR USE OF THE DOCUMENTATION. +# +# +# AU280 HBM - Master XDC +# +# Key Notes: +# 1) PCIe Clocks Support x16 and x8 Bifurcation with both synchronous or asynchronous operation +# 2) Power warning constraint set to warn user if design exceeds 160 Watts +# 3) Refer to XAPP1321 for DDR4 Self refresh and fast calibration. +# +# Clock Trees +# +# 1) AB-557-03 - ABRACON AB-557-03-HCHC-F-L-C-T @ 100.000Mhz Dual Output PCIe MEMs Oscillator +# +# - OUT0--> SYS_CLK5_P/SYS_CLK5_N @ 100.000Mhz - PCIe REFCLK1 for x16 and Bifurcated x8 Lanes 8-15 Asynchronous Clocking +# PINS: MGTREFCLK1P_225_AP13/MGTREFCLK1N_225_AP12 +# +# - OUT1--> SYSCLK_P/SYSCLK_P @ 100.000Mhz 1-to-4 Clock buffer +# | +# |--> SI53340-B-GM --> OUT0 SYSCLK0_P/SYSCLK0_N 100.000Mhz - System Clock for first DDR4 MIG interface and HBM Interfaces. +# | PINS: IO_L12P_T1U_N10_GC_A08_D24_65/IO_L12N_T1U_N11_GC_A09_D25_65 +# | +# |-> OUT1 SYSCLK1_P/SYSCLK1_N 100.000Mhz - System Clock for second DDR4 MIG interface. +# | PINS: IO_L13P_T2L_N0_GC_QBC_69/IO_L13N_T2L_N1_GC_QBC_69 +# | +# |-> OUT2 SYSCLK2_P/SYSCLK2_N 100.000Mhz - PCIe REFCLK1 for Bifurcated x8 Lanes 0-7 Asynchronous Clocking +# | PINS: MGTREFCLK1P_227_AK13/MGTREFCLK1N_227_AK12 +# | +# |-> OUT3 SYSCLK3_P/SYSCLK3_N 100.000Mhz - BANK 75 100Mhz Input clock +# PINS: IO_L11P_T1U_N8_GC_75/IO_L11N_T1U_N9_GC_75 +# +# 2) SI570 - SiLabs 570BAB000544DG @ 156.250Mhz Programmable Oscillator (Re-programming I2C access ONLY possible via Satellite Controller) +# +# - OUT---> SI570_OUTPUT_P/SI570_OUTPUT_N @ 156.250Mhz LVDS +# | +# |--> SI53340-B-GM --> OUT0 USER_SI570_CLOCK_P/USER_SI570_CLOCK_N 156.250Mhz - General Perpose System Clock. +# | PINS: IO_L12P_T1U_N10_GC_75_G30/IO_L12N_T1U_N11_GC_75_F30 +# | +# |-> OUT1 Not Connected +# | PINS: NA +# | +# |-> OUT2 MGT_SI570_CLOCK0_C_P/MGT_SI570_CLOCK0_C_N 156.250Mhz - QSFP0 REFCLK0 +# | PINS: MGTREFCLK0P_134_T42/MGTREFCLK0N_134_T43 +# | +# |-> OUT3 MGT_SI570_CLOCK1_C_P/MGT_SI570_CLOCK1_C_N 156.250Mhz - QSFP0 REFCLK1 +# PINS: MGTREFCLK0P_135_P42/MGTREFCLK0N_135_P43 +# +# 3) SI546 - SiLabs 546BAB001028BBG Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP0 REFCLK1 +# +# - OE_B <-- Active low input to SI546 to enable output frequency - Connected to +# PINS: "QSFP0_OEB" - IO_L9P_T1L_N4_AD12P_75_H32 +# - FS <-- Clock Select Pin FS = 1 -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z or driven High) +# FS = 0 -> 156.25 MHz 1.8V LVDS When driven low by FPGA +# PINS: "QSFP0_FS" - IO_L9N_T1L_N5_AD12N_75_G32 +# +# - OUT0--> QSFP0_CLOCK_P/QSFP0_CLOCK_N @ 161.1328125Mhz +# PINS: MGTREFCLK1P_134_R40/MGTREFCLK1N_134_R41 +# +# 4) SI546 - SiLabs 546BAB001028BBG Selectable output Oscillator 156.2500Mhz/161.1328125Mhz For QSFP1 REFCLK1 +# +# - OE_B <-- Active low input to SI546 to enable output frequency - Connected to +# PINS: QSFP1_OEB - IO_L8N_T1L_N3_AD5N_75_H30 +# - FS <-- Clock Select Pin FS = 1 -> 161.132812 MHz 1.8V LVDS (default when FPGA pin Hi-Z or driven High) +# FS = 0 -> 156.25 MHz 1.8V LVDS when driven low by FPGA +# PINS: "QSFP1_FS" - IO_L7N_T1L_N1_QBC_AD13N_75_G33 +# +# - OUT0--> QSFP1_CLOCK_P/QSFP1_CLOCK_N @ 161.1328125Mhz +# PINS: MGTREFCLK1P_135_M42/MGTREFCLK1N_135_M43 +# +# +# 5) PCIE Fingers PEX_REFCLK_P/PEX_REFCLK_P 100.000Mhz +# |-> SI53322-B-GM --> OUT0 PCIE_CLK0_P/PCIE_CLK0_N 100.000Mhz - PCIe REFCLK0 for Bifurcated x8 Lanes 0-7 synchronous Clocking +# | PINS: MGTREFCLK0P_227_AL15/MGTREFCLK0N_227_AL14 +# | +# |-> OUT1 PCIE_CLK1_P/PCIE_CLK1_N 100.000Mhz - PCIe REFCLK0 for x16 and Bifurcated x8 Lanes 8-15 synchronous Clocking +# PINS: MGTREFCLK0P_225_AR15/MGTREFCLK0N_225_AR14 +# +# Revision 1.00 - Intial Release for AU280 ES1 +# Revision 2.00 - Intial Release for Production Release AU280 (not for use on ES1 version cards ) +# Revision 2.01 - Fixed text typos. +# Revision 2.02 - Corrected PN typos on clocks and DIFF_SSTL12_DCI on DDR4 clocks. +# Revision 2.03 - Added Bitstream generation constraints. +# Revision 2.04 - Added pulldown constraint to CATTRIP signal incase desing does not use it. +# +################################################################################# +# +# Power Constraint to warn User if Desing will possibly be over cards power limit, this assume the 2x4 PCIe AUX power is connectd to the board. +# +set_operating_conditions -design_power_budget 160 +# +# Bitstream generation +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design] ;# Golden image is the fall back image if new bitstream is corrupted. +set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] +set_property CONFIG_MODE SPIx4 [current_design] +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] +#set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design] ;# Customer can try but may not be reliable over all conditions. +set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN disable [current_design] +set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] +set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design] ;# Choices are pullnone, pulldown, and pullup. +set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design] +# +# LVDS Input SYSTEM CLOCKS for Memory Interfaces (1.2V banks 65 and 69) +# +set_property PACKAGE_PIN BJ44 [get_ports clk_300mhz_0_n_i]; # [ get_ports {SYS_CLK0_N} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property IOSTANDARD LVDS [get_ports clk_300mhz_0_n_i]; # [ get_ports {SYS_CLK0_N} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +set_property PACKAGE_PIN BJ43 [get_ports clk_300mhz_0_p_i]; # [ get_ports {SYS_CLK0_P} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +set_property IOSTANDARD LVDS [get_ports clk_300mhz_0_p_i]; # [ get_ports {SYS_CLK0_P} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +# <<<>>> No external BIAS on AC coupled LVDS clock inputs to 1.2V bank so this constraint is added to recenter LVDS signal on 1.2V IO standard. +set_property DQS_BIAS TRUE [get_ports clk_300mhz_0_p_i]; # [ get_ports {SYS_CLK0_P} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +# +set_property PACKAGE_PIN BJ6 [ get_ports {clk_300mhz_1_n_i} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_N" - IO_L13N_T2L_N1_GC_QBC_69 +set_property IOSTANDARD LVDS [ get_ports {clk_300mhz_1_n_i} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_N" - IO_L13N_T2L_N1_GC_QBC_69 +set_property PACKAGE_PIN BH6 [ get_ports {clk_300mhz_1_p_i} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_P" - IO_L13P_T2L_N0_GC_QBC_69 +set_property IOSTANDARD LVDS [ get_ports {clk_300mhz_1_p_i} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_P" - IO_L13P_T2L_N0_GC_QBC_69 +# <<<>>> No external BIAS on AC coupled LVDS clock inputs to 1.2V bank so this constraint is added to recenter LVDS signal on 1.2V IO standard. +set_property DQS_BIAS TRUE [ get_ports {clk_300mhz_1_p_i} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_P" - IO_L13P_T2L_N0_GC_QBC_69 +# # +# # LVDS Input SYSTEM CLOCKS (1.8V bank 75) General Purpose and HBM Clock Sources +# # +# set_property PACKAGE_PIN F31 [get_ports {SYS_CLK3_N} ] ;# Bank 75 VCCO - VCC1V8 Net "SYSCLK3_N" - IO_L11N_T1U_N9_GC_75 +# set_property IOSTANDARD LVDS [get_ports {SYS_CLK3_N} ] ;# Bank 75 VCCO - VCC1V8 Net "SYSCLK3_N" - IO_L11N_T1U_N9_GC_75 +# set_property PACKAGE_PIN G31 [get_ports {SYS_CLK3_P} ] ;# Bank 75 VCCO - VCC1V8 Net "SYSCLK3_P" - IO_L11P_T1U_N8_GC_75 +# set_property IOSTANDARD LVDS [get_ports {SYS_CLK3_P} ] ;# Bank 75 VCCO - VCC1V8 Net "SYSCLK3_P" - IO_L11P_T1U_N8_GC_75 +# # +# set_property PACKAGE_PIN F30 [get_ports {USER_SI570_CLOCK_N}] ;# Bank 75 VCCO - VCC1V8 Net "USER_SI570_CLOCK_N" - IO_L12N_T1U_N11_GC_75 +# set_property IOSTANDARD LVDS [get_ports {USER_SI570_CLOCK_N}] ;# Bank 75 VCCO - VCC1V8 Net "USER_SI570_CLOCK_N" - IO_L12N_T1U_N11_GC_75 +# set_property PACKAGE_PIN G30 [get_ports {USER_SI570_CLOCK_P}] ;# Bank 75 VCCO - VCC1V8 Net "USER_SI570_CLOCK_P" - IO_L12P_T1U_N10_GC_75 +# set_property IOSTANDARD LVDS [get_ports {USER_SI570_CLOCK_P}] ;# Bank 75 VCCO - VCC1V8 Net "USER_SI570_CLOCK_P" - IO_L12P_T1U_N10_GC_75 +# +# MGT Clocks +# +# PCIe Clocks +# +# Input Clocks for Gen3 x16 or Dual x8 Bifurcation on Lane 8-15 +# PCIE_CLK1 -> PCIe 100Mhz Host clock +# SYS_CLK5 -> PCIe 100Mhz Asynchrnous clock +# set_property PACKAGE_PIN AR14 [get_ports {PCIE_CLK1_N} ] ;# Bank 225 - MGTREFCLK0N_225 +# set_property PACKAGE_PIN AR15 [get_ports {PCIE_CLK1_P} ] ;# Bank 225 - MGTREFCLK0P_225 +# set_property PACKAGE_PIN AP12 [get_ports {SYS_CLK5_N}] ;# Bank 225 - MGTREFCLK1N_225 +# set_property PACKAGE_PIN AP13 [get_ports {SYS_CLK5_P}] ;# Bank 225 - MGTREFCLK1P_225 +# +# Input Clocks for Dual x8 Bifurcation on Lane 0-7 +# PCIE_CLK0 -> PCIe 100Mhz Host clock +# SYS_CLK2 -> PCIe 100Mhz Asynchrnous clock +set_property PACKAGE_PIN AL14 [get_ports pcie_refclk_n_i]; # [ get_ports {PCIE_CLK0_N} ] ;# Bank 227 - MGTREFCLK0N_227 +set_property PACKAGE_PIN AL15 [get_ports pcie_refclk_p_i]; #[ get_ports {PCIE_CLK0_P} ] ;# Bank 227 - MGTREFCLK0P_227 +# set_property PACKAGE_PIN AK12 [get_ports {SYS_CLK2_N} ] ;# Bank 227 - MGTREFCLK1N_227 +# set_property PACKAGE_PIN AK13 [get_ports {SYS_CLK2_P} ] ;# Bank 227 - MGTREFCLK1P_227 +# +create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p_i] +# +set_false_path -from [get_ports pcie_resetn_i] +set_input_delay 0 [get_ports pcie_resetn_i] +# Input Clocks and Controls for QSFP28 Port 0 +# +# MGT_SI570_CLOCK0 -> MGT Ref Clock 0 156.25MHz Default (Not User re-programmable) +# QSFP0_CLOCK -> MGT Ref Clock 1 User selectable by QSFP0_FS=0 161.132812 MHz and QSFP0_FS=1 156.250MHz; QSFP0_OEB must driven low to enable clock output +# +# set_property PACKAGE_PIN T43 [get_ports "MGT_SI570_CLOCK0_N"] ;# Bank 134 - MGTREFCLK0N_134 +# set_property PACKAGE_PIN T42 [get_ports "MGT_SI570_CLOCK0_P"] ;# Bank 134 - MGTREFCLK0P_134 +# set_property PACKAGE_PIN R41 [get_ports "QSFP0_CLOCK_N"] ;# Bank 134 - MGTREFCLK1N_134 +# set_property PACKAGE_PIN R40 [get_ports "QSFP0_CLOCK_P"] ;# Bank 134 - MGTREFCLK1P_134 +# # QSFP0_CLOCK control signals +# set_property PACKAGE_PIN G32 [get_ports "QSFP0_FS" ] ;# Bank 75 VCCO - VCC1V8 Net "QSFP0_FS" - IO_L9N_T1L_N5_AD12N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP0_FS" ] ;# Bank 75 VCCO - VCC1V8 Net "QSFP0_FS" - IO_L9N_T1L_N5_AD12N_75 +# set_property PACKAGE_PIN H32 [get_ports "QSFP0_OEB"] ;# Bank 75 VCCO - VCC1V8 Net "QSFP0_OEB" - IO_L9P_T1L_N4_AD12P_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP0_OEB"] ;# Bank 75 VCCO - VCC1V8 Net "QSFP0_OEB" - IO_L9P_T1L_N4_AD12P_75 +# +# Input Clocks and Controls for QSFP28 Port 1 +# +# MGT_SI570_CLOCK1_N -> MGT Ref Clock 0 156.25MHz Default (Not User re-programmable) +# QSFP1_CLOCK_N -> MGT Ref Clock 1 User selectable by QSFP1_FS=0 161.132812 MHz and QSFP1_FS=1 156.250MHz; QSFP1_OEB must be low to enable clock output +# +# set_property PACKAGE_PIN P43 [get_ports "MGT_SI570_CLOCK1_N"] ;# Bank 135 - MGTREFCLK0N_135 +# set_property PACKAGE_PIN P42 [get_ports "MGT_SI570_CLOCK1_P"] ;# Bank 135 - MGTREFCLK0P_135 +# set_property PACKAGE_PIN M43 [get_ports "QSFP1_CLOCK_N"] ;# Bank 135 - MGTREFCLK1N_135 +# set_property PACKAGE_PIN M42 [get_ports "QSFP1_CLOCK_P"] ;# Bank 135 - MGTREFCLK1P_135 +# set_property PACKAGE_PIN H30 [get_ports "QSFP1_OEB"] ;# Bank 75 VCCO - VCC1V8 Net "QSFP1_OEB" - IO_L8N_T1L_N3_AD5N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_OEB"] ;# Bank 75 VCCO - VCC1V8 Net "QSFP1_OEB" - IO_L8N_T1L_N3_AD5N_75 +# set_property PACKAGE_PIN G33 [get_ports "QSFP1_FS"] ;# Bank 75 VCCO - VCC1V8 Net "QSFP1_FS" - IO_L7N_T1L_N1_QBC_AD13N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "QSFP1_FS"] ;# Bank 75 VCCO - VCC1V8 Net "QSFP1_FS" - IO_L7N_T1L_N1_QBC_AD13N_75 +# +# Create Clock Constraints +# +# create_clock -period 10.000 -name sysclk0 [get_ports "SYS_CLK0_P"] +# create_clock -period 10.000 -name sysclk1 [get_ports "SYS_CLK1_P"] +# create_clock -period 10.000 -name sysclk3 [get_ports "SYS_CLK3_P"] +# create_clock -period 10.000 -name pcie_ref_clk0 [get_ports "PCIE_CLK0_P"] +# create_clock -period 10.000 -name async_ref_clk0 [get_ports "SYS_CLK2_P"] +# create_clock -period 10.000 -name pcie_ref_clk1 [get_ports "PCIE_CLK1_P"] +# create_clock -period 10.000 -name async_ref_clk1 [get_ports "SYS_CLK5_P"] +# create_clock -period 6.400 -name gt0refclk0 [get_ports "MGT_SI570_CLOCK0_P"] +# create_clock -period 6.206 -name gt0refclk1 [get_ports "QSFP0_CLOCK_P"] +# create_clock -period 6.400 -name gt1refclk0 [get_ports "MGT_SI570_CLOCK1_P"] +# create_clock -period 6.206 -name gt1refclk1 [get_ports "QSFP1_CLOCK_P"] +# +# PCIe Connections Bank 67 and Bank 75 (1.8V bank) +# PCIE_PERSTN Active low input from PCIe Connector to Ultrascale+ Device to detect presence. +# PEX_PWRBRKN Active low input from PCIe Connector Signaling PCIe card to shut down card power in Server failing condition. +# +# set_property PACKAGE_PIN C32 [get_ports "PEX_PWRBRKN"] ;# Bank 75 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "PEX_PWRBRKN"] ;# Bank 75 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_75 +set_property PACKAGE_PIN BH26 [get_ports pcie_resetn_i]; # [get_ports "PCIE_PERST"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +set_property IOSTANDARD LVCMOS18 [get_ports pcie_resetn_i]; # [get_ports "PCIE_PERST"] ;# Bank 67 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_67 +# +# Bank 75 Ultrascale+ Device SYSMON I2C Slave Interface to Sattelite Controller to monitor Ultrascale+ Device Temperatures and Voltages. +# SYSMON_SCL Slave I2C clock connection from Satellite Controller to Ultrascale+ Device +# SYSMON_SDA Slave I2C data connection from Satellite Controller to Ultrascale+ Device +# +# set_property PACKAGE_PIN B28 [get_ports "SYSMON_SDA"] ;# Bank 75 VCCO - VCC1V8 - IO_L24P_T3U_N10_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SDA"] ;# Bank 75 VCCO - VCC1V8 - IO_L24P_T3U_N10_75 +# set_property PACKAGE_PIN A30 [get_ports "SYSMON_SCL"] ;# Bank 75 VCCO - VCC1V8 - IO_L23N_T3U_N9_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "SYSMON_SCL"] ;# Bank 75 VCCO - VCC1V8 - IO_L23N_T3U_N9_75 +# +# Bank 75 Ultrascale+ Device I2C Slave Interface to Sattelite Controller. +# I2C_FPGA_SCL Slave I2C clock connection from Satellite Controller to Ultrascale+ Device +# I2C_FPGA_SDA Slave I2C data connection from Satellite Controller to Ultrascale+ Device +# I2C_MUX0_INTB_FPGA Slave I2C active low interrupt output from Ultrascale+ Device to Satellite Controller +# I2C_MAIN_INT_B Slave I2C active low system interrupt output from Ultrascale+ Device to Satellite Controller +# +# set_property PACKAGE_PIN B31 [get_ports "I2C_MAIN_INT_B"] ;# Bank 75 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "I2C_MAIN_INT_B"] ;# Bank 75 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_75 +# set_property PACKAGE_PIN D31 [get_ports "I2C_MUX0_INTB_FPGA"] ;# Bank 75 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "I2C_MUX0_INTB_FPGA"] ;# Bank 75 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_75 +# set_property PACKAGE_PIN C33 [get_ports "I2C_FPGA_SDA"] ;# Bank 75 VCCO - VCC1V8 - IO_T2U_N12_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "I2C_FPGA_SDA"] ;# Bank 75 VCCO - VCC1V8 - IO_T2U_N12_75 +# set_property PACKAGE_PIN C30 [get_ports "I2C_FPGA_SCL"] ;# Bank 75 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "I2C_FPGA_SCL"] ;# Bank 75 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_75 +# +# Bank 75 FPGA UART Interface to FTDI FT4232 Port 3 of 4 (User selectable Baud) +# USB_UART_RX Input from FT4232 UART to FPGA +# USB_UART_TX Output from FPGA to FT4232 UART +# +# set_property PACKAGE_PIN A28 [get_ports "USB_UART_TX"] ;# Bank 75 VCCO - VCC1V8 - IO_L24N_T3U_N11_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_TX"] ;# Bank 75 VCCO - VCC1V8 - IO_L24N_T3U_N11_75 +# set_property PACKAGE_PIN B33 [get_ports "USB_UART_RX"] ;# Bank 75 VCCO - VCC1V8 - IO_T3U_N12_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "USB_UART_RX"] ;# Bank 75 VCCO - VCC1V8 - IO_T3U_N12_75 +# +# Bank 75 Ultrascale+ Device to Satellite Controller CMS UART Interface (115200, No parity, 8 bits, 1 stop bit) +# FPGA_RXD_MSP Input from Satellite Controller UART to Ultrascale+ Device +# FPGA_TXD_MSP Output from Ultrascale+ Device to Satellite Controller UART +# This interface is used for the CMS command path, refer to https://www.xilinx.com/products/intellectual-property/cms-subsystem.html and Xilinx PG348 +# +# set_property PACKAGE_PIN D29 [get_ports "FPGA_TXD_MSP"] ;# Bank 75 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_TXD_MSP"] ;# Bank 75 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_75 +# set_property PACKAGE_PIN E28 [get_ports "FPGA_RXD_MSP"] ;# Bank 75 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_RXD_MSP"] ;# Bank 75 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_75 +# +# HBM Catastrophic Over temperature Output signal to Satellite Controller +# HBM_CATTRIP Active high indicator to Satellite controller to indicate the HBM has exceeded its maximum allowable temperature. +# This signal is not a dedicated Ultrascale+ Device output and is a derived signal in RTL. Making the signal Active will shut +# the Ultrascale+ Device power rails off. +# +# set_property PACKAGE_PIN D32 [get_ports "HBM_CATTRIP"] ;# Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "HBM_CATTRIP"] ;# Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +# set_property PULLDOWN TRUE [get_ports "HBM_CATTRIP"] ;# Bank 75 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_75 +# +# DDR4_RESET_GATE Active High Output from Ultrascale+ Device to hold all External DDR4 interfaces in Self refresh. +# This Output disconnects the Memory interface reset and holds it in active and pulls the Clock Enables signal on the Memory Interfaces. +# Refer to XAPP1321 for details on Self refresh mode. +# +# set_property PACKAGE_PIN H33 [get_ports "DDR4_RESET_GATE"] ;# Bank 75 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "DDR4_RESET_GATE"] ;# Bank 75 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_75 +# +# GPIO_MSP0/1/2/3 General purpose IO interconnects between Ultrascale+ Device and Satellite Controller. Currently not used. +# +#set_property PACKAGE_PIN K28 [get_ports "GPIO_MSP0"] ;# Bank 75 VCCO - VCC1V8 - IO_T0U_N12_VRP_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_MSP0"] ;# Bank 75 VCCO - VCC1V8 - IO_T0U_N12_VRP_75 +#set_property PACKAGE_PIN J29 [get_ports "GPIO_MSP1"] ;# Bank 75 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_MSP1"] ;# Bank 75 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_75 +#set_property PACKAGE_PIN K29 [get_ports "GPIO_MSP2"] ;# Bank 75 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_MSP2"] ;# Bank 75 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_75 +#set_property PACKAGE_PIN J31 [get_ports "GPIO_MSP3"] ;# Bank 75 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "GPIO_MSP3"] ;# Bank 75 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_75 +# +# CPU_RESET_FPGA Connects to SW1 push button On the top edge of the PCB Assembly, also connects to Satellite Contoller +# Desinged to be a active low reset input to the FPGA. +# +# set_property PACKAGE_PIN L30 [get_ports "CPU_RESET_FPGA"] ;# Bank 75 VCCO - VCC1V8 - IO_L2N_T0L_N3_75 +# set_property IOSTANDARD LVCMOS18 [get_ports "CPU_RESET_FPGA"] ;# Bank 75 VCCO - VCC1V8 - IO_L2N_T0L_N3_75 +# +# Test point unaccessable to user due to Haetsink. +# +#set_property PACKAGE_PIN L33 [get_ports "TESTCLK_OUT"] ;# Bank 75 VCCO - VCC1V8 Net TESTCLK_OUT - IO_L1P_T0L_N0_DBC_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "TESTCLK_OUT"] ;# Bank 75 VCCO - VCC1V8 Net TESTCLK_OUT - IO_L1P_T0L_N0_DBC_75 +# +# DDR4 RDIMM Controller 0, 72-bit Data Interface, x4 Componets, Single Rank +# <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# +set_property PACKAGE_PIN BE51 [ get_ports c0_ddr4_dq[42] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[42] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ42" - IO_L24N_T3U_N11_66 +set_property PACKAGE_PIN BD51 [ get_ports c0_ddr4_dq[43] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[43] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ43" - IO_L24P_T3U_N10_66 +set_property PACKAGE_PIN BE50 [ get_ports c0_ddr4_dq[40] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[40] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ40" - IO_L23N_T3U_N9_66 +set_property PACKAGE_PIN BE49 [ get_ports c0_ddr4_dq[41] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[41] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ41" - IO_L23P_T3U_N8_66 +set_property PACKAGE_PIN BF48 [ get_ports c0_ddr4_dqs_c[10] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[10] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C5" - IO_L22N_T3U_N7_DBC_AD0N_66 +set_property PACKAGE_PIN BF47 [ get_ports c0_ddr4_dqs_t[10] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[10] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T5" - IO_L22P_T3U_N6_DBC_AD0P_66 +set_property PACKAGE_PIN BF52 [ get_ports c0_ddr4_dq[44] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[44] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ44" - IO_L21N_T3L_N5_AD8N_66 +set_property PACKAGE_PIN BF51 [ get_ports c0_ddr4_dq[45] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - IO_L21P_T3L_N4_AD8P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[45] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ45" - IO_L21P_T3L_N4_AD8P_66 +set_property PACKAGE_PIN BG50 [ get_ports c0_ddr4_dq[46] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[46] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ46" - IO_L20N_T3L_N3_AD1N_66 +set_property PACKAGE_PIN BF50 [ get_ports c0_ddr4_dq[47] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[47] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ47" - IO_L20P_T3L_N2_AD1P_66 +set_property PACKAGE_PIN BG49 [ get_ports c0_ddr4_dqs_c[11] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[11] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C14" - IO_L19N_T3L_N1_DBC_AD9N_66 +set_property PACKAGE_PIN BG48 [ get_ports c0_ddr4_dqs_t[11] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[11] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T14" - IO_L19P_T3L_N0_DBC_AD9P_66 +#set_property PACKAGE_PIN BG47 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T3U_N12_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T3U_N12_66 +#set_property PACKAGE_PIN BF53 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T2U_N12_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T2U_N12_66 +set_property PACKAGE_PIN BE54 [ get_ports c0_ddr4_dq[67] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[67] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ67" - IO_L18N_T2U_N11_AD2N_66 +set_property PACKAGE_PIN BE53 [ get_ports c0_ddr4_dq[66] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[66] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ66" - IO_L18P_T2U_N10_AD2P_66 +set_property PACKAGE_PIN BG54 [ get_ports c0_ddr4_dq[64] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[64] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ64" - IO_L17N_T2U_N9_AD10N_66 +set_property PACKAGE_PIN BG53 [ get_ports c0_ddr4_dq[65] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[65] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ65" - IO_L17P_T2U_N8_AD10P_66 +set_property PACKAGE_PIN BJ54 [ get_ports c0_ddr4_dqs_c[16] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[16] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C8" - IO_L16N_T2U_N7_QBC_AD3N_66 +set_property PACKAGE_PIN BH54 [ get_ports c0_ddr4_dqs_t[16] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[16] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T8" - IO_L16P_T2U_N6_QBC_AD3P_66 +set_property PACKAGE_PIN BK54 [ get_ports c0_ddr4_dq[70] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[70] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ70" - IO_L15N_T2L_N5_AD11N_66 +set_property PACKAGE_PIN BK53 [ get_ports c0_ddr4_dq[71] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[71] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ71" - IO_L15P_T2L_N4_AD11P_66 +set_property PACKAGE_PIN BH52 [ get_ports c0_ddr4_dq[68] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[68] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ68" - IO_L14N_T2L_N3_GC_66 +set_property PACKAGE_PIN BG52 [ get_ports c0_ddr4_dq[69] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[69] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ69" - IO_L14P_T2L_N2_GC_66 +set_property PACKAGE_PIN BJ53 [ get_ports c0_ddr4_dqs_c[17] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[17] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C17" - IO_L13N_T2L_N1_GC_QBC_66 +set_property PACKAGE_PIN BJ52 [ get_ports c0_ddr4_dqs_t[17] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[17] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T17" - IO_L13P_T2L_N0_GC_QBC_66 +set_property PACKAGE_PIN BH50 [ get_ports c0_ddr4_dq[48] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[48] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ48" - IO_L12N_T1U_N11_GC_66 +set_property PACKAGE_PIN BH49 [ get_ports c0_ddr4_dq[51] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[51] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ51" - IO_L12P_T1U_N10_GC_66 +set_property PACKAGE_PIN BJ51 [ get_ports c0_ddr4_dq[49] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[49] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ49" - IO_L11N_T1U_N9_GC_66 +set_property PACKAGE_PIN BH51 [ get_ports c0_ddr4_dq[50] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[50] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ50" - IO_L11P_T1U_N8_GC_66 +set_property PACKAGE_PIN BJ47 [ get_ports c0_ddr4_dqs_c[12] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[12] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C6" - IO_L10N_T1U_N7_QBC_AD4N_66 +set_property PACKAGE_PIN BH47 [ get_ports c0_ddr4_dqs_t[12] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[12] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T6" - IO_L10P_T1U_N6_QBC_AD4P_66 +set_property PACKAGE_PIN BJ49 [ get_ports c0_ddr4_dq[54] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[54] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ54" - IO_L9N_T1L_N5_AD12N_66 +set_property PACKAGE_PIN BJ48 [ get_ports c0_ddr4_dq[55] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[55] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ55" - IO_L9P_T1L_N4_AD12P_66 +set_property PACKAGE_PIN BK51 [ get_ports c0_ddr4_dq[53] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[53] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ53" - IO_L8N_T1L_N3_AD5N_66 +set_property PACKAGE_PIN BK50 [ get_ports c0_ddr4_dq[52] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[52] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ52" - IO_L8P_T1L_N2_AD5P_66 +set_property PACKAGE_PIN BK49 [ get_ports c0_ddr4_dqs_c[13] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[13] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C15" - IO_L7N_T1L_N1_QBC_AD13N_66 +set_property PACKAGE_PIN BK48 [ get_ports c0_ddr4_dqs_t[13] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[13] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T15" - IO_L7P_T1L_N0_QBC_AD13P_66 +#set_property PACKAGE_PIN BL48 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_66 +#set_property PACKAGE_PIN BL50 #N/A ;# Bank 66 VCCO - VCC1V2 Net "VRP_61" - IO_T0U_N12_VRP_66 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 66 VCCO - VCC1V2 Net "VRP_61" - IO_T0U_N12_VRP_66 +set_property PACKAGE_PIN BL53 [ get_ports c0_ddr4_dq[33] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[33] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ33" - IO_L6N_T0U_N11_AD6N_66 +set_property PACKAGE_PIN BL52 [ get_ports c0_ddr4_dq[34] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[34] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ34" - IO_L6P_T0U_N10_AD6P_66 +set_property PACKAGE_PIN BM52 [ get_ports c0_ddr4_dq[32] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[32] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ32" - IO_L5N_T0U_N9_AD14N_66 +set_property PACKAGE_PIN BL51 [ get_ports c0_ddr4_dq[35] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[35] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ35" - IO_L5P_T0U_N8_AD14P_66 +set_property PACKAGE_PIN BM50 [ get_ports c0_ddr4_dqs_c[8] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[8] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_66 +set_property PACKAGE_PIN BM49 [ get_ports c0_ddr4_dqs_t[8] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[8] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_66 +set_property PACKAGE_PIN BN49 [ get_ports c0_ddr4_dq[38] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[38] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ38" - IO_L3N_T0L_N5_AD15N_66 +set_property PACKAGE_PIN BM48 [ get_ports c0_ddr4_dq[39] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[39] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ39" - IO_L3P_T0L_N4_AD15P_66 +set_property PACKAGE_PIN BN51 [ get_ports c0_ddr4_dq[37] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[37] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ37" - IO_L2N_T0L_N3_66 +set_property PACKAGE_PIN BN50 [ get_ports c0_ddr4_dq[36] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[36] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQ36" - IO_L2P_T0L_N2_66 +set_property PACKAGE_PIN BP49 [ get_ports c0_ddr4_dqs_c[9] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[9] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_C13" - IO_L1N_T0L_N1_DBC_66 +set_property PACKAGE_PIN BP48 [ get_ports c0_ddr4_dqs_t[9] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[9] ] ;# Bank 66 VCCO - VCC1V2 Net "DDR4_C0_DQS_T13" - IO_L1P_T0L_N0_DBC_66 +# +# DDR4 RDIMM Control, Command and Address +# The DIMM interfaces have connectivity to support UDIMM, RDIMM, LRDIMM and 3DS devices. +# The below constraints are configured to support DDR4, Single Rank, RDIMMs with x4 Compnent Connectivity and the unused pins are commented out. +# The System Clock for the MEMORY interface are comemented out and moved to the Clock section of the XDC file +# +set_property PACKAGE_PIN BE44 [ get_ports c0_ddr4_adr[13] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[13] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR13" - IO_L24N_T3U_N11_DOUT_CSO_B_65 +set_property PACKAGE_PIN BE43 [ get_ports c0_ddr4_adr[14] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[14] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR14" - IO_L24P_T3U_N10_EMCCLK_65 +#set_property PACKAGE_PIN BD42 [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_cs_n[2]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B2" - IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65 +#set_property PACKAGE_PIN BC42 [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property IOSTANDARD LVCMOS12 [ get_ports {c0_ddr4_alert_n} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ALERT_B" - IO_L23P_T3U_N8_I2C_SCLK_65 +#set_property PACKAGE_PIN BE46 [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_odt[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT1" - IO_L22N_T3U_N7_DBC_AD0N_D05_65 +#set_property PACKAGE_PIN BE45 [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_cs_n[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B1" - IO_L22P_T3U_N6_DBC_AD0P_D04_65 +set_property PACKAGE_PIN BF43 [ get_ports c0_ddr4_adr[5] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[5] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR5" - IO_L21N_T3L_N5_AD8N_D07_65 +set_property PACKAGE_PIN BF42 [ get_ports c0_ddr4_adr[3] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[3] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR3" - IO_L21P_T3L_N4_AD8P_D06_65 +set_property PACKAGE_PIN BF46 [ get_ports c0_ddr4_adr[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR0" - IO_L20N_T3L_N3_AD1N_D09_65 +set_property PACKAGE_PIN BF45 [ get_ports c0_ddr4_parity ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_parity ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_PAR" - IO_L20P_T3L_N2_AD1P_D08_65 +set_property PACKAGE_PIN BE41 [ get_ports c0_ddr4_bg[1] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_bg[1] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG1" - IO_L19N_T3L_N1_DBC_AD9N_D11_65 +set_property PACKAGE_PIN BD41 [ get_ports c0_ddr4_adr[11] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[11] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR11" - IO_L19P_T3L_N0_DBC_AD9P_D10_65 +set_property PACKAGE_PIN BF41 [ get_ports c0_ddr4_bg[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_bg[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BG0" - IO_T3U_N12_PERSTN0_65 +set_property PACKAGE_PIN BH41 [ get_ports c0_ddr4_act_n ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_act_n ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ACT_B" - IO_T2U_N12_CSI_ADV_B_65 +set_property PACKAGE_PIN BG45 [ get_ports c0_ddr4_adr[10] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[10] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR10" - IO_L18N_T2U_N11_AD2N_D13_65 +set_property PACKAGE_PIN BG44 [ get_ports c0_ddr4_odt[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_odt[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ODT0" - IO_L18P_T2U_N10_AD2P_D12_65 +set_property PACKAGE_PIN BG43 [ get_ports c0_ddr4_adr[1] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[1] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR1" - IO_L17N_T2U_N9_AD10N_D15_65 +set_property PACKAGE_PIN BG42 [ get_ports c0_ddr4_adr[6] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[6] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR6" - IO_L17P_T2U_N8_AD10P_D14_65 +set_property PACKAGE_PIN BJ46 [ get_ports c0_ddr4_ck_c[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports c0_ddr4_ck_c[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C0" - IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65 +set_property PACKAGE_PIN BH46 [ get_ports c0_ddr4_ck_t[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports c0_ddr4_ck_t[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T0" - IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65 +#set_property PACKAGE_PIN BK41 [ get_ports {c0_ddr4_ck_c[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_ck_c[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_C1" - IO_L15N_T2L_N5_AD11N_A03_D19_65 +#set_property PACKAGE_PIN BJ41 [ get_ports {c0_ddr4_ck_t[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_ck_t[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CK_T1" - IO_L15P_T2L_N4_AD11P_A02_D18_65 +set_property PACKAGE_PIN BH45 [ get_ports c0_ddr4_ba[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_ba[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA0" - IO_L14N_T2L_N3_GC_A05_D21_65 +set_property PACKAGE_PIN BH44 [ get_ports c0_ddr4_adr[16] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[16] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR16" - IO_L14P_T2L_N2_GC_A04_D20_65 +#set_property PACKAGE_PIN BJ42 [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_cke[1]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE1" - IO_L13N_T2L_N1_GC_QBC_A07_D23_65 +set_property PACKAGE_PIN BH42 [ get_ports c0_ddr4_cke[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_cke[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CKE0" - IO_L13P_T2L_N0_GC_QBC_A06_D22_65 +# Clocks at top of XDC +#set_property PACKAGE_PIN BJ44 [ get_ports {sys_clk0_n} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property IOSTANDARD LVDS [ get_ports {sys_clk0_n} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_N" - IO_L12N_T1U_N11_GC_A09_D25_65 +#set_property PACKAGE_PIN BJ43 [ get_ports {sys_clk0_p} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property IOSTANDARD LVDS [ get_ports {sys_clk0_p} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +## <<<>>> No external BIAS on AC coupled LVDS clock inputs to 1.2V bank so this constraint is added to recenter LVDS signal on 1.2V IO standard. +#set_property DQS_BIAS TRUE [ get_ports {sys_clk0_p} ] ;# Bank 65 VCCO - VCC1V2 Net "SYSCLK0_P" - IO_L12P_T1U_N10_GC_A08_D24_65 +#set_property PACKAGE_PIN BK44 #N/A ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B3" - IO_L11N_T1U_N9_GC_A11_D27_65 +set_property PACKAGE_PIN BK43 [ get_ports c0_ddr4_adr[8] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[8] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR8" - IO_L11P_T1U_N8_GC_A10_D26_65 +set_property PACKAGE_PIN BK46 [ get_ports c0_ddr4_cs_n[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_cs_n[0] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_CS_B0" - IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65 +set_property PACKAGE_PIN BK45 [ get_ports c0_ddr4_adr[2] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[2] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR2" - IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65 +set_property PACKAGE_PIN BL43 [ get_ports c0_ddr4_adr[7] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[7] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR7" - IO_L9N_T1L_N5_AD12N_A15_D31_65 +set_property PACKAGE_PIN BL42 [ get_ports c0_ddr4_adr[12] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[12] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR12" - IO_L9P_T1L_N4_AD12P_A14_D30_65 +set_property PACKAGE_PIN BL46 [ get_ports c0_ddr4_adr[15] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[15] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR15" - IO_L8N_T1L_N3_AD5N_A17_65 +set_property PACKAGE_PIN BL45 [ get_ports c0_ddr4_adr[4] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[4] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR4" - IO_L8P_T1L_N2_AD5P_A16_65 +set_property PACKAGE_PIN BM47 [ get_ports c0_ddr4_ba[1] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_ba[1] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_BA1" - IO_L7N_T1L_N1_QBC_AD13N_A19_65 +#set_property PACKAGE_PIN BL47 [ get_ports {c0_ddr4_adr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c0_ddr4_adr[17]} ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR17" - IO_L7P_T1L_N0_QBC_AD13P_A18_65 +set_property PACKAGE_PIN BM42 [ get_ports c0_ddr4_adr[9] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 +set_property IOSTANDARD SSTL12_DCI [ get_ports c0_ddr4_adr[9] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_ADR9" - IO_T1U_N12_SMBALERT_65 +set_property PACKAGE_PIN BN45 [ get_ports c0_ddr4_dq[57] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[57] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ57" - IO_L6N_T0U_N11_AD6N_A21_65 +set_property PACKAGE_PIN BM45 [ get_ports c0_ddr4_dq[59] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[59] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ59" - IO_L6P_T0U_N10_AD6P_A20_65 +set_property PACKAGE_PIN BN44 [ get_ports c0_ddr4_dq[56] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[56] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ56" - IO_L5N_T0U_N9_AD14N_A23_65 +set_property PACKAGE_PIN BM44 [ get_ports c0_ddr4_dq[58] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[58] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ58" - IO_L5P_T0U_N8_AD14P_A22_65 +set_property PACKAGE_PIN BP46 [ get_ports c0_ddr4_dqs_c[14] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[14] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C7" - IO_L4N_T0U_N7_DBC_AD7N_A25_65 +set_property PACKAGE_PIN BN46 [ get_ports c0_ddr4_dqs_t[14] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[14] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T7" - IO_L4P_T0U_N6_DBC_AD7P_A24_65 +set_property PACKAGE_PIN BP44 [ get_ports c0_ddr4_dq[61] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[61] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ61" - IO_L3N_T0L_N5_AD15N_A27_65 +set_property PACKAGE_PIN BP43 [ get_ports c0_ddr4_dq[60] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[60] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ60" - IO_L3P_T0L_N4_AD15P_A26_65 +set_property PACKAGE_PIN BP47 [ get_ports c0_ddr4_dq[63] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[63] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ63" - IO_L2N_T0L_N3_FWE_FCS2_B_65 +set_property PACKAGE_PIN BN47 [ get_ports c0_ddr4_dq[62] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[62] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQ62" - IO_L2P_T0L_N2_FOE_B_65 +set_property PACKAGE_PIN BP42 [ get_ports c0_ddr4_dqs_c[15] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[15] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_C16" - IO_L1N_T0L_N1_DBC_RS1_65 +set_property PACKAGE_PIN BN42 [ get_ports c0_ddr4_dqs_t[15] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[15] ] ;# Bank 65 VCCO - VCC1V2 Net "DDR4_C0_DQS_T16" - IO_L1P_T0L_N0_DBC_RS0_65 +set_property PACKAGE_PIN BJ31 [ get_ports c0_ddr4_dq[8] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[8] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ8" - IO_L24N_T3U_N11_64 +set_property PACKAGE_PIN BH31 [ get_ports c0_ddr4_dq[9] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[9] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ9" - IO_L24P_T3U_N10_64 +set_property PACKAGE_PIN BF33 [ get_ports c0_ddr4_dq[11] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[11] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ11" - IO_L23N_T3U_N9_64 +set_property PACKAGE_PIN BF32 [ get_ports c0_ddr4_dq[10] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[10] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ10" - IO_L23P_T3U_N8_64 +set_property PACKAGE_PIN BK30 [ get_ports c0_ddr4_dqs_c[2] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[2] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C1" - IO_L22N_T3U_N7_DBC_AD0N_64 +set_property PACKAGE_PIN BJ29 [ get_ports c0_ddr4_dqs_t[2] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[2] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T1" - IO_L22P_T3U_N6_DBC_AD0P_64 +set_property PACKAGE_PIN BG32 [ get_ports c0_ddr4_dq[15] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[15] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ15" - IO_L21N_T3L_N5_AD8N_64 +set_property PACKAGE_PIN BF31 [ get_ports c0_ddr4_dq[14] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[14] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ14" - IO_L21P_T3L_N4_AD8P_64 +set_property PACKAGE_PIN BH30 [ get_ports c0_ddr4_dq[13] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[13] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ13" - IO_L20N_T3L_N3_AD1N_64 +set_property PACKAGE_PIN BH29 [ get_ports c0_ddr4_dq[12] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[12] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ12" - IO_L20P_T3L_N2_AD1P_64 +set_property PACKAGE_PIN BG30 [ get_ports c0_ddr4_dqs_c[3] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[3] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C10" - IO_L19N_T3L_N1_DBC_AD9N_64 +set_property PACKAGE_PIN BG29 [ get_ports c0_ddr4_dqs_t[3] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[3] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T10" - IO_L19P_T3L_N0_DBC_AD9P_64 +#set_property PACKAGE_PIN BK29 [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +#set_property IOSTANDARD LVCMOS12 [ get_ports {c0_ddr4_event_n} ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_EVENT_B" - IO_T3U_N12_64 +set_property PACKAGE_PIN BG33 [ get_ports c0_ddr4_reset_n ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 +set_property IOSTANDARD LVCMOS12 [ get_ports c0_ddr4_reset_n ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_RESET_N" - IO_T2U_N12_64 +set_property PACKAGE_PIN BH35 [ get_ports c0_ddr4_dq[25] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[25] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ25" - IO_L18N_T2U_N11_AD2N_64 +set_property PACKAGE_PIN BH34 [ get_ports c0_ddr4_dq[24] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[24] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ24" - IO_L18P_T2U_N10_AD2P_64 +set_property PACKAGE_PIN BF36 [ get_ports c0_ddr4_dq[27] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[27] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ27" - IO_L17N_T2U_N9_AD10N_64 +set_property PACKAGE_PIN BF35 [ get_ports c0_ddr4_dq[26] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[26] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ26" - IO_L17P_T2U_N8_AD10P_64 +set_property PACKAGE_PIN BK35 [ get_ports c0_ddr4_dqs_c[6] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[6] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_64 +set_property PACKAGE_PIN BK34 [ get_ports c0_ddr4_dqs_t[6] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[6] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_64 +set_property PACKAGE_PIN BG35 [ get_ports c0_ddr4_dq[31] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[31] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ31" - IO_L15N_T2L_N5_AD11N_64 +set_property PACKAGE_PIN BG34 [ get_ports c0_ddr4_dq[30] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[30] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ30" - IO_L15P_T2L_N4_AD11P_64 +set_property PACKAGE_PIN BJ34 [ get_ports c0_ddr4_dq[29] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[29] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ29" - IO_L14N_T2L_N3_GC_64 +set_property PACKAGE_PIN BJ33 [ get_ports c0_ddr4_dq[28] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[28] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ28" - IO_L14P_T2L_N2_GC_64 +set_property PACKAGE_PIN BJ32 [ get_ports c0_ddr4_dqs_c[7] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[7] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_64 +set_property PACKAGE_PIN BH32 [ get_ports c0_ddr4_dqs_t[7] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[7] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_64 +set_property PACKAGE_PIN BL33 [ get_ports c0_ddr4_dq[19] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[19] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ19" - IO_L12N_T1U_N11_GC_64 +set_property PACKAGE_PIN BK33 [ get_ports c0_ddr4_dq[18] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[18] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ18" - IO_L12P_T1U_N10_GC_64 +set_property PACKAGE_PIN BL31 [ get_ports c0_ddr4_dq[17] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[17] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ17" - IO_L11N_T1U_N9_GC_64 +set_property PACKAGE_PIN BK31 [ get_ports c0_ddr4_dq[16] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[16] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ16" - IO_L11P_T1U_N8_GC_64 +set_property PACKAGE_PIN BM35 [ get_ports c0_ddr4_dqs_c[4] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[4] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C2" - IO_L10N_T1U_N7_QBC_AD4N_64 +set_property PACKAGE_PIN BL35 [ get_ports c0_ddr4_dqs_t[4] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[4] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T2" - IO_L10P_T1U_N6_QBC_AD4P_64 +set_property PACKAGE_PIN BM33 [ get_ports c0_ddr4_dq[21] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[21] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ21" - IO_L9N_T1L_N5_AD12N_64 +set_property PACKAGE_PIN BL32 [ get_ports c0_ddr4_dq[20] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[20] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ20" - IO_L9P_T1L_N4_AD12P_64 +set_property PACKAGE_PIN BP34 [ get_ports c0_ddr4_dq[23] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[23] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ23" - IO_L8N_T1L_N3_AD5N_64 +set_property PACKAGE_PIN BN34 [ get_ports c0_ddr4_dq[22] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[22] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ22" - IO_L8P_T1L_N2_AD5P_64 +set_property PACKAGE_PIN BN35 [ get_ports c0_ddr4_dqs_c[5] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[5] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C11" - IO_L7N_T1L_N1_QBC_AD13N_64 +set_property PACKAGE_PIN BM34 [ get_ports c0_ddr4_dqs_t[5] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[5] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T11" - IO_L7P_T1L_N0_QBC_AD13P_64 +#set_property PACKAGE_PIN BP33 #N/A ;# Bank 64 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_64 +#set_property IOSTANDARD LVCMOS12 #N/A ;# Bank 64 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_64 +set_property PACKAGE_PIN BP32 [ get_ports c0_ddr4_dq[1] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[1] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ1" - IO_L6N_T0U_N11_AD6N_64 +set_property PACKAGE_PIN BN32 [ get_ports c0_ddr4_dq[0] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[0] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ0" - IO_L6P_T0U_N10_AD6P_64 +set_property PACKAGE_PIN BM30 [ get_ports c0_ddr4_dq[3] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[3] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ3" - IO_L5N_T0U_N9_AD14N_64 +set_property PACKAGE_PIN BL30 [ get_ports c0_ddr4_dq[2] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[2] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ2" - IO_L5P_T0U_N8_AD14P_64 +set_property PACKAGE_PIN BN30 [ get_ports c0_ddr4_dqs_c[0] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[0] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C0" - IO_L4N_T0U_N7_DBC_AD7N_64 +set_property PACKAGE_PIN BN29 [ get_ports c0_ddr4_dqs_t[0] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[0] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T0" - IO_L4P_T0U_N6_DBC_AD7P_64 +set_property PACKAGE_PIN BP31 [ get_ports c0_ddr4_dq[6] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[6] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ6" - IO_L3N_T0L_N5_AD15N_64 +set_property PACKAGE_PIN BN31 [ get_ports c0_ddr4_dq[7] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[7] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ7" - IO_L3P_T0L_N4_AD15P_64 +set_property PACKAGE_PIN BP29 [ get_ports c0_ddr4_dq[4] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[4] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ4" - IO_L2N_T0L_N3_64 +set_property PACKAGE_PIN BP28 [ get_ports c0_ddr4_dq[5] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 +set_property IOSTANDARD POD12_DCI [ get_ports c0_ddr4_dq[5] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQ5" - IO_L2P_T0L_N2_64 +set_property PACKAGE_PIN BM29 [ get_ports c0_ddr4_dqs_c[1] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_c[1] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_C9" - IO_L1N_T0L_N1_DBC_64 +set_property PACKAGE_PIN BM28 [ get_ports c0_ddr4_dqs_t[1] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports c0_ddr4_dqs_t[1] ] ;# Bank 64 VCCO - VCC1V2 Net "DDR4_C0_DQS_T9" - IO_L1P_T0L_N0_DBC_64 +# +# DDR4 RDIMM Controller 1, 72-bit Data Interface, x4 Componets, Single Rank +# <<>> DQS Clock strobes have been swapped from JEDEC standard to match Xilinx MIG Clock order: +# JEDEC Order DQS -> 0 9 1 10 2 11 3 12 4 13 5 14 6 15 7 16 8 17 +# Xil MIG Order DQS -> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +# +set_property PACKAGE_PIN A8 [ get_ports {c1_ddr4_dq[3]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ3" - IO_L24N_T3U_N11_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[3]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ3" - IO_L24N_T3U_N11_70 +set_property PACKAGE_PIN A9 [ get_ports {c1_ddr4_dq[2]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ2" - IO_L24P_T3U_N10_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[2]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ2" - IO_L24P_T3U_N10_70 +set_property PACKAGE_PIN A10 [ get_ports {c1_ddr4_dq[1]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ1" - IO_L23N_T3U_N9_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[1]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ1" - IO_L23N_T3U_N9_70 +set_property PACKAGE_PIN A11 [ get_ports {c1_ddr4_dq[0]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ0" - IO_L23P_T3U_N8_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[0]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ0" - IO_L23P_T3U_N8_70 +set_property PACKAGE_PIN A13 [ get_ports {c1_ddr4_dqs_c[0]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C0" - IO_L22N_T3U_N7_DBC_AD0N_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[0]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C0" - IO_L22N_T3U_N7_DBC_AD0N_70 +set_property PACKAGE_PIN B13 [ get_ports {c1_ddr4_dqs_t[0]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T0" - IO_L22P_T3U_N6_DBC_AD0P_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[0]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T0" - IO_L22P_T3U_N6_DBC_AD0P_70 +set_property PACKAGE_PIN B12 [ get_ports {c1_ddr4_dq[4]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ4" - IO_L21N_T3L_N5_AD8N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[4]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ4" - IO_L21N_T3L_N5_AD8N_70 +set_property PACKAGE_PIN C12 [ get_ports {c1_ddr4_dq[6]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ6" - IO_L21P_T3L_N4_AD8P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[6]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ6" - IO_L21P_T3L_N4_AD8P_70 +set_property PACKAGE_PIN B10 [ get_ports {c1_ddr4_dq[5]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ5" - IO_L20N_T3L_N3_AD1N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[5]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ5" - IO_L20N_T3L_N3_AD1N_70 +set_property PACKAGE_PIN B11 [ get_ports {c1_ddr4_dq[7]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ7" - IO_L20P_T3L_N2_AD1P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[7]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ7" - IO_L20P_T3L_N2_AD1P_70 +set_property PACKAGE_PIN C9 [ get_ports {c1_ddr4_dqs_c[1]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C9" - IO_L19N_T3L_N1_DBC_AD9N_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[1]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C9" - IO_L19N_T3L_N1_DBC_AD9N_70 +set_property PACKAGE_PIN C10 [ get_ports {c1_ddr4_dqs_t[1]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T9" - IO_L19P_T3L_N0_DBC_AD9P_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[1]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T9" - IO_L19P_T3L_N0_DBC_AD9P_70 +#set_property PACKAGE_PIN C13 #N/A ;# Bank 70 VCCO - VCC1V2 Net "Not Connected" - IO_T3U_N12_70 +#set_property IOSTANDARD LVCMOS12 #N/A ;# Bank 70 VCCO - VCC1V2 Net "Not Connected" - IO_T3U_N12_70 +#set_property PACKAGE_PIN C14 #N/A ;# Bank 70 VCCO - VCC1V2 Net "Not Connected" - IO_T2U_N12_70 +#set_property IOSTANDARD LVCMOS12 #N/A ;# Bank 70 VCCO - VCC1V2 Net "Not Connected" - IO_T2U_N12_70 +set_property PACKAGE_PIN A14 [ get_ports {c1_ddr4_dq[24]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ27" - IO_L18N_T2U_N11_AD2N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[24]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ27" - IO_L18N_T2U_N11_AD2N_70 +set_property PACKAGE_PIN A15 [ get_ports {c1_ddr4_dq[26]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ25" - IO_L18P_T2U_N10_AD2P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[26]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ25" - IO_L18P_T2U_N10_AD2P_70 +set_property PACKAGE_PIN B15 [ get_ports {c1_ddr4_dq[27]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ24" - IO_L17N_T2U_N9_AD10N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[27]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ24" - IO_L17N_T2U_N9_AD10N_70 +set_property PACKAGE_PIN C15 [ get_ports {c1_ddr4_dq[25]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ26" - IO_L17P_T2U_N8_AD10P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[25]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ26" - IO_L17P_T2U_N8_AD10P_70 +set_property PACKAGE_PIN D14 [ get_ports {c1_ddr4_dqs_c[6]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[6]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C3" - IO_L16N_T2U_N7_QBC_AD3N_70 +set_property PACKAGE_PIN D15 [ get_ports {c1_ddr4_dqs_t[6]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[6]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T3" - IO_L16P_T2U_N6_QBC_AD3P_70 +set_property PACKAGE_PIN E14 [ get_ports {c1_ddr4_dq[29]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ29" - IO_L15N_T2L_N5_AD11N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[29]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ29" - IO_L15N_T2L_N5_AD11N_70 +set_property PACKAGE_PIN F15 [ get_ports {c1_ddr4_dq[28]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ31" - IO_L15P_T2L_N4_AD11P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[28]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ31" - IO_L15P_T2L_N4_AD11P_70 +set_property PACKAGE_PIN F13 [ get_ports {c1_ddr4_dq[31]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ28" - IO_L14N_T2L_N3_GC_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[31]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ28" - IO_L14N_T2L_N3_GC_70 +set_property PACKAGE_PIN F14 [ get_ports {c1_ddr4_dq[30]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ30" - IO_L14P_T2L_N2_GC_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[30]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ30" - IO_L14P_T2L_N2_GC_70 +set_property PACKAGE_PIN D12 [ get_ports {c1_ddr4_dqs_c[7]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[7]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C12" - IO_L13N_T2L_N1_GC_QBC_70 +set_property PACKAGE_PIN E13 [ get_ports {c1_ddr4_dqs_t[7]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[7]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T12" - IO_L13P_T2L_N0_GC_QBC_70 +set_property PACKAGE_PIN E11 [ get_ports {c1_ddr4_dq[8]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ8" - IO_L12N_T1U_N11_GC_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[8]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ8" - IO_L12N_T1U_N11_GC_70 +set_property PACKAGE_PIN F11 [ get_ports {c1_ddr4_dq[11]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ11" - IO_L12P_T1U_N10_GC_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[11]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ11" - IO_L12P_T1U_N10_GC_70 +set_property PACKAGE_PIN D11 [ get_ports {c1_ddr4_dq[9]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ9" - IO_L11N_T1U_N9_GC_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[9]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ9" - IO_L11N_T1U_N9_GC_70 +set_property PACKAGE_PIN E12 [ get_ports {c1_ddr4_dq[10]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ10" - IO_L11P_T1U_N8_GC_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[10]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ10" - IO_L11P_T1U_N8_GC_70 +set_property PACKAGE_PIN D9 [ get_ports {c1_ddr4_dqs_c[2]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C1" - IO_L10N_T1U_N7_QBC_AD4N_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[2]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C1" - IO_L10N_T1U_N7_QBC_AD4N_70 +set_property PACKAGE_PIN D10 [ get_ports {c1_ddr4_dqs_t[2]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T1" - IO_L10P_T1U_N6_QBC_AD4P_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[2]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T1" - IO_L10P_T1U_N6_QBC_AD4P_70 +set_property PACKAGE_PIN E9 [ get_ports {c1_ddr4_dq[13]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ13" - IO_L9N_T1L_N5_AD12N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[13]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ13" - IO_L9N_T1L_N5_AD12N_70 +set_property PACKAGE_PIN F9 [ get_ports {c1_ddr4_dq[14]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ14" - IO_L9P_T1L_N4_AD12P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[14]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ14" - IO_L9P_T1L_N4_AD12P_70 +set_property PACKAGE_PIN F10 [ get_ports {c1_ddr4_dq[12]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ12" - IO_L8N_T1L_N3_AD5N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[12]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ12" - IO_L8N_T1L_N3_AD5N_70 +set_property PACKAGE_PIN G11 [ get_ports {c1_ddr4_dq[15]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ15" - IO_L8P_T1L_N2_AD5P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[15]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ15" - IO_L8P_T1L_N2_AD5P_70 +set_property PACKAGE_PIN G10 [ get_ports {c1_ddr4_dqs_c[3]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C10" - IO_L7N_T1L_N1_QBC_AD13N_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[3]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C10" - IO_L7N_T1L_N1_QBC_AD13N_70 +set_property PACKAGE_PIN H10 [ get_ports {c1_ddr4_dqs_t[3]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T10" - IO_L7P_T1L_N0_QBC_AD13P_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[3]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T10" - IO_L7P_T1L_N0_QBC_AD13P_70 +#set_property PACKAGE_PIN H9 #N/A ;# Bank 70 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_70 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 70 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_70 +set_property PACKAGE_PIN G13 [ get_ports {c1_ddr4_dq[17]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ17" - IO_L6N_T0U_N11_AD6N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[17]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ17" - IO_L6N_T0U_N11_AD6N_70 +set_property PACKAGE_PIN H14 [ get_ports {c1_ddr4_dq[19]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ19" - IO_L6P_T0U_N10_AD6P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[19]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ19" - IO_L6P_T0U_N10_AD6P_70 +set_property PACKAGE_PIN H12 [ get_ports {c1_ddr4_dq[16]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ16" - IO_L5N_T0U_N9_AD14N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[16]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ16" - IO_L5N_T0U_N9_AD14N_70 +set_property PACKAGE_PIN H13 [ get_ports {c1_ddr4_dq[18]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ18" - IO_L5P_T0U_N8_AD14P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[18]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ18" - IO_L5P_T0U_N8_AD14P_70 +set_property PACKAGE_PIN G15 [ get_ports {c1_ddr4_dqs_c[4]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C2" - IO_L4N_T0U_N7_DBC_AD7N_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[4]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C2" - IO_L4N_T0U_N7_DBC_AD7N_70 +set_property PACKAGE_PIN H15 [ get_ports {c1_ddr4_dqs_t[4]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T2" - IO_L4P_T0U_N6_DBC_AD7P_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[4]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T2" - IO_L4P_T0U_N6_DBC_AD7P_70 +set_property PACKAGE_PIN J11 [ get_ports {c1_ddr4_dq[20]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ20" - IO_L3N_T0L_N5_AD15N_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[20]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ20" - IO_L3N_T0L_N5_AD15N_70 +set_property PACKAGE_PIN J12 [ get_ports {c1_ddr4_dq[21]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ21" - IO_L3P_T0L_N4_AD15P_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[21]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ21" - IO_L3P_T0L_N4_AD15P_70 +set_property PACKAGE_PIN J14 [ get_ports {c1_ddr4_dq[23]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ23" - IO_L2N_T0L_N3_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[23]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ23" - IO_L2N_T0L_N3_70 +set_property PACKAGE_PIN J15 [ get_ports {c1_ddr4_dq[22]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ22" - IO_L2P_T0L_N2_70 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[22]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQ22" - IO_L2P_T0L_N2_70 +set_property PACKAGE_PIN K13 [ get_ports {c1_ddr4_dqs_c[5]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C11" - IO_L1N_T0L_N1_DBC_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[5]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_C11" - IO_L1N_T0L_N1_DBC_70 +set_property PACKAGE_PIN K14 [ get_ports {c1_ddr4_dqs_t[5]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T11" - IO_L1P_T0L_N0_DBC_70 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[5]} ] ;# Bank 70 VCCO - VCC1V2 Net "DDR4_C1_DQS_T11" - IO_L1P_T0L_N0_DBC_70 +# +# DDR4 RDIMM Control, Command and Address +# The DIMM interfaces have connectivity to support UDIMM, RDIMM, LRDIMM and 3DS devices. +# The below constraints are configured to support DDR4, Single Rank, RDIMMs with x4 Compnent Connectivity and the unused pins are commented out. +# The System Clock for the MEMORY interface are comemented out and moved to the Clock section of the XDC file +# +set_property PACKAGE_PIN BF1 [ get_ports {c1_ddr4_cke[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CKE1" - IO_L24N_T3U_N11_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_cke[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CKE1" - IO_L24N_T3U_N11_69 +set_property PACKAGE_PIN BE1 [ get_ports {c1_ddr4_cke[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CKE0" - IO_L24P_T3U_N10_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_cke[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CKE0" - IO_L24P_T3U_N10_69 +set_property PACKAGE_PIN BE3 [ get_ports {c1_ddr4_adr[4]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR4" - IO_L23N_T3U_N9_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[4]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR4" - IO_L23N_T3U_N9_69 +set_property PACKAGE_PIN BE4 [ get_ports {c1_ddr4_adr[11]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR11" - IO_L23P_T3U_N8_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[11]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR11" - IO_L23P_T3U_N8_69 +set_property PACKAGE_PIN BE5 [ get_ports {c1_ddr4_adr[6]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR6" - IO_L22N_T3U_N7_DBC_AD0N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[6]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR6" - IO_L22N_T3U_N7_DBC_AD0N_69 +set_property PACKAGE_PIN BE6 [ get_ports {c1_ddr4_adr[5]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR5" - IO_L22P_T3U_N6_DBC_AD0P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[5]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR5" - IO_L22P_T3U_N6_DBC_AD0P_69 +set_property PACKAGE_PIN BF2 [ get_ports {c1_ddr4_bg[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BG1" - IO_L21N_T3L_N5_AD8N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_bg[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BG1" - IO_L21N_T3L_N5_AD8N_69 +set_property PACKAGE_PIN BF3 [ get_ports {c1_ddr4_bg[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BG0" - IO_L21P_T3L_N4_AD8P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_bg[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BG0" - IO_L21P_T3L_N4_AD8P_69 +set_property PACKAGE_PIN BG2 [ get_ports {c1_ddr4_adr[9]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR9" - IO_L20N_T3L_N3_AD1N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[9]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR9" - IO_L20N_T3L_N3_AD1N_69 +set_property PACKAGE_PIN BG3 [ get_ports {c1_ddr4_act_n} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ACT_B" - IO_L20P_T3L_N2_AD1P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_act_n} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ACT_B" - IO_L20P_T3L_N2_AD1P_69 +set_property PACKAGE_PIN BG4 [ get_ports {c1_ddr4_cs_n[3]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B3" - IO_L19N_T3L_N1_DBC_AD9N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_cs_n[3]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B3" - IO_L19N_T3L_N1_DBC_AD9N_69 +set_property PACKAGE_PIN BG5 [ get_ports {c1_ddr4_cs_n[2]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B2" - IO_L19P_T3L_N0_DBC_AD9P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_cs_n[2]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B2" - IO_L19P_T3L_N0_DBC_AD9P_69 +set_property PACKAGE_PIN BF5 [ get_ports {c1_ddr4_adr[3]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR3" - IO_T3U_N12_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[3]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR3" - IO_T3U_N12_69 +set_property PACKAGE_PIN BF6 [ get_ports {c1_ddr4_adr[2]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR2" - IO_T2U_N12_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[2]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR2" - IO_T2U_N12_69 +set_property PACKAGE_PIN BF7 [ get_ports {c1_ddr4_adr[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR0" - IO_L18N_T2U_N11_AD2N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR0" - IO_L18N_T2U_N11_AD2N_69 +set_property PACKAGE_PIN BF8 [ get_ports {c1_ddr4_adr[16]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR16" - IO_L18P_T2U_N10_AD2P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[16]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR16" - IO_L18P_T2U_N10_AD2P_69 +set_property PACKAGE_PIN BG7 [ get_ports {c1_ddr4_adr[7]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR7" - IO_L17N_T2U_N9_AD10N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[7]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR7" - IO_L17N_T2U_N9_AD10N_69 +set_property PACKAGE_PIN BG8 [ get_ports {c1_ddr4_ba[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BA0" - IO_L17P_T2U_N8_AD10P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_ba[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BA0" - IO_L17P_T2U_N8_AD10P_69 +set_property PACKAGE_PIN BJ7 [ get_ports {c1_ddr4_ck_c[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_69 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports {c1_ddr4_ck_c[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_C1" - IO_L16N_T2U_N7_QBC_AD3N_69 +set_property PACKAGE_PIN BH7 [ get_ports {c1_ddr4_ck_t[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_69 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports {c1_ddr4_ck_t[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_T1" - IO_L16P_T2U_N6_QBC_AD3P_69 +set_property PACKAGE_PIN BK8 [ get_ports {c1_ddr4_adr[14]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR14" - IO_L15N_T2L_N5_AD11N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[14]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR14" - IO_L15N_T2L_N5_AD11N_69 +set_property PACKAGE_PIN BJ8 [ get_ports {c1_ddr4_adr[10]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR10" - IO_L15P_T2L_N4_AD11P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[10]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR10" - IO_L15P_T2L_N4_AD11P_69 +set_property PACKAGE_PIN BH4 [ get_ports {c1_ddr4_odt[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ODT1" - IO_L14N_T2L_N3_GC_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_odt[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ODT1" - IO_L14N_T2L_N3_GC_69 +set_property PACKAGE_PIN BH5 [ get_ports {c1_ddr4_cs_n[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B1" - IO_L14P_T2L_N2_GC_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_cs_n[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B1" - IO_L14P_T2L_N2_GC_69 +# Clocks at top of XDC +#set_property PACKAGE_PIN BJ6 [ get_ports {sys_clk1_n} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_N" - IO_L13N_T2L_N1_GC_QBC_69 +#set_property IOSTANDARD LVCMOS18 [ get_ports {sys_clk1_n} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_N" - IO_L13N_T2L_N1_GC_QBC_69 +#set_property PACKAGE_PIN BH6 [ get_ports {sys_clk1_p} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_P" - IO_L13P_T2L_N0_GC_QBC_69 +#set_property IOSTANDARD LVCMOS18 [ get_ports {sys_clk1_p} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_P" - IO_L13P_T2L_N0_GC_QBC_69 +## <<<>>> No external BIAS on AC coupled LVDS clock inputs to 1.2V bank so this constraint is added to recenter LVDS signal on 1.2V IO standard. +#set_property DQS_BIAS TRUE [ get_ports {sys_clk1_p} ] ;# Bank 69 VCCO - VCC1V2 Net "SYSCLK1_P" - IO_L13P_T2L_N0_GC_QBC_69 +set_property PACKAGE_PIN BK4 [ get_ports {c1_ddr4_ba[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BA1" - IO_L12N_T1U_N11_GC_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_ba[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_BA1" - IO_L12N_T1U_N11_GC_69 +set_property PACKAGE_PIN BK5 [ get_ports {c1_ddr4_adr[13]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR13" - IO_L12P_T1U_N10_GC_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[13]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR13" - IO_L12P_T1U_N10_GC_69 +#set_property PACKAGE_PIN BK3 [ get_ports {c1_ddr4_alert_n} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ALERT_B" - IO_L11N_T1U_N9_GC_69 +#set_property IOSTANDARD LVCMOS12 [ get_ports {c1_ddr4_alert_n} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ALERT_B" - IO_L11N_T1U_N9_GC_69 +set_property PACKAGE_PIN BJ4 [ get_ports {c1_ddr4_adr[15]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR15" - IO_L11P_T1U_N8_GC_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[15]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR15" - IO_L11P_T1U_N8_GC_69 +set_property PACKAGE_PIN BJ2 [ get_ports {c1_ddr4_ck_c[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_C0" - IO_L10N_T1U_N7_QBC_AD4N_69 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports {c1_ddr4_ck_c[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_C0" - IO_L10N_T1U_N7_QBC_AD4N_69 +set_property PACKAGE_PIN BJ3 [ get_ports {c1_ddr4_ck_t[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_T0" - IO_L10P_T1U_N6_QBC_AD4P_69 +set_property IOSTANDARD DIFF_SSTL12_DCI [ get_ports {c1_ddr4_ck_t[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CK_T0" - IO_L10P_T1U_N6_QBC_AD4P_69 +set_property PACKAGE_PIN BH1 [ get_ports {c1_ddr4_parity} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_PAR" - IO_L9N_T1L_N5_AD12N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_parity} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_PAR" - IO_L9N_T1L_N5_AD12N_69 +set_property PACKAGE_PIN BH2 [ get_ports {c1_ddr4_odt[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ODT0" - IO_L9P_T1L_N4_AD12P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_odt[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ODT0" - IO_L9P_T1L_N4_AD12P_69 +set_property PACKAGE_PIN BK1 [ get_ports {c1_ddr4_adr[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR1" - IO_L8N_T1L_N3_AD5N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[1]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR1" - IO_L8N_T1L_N3_AD5N_69 +set_property PACKAGE_PIN BJ1 [ get_ports {c1_ddr4_adr[8]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR8" - IO_L8P_T1L_N2_AD5P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[8]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR8" - IO_L8P_T1L_N2_AD5P_69 +set_property PACKAGE_PIN BL2 [ get_ports {c1_ddr4_adr[12]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR12" - IO_L7N_T1L_N1_QBC_AD13N_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[12]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR12" - IO_L7N_T1L_N1_QBC_AD13N_69 +set_property PACKAGE_PIN BL3 [ get_ports {c1_ddr4_cs_n[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B0" - IO_L7P_T1L_N0_QBC_AD13P_69 +set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_cs_n[0]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_CS_B0" - IO_L7P_T1L_N0_QBC_AD13P_69 +#set_property PACKAGE_PIN BK6 [ get_ports {c1_ddr4_adr[17]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR17" - IO_T1U_N12_69 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_adr[17]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_ADR17" - IO_T1U_N12_69 +set_property PACKAGE_PIN BM3 [ get_ports {c1_ddr4_dq[32]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ32" - IO_L6N_T0U_N11_AD6N_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[32]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ32" - IO_L6N_T0U_N11_AD6N_69 +set_property PACKAGE_PIN BM4 [ get_ports {c1_ddr4_dq[33]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ33" - IO_L6P_T0U_N10_AD6P_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[33]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ33" - IO_L6P_T0U_N10_AD6P_69 +set_property PACKAGE_PIN BM5 [ get_ports {c1_ddr4_dq[34]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ34" - IO_L5N_T0U_N9_AD14N_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[34]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ34" - IO_L5N_T0U_N9_AD14N_69 +set_property PACKAGE_PIN BL6 [ get_ports {c1_ddr4_dq[35]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ35" - IO_L5P_T0U_N8_AD14P_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[35]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ35" - IO_L5P_T0U_N8_AD14P_69 +set_property PACKAGE_PIN BM7 [ get_ports {c1_ddr4_dqs_c[8]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_69 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[8]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_C4" - IO_L4N_T0U_N7_DBC_AD7N_69 +set_property PACKAGE_PIN BL7 [ get_ports {c1_ddr4_dqs_t[8]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_69 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[8]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_T4" - IO_L4P_T0U_N6_DBC_AD7P_69 +set_property PACKAGE_PIN BN4 [ get_ports {c1_ddr4_dq[36]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ36" - IO_L3N_T0L_N5_AD15N_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[36]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ36" - IO_L3N_T0L_N5_AD15N_69 +set_property PACKAGE_PIN BN5 [ get_ports {c1_ddr4_dq[37]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ37" - IO_L3P_T0L_N4_AD15P_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[37]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ37" - IO_L3P_T0L_N4_AD15P_69 +set_property PACKAGE_PIN BN6 [ get_ports {c1_ddr4_dq[38]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ38" - IO_L2N_T0L_N3_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[38]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ38" - IO_L2N_T0L_N3_69 +set_property PACKAGE_PIN BN7 [ get_ports {c1_ddr4_dq[39]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ39" - IO_L2P_T0L_N2_69 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[39]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQ39" - IO_L2P_T0L_N2_69 +set_property PACKAGE_PIN BP6 [ get_ports {c1_ddr4_dqs_c[9]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_C13" - IO_L1N_T0L_N1_DBC_69 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[9]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_C13" - IO_L1N_T0L_N1_DBC_69 +set_property PACKAGE_PIN BP7 [ get_ports {c1_ddr4_dqs_t[9]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_T13" - IO_L1P_T0L_N0_DBC_69 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[9]} ] ;# Bank 69 VCCO - VCC1V2 Net "DDR4_C1_DQS_T13" - IO_L1P_T0L_N0_DBC_69 +set_property PACKAGE_PIN BE9 [ get_ports {c1_ddr4_dq[64]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ65" - IO_L24N_T3U_N11_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[64]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ65" - IO_L24N_T3U_N11_68 +set_property PACKAGE_PIN BE10 [ get_ports {c1_ddr4_dq[65]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ67" - IO_L24P_T3U_N10_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[65]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ67" - IO_L24P_T3U_N10_68 +set_property PACKAGE_PIN BF10 [ get_ports {c1_ddr4_dq[66]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ66" - IO_L23N_T3U_N9_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[66]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ66" - IO_L23N_T3U_N9_68 +set_property PACKAGE_PIN BE11 [ get_ports {c1_ddr4_dq[67]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ64" - IO_L23P_T3U_N8_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[67]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ64" - IO_L23P_T3U_N8_68 +set_property PACKAGE_PIN BF11 [ get_ports {c1_ddr4_dqs_c[16]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C8" - IO_L22N_T3U_N7_DBC_AD0N_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[16]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C8" - IO_L22N_T3U_N7_DBC_AD0N_68 +set_property PACKAGE_PIN BF12 [ get_ports {c1_ddr4_dqs_t[16]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T8" - IO_L22P_T3U_N6_DBC_AD0P_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[16]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T8" - IO_L22P_T3U_N6_DBC_AD0P_68 +set_property PACKAGE_PIN BG9 [ get_ports {c1_ddr4_dq[70]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ71" - IO_L21N_T3L_N5_AD8N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[70]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ71" - IO_L21N_T3L_N5_AD8N_68 +set_property PACKAGE_PIN BG10 [ get_ports {c1_ddr4_dq[71]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ69" - IO_L21P_T3L_N4_AD8P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[71]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ69" - IO_L21P_T3L_N4_AD8P_68 +set_property PACKAGE_PIN BG12 [ get_ports {c1_ddr4_dq[69]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ70" - IO_L20N_T3L_N3_AD1N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[69]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ70" - IO_L20N_T3L_N3_AD1N_68 +set_property PACKAGE_PIN BG13 [ get_ports {c1_ddr4_dq[68]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ68" - IO_L20P_T3L_N2_AD1P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[68]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ68" - IO_L20P_T3L_N2_AD1P_68 +set_property PACKAGE_PIN BH9 [ get_ports {c1_ddr4_dqs_c[17]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C17" - IO_L19N_T3L_N1_DBC_AD9N_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[17]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C17" - IO_L19N_T3L_N1_DBC_AD9N_68 +set_property PACKAGE_PIN BH10 [ get_ports {c1_ddr4_dqs_t[17]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T17" - IO_L19P_T3L_N0_DBC_AD9P_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[17]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T17" - IO_L19P_T3L_N0_DBC_AD9P_68 +#set_property PACKAGE_PIN BH11 [ get_ports {c1_ddr4_event_n} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_EVENT_B" - IO_T3U_N12_68 +#set_property IOSTANDARD SSTL12_DCI [ get_ports {c1_ddr4_event_n} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_EVENT_B" - IO_T3U_N12_68 +set_property PACKAGE_PIN BH12 [ get_ports {c1_ddr4_reset_n} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_RESET_N" - IO_T2U_N12_68 +set_property IOSTANDARD LVCMOS12 [ get_ports {c1_ddr4_reset_n} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_RESET_N" - IO_T2U_N12_68 +set_property PACKAGE_PIN BH14 [ get_ports {c1_ddr4_dq[59]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ59" - IO_L18N_T2U_N11_AD2N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[59]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ59" - IO_L18N_T2U_N11_AD2N_68 +set_property PACKAGE_PIN BH15 [ get_ports {c1_ddr4_dq[58]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ58" - IO_L18P_T2U_N10_AD2P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[58]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ58" - IO_L18P_T2U_N10_AD2P_68 +set_property PACKAGE_PIN BJ12 [ get_ports {c1_ddr4_dq[57]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ57" - IO_L17N_T2U_N9_AD10N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[57]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ57" - IO_L17N_T2U_N9_AD10N_68 +set_property PACKAGE_PIN BJ13 [ get_ports {c1_ddr4_dq[56]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ56" - IO_L17P_T2U_N8_AD10P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[56]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ56" - IO_L17P_T2U_N8_AD10P_68 +set_property PACKAGE_PIN BK13 [ get_ports {c1_ddr4_dqs_c[14]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C7" - IO_L16N_T2U_N7_QBC_AD3N_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[14]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C7" - IO_L16N_T2U_N7_QBC_AD3N_68 +set_property PACKAGE_PIN BJ14 [ get_ports {c1_ddr4_dqs_t[14]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T7" - IO_L16P_T2U_N6_QBC_AD3P_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[14]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T7" - IO_L16P_T2U_N6_QBC_AD3P_68 +set_property PACKAGE_PIN BK14 [ get_ports {c1_ddr4_dq[60]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ60" - IO_L15N_T2L_N5_AD11N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[60]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ60" - IO_L15N_T2L_N5_AD11N_68 +set_property PACKAGE_PIN BK15 [ get_ports {c1_ddr4_dq[61]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ61" - IO_L15P_T2L_N4_AD11P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[61]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ61" - IO_L15P_T2L_N4_AD11P_68 +set_property PACKAGE_PIN BL12 [ get_ports {c1_ddr4_dq[62]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ62" - IO_L14N_T2L_N3_GC_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[62]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ62" - IO_L14N_T2L_N3_GC_68 +set_property PACKAGE_PIN BL13 [ get_ports {c1_ddr4_dq[63]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ63" - IO_L14P_T2L_N2_GC_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[63]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ63" - IO_L14P_T2L_N2_GC_68 +set_property PACKAGE_PIN BK11 [ get_ports {c1_ddr4_dqs_c[15]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C16" - IO_L13N_T2L_N1_GC_QBC_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[15]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C16" - IO_L13N_T2L_N1_GC_QBC_68 +set_property PACKAGE_PIN BJ11 [ get_ports {c1_ddr4_dqs_t[15]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T16" - IO_L13P_T2L_N0_GC_QBC_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[15]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T16" - IO_L13P_T2L_N0_GC_QBC_68 +set_property PACKAGE_PIN BK9 [ get_ports {c1_ddr4_dq[41]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ41" - IO_L12N_T1U_N11_GC_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[41]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ41" - IO_L12N_T1U_N11_GC_68 +set_property PACKAGE_PIN BJ9 [ get_ports {c1_ddr4_dq[40]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ40" - IO_L12P_T1U_N10_GC_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[40]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ40" - IO_L12P_T1U_N10_GC_68 +set_property PACKAGE_PIN BL10 [ get_ports {c1_ddr4_dq[43]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ43" - IO_L11N_T1U_N9_GC_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[43]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ43" - IO_L11N_T1U_N9_GC_68 +set_property PACKAGE_PIN BK10 [ get_ports {c1_ddr4_dq[42]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ42" - IO_L11P_T1U_N8_GC_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[42]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ42" - IO_L11P_T1U_N8_GC_68 +set_property PACKAGE_PIN BM8 [ get_ports {c1_ddr4_dqs_c[10]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C5" - IO_L10N_T1U_N7_QBC_AD4N_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[10]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C5" - IO_L10N_T1U_N7_QBC_AD4N_68 +set_property PACKAGE_PIN BL8 [ get_ports {c1_ddr4_dqs_t[10]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T5" - IO_L10P_T1U_N6_QBC_AD4P_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[10]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T5" - IO_L10P_T1U_N6_QBC_AD4P_68 +set_property PACKAGE_PIN BN9 [ get_ports {c1_ddr4_dq[45]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ45" - IO_L9N_T1L_N5_AD12N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[45]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ45" - IO_L9N_T1L_N5_AD12N_68 +set_property PACKAGE_PIN BM9 [ get_ports {c1_ddr4_dq[44]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ44" - IO_L9P_T1L_N4_AD12P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[44]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ44" - IO_L9P_T1L_N4_AD12P_68 +set_property PACKAGE_PIN BN10 [ get_ports {c1_ddr4_dq[46]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ46" - IO_L8N_T1L_N3_AD5N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[46]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ46" - IO_L8N_T1L_N3_AD5N_68 +set_property PACKAGE_PIN BM10 [ get_ports {c1_ddr4_dq[47]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ47" - IO_L8P_T1L_N2_AD5P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[47]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ47" - IO_L8P_T1L_N2_AD5P_68 +set_property PACKAGE_PIN BP8 [ get_ports {c1_ddr4_dqs_c[11]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C14" - IO_L7N_T1L_N1_QBC_AD13N_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[11]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C14" - IO_L7N_T1L_N1_QBC_AD13N_68 +set_property PACKAGE_PIN BP9 [ get_ports {c1_ddr4_dqs_t[11]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T14" - IO_L7P_T1L_N0_QBC_AD13P_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[11]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T14" - IO_L7P_T1L_N0_QBC_AD13P_68 +#set_property PACKAGE_PIN BL11 #N/A ;# Bank 68 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_68 +#set_property IOSTANDARD LVCMOS18 #N/A ;# Bank 68 VCCO - VCC1V2 Net "Not Connected" - IO_T1U_N12_68 +set_property PACKAGE_PIN BM15 [ get_ports {c1_ddr4_dq[48]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ48" - IO_L6N_T0U_N11_AD6N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[48]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ48" - IO_L6N_T0U_N11_AD6N_68 +set_property PACKAGE_PIN BL15 [ get_ports {c1_ddr4_dq[50]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ50" - IO_L6P_T0U_N10_AD6P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[50]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ50" - IO_L6P_T0U_N10_AD6P_68 +set_property PACKAGE_PIN BM13 [ get_ports {c1_ddr4_dq[51]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ51" - IO_L5N_T0U_N9_AD14N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[51]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ51" - IO_L5N_T0U_N9_AD14N_68 +set_property PACKAGE_PIN BM14 [ get_ports {c1_ddr4_dq[49]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ49" - IO_L5P_T0U_N8_AD14P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[49]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ49" - IO_L5P_T0U_N8_AD14P_68 +set_property PACKAGE_PIN BN14 [ get_ports {c1_ddr4_dqs_c[12]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C6" - IO_L4N_T0U_N7_DBC_AD7N_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[12]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C6" - IO_L4N_T0U_N7_DBC_AD7N_68 +set_property PACKAGE_PIN BN15 [ get_ports {c1_ddr4_dqs_t[12]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T6" - IO_L4P_T0U_N6_DBC_AD7P_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[12]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T6" - IO_L4P_T0U_N6_DBC_AD7P_68 +set_property PACKAGE_PIN BN12 [ get_ports {c1_ddr4_dq[52]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ52" - IO_L3N_T0L_N5_AD15N_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[52]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ52" - IO_L3N_T0L_N5_AD15N_68 +set_property PACKAGE_PIN BM12 [ get_ports {c1_ddr4_dq[53]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ53" - IO_L3P_T0L_N4_AD15P_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[53]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ53" - IO_L3P_T0L_N4_AD15P_68 +set_property PACKAGE_PIN BP13 [ get_ports {c1_ddr4_dq[54]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ54" - IO_L2N_T0L_N3_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[54]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ54" - IO_L2N_T0L_N3_68 +set_property PACKAGE_PIN BP14 [ get_ports {c1_ddr4_dq[55]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ55" - IO_L2P_T0L_N2_68 +set_property IOSTANDARD POD12_DCI [ get_ports {c1_ddr4_dq[55]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQ55" - IO_L2P_T0L_N2_68 +set_property PACKAGE_PIN BP11 [ get_ports {c1_ddr4_dqs_c[13]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C15" - IO_L1N_T0L_N1_DBC_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_c[13]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_C15" - IO_L1N_T0L_N1_DBC_68 +set_property PACKAGE_PIN BP12 [ get_ports {c1_ddr4_dqs_t[13]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T15" - IO_L1P_T0L_N0_DBC_68 +set_property IOSTANDARD DIFF_POD12_DCI [ get_ports {c1_ddr4_dqs_t[13]} ] ;# Bank 68 VCCO - VCC1V2 Net "DDR4_C1_DQS_T15" - IO_L1P_T0L_N0_DBC_68 +# +# MGTY Connections +# +# These are commented out because typical IPs have the pin location embedded constraints in the IP +# +# QSFP28 MGTY Interface +# +# #set_property PACKAGE_PIN T43 [get_ports "MGT_SI570_CLOCK0_C_N"] ;# Bank 134 - MGTREFCLK0N_134 +# #set_property PACKAGE_PIN T42 [get_ports "MGT_SI570_CLOCK0_C_P"] ;# Bank 134 - MGTREFCLK0P_134 +# #set_property PACKAGE_PIN R41 [get_ports "QSFP0_CLOCK_N"] ;# Bank 134 - MGTREFCLK1N_134 +# #set_property PACKAGE_PIN R40 [get_ports "QSFP0_CLOCK_P"] ;# Bank 134 - MGTREFCLK1P_134 +# set_property PACKAGE_PIN L54 [get_ports "QSFP0_RX1_N"] ;# Bank 134 - MGTYRXN0_134 +# set_property PACKAGE_PIN K52 [get_ports "QSFP0_RX2_N"] ;# Bank 134 - MGTYRXN1_134 +# set_property PACKAGE_PIN J54 [get_ports "QSFP0_RX3_N"] ;# Bank 134 - MGTYRXN2_134 +# set_property PACKAGE_PIN H52 [get_ports "QSFP0_RX4_N"] ;# Bank 134 - MGTYRXN3_134 +# set_property PACKAGE_PIN L53 [get_ports "QSFP0_RX1_P"] ;# Bank 134 - MGTYRXP0_134 +# set_property PACKAGE_PIN K51 [get_ports "QSFP0_RX2_P"] ;# Bank 134 - MGTYRXP1_134 +# set_property PACKAGE_PIN J53 [get_ports "QSFP0_RX3_P"] ;# Bank 134 - MGTYRXP2_134 +# set_property PACKAGE_PIN H51 [get_ports "QSFP0_RX4_P"] ;# Bank 134 - MGTYRXP3_134 +# set_property PACKAGE_PIN L49 [get_ports "QSFP0_TX1_N"] ;# Bank 134 - MGTYTXN0_134 +# set_property PACKAGE_PIN L45 [get_ports "QSFP0_TX2_N"] ;# Bank 134 - MGTYTXN1_134 +# set_property PACKAGE_PIN K47 [get_ports "QSFP0_TX3_N"] ;# Bank 134 - MGTYTXN2_134 +# set_property PACKAGE_PIN J49 [get_ports "QSFP0_TX4_N"] ;# Bank 134 - MGTYTXN3_134 +# set_property PACKAGE_PIN L48 [get_ports "QSFP0_TX1_P"] ;# Bank 134 - MGTYTXP0_134 +# set_property PACKAGE_PIN L44 [get_ports "QSFP0_TX2_P"] ;# Bank 134 - MGTYTXP1_134 +# set_property PACKAGE_PIN K46 [get_ports "QSFP0_TX3_P"] ;# Bank 134 - MGTYTXP2_134 +# set_property PACKAGE_PIN J48 [get_ports "QSFP0_TX4_P"] ;# Bank 134 - MGTYTXP3_134 +# #set_property PACKAGE_PIN P43 [get_ports "MGT_SI570_CLOCK1_C_N"] ;# Bank 135 - MGTREFCLK0N_135 +# #set_property PACKAGE_PIN P42 [get_ports "MGT_SI570_CLOCK1_C_P"] ;# Bank 135 - MGTREFCLK0P_135 +# #set_property PACKAGE_PIN M43 [get_ports "QSFP1_CLOCK_N"] ;# Bank 135 - MGTREFCLK1N_135 +# #set_property PACKAGE_PIN M42 [get_ports "QSFP1_CLOCK_P"] ;# Bank 135 - MGTREFCLK1P_135 +# set_property PACKAGE_PIN G54 [get_ports "QSFP1_RX1_N"] ;# Bank 135 - MGTYRXN0_135 +# set_property PACKAGE_PIN F52 [get_ports "QSFP1_RX2_N"] ;# Bank 135 - MGTYRXN1_135 +# set_property PACKAGE_PIN E54 [get_ports "QSFP1_RX3_N"] ;# Bank 135 - MGTYRXN2_135 +# set_property PACKAGE_PIN D52 [get_ports "QSFP1_RX4_N"] ;# Bank 135 - MGTYRXN3_135 +# set_property PACKAGE_PIN G53 [get_ports "QSFP1_RX1_P"] ;# Bank 135 - MGTYRXP0_135 +# set_property PACKAGE_PIN F51 [get_ports "QSFP1_RX2_P"] ;# Bank 135 - MGTYRXP1_135 +# set_property PACKAGE_PIN E53 [get_ports "QSFP1_RX3_P"] ;# Bank 135 - MGTYRXP2_135 +# set_property PACKAGE_PIN D51 [get_ports "QSFP1_RX4_P"] ;# Bank 135 - MGTYRXP3_135 +# set_property PACKAGE_PIN G49 [get_ports "QSFP1_TX1_N"] ;# Bank 135 - MGTYTXN0_135 +# set_property PACKAGE_PIN E49 [get_ports "QSFP1_TX2_N"] ;# Bank 135 - MGTYTXN1_135 +# set_property PACKAGE_PIN C49 [get_ports "QSFP1_TX3_N"] ;# Bank 135 - MGTYTXN2_135 +# set_property PACKAGE_PIN A50 [get_ports "QSFP1_TX4_N"] ;# Bank 135 - MGTYTXN3_135 +# set_property PACKAGE_PIN G48 [get_ports "QSFP1_TX1_P"] ;# Bank 135 - MGTYTXP0_135 +# set_property PACKAGE_PIN E48 [get_ports "QSFP1_TX2_P"] ;# Bank 135 - MGTYTXP1_135 +# set_property PACKAGE_PIN C48 [get_ports "QSFP1_TX3_P"] ;# Bank 135 - MGTYTXP2_135 +# set_property PACKAGE_PIN A49 [get_ports "QSFP1_TX4_P"] ;# Bank 135 - MGTYTXP3_135 +# +# PCIe MGTY Interface +# +# set_property PACKAGE_PIN BC1 [get_ports {pci_exp_rxn[15]} ] ;# Bank 224 - MGTYRXN0_224 +# set_property PACKAGE_PIN BB3 [get_ports {pci_exp_rxn[14]} ] ;# Bank 224 - MGTYRXN1_224 +# set_property PACKAGE_PIN BA1 [get_ports {pci_exp_rxn[13]} ] ;# Bank 224 - MGTYRXN2_224 +# set_property PACKAGE_PIN BA5 [get_ports {pci_exp_rxn[12]} ] ;# Bank 224 - MGTYRXN3_224 +# set_property PACKAGE_PIN BC2 [get_ports {pci_exp_rxp[15]} ] ;# Bank 224 - MGTYRXP0_224 +# set_property PACKAGE_PIN BB4 [get_ports {pci_exp_rxp[14]} ] ;# Bank 224 - MGTYRXP1_224 +# set_property PACKAGE_PIN BA2 [get_ports {pci_exp_rxp[13]} ] ;# Bank 224 - MGTYRXP2_224 +# set_property PACKAGE_PIN BA6 [get_ports {pci_exp_rxp[12]} ] ;# Bank 224 - MGTYRXP3_224 +# set_property PACKAGE_PIN BC6 [get_ports {pci_exp_txn[15]} ] ;# Bank 224 - MGTYTXN0_224 +# set_property PACKAGE_PIN BC10 [get_ports {pci_exp_txn[14]} ] ;# Bank 224 - MGTYTXN1_224 +# set_property PACKAGE_PIN BB8 [get_ports {pci_exp_txn[13]} ] ;# Bank 224 - MGTYTXN2_224 +# set_property PACKAGE_PIN BA10 [get_ports {pci_exp_txn[12]} ] ;# Bank 224 - MGTYTXN3_224 +# set_property PACKAGE_PIN BC7 [get_ports {pci_exp_txp[15]} ] ;# Bank 224 - MGTYTXP0_224 +# set_property PACKAGE_PIN BC11 [get_ports {pci_exp_txp[14]} ] ;# Bank 224 - MGTYTXP1_224 +# set_property PACKAGE_PIN BB9 [get_ports {pci_exp_txp[13]} ] ;# Bank 224 - MGTYTXP2_224 +# set_property PACKAGE_PIN BA11 [get_ports {pci_exp_txp[12]} ] ;# Bank 224 - MGTYTXP3_224 +# #set_property PACKAGE_PIN AR14 [get_ports "pcie_clk0_p" ] ;# Bank 225 - MGTREFCLK0N_225 +# #set_property PACKAGE_PIN AR15 [get_ports "pcie_clk0_p" ] ;# Bank 225 - MGTREFCLK0P_225 +# #set_property PACKAGE_PIN AP12 [get_ports "SYSCLK5_N"] ;# Bank 225 - MGTREFCLK1N_225 +# #set_property PACKAGE_PIN AP13 [get_ports "SYSCLK5_P"] ;# Bank 225 - MGTREFCLK1P_225 +# set_property PACKAGE_PIN AY3 [get_ports {pci_exp_rxn[11]} ] ;# Bank 225 - MGTYRXN0_225 +# set_property PACKAGE_PIN AW1 [get_ports {pci_exp_rxn[10]} ] ;# Bank 225 - MGTYRXN1_225 +# set_property PACKAGE_PIN AW5 [get_ports {pci_exp_rxn[9]} ] ;# Bank 225 - MGTYRXN2_225 +# set_property PACKAGE_PIN AV3 [get_ports {pci_exp_rxn[8]} ] ;# Bank 225 - MGTYRXN3_225 +# set_property PACKAGE_PIN AY4 [get_ports {pci_exp_rxp[11]} ] ;# Bank 225 - MGTYRXP0_225 +# set_property PACKAGE_PIN AW2 [get_ports {pci_exp_rxp[10]} ] ;# Bank 225 - MGTYRXP1_225 +# set_property PACKAGE_PIN AW6 [get_ports {pci_exp_rxp[9]} ] ;# Bank 225 - MGTYRXP2_225 +# set_property PACKAGE_PIN AV4 [get_ports {pci_exp_rxp[8]} ] ;# Bank 225 - MGTYRXP3_225 +# set_property PACKAGE_PIN AY8 [get_ports {pci_exp_txn[11]} ] ;# Bank 225 - MGTYTXN0_225 +# set_property PACKAGE_PIN AW10 [get_ports {pci_exp_txn[10]} ] ;# Bank 225 - MGTYTXN1_225 +# set_property PACKAGE_PIN AV8 [get_ports {pci_exp_txn[9]} ] ;# Bank 225 - MGTYTXN2_225 +# set_property PACKAGE_PIN AU6 [get_ports {pci_exp_txn[8]} ] ;# Bank 225 - MGTYTXN3_225 +# set_property PACKAGE_PIN AY9 [get_ports {pci_exp_txp[11]} ] ;# Bank 225 - MGTYTXP0_225 +# set_property PACKAGE_PIN AW11 [get_ports {pci_exp_txp[10]} ] ;# Bank 225 - MGTYTXP1_225 +# set_property PACKAGE_PIN AV9 [get_ports {pci_exp_txp[9]} ] ;# Bank 225 - MGTYTXP2_225 +# set_property PACKAGE_PIN AU7 [get_ports {pci_exp_txp[8]} ] ;# Bank 225 - MGTYTXP3_225 +set_property PACKAGE_PIN AU1 [get_ports pci_exp_rxn_i[7] ] ;# Bank 226 - MGTYRXN0_226 +set_property PACKAGE_PIN AT3 [get_ports pci_exp_rxn_i[6] ] ;# Bank 226 - MGTYRXN1_226 +set_property PACKAGE_PIN AR1 [get_ports pci_exp_rxn_i[5] ] ;# Bank 226 - MGTYRXN2_226 +set_property PACKAGE_PIN AP3 [get_ports pci_exp_rxn_i[4] ] ;# Bank 226 - MGTYRXN3_226 +set_property PACKAGE_PIN AU2 [get_ports pci_exp_rxp_i[7] ] ;# Bank 226 - MGTYRXP0_226 +set_property PACKAGE_PIN AT4 [get_ports pci_exp_rxp_i[6] ] ;# Bank 226 - MGTYRXP1_226 +set_property PACKAGE_PIN AR2 [get_ports pci_exp_rxp_i[5] ] ;# Bank 226 - MGTYRXP2_226 +set_property PACKAGE_PIN AP4 [get_ports pci_exp_rxp_i[4] ] ;# Bank 226 - MGTYRXP3_226 +set_property PACKAGE_PIN AU10 [get_ports pci_exp_txn_o[7] ] ;# Bank 226 - MGTYTXN0_226 +set_property PACKAGE_PIN AT8 [get_ports pci_exp_txn_o[6] ] ;# Bank 226 - MGTYTXN1_226 +set_property PACKAGE_PIN AR6 [get_ports pci_exp_txn_o[5] ] ;# Bank 226 - MGTYTXN2_226 +set_property PACKAGE_PIN AR10 [get_ports pci_exp_txn_o[4] ] ;# Bank 226 - MGTYTXN3_226 +set_property PACKAGE_PIN AU11 [get_ports pci_exp_txp_o[7] ] ;# Bank 226 - MGTYTXP0_226 +set_property PACKAGE_PIN AT9 [get_ports pci_exp_txp_o[6] ] ;# Bank 226 - MGTYTXP1_226 +set_property PACKAGE_PIN AR7 [get_ports pci_exp_txp_o[5] ] ;# Bank 226 - MGTYTXP2_226 +set_property PACKAGE_PIN AR11 [get_ports pci_exp_txp_o[4] ] ;# Bank 226 - MGTYTXP3_226 +#set_property PACKAGE_PIN AL14 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0N_227 +#set_property PACKAGE_PIN AL15 [get_ports {pcie_clk0_n} ] ;# Bank 227 - MGTREFCLK0P_227 +#set_property PACKAGE_PIN AK12 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1N_227 +#set_property PACKAGE_PIN AK13 [get_ports {sys_clk2_n} ] ;# Bank 227 - MGTREFCLK1P_227 +set_property PACKAGE_PIN AN1 [get_ports pci_exp_rxn_i[3] ] ;# Bank 227 - MGTYRXN0_227 +set_property PACKAGE_PIN AN5 [get_ports pci_exp_rxn_i[2] ] ;# Bank 227 - MGTYRXN1_227 +set_property PACKAGE_PIN AM3 [get_ports pci_exp_rxn_i[1] ] ;# Bank 227 - MGTYRXN2_227 +set_property PACKAGE_PIN AL1 [get_ports pci_exp_rxn_i[0] ] ;# Bank 227 - MGTYRXN3_227 +set_property PACKAGE_PIN AN2 [get_ports pci_exp_rxp_i[3] ] ;# Bank 227 - MGTYRXP0_227 +set_property PACKAGE_PIN AN6 [get_ports pci_exp_rxp_i[2] ] ;# Bank 227 - MGTYRXP1_227 +set_property PACKAGE_PIN AM4 [get_ports pci_exp_rxp_i[1] ] ;# Bank 227 - MGTYRXP2_227 +set_property PACKAGE_PIN AL2 [get_ports pci_exp_rxp_i[0] ] ;# Bank 227 - MGTYRXP3_227 +set_property PACKAGE_PIN AP8 [get_ports pci_exp_txn_o[3] ] ;# Bank 227 - MGTYTXN0_227 +set_property PACKAGE_PIN AN10 [get_ports pci_exp_txn_o[2] ] ;# Bank 227 - MGTYTXN1_227 +set_property PACKAGE_PIN AM8 [get_ports pci_exp_txn_o[1] ] ;# Bank 227 - MGTYTXN2_227 +set_property PACKAGE_PIN AL10 [get_ports pci_exp_txn_o[0] ] ;# Bank 227 - MGTYTXN3_227 +set_property PACKAGE_PIN AP9 [get_ports pci_exp_txp_o[3] ] ;# Bank 227 - MGTYTXP0_227 +set_property PACKAGE_PIN AN11 [get_ports pci_exp_txp_o[2] ] ;# Bank 227 - MGTYTXP1_227 +set_property PACKAGE_PIN AM9 [get_ports pci_exp_txp_o[1] ] ;# Bank 227 - MGTYTXP2_227 +set_property PACKAGE_PIN AL11 [get_ports pci_exp_txp_o[0] ] ;# Bank 227 - MGTYTXP3_227 +# +# UNCONNECTED or Grounded Pins +# +#set_property PACKAGE_PIN A29 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L23P_T3U_N8_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L23P_T3U_N8_75 +#set_property PACKAGE_PIN A31 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_75 +#set_property PACKAGE_PIN B30 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_75 +#set_property PACKAGE_PIN A33 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_75 +#set_property PACKAGE_PIN B32 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_75 +#set_property PACKAGE_PIN C29 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_75 +#set_property PACKAGE_PIN C28 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_75 +#set_property PACKAGE_PIN D30 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_75 +#set_property PACKAGE_PIN E33 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_75 +#set_property PACKAGE_PIN F33 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_75 +#set_property PACKAGE_PIN E29 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_75 +#set_property PACKAGE_PIN F29 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_75 +#set_property PACKAGE_PIN E32 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_75 +#set_property PACKAGE_PIN E31 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L13P_T2L_N0_GC_QBC_75 +#set_property PACKAGE_PIN F28 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_75 +#set_property PACKAGE_PIN G28 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_75 +#set_property PACKAGE_PIN H28 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_T1U_N12_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_T1U_N12_75 +#set_property PACKAGE_PIN H29 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_75 +#set_property PACKAGE_PIN J30 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_75 +#set_property PACKAGE_PIN L31 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_75 +#set_property PACKAGE_PIN J32 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_75 +#set_property PACKAGE_PIN K32 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_75 +#set_property PACKAGE_PIN K31 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_75 +#set_property PACKAGE_PIN L29 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L2P_T0L_N2_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L2P_T0L_N2_75 +#set_property PACKAGE_PIN K33 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_75 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 75 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_75 +#set_property PACKAGE_PIN BF21 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L24N_T3U_N11_67 +#set_property PACKAGE_PIN BF22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L24P_T3U_N10_67 +#set_property PACKAGE_PIN BH22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L23N_T3U_N9_67 +#set_property PACKAGE_PIN BG22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L23P_T3U_N8_67 +#set_property PACKAGE_PIN BJ21 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_67 +#set_property PACKAGE_PIN BH21 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_67 +#set_property PACKAGE_PIN BK21 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_67 +#set_property PACKAGE_PIN BJ22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L21P_T3L_N4_AD8P_67 +#set_property PACKAGE_PIN BK23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L20N_T3L_N3_AD1N_67 +#set_property PACKAGE_PIN BK24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L20P_T3L_N2_AD1P_67 +#set_property PACKAGE_PIN BL22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L19N_T3L_N1_DBC_AD9N_67 +#set_property PACKAGE_PIN BL23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_67 +#set_property PACKAGE_PIN BG23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T3U_N12_67 +#set_property PACKAGE_PIN BF23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T2U_N12_67 +#set_property PACKAGE_PIN BH24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_67 +#set_property PACKAGE_PIN BG24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_67 +#set_property PACKAGE_PIN BG25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_67 +#set_property PACKAGE_PIN BF25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_67 +#set_property PACKAGE_PIN BF26 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_67 +#set_property PACKAGE_PIN BF27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_67 +#set_property PACKAGE_PIN BG27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_67 +#set_property PACKAGE_PIN BG28 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_67 +#set_property PACKAGE_PIN BJ23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_67 +#set_property PACKAGE_PIN BJ24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_67 +#set_property PACKAGE_PIN BH25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L13N_T2L_N1_GC_QBC_67 +#set_property PACKAGE_PIN BJ27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L12N_T1U_N11_GC_67 +#set_property PACKAGE_PIN BH27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L12P_T1U_N10_GC_67 +#set_property PACKAGE_PIN BK25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L11N_T1U_N9_GC_67 +#set_property PACKAGE_PIN BJ26 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L11P_T1U_N8_GC_67 +#set_property PACKAGE_PIN BL25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_67 +#set_property PACKAGE_PIN BK26 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_67 +#set_property PACKAGE_PIN BK28 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_67 +#set_property PACKAGE_PIN BJ28 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_67 +#set_property PACKAGE_PIN BL26 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_67 +#set_property PACKAGE_PIN BL27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_67 +#set_property PACKAGE_PIN BM27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_67 +#set_property PACKAGE_PIN BL28 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_67 +#set_property PACKAGE_PIN BN27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T1U_N12_67 +#set_property PACKAGE_PIN BP27 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_T0U_N12_VRP_67 +#set_property PACKAGE_PIN BN22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_67 +#set_property PACKAGE_PIN BM22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_67 +#set_property PACKAGE_PIN BM23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_67 +#set_property PACKAGE_PIN BM24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_67 +#set_property PACKAGE_PIN BN25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_67 +#set_property PACKAGE_PIN BM25 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_67 +#set_property PACKAGE_PIN BP24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_67 +#set_property PACKAGE_PIN BN24 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_67 +#set_property PACKAGE_PIN BP26 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L2N_T0L_N3_67 +#set_property PACKAGE_PIN BN26 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L2P_T0L_N2_67 +#set_property PACKAGE_PIN BP22 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_67 +#set_property PACKAGE_PIN BP23 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 67 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_67 +#set_property PACKAGE_PIN A16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L24N_T3U_N11_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L24N_T3U_N11_71 +#set_property PACKAGE_PIN B16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L24P_T3U_N10_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L24P_T3U_N10_71 +#set_property PACKAGE_PIN A18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L23N_T3U_N9_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L23N_T3U_N9_71 +#set_property PACKAGE_PIN A19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L23P_T3U_N8_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L23P_T3U_N8_71 +#set_property PACKAGE_PIN A20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_71 +#set_property PACKAGE_PIN A21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_71 +#set_property PACKAGE_PIN B17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_71 +#set_property PACKAGE_PIN B18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_71 +#set_property PACKAGE_PIN B20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_71 +#set_property PACKAGE_PIN B21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_71 +#set_property PACKAGE_PIN C17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_71 +#set_property PACKAGE_PIN C18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_71 +#set_property PACKAGE_PIN C19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T3U_N12_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T3U_N12_71 +#set_property PACKAGE_PIN C20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T2U_N12_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T2U_N12_71 +#set_property PACKAGE_PIN D19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_71 +#set_property PACKAGE_PIN D20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_71 +#set_property PACKAGE_PIN D16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_71 +#set_property PACKAGE_PIN D17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_71 +#set_property PACKAGE_PIN D21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_71 +#set_property PACKAGE_PIN E21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_71 +#set_property PACKAGE_PIN E16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_71 +#set_property PACKAGE_PIN F16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_71 +#set_property PACKAGE_PIN E18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L14N_T2L_N3_GC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L14N_T2L_N3_GC_71 +#set_property PACKAGE_PIN E19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L14P_T2L_N2_GC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L14P_T2L_N2_GC_71 +#set_property PACKAGE_PIN E17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_71 +#set_property PACKAGE_PIN F18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_71 +#set_property PACKAGE_PIN F19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L12N_T1U_N11_GC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L12N_T1U_N11_GC_71 +#set_property PACKAGE_PIN F20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L12P_T1U_N10_GC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L12P_T1U_N10_GC_71 +#set_property PACKAGE_PIN G17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L11N_T1U_N9_GC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L11N_T1U_N9_GC_71 +#set_property PACKAGE_PIN G18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L11P_T1U_N8_GC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L11P_T1U_N8_GC_71 +#set_property PACKAGE_PIN F21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_71 +#set_property PACKAGE_PIN G21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_71 +#set_property PACKAGE_PIN H18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_71 +#set_property PACKAGE_PIN H19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_71 +#set_property PACKAGE_PIN G20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_71 +#set_property PACKAGE_PIN H20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_71 +#set_property PACKAGE_PIN G16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_71 +#set_property PACKAGE_PIN H17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_71 +#set_property PACKAGE_PIN J16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T1U_N12_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T1U_N12_71 +#set_property PACKAGE_PIN J17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T0U_N12_VRP_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_T0U_N12_VRP_71 +#set_property PACKAGE_PIN J19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_71 +#set_property PACKAGE_PIN J20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_71 +#set_property PACKAGE_PIN J21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_71 +#set_property PACKAGE_PIN K21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_71 +#set_property PACKAGE_PIN K18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_71 +#set_property PACKAGE_PIN K19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_71 +#set_property PACKAGE_PIN L20 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_71 +#set_property PACKAGE_PIN L21 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_71 +#set_property PACKAGE_PIN L18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L2N_T0L_N3_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L2N_T0L_N3_71 +#set_property PACKAGE_PIN L19 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L2P_T0L_N2_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L2P_T0L_N2_71 +#set_property PACKAGE_PIN K16 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L1N_T0L_N1_DBC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L1N_T0L_N1_DBC_71 +#set_property PACKAGE_PIN K17 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L1P_T0L_N0_DBC_71 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 71 VCCO - Grounded - IO_L1P_T0L_N0_DBC_71 +#set_property PACKAGE_PIN A35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L24N_T3U_N11_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L24N_T3U_N11_74 +#set_property PACKAGE_PIN A34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L24P_T3U_N10_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L24P_T3U_N10_74 +#set_property PACKAGE_PIN A36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L23N_T3U_N9_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L23N_T3U_N9_74 +#set_property PACKAGE_PIN B35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L23P_T3U_N8_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L23P_T3U_N8_74 +#set_property PACKAGE_PIN A38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_74 +#set_property PACKAGE_PIN B37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_74 +#set_property PACKAGE_PIN B36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_74 +#set_property PACKAGE_PIN C35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_74 +#set_property PACKAGE_PIN B38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_74 +#set_property PACKAGE_PIN C37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_74 +#set_property PACKAGE_PIN C34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_74 +#set_property PACKAGE_PIN D34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_74 +#set_property PACKAGE_PIN C38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T3U_N12_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T3U_N12_74 +#set_property PACKAGE_PIN C39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T2U_N12_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T2U_N12_74 +#set_property PACKAGE_PIN D37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_74 +#set_property PACKAGE_PIN E36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_74 +#set_property PACKAGE_PIN E34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_74 +#set_property PACKAGE_PIN F34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_74 +#set_property PACKAGE_PIN D39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_74 +#set_property PACKAGE_PIN E39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_74 +#set_property PACKAGE_PIN D36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_74 +#set_property PACKAGE_PIN D35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_74 +#set_property PACKAGE_PIN E38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L14N_T2L_N3_GC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L14N_T2L_N3_GC_74 +#set_property PACKAGE_PIN E37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L14P_T2L_N2_GC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L14P_T2L_N2_GC_74 +#set_property PACKAGE_PIN F36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_74 +#set_property PACKAGE_PIN F35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_74 +#set_property PACKAGE_PIN F38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L12N_T1U_N11_GC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L12N_T1U_N11_GC_74 +#set_property PACKAGE_PIN G37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L12P_T1U_N10_GC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L12P_T1U_N10_GC_74 +#set_property PACKAGE_PIN G36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L11N_T1U_N9_GC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L11N_T1U_N9_GC_74 +#set_property PACKAGE_PIN G35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L11P_T1U_N8_GC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L11P_T1U_N8_GC_74 +#set_property PACKAGE_PIN F39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_74 +#set_property PACKAGE_PIN G38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_74 +#set_property PACKAGE_PIN H35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_74 +#set_property PACKAGE_PIN H34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_74 +#set_property PACKAGE_PIN H38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_74 +#set_property PACKAGE_PIN H37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_74 +#set_property PACKAGE_PIN H39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_74 +#set_property PACKAGE_PIN J39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_74 +#set_property PACKAGE_PIN J34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T1U_N12_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T1U_N12_74 +#set_property PACKAGE_PIN J35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T0U_N12_VRP_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_T0U_N12_VRP_74 +#set_property PACKAGE_PIN J37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_74 +#set_property PACKAGE_PIN K37 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_74 +#set_property PACKAGE_PIN K34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_74 +#set_property PACKAGE_PIN L34 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_74 +#set_property PACKAGE_PIN K38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_74 +#set_property PACKAGE_PIN L38 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_74 +#set_property PACKAGE_PIN J36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_74 +#set_property PACKAGE_PIN K36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_74 +#set_property PACKAGE_PIN K39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L2N_T0L_N3_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L2N_T0L_N3_74 +#set_property PACKAGE_PIN L39 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L2P_T0L_N2_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L2P_T0L_N2_74 +#set_property PACKAGE_PIN L36 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L1N_T0L_N1_DBC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L1N_T0L_N1_DBC_74 +#set_property PACKAGE_PIN L35 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L1P_T0L_N0_DBC_74 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 74 VCCO - Grounded - IO_L1P_T0L_N0_DBC_74 +#set_property PACKAGE_PIN A40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L24N_T3U_N11_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L24N_T3U_N11_73 +#set_property PACKAGE_PIN A39 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L24P_T3U_N10_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L24P_T3U_N10_73 +#set_property PACKAGE_PIN B42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L23N_T3U_N9_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L23N_T3U_N9_73 +#set_property PACKAGE_PIN B41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L23P_T3U_N8_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L23P_T3U_N8_73 +#set_property PACKAGE_PIN A41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_73 +#set_property PACKAGE_PIN B40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_73 +#set_property PACKAGE_PIN D41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_73 +#set_property PACKAGE_PIN E41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_73 +#set_property PACKAGE_PIN C40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_73 +#set_property PACKAGE_PIN D40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_73 +#set_property PACKAGE_PIN F41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_73 +#set_property PACKAGE_PIN F40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_73 +#set_property PACKAGE_PIN C42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T3U_N12_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T3U_N12_73 +#set_property PACKAGE_PIN B43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T2U_N12_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T2U_N12_73 +#set_property PACKAGE_PIN A44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_73 +#set_property PACKAGE_PIN A43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_73 +#set_property PACKAGE_PIN B45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_73 +#set_property PACKAGE_PIN C44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_73 +#set_property PACKAGE_PIN A46 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_73 +#set_property PACKAGE_PIN A45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_73 +#set_property PACKAGE_PIN B46 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_73 +#set_property PACKAGE_PIN C45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_73 +#set_property PACKAGE_PIN C43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L14N_T2L_N3_GC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L14N_T2L_N3_GC_73 +#set_property PACKAGE_PIN D42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L14P_T2L_N2_GC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L14P_T2L_N2_GC_73 +#set_property PACKAGE_PIN E43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_73 +#set_property PACKAGE_PIN E42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_73 +#set_property PACKAGE_PIN D45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L12N_T1U_N11_GC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L12N_T1U_N11_GC_73 +#set_property PACKAGE_PIN D44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L12P_T1U_N10_GC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L12P_T1U_N10_GC_73 +#set_property PACKAGE_PIN E44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L11N_T1U_N9_GC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L11N_T1U_N9_GC_73 +#set_property PACKAGE_PIN F44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L11P_T1U_N8_GC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L11P_T1U_N8_GC_73 +#set_property PACKAGE_PIN D46 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_73 +#set_property PACKAGE_PIN E46 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_73 +#set_property PACKAGE_PIN G45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_73 +#set_property PACKAGE_PIN H45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_73 +#set_property PACKAGE_PIN F46 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_73 +#set_property PACKAGE_PIN F45 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_73 +#set_property PACKAGE_PIN H44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_73 +#set_property PACKAGE_PIN J44 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_73 +#set_property PACKAGE_PIN G46 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T1U_N12_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T1U_N12_73 +#set_property PACKAGE_PIN F43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T0U_N12_VRP_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_T0U_N12_VRP_73 +#set_property PACKAGE_PIN G43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_73 +#set_property PACKAGE_PIN H43 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_73 +#set_property PACKAGE_PIN G42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_73 +#set_property PACKAGE_PIN G41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_73 +#set_property PACKAGE_PIN G40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_73 +#set_property PACKAGE_PIN H40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_73 +#set_property PACKAGE_PIN J41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_73 +#set_property PACKAGE_PIN J40 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_73 +#set_property PACKAGE_PIN H42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L2N_T0L_N3_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L2N_T0L_N3_73 +#set_property PACKAGE_PIN J42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L2P_T0L_N2_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L2P_T0L_N2_73 +#set_property PACKAGE_PIN K42 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L1N_T0L_N1_DBC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L1N_T0L_N1_DBC_73 +#set_property PACKAGE_PIN K41 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L1P_T0L_N0_DBC_73 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 73 VCCO - Grounded - IO_L1P_T0L_N0_DBC_73 +#set_property PACKAGE_PIN A24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L24N_T3U_N11_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L24N_T3U_N11_72 +#set_property PACKAGE_PIN A25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L24P_T3U_N10_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L24P_T3U_N10_72 +#set_property PACKAGE_PIN A26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L23N_T3U_N9_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L23N_T3U_N9_72 +#set_property PACKAGE_PIN B27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L23P_T3U_N8_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L23P_T3U_N8_72 +#set_property PACKAGE_PIN A23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L22N_T3U_N7_DBC_AD0N_72 +#set_property PACKAGE_PIN B23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L22P_T3U_N6_DBC_AD0P_72 +#set_property PACKAGE_PIN B25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L21N_T3L_N5_AD8N_72 +#set_property PACKAGE_PIN B26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L21P_T3L_N4_AD8P_72 +#set_property PACKAGE_PIN C24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L20N_T3L_N3_AD1N_72 +#set_property PACKAGE_PIN C25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L20P_T3L_N2_AD1P_72 +#set_property PACKAGE_PIN B22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L19N_T3L_N1_DBC_AD9N_72 +#set_property PACKAGE_PIN C23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L19P_T3L_N0_DBC_AD9P_72 +#set_property PACKAGE_PIN C22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T3U_N12_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T3U_N12_72 +#set_property PACKAGE_PIN C27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T2U_N12_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T2U_N12_72 +#set_property PACKAGE_PIN D27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L18N_T2U_N11_AD2N_72 +#set_property PACKAGE_PIN E27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L18P_T2U_N10_AD2P_72 +#set_property PACKAGE_PIN D26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L17N_T2U_N9_AD10N_72 +#set_property PACKAGE_PIN E26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L17P_T2U_N8_AD10P_72 +#set_property PACKAGE_PIN D24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L16N_T2U_N7_QBC_AD3N_72 +#set_property PACKAGE_PIN D25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L16P_T2U_N6_QBC_AD3P_72 +#set_property PACKAGE_PIN D22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L15N_T2L_N5_AD11N_72 +#set_property PACKAGE_PIN E22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L15P_T2L_N4_AD11P_72 +#set_property PACKAGE_PIN F25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L14N_T2L_N3_GC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L14N_T2L_N3_GC_72 +#set_property PACKAGE_PIN F26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L14P_T2L_N2_GC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L14P_T2L_N2_GC_72 +#set_property PACKAGE_PIN E23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L13N_T2L_N1_GC_QBC_72 +#set_property PACKAGE_PIN E24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L13P_T2L_N0_GC_QBC_72 +#set_property PACKAGE_PIN G25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L12N_T1U_N11_GC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L12N_T1U_N11_GC_72 +#set_property PACKAGE_PIN G26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L12P_T1U_N10_GC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L12P_T1U_N10_GC_72 +#set_property PACKAGE_PIN F23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L11N_T1U_N9_GC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L11N_T1U_N9_GC_72 +#set_property PACKAGE_PIN F24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L11P_T1U_N8_GC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L11P_T1U_N8_GC_72 +#set_property PACKAGE_PIN G22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L10N_T1U_N7_QBC_AD4N_72 +#set_property PACKAGE_PIN G23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L10P_T1U_N6_QBC_AD4P_72 +#set_property PACKAGE_PIN G27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L9N_T1L_N5_AD12N_72 +#set_property PACKAGE_PIN H27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L9P_T1L_N4_AD12P_72 +#set_property PACKAGE_PIN H22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L8N_T1L_N3_AD5N_72 +#set_property PACKAGE_PIN J22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L8P_T1L_N2_AD5P_72 +#set_property PACKAGE_PIN H23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L7N_T1L_N1_QBC_AD13N_72 +#set_property PACKAGE_PIN H24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L7P_T1L_N0_QBC_AD13P_72 +#set_property PACKAGE_PIN H25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T1U_N12_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T1U_N12_72 +#set_property PACKAGE_PIN J24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T0U_N12_VRP_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_T0U_N12_VRP_72 +#set_property PACKAGE_PIN J25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L6N_T0U_N11_AD6N_72 +#set_property PACKAGE_PIN J26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L6P_T0U_N10_AD6P_72 +#set_property PACKAGE_PIN J27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L5N_T0U_N9_AD14N_72 +#set_property PACKAGE_PIN K27 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L5P_T0U_N8_AD14P_72 +#set_property PACKAGE_PIN K22 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L4N_T0U_N7_DBC_AD7N_72 +#set_property PACKAGE_PIN L23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L4P_T0U_N6_DBC_AD7P_72 +#set_property PACKAGE_PIN K23 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L3N_T0L_N5_AD15N_72 +#set_property PACKAGE_PIN K24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L3P_T0L_N4_AD15P_72 +#set_property PACKAGE_PIN K26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L2N_T0L_N3_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L2N_T0L_N3_72 +#set_property PACKAGE_PIN L26 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L2P_T0L_N2_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L2P_T0L_N2_72 +#set_property PACKAGE_PIN L24 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L1N_T0L_N1_DBC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L1N_T0L_N1_DBC_72 +#set_property PACKAGE_PIN L25 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L1P_T0L_N0_DBC_72 +#set_property IOSTANDARD LVCMOS18 [get_ports "Not Connected"] ;# Bank 72 VCCO - Grounded - IO_L1P_T0L_N0_DBC_72 +#set_property PACKAGE_PIN AV43 [get_ports "Not Connected"] ;# Bank 124 - MGTREFCLK0N_124 +#set_property PACKAGE_PIN AV42 [get_ports "Not Connected"] ;# Bank 124 - MGTREFCLK0P_124 +#set_property PACKAGE_PIN AT43 [get_ports "Not Connected"] ;# Bank 124 - MGTREFCLK1N_124 +#set_property PACKAGE_PIN AT42 [get_ports "Not Connected"] ;# Bank 124 - MGTREFCLK1P_124 +#set_property PACKAGE_PIN BC54 [get_ports "Grounded"] ;# Bank 124 - MGTYRXN0_124 +#set_property PACKAGE_PIN BB52 [get_ports "Grounded"] ;# Bank 124 - MGTYRXN1_124 +#set_property PACKAGE_PIN BA54 [get_ports "Grounded"] ;# Bank 124 - MGTYRXN2_124 +#set_property PACKAGE_PIN BA50 [get_ports "Grounded"] ;# Bank 124 - MGTYRXN3_124 +#set_property PACKAGE_PIN BC53 [get_ports "Grounded"] ;# Bank 124 - MGTYRXP0_124 +#set_property PACKAGE_PIN BB51 [get_ports "Grounded"] ;# Bank 124 - MGTYRXP1_124 +#set_property PACKAGE_PIN BA53 [get_ports "Grounded"] ;# Bank 124 - MGTYRXP2_124 +#set_property PACKAGE_PIN BA49 [get_ports "Grounded"] ;# Bank 124 - MGTYRXP3_124 +#set_property PACKAGE_PIN BC49 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXN0_124 +#set_property PACKAGE_PIN BC45 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXN1_124 +#set_property PACKAGE_PIN BB47 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXN2_124 +#set_property PACKAGE_PIN BA45 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXN3_124 +#set_property PACKAGE_PIN BC48 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXP0_124 +#set_property PACKAGE_PIN BC44 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXP1_124 +#set_property PACKAGE_PIN BB46 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXP2_124 +#set_property PACKAGE_PIN BA44 [get_ports "Not Connected"] ;# Bank 124 - MGTYTXP3_124 +#set_property PACKAGE_PIN AR41 [get_ports "Not Connected"] ;# Bank 125 - MGTREFCLK0N_125 +#set_property PACKAGE_PIN AR40 [get_ports "Not Connected"] ;# Bank 125 - MGTREFCLK0P_125 +#set_property PACKAGE_PIN AP43 [get_ports "Not Connected"] ;# Bank 125 - MGTREFCLK1N_125 +#set_property PACKAGE_PIN AP42 [get_ports "Not Connected"] ;# Bank 125 - MGTREFCLK1P_125 +#set_property PACKAGE_PIN AU41 [get_ports "Grounded"] ;# Bank 125 - MGTRREF_LS +#set_property PACKAGE_PIN AY52 [get_ports "Grounded"] ;# Bank 125 - MGTYRXN0_125 +#set_property PACKAGE_PIN AW54 [get_ports "Grounded"] ;# Bank 125 - MGTYRXN1_125 +#set_property PACKAGE_PIN AW50 [get_ports "Grounded"] ;# Bank 125 - MGTYRXN2_125 +#set_property PACKAGE_PIN AV52 [get_ports "Grounded"] ;# Bank 125 - MGTYRXN3_125 +#set_property PACKAGE_PIN AY51 [get_ports "Grounded"] ;# Bank 125 - MGTYRXP0_125 +#set_property PACKAGE_PIN AW53 [get_ports "Grounded"] ;# Bank 125 - MGTYRXP1_125 +#set_property PACKAGE_PIN AW49 [get_ports "Grounded"] ;# Bank 125 - MGTYRXP2_125 +#set_property PACKAGE_PIN AV51 [get_ports "Grounded"] ;# Bank 125 - MGTYRXP3_125 +#set_property PACKAGE_PIN AY47 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXN0_125 +#set_property PACKAGE_PIN AW45 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXN1_125 +#set_property PACKAGE_PIN AV47 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXN2_125 +#set_property PACKAGE_PIN AU45 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXN3_125 +#set_property PACKAGE_PIN AY46 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXP0_125 +#set_property PACKAGE_PIN AW44 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXP1_125 +#set_property PACKAGE_PIN AV46 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXP2_125 +#set_property PACKAGE_PIN AU44 [get_ports "Not Connected"] ;# Bank 125 - MGTYTXP3_125 +#set_property PACKAGE_PIN AN41 [get_ports "Not Connected"] ;# Bank 126 - MGTREFCLK0N_126 +#set_property PACKAGE_PIN AN40 [get_ports "Not Connected"] ;# Bank 126 - MGTREFCLK0P_126 +#set_property PACKAGE_PIN AM43 [get_ports "Not Connected"] ;# Bank 126 - MGTREFCLK1N_126 +#set_property PACKAGE_PIN AM42 [get_ports "Not Connected"] ;# Bank 126 - MGTREFCLK1P_126 +#set_property PACKAGE_PIN AU54 [get_ports "Grounded"] ;# Bank 126 - MGTYRXN0_126 +#set_property PACKAGE_PIN AT52 [get_ports "Grounded"] ;# Bank 126 - MGTYRXN1_126 +#set_property PACKAGE_PIN AR54 [get_ports "Grounded"] ;# Bank 126 - MGTYRXN2_126 +#set_property PACKAGE_PIN AP52 [get_ports "Grounded"] ;# Bank 126 - MGTYRXN3_126 +#set_property PACKAGE_PIN AU53 [get_ports "Grounded"] ;# Bank 126 - MGTYRXP0_126 +#set_property PACKAGE_PIN AT51 [get_ports "Grounded"] ;# Bank 126 - MGTYRXP1_126 +#set_property PACKAGE_PIN AR53 [get_ports "Grounded"] ;# Bank 126 - MGTYRXP2_126 +#set_property PACKAGE_PIN AP51 [get_ports "Grounded"] ;# Bank 126 - MGTYRXP3_126 +#set_property PACKAGE_PIN AU49 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXN0_126 +#set_property PACKAGE_PIN AT47 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXN1_126 +#set_property PACKAGE_PIN AR49 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXN2_126 +#set_property PACKAGE_PIN AR45 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXN3_126 +#set_property PACKAGE_PIN AU48 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXP0_126 +#set_property PACKAGE_PIN AT46 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXP1_126 +#set_property PACKAGE_PIN AR48 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXP2_126 +#set_property PACKAGE_PIN AR44 [get_ports "Not Connected"] ;# Bank 126 - MGTYTXP3_126 +#set_property PACKAGE_PIN AL41 [get_ports "Not Connected"] ;# Bank 127 - MGTREFCLK0N_127 +#set_property PACKAGE_PIN AL40 [get_ports "Not Connected"] ;# Bank 127 - MGTREFCLK0P_127 +#set_property PACKAGE_PIN AK43 [get_ports "Not Connected"] ;# Bank 127 - MGTREFCLK1N_127 +#set_property PACKAGE_PIN AK42 [get_ports "Not Connected"] ;# Bank 127 - MGTREFCLK1P_127 +#set_property PACKAGE_PIN AN54 [get_ports "Grounded"] ;# Bank 127 - MGTYRXN0_127 +#set_property PACKAGE_PIN AN50 [get_ports "Grounded"] ;# Bank 127 - MGTYRXN1_127 +#set_property PACKAGE_PIN AM52 [get_ports "Grounded"] ;# Bank 127 - MGTYRXN2_127 +#set_property PACKAGE_PIN AL54 [get_ports "Grounded"] ;# Bank 127 - MGTYRXN3_127 +#set_property PACKAGE_PIN AN53 [get_ports "Grounded"] ;# Bank 127 - MGTYRXP0_127 +#set_property PACKAGE_PIN AN49 [get_ports "Grounded"] ;# Bank 127 - MGTYRXP1_127 +#set_property PACKAGE_PIN AM51 [get_ports "Grounded"] ;# Bank 127 - MGTYRXP2_127 +#set_property PACKAGE_PIN AL53 [get_ports "Grounded"] ;# Bank 127 - MGTYRXP3_127 +#set_property PACKAGE_PIN AP47 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXN0_127 +#set_property PACKAGE_PIN AN45 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXN1_127 +#set_property PACKAGE_PIN AM47 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXN2_127 +#set_property PACKAGE_PIN AL45 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXN3_127 +#set_property PACKAGE_PIN AP46 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXP0_127 +#set_property PACKAGE_PIN AN44 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXP1_127 +#set_property PACKAGE_PIN AM46 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXP2_127 +#set_property PACKAGE_PIN AL44 [get_ports "Not Connected"] ;# Bank 127 - MGTYTXP3_127 +#set_property PACKAGE_PIN AJ41 [get_ports "Not Connected"] ;# Bank 128 - MGTREFCLK0N_128 +#set_property PACKAGE_PIN AJ40 [get_ports "Not Connected"] ;# Bank 128 - MGTREFCLK0P_128 +#set_property PACKAGE_PIN AH43 [get_ports "Not Connected"] ;# Bank 128 - MGTREFCLK1N_128 +#set_property PACKAGE_PIN AH42 [get_ports "Not Connected"] ;# Bank 128 - MGTREFCLK1P_128 +#set_property PACKAGE_PIN AL50 [get_ports "Grounded"] ;# Bank 128 - MGTYRXN0_128 +#set_property PACKAGE_PIN AK52 [get_ports "Grounded"] ;# Bank 128 - MGTYRXN1_128 +#set_property PACKAGE_PIN AJ54 [get_ports "Grounded"] ;# Bank 128 - MGTYRXN2_128 +#set_property PACKAGE_PIN AH52 [get_ports "Grounded"] ;# Bank 128 - MGTYRXN3_128 +#set_property PACKAGE_PIN AL49 [get_ports "Grounded"] ;# Bank 128 - MGTYRXP0_128 +#set_property PACKAGE_PIN AK51 [get_ports "Grounded"] ;# Bank 128 - MGTYRXP1_128 +#set_property PACKAGE_PIN AJ53 [get_ports "Grounded"] ;# Bank 128 - MGTYRXP2_128 +#set_property PACKAGE_PIN AH51 [get_ports "Grounded"] ;# Bank 128 - MGTYRXP3_128 +#set_property PACKAGE_PIN AK47 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXN0_128 +#set_property PACKAGE_PIN AJ49 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXN1_128 +#set_property PACKAGE_PIN AJ45 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXN2_128 +#set_property PACKAGE_PIN AH47 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXN3_128 +#set_property PACKAGE_PIN AK46 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXP0_128 +#set_property PACKAGE_PIN AJ48 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXP1_128 +#set_property PACKAGE_PIN AJ44 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXP2_128 +#set_property PACKAGE_PIN AH46 [get_ports "Not Connected"] ;# Bank 128 - MGTYTXP3_128 +#set_property PACKAGE_PIN AG41 [get_ports "Not Connected"] ;# Bank 129 - MGTREFCLK0N_129 +#set_property PACKAGE_PIN AG40 [get_ports "Not Connected"] ;# Bank 129 - MGTREFCLK0P_129 +#set_property PACKAGE_PIN AF43 [get_ports "Not Connected"] ;# Bank 129 - MGTREFCLK1N_129 +#set_property PACKAGE_PIN AF42 [get_ports "Not Connected"] ;# Bank 129 - MGTREFCLK1P_129 +#set_property PACKAGE_PIN AE41 [get_ports "Grounded"] ;# Bank 129 - MGTRREF_LC +#set_property PACKAGE_PIN AG54 [get_ports "Grounded"] ;# Bank 129 - MGTYRXN0_129 +#set_property PACKAGE_PIN AF52 [get_ports "Grounded"] ;# Bank 129 - MGTYRXN1_129 +#set_property PACKAGE_PIN AE54 [get_ports "Grounded"] ;# Bank 129 - MGTYRXN2_129 +#set_property PACKAGE_PIN AE50 [get_ports "Grounded"] ;# Bank 129 - MGTYRXN3_129 +#set_property PACKAGE_PIN AG53 [get_ports "Grounded"] ;# Bank 129 - MGTYRXP0_129 +#set_property PACKAGE_PIN AF51 [get_ports "Grounded"] ;# Bank 129 - MGTYRXP1_129 +#set_property PACKAGE_PIN AE53 [get_ports "Grounded"] ;# Bank 129 - MGTYRXP2_129 +#set_property PACKAGE_PIN AE49 [get_ports "Grounded"] ;# Bank 129 - MGTYRXP3_129 +#set_property PACKAGE_PIN AG49 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXN0_129 +#set_property PACKAGE_PIN AG45 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXN1_129 +#set_property PACKAGE_PIN AF47 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXN2_129 +#set_property PACKAGE_PIN AE45 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXN3_129 +#set_property PACKAGE_PIN AG48 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXP0_129 +#set_property PACKAGE_PIN AG44 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXP1_129 +#set_property PACKAGE_PIN AF46 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXP2_129 +#set_property PACKAGE_PIN AE44 [get_ports "Not Connected"] ;# Bank 129 - MGTYTXP3_129 +#set_property PACKAGE_PIN AD43 [get_ports "Not Connected"] ;# Bank 130 - MGTREFCLK0N_130 +#set_property PACKAGE_PIN AD42 [get_ports "Not Connected"] ;# Bank 130 - MGTREFCLK0P_130 +#set_property PACKAGE_PIN AC41 [get_ports "Not Connected"] ;# Bank 130 - MGTREFCLK1N_130 +#set_property PACKAGE_PIN AC40 [get_ports "Not Connected"] ;# Bank 130 - MGTREFCLK1P_130 +#set_property PACKAGE_PIN AD52 [get_ports "Grounded"] ;# Bank 130 - MGTYRXN0_130 +#set_property PACKAGE_PIN AC54 [get_ports "Grounded"] ;# Bank 130 - MGTYRXN1_130 +#set_property PACKAGE_PIN AC50 [get_ports "Grounded"] ;# Bank 130 - MGTYRXN2_130 +#set_property PACKAGE_PIN AB52 [get_ports "Grounded"] ;# Bank 130 - MGTYRXN3_130 +#set_property PACKAGE_PIN AD51 [get_ports "Grounded"] ;# Bank 130 - MGTYRXP0_130 +#set_property PACKAGE_PIN AC53 [get_ports "Grounded"] ;# Bank 130 - MGTYRXP1_130 +#set_property PACKAGE_PIN AC49 [get_ports "Grounded"] ;# Bank 130 - MGTYRXP2_130 +#set_property PACKAGE_PIN AB51 [get_ports "Grounded"] ;# Bank 130 - MGTYRXP3_130 +#set_property PACKAGE_PIN AD47 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXN0_130 +#set_property PACKAGE_PIN AC45 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXN1_130 +#set_property PACKAGE_PIN AB47 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXN2_130 +#set_property PACKAGE_PIN AA49 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXN3_130 +#set_property PACKAGE_PIN AD46 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXP0_130 +#set_property PACKAGE_PIN AC44 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXP1_130 +#set_property PACKAGE_PIN AB46 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXP2_130 +#set_property PACKAGE_PIN AA48 [get_ports "Not Connected"] ;# Bank 130 - MGTYTXP3_130 +#set_property PACKAGE_PIN AB43 [get_ports "Not Connected"] ;# Bank 131 - MGTREFCLK0N_131 +#set_property PACKAGE_PIN AB42 [get_ports "Not Connected"] ;# Bank 131 - MGTREFCLK0P_131 +#set_property PACKAGE_PIN AA41 [get_ports "Not Connected"] ;# Bank 131 - MGTREFCLK1N_131 +#set_property PACKAGE_PIN AA40 [get_ports "Not Connected"] ;# Bank 131 - MGTREFCLK1P_131 +#set_property PACKAGE_PIN AA54 [get_ports "Grounded"] ;# Bank 131 - MGTYRXN0_131 +#set_property PACKAGE_PIN Y52 [get_ports "Grounded"] ;# Bank 131 - MGTYRXN1_131 +#set_property PACKAGE_PIN W54 [get_ports "Grounded"] ;# Bank 131 - MGTYRXN2_131 +#set_property PACKAGE_PIN V52 [get_ports "Grounded"] ;# Bank 131 - MGTYRXN3_131 +#set_property PACKAGE_PIN AA53 [get_ports "Grounded"] ;# Bank 131 - MGTYRXP0_131 +#set_property PACKAGE_PIN Y51 [get_ports "Grounded"] ;# Bank 131 - MGTYRXP1_131 +#set_property PACKAGE_PIN W53 [get_ports "Grounded"] ;# Bank 131 - MGTYRXP2_131 +#set_property PACKAGE_PIN V51 [get_ports "Grounded"] ;# Bank 131 - MGTYRXP3_131 +#set_property PACKAGE_PIN AA45 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXN0_131 +#set_property PACKAGE_PIN Y47 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXN1_131 +#set_property PACKAGE_PIN W49 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXN2_131 +#set_property PACKAGE_PIN W45 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXN3_131 +#set_property PACKAGE_PIN AA44 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXP0_131 +#set_property PACKAGE_PIN Y46 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXP1_131 +#set_property PACKAGE_PIN W48 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXP2_131 +#set_property PACKAGE_PIN W44 [get_ports "Not Connected"] ;# Bank 131 - MGTYTXP3_131 +#set_property PACKAGE_PIN Y43 [get_ports "Not Connected"] ;# Bank 132 - MGTREFCLK0N_132 +#set_property PACKAGE_PIN Y42 [get_ports "Not Connected"] ;# Bank 132 - MGTREFCLK0P_132 +#set_property PACKAGE_PIN W41 [get_ports "Not Connected"] ;# Bank 132 - MGTREFCLK1N_132 +#set_property PACKAGE_PIN W40 [get_ports "Not Connected"] ;# Bank 132 - MGTREFCLK1P_132 +#set_property PACKAGE_PIN U54 [get_ports "Grounded"] ;# Bank 132 - MGTYRXN0_132 +#set_property PACKAGE_PIN U50 [get_ports "Grounded"] ;# Bank 132 - MGTYRXN1_132 +#set_property PACKAGE_PIN T52 [get_ports "Grounded"] ;# Bank 132 - MGTYRXN2_132 +#set_property PACKAGE_PIN R54 [get_ports "Grounded"] ;# Bank 132 - MGTYRXN3_132 +#set_property PACKAGE_PIN U53 [get_ports "Grounded"] ;# Bank 132 - MGTYRXP0_132 +#set_property PACKAGE_PIN U49 [get_ports "Grounded"] ;# Bank 132 - MGTYRXP1_132 +#set_property PACKAGE_PIN T51 [get_ports "Grounded"] ;# Bank 132 - MGTYRXP2_132 +#set_property PACKAGE_PIN R53 [get_ports "Grounded"] ;# Bank 132 - MGTYRXP3_132 +#set_property PACKAGE_PIN V47 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXN0_132 +#set_property PACKAGE_PIN U45 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXN1_132 +#set_property PACKAGE_PIN T47 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXN2_132 +#set_property PACKAGE_PIN R45 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXN3_132 +#set_property PACKAGE_PIN V46 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXP0_132 +#set_property PACKAGE_PIN U44 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXP1_132 +#set_property PACKAGE_PIN T46 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXP2_132 +#set_property PACKAGE_PIN R44 [get_ports "Not Connected"] ;# Bank 132 - MGTYTXP3_132 +#set_property PACKAGE_PIN V43 [get_ports "Not Connected"] ;# Bank 133 - MGTREFCLK0N_133 +#set_property PACKAGE_PIN V42 [get_ports "Not Connected"] ;# Bank 133 - MGTREFCLK0P_133 +#set_property PACKAGE_PIN U41 [get_ports "Not Connected"] ;# Bank 133 - MGTREFCLK1N_133 +#set_property PACKAGE_PIN U40 [get_ports "Not Connected"] ;# Bank 133 - MGTREFCLK1P_133 +#set_property PACKAGE_PIN N41 [get_ports "N38370065"] ;# Bank 133 - MGTRREF_LN +#set_property PACKAGE_PIN R50 [get_ports "Grounded"] ;# Bank 133 - MGTYRXN0_133 +#set_property PACKAGE_PIN P52 [get_ports "Grounded"] ;# Bank 133 - MGTYRXN1_133 +#set_property PACKAGE_PIN N54 [get_ports "Grounded"] ;# Bank 133 - MGTYRXN2_133 +#set_property PACKAGE_PIN M52 [get_ports "Grounded"] ;# Bank 133 - MGTYRXN3_133 +#set_property PACKAGE_PIN R49 [get_ports "Grounded"] ;# Bank 133 - MGTYRXP0_133 +#set_property PACKAGE_PIN P51 [get_ports "Grounded"] ;# Bank 133 - MGTYRXP1_133 +#set_property PACKAGE_PIN N53 [get_ports "Grounded"] ;# Bank 133 - MGTYRXP2_133 +#set_property PACKAGE_PIN M51 [get_ports "Grounded"] ;# Bank 133 - MGTYRXP3_133 +#set_property PACKAGE_PIN P47 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXN0_133 +#set_property PACKAGE_PIN N49 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXN1_133 +#set_property PACKAGE_PIN N45 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXN2_133 +#set_property PACKAGE_PIN M47 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXN3_133 +#set_property PACKAGE_PIN P46 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXP0_133 +#set_property PACKAGE_PIN N48 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXP1_133 +#set_property PACKAGE_PIN N44 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXP2_133 +#set_property PACKAGE_PIN M46 [get_ports "Not Connected"] ;# Bank 133 - MGTYTXP3_133 +#set_property PACKAGE_PIN AV12 [get_ports "Not Connected"] ;# Bank 224 - MGTREFCLK0N_224 +#set_property PACKAGE_PIN AV13 [get_ports "Not Connected"] ;# Bank 224 - MGTREFCLK0P_224 +#set_property PACKAGE_PIN AT12 [get_ports "Not Connected"] ;# Bank 224 - MGTREFCLK1N_224 +#set_property PACKAGE_PIN AT13 [get_ports "Not Connected"] ;# Bank 224 - MGTREFCLK1P_224 +#set_property PACKAGE_PIN AN14 [get_ports "Not Connected"] ;# Bank 226 - MGTREFCLK0N_226 +#set_property PACKAGE_PIN AN15 [get_ports "Not Connected"] ;# Bank 226 - MGTREFCLK0P_226 +#set_property PACKAGE_PIN AM12 [get_ports "Not Connected"] ;# Bank 226 - MGTREFCLK1N_226 +#set_property PACKAGE_PIN AM13 [get_ports "Not Connected"] ;# Bank 226 - MGTREFCLK1P_226 +#set_property PACKAGE_PIN AJ14 [get_ports "Not Connected"] ;# Bank 228 - MGTREFCLK0N_228 +#set_property PACKAGE_PIN AJ15 [get_ports "Not Connected"] ;# Bank 228 - MGTREFCLK0P_228 +#set_property PACKAGE_PIN AH12 [get_ports "Not Connected"] ;# Bank 228 - MGTREFCLK1N_228 +#set_property PACKAGE_PIN AH13 [get_ports "Not Connected"] ;# Bank 228 - MGTREFCLK1P_228 +#set_property PACKAGE_PIN AL5 [get_ports "Grounded"] ;# Bank 228 - MGTYRXN0_228 +#set_property PACKAGE_PIN AK3 [get_ports "Grounded"] ;# Bank 228 - MGTYRXN1_228 +#set_property PACKAGE_PIN AJ1 [get_ports "Grounded"] ;# Bank 228 - MGTYRXN2_228 +#set_property PACKAGE_PIN AH3 [get_ports "Grounded"] ;# Bank 228 - MGTYRXN3_228 +#set_property PACKAGE_PIN AL6 [get_ports "Grounded"] ;# Bank 228 - MGTYRXP0_228 +#set_property PACKAGE_PIN AK4 [get_ports "Grounded"] ;# Bank 228 - MGTYRXP1_228 +#set_property PACKAGE_PIN AJ2 [get_ports "Grounded"] ;# Bank 228 - MGTYRXP2_228 +#set_property PACKAGE_PIN AH4 [get_ports "Grounded"] ;# Bank 228 - MGTYRXP3_228 +#set_property PACKAGE_PIN AK8 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXN0_228 +#set_property PACKAGE_PIN AJ6 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXN1_228 +#set_property PACKAGE_PIN AJ10 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXN2_228 +#set_property PACKAGE_PIN AH8 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXN3_228 +#set_property PACKAGE_PIN AK9 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXP0_228 +#set_property PACKAGE_PIN AJ7 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXP1_228 +#set_property PACKAGE_PIN AJ11 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXP2_228 +#set_property PACKAGE_PIN AH9 [get_ports "Not Connected"] ;# Bank 228 - MGTYTXP3_228 +#set_property PACKAGE_PIN AG14 [get_ports "Not Connected"] ;# Bank 229 - MGTREFCLK0N_229 +#set_property PACKAGE_PIN AG15 [get_ports "Not Connected"] ;# Bank 229 - MGTREFCLK0P_229 +#set_property PACKAGE_PIN AF12 [get_ports "Not Connected"] ;# Bank 229 - MGTREFCLK1N_229 +#set_property PACKAGE_PIN AF13 [get_ports "Not Connected"] ;# Bank 229 - MGTREFCLK1P_229 +#set_property PACKAGE_PIN AE14 [get_ports "Grounded"] ;# Bank 229 - MGTRREF_RC +#set_property PACKAGE_PIN AG1 [get_ports "Grounded"] ;# Bank 229 - MGTYRXN0_229 +#set_property PACKAGE_PIN AF3 [get_ports "Grounded"] ;# Bank 229 - MGTYRXN1_229 +#set_property PACKAGE_PIN AE1 [get_ports "Grounded"] ;# Bank 229 - MGTYRXN2_229 +#set_property PACKAGE_PIN AE5 [get_ports "Grounded"] ;# Bank 229 - MGTYRXN3_229 +#set_property PACKAGE_PIN AG2 [get_ports "Grounded"] ;# Bank 229 - MGTYRXP0_229 +#set_property PACKAGE_PIN AF4 [get_ports "Grounded"] ;# Bank 229 - MGTYRXP1_229 +#set_property PACKAGE_PIN AE2 [get_ports "Grounded"] ;# Bank 229 - MGTYRXP2_229 +#set_property PACKAGE_PIN AE6 [get_ports "Grounded"] ;# Bank 229 - MGTYRXP3_229 +#set_property PACKAGE_PIN AG6 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXN0_229 +#set_property PACKAGE_PIN AG10 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXN1_229 +#set_property PACKAGE_PIN AF8 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXN2_229 +#set_property PACKAGE_PIN AE10 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXN3_229 +#set_property PACKAGE_PIN AG7 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXP0_229 +#set_property PACKAGE_PIN AG11 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXP1_229 +#set_property PACKAGE_PIN AF9 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXP2_229 +#set_property PACKAGE_PIN AE11 [get_ports "Not Connected"] ;# Bank 229 - MGTYTXP3_229 +#set_property PACKAGE_PIN AD12 [get_ports "Not Connected"] ;# Bank 230 - MGTREFCLK0N_230 +#set_property PACKAGE_PIN AD13 [get_ports "Not Connected"] ;# Bank 230 - MGTREFCLK0P_230 +#set_property PACKAGE_PIN AC14 [get_ports "Not Connected"] ;# Bank 230 - MGTREFCLK1N_230 +#set_property PACKAGE_PIN AC15 [get_ports "Not Connected"] ;# Bank 230 - MGTREFCLK1P_230 +#set_property PACKAGE_PIN AD3 [get_ports "Grounded"] ;# Bank 230 - MGTYRXN0_230 +#set_property PACKAGE_PIN AC1 [get_ports "Grounded"] ;# Bank 230 - MGTYRXN1_230 +#set_property PACKAGE_PIN AC5 [get_ports "Grounded"] ;# Bank 230 - MGTYRXN2_230 +#set_property PACKAGE_PIN AB3 [get_ports "Grounded"] ;# Bank 230 - MGTYRXN3_230 +#set_property PACKAGE_PIN AD4 [get_ports "Grounded"] ;# Bank 230 - MGTYRXP0_230 +#set_property PACKAGE_PIN AC2 [get_ports "Grounded"] ;# Bank 230 - MGTYRXP1_230 +#set_property PACKAGE_PIN AC6 [get_ports "Grounded"] ;# Bank 230 - MGTYRXP2_230 +#set_property PACKAGE_PIN AB4 [get_ports "Grounded"] ;# Bank 230 - MGTYRXP3_230 +#set_property PACKAGE_PIN AD8 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXN0_230 +#set_property PACKAGE_PIN AC10 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXN1_230 +#set_property PACKAGE_PIN AB8 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXN2_230 +#set_property PACKAGE_PIN AA6 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXN3_230 +#set_property PACKAGE_PIN AD9 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXP0_230 +#set_property PACKAGE_PIN AC11 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXP1_230 +#set_property PACKAGE_PIN AB9 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXP2_230 +#set_property PACKAGE_PIN AA7 [get_ports "Not Connected"] ;# Bank 230 - MGTYTXP3_230 +#set_property PACKAGE_PIN AB12 [get_ports "Not Connected"] ;# Bank 231 - MGTREFCLK0N_231 +#set_property PACKAGE_PIN AB13 [get_ports "Not Connected"] ;# Bank 231 - MGTREFCLK0P_231 +#set_property PACKAGE_PIN AA14 [get_ports "Not Connected"] ;# Bank 231 - MGTREFCLK1N_231 +#set_property PACKAGE_PIN AA15 [get_ports "Not Connected"] ;# Bank 231 - MGTREFCLK1P_231 +#set_property PACKAGE_PIN AA1 [get_ports "Grounded"] ;# Bank 231 - MGTYRXN0_231 +#set_property PACKAGE_PIN Y3 [get_ports "Grounded"] ;# Bank 231 - MGTYRXN1_231 +#set_property PACKAGE_PIN W1 [get_ports "Grounded"] ;# Bank 231 - MGTYRXN2_231 +#set_property PACKAGE_PIN V3 [get_ports "Grounded"] ;# Bank 231 - MGTYRXN3_231 +#set_property PACKAGE_PIN AA2 [get_ports "Grounded"] ;# Bank 231 - MGTYRXP0_231 +#set_property PACKAGE_PIN Y4 [get_ports "Grounded"] ;# Bank 231 - MGTYRXP1_231 +#set_property PACKAGE_PIN W2 [get_ports "Grounded"] ;# Bank 231 - MGTYRXP2_231 +#set_property PACKAGE_PIN V4 [get_ports "Grounded"] ;# Bank 231 - MGTYRXP3_231 +#set_property PACKAGE_PIN AA10 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXN0_231 +#set_property PACKAGE_PIN Y8 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXN1_231 +#set_property PACKAGE_PIN W6 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXN2_231 +#set_property PACKAGE_PIN W10 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXN3_231 +#set_property PACKAGE_PIN AA11 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXP0_231 +#set_property PACKAGE_PIN Y9 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXP1_231 +#set_property PACKAGE_PIN W7 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXP2_231 +#set_property PACKAGE_PIN W11 [get_ports "Not Connected"] ;# Bank 231 - MGTYTXP3_231 +#set_property PACKAGE_PIN Y12 [get_ports "Not Connected"] ;# Bank 232 - MGTREFCLK0N_232 +#set_property PACKAGE_PIN Y13 [get_ports "Not Connected"] ;# Bank 232 - MGTREFCLK0P_232 +#set_property PACKAGE_PIN W14 [get_ports "Not Connected"] ;# Bank 232 - MGTREFCLK1N_232 +#set_property PACKAGE_PIN W15 [get_ports "Not Connected"] ;# Bank 232 - MGTREFCLK1P_232 +#set_property PACKAGE_PIN U1 [get_ports "Grounded"] ;# Bank 232 - MGTYRXN0_232 +#set_property PACKAGE_PIN U5 [get_ports "Grounded"] ;# Bank 232 - MGTYRXN1_232 +#set_property PACKAGE_PIN T3 [get_ports "Grounded"] ;# Bank 232 - MGTYRXN2_232 +#set_property PACKAGE_PIN R1 [get_ports "Grounded"] ;# Bank 232 - MGTYRXN3_232 +#set_property PACKAGE_PIN U2 [get_ports "Grounded"] ;# Bank 232 - MGTYRXP0_232 +#set_property PACKAGE_PIN U6 [get_ports "Grounded"] ;# Bank 232 - MGTYRXP1_232 +#set_property PACKAGE_PIN T4 [get_ports "Grounded"] ;# Bank 232 - MGTYRXP2_232 +#set_property PACKAGE_PIN R2 [get_ports "Grounded"] ;# Bank 232 - MGTYRXP3_232 +#set_property PACKAGE_PIN V8 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXN0_232 +#set_property PACKAGE_PIN U10 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXN1_232 +#set_property PACKAGE_PIN T8 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXN2_232 +#set_property PACKAGE_PIN R10 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXN3_232 +#set_property PACKAGE_PIN V9 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXP0_232 +#set_property PACKAGE_PIN U11 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXP1_232 +#set_property PACKAGE_PIN T9 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXP2_232 +#set_property PACKAGE_PIN R11 [get_ports "Not Connected"] ;# Bank 232 - MGTYTXP3_232 +#set_property PACKAGE_PIN V12 [get_ports "Not Connected"] ;# Bank 233 - MGTREFCLK0N_233 +#set_property PACKAGE_PIN V13 [get_ports "Not Connected"] ;# Bank 233 - MGTREFCLK0P_233 +#set_property PACKAGE_PIN U14 [get_ports "Not Connected"] ;# Bank 233 - MGTREFCLK1N_233 +#set_property PACKAGE_PIN U15 [get_ports "Not Connected"] ;# Bank 233 - MGTREFCLK1P_233 +#set_property PACKAGE_PIN N14 [get_ports "Grounded"] ;# Bank 233 - MGTRREF_RN +#set_property PACKAGE_PIN R5 [get_ports "Grounded"] ;# Bank 233 - MGTYRXN0_233 +#set_property PACKAGE_PIN P3 [get_ports "Grounded"] ;# Bank 233 - MGTYRXN1_233 +#set_property PACKAGE_PIN N1 [get_ports "Grounded"] ;# Bank 233 - MGTYRXN2_233 +#set_property PACKAGE_PIN M3 [get_ports "Grounded"] ;# Bank 233 - MGTYRXN3_233 +#set_property PACKAGE_PIN R6 [get_ports "Grounded"] ;# Bank 233 - MGTYRXP0_233 +#set_property PACKAGE_PIN P4 [get_ports "Grounded"] ;# Bank 233 - MGTYRXP1_233 +#set_property PACKAGE_PIN N2 [get_ports "Grounded"] ;# Bank 233 - MGTYRXP2_233 +#set_property PACKAGE_PIN M4 [get_ports "Grounded"] ;# Bank 233 - MGTYRXP3_233 +#set_property PACKAGE_PIN P8 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXN0_233 +#set_property PACKAGE_PIN N6 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXN1_233 +#set_property PACKAGE_PIN N10 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXN2_233 +#set_property PACKAGE_PIN M8 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXN3_233 +#set_property PACKAGE_PIN P9 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXP0_233 +#set_property PACKAGE_PIN N7 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXP1_233 +#set_property PACKAGE_PIN N11 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXP2_233 +#set_property PACKAGE_PIN M9 [get_ports "Not Connected"] ;# Bank 233 - MGTYTXP3_233 +#set_property PACKAGE_PIN T12 [get_ports "Not Connected"] ;# Bank 234 - MGTREFCLK0N_234 +#set_property PACKAGE_PIN T13 [get_ports "Not Connected"] ;# Bank 234 - MGTREFCLK0P_234 +#set_property PACKAGE_PIN R14 [get_ports "Not Connected"] ;# Bank 234 - MGTREFCLK1N_234 +#set_property PACKAGE_PIN R15 [get_ports "Not Connected"] ;# Bank 234 - MGTREFCLK1P_234 +#set_property PACKAGE_PIN L1 [get_ports "Grounded"] ;# Bank 234 - MGTYRXN0_234 +#set_property PACKAGE_PIN K3 [get_ports "Grounded"] ;# Bank 234 - MGTYRXN1_234 +#set_property PACKAGE_PIN J1 [get_ports "Grounded"] ;# Bank 234 - MGTYRXN2_234 +#set_property PACKAGE_PIN H3 [get_ports "Grounded"] ;# Bank 234 - MGTYRXN3_234 +#set_property PACKAGE_PIN L2 [get_ports "Grounded"] ;# Bank 234 - MGTYRXP0_234 +#set_property PACKAGE_PIN K4 [get_ports "Grounded"] ;# Bank 234 - MGTYRXP1_234 +#set_property PACKAGE_PIN J2 [get_ports "Grounded"] ;# Bank 234 - MGTYRXP2_234 +#set_property PACKAGE_PIN H4 [get_ports "Grounded"] ;# Bank 234 - MGTYRXP3_234 +#set_property PACKAGE_PIN L6 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXN0_234 +#set_property PACKAGE_PIN L10 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXN1_234 +#set_property PACKAGE_PIN K8 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXN2_234 +#set_property PACKAGE_PIN J6 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXN3_234 +#set_property PACKAGE_PIN L7 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXP0_234 +#set_property PACKAGE_PIN L11 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXP1_234 +#set_property PACKAGE_PIN K9 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXP2_234 +#set_property PACKAGE_PIN J7 [get_ports "Not Connected"] ;# Bank 234 - MGTYTXP3_234 +#set_property PACKAGE_PIN P12 [get_ports "Not Connected"] ;# Bank 235 - MGTREFCLK0N_235 +#set_property PACKAGE_PIN P13 [get_ports "Not Connected"] ;# Bank 235 - MGTREFCLK0P_235 +#set_property PACKAGE_PIN M12 [get_ports "Not Connected"] ;# Bank 235 - MGTREFCLK1N_235 +#set_property PACKAGE_PIN M13 [get_ports "Not Connected"] ;# Bank 235 - MGTREFCLK1P_235 +#set_property PACKAGE_PIN G1 [get_ports "Grounded"] ;# Bank 235 - MGTYRXN0_235 +#set_property PACKAGE_PIN F3 [get_ports "Grounded"] ;# Bank 235 - MGTYRXN1_235 +#set_property PACKAGE_PIN E1 [get_ports "Grounded"] ;# Bank 235 - MGTYRXN2_235 +#set_property PACKAGE_PIN D3 [get_ports "Grounded"] ;# Bank 235 - MGTYRXN3_235 +#set_property PACKAGE_PIN G2 [get_ports "Grounded"] ;# Bank 235 - MGTYRXP0_235 +#set_property PACKAGE_PIN F4 [get_ports "Grounded"] ;# Bank 235 - MGTYRXP1_235 +#set_property PACKAGE_PIN E2 [get_ports "Grounded"] ;# Bank 235 - MGTYRXP2_235 +#set_property PACKAGE_PIN D4 [get_ports "Grounded"] ;# Bank 235 - MGTYRXP3_235 +#set_property PACKAGE_PIN G6 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXN0_235 +#set_property PACKAGE_PIN E6 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXN1_235 +#set_property PACKAGE_PIN C6 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXN2_235 +#set_property PACKAGE_PIN A5 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXN3_235 +#set_property PACKAGE_PIN G7 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXP0_235 +#set_property PACKAGE_PIN E7 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXP1_235 +#set_property PACKAGE_PIN C7 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXP2_235 +#set_property PACKAGE_PIN A6 [get_ports "Not Connected"] ;# Bank 235 - MGTYTXP3_235 diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/uninasoc.xdc b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/uninasoc.xdc new file mode 100644 index 0000000000000000000000000000000000000000..6d234bf51a49d0922d6b4e68a30a9597d1fd3119 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/constraints/uninasoc.xdc @@ -0,0 +1,6 @@ +# Author: Vincenzo Maisto +# Description: Board-independent constraints + +# False path though VIO reset +set VIO_RESETN [get_pins -of [get_nets vio_resetn] -filter {NAME=~vio_inst/*}] +set_false_path -hold -through $VIO_RESETN \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/add_ila.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/add_ila.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f34ffeed6cd340852a33c266c4581df2380e78c0 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/add_ila.tcl @@ -0,0 +1,62 @@ +# Author: Vincenzo Maisto +# Author: Cyril Koenig +# Description: Create an ILA core and attach all nets in the design marked as MARK_DEBUG. + +# ILA clock from SoC design +# Choose a clock net as fast as the fastest net to probe +set ila_clk_net [get_nets $::env(XILINX_ILA_CLOCK)] + +# Get market nets +set debug_nets [lsort -dictionary [get_nets -hier -filter {MARK_DEBUG == 1}]] + +# Return if there is any marked net +if { ![llength $debug_nets] } { + puts "\[ILA\] No nets marked for debug" + return +} + +# Create and configure debug core +puts "\[ILA\] Creating debug core..." +create_debug_core ila_u ila +set_property -dict [list \ + ALL_PROBE_SAME_MU {true} \ + ALL_PROBE_SAME_MU_CNT {4} \ + C_ADV_TRIGGER {true} \ + C_DATA_DEPTH {16384} \ + C_EN_STRG_QUAL {true} \ + C_INPUT_PIPE_STAGES {0} \ + C_TRIGIN_EN {false} \ + C_TRIGOUT_EN {false} \ + ] [get_debug_cores ila_u] + +# Connect SoC clock +set_property port_width 1 [get_debug_ports ila_u/clk] +connect_debug_port ila_u/clk [get_nets $ila_clk_net] + +# Loop through debug nets (add extra list element to ensure last net is processed) +set net_name_last "" +set i 0 +foreach net [concat $debug_nets {""}] { + # Remove trailing array index + regsub {\[[0-9]*\]$} $net {} net_name + # Create probe after all signals with the same name have been collected + if { $net_name_last != $net_name } { + if { $net_name_last != "" } { + puts "\[ILA\] Creating probe $i of width [llength $sig_list] for `$net_name_last`." + # probe0 already exists, and does not need to be created + if { $i != 0 } { create_debug_port ila_u probe } + set_property port_width [llength $sig_list] [get_debug_ports ila_u/probe$i] + # Set all probes both as data and trigger, although it might be overkill and could be simplified for more challenging designs + set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports ila_u/probe$i] + connect_debug_port ila_u/probe$i [get_nets $sig_list] + incr i + } + set sig_list "" + } + lappend sig_list $net + set net_name_last $net_name +} + +# Save constraints, then implement the debug core +save_constraints -force +implement_debug_core diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/add_xilinx_sources.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/add_xilinx_sources.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1fb135ca289831eb1a0b13fdd4da5c783d09ca1b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/add_xilinx_sources.tcl @@ -0,0 +1,28 @@ +## Author: Vincenzo Maisto +## Description: Utility variables and macros for AXI interconnections in UninaSoC + +# Define a list of all the source files +set src_file_list [ list \ + $::env(XILINX_ROOT)/rtl/uninasoc_pkg.sv \ + $::env(XILINX_ROOT)/rtl/uninasoc_axi.svh \ + $::env(XILINX_ROOT)/rtl/uninasoc_pcie.svh \ + $::env(XILINX_ROOT)/rtl/uninasoc_ddr4.svh \ + $::env(XILINX_ROOT)/rtl/mbus_buses.svinc \ + $::env(XILINX_ROOT)/rtl/pbus_buses.svinc \ + $::env(XILINX_ROOT)/rtl/hbus_buses.svinc \ + $::env(XILINX_ROOT)/rtl/highperformance_bus.sv \ + $::env(XILINX_ROOT)/rtl/hls_conv2d_wrapper.sv \ + $::env(XILINX_ROOT)/rtl/uninasoc_clk_assignments.svinc \ + $::env(XILINX_ROOT)/rtl/axi_clock_converter_wrapper.sv \ + $::env(XILINX_ROOT)/rtl/sys_master.sv \ + $::env(XILINX_ROOT)/rtl/rv_socket.sv \ + $::env(XILINX_ROOT)/rtl/virtual_uart.sv \ + $::env(XILINX_ROOT)/rtl/axilite_uart.sv \ + $::env(XILINX_ROOT)/rtl/peripheral_bus.sv \ + $::env(XILINX_ROOT)/rtl/ddr4_channel_wrapper.sv \ + $::env(XILINX_ROOT)/rtl/plic_wrapper.sv \ + $::env(XILINX_ROOT)/rtl/uninasoc.sv \ +] + +# Add files to project +add_files -norecurse -fileset [current_fileset] $src_file_list diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/build_bitstream.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/build_bitstream.tcl new file mode 100644 index 0000000000000000000000000000000000000000..1137e23866fcd231374bf40eb9684bff094acaf0 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/build_bitstream.tcl @@ -0,0 +1,153 @@ +# Author: Vincenzo Maisto +# Author: Manuel Maddaluno +# Description: Create a Vivado project, import sources and IPs and run: elaboration, +# synthesis and implementation up to bitstream generation. +# Input args: +# None +# Note: +# This script entirely relies on enironment variables + +######################## +# Setup Vivado project # +######################## +# Create new project (force) +create_project $::env(XILINX_PROJECT_NAME) . -part $::env(XILINX_PART_NUMBER) -force +set_property board_part $::env(XILINX_BOARD_PART) [current_project] + +####################### +# Suppress Message(s) # +####################### +source $::env(XILINX_SYNTH_TCL_ROOT)/suppress_messages.tcl + +################### +# Verilog defines # +################### +source $::env(XILINX_SYNTH_TCL_ROOT)/verilog_defines.tcl + +############### +# Add sources # +############### + +# RTL +source $::env(XILINX_SYNTH_TCL_ROOT)/add_xilinx_sources.tcl + +# Load constraints +import_files -fileset constrs_1 -norecurse $::env(XILINX_ROOT)/synth/constraints/$::env(XILINX_PROJECT_NAME).xdc +import_files -fileset constrs_1 -norecurse $::env(XILINX_ROOT)/synth/constraints/$::env(BOARD).xdc + +# Import IPS +puts "\[INFO\] Importing IPs: $::env(IP_LIST_XCI)" +import_ip $::env(IP_LIST_XCI) + +###################### +# Project properties # +###################### +# TODO: Which memory IP was this for? +set_property XPM_LIBRARIES XPM_MEMORY [current_project] + +# Set top level module +set_property top $::env(XILINX_PROJECT_NAME) [current_fileset] + +# Generate compilation order +update_compile_order -fileset sources_1 + +# Reports directory +set project_dir [get_property directory [current_project]] +set report_dir $project_dir/reports +exec mkdir -p $report_dir + +########## +# Linter # +########## + +# Run linter +set lint_filename $report_dir/lint.log +synth_design -lint -file $lint_filename + +# Read-back file +set fp [open $lint_filename r] +set file_data [read $fp] +close $fp +# Parse for critical warnings +set lines [split $file_data "\n"] +set substring "CRITICAL WARNING" +set line_cnt 0 +set critical_found "false" +foreach line_value $lines { + set line_cnt [expr $line_cnt + 1] + if {[string first $substring $line_value] != -1} { + puts "\[ERROR\] Found $substring during linting! $lint_filename:$line_cnt" + set critical_found "true" + } +} +# Exit if found +if { $critical_found == "true" } { + exit 1 +} + +################### +# RTL elaboration # +################### +synth_design -rtl -name rtl_1 + +############# +# Synthesis # +############# +# Set strategy +set_property STRATEGY $::env(SYNTH_STRATEGY) [get_runs synth_1] +# Preserve the net names and hierarchy for debug +set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY none [get_runs synth_1] +set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1] +# # Enable retiming in synthesis +# set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1] + +# Run +launch_runs synth_1 +wait_on_run synth_1 +# Open synthesized design +open_run synth_1 -name synth_1 +# Genate reports +check_timing -verbose -file $report_dir/$::env(XILINX_PROJECT_NAME).post_synth.check_timing.rpt +report_utilization -hierarchical -hierarchical_percentage -file $report_dir/$::env(XILINX_PROJECT_NAME).post_synth.utilization.rpt + +############ +# Add ILAs # +############ +if { $::env(XILINX_ILA) == 1 } { + source $::env(XILINX_SYNTH_TCL_ROOT)/mark_debug_nets.tcl + source $::env(XILINX_SYNTH_TCL_ROOT)/add_ila.tcl +} + +################## +# Implementation # +################## +# Runtime optimized build +# set_property "steps.place_design.args.directive" "RuntimeOptimized" [get_runs impl_1] +# set_property "steps.route_design.args.directive" "RuntimeOptimized" [get_runs impl_1] +# # Set strategy +set_property STRATEGY $::env(IMPL_STRATEGY) [get_runs impl_1] +# # Enable physical optimizations (longer runtime) +# set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] +# set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] + +# Run +launch_runs impl_1 -to_step write_bitstream +wait_on_run impl_1 +# Open implemented design +open_run impl_1 + +# Generate reports +check_timing -file $report_dir/$::env(XILINX_PROJECT_NAME).post_impl.check_timing.rpt +report_timing -max_paths 100 -nworst 100 -delay_type max -sort_by slack -file $report_dir/$::env(XILINX_PROJECT_NAME).post_impl.timing_WORST_100.rpt +report_timing -nworst 1 -delay_type max -sort_by group -file $report_dir/$::env(XILINX_PROJECT_NAME).post_impl.timing.rpt +report_utilization -hierarchical -hierarchical_percentage -file $report_dir/$::env(XILINX_PROJECT_NAME).post_impl.utilization.rpt +report_timing_summary -file $report_dir/$::env(XILINX_PROJECT_NAME).post_impl.timing_summary.rpt + +# Print info +puts " \[REPORT\] prj [current_project] + \[REPORT\] strategy [get_property STRATEGY [get_runs]] + \[REPORT\] status [get_property status [get_runs]] + \[REPORT\] elapsed [get_property stats.elapsed [get_runs]] + \[REPORT\] wns [get_property stats.wns [get_runs impl_1]] + \[REPORT\] whs [get_property stats.whs [get_runs impl_1]] +" diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/jtag2axi_read.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/jtag2axi_read.tcl new file mode 100644 index 0000000000000000000000000000000000000000..8965b2557b638b276adda8388178fcbd24a60ecc --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/jtag2axi_read.tcl @@ -0,0 +1,84 @@ +# Author: Vincenzo Maisto +# Description: tcl script used to read back from AXI +# Input args: +# -argv0: base address +# -argv1: number of transactions + +######### +# Utils # +######### + +# Utility function to read binary file +proc read_file_to_words {filename fsize} { + # Open file + set fp [open $filename r] + + # Translate file to binary + fconfigure $fp -translation binary + + # Read data + set file_data [read $fp $fsize] + + # Close file + close $fp + + # Return + return $file_data +} + +############## +# Parse args # +############## +puts "Usage " +puts "base_address : base address" +puts "num_bytes : number of bytes" +if { $argc != 2 } { + # Default + set base_address 0x0000 + set num_bytes 16 +} else { + set base_address [lindex $argv 0] + set num_bytes [lindex $argv 1] +} + +######## +# Init # +######## + +# Disable message limit +set_msg_config -id {Labtoolstcl 44-481} -limit 99999 + +# Connects to hw_server and sets variable hw_device +source $::env(XILINX_SYNTH_TCL_ROOT)/open_hw_manager.tcl + +# AXI transaction names +set gpio_wr_txn gpio_wr_txn +set gpio_rd_txn gpio_rd_txn + +# Bytes per burst +set burst_size 4 +# Number of $burst_size-bytes transaction +set num_bursts [expr {int( $num_bytes / $burst_size)}] + +######################### +# Read-back from memory # +######################### + +for {set i 0} {$i < $num_bursts} {incr i} { + # Compose address + set address [format 0x%x [expr {$base_address + $i * $burst_size}]] + + # Debug + puts "Reading from address $address" + + # Create and run transaction + create_hw_axi_txn $gpio_rd_txn [get_hw_axis hw_axi_1] -type read -force -address $address + run_hw_axi [get_hw_axi_txns $gpio_rd_txn] + +} + +############ +# Clean up # +############ +# Restore message limit +reset_msg_config -id {Labtoolstcl 44-481} -limit \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/mark_debug_nets.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/mark_debug_nets.tcl new file mode 100644 index 0000000000000000000000000000000000000000..0cfd668dd66c1e1828be0eefd8aca421383579d1 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/mark_debug_nets.tcl @@ -0,0 +1,5 @@ +# Author: Vincenzo Maisto +# Description: Mark nets in the post-syntesis netlist for debug + +# System master AXI interface +set_property MARK_DEBUG 1 [get_nets sys_master_u/m_axi_*] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/package_ip.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/package_ip.tcl new file mode 100644 index 0000000000000000000000000000000000000000..66c780338dfd05cbe4510fc0c073ed6eca115722 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/package_ip.tcl @@ -0,0 +1,25 @@ +# Author: Stefano Mercogliano +# Description: Package Vivado IP from $src_file_list over $top_module, from an opened project +# Input args: +# None + +# Add files to project +import_files -norecurse -fileset [current_fileset] $src_file_list +update_compile_order -fileset sources_1 +set_property top ${top_module} [current_fileset] + +# Suppress: WARNING: [IP_Flow 19-3833] Unreferenced file from the top module is not packaged: <...>. +set_msg_config -id {[IP_Flow 19-3833]} -suppress + +# Package the IP and update the catalog +ipx::package_project -root_dir $::env(IP_DIR)/build/$::env(IP_PRJ_NAME).srcs/sources_1/imports -vendor user.org -library user -taxonomy /UserIP +set_property name $::env(IP_PRJ_NAME) [ipx::current_core] +set_property core_revision 2 [ipx::current_core] +ipx::update_checksums [ipx::current_core] +ipx::check_integrity [ipx::current_core] +ipx::save_core [ipx::current_core] +set_property ip_repo_paths $::env(IP_DIR)/build/$::env(IP_PRJ_NAME).srcs/sources_1/imports [current_project] +update_ip_catalog + +# Import IP into the project +create_ip -vlnv user.org:user:$::env(IP_PRJ_NAME):1.0 -module_name $::env(IP_NAME) diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/suppress_messages.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/suppress_messages.tcl new file mode 100644 index 0000000000000000000000000000000000000000..f03c91992353717fb6c8478dd0be0acc9e5a35a2 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/suppress_messages.tcl @@ -0,0 +1,13 @@ +# Author: Vincenzo Maisto +# Description: Suppress or change severity of Vivado messages +# Input args: +# None + +# The IP file <...> has been moved from its original location, as a result the outputs for this IP will now be generated in <...>. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands. +set_msg_config -id {[Vivado 12-13650]} -suppress + +# INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170] +set_msg_config -id {[Synth 8-11241]} -suppress + +# WARNING: [Board 49-26] cannot add Board Part<...> available at /data/xhub/boards/XilinxBoardStore/boards<...> as part <...> specified in board_part file is either invalid or not available +# set_msg_config -id {[Board 49-26]} -suppress diff --git a/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/verilog_defines.tcl b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/verilog_defines.tcl new file mode 100644 index 0000000000000000000000000000000000000000..d248959271f13d42cf6791af9ae0fa6464ea284b --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/hw/xilinx/synth/tcl/verilog_defines.tcl @@ -0,0 +1,43 @@ +# Author: Vincenzo Maisto +# Description: Define Verilog macros for build environment, in an opened project +# Input args: +# None + +# Prepare list +set verilog_defines "" + +# HPC/EMBEDDED +if { "$::env(SOC_CONFIG)" == "hpc" } { + lappend verilog_defines HPC=1 +} elseif { "$::env(SOC_CONFIG)" == "embedded" } { + lappend verilog_defines EMBEDDED=1 +} else { + puts "Unsupported board $::env(SOC_CONFIG)" + exit 1 +} + +# AXI config +lappend verilog_defines MBUS_DATA_WIDTH=$::env(MBUS_DATA_WIDTH) +lappend verilog_defines MBUS_ADDR_WIDTH=$::env(MBUS_ADDR_WIDTH) +lappend verilog_defines MBUS_ID_WIDTH=$::env(MBUS_ID_WIDTH) +lappend verilog_defines MBUS_NUM_SI=$::env(MBUS_NUM_SI) +lappend verilog_defines MBUS_NUM_MI=$::env(MBUS_NUM_MI) +lappend verilog_defines PBUS_NUM_MI=$::env(PBUS_NUM_MI) +lappend verilog_defines PBUS_ID_WIDTH=$::env(MBUS_ID_WIDTH) +lappend verilog_defines HBUS_NUM_MI=$::env(HBUS_NUM_MI) +lappend verilog_defines HBUS_NUM_SI=$::env(HBUS_NUM_SI) +lappend verilog_defines HBUS_ID_WIDTH=$::env(MBUS_ID_WIDTH) +# Core selection +lappend verilog_defines CORE_SELECTOR=$::env(CORE_SELECTOR) +# Clock domains +lappend verilog_defines MAIN_CLOCK_FREQ_MHZ=$::env(MAIN_CLOCK_FREQ_MHZ) +set clock_domain_list [split $::env(RANGE_CLOCK_DOMAINS) " "] +foreach clock_domain $clock_domain_list { + lappend verilog_defines $clock_domain=$clock_domain +} + +# Info +puts "\[INFO\] Verilog defines: $verilog_defines" + +# Set property to list +set_property verilog_define $verilog_defines [current_fileset] diff --git a/snapshots/HiSA-Team_Simply-V_pr166/sw/.gitignore b/snapshots/HiSA-Team_Simply-V_pr166/sw/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7e3f87b485d4decd78d5cd3e5579127b6c2631e8 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/sw/.gitignore @@ -0,0 +1,7 @@ +# Software build outputs +*.elf +*.bin +*.dump +*.o +*.so +*.a diff --git a/snapshots/HiSA-Team_Simply-V_pr166/sw/Makefile b/snapshots/HiSA-Team_Simply-V_pr166/sw/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..3546f93ea8c3cef73840f63639e9230a600cc39c --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/sw/Makefile @@ -0,0 +1,28 @@ +# Author: Vincenzo Maisto +# Description: +# Top Makefile for the software flow. It just redirects to sub-folders' Makefiles. + +# Environment check +ifndef SW_ROOT +$(error Setup script settings.sh has not been sourced, aborting) +endif + + +all: host SoC + +VIRTUAL_UART_PATH = ${SW_HOST_ROOT}/virtual_uart +host: +# Virtual UART is the only host application so far + make -C ${VIRTUAL_UART_PATH} + +SoC: +# Init and checkout tinyIO + git submodule update --init SoC/lib/tinyio +# Build SoC sw + make -C ${SW_SOC_ROOT} + +clean: + make -C ${VIRTUAL_UART_PATH} clean + make -C ${SW_SOC_ROOT} clean + +.PHONY: host SoC \ No newline at end of file diff --git a/snapshots/HiSA-Team_Simply-V_pr166/sw/README.md b/snapshots/HiSA-Team_Simply-V_pr166/sw/README.md new file mode 100644 index 0000000000000000000000000000000000000000..beb0c1b3941596be4274f18acb0bc9b21792dd68 --- /dev/null +++ b/snapshots/HiSA-Team_Simply-V_pr166/sw/README.md @@ -0,0 +1,11 @@ +# Software for UninaSoC +The sw directory is organized in two major components: +* `host/` - Contains software that runs on the host side, typically x86-based systems. This includes host applications to interface with UninaSoC. Currently, it only applies to HPC configurations, see [host/virtual_uart/README.md](host/virtual_uart/README.md), +* `SoC/` - Contains software for UninaSoC, see [SoC/README.md](SoC/README.md), + +## Installation Instructions + + +Additional installation-related technical documentation can be found in the `doc/` folder for: +* [RISC-V GCC installation](doc/GCC_INSTALLATION.md). +* [RISC-V OpenOCD installation](doc/OPENOCD_INSTALLATION.md). diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/build_tests_matrix.py b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/build_tests_matrix.py new file mode 100644 index 0000000000000000000000000000000000000000..c33ece199a0b6633d0416d202f605f59e844bb46 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/build_tests_matrix.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import os +import yaml + +def main(): + + # Load and parse YAML description + file_name = "src/integration/stimulus/L0_regression.yml" + with open(file_name, "r") as fp: + yaml_root = yaml.safe_load(fp) + + # Get excluded test list + excluded = os.environ.get("EXCLUDE_TESTS", "") + excluded = [s.strip() for s in excluded.strip().split(",")] + + # Get test list + content = yaml_root["contents"][0] + tests = content["tests"] + paths = tests["paths"] + + # Extract test names from paths + test_list = [] + for path in paths: + parts = path.split("/") + + for i, part in enumerate(parts): + if part == "test_suites" and i + 1 < len(parts): + test_name = parts[i+1] + if test_name not in excluded: + test_list.append(test_name) + break + + # Output names + print(test_list) + +if __name__ == "__main__": + main() diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/file_hash.sh b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/file_hash.sh new file mode 100644 index 0000000000000000000000000000000000000000..18170bfe671b59a8f6f17cfbf391423033b65a21 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/file_hash.sh @@ -0,0 +1,67 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# DESCRIPTION: +# ==================================== +# This tool is used to generate a hash over the Adamsbridge source code files +# This can be used to verify the hash of the code for which internal workflows were +# run prior to submission to the adams-bridge repo. +# +# Usage: file_hash.sh +# path_to_rtl_src_dir Path to the root directory of the adamsbridge RTL repo. +# file_list This list of all the files that should be included in the hash +# is generated +# +# Exit and report failure if anything fails +set -euo pipefail + +# Check arg count +if [ $# -ne 2 ] + then + echo "Usage: $(basename $0) " + exit -1 +fi + +# Get args +rtl_path=$1 + +# Read expected file list, prepend rtl path, and store in array +IFS=$'\n' expected_file_list=($(cat "$2" | sed "s@^@""$rtl_path""/@")) + +# Make sure all files exist +missing_files=0 +for file in "${expected_file_list[@]}" +do + # Check if the file is missing + if ! test -f "$file"; then + # Report any missing files (and keep count) + if [ "$missing_files" -eq 0 ]; then + echo "Missing expected files: " + fi + missing_files=$(($missing_files + 1)) + echo " $file" + fi +done + +# Calculate the hash (only if no files were missing) +if [ "$missing_files" -eq 0 ]; then + hash=$(cat "${expected_file_list[@]}" | sha384sum | tr -d "\n *-") + echo "$hash" +else + echo "Failed to generate code hash" + exit -1 +fi + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/license_header_check.sh b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/license_header_check.sh new file mode 100644 index 0000000000000000000000000000000000000000..90995c4a287d1218d362c2289ecf0f02af115e78 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/license_header_check.sh @@ -0,0 +1,95 @@ +#!/usr/bin/env bash +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +function show_usage() { + printf "Usage: $0 [optional [parameters]]\n" + printf "\n" + printf "Options:\n" + printf " -i|--insertHeader\tInsert license header in files missing it (Currently unavailable) \n" + printf " -h|--help\tShow usage information\n" + + return 0 +} + +set -euo pipefail + +apacheLicenseHeader="# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the \"License\"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an \"AS IS\" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License." + +apacheLicenseHeader_v_c="//******************************************************************************** +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2020 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the \"License\"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an \"AS IS\" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//********************************************************************************" + +while [[ ! -z "${1:+empty}" ]]; do + if [[ "$1" == "--help" ]] || [[ "$1" == "-h" ]]; then + show_usage + #elif [[ "$1" == "-i" ]] || [[ "$1" == "--insertHeader"]]; then + # insHeader=1 + # shift + fi + shift +done + +if [[ -z ${ADAMSBRIDGE_ROOT:+"empty"} ]]; then + echo "Must set ADAMSBRIDGE_ROOT prior to running script" + exit 1 +fi + +exclude_dir='{uvmf*,.git,cmark,__pycache__,templates,docs}' +exclude_suffix='*.{tcl,txt,js,htm,html,json,vf,yml,woff,rsp,rdl,bashrc,waiver,cfg,hex,rc,exe,pdf,png,hvp,svg,log}' +exclude_regs='*_reg*.{sv,rdl}' +exclude_csr='*_csr*.*' +exclude_file='{sglint_waivers,pr_hash,pr_timestamp,.git-comodules,.gitignore,spyglass_lint.policy,ascent.ctl,clp_mapfile,readme.md,README.md,SECURITY.md,c_sample.c}' +apache_patn='Licensed under the Apache License' + +# Recursive find through repository with some major exclusions +# 'eval' is used to expand exclude vars into a usable glob pattern +files_missing_header=$(eval grep -r -L -i --exclude-dir=${exclude_dir} --exclude=${exclude_suffix} --exclude=${exclude_regs} --exclude=${exclude_csr} --exclude=${exclude_file} \"${apache_patn}\" "${ADAMSBRIDGE_ROOT}") + +if [[ $files_missing_header != "" ]]; then + echo -e "\n\n\tPlease add Apache license header to the following files and try again. \n" + for file in $files_missing_header; do + echo -e "\t\e[1;31m $file \e[0m\n" + done + exit 1 +fi +echo "Apache license header check completed successfully" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/pr_rdl_check.sh b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/pr_rdl_check.sh new file mode 100644 index 0000000000000000000000000000000000000000..5d8169cf3a8ab7f1dbb5026f58abd4ff5b3490b1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/pr_rdl_check.sh @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +set -euo pipefail + +if [[ $# -ne 1 ]]; then + echo "Error, requires branch name argument" + exit 1 +else + merge_dest=$1 +fi + +if ! git show-ref --quiet "${merge_dest}"; then + echo "Could not find ref named [${merge_dest}]" + exit 1 +else + echo "Evaluating RDL modifications for merge into [${merge_dest}] with ref [$(git show-ref "${merge_dest}")]" +fi + +if [[ -z "${ADAMSBRIDGE_ROOT:+"empty"}" ]]; then + echo "Error, must set ADAMSBRIDGE_ROOT" + exit 1 +fi +cd "${ADAMSBRIDGE_ROOT}" + +# Find all RTL files that are generated from RDL +declare -a gen_rtl_list +for rdl_file in $(find "${ADAMSBRIDGE_ROOT}/src" -name "*.rdl"); do + rtl_file=$(sed 's,\.rdl,.sv,' <<< $(basename $rdl_file)); + if [[ $(find $(dirname $(dirname $rdl_file)) -name "$rtl_file" | wc -l) -eq 1 ]]; then + gen_rtl_list+=("${rtl_file}") + else + echo "Did not find any file named [$rtl_file] that would be generated from [$rdl_file]"; + fi; +done +patn=$(echo "${gen_rtl_list[@]}" | sed 's, ,\\\|,g') + +# Find file modifications +rdl_mod_count=$(git diff --merge-base "${merge_dest}" --name-only | grep -c -e '\.rdl$\|tools\/templates\/rdl\|reg_gen.sh\|reg_gen.py\|reg_doc_gen.sh\|reg_doc_gen.py' -e "${patn}" || exit 0) +if [[ "${rdl_mod_count}" -gt 0 ]]; then + # Run the HTML Doc generator script (to update the REG macro header files) + # and the individual reg generator script but then remove the docs directories + bash "${ADAMSBRIDGE_ROOT}/tools/scripts/reg_gen.sh" + + # Check for any file changes + if [[ $(git status -s --untracked-files=all --ignored=traditional -- "${ADAMSBRIDGE_ROOT}/src/" | wc -l) -gt 0 ]]; then + echo "Regenerating reg RDL outputs produced some file changes:"; + git status -s --untracked-files=all --ignored=traditional; + git diff; + echo "*****************************************"; + echo "Review above changes locally and resubmit pipeline"; + echo "(Hint: Check ${ADAMSBRIDGE_ROOT} for the above changes)"; + echo "*****************************************"; + exit 1; + fi +else + echo "skipping RDL check since no RDL files were modified" +fi diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/stamp_repo.sh b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/stamp_repo.sh new file mode 100644 index 0000000000000000000000000000000000000000..70871aa5603834ecfcce43f9a7b783dafc2c387a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/stamp_repo.sh @@ -0,0 +1,75 @@ +#!/usr/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# ENV Check +if [[ -z "${ADAMSBRIDGE_ROOT:+"empty"}" ]]; then + echo "Error, must set ADAMSBRIDGE_ROOT" + exit 1 +fi + +# Create file list +find "$ADAMSBRIDGE_ROOT" -type f -name "*.sv" \ + -o -name "*.svh" \ + -o -name "*.rdl" \ + -o -name "*.json" \ + -o -name "*.v" \ + -o -name "*.vh" \ + -o -name "*.rsp" \ + -o -name "*.s" \ + -o -name "*.c" \ + -o -name "*.cpp" \ + -o -name "*.h" \ + -o -name "*.hex" \ + -o -name "*.ld" \ + -o -name "*.gdb" \ + -o -name "*.yml" \ + -o -name "*.sh" \ + -o -name "*.py" \ + -o -name "pr_timestamp" \ + ! -path "*.git/*" | LC_COLLATE=C sort -o $ADAMSBRIDGE_ROOT/.github/workflow_metadata/file_list.txt +sed -i "s,^$ADAMSBRIDGE_ROOT/,," $ADAMSBRIDGE_ROOT/.github/workflow_metadata/file_list.txt +echo "Found $(wc -l $ADAMSBRIDGE_ROOT/.github/workflow_metadata/file_list.txt) source code files to hash" +echo -e "First five files:\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>" +head -5 $ADAMSBRIDGE_ROOT/.github/workflow_metadata/file_list.txt +echo -e ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>" + +# Create timestamp +if [[ ! -f $ADAMSBRIDGE_ROOT/.github/workflow_metadata/pr_timestamp ]]; then + echo "Error, file not found: $ADAMSBRIDGE_ROOT/.github/workflow_metadata/pr_timestamp" + exit 1 +fi +timestamp=$(date +%s) +echo "Submitting timestamp [${timestamp}]" +echo -n ${timestamp} > $ADAMSBRIDGE_ROOT/.github/workflow_metadata/pr_timestamp + +# Create hash +hash=$($ADAMSBRIDGE_ROOT/.github/scripts/file_hash.sh $ADAMSBRIDGE_ROOT $ADAMSBRIDGE_ROOT/.github/workflow_metadata/file_list.txt) +if [[ -z ${hash:+"empty"} ]]; then + echo "Failed to run hash script" + echo $hash + exit 1; +fi +echo "RTL hash is $hash" +if [[ ! -f $ADAMSBRIDGE_ROOT/.github/workflow_metadata/pr_hash ]]; then + echo "Error, file not found: $ADAMSBRIDGE_ROOT/.github/workflow_metadata/pr_hash" + exit 1 +fi +echo "Submitting hash [${hash}]" +echo -n ${hash} > $ADAMSBRIDGE_ROOT/.github/workflow_metadata/pr_hash + +# Clean up +rm $ADAMSBRIDGE_ROOT/.github/workflow_metadata/file_list.txt diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/utils.sh b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/utils.sh new file mode 100644 index 0000000000000000000000000000000000000000..24bd83242756ff4ea679f4546cbfa721fd3451cc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/scripts/utils.sh @@ -0,0 +1,63 @@ +#!/bin/bash +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# Colors +COLOR_OFF='\033[0m' +COLOR_RED='\033[31m' +COLOR_GREEN='\033[32m' +COLOR_WHITE='\033[1;37m' + +# Waits until the given phrase appears in a log file (actively written to) +# Usage: wait_for_phrase +wait_for_phrase () { + + # Check if the log exists + sleep 1s + if ! [ -f "$1" ]; then + echo -e "${COLOR_RED}Log file '$1' not found!${COLOR_OFF}" + return -1 + fi + + # Wait for the phrase + DEADLINE=$((${EPOCHSECONDS} + 30)) + while [ ${EPOCHSECONDS} -lt ${DEADLINE} ] + do + # Check for the phrase + grep "$2" "$1" >/dev/null + if [ $? -eq 0 ]; then + return 0 + fi + + # Sleep and retry + sleep 1s + done + + # Timeout + return -1 +} + +# Terminates a process. First via SIGINT and if this doesn't work after 10s +# retries with SIGKILL +# Usage: terminate +terminate () { + + local PID=$1 + + # Gently interrupt, wait some time and then kill + /bin/kill -s SIGINT ${PID} || true + sleep 10s + /bin/kill -s SIGKILL ${PID} || true +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/README.md b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/README.md new file mode 100644 index 0000000000000000000000000000000000000000..a17cc47b1b7a0d33bd0ea0b59d862627503e56f0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/README.md @@ -0,0 +1,21 @@ +Files in this directory are used to support workflow checks that run on the adams-bridge repository using GitHub actions. + +pr\_\* objects are used to validate a Pull Request run. This is in support of an honor based system that allows contributors to create internal pipelines (for example, to run tests with proprietary toolchains). The suggested procedure here is: + 1. Contributor develops a new feature and pushes a branch to the adams-bridge GitHub repository + 1. Contributor runs an internal workflow on a branch that contains the merge of the feature branch into main. This workflow includes the complete test-suite and (possibly) some additional checks required by the company policy of that contributor + - All contributors MUST perform the following checks in their development pipeline: + - VCS test of the complete L0 regression suite (smoke tests) + - Lint check run against adamsbridge_top + 1. Upon successfully completing, the internal workflow runs the script [stamp_repo.sh](../scripts/stamp_repo.sh). This script: + - Updates the pr\_timestamp file to the current date + - Runs the hash script [file_hash.sh](../scripts/file_hash.sh) to measure the code that the workflow ran on (including the pr\_timestamp file) + - Writes the hash to the pr\_hash file + 1. The internal workflow should commit the updates to pr\_timestamp and pr\_hash as the final commit to the feature branch + - ⚠️ IMPORTANT! The workflow should be run upon a branch containing the MERGE of the feature branch into main, and this merge branch should be used to calculate the file hash. But the updated stamp files should be committed directly to the feature branch. + 1. Contributor creates a Pull Request to submit the feature branch to the GitHub `main` branch + 1. Pull Request triggers GitHub Actions to run + - Check on the timestamp. If the timestamp is sufficiently outdated (predates the final commit to the branch by more than 1 hour) the feature branch is considered to have failed the internal workflow + - Pull Request runs a hash on the branch fileset (including the timestamp), compares with the contents of pr\_hash. If the hash mismatches, the feature branch is considered to have failed the internal workflow + 1. Pull Request is allowed to be merged only once all Actions complete successfully + +The Pull Request run ignores updates to documentation files. That is, commits containing only markdown (.md) or image (.png) files are not required to pass the timestamp/hash check. diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/pr_hash b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/pr_hash new file mode 100644 index 0000000000000000000000000000000000000000..2e587ef7764cdf9a90135a6246d49c35a46e809e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/pr_hash @@ -0,0 +1 @@ +a595024ac6beff7fb06896cffc8e64daa085dd8ac831b8f4f97a6f835e1de1a4442910cc62cc8a5e35e3fe24246c409c \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/pr_timestamp b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/pr_timestamp new file mode 100644 index 0000000000000000000000000000000000000000..0e08115f6d39f48e5b583fc46c50d31a77b62b70 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflow_metadata/pr_timestamp @@ -0,0 +1 @@ +1737666013 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/workflows/pre-run-check.yml b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflows/pre-run-check.yml new file mode 100644 index 0000000000000000000000000000000000000000..ce2209c874c9cb6b01fab0834713aa3a0354caf2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflows/pre-run-check.yml @@ -0,0 +1,204 @@ +# docs: https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions + +# This workflow implements a check that allows integrators to enforce +# successful completion of testcases that should have been performed +# on internal environments against the code base in the submitted branch. +# For example, this allows internal pipelines to run proprietary toolchains +# to sign-off on the code before allowing GitHub workflows to start. +name: Pre Run Check + +on: + workflow_dispatch: + inputs: + base_ref: + description: "Manual override for target branch to perform merge comparisons" + required: true + type: string + default: 'main' + workflow_call: + +env: + MSFT_ACTORS: ( "Nitsirks" "calebofearth" "mojtaba-bisheh" "anjpar" "upadhyayulakiran" "nileshbpat" "ekarabu" ) + +jobs: + # Fail if any compile.yml has been modified + # (Microsoft employees use these to run an internal tool) + # Don't run this job for manual runs + compile_yml_check: + name: compile.yml Check + runs-on: ubuntu-22.04 + if: ${{ github.event_name == 'pull_request' }} + steps: + - name: Checkout RTL repo + uses: actions/checkout@v4 + with: + fetch-depth: 0 + - name: Compare against target + env: + PR_OPENER: ${{ github.event.pull_request.user.login }} + SOURCE_BR: ${{ github.event.pull_request.head.ref }} + SOURCE_FORK: ${{ github.event.pull_request.head.repo.fork }} + SOURCE_OWN: ${{ github.event.pull_request.head.repo.owner.login }} + SOURCE_URL: ${{ github.event.pull_request.head.repo.clone_url }} + TARGET_BR: ${{ github.event.pull_request.base.ref }} + run: | + echo "Comparing $SOURCE_OWN/$SOURCE_BR against merge target origin/$TARGET_BR to look for compile.yml" + local_msft_actors=${{ env.MSFT_ACTORS }} + for msft_actor in "${local_msft_actors[@]}"; do + if [[ "${PR_OPENER}" == "${msft_actor}" ]]; then + echo "Skipping check on compile.yml modifications for detected Microsoft contributor: ${msft_actor}" + exit 0 + fi + done + if [[ "${SOURCE_FORK}" == "true" ]]; then + echo "pull request is from a fork: ${SOURCE_FORK}" + echo "fork repository owner is ${SOURCE_OWN}" + echo "adding remote '${SOURCE_OWN}' at url '${SOURCE_URL}'" + git remote add -f ${SOURCE_OWN} ${SOURCE_URL} + fi + echo "target ref is $(git show-ref origin/${TARGET_BR} 2> /dev/null)" + echo "source ref is $(git show-ref ${SOURCE_OWN}/${SOURCE_BR} 2> /dev/null)" + compiles=$(git diff --name-only $(git show-ref --hash "origin/$TARGET_BR")...$(git show-ref --hash "${SOURCE_OWN}/${SOURCE_BR}")) + if [[ $(grep -c compile.yml <<< "$compiles") -gt 0 ]]; then + echo "compile.yml should not be modified for pull requests! Found:" + echo "$compiles" + exit 1 + else + echo "Found no modifications to compile.yml" + fi + + # Build the comparison hash file + hash_check: + name: Hash Check + runs-on: ubuntu-22.04 + steps: + - name: Checkout RTL repo + uses: actions/checkout@v4 + with: + fetch-depth: 0 + + - name: Gen File List + run: | + find "$GITHUB_WORKSPACE" -type f -name "*.sv" \ + -o -name "*.svh" \ + -o -name "*.rdl" \ + -o -name "*.json" \ + -o -name "*.v" \ + -o -name "*.vh" \ + -o -name "*.rsp" \ + -o -name "*.s" \ + -o -name "*.c" \ + -o -name "*.cpp" \ + -o -name "*.h" \ + -o -name "*.hex" \ + -o -name "*.ld" \ + -o -name "*.gdb" \ + -o -name "*.yml" \ + -o -name "*.sh" \ + -o -name "*.py" \ + -o -name "pr_timestamp" \ + ! -path "*.git/*" | LC_COLLATE=C sort -o $GITHUB_WORKSPACE/.github/workflow_metadata/file_list.txt + sed -i "s,^$GITHUB_WORKSPACE/,," $GITHUB_WORKSPACE/.github/workflow_metadata/file_list.txt + echo "Found $(wc -l $GITHUB_WORKSPACE/.github/workflow_metadata/file_list.txt) source code files to hash" + echo -e "First five files:\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>" + head -5 $GITHUB_WORKSPACE/.github/workflow_metadata/file_list.txt + echo -e ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>" + + - name: Check Timestamp + run: | + # Find the last commit that modified any design file (not documentation) + # Start the search with the second parent of the PR merge commit + # in order to only traverse the feature branch commits + last_commit=$(git rev-parse HEAD^2) + until git diff --name-only "${last_commit}^..${last_commit}" | grep -v '\.md\|\.png' > /dev/null; do + last_commit="$(git rev-parse ${last_commit}^)" + done + echo "Latest non-doc hash is ${last_commit}" + # If the last non-doc commit is already contained in branch 'main', then skip the + # timestamp check -- as that commit would already be signed off through another PR. + # Otherwise, that commit would fail because it's part of a commit that was squashed into main + # much later than the original stamp commit. + if [[ $(git branch --remotes --list 'origin/main' --contains ${last_commit}) =~ 'origin/main' ]]; then + echo "Commit ${last_commit} is contained in branch 'main', skipping timestamp check" + else + # Compare the timestamp from the latest commit with the pr_timestamp file + timestamp_exp=$(bc <<< "$(git log -n1 --pretty=tformat:'%ct' ${last_commit})-3600") + if [[ ! -f $GITHUB_WORKSPACE/.github/workflow_metadata/pr_timestamp ]]; then + echo "Error, file not found: $GITHUB_WORKSPACE/.github/workflow_metadata/pr_timestamp" + exit 1 + fi + timestamp=$(tail -1 $GITHUB_WORKSPACE/.github/workflow_metadata/pr_timestamp) + if [[ ${timestamp} -lt ${timestamp_exp} ]]; then + echo "Error, submitted timestamp [${timestamp}] is outdated: it precedes the latest non-documentation commit to branch by more than an hour [${timestamp_exp}]" + echo "Please rerun any internal/company proprietary testcases, which should invoke .github/scripts/stamp_repo.sh to attest to successful completion" + echo "DO NOT manually run stamp_repo.sh on your branch to bypass this step - the output timestamp/hash is used to verify internal testcase sign-off is successful" + exit 1 + fi + echo "Submitted timestamp [${timestamp}] meets the recency requirement: [${timestamp_exp}]" + fi + + - name: Check Hash + run: | + hash=$($GITHUB_WORKSPACE/.github/scripts/file_hash.sh $GITHUB_WORKSPACE $GITHUB_WORKSPACE/.github/workflow_metadata/file_list.txt) + if [[ -z ${hash:+"empty"} ]]; then + echo "Failed to run hash script" + echo $hash + exit 1; + fi + echo "RTL hash is $hash" + if [[ ! -f $GITHUB_WORKSPACE/.github/workflow_metadata/pr_hash ]]; then + echo "Error, file not found: $GITHUB_WORKSPACE/.github/workflow_metadata/pr_hash" + exit 1 + fi + hash_orig=$(tail -1 $GITHUB_WORKSPACE/.github/workflow_metadata/pr_hash) + if [[ ${hash_orig} != ${hash} ]]; then + echo "Error, submitted hash [${hash_orig}] does not match calculated hash [${hash}]" + echo "If your internal testcase completed successfully and invoked .github/scripts/stamp_repo.sh to generate this hash, please open a support issue on the adams-bridge repository" + exit 1 + fi + echo "Submitted hash [${hash_orig}] matches the calculated hash: [${hash}]" + rm $GITHUB_WORKSPACE/.github/workflow_metadata/file_list.txt + + # Check License Headers + # Check for microsoft employee or that all compile.yml/.vf are untouched + hdr_check: + name: License Header Check + runs-on: ubuntu-22.04 + steps: + - name: Checkout RTL repo + uses: actions/checkout@v4 + + - name: Run Script + run: | + export ADAMSBRIDGE_ROOT=$GITHUB_WORKSPACE + $GITHUB_WORKSPACE/.github/scripts/license_header_check.sh + + # Check RDL files for modifications + rdl_check: + name: RDL File Check + runs-on: ubuntu-22.04 + if: ${{ (github.event_name == 'pull_request' && github.base_ref == 'main') || (github.event_name == 'workflow_dispatch') }} + steps: + - name: Checkout RTL repo + uses: actions/checkout@v4 + with: + fetch-depth: 0 + + - name: Install peakrdl + run: | + python3 -m pip install \ + systemrdl-compiler==1.27.3 \ + peakrdl-systemrdl==0.3.0 \ + peakrdl-regblock==0.21.0 \ + peakrdl-uvm==2.3.0 \ + peakrdl-ipxact==3.4.3 \ + peakrdl-html==2.10.1 \ + peakrdl-cheader==1.0.0 \ + peakrdl==1.1.0 + + - name: Run Script + env: + TARGET_BR: ${{ (github.event_name == 'pull_request' && github.base_ref) || (github.event_name == 'workflow_dispatch' && inputs.base_ref) }} + run: | + export ADAMSBRIDGE_ROOT=$GITHUB_WORKSPACE + $GITHUB_WORKSPACE/.github/scripts/pr_rdl_check.sh "origin/$TARGET_BR" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/.github/workflows/pull_request.yml b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflows/pull_request.yml new file mode 100644 index 0000000000000000000000000000000000000000..79566f992a854e6ae4233e20fd8298efc6b4d427 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/.github/workflows/pull_request.yml @@ -0,0 +1,22 @@ +# docs: https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions + +# This is the top-level workflow to run on all pull-requests, and invokes +# several other workflow dependencies +name: Pull Request + +on: + workflow_dispatch: + pull_request: + +jobs: + # Call auxiliary workflows + pre_run: + uses: ./.github/workflows/pre-run-check.yml + post_run: + name: Call Post Run Final + runs-on: ubuntu-22.04 + needs: [pre_run] + steps: + - name: Checkout RTL repo + uses: actions/checkout@v4 + - run: echo "Finalize" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/config/compilespecs.yml b/snapshots/chipsalliance_adams-bridge_pr82/config/compilespecs.yml new file mode 100644 index 0000000000000000000000000000000000000000..26eaafba857a462a3c10bc3b6371c07e8f69c32d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/config/compilespecs.yml @@ -0,0 +1,26 @@ +name: adams_bridge_lib +files: + # Adams Bridge design + - src/abr_libs/config/compile.yml + - src/abr_prim_generic/config/compile.yml + - src/abr_prim/config/compile.yml + - src/abr_sha3/config/compile.yml + - src/rej_sampler/config/compile.yml + - src/rej_bounded/config/compile.yml + - src/exp_mask/config/compile.yml + - src/sample_in_ball/config/compile.yml + - src/decompose/config/compile.yml + - src/sk_encode/config/compile.yml + - src/sk_decode/config/compile.yml + - src/makehint/config/compile.yml + - src/norm_check/config/compile.yml + - src/sig_encode_z/config/compile.yml + - src/sig_decode_z/config/compile.yml + - src/sigdecode_h/config/compile.yml + - src/pk_decode/config/compile.yml + - src/power2round/config/compile.yml + - src/mldsa_sampler_top/config/compile.yml + - src/ntt_top/config/compile.yml + - src/mldsa_top/config/compile.yml + # UVMF TBs + - src/mldsa_top/uvmf/config/compile.yml diff --git a/snapshots/chipsalliance_adams-bridge_pr82/docs/AdamsBridgeHardwareSpecification.md b/snapshots/chipsalliance_adams-bridge_pr82/docs/AdamsBridgeHardwareSpecification.md new file mode 100644 index 0000000000000000000000000000000000000000..c9e40e97e39e529d25b5aa3fb39c0362cc4cbbfd --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/docs/AdamsBridgeHardwareSpecification.md @@ -0,0 +1,40 @@ +![OCP Logo](./images/OCP_logo.png) + +

Adam's Bridge Hardware Specification

+ +

Version 1.0

+ +
+ +# Scope + +This document defines technical specifications for a Adam's Bridge Post-Quantum Cryptography (PQC ML-DSA) subsystem used in the Open Compute Project (OCP). This document shall comprise the Adam's Bridge technical specification. + +# Overview + +This document provides definitions and requirements for a Adam's Bridge Post-Quantum Cryptography (PQC ML-DSA) subsystem. The document then relates these definitions to existing technologies, enabling device and platform vendors to better understand those technologies in trusted computing terms. + +# Adam's Bridge Core + +## API + +| Name | Input/Output | Operation | Size (Byte) | Start Address | End Address | +|------------------------|----------------|---------------|-------------|---------------|---------------| +| name | Output | All | 8 | 0x00000000 | 0x00000007 | +| version | Output | All | 8 | 0x00000008 | 0x0000000F | +| ctrl | Input | All | 4 | 0x00000010 | 0x00000013 | +| status | Output | All | 4 | 0x00000018 | 0x0000001B | +| IV (SCA) | Input | All | 64 | 0x00000080 | 0x000000BF | +| seed | Input | Keygen | 32 | 0x00000100 | 0x0000011F | +| sign_rnd | Input | Sign | 32 | 0x00000180 | 0x0000019F | +| message | Input | Sign/Verify | 64 | 0x00000200 | 0x0000023F | +| verification result | Output | Verify | 64 | 0x00000280 | 0x000002BF | +| sk_out (software only) | Output | Keygen | 4864 | 0x00000300 | 0x000015FF | +| sk_in | Input | Signing | 4864 | 0x00001600 | 0x000028FF | +| pk | Input/Output | Keygen/Verify | 2592 | 0x00002900 | 0x0000331F | +| signature | Input/Output | Sign/Verify | 4596 | 0x00003400 | 0x000045F3 | +| Interrupt | Output | All | 520 | 0x00004600 | 0x00004807 | +|------------------------|----------------|---------------|-------------|---------------|---------------| +| Total | | | 18440 | 0x00000000 | 0x00004807 | + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/Dilithium_samplers.ipynb b/snapshots/chipsalliance_adams-bridge_pr82/src/Dilithium_samplers.ipynb new file mode 100644 index 0000000000000000000000000000000000000000..01a2d7c68943b70fc3af0085242e899ff7fae7e6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/Dilithium_samplers.ipynb @@ -0,0 +1,463 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +{ + "cells": [ + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "# Dilithium Samplers Reference Implementation" + ] + }, + { + "cell_type": "code", + "execution_count": 1, + "metadata": {}, + "outputs": [], + "source": [ + "import os\n", + "import binascii" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### Parameters" + ] + }, + { + "cell_type": "code", + "execution_count": 2, + "metadata": {}, + "outputs": [], + "source": [ + "DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1\n", + "DILITHIUM_N = 256\n", + "DILITHIUM_LOGN = 8\n", + "DILITHIUM_ROOT_OF_UNITY = 1753\n", + "\n", + "## Category 5 parameters:\n", + "DILITHIUM_ETA = 2\n", + "DILITHIUM_ETA_BOUND = 15\n", + "DILITHIUM_TAU = 60\n", + "DILITHIUM_GAMMA1 = 2**19" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### SHAKE" + ] + }, + { + "cell_type": "code", + "execution_count": 3, + "metadata": {}, + "outputs": [], + "source": [ + "from hashlib import shake_128, shake_256\n", + "\n", + "class Shake():\n", + " def __init__(self, algorithm, block_length):\n", + " self.algorithm = algorithm\n", + " self.block_length = block_length\n", + " self.read_blocks = 0\n", + " self.read_data = b\"\"\n", + " \n", + " def absorb(self, input_bytes):\n", + " self.read_blocks = 0\n", + " self.read_data = b\"\"\n", + " self.xof = self.algorithm(input_bytes)\n", + " \n", + " def digest(self, input_bytes, length):\n", + " return self.algorithm(input_bytes).digest(length)\n", + " \n", + " def get_n_blocks(self, n):\n", + " byte_count = self.block_length * (self.read_blocks + n)\n", + " xof_data = self.xof.digest(byte_count)\n", + " self.read_blocks += n\n", + " self.read_data = xof_data[-self.block_length*n:]\n", + " \n", + " def read(self, n):\n", + " if n > len(self.read_data):\n", + " self.get_n_blocks(5*n)\n", + " send = self.read_data[:n]\n", + " self.read_data = self.read_data[n:]\n", + " return send\n", + "\n", + "Shake128 = Shake(shake_128, 168)\n", + "Shake256 = Shake(shake_256, 136)" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### RejBounded ref model" + ] + }, + { + "cell_type": "code", + "execution_count": 4, + "metadata": {}, + "outputs": [], + "source": [ + "def rejbounded(seed, i):\n", + " global DILITHIUM_Q\n", + " global DILITHIUM_N\n", + " global DILITHIUM_ETA\n", + " global DILITHIUM_ETA_BOUND\n", + " \n", + " def rejection_sample(xof):\n", + " while True:\n", + " js = []\n", + "\n", + " # Consider two values for each byte (top and bottom four bits)\n", + " j = xof.read(1)\n", + " j = int.from_bytes(j, \"little\")\n", + " j0 = j & 0x0F\n", + " j1 = j >> 4\n", + " \n", + " # rejection sample\n", + " if j0 < DILITHIUM_ETA_BOUND:\n", + " if DILITHIUM_ETA == 2: j0 %= 5\n", + " js.append((DILITHIUM_ETA - j0) % DILITHIUM_Q)\n", + " \n", + " if j1 < DILITHIUM_ETA_BOUND:\n", + " if DILITHIUM_ETA == 2: j1 %= 5\n", + " js.append((DILITHIUM_ETA - j1) % DILITHIUM_Q)\n", + " \n", + " if js:\n", + " return js\n", + " \n", + " # Initialise the XOF\n", + " seed = seed + int.to_bytes(i, 2, \"little\")\n", + " Shake256.absorb(seed)\n", + "\n", + " coeffs = []\n", + " while len(coeffs) < DILITHIUM_N:\n", + " js = rejection_sample(Shake256)\n", + " coeffs += js\n", + "\n", + " # Remove the last byte if we ended up overfilling\n", + " if len(coeffs) > DILITHIUM_N:\n", + " coeffs = coeffs[:DILITHIUM_N]\n", + " \n", + " return coeffs" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### Rejection_q ref model" + ] + }, + { + "cell_type": "code", + "execution_count": 5, + "metadata": {}, + "outputs": [], + "source": [ + "def rejection_q(seed, i, j):\n", + " global DILITHIUM_Q\n", + " global DILITHIUM_N\n", + "\n", + " def rejection_sample(xof):\n", + " while True: \n", + " j_bytes = xof.read(3)\n", + " j = int.from_bytes(j_bytes, \"little\")\n", + " j &= 0x7FFFFF\n", + " if j < DILITHIUM_Q:\n", + " return j\n", + "\n", + " # Initialise the XOF\n", + " seed = seed + bytes([j, i])\n", + " Shake128.absorb(seed)\n", + " coeffs = [rejection_sample(Shake128) for _ in range(DILITHIUM_N)]\n", + " return coeffs" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### SampleInBall Ref Model" + ] + }, + { + "cell_type": "code", + "execution_count": 6, + "metadata": {}, + "outputs": [], + "source": [ + "def sample_in_ball(seed):\n", + " global DILITHIUM_Q\n", + " global DILITHIUM_N\n", + " global DILITHIUM_TAU\n", + "\n", + " def rejection_sample(i, xof):\n", + " while True:\n", + " j = xof.read(1)\n", + " j = int.from_bytes(j, \"little\")\n", + " if j <= i: \n", + " return j\n", + " \n", + " # Initialise the XOF\n", + " Shake256.absorb(seed)\n", + " \n", + " # Set the first 8 bytes for the sign, and leave the rest for\n", + " # sampling.\n", + " sign_bytes = Shake256.read(8)\n", + " sign_int = int.from_bytes(sign_bytes, \"little\")\n", + " \n", + " # Set the list of coeffs to be 0\n", + " coeffs = [0 for _ in range(DILITHIUM_N)]\n", + " \n", + " # Now set tau values of coeffs to be ±1\n", + " for i in range(DILITHIUM_N - DILITHIUM_TAU, DILITHIUM_N):\n", + " j = rejection_sample(i, Shake256)\n", + " coeffs[i] = coeffs[j]\n", + " coeffs[j] = (1 - 2*(sign_int & 1)) % DILITHIUM_Q\n", + " sign_int >>= 1\n", + " \n", + " return coeffs" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### Expand_Mask Ref Model" + ] + }, + { + "cell_type": "code", + "execution_count": 7, + "metadata": {}, + "outputs": [], + "source": [ + "def expand_mask(seed, i, kappa): \n", + " global DILITHIUM_Q\n", + " global DILITHIUM_N\n", + " global DILITHIUM_GAMMA1\n", + "\n", + " if DILITHIUM_GAMMA1 == (1 << 17):\n", + " bit_count = 18\n", + " total_bytes = 576 # (256 * 18) / 8\n", + " else:\n", + " bit_count = 20\n", + " total_bytes = 640 # (256 * 20) / 8\n", + " \n", + " # Initialise the XOF\n", + " seed = seed + int.to_bytes(kappa+i, 2, \"little\")\n", + " xof_bytes = Shake256.digest(seed, total_bytes)\n", + " r = int.from_bytes(xof_bytes, 'little')\n", + " mask = (1 << bit_count) - 1\n", + " coeffs = [((DILITHIUM_GAMMA1 - ((r >> bit_count*i) & mask)) % DILITHIUM_Q) for i in range(DILITHIUM_N)]\n", + " \n", + " return coeffs" + ] + }, + { + "cell_type": "markdown", + "metadata": {}, + "source": [ + "### Test" + ] + }, + { + "cell_type": "code", + "execution_count": 8, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + " 0 7FDFFF 7FE000 7FE000 0 7FE000 0 2 0 7FE000 2 7FE000 2 1 7FE000 2\n", + " 1 1 1 0 0 7FE000 1 0 1 2 0 0 1 7FDFFF 2 0\n", + " 0 0 7FE000 1 7FDFFF 2 7FE000 1 0 7FDFFF 2 7FDFFF 7FE000 7FE000 0 1\n", + " 2 7FE000 2 0 1 0 7FDFFF 7FE000 1 7FDFFF 2 7FE000 2 7FDFFF 2 7FE000\n", + " 2 7FE000 7FDFFF 2 7FE000 7FDFFF 2 7FDFFF 2 0 7FDFFF 1 0 2 2 0\n", + " 2 1 1 7FDFFF 7FE000 2 1 7FDFFF 1 2 1 2 1 7FDFFF 7FE000 0\n", + " 1 1 1 1 7FDFFF 0 7FE000 2 1 0 1 2 7FE000 2 7FDFFF 7FE000\n", + " 2 2 0 2 7FE000 2 7FE000 0 0 7FDFFF 0 7FE000 7FDFFF 7FE000 7FE000 1\n", + " 1 7FDFFF 2 1 0 1 2 2 2 7FE000 7FE000 2 7FDFFF 0 0 1\n", + " 2 0 1 7FE000 2 7FDFFF 1 2 2 0 2 1 2 2 7FE000 0\n", + " 2 7FDFFF 1 7FE000 7FDFFF 7FE000 1 0 1 1 7FDFFF 7FDFFF 7FDFFF 7FE000 1 7FDFFF\n", + " 0 2 1 0 7FDFFF 0 1 7FE000 7FDFFF 0 7FE000 1 7FE000 1 2 7FDFFF\n", + " 0 0 1 7FE000 1 2 7FE000 7FE000 7FDFFF 0 1 7FE000 0 7FE000 7FE000 7FE000\n", + "7FE000 7FE000 0 2 0 2 7FE000 2 0 2 2 2 1 7FE000 7FE000 7FE000\n", + " 0 1 2 1 0 2 1 2 7FE000 1 7FDFFF 1 2 0 1 2\n", + "7FDFFF 7FDFFF 0 2 7FDFFF 7FDFFF 2 7FE000 7FE000 0 1 1 0 7FE000 7FE000 7FE000\n" + ] + } + ], + "source": [ + "seed_rnd = os.urandom(64).hex()\n", + "seed_fixed = \"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\"\n", + "seed = binascii.unhexlify(seed_fixed)\n", + "i = 0 # i < k+l = 15\n", + "coeffs = rejbounded(seed, 0)\n", + "\n", + "print(\"\\n\".join(\" \".join(f\"{x:6X}\" for x in coeffs[i:i + 16]) for i in range(0, len(coeffs), 16)))" + ] + }, + { + "cell_type": "code", + "execution_count": 9, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "59DF49 3C9B80 4A0154 6ACCAB 75199A 2D48ED 19D957 729102 9B601 462A78 6D5EC7 10AAA9 2E342E 4D5FC7 556419 39C8B8\n", + "5F75BC 59F799 6A6A16 A1A97 47C0BC 49EF15 529E3D 46698B 11E056 37606B 55A075 32AA95 7A9541 652F69 45A182 2C86C6\n", + "5209F4 3102C5 75DC85 25F1F 245B55 939A4 2D95B 3D4747 46C617 1247F3 77F90D 4A5F3A 505508 99F99 1B517C 12CD3A\n", + "116B7C 4BE2D4 1DBDEA 450D85 48DEF0 420F06 7E2015 612643 250348 1FBF76 4C10A9 6713EA 7FB5D 73D309 138FF4 7038AC\n", + "64351F 5749BA 2D5CDC 4C1A1 597363 7E1C01 53629D 6870C8 52CDA2 72FA23 5FB6AE 4822AD 572105 38F1AF 5A8FA5 1B6112\n", + "690176 742C 3B437A 5947D9 1410BC 77125C 1707BF 7D4168 4CE295 180B07 14E13D 254BAA 2FDFAD 3077B1 50AE3A 244903\n", + "59814B 3B0A15 161B9F 85C13 3DFDA0 4BB71C 666398 712EBD 6C921A 34BC7 6AA929 2C0A2C 1F3480 7FB3DD 55E229 13AC54\n", + "179F34 7EF9D4 7F50C7 36AD97 6CD233 9FA8E 30D973 45591B 5753C7 1588A3 7860FD 5E957E 2C1D79 665EC 79D0BC 264E1D\n", + "543F36 18F808 755A6E 48193A 7EE4F2 50EE91 53F012 303B4A 54C826 101F3D 3F2968 287D64 E2188 CE625 1DED2C 4DAF4D\n", + " 40DF7 60CD8A 78B93 350C7B 53BD2E 66D9A1 196C5E 7B37C7 34771D 6B9D65 702E0B 7AA3DF 4977BD 163AC1 5C9813 363BE9\n", + "3E743A 4B2938 40C73C 630ECC 7892CE 1CF507 129145 52A841 24D11 4EB060 649D59 376A0E 5F909 385849 2D0743 7B4DEE\n", + "2F360F 338CD2 47FBD4 56ECC3 453823 7E8BD1 22C112 7BD400 70AB20 3AC7D5 2A85C 9157B 3F688F 2E40EE 4DC6AC E8766\n", + "5FF4EE 567387 6F0878 3406EE 6DA88C 5A9F3E 1F3256 74BFEF 3A7D54 1718F2 1851A2 13BE01 75BE58 6C4A45 6638E6 5C320C\n", + "4CC3E9 67A4FD 3346F9 2C2F3E 464A5B 11C95C 385454 41C0D0 AF8D8 1F5915 183FF3 5947F0 3ABFA4 7738DD 6E1FE7 70FCA5\n", + "3CD6A7 7C8F76 3821F7 73A11 1ECE92 B3081 153174 64D2EA 6D2757 2C7980 3BB9E0 444986 2FC56F 20F574 32CA93 2C93CC\n", + "51D0CF 1E20D1 1A8FD9 5BCBC5 378CEA 40136D 310189 5307C8 6CF1D0 5F3F42 3E79F8 417737 127341 234421 1078D9 38EE4\n" + ] + } + ], + "source": [ + "seed_rnd = os.urandom(32).hex()\n", + "seed_fixed = \"0000000000000000000000000000000000000000000000000000000000000000\"\n", + "seed = binascii.unhexlify(seed_fixed)\n", + "i = 0 # i < k = 8\n", + "j = 0 # j < l = 7\n", + "coeffs = rejection_q(seed, i, j)\n", + "\n", + "print(\"\\n\".join(\" \".join(f\"{x:6X}\" for x in coeffs[i:i + 16]) for i in range(0, len(coeffs), 16)))" + ] + }, + { + "cell_type": "code", + "execution_count": 10, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + "nonzero_count = 60\n", + " 0 7FE000 0 0 7FE000 1 0 0 0 0 1 1 0 0 0 0\n", + " 0 1 1 0 0 0 0 1 0 7FE000 0 0 0 7FE000 1 0\n", + " 0 0 7FE000 0 0 0 7FE000 0 0 0 0 0 7FE000 0 0 0\n", + "7FE000 0 0 7FE000 0 0 1 7FE000 0 0 0 1 0 0 0 7FE000\n", + " 0 0 0 7FE000 0 0 1 0 1 7FE000 0 0 0 0 1 7FE000\n", + " 1 0 0 0 0 0 1 1 7FE000 0 0 0 0 0 0 0\n", + " 0 0 7FE000 0 1 0 0 0 0 0 0 0 0 0 0 0\n", + " 0 1 7FE000 0 1 0 0 0 0 0 0 0 0 0 0 1\n", + " 0 1 0 0 0 0 0 1 1 0 0 0 0 1 0 0\n", + " 0 0 0 7FE000 1 0 0 7FE000 0 0 0 0 0 1 0 0\n", + " 1 0 0 0 0 0 0 0 0 0 0 0 0 7FE000 0 0\n", + " 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n", + " 0 0 0 7FE000 0 0 0 0 0 0 0 0 0 0 0 0\n", + " 0 0 0 1 0 7FE000 0 0 1 0 0 0 7FE000 0 7FE000 0\n", + " 1 0 0 0 0 7FE000 0 0 0 7FE000 0 0 0 0 7FE000 0\n", + " 0 0 0 0 0 0 0 7FE000 7FE000 7FE000 0 0 0 0 0 0\n" + ] + } + ], + "source": [ + "seed_rnd = os.urandom(32).hex()\n", + "seed_fixed = \"0000000000000000000000000000000000000000000000000000000000000000\"\n", + "seed = binascii.unhexlify(seed_fixed)\n", + "coeffs = sample_in_ball(seed)\n", + "\n", + "nonzero_count = sum(1 for elem in coeffs if elem != 0)\n", + "print(\"nonzero_count =\", nonzero_count)\n", + "\n", + "\n", + "print(\"\\n\".join(\" \".join(f\"{x:6X}\" for x in coeffs[i:i + 16]) for i in range(0, len(coeffs), 16)))" + ] + }, + { + "cell_type": "code", + "execution_count": 11, + "metadata": {}, + "outputs": [ + { + "name": "stdout", + "output_type": "stream", + "text": [ + " 57CB4 786F89 7CD75E 6E0F8 62D3A D5EE 20641 7EE83F 7C5FB6 7A956A 7A8E39 59DF1 7DE4C3 71FCB 7D4CF9 7D4519\n", + "7D641A 7CC5DC 7EC5C3 7C39A6 7C2873 7F164B 7C1E07 7F4F77 7F3901 79632C 7F0175 6F64F 7D3FE5 7DE524 5939 16A2A\n", + " 28F06 788A42 788084 7EF79D 7EC990 7E7718 38EAE 7B9C95 7D7C9E 7AC838 372FA 7F6C9F C273 72F3B 75581 780C30\n", + " 650E9 4A4AE 7B34B6 77F1FB 7BB5E 7C60CE 7F5CDB 7FC2E7 7BC6AE 7C7CCD 26A0E 2B936 427E8 7D3A2F 7A4036 7F1CB3\n", + "79F0EB 1D8D 7C4710 37C3F 73096 7A3CE6 7A01ED 41F44 3010 7FAD97 787F4 7A63C3 2A799 7988BE 6DC23 7AEC0F\n", + " 62FC5 7E61ED 7D37C9 7F481 7D07EC 79B0AB 7CD023 7EEBC9 495B5 7E5330 41EA8 7D468D 1EC25 780E2C 6E435 7ED7A5\n", + " 5E5AA 7D7A9D 78C509 7FAB0C 7C50C2 710AE 5B50C 22481 7900A4 26B35 5595F 33F93 F384 1C93D 56273 793D6A\n", + " 4A094 789899 7BB2E5 7FDD59 7D886A 7E2633 58572 7D5D03 58CB5 2FBC3 701C5 7EC79E 7B6853 2A33 5EE57 52229\n", + "7AABA1 1075 7EFC52 7D713A 3CC4A 785B84 332F 3CD25 35410 7A6066 36A 78CB6B 339AF 3075F 79642D 77EC58\n", + "7B9C02 6E6DE 7C7DF B0C9 55A10 7E7FEC 1ADE5 471B2 59963 518F9 7BAE2A 795116 68EF2 7E9B36 D9B9 358BF\n", + " 55AC4 7C73E9 7D0832 7A4C7D 51780 2F6FC 63CDD 7AC043 7DFF7D 7F67BF 7EE0E4 1F23E 7DE52 5C550 7E09C4 120F3\n", + "7EAAB7 2E8FD 67C64 36513 7800D5 4D79C 7D0B80 7C1FC 7B2C1 7BD166 3CA81 3DD6C 783159 7F3036 4A0B8 51615\n", + " 3156D 70E86 7BFC29 12D4E 21651 7A6ABF 5704D 784B6A EAE8 39BBD 13A0F 779 70A47 74D15 19B44 22DD5\n", + "7E8DBB 19FF7 19654 7BFCFA 7912A2 7B5B41 14C36 7E6D4A 7F5E57 7C6BF7 7F3956 7EB207 290B4 7FD6A3 7BAF2 3C565\n", + "7CC473 7E197F 479E9 7DDFE5 79637 7FAF2E 786731 6FF54 7C0AF2 796EF2 5D229 7D21CD 12863 7FDA25 7A03DB 7C25BB\n", + " 7DAFE 7D8733 7DF3BC A0DF 368F6 783537 360A3 46113 78F179 58DCC 79AC6E 7EFB21 7F6C88 78A9CA 7EE27A 6640A\n" + ] + } + ], + "source": [ + "seed_rnd = os.urandom(64).hex()\n", + "seed_fixed = \"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\"\n", + "seed = binascii.unhexlify(seed_fixed)\n", + "i = 0\n", + "kappa = 0\n", + "coeffs = expand_mask(seed, i, kappa)\n", + "\n", + "print(\"\\n\".join(\" \".join(f\"{x:6X}\" for x in coeffs[i:i + 16]) for i in range(0, len(coeffs), 16)))" + ] + } + ], + "metadata": { + "kernelspec": { + "display_name": "Python 3", + "language": "python", + "name": "python3" + }, + "language_info": { + "codemirror_mode": { + "name": "ipython", + "version": 3 + }, + "file_extension": ".py", + "mimetype": "text/x-python", + "name": "python", + "nbconvert_exporter": "python", + "pygments_lexer": "ipython3", + "version": "3.11.8" + } + }, + "nbformat": 4, + "nbformat_minor": 2 +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/abr_libs.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/abr_libs.vf new file mode 100644 index 0000000000000000000000000000000000000000..91e9713418e5b04bc33d71a3cd96c032f570ff6d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/abr_libs.vf @@ -0,0 +1,33 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..94249642fab504a0e95228ff81819c97b3d6de37 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/compile.yml @@ -0,0 +1,204 @@ +--- +provides: [abr_libs] +schema_version: 2.4.0 +requires: + - mldsa_defines +targets: + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_sva.svh + - $COMPILE_ROOT/rtl/abr_macros.svh + - $COMPILE_ROOT/rtl/abr_1r1w_ram.sv + - $COMPILE_ROOT/rtl/abr_1r1w_be_ram.sv + - $COMPILE_ROOT/rtl/abr_1r1w_512x4_ram.sv + - $COMPILE_ROOT/rtl/abr_ram_regout.sv + - $COMPILE_ROOT/rtl/abr_icg.sv + - $COMPILE_ROOT/rtl/abr_2ff_sync.sv + - $COMPILE_ROOT/rtl/abr_piso_4.sv + - $COMPILE_ROOT/rtl/abr_piso.sv + - $COMPILE_ROOT/rtl/abr_sample_buffer.sv + - $COMPILE_ROOT/rtl/abr_ahb_defines_pkg.sv + - $COMPILE_ROOT/rtl/abr_ahb_slv_sif.sv + - $COMPILE_ROOT/rtl/abr_masked_AND.sv + - $COMPILE_ROOT/rtl/abr_delay_masked_shares.sv + - $COMPILE_ROOT/rtl/abr_masked_add_sub_mod_Boolean.sv + - $COMPILE_ROOT/rtl/abr_masked_MUX.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_sub.sv + - $COMPILE_ROOT/rtl/abr_masked_full_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_A2B_conv.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_B2A_conv.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult_two_share.sv + - $COMPILE_ROOT/rtl/abr_adder.sv + - $COMPILE_ROOT/rtl/abr_add_sub_mod.sv + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_sva.svh + - $COMPILE_ROOT/rtl/abr_macros.svh + - $COMPILE_ROOT/rtl/abr_1r1w_ram.sv + - $COMPILE_ROOT/rtl/abr_1r1w_be_ram.sv + - $COMPILE_ROOT/rtl/abr_1r1w_512x4_ram.sv + - $COMPILE_ROOT/rtl/abr_ram_regout.sv + - $COMPILE_ROOT/rtl/abr_icg.sv + - $COMPILE_ROOT/rtl/abr_2ff_sync.sv + - $COMPILE_ROOT/rtl/abr_piso_4.sv + - $COMPILE_ROOT/rtl/abr_piso.sv + - $COMPILE_ROOT/rtl/abr_sample_buffer.sv + - $COMPILE_ROOT/rtl/abr_ahb_defines_pkg.sv + - $COMPILE_ROOT/rtl/abr_ahb_slv_sif.sv + - $COMPILE_ROOT/rtl/abr_masked_AND.sv + - $COMPILE_ROOT/rtl/abr_delay_masked_shares.sv + - $COMPILE_ROOT/rtl/abr_masked_add_sub_mod_Boolean.sv + - $COMPILE_ROOT/rtl/abr_masked_MUX.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_sub.sv + - $COMPILE_ROOT/rtl/abr_masked_full_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_A2B_conv.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Arith_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_B2A_conv.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult_two_share.sv + - $COMPILE_ROOT/rtl/abr_adder.sv + - $COMPILE_ROOT/rtl/abr_add_sub_mod.sv +--- +provides: [masking_tb] +schema_version: 2.4.0 +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_masked_AND.sv + - $COMPILE_ROOT/rtl/abr_delay_masked_shares.sv + - $COMPILE_ROOT/rtl/abr_masked_add_sub_mod_Boolean.sv + - $COMPILE_ROOT/rtl/abr_masked_MUX.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_sub.sv + - $COMPILE_ROOT/rtl/abr_masked_full_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_A2B_conv.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_Boolean_adder.sv + - $COMPILE_ROOT/rtl/abr_masked_B2A_conv.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult.sv + - $COMPILE_ROOT/rtl/abr_masked_N_bit_mult_two_share.sv + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/abr_masked_A2B_conv_tb.sv + - $COMPILE_ROOT/tb/abr_masked_N_bit_Boolean_adder_tb.sv + - $COMPILE_ROOT/tb/abr_masked_B2A_conv_tb.sv + - $COMPILE_ROOT/tb/abr_masked_N_bit_mult_tb.sv + - $COMPILE_ROOT/tb/abr_masked_N_bit_mult_two_share_tb.sv + + tops: [abr_masked_N_bit_mult_two_share_tb] +--- +provides: [mldsa_uvm_lib] +schema_version: 2.4.0 +targets: + tb: + directories: + - $UVM_HOME/src + - $UVM_HOME/src/dpi + files: + - $UVM_HOME/src/uvm_pkg.sv + tops: [] + dpi_compile: + directories: + - $UVM_HOME/src/dpi + files: + - $UVM_HOME/src/dpi/uvm_dpi.cc + - $UVM_HOME/src/dpi/uvm_regex.cc + options: + - '-Wno-unused-variable' + - '-Wno-unused-function' + - tool: + vcs: + - '-DVCS' + ius: + - '-DXCELIUM' +--- +provides: [mldsa_mvc_lib] +schema_version: 2.4.0 +requires: + - mldsa_uvm_lib +targets: + tb: + directories: + [ + $QUESTA_MVC_HOME/questa_mvc_src/sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb, + $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules, + $QUESTA_MVC_HOME/questa_mvc_src/sv/apb3, + $QUESTA_MVC_HOME/questa_mvc_src/sv/apb3/modules, + ] + files: + [ + $QUESTA_MVC_HOME/include/questa_mvc_svapi.svh, + $QUESTA_MVC_HOME/questa_mvc_src/sv/mvc_pkg.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/apb3/modules/apb5_master.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/apb3/modules/apb_monitor.sv, + $QUESTA_MVC_HOME/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv, + ] + options: + - +define+MAP_PROT_ATTR +--- +provides: [mldsa_uvmf_lib] +schema_version: 2.4.0 +requires: + - mldsa_mvc_lib +targets: + tb: + directories: + [ + $QUESTA_MVC_HOME/questa_mvc_src/sv, + $UVMF_HOME/common/mgc_vip/ahb, + $UVMF_HOME/common/mgc_vip/apb, + $UVMF_HOME/common/modules, + $UVMF_HOME/common/utility_packages/qvip_utils_pkg, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset, + $UVMF_HOME/uvmf_base_pkg, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/uvmf, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/config_policies, + ] + files: + [ + $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.sv, + $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.sv, + $UVMF_HOME/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv, + $UVMF_HOME/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv, + $UVMF_HOME/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv, + $UVMF_HOME/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv, + $UVMF_HOME/common/mgc_vip/ahb/mgc_ahb_signal_if.sv, + $UVMF_HOME/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv, + $UVMF_HOME/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv, + $UVMF_HOME/common/modules/ahb_master.v, + $UVMF_HOME/common/modules/ahb_memory_slave_module_hdl.sv, + $UVMF_HOME/common/modules/ahb_memory_slave_module_hvl.sv, + $UVMF_HOME/common/modules/ahb_memory_slave_module.sv, + $UVMF_HOME/common/modules/ahb_slave.v, + $UVMF_HOME/common/modules/apb3_memory_slave_module.sv, + $UVMF_HOME/common/mgc_vip/apb/apb_master_hdl_wrapper.sv, + $UVMF_HOME/common/mgc_vip/apb/apb_master_hvl_wrapper.sv, + $UVMF_HOME/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv, + $UVMF_HOME/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv, + $UVMF_HOME/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv, + $COMPILE_ROOT/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv, + ] + tops: [] + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/masking_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/masking_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..cbd79ec8782f4958ada593f1069d8c8ca403ff88 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/masking_tb.vf @@ -0,0 +1,18 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl +${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_mvc_lib.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_mvc_lib.vf new file mode 100644 index 0000000000000000000000000000000000000000..a9d638c24bffc743ef71fc3509152140c9d93065 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_mvc_lib.vf @@ -0,0 +1,18 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_uvm_lib.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_uvm_lib.vf new file mode 100644 index 0000000000000000000000000000000000000000..c12fb083e5c848c51474bf70592967cf1f9065ca --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_uvm_lib.vf @@ -0,0 +1,3 @@ ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi +${UVM_HOME}/src/uvm_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_uvmf_lib.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_uvmf_lib.vf new file mode 100644 index 0000000000000000000000000000000000000000..f0aa826f3568fd8f979afe5f8fa31a4075edb5ea --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/config/mldsa_uvmf_lib.vf @@ -0,0 +1,59 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv new file mode 100644 index 0000000000000000000000000000000000000000..9a114aa77b0d5e438fa6d3cacd9b5a791dad6160 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "mldsa_config_defines.svh" + +module abr_1r1w_512x4_ram #( + parameter DEPTH = 512 + ,parameter DATA_WIDTH = 4 + ,parameter ADDR_WIDTH = $clog2(DEPTH) + + ) + ( + input logic clk_i, + + input logic we_i, + input logic [ADDR_WIDTH-1:0] waddr_i, + input logic [DATA_WIDTH-1:0] wdata_i, + input logic re_i, + input logic [ADDR_WIDTH-1:0] raddr_i, + output logic [DATA_WIDTH-1:0] rdata_o + ); + + //storage element +`ifndef RV_FPGA_OPTIMIZE + logic [DEPTH-1:0][DATA_WIDTH-1:0] ram; +`else + (* ram_style = "block" *) logic [DATA_WIDTH-1:0] ram [DEPTH-1:0]; +`endif + + always @(posedge clk_i) begin + if (we_i) begin + ram[waddr_i] <= wdata_i; + end + end + + always @(posedge clk_i) begin + if (re_i) begin + rdata_o <= ram[raddr_i]; + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_be_ram.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_be_ram.sv new file mode 100644 index 0000000000000000000000000000000000000000..129e4b37e878887d1b04c7a66a19c041d6352d3b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_be_ram.sv @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "mldsa_config_defines.svh" +module abr_1r1w_be_ram #( + parameter DEPTH = 64 + ,parameter DATA_WIDTH = 32 + ,parameter STROBE_WIDTH = 8 + ,localparam ADDR_WIDTH = $clog2(DEPTH) + ) + ( + input logic clk_i, + + input logic we_i, + input logic [(DATA_WIDTH/STROBE_WIDTH)-1:0] wstrobe_i, + input logic [ADDR_WIDTH-1:0] waddr_i, + input logic [(DATA_WIDTH/STROBE_WIDTH)-1:0][STROBE_WIDTH-1:0] wdata_i, + input logic re_i, + input logic [ADDR_WIDTH-1:0] raddr_i, + output logic [DATA_WIDTH-1:0] rdata_o + ); + +`ifdef RV_FPGA_OPTIMIZE + + + logic [DATA_WIDTH-1:0] flattened_wdata; + + // Create a flattened version of the wdata_i using always_comb + always_comb begin + flattened_wdata = '0; // Initialize to zero + for (int i = 0; i < (DATA_WIDTH/STROBE_WIDTH); i++) begin + flattened_wdata[i*STROBE_WIDTH +: STROBE_WIDTH] = wdata_i[i]; + end + end + + // Instantiation of the dual-port byte-write RAM + bytewrite_tdp_ram_rf #( + .NUM_COL(DATA_WIDTH / STROBE_WIDTH), // Number of columns (bytes) + .COL_WIDTH(STROBE_WIDTH), // Width of each column (byte width) + .ADDR_WIDTH(ADDR_WIDTH), // Address width + .DATA_WIDTH(DATA_WIDTH), // Data width (total) + .DEPTH(DEPTH) + ) bytewrite_ram_inst ( + .clkA(clk_i), // Clock for Port A (write) + .enaA(we_i), // Enable for Port A (write enable) + .weA(wstrobe_i), // Byte-wise write enable for Port A + .addrA(waddr_i), // Address for Port A (write) + .dinA(flattened_wdata), // Data input for Port A (flattened) + .doutA(), // Data output for Port A (unused in write-only) + + .clkB(clk_i), // Clock for Port B (read) + .enaB(re_i), // Enable for Port B (read enable) + .weB({(DATA_WIDTH/STROBE_WIDTH){1'b0}}), // No write enable for Port B + .addrB(raddr_i), // Address for Port B (read) + .dinB({DATA_WIDTH{1'b0}}), // No data input for Port B + .doutB(rdata_o) // Data output for Port B (read data) + ); + +`else + + //storage element + logic [(DATA_WIDTH/STROBE_WIDTH)-1:0][STROBE_WIDTH-1:0] ram [DEPTH-1:0]; + + always @(posedge clk_i) begin + if (we_i) begin + for (int i = 0; i < (DATA_WIDTH/STROBE_WIDTH); i++) begin + if (wstrobe_i[i]) + ram[waddr_i][i] <= wdata_i[i]; + end + end + end + + always @(posedge clk_i) begin + if (re_i) begin + rdata_o <= ram[raddr_i]; + end + end + + +`endif + + +endmodule + +`ifdef RV_FPGA_OPTIMIZE + +module bytewrite_tdp_ram_rf #( + parameter NUM_COL = 4, // Number of columns (bytes) + parameter COL_WIDTH = 8, // Width of each column (byte) + parameter ADDR_WIDTH = 10, // Address width + parameter DATA_WIDTH = NUM_COL * COL_WIDTH, // Data width (total) + parameter DEPTH = 64 +) ( + input wire clkA, // Clock for Port A + input wire enaA, // Enable for Port A + input wire [NUM_COL-1:0] weA, // Write enable for Port A (byte-wise) + input wire [ADDR_WIDTH-1:0] addrA, // Address for Port A + input wire [DATA_WIDTH-1:0] dinA, // Data input for Port A + output reg [DATA_WIDTH-1:0] doutA, // Data output for Port A + + input wire clkB, // Clock for Port B + input wire enaB, // Enable for Port B + input wire [NUM_COL-1:0] weB, // Write enable for Port B (byte-wise) + input wire [ADDR_WIDTH-1:0] addrB, // Address for Port B + input wire [DATA_WIDTH-1:0] dinB, // Data input for Port B + output reg [DATA_WIDTH-1:0] doutB // Data output for Port B +); + + // Core memory storage (True Dual Port) + (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram_block [DEPTH-1:0]; // Memory array + + integer i; + + // Port A Operations + always @(posedge clkA) begin + if (enaA) begin + for (i = 0; i < NUM_COL; i = i + 1) begin + if (weA[i]) begin + ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH]; // Write byte + end + end + doutA <= ram_block[addrA]; // Read operation (read-first) + end + end + + // Port B Operations + always @(posedge clkB) begin + if (enaB) begin + for (i = 0; i < NUM_COL; i = i + 1) begin + if (weB[i]) begin + ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH]; // Write byte + end + end + doutB <= ram_block[addrB]; // Read operation (read-first) + end + end + +endmodule + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_ram.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_ram.sv new file mode 100644 index 0000000000000000000000000000000000000000..b580147df9b1b3984cbf428514ad1550451a529e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_1r1w_ram.sv @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +`include "mldsa_config_defines.svh" +`ifndef RV_FPGA_OPTIMIZE +module abr_1r1w_ram #( + parameter DEPTH = 64 + ,parameter DATA_WIDTH = 32 + ,parameter ADDR_WIDTH = $clog2(DEPTH) + + ) + ( + input logic clk_i, + + input logic we_i, + input logic [ADDR_WIDTH-1:0] waddr_i, + input logic [DATA_WIDTH-1:0] wdata_i, + input logic re_i, + input logic [ADDR_WIDTH-1:0] raddr_i, + output logic [DATA_WIDTH-1:0] rdata_o + ); + + //storage element + logic [DEPTH-1:0][DATA_WIDTH-1:0] ram; + + always @(posedge clk_i) begin + if (we_i) begin + ram[waddr_i] <= wdata_i; + end + end + + always @(posedge clk_i) begin + if (re_i) begin + rdata_o <= ram[raddr_i]; + end + end + +endmodule + +`else +module abr_1r1w_ram #( + parameter DEPTH = 64 + ,parameter DATA_WIDTH = 32 + ,parameter ADDR_WIDTH = $clog2(DEPTH) + + ) + ( + input logic clk_i, + + input logic we_i, + input logic [ADDR_WIDTH-1:0] waddr_i, + input logic [DATA_WIDTH-1:0] wdata_i, + input logic re_i, + input logic [ADDR_WIDTH-1:0] raddr_i, + output logic [DATA_WIDTH-1:0] rdata_o + ); + + (* ram_style = "block" *) reg [DATA_WIDTH-1:0] ram [DEPTH-1:0]; + + always @(posedge clk_i) begin + if (we_i) begin + if (we_i) + ram[waddr_i] <= wdata_i; + end + end + + always @(posedge clk_i) begin + if (re_i) + rdata_o <= ram[raddr_i]; + end + +endmodule + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_2ff_sync.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_2ff_sync.sv new file mode 100644 index 0000000000000000000000000000000000000000..0a375ecd037e09261252858d6faa2cba5ae22d2e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_2ff_sync.sv @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module abr_2ff_sync #( parameter WIDTH=1, + parameter RST_VAL=0) + ( + input logic clk, + input logic rst_b, + input logic [WIDTH-1:0] din, + output logic [WIDTH-1:0] dout + +); + +logic din_ff; + +always_ff@(posedge clk or negedge rst_b) begin + if(!rst_b) begin + dout <= RST_VAL; + din_ff <= RST_VAL; + end + else begin + din_ff <= din; + dout <= din_ff; + end +end + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_add_sub_mod.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_add_sub_mod.sv new file mode 100644 index 0000000000000000000000000000000000000000..dec1ebe4e264b563d238d8f5ea1d6cf2e002e4f2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_add_sub_mod.sv @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// abr_add_sub_mod.sv +// -------- +// modular addtion/subtraction module to compute opa+-opb % prime +// +// +//====================================================================== + +module abr_add_sub_mod #( + parameter REG_SIZE = 384 + ) + ( + // Clock and reset. + input wire clk, + input wire reset_n, + input wire zeroize, + + // DATA PORT + input wire add_en_i, + input wire sub_i, + input wire [REG_SIZE-1:0] opa_i, + input wire [REG_SIZE-1:0] opb_i, + input wire [REG_SIZE-1:0] prime_i, + output logic [REG_SIZE-1:0] res_o, + output logic ready_o +); + + logic [REG_SIZE-1 : 0] opb0; + logic [REG_SIZE-1 : 0] opb1; + logic [REG_SIZE-1 : 0] r0; + logic [REG_SIZE-1 : 0] r1; + logic carry0; + + logic sub_n; + logic [REG_SIZE-1 : 0] r0_reg; + logic carry0_reg; + + logic carry1; + logic [1 : 0] push_result_reg; + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_0( + .a_i(opa_i), + .b_i(opb0), + .cin_i(sub_i), + .s_o(r0), + .cout_o(carry0) + ); + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_1( + .a_i(r0_reg), + .b_i(opb1), + .cin_i(sub_n), + .s_o(r1), + .cout_o(carry1) + ); + + + assign opb0 = sub_i ? ~opb_i : opb_i; + + always_ff @(posedge clk or negedge reset_n) + begin + if(!reset_n) begin + r0_reg <= '0; + carry0_reg <= '0; + sub_n <= '0; + opb1 <= '0; + end + else if (zeroize) begin + r0_reg <= '0; + carry0_reg <= '0; + sub_n <= '0; + opb1 <= '0; + end + else if (add_en_i) begin + r0_reg <= r0; + carry0_reg <= carry0; + sub_n <= !sub_i; + if (sub_i) + opb1 <= prime_i; + else + opb1 <= ~prime_i; + end + end + + // Determines when results are ready + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + push_result_reg <= 2'b0; + else if (zeroize) + push_result_reg <= 2'b0; + else if (add_en_i) + push_result_reg <= 2'b10; + else // one shift to right + push_result_reg <= 2'(push_result_reg >> 1); + end + + assign ready_o = push_result_reg[0]; + + assign res_o = sub_n ? (carry0_reg ^ carry1)? r1 : r0_reg : (carry0_reg) ? r0_reg : r1; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_adder.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_adder.sv new file mode 100644 index 0000000000000000000000000000000000000000..2ed0af88b2500d2a18c15c34c30e75f206c161b5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_adder.sv @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// abr_adder.sv +// -------- +// Full adder module to compute a + b in RADIX bits and output add result +// with carry +// +// +//====================================================================== + +module abr_adder #( + parameter RADIX = 8 +) +( + // DATA PORT + input wire [RADIX-1:0] a_i, + input wire [RADIX-1:0] b_i, + input wire cin_i, + output wire [RADIX-1:0] s_o, + output wire cout_o +); + + logic [RADIX : 0] s_full; + + always_comb begin + s_full = a_i + b_i + cin_i; + end + + assign s_o = s_full[RADIX-1 : 0]; + assign cout_o = s_full[RADIX]; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ahb_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ahb_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..3598c4db1e750154b88d36add4df74980826f594 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ahb_defines_pkg.sv @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +`ifndef ABR_AHB_DEFINES_PKG +`define ABR_AHB_DEFINES_PKG + +package abr_ahb_defines_pkg; + + parameter ABR_H_OKAY=1'b0; + parameter ABR_H_ERROR=1'b1; + +endpackage + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ahb_slv_sif.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ahb_slv_sif.sv new file mode 100644 index 0000000000000000000000000000000000000000..8e379224f2d68e704e8c4f119d183cdf31b64a95 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ahb_slv_sif.sv @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module abr_ahb_slv_sif + import abr_ahb_defines_pkg::*; + #( + parameter AHB_DATA_WIDTH = 64 + ,parameter CLIENT_DATA_WIDTH = 32 + ,parameter AHB_ADDR_WIDTH = 32 + ,parameter CLIENT_ADDR_WIDTH = AHB_ADDR_WIDTH + + ) + ( + //AMBA AHB Lite INF + input logic hclk, + input logic hreset_n, + input logic [AHB_ADDR_WIDTH-1:0] haddr_i, + input logic [AHB_DATA_WIDTH-1:0] hwdata_i, + input logic hsel_i, + input logic hwrite_i, + + input logic hready_i, + input logic [1:0] htrans_i, + input logic [2:0] hsize_i, + + + output logic hresp_o, + output logic hreadyout_o, + output logic [AHB_DATA_WIDTH-1:0] hrdata_o, + + //COMPONENT INF + output logic dv, + input logic hld, + input logic err, + output logic write, + output logic [CLIENT_DATA_WIDTH-1:0] wdata, + output logic [CLIENT_ADDR_WIDTH-1:0] addr, + + input logic [CLIENT_DATA_WIDTH-1:0] rdata + ); + +logic err_f; + +localparam BITS_WDATA = $bits(wdata); + +//support bus widths: +//64b ahb, 32b client +//64b ahb, 64b client +generate + if ((AHB_DATA_WIDTH == 32) & (CLIENT_DATA_WIDTH == 32)) begin + always_comb begin + unique case (hsize_i) inside + 3'b000: //byte + //wdata = {{$bits(wdata)-8{1'b0}},hwdata_i[7:0]}; + wdata = {{BITS_WDATA-8{1'b0}},hwdata_i[7:0]}; + 3'b001: //halfword + //wdata = {{$bits(wdata)-16{1'b0}},hwdata_i[15:0]}; + wdata = {{BITS_WDATA-16{1'b0}},hwdata_i[15:0]}; + 3'b010: //word + wdata = hwdata_i[31:0]; + default: //word + wdata = hwdata_i[31:0]; + endcase + end + always_comb hrdata_o = rdata; + end else if ((AHB_DATA_WIDTH == 64) & (CLIENT_DATA_WIDTH == 32)) begin + always_comb begin + unique case (hsize_i) inside + 3'b000: //byte + //wdata = addr[2] ? {{$bits(wdata)-8{1'b0}},hwdata_i[39:32]} : {{$bits(wdata)-8{1'b0}},hwdata_i[7:0]}; + wdata = addr[2] ? {{BITS_WDATA-8{1'b0}},hwdata_i[39:32]} : {{BITS_WDATA-8{1'b0}},hwdata_i[7:0]}; + 3'b001: //halfword + //wdata = addr[2] ? {{$bits(wdata)-16{1'b0}},hwdata_i[47:32]} : {{$bits(wdata)-16{1'b0}},hwdata_i[15:0]}; + wdata = addr[2] ? {{BITS_WDATA-16{1'b0}},hwdata_i[47:32]} : {{BITS_WDATA-16{1'b0}},hwdata_i[15:0]}; + 3'b010: //word + wdata = addr[2] ? hwdata_i[63:32] : hwdata_i[31:0]; + default: //word + wdata = addr[2] ? hwdata_i[63:32] : hwdata_i[31:0]; + endcase + end + always_comb hrdata_o = addr[2] ? {rdata, 32'b0} : {32'b0, rdata}; + end else if ((AHB_DATA_WIDTH == 64) & (CLIENT_DATA_WIDTH == 64)) begin + always_comb begin + unique case (hsize_i) inside + 3'b000: //byte + //wdata = {{$bits(wdata)-8{1'b0}},hwdata_i[7:0]}; + wdata = {{BITS_WDATA-8{1'b0}},hwdata_i[7:0]}; + 3'b001: //halfword + //wdata = {{$bits(wdata)-16{1'b0}},hwdata_i[15:0]}; + wdata = {{BITS_WDATA-16{1'b0}},hwdata_i[15:0]}; + 3'b010: //word + wdata = addr[2]? hwdata_i[63:32] : hwdata_i[31:0]; + 3'b011: //dword + wdata = hwdata_i; + default: //dword + wdata = hwdata_i; + endcase + end + always_comb hrdata_o = rdata; + end + +endgenerate + + always_ff @(posedge hclk or negedge hreset_n) begin + if(!hreset_n) begin + dv <= 1'b0; + write <= 1'b0; + addr <= '0; + err_f <= '0; + end + else begin + err_f <= err; + if (hready_i) begin + dv <= hsel_i & htrans_i inside {2'b10, 2'b11}; + end + if(hready_i & hsel_i) begin + addr <= haddr_i[CLIENT_ADDR_WIDTH-1:0]; + write <= hwrite_i & |htrans_i; + end + end + end + +always_comb begin : response_block + hreadyout_o = 1'b1; + hresp_o = ABR_H_OKAY; + //first err cycle, de-assert ready and drive err + if (err & ~err_f) begin + hreadyout_o = 1'b0; + hresp_o = ABR_H_ERROR; + end else if (hld) begin + hreadyout_o = 1'b0; + hresp_o = ABR_H_OKAY; + end else if (err_f) begin + hreadyout_o = 1'b1; + hresp_o = ABR_H_ERROR; + end +end + +//Coverage +`ifndef VERILATOR +`ifdef FCOV + +covergroup ahb_slv_sif_cov_grp @(posedge hclk); + option.per_instance = 1; + + ahb_read_cp: coverpoint (dv & ~write) {option.comment = "AHB read transaction";} + ahb_write_cp: coverpoint (dv & write) {option.comment = "AHB write transaction";} +endgroup + +ahb_slv_sif_cov_grp ahb_slv_sif_cov_grp1 = new(); + +`endif +`endif + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_delay_masked_shares.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_delay_masked_shares.sv new file mode 100644 index 0000000000000000000000000000000000000000..bb10e9e709cea5975eb2011641a90e2b480258bb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_delay_masked_shares.sv @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// abr_delay_masked_shares +// Buffers the masked shares for the N cycle +//====================================================================== + +module abr_delay_masked_shares +#( + parameter WIDTH = 46, // Width of the input array + parameter N = 5 // Number of cycles to delay +) +( + input wire clk, + input wire rst_n, + input wire zeroize, + input wire [1:0] input_reg [WIDTH-1:0], // Input signal + output logic [1:0] delayed_reg [WIDTH-1:0] // Delayed output +); + + // Create an array of shift registers to store the delayed values + logic [N-1:0][WIDTH-1:0][1:0] shift_reg ; + + // Use an always_ff block to implement the shift register + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + // Reset all shift register values to 0 + for (int j = 0; j < N; j = j + 1) begin + shift_reg[j] <= '0; + end + end + else if (zeroize) begin + // Reset all shift register values to 0 + for (int j = 0; j < N; j = j + 1) begin + shift_reg[j] <= '0; + end + end + else begin + // Shift the values through the registers + for (int j = 0; j < N-1; j = j + 1) begin + shift_reg[j+1] <= shift_reg[j]; + end + + // Load the input values into the first shift register stage + for (int i = 0; i < WIDTH; i = i + 1) begin + shift_reg[0][i] <= input_reg[i]; + end + end + end + + // Assign the output to the last stage of the shift register + always_comb begin + for (int i = 0; i < WIDTH; i = i + 1) begin + delayed_reg[i] = shift_reg[N-1][i]; + end + end + +endmodule: abr_delay_masked_shares \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_icg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_icg.sv new file mode 100644 index 0000000000000000000000000000000000000000..a6af60d360f31b4abac04e928900ce79ff679c03 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_icg.sv @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "mldsa_config_defines.svh" + +`ifndef TECH_SPECIFIC_ICG + module `ABR_ICG ( + input logic clk, + input logic en, + output clk_cg + ); + logic en_lat; + + //Latch disable for both clk and soc_ifc clk + always_latch begin + if(!clk) begin + en_lat = en; + end + end + + //Gate clk + assign clk_cg = clk && en_lat; + + endmodule +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_macros.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_macros.svh new file mode 100644 index 0000000000000000000000000000000000000000..835f42cce59344a9d0bf236e6c6f1e50e3b71d1c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_macros.svh @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef ABR_MACROS +`define ABR_MACROS + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_masked_A2B_conv.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_masked_A2B_conv.sv new file mode 100644 index 0000000000000000000000000000000000000000..62ded58525f149486d10ec9a24f79913c7fb3ea7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_masked_A2B_conv.sv @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// Module: abr_masked_A2B_conv +// Description: This module implements a pipelined, parametric ripple-carry adder using the abr_masked_full_adder. +// It performs addition of two boolean shared inputs, producing a boolean shared output. +// +// Parameters: +// - WIDTH: Specifies the bit-width of the operands. +// +// Functionality: +// - The module performs a share conversion between arithmetic and Boolean shares. +// - It takes WIDTH+2 cycle latency +// +//====================================================================== + + module abr_masked_A2B_conv #( + parameter WIDTH = 8 // Default width is 8 bits +)( + input wire clk, // Clock signal + input wire rst_n, // Active low reset signal + input wire zeroize, // Zeroize signal + input wire [1:0] x [WIDTH-1:0], // WIDTH-bit arithmetic shares operand x + input wire [WIDTH-1:0] rnd, // Random bits for masking + input wire [WIDTH-1:0] rnd_for_Boolean0, // Random bits for masking + input wire [WIDTH-1:0] rnd_for_Boolean1, // Random bits for masking + + output logic [1:0] s [WIDTH-1:0] +); + + // Internal signals + logic [WIDTH:0] [1:0] carry; // Carry signals for each stage + logic [WIDTH-1:0] [1:0] sum; // Sum signals for each stage + logic [WIDTH-1:0][WIDTH-1:0][1:0] x_reg; // Pipeline registers for x + logic [WIDTH-1:0][WIDTH-1:0][1:0] y_reg; // Pipeline registers for y + logic [WIDTH-1:0][WIDTH-1:0][1:0] sum_reg; // Pipeline registers for sum + logic [1:0] the_last_sum; + + // Initialize the first carry input to 0 + assign carry[0] = 2'b00; + + // Generate the full adders for each bit + genvar i; + generate + for (i = 0; i < WIDTH; i = i + 1) begin : gen_full_adders + // Pipeline registers for x and y inputs + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + x_reg[i] <= '0; + y_reg[i] <= '0; + end + else if (zeroize) begin + x_reg[i] <= '0; + y_reg[i] <= '0; + end + else begin + for (int j = 0; j < WIDTH; j = j + 1) begin + if (j == 0) begin + x_reg[i][j] <= {rnd_for_Boolean0[i], (x[i][0] ^ rnd_for_Boolean0[i])}; + y_reg[i][j] <= {rnd_for_Boolean1[i], (x[i][1] ^ rnd_for_Boolean1[i])}; + end + else begin + x_reg[i][j] <= x_reg[i][j-1]; + y_reg[i][j] <= y_reg[i][j-1]; + end + end + end + end + + // Pipeline registers for sum output + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + sum_reg[i] <= '0; + end + else if (zeroize) begin + sum_reg[i] <= '0; + end + else begin + for (int j = i; j < WIDTH; j = j + 1) begin + if (j == i && i == WIDTH-1) begin + sum_reg[i][j] <= the_last_sum; + end + else if (j == i) begin + sum_reg[i][j] <= sum[i]; + end + else begin + sum_reg[i][j] <= sum_reg[i][j-1]; + end + end + end + end + if (i<(WIDTH-1)) begin + // Instance of abr_masked_full_adder + abr_masked_full_adder u_abr_masked_full_adder ( + .clk(clk), // Connect clk to clk + .rst_n(rst_n), // Connect rst_n to rst_n + .zeroize(zeroize), // Connect zeroize to zeroize + .x(x_reg[i][i]), // Connect x to the last stage of the x pipeline + .y(y_reg[i][i]), // Connect y to the last stage of the y pipeline + .c_in(carry[i]), // Connect c_in to carry[i] + .rnd(rnd[i]), // Connect rnd to corresponding random bit + .s(sum[i]), // Connect sum to sum[i] + .c_out(carry[i+1]) // Connect carry out to carry[i+1] + ); + end + end + endgenerate + + always_ff @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + the_last_sum <= 2'b00; + end + else if (zeroize) begin + the_last_sum <= 2'b00; + end + else begin + the_last_sum <= x_reg[WIDTH-1][WIDTH-1] ^ y_reg[WIDTH-1][WIDTH-1] ^ carry[WIDTH-1]; + end + end + + // Assign the outputs + always_comb begin + for (int i =0; i (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate); + + always_comb data_o = buffer[PISO_OUTPUT_RATE-1:0]; + always_comb valid_o = buffer_wr_ptr >= current_output_rate; + + always_comb buffer_wr = valid_i & ~hold_o; + always_comb buffer_rd = valid_o & ~hold_i; + always_comb update_buffer = buffer_rd | buffer_wr; + + //storage element + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + buffer <= '0; + buffer_wr_ptr <= '0; + end else if (zeroize) begin + buffer <= '0; + buffer_wr_ptr <= '0; + end else if (update_buffer) begin + buffer <= buffer_d; + buffer_wr_ptr <= buffer_wr_ptr_d; + end + end + + //write pointer control + always_comb begin + unique case ({buffer_rd, buffer_wr}) + 2'b00 : buffer_wr_ptr_d = buffer_wr_ptr; + 2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + current_input_rate; + 2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - current_output_rate; + 2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (current_input_rate - current_output_rate); + default : buffer_wr_ptr_d = buffer_wr_ptr; + endcase + end + + logic [PISO_BUFFER_W-1:0] buffer_wdata; + logic [PISO_BUFFER_W-1:0] buffer_wdata_mask; + + always_comb begin + buffer_wdata = '0; + buffer_wdata_mask = '1; + buffer_wdata_mask = PISO_BUFFER_W'(buffer_wdata_mask >> (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate)); + buffer_wdata = {{BUFFER_W_DELTA{1'b0}},data_i} & buffer_wdata_mask; + end + + //buffer next logic + always_comb begin + unique case ({buffer_rd, buffer_wr}) + 2'b00 : buffer_d = buffer; + 2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> current_output_rate); + 2'b01 : buffer_d = PISO_BUFFER_W'(buffer_wdata << buffer_wr_ptr) | buffer; + 2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_wr_ptr - current_output_rate)) | PISO_BUFFER_W'(buffer >> current_output_rate); + default : buffer_d = buffer; + endcase + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_piso_4.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_piso_4.sv new file mode 100644 index 0000000000000000000000000000000000000000..059781078a15fc45edc4ecfc93d0c0a2ed29b2d9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_piso_4.sv @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either sibress or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// PISO supports 4 modes of operation, each with unique input and output rates + +module abr_piso_4 + #( parameter PISO_BUFFER_W = 1344 + ,parameter PISO_PTR_W = $clog2(PISO_BUFFER_W) + ,parameter PISO_INPUT_RATE0 = 1088 + ,parameter PISO_INPUT_RATE1 = 1088 + ,parameter PISO_INPUT_RATE2 = 1088 + ,parameter PISO_INPUT_RATE3 = 1088 + ,parameter PISO_OUTPUT_RATE0 = 80 + ,parameter PISO_OUTPUT_RATE1 = 80 + ,parameter PISO_OUTPUT_RATE2 = 80 + ,parameter PISO_OUTPUT_RATE3 = 80 + ,parameter PISO_ACT_INPUT_RATE = 1088 + ,parameter PISO_ACT_OUTPUT_RATE = 80 + ) + ( + input logic clk, + input logic rst_b, + input logic zeroize, + + //input data + input logic [1:0] mode, + input logic valid_i, + output logic hold_o, + input logic [PISO_ACT_INPUT_RATE-1:0] data_i, + + //Output data + output logic valid_o, + input logic hold_i, + output logic [PISO_ACT_OUTPUT_RATE-1:0] data_o + + ); + + parameter BUFFER_W_DELTA = PISO_BUFFER_W - PISO_ACT_INPUT_RATE; + + logic [PISO_BUFFER_W-1:0] buffer, buffer_d; + logic [PISO_PTR_W-1:0] buffer_wr_ptr, buffer_wr_ptr_d; + + logic [PISO_PTR_W-1:0] current_input_rate, current_output_rate; + + logic buffer_wr, buffer_rd; + logic update_buffer; + + always_comb begin + unique case (mode) + 2'b00: current_input_rate = PISO_INPUT_RATE0; + 2'b01: current_input_rate = PISO_INPUT_RATE1; + 2'b10: current_input_rate = PISO_INPUT_RATE2; + 2'b11: current_input_rate = PISO_INPUT_RATE3; + endcase + + unique case (mode) + 2'b00: current_output_rate = PISO_OUTPUT_RATE0; + 2'b01: current_output_rate = PISO_OUTPUT_RATE1; + 2'b10: current_output_rate = PISO_OUTPUT_RATE2; + 2'b11: current_output_rate = PISO_OUTPUT_RATE3; + endcase + end + + //hold when not enough room for full input data + always_comb hold_o = buffer_wr_ptr > (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate); + + always_comb data_o = buffer[PISO_ACT_OUTPUT_RATE-1:0]; + always_comb valid_o = buffer_wr_ptr >= current_output_rate; + + always_comb buffer_wr = valid_i & ~hold_o; + always_comb buffer_rd = valid_o & ~hold_i; + always_comb update_buffer = buffer_rd | buffer_wr; + + //storage element + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + buffer <= '0; + buffer_wr_ptr <= '0; + end else if (zeroize) begin + buffer <= '0; + buffer_wr_ptr <= '0; + end else if (update_buffer) begin + buffer <= buffer_d; + buffer_wr_ptr <= buffer_wr_ptr_d; + end + end + + //write pointer control + always_comb begin + unique case ({buffer_rd, buffer_wr}) + 2'b00 : buffer_wr_ptr_d = buffer_wr_ptr; + 2'b01 : buffer_wr_ptr_d = buffer_wr_ptr + current_input_rate; + 2'b10 : buffer_wr_ptr_d = buffer_wr_ptr - current_output_rate; + 2'b11 : buffer_wr_ptr_d = buffer_wr_ptr + (current_input_rate - current_output_rate); + default : buffer_wr_ptr_d = buffer_wr_ptr; + endcase + end + + logic [PISO_BUFFER_W-1:0] buffer_wdata; + logic [PISO_BUFFER_W-1:0] buffer_wdata_mask; + + always_comb begin + buffer_wdata = '0; + buffer_wdata_mask = '1; + buffer_wdata_mask = PISO_BUFFER_W'(buffer_wdata_mask >> (PISO_BUFFER_W[PISO_PTR_W-1:0] - current_input_rate)); + buffer_wdata = {{BUFFER_W_DELTA{1'b0}},data_i} & buffer_wdata_mask; + end + + //buffer next logic + always_comb begin + unique case ({buffer_rd, buffer_wr}) + 2'b00 : buffer_d = buffer; + 2'b10 : buffer_d = PISO_BUFFER_W'(buffer >> current_output_rate); + 2'b01 : buffer_d = PISO_BUFFER_W'(buffer_wdata << buffer_wr_ptr) | buffer; + 2'b11 : buffer_d = PISO_BUFFER_W'(buffer_wdata << (buffer_wr_ptr - current_output_rate)) | PISO_BUFFER_W'(buffer >> current_output_rate); + default : buffer_d = buffer; + endcase + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ram_regout.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ram_regout.sv new file mode 100644 index 0000000000000000000000000000000000000000..0679c533ff12c004924b2176070b3ac15ebac8c2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_ram_regout.sv @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module abr_ram_regout #( + parameter DEPTH = 64 + ,parameter DATA_WIDTH = 32 + ,parameter NUM_RD_PORTS = 1 + ,parameter NUM_WR_PORTS = 1 + ,parameter ADDR_WIDTH = $clog2(DEPTH) + + ) + ( + input logic clk_i, + input logic zeroize_i, + input logic [NUM_WR_PORTS-1:0] we_i, + input logic [NUM_WR_PORTS-1:0][ADDR_WIDTH-1:0] waddr_i, + input logic [NUM_WR_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, + input logic [NUM_RD_PORTS-1:0] re_i, + input logic [NUM_RD_PORTS-1:0][ADDR_WIDTH-1:0] raddr_i, + output logic [NUM_RD_PORTS-1:0][DATA_WIDTH-1:0] rdata_o, + output logic [DEPTH-1:0][DATA_WIDTH-1:0] reg_o + ); + + //storage element + logic [DEPTH-1:0][DATA_WIDTH-1:0] ram; + + always @(posedge clk_i) begin + if (zeroize_i) begin + ram <= '0; + end + else begin + for (int port = 0; port < NUM_WR_PORTS; port++) begin + if (we_i[port]) begin + ram[waddr_i[port]] <= wdata_i[port]; + end + end + end + end + + always @(posedge clk_i) begin + for (int port = 0; port < NUM_RD_PORTS; port++) begin + if (re_i[port]) begin + rdata_o[port] <= ram[raddr_i[port]]; + end + end + end + + assign reg_o = ram; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_sample_buffer.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_sample_buffer.sv new file mode 100644 index 0000000000000000000000000000000000000000..9e7666604216b4a5812bf081fcfc629c6283de44 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_sample_buffer.sv @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// Sample Buffer takes in NUM_WR samples and valid bits +// Valid samples are packed and shifted onto a buffer +// Outputs are presented valid once NUM_RD entries are valid in the buffer + +module abr_sample_buffer + // import ::*; + #( + parameter NUM_WR = 5 + ,parameter NUM_RD = 4 + ,parameter BUFFER_DATA_W = 32 + ,parameter OPT_BUFFER_DEPTH = 0 + ,localparam BUFFER_DEPTH = (NUM_WR + NUM_RD) + ,localparam BUF_W = BUFFER_DEPTH*BUFFER_DATA_W + ) + ( + input logic clk, + input logic rst_b, + + input logic zeroize, + + //input data + input logic [NUM_WR-1:0] data_valid_i, + input logic [NUM_WR-1:0][BUFFER_DATA_W-1:0] data_i, + output logic buffer_full_o, + //output data + output logic data_valid_o, + output logic [NUM_RD-1:0][BUFFER_DATA_W-1:0] data_o + + ); + + logic buffer_rd, buffer_wr; + logic update_buffer; + + //Incoming samples to write to buffer + logic [BUFFER_DEPTH-1:0][BUFFER_DATA_W-1:0] buffer_wr_data, buffer_wr_data_shift; + logic [BUFFER_DEPTH-1:0] buffer_wr_valid, buffer_wr_valid_shift; + + //Valid sample buffer + logic [BUFFER_DEPTH-1:0] buffer_valid, buffer_valid_d, buffer_valid_shift; + logic [BUFFER_DEPTH-1:0][BUFFER_DATA_W-1:0] buffer, buffer_d, buffer_shift; + logic [$clog2(BUFFER_DEPTH):0] num_valid; + + + //Buffer is full when it can't take a full write cycle + //Check for at least N entries available, where N is the difference between WR/RD bandwidth + generate + if (NUM_WR == NUM_RD) always_comb buffer_full_o = '0; + else always_comb buffer_full_o = buffer_valid[(BUFFER_DEPTH-(NUM_WR-NUM_RD))]; + endgenerate + //Read when we have NUM_RD worth of valid data + always_comb buffer_rd = buffer_valid[NUM_RD-1]; + //Write as long as we have 1 valid sample and not full + always_comb buffer_wr = (|data_valid_i) & ~buffer_full_o; + //update buffer for any read or write + always_comb update_buffer = buffer_rd | buffer_wr; + + always_comb begin + //count the valid entries in the buffer already + num_valid = '0; + for (int i = 0; i < BUFFER_DEPTH; i++) begin + if (buffer_valid[i] == 1'b1) num_valid += 1'b1; + end + end + + //Concat the valid samples + logic [$clog2(BUFFER_DEPTH)-1:0] sample_wr_ptr; + always_comb begin + sample_wr_ptr = '0; + buffer_wr_data = '0; + buffer_wr_valid = '0; + for (int sample = 0; sample < NUM_WR; sample++) begin + if (data_valid_i[sample]) begin + //concat the next valid sample + buffer_wr_data[sample_wr_ptr] = data_i[sample][BUFFER_DATA_W-1:0]; + buffer_wr_valid[sample_wr_ptr] = 1'b1; + //increment the write pointer + sample_wr_ptr += 1; + end + end + + //shift the write data left by the count, or count - NUM_RD if there is a read + buffer_wr_data_shift = buffer_rd ? buffer_wr_data << (num_valid - NUM_RD)*BUFFER_DATA_W : + buffer_wr_data << (num_valid)*BUFFER_DATA_W; + buffer_wr_valid_shift = buffer_wr ? + (buffer_rd ? buffer_wr_valid << (num_valid - NUM_RD) : + buffer_wr_valid << (num_valid)) : '0; + end + + //Shift the buffer contents and append new samples + always_comb begin + //shift the buffer data right by NUM_RD if there is a read + buffer_shift = buffer_rd ? BUF_W'(buffer >> (NUM_RD*BUFFER_DATA_W)) : buffer; + buffer_valid_shift = buffer_rd ? BUFFER_DEPTH'(buffer_valid >> NUM_RD) : buffer_valid; + + //OR together the write data and the buffer data + buffer_d = buffer_shift | buffer_wr_data_shift; + buffer_valid_d = buffer_valid_shift | buffer_wr_valid_shift; + end + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + buffer <= '0; + buffer_valid <= '0; + end else if (zeroize) begin + buffer <= '0; + buffer_valid <= '0; + end else if (update_buffer) begin + buffer <= buffer_d; + buffer_valid <= buffer_valid_d; + end + end + + //Output is valid when we have NUM_RD worth of valid data + always_comb data_valid_o = buffer_rd & ~zeroize; + always_comb data_o = buffer[NUM_RD-1:0]; + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_sva.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_sva.svh new file mode 100644 index 0000000000000000000000000000000000000000..41f248b279ee33b521cb06c82b0e559645afbf1c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/rtl/abr_sva.svh @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef ABR_SVA +`define ABR_SVA + +// Default clk and reset signals used by assertion macros below. +`define ABR_ASSERT_DEFAULT_CLK clk_i +`define ABR_ASSERT_DEFAULT_RST !rst_b + +// Converts an arbitrary block of code into a Verilog string +`define STRINGIFY(__x) `"__x`" + +// ABR_ASSERT_RPT is available to change the reporting mechanism when an assert fails +`define ABR_ASSERT_RPT(name) \ +`ifdef UVM \ + assert_rpt_pkg::assert_rpt($sformatf("[%m] %s (%s:%0d)", \ + name, `__FILE__, `__LINE__)); \ +`else \ + $fatal(1, "[ABR_ASSERT FAILED] [%m] %s (%s:%0d)",name, `__FILE__, `__LINE__); \ +`endif + +// Assert a concurrent property directly. +`define ABR_ASSERT(assert_name, prop, clk = `ABR_ASSERT_DEFAULT_CLK, rst = `ABR_ASSERT_DEFAULT_RST, en = 1) \ +`ifdef ABR_ASSERT_ON \ + assert_name: assert property (@(posedge clk) disable iff ((rst !== 0) | (en === 0)) (prop)) \ + else begin \ + `ABR_ASSERT_RPT(`STRINGIFY(assert_name)) \ + end \ +`endif + +// Assert a concurrent property NEVER happens +`define ABR_ASSERT_NEVER(assert_name, prop, clk = `ABR_ASSERT_DEFAULT_CLK, rst = `ABR_ASSERT_DEFAULT_RST, en = 1) \ +`ifdef ABR_ASSERT_ON \ + assert_name: assert property (@(posedge clk) disable iff ((rst !== 0) | (en === 0)) not (prop)) \ + else begin \ + `ABR_ASSERT_RPT(`STRINGIFY(assert_name)) \ + end \ +`endif + +// Assert that signal is not x +`define ABR_ASSERT_KNOWN(assert_name, sig, clk = `ABR_ASSERT_DEFAULT_CLK, rst = `ABR_ASSERT_DEFAULT_RST, en = 1) \ + `ABR_ASSERT(assert_name, !$isunknown(sig), clk, rst, en) + +// Assert that a vector of signals is mutually exclusive +`define ABR_ASSERT_MUTEX(assert_name, sig, clk = `ABR_ASSERT_DEFAULT_CLK, rst = `ABR_ASSERT_DEFAULT_RST, en = 1) \ + `ABR_ASSERT(assert_name, $onehot0(sig), clk, rst, en) + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/stimulus/tests/directed/masking_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/stimulus/tests/directed/masking_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..0055f8181523b400c6409fa38ecdc9a8e8a87060 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/stimulus/tests/directed/masking_test.yml @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +testname: masking_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..990ad352d68c9c16a953992c1bce921b441d8982 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +module abr_masked_A2B_conv_tb; + + // Parameter for the width of the ripple-carry adder + localparam WIDTH = 8; + + + // DEBUG flag and number of test vector + localparam DEBUG = 0; + localparam NUM_OF_TEST_VECTOR = 32'd1_000_000; + + // Testbench signals + logic clk; + logic rst_n; + logic zeroize; + logic [1:0] x [WIDTH-1:0]; + logic [WIDTH-1:0] rnd, rnd_for_Boolean0, rnd_for_Boolean1; + logic [1:0] s [WIDTH-1:0]; + + // Queue to store inputs + typedef struct { + logic [WIDTH-1:0] x_comb; + logic [WIDTH-1:0] x0_arith; + logic [WIDTH-1:0] x1_arith; + } input_t; + input_t input_queue[(WIDTH + 2)]; + + + logic [WIDTH-1:0] x0_arith, x1_arith, x_comb; + logic [WIDTH:0] expected_sum; // One extra bit for carry + logic [WIDTH:0] actual_sum; // One extra bit for carry + input_t inputs; + + // Instantiate the DUT (Device Under Test) + abr_masked_A2B_conv #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(x), + .rnd(rnd), + .rnd_for_Boolean0(rnd_for_Boolean0), + .rnd_for_Boolean1(rnd_for_Boolean1), + .s(s) + ); + + // Clock generation + always #5 clk = ~clk; + + // Task to initialize the inputs + task initialize_inputs(); + integer i; + begin + rst_n = 1; + zeroize = 0; + for (i = 0; i < WIDTH; i = i + 1) begin + x[i] = 2'b00; + rnd[i] = 1'b0; + rnd_for_Boolean0[i] = 1'b0; + rnd_for_Boolean1[i] = 1'b0; + end + end + endtask + + // Task to apply a reset + task apply_reset(); + begin + rst_n = 0; + #10; + rst_n = 1; + end + endtask + + // Task to perform test with specified number of vectors + task perform_test(input int num_vectors); + + fork + // Refresh the randomoness + begin + for (int i = 0; i < num_vectors + (WIDTH + 2); i++) begin + @(posedge clk); + rnd = $random; + rnd_for_Boolean0 = $random; + rnd_for_Boolean1 = $random; + end + end + // Drive inputs and push into queue + begin + for (int i = 0; i < num_vectors + (WIDTH + 2); i++) begin + @(posedge clk); + if (i < num_vectors) begin + x_comb = $random; + //Split one secret into arithmetic shares + x1_arith = $random; + x0_arith = (x_comb-x1_arith); + // split each share into two Boolean shares + for (int j = 0; j < WIDTH; j = j + 1) begin + x[j][0] = x0_arith[j]; + x[j][1] = x1_arith[j]; + end + + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j-1]; + end + input_queue[0] = '{x_comb: x_comb, x0_arith: x0_arith, x1_arith: x1_arith}; + if (DEBUG) $display("[%0t] Input pushed: x_comb = %0b, x1_arith = %0b, x0_arith = %0b", $time, x_comb, x0_arith, x1_arith); + end + else begin + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j-1]; + end + end + end + end + + // Collect results, perform addition, and compare + begin + repeat (WIDTH+1) @(posedge clk); + for (int i = 0; i < num_vectors; i++) begin + @(posedge clk); + + // Access inputs from the queue + inputs = input_queue[WIDTH+1]; + if (DEBUG) $display("[%0t] Input poped: x_comb = %0b, x1_arith = %0b, x0_arith = %0b", $time, inputs.x_comb, inputs.x0_arith, inputs.x1_arith); + + // Calculate expected results + expected_sum = inputs.x_comb; + #1; + + // Combine the shares + actual_sum = (s[WIDTH-1][0] ^ s[WIDTH-1][1]); + for (int j = WIDTH-2; j >= 0; j = j - 1) begin + actual_sum = {actual_sum, (s[j][0] ^ s[j][1])}; + end + + // Compare the results + if (actual_sum !== expected_sum) begin + $display("[%0t] Error: Expected sum = %0b, got %0b", $time, expected_sum, actual_sum); + end + else begin + if (DEBUG) $display("[%0t] Correct: sum = %0b", $time, actual_sum); + end + end + end + join + endtask + + // Initial block to control the simulation + initial begin + // Initialize the clock + clk = 0; + + // Initialize inputs + initialize_inputs(); + + // Apply reset + apply_reset(); + + // Perform test with specified number of vectors + perform_test(NUM_OF_TEST_VECTOR); + + // Wait for some time to observe the outputs + #100; + + // Finish the simulation + $finish; + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..e311fe8f09e62aafe3a9f1d7415f09369e600d70 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + + +module abr_masked_B2A_conv_tb; + + // Parameters + localparam WIDTH = 8; + localparam MOD = 2**WIDTH; + localparam NUM_OF_TEST_VECTOR = 32'd1_000_000; + localparam DEBUG = 0; + + // Testbench signals + logic clk; + logic rst_n; + logic zeroize; + logic [WIDTH-1:0] rnd; + logic [1:0] x_boolean [WIDTH-1:0]; + logic [1:0] A [WIDTH-1:0]; + logic [WIDTH-1:0] expected_A; + logic [WIDTH-1:0] actual_A; + logic [WIDTH-1:0] A0; + logic [WIDTH-1:0] A1; + + // Queue to store inputs + typedef struct { + logic [1:0] x_boolean [WIDTH-1:0]; + logic [WIDTH-1:0] rnd; + } input_t; + input_t input_queue [(WIDTH + 2)]; + + input_t inputs; + + // Instantiate the DUT (Device Under Test) + abr_masked_B2A_conv #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .rnd(rnd), + .x_boolean(x_boolean), + .x_arith(A) + ); + + // Clock generation + always #5 clk = ~clk; + + // Task to initialize the inputs + task initialize_inputs(); + integer i; + begin + rst_n = 1; + zeroize = 0; + rnd = 'h0; + expected_A = 'h0; + actual_A = 'h0; + for (i = 0; i < WIDTH; i = i + 1) begin + x_boolean[i] = 2'b00; + end + end + endtask + + // Task to apply a reset + task apply_reset(); + begin + rst_n = 0; + #10; + rst_n = 1; + end + endtask + + // Task to perform test with specified number of vectors + task perform_test(input int num_vectors); + + fork + // Refresh the randomness + begin + for (int i = 0; i < num_vectors + 3; i++) begin + @(posedge clk); + #1; + rnd = $random; + end + end + // Drive inputs and push into queue + begin + for (int i = 0; i < num_vectors + 3; i++) begin + @(posedge clk); + #3; + if (i < num_vectors) begin + // Generate random inputs + for (int j = 0; j < WIDTH; j = j + 1) begin + x_boolean[j] = $random; + end + + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j - 1]; + end + input_queue[0] = '{x_boolean: x_boolean, rnd: rnd}; + + if (DEBUG) $display("[%0t] Input pushed: x_boolean = %p, rnd = %0b", $time, x_boolean, rnd); + end + else begin + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j - 1]; + end + end + end + end + + // Collect results and compare + begin + repeat (2) @(negedge clk); + for (int i = 0; i < num_vectors; i++) begin + @(negedge clk); + + // Access inputs from the queue + inputs = input_queue[2]; + if (DEBUG) $display("[%0t] Input popped: x_boolean = %p, rnd = %0b", $time, inputs.x_boolean, inputs.rnd); + + // Compare the results (you can define the expected results based on your logic) + #2; // Wait for outputs to stabilize + for (int j = 0; j < WIDTH; j = j + 1) begin + expected_A[j] = inputs.x_boolean[j][0] ^ inputs.x_boolean[j][1]; + A0[j] = A[j][0]; + A1[j] = A[j][1]; + end + actual_A = (A0+A1) % MOD; + + //Placeholder for comparison logic + if (actual_A !== expected_A) begin + $display("[%0t] Error: Expected A = %p, got %p", $time, expected_A, actual_A); + end + else begin + if (DEBUG) $display("[%0t] Correct: A = %p", $time, actual_A); + end + end + end + join + endtask + + // Initial block to control the simulation + initial begin + // Initialize the clock + clk = 0; + + // Initialize inputs + initialize_inputs(); + + // Apply reset + apply_reset(); + #10; + + // Perform test with specified number of vectors + perform_test(NUM_OF_TEST_VECTOR); + + // Wait for some time to observe the outputs + #100; + + // Finish the simulation + $finish; + end + + endmodule + \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..aba691240431690abc046d8f1c246c2e28f19dce --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +module abr_masked_N_bit_Boolean_adder_tb; + + // Parameter for the width of the ripple-carry adder + localparam WIDTH = 15; + localparam MOD = (2**WIDTH); + + + // DEBUG flag and number of test vector + localparam DEBUG = 0; + localparam NUM_OF_TEST_VECTOR = 32'd1_000_000; + + // Testbench signals + logic clk; + logic rst_n; + logic zeroize; + logic [1:0] x [WIDTH-1:0]; + logic [1:0] y [WIDTH-1:0]; + logic [WIDTH-1:0] rnd; + logic [1:0] s [WIDTH-1:0]; + + // Queue to store inputs + typedef struct { + logic [WIDTH-1:0] x_comb; + logic [WIDTH-1:0] y_comb; + } input_t; + input_t input_queue[(WIDTH + 2)]; + + // Instantiate the DUT (Device Under Test) + abr_masked_N_bit_Boolean_adder #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(x), + .y(y), + .rnd(rnd), + .s(s) + ); + + // Clock generation + always #5 clk = ~clk; + + // Task to initialize the inputs + task initialize_inputs(); + integer i; + begin + rst_n = 1; + zeroize = 0; + for (i = 0; i < WIDTH; i = i + 1) begin + x[i] = 2'b00; + y[i] = 2'b00; + rnd[i] = 1'b0; + end + end + endtask + + // Task to apply a reset + task apply_reset(); + begin + rst_n = 0; + #10; + rst_n = 1; + end + endtask + + // Task to perform test with specified number of vectors + logic [WIDTH-1:0] x_comb, y_comb; + logic [WIDTH:0] expected_sum; // One extra bit for carry + logic [WIDTH:0] actual_sum; // One extra bit for carry + input_t inputs; + task perform_test(input int num_vectors); + + fork + // Refresh the randomness + begin + for (int i = 0; i < num_vectors + (WIDTH + 2); i++) begin + @(posedge clk); + #1; + rnd = $random; + end + end + // Drive inputs and push into queue + begin + for (int i = 0; i < num_vectors + (WIDTH + 2); i++) begin + @(posedge clk); + if (i < num_vectors) begin + x_comb = $random; + y_comb = $random; + for (int j = 0; j < WIDTH; j = j + 1) begin + x[j] = {1'b0, x_comb[j]}; + y[j] = {1'b0, y_comb[j]}; + rnd[j] = 0; + end + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j-1]; + end + input_queue[0] = '{x_comb: x_comb, y_comb: y_comb}; + if (DEBUG) $display("[%0t] Input pushed: x_comb = %0b, y_comb = %0b", $time, x_comb, y_comb); + end + else begin + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j-1]; + end + end + end + end + + // Collect results, perform addition, and compare + begin + repeat (WIDTH+1) @(posedge clk); + for (int i = 0; i < num_vectors; i++) begin + @(posedge clk); + + // Access inputs from the queue + inputs = input_queue[WIDTH+1]; + if (DEBUG) $display("[%0t] Input poped: x_comb = %0b, y_comb = %0b", $time, inputs.x_comb, inputs.y_comb); + + // Calculate expected results + expected_sum = (inputs.x_comb + inputs.y_comb) % MOD; + #1; + + // Combine the shares + actual_sum = (s[WIDTH-1][0] ^ s[WIDTH-1][1]); + for (int j = WIDTH-2; j >= 0; j = j - 1) begin + actual_sum = {actual_sum, (s[j][0] ^ s[j][1])}; + end + + // Compare the results + if (actual_sum !== expected_sum) begin + $display("[%0t] Error: Expected sum = %0b, got %0b", $time, expected_sum, actual_sum); + end + else begin + if (DEBUG) $display("[%0t] Correct: sum = %0b", $time, actual_sum); + end + end + end + join + endtask + + // Initial block to control the simulation + initial begin + // Initialize the clock + $display("abr_masked_N_bit_Boolean_adder TEST started"); + clk = 0; + + // Initialize inputs + initialize_inputs(); + + // Apply reset + apply_reset(); + + // Perform test with specified number of vectors + perform_test(NUM_OF_TEST_VECTOR); + + // Wait for some time to observe the outputs + #100; + + // Finish the simulation + $finish; + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..43347372885855c3d3dbaac3bd7c34fa7b97f5d1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +module abr_masked_N_bit_mult_tb; + + // Parameters + localparam WIDTH = 22; + localparam HALF_WIDTH = WIDTH/2; + localparam MOD = 2**WIDTH; + localparam NUM_OF_TEST_VECTOR = 32'd0_100_000; + localparam DEBUG = 0; + + // Testbench signals + logic clk; + logic rst_n; + logic zeroize; + logic [1:0] x [WIDTH-1:0]; + logic [HALF_WIDTH-1:0] y; + logic [1:0] z [WIDTH-1:0]; + logic [WIDTH-1:0] expected_z; + logic [WIDTH-1:0] actual_z; + logic [HALF_WIDTH-1:0] actual_input; + logic [WIDTH-1:0] x0, z0, tmp0; + logic [WIDTH-1:0] x1, z1, tmp1; + + // Queue to store inputs + typedef struct { + logic [1:0] x [WIDTH-1:0]; + logic [HALF_WIDTH-1:0] y; + } input_t; + input_t input_queue [(WIDTH + 2)]; + + input_t inputs; + + // Instantiate the DUT (Device Under Test) + abr_masked_N_bit_mult #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(x), + .y(y), + .z(z) + ); + + // Clock generation + always #5 clk = ~clk; + + // Task to initialize the inputs + task initialize_inputs(); + integer i; + begin + rst_n = 1; + zeroize = 0; + y = 'h0; + expected_z = 'h0; + actual_z = 'h0; + for (i = 0; i < WIDTH; i = i + 1) begin + x[i] = 2'b00; + end + end + endtask + + // Task to apply a reset + task apply_reset(); + begin + rst_n = 0; + #10; + rst_n = 1; + end + endtask + + // Task to perform test with specified number of vectors + task perform_test(input int num_vectors); + + fork + // Drive inputs and push into queue + begin + for (int i = 0; i < num_vectors + 2; i++) begin + @(posedge clk); + #3; + if (i < num_vectors) begin + // Generate random inputs + actual_input = $random; + tmp1 = $random; + tmp0 = (actual_input - tmp1) % MOD; + for (int j = 0; j < WIDTH; j = j + 1) begin + x[j] = {tmp1[j], tmp0[j]}; + end + y = $random; + + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j - 1]; + end + input_queue[0] = '{x: x, y: y}; + + if (DEBUG) $display("[%0t] Input pushed: x = %d ({%d,%d}), y = %d", $time, actual_input, tmp0, tmp1, y); + end + else begin + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j - 1]; + end + end + end + end + + // Collect results and compare + begin + repeat (1) @(negedge clk); + for (int i = 0; i < num_vectors; i++) begin + @(negedge clk); + + // Access inputs from the queue + inputs = input_queue[1]; + + for (int i = 0; i < WIDTH; i++) begin + x0[i] = inputs.x[i][0]; + x1[i] = inputs.x[i][1]; + end + if (DEBUG) $display("[%0t] Input popped: x = %d, y = %d", $time, (x0+x1) % MOD, inputs.y); + + // Compare the results (you can define the expected results based on your logic) + #2; // Wait for outputs to stabilize + expected_z = ((x0 + x1) * inputs.y) % MOD; + for (int j = 0; j < WIDTH; j = j + 1) begin + z0[j] = z[j][0]; + z1[j] = z[j][1]; + end + actual_z = (z0 + z1) % MOD; + + // Placeholder for comparison logic + if (actual_z !== expected_z) begin + $display("[%0t] Error: Expected z = %p, got %p", $time, expected_z, actual_z); + end + else begin + if (DEBUG) $display("[%0t] Correct: z = %p", $time, actual_z); + end + end + end + join + endtask + + // Initial block to control the simulation + initial begin + // Initialize the clock + clk = 0; + + // Initialize inputs + initialize_inputs(); + + // Apply reset + apply_reset(); + #10; + + // Perform test with specified number of vectors + perform_test(NUM_OF_TEST_VECTOR); + + // Wait for some time to observe the outputs + #100; + + // Finish the simulation + $finish; + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..a819c73a27af44ae3294ea228df0042dfbfcb167 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +module abr_masked_N_bit_mult_two_share_tb; + + // Parameters + localparam WIDTH = 22; + localparam HALF_WIDTH = WIDTH/2; + localparam MOD = 2**WIDTH; + localparam NUM_OF_TEST_VECTOR = 32'd0_100_000; + localparam DEBUG = 0; + + // Testbench signals + logic clk; + logic rst_n; + logic zeroize; + logic [1:0] x [WIDTH-1:0]; + logic [1:0] y [WIDTH-1:0]; + logic [1:0] z [WIDTH-1:0]; + logic [WIDTH-1:0] expected_z; + logic [WIDTH-1:0] actual_z; + logic [WIDTH-1:0] random_tb; + logic [HALF_WIDTH-1:0] actual_input, actual_y; + logic [WIDTH-1:0] x0, y0, z0, tmp0, y_tmp0; + logic [WIDTH-1:0] x1, y1, z1, tmp1, y_tmp1; + + // Queue to store inputs + typedef struct { + logic [1:0] x [WIDTH-1:0]; + logic [1:0] y [WIDTH-1:0]; + } input_t; + input_t input_queue [(WIDTH + 2)]; + + input_t inputs; + + // Instantiate the DUT (Device Under Test) + abr_masked_N_bit_mult_two_share #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .random(random_tb), + .x(x), + .y(y), + .z(z) + ); + + // Clock generation + always #5 clk = ~clk; + + // Task to initialize the inputs + task initialize_inputs(); + integer i; + begin + rst_n = 1; + zeroize = 0; + + expected_z = 'h0; + actual_z = 'h0; + for (i = 0; i < WIDTH; i = i + 1) begin + x[i] = 2'b00; + y[i] = 2'h0; + end + end + endtask + + // Task to apply a reset + task apply_reset(); + begin + rst_n = 0; + #10; + rst_n = 1; + end + endtask + + // Task to perform test with specified number of vectors + task perform_test(input int num_vectors); + + fork + // Drive inputs and push into queue + begin + for (int i = 0; i < num_vectors + 2; i++) begin + @(posedge clk); + #3; + if (i < num_vectors) begin + // Generate random inputs + random_tb = $random; + actual_input = $random; + actual_y = $random; + tmp1 = $random; + tmp0 = (actual_input - tmp1) % MOD; + for (int j = 0; j < WIDTH; j = j + 1) begin + x[j] = {tmp1[j], tmp0[j]}; + end + y_tmp1 = $random; + y_tmp0 = (actual_y - y_tmp1) % MOD; + for (int j = 0; j < WIDTH; j = j+1) begin + y[j] = {y_tmp1[j], y_tmp0[j]}; + end + + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j - 1]; + end + input_queue[0] = '{x: x, y: y}; + + if (DEBUG) $display("[%0t] Input pushed: x = %d ({%d,%d}), y = %d ({%d,%d})", $time, actual_input, tmp0, tmp1, actual_y, y_tmp0, y_tmp1); + end + else begin + // Shift left and insert new inputs + for (int j = WIDTH + 1; j > 0; j = j - 1) begin + input_queue[j] = input_queue[j - 1]; + end + end + end + end + + // Collect results and compare + begin + repeat (1) @(negedge clk); + for (int i = 0; i < num_vectors; i++) begin + @(negedge clk); + + // Access inputs from the queue + inputs = input_queue[1]; + + for (int i = 0; i < WIDTH; i++) begin + x0[i] = inputs.x[i][0]; + x1[i] = inputs.x[i][1]; + + y0[i] = inputs.y[i][0]; + y1[i] = inputs.y[i][1]; + end + if (DEBUG) $display("[%0t] Input popped: x = %d, y = %d", $time, (x0+x1) % MOD, (y0+y1)%MOD); + + // Compare the results (you can define the expected results based on your logic) + #2; // Wait for outputs to stabilize + expected_z = ((x0 + x1) * (y0+y1)) % MOD; + for (int j = 0; j < WIDTH; j = j + 1) begin + z0[j] = z[j][0]; + z1[j] = z[j][1]; + end + actual_z = (z0 + z1) % MOD; + + // Placeholder for comparison logic + if (actual_z !== expected_z) begin + $display("[%0t] Error: Expected z = %p, got %p", $time, expected_z, actual_z); + end + else begin + if (DEBUG) $display("[%0t] Correct: z = %p", $time, actual_z); + end + end + end + join + endtask + + // Initial block to control the simulation + initial begin + // Initialize the clock + clk = 0; + + // Initialize inputs + initialize_inputs(); + + // Apply reset + apply_reset(); + #10; + + // Perform test with specified number of vectors + perform_test(NUM_OF_TEST_VECTOR); + + // Wait for some time to observe the outputs + #100; + + // Finish the simulation + $finish; + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh new file mode 100644 index 0000000000000000000000000000000000000000..55943973e6baed673cce6b6c5ae7ffbf8073009b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/ahb_lite_slave_0_config_policy.svh @@ -0,0 +1,169 @@ +// +// File: ahb_lite_slave_0_config_policy.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class ahb_lite_slave_0_config_policy; + static function void configure + ( + input ahb_lite_slave_0_cfg_t cfg, + input address_map addrm + ); + // + // Agent setup configurations: + // + // + // + // Active or Passive + cfg.agent_cfg.is_active = 1; + // VIP agent type + cfg.agent_cfg.agent_type = mgc_ahb_v2_0_pkg::AHB_MASTER; + // Interface type + cfg.agent_cfg.if_type = mgc_ahb_v2_0_pkg::AHB_LITE; + // Master / Slave index + cfg.agent_cfg.index = 0; + // Use external decoder + cfg.agent_cfg.ext_decoder = 1'b0; + // Use external clock + cfg.agent_cfg.ext_clock = 1; + // Use external reset + cfg.agent_cfg.ext_reset = 1; + // Enable master coverage + cfg.agent_cfg.en_cvg.master = 1'b0; + // Enable slave coverage + cfg.agent_cfg.en_cvg.slave = 1'b0; + // Enable response coverage + cfg.agent_cfg.en_cvg.response = 1'b0; + // Enable arbitration coverage + cfg.agent_cfg.en_cvg.arbiter = 1'b0; + // Enable arbiter reset coverage + cfg.agent_cfg.en_cvg.arbiter_reset = 1'b0; + // Enable transaction logger + cfg.agent_cfg.en_logger.txn_log = 0; + // Enable beat logger + cfg.agent_cfg.en_logger.beat_log = 0; + // Transaction logger file name + cfg.agent_cfg.en_logger.txn_log_name = "txn.log"; + // Beat logger file name + cfg.agent_cfg.en_logger.beat_log_name = "beat.log"; + cfg.agent_cfg.en_logger.txn_column.tr = 1; + cfg.agent_cfg.en_logger.txn_column.addr = 1; + cfg.agent_cfg.en_logger.txn_column.nonseq_time = 1; + cfg.agent_cfg.en_logger.txn_column.data = 1; + cfg.agent_cfg.en_logger.txn_column.data_time = 1; + cfg.agent_cfg.en_logger.txn_column.resp = 1; + cfg.agent_cfg.en_logger.txn_column.len = 1; + cfg.agent_cfg.en_logger.txn_column.burst_type = 1; + cfg.agent_cfg.en_logger.txn_column.burst_size = 1; + cfg.agent_cfg.en_logger.txn_column.lock = 1; + cfg.agent_cfg.en_logger.txn_column.hsel = 1; + cfg.agent_cfg.en_logger.beat_column.nonseq_time = 1; + cfg.agent_cfg.en_logger.beat_column.ready_time = 1; + cfg.agent_cfg.en_logger.beat_column.dir_ph = 1; + cfg.agent_cfg.en_logger.beat_column.addr = 1; + cfg.agent_cfg.en_logger.beat_column.beat_num = 1; + cfg.agent_cfg.en_logger.beat_column.len = 1; + cfg.agent_cfg.en_logger.beat_column.data = 1; + cfg.agent_cfg.en_logger.beat_column.resp = 1; + cfg.agent_cfg.en_logger.beat_column.burst_type = 1; + cfg.agent_cfg.en_logger.beat_column.burst_size = 1; + cfg.agent_cfg.en_logger.beat_column.prot = 1; + cfg.agent_cfg.en_logger.beat_column.hsel = 1; + // Transaction logger data mask + cfg.agent_cfg.en_logger.txn_data_mask = 1; + // Beat logger data mask + cfg.agent_cfg.en_logger.beat_data_mask = 1; + // Enable clock period change logging + cfg.agent_cfg.en_logger.clk_mon = 0; + // Enable HSEL value printing + cfg.agent_cfg.en_logger.hsel_val = 1; + // Enable scoreboard + cfg.agent_cfg.en_sb = 1; + // Enable transaction listener + cfg.agent_cfg.en_txn_ltnr = 1'b0; + // Enable generic payload adapter + cfg.agent_cfg.en_rw_adapter = 1'b0; + cfg.agent_cfg.en_perf_stats.enable = 0; + cfg.agent_cfg.en_perf_stats.step = 100; + cfg.agent_cfg.en_perf_stats.multiple = 5; + cfg.agent_cfg.en_debug.arbiter_seq = 1'b0; + cfg.agent_cfg.en_debug.master_seq = 1'b0; + cfg.agent_cfg.en_debug.slave_seq = 1'b0; + cfg.agent_cfg.en_debug.vip_config = 1'b0; + // + // VIP Config setup configurations: + // + // + // + // Slave IDs for all slaves + cfg.slave_id = '{1{-1}}; + if ( addrm != null ) + begin + cfg.addr_map = addrm; + end + // + // VIP Config setup configurations at default value: + // // Enable warning for uninitialized reads + // cfg.m_warn_on_uninitialized_read = 1'b0; + // + + // + // BFM setup configurations at default value: + // // Maximum beats in increment burst + // cfg.m_bfm.config_max_incr_burst_beats = 32; + // // Default master number in environment + // cfg.m_bfm.config_default_master = 0; + // // Enables master to send new transfer after it receives error response + // cfg.m_bfm.config_master_idle_on_error = 1'b0; + // // Enables hready driven externally + // cfg.m_bfm.config_HREADYin_external = 1'b0; + // // If true, drives previous address when bus is IDLE + // cfg.m_bfm.config_address_on_idle = 1'b0; + // // Maximum number of successive wait states + cfg.m_bfm.config_max_wait_states_count = 67; + // // Data endianness + // cfg.m_bfm.config_endianness = AHB_LITTLE_ENDIAN; + // // Sets the domain + // cfg.m_bfm.config_domain = '{AHB_NUM_MASTERS{0}}; + // // Asserts HUNALIGN signal even if address is aligned with no sparse strobes + // cfg.m_bfm.config_assert_hunalign_high = 16'h0000; + // // Enables ahblite specification update features + // cfg.m_bfm.config_en_ahblite_spec_updt = 1'b0; + // // Enables signals to be stable for extended transfers + // cfg.m_bfm.config_en_stable_btw_clk = 1'b1; + // // Enables secure transfers + // cfg.m_bfm.config_en_sec_xfer = 1'b1; + // // Enables extended memory types + // cfg.m_bfm.config_en_ext_mem_types = 1'b1; + // // Enables multiple slave select signal + // cfg.m_bfm.config_en_mult_slv_sel = 1'b0; + // // Enables exclusive transfers + // cfg.m_bfm.config_en_excl_xfer = 1'b1; + // // Enables slave to drive default value of data for idle transfers + // cfg.m_bfm.config_slave_drive_default_value_idle = 1'b0; + // // Enable all protocol assertions + // cfg.m_bfm.config_enable_all_assertions = 1'b1; + // // Enable individual protocol assertion + // cfg.m_bfm.config_enable_assertion = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + // // Enables user data signals + // cfg.m_bfm.config_user_data_support = 1'b0; + // // Enables user address signals + // cfg.m_bfm.config_user_address_support = 1'b0; + // // Timeout for complete read/write transaction + // cfg.m_bfm.config_transaction_timeout_factor = 100000; + // // Arbitration timeout between request initiated by master to request completed + // cfg.m_bfm.config_arbitration_timeout_factor = 1000; + // cfg.m_bfm.config_clk_init_value = 1'b0; + // cfg.m_bfm.config_clk_phase_shift = QUESTA_MVC::questa_mvc_sv_convert_to_precision(0, QUESTA_MVC::QUESTA_MVC_TIME_X); + // cfg.m_bfm.config_clk_1st_time = QUESTA_MVC::questa_mvc_sv_convert_to_precision(5, QUESTA_MVC::QUESTA_MVC_TIME_X); + // cfg.m_bfm.config_clk_2nd_time = QUESTA_MVC::questa_mvc_sv_convert_to_precision(5, QUESTA_MVC::QUESTA_MVC_TIME_X); + // cfg.m_bfm.config_reset_low_clocks = 5; + // // Configures checking addr in addr_map + // cfg.m_bfm.check_addr_map = AHB_CHK_LEGAL; + // + + endfunction: configure + +endclass: ahb_lite_slave_0_config_policy + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..1b02e0122136eeb496069fe09f0f0386bc5030fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv @@ -0,0 +1,33 @@ +// +// File: qvip_ahb_lite_slave_params_pkg.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +package qvip_ahb_lite_slave_params_pkg; + import addr_map_pkg::*; + // + // Import the necessary QVIP packages: + // + import mgc_ahb_v2_0_pkg::*; + import mgc_ahb_seq_pkg::*; + class ahb_lite_slave_0_params; + localparam int AHB_NUM_MASTERS = 1; + localparam int AHB_NUM_MASTER_BITS = 1; + localparam int AHB_NUM_SLAVES = 1; + localparam int AHB_ADDRESS_WIDTH = 32; + localparam int AHB_WDATA_WIDTH = 32; + localparam int AHB_RDATA_WIDTH = 32; + endclass: ahb_lite_slave_0_params + + typedef ahb_vip_config #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS,ahb_lite_slave_0_params::AHB_NUM_SLAVES,ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH,ahb_lite_slave_0_params::AHB_WDATA_WIDTH,ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_lite_slave_0_cfg_t; + + typedef ahb_agent #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS,ahb_lite_slave_0_params::AHB_NUM_SLAVES,ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH,ahb_lite_slave_0_params::AHB_WDATA_WIDTH,ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_lite_slave_0_agent_t; + + typedef virtual mgc_ahb #(ahb_lite_slave_0_params::AHB_NUM_MASTERS,ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS,ahb_lite_slave_0_params::AHB_NUM_SLAVES,ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH,ahb_lite_slave_0_params::AHB_WDATA_WIDTH,ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_lite_slave_0_bfm_t; + + // + // `includes for the config policy classes: + // + `include "ahb_lite_slave_0_config_policy.svh" +endpackage: qvip_ahb_lite_slave_params_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/qvip_ahb_lite_slave_dir.cmd b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/qvip_ahb_lite_slave_dir.cmd new file mode 100644 index 0000000000000000000000000000000000000000..6d17d7d83ac4215612c6121752feda45f2b295cd --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/qvip_ahb_lite_slave_dir.cmd @@ -0,0 +1,36 @@ +// Version '20220406' +// Library '2022.2:04/20/2022:16:06' +"Configurator" create VIP_instance 2022.2:MGC/amba/ahb +"Configurator" change type ahb_lite_slave rename +"Configurator" change instance /top/ahb_lite_slave_0 agent ahb_lite_slave_0 +"Configurator" change variable agent.agent_type AHB_MASTER +"Configurator" sequence add ahb_lite_slave_0 ahb_single_rd_deparam_seq +"Configurator" sequence add ahb_lite_slave_0 ahb_single_wr_deparam_seq 0 +"Configurator" change instance /top/ahb_lite_slave_0 bfm +"Configurator" change instance /top/ahb_lite_slave_0 agent ahb_lite_slave_0 +"Configurator" change instance /top/ahb_lite_slave_0 rtl ahb_lite_slave_0 +"Configurator" change instance /top/ahb_lite_slave_0 agent ahb_lite_slave_0 +"Configurator" address_map create MEM +"Configurator" address_map create CSR +"Configurator" address_map create REG +"Configurator" change variable vip_config.addr_map MEM +"Configurator" address_map delete REG +"Configurator" address_map delete CSR +"Configurator" address_map delete MEM +"Configurator" address_map create MBOX +"Configurator" address_map MBOX add MAP_NORMAL,"MEM",0,MAP_NS,4'h0,64'h30000000,64'h20000,MEM_NORMAL,MAP_NORM_SEC_DATA +"Configurator" address_map MBOX add MAP_NORMAL,"CSR",1,MAP_NS,4'h0,64'h30030000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA +"Configurator" address_map MBOX add MAP_NORMAL,"CSR_",1,MAP_NS,4'h0,64'h30030000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA +"Configurator" address_map MBOX update MAP_NORMAL,"CSR",1,MAP_NS,4'h0,64'h30020000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA +"Configurator" address_map MBOX update MAP_NORMAL,"REG",2,MAP_NS,4'h0,64'h30030000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA +"Configurator" change variable vip_config.addr_map MBOX +"Configurator" change instance /top/default_clk_gen +"Configurator" change instance /top/default_reset_gen +"Configurator" change instance /top/ahb_lite_slave_0 +"Configurator" change instance /top/ahb_lite_slave_0 bfm +"Configurator" change instance /top/ahb_lite_slave_0 agent ahb_lite_slave_0 +"Configurator" change instance /top/ahb_lite_slave_0 rtl ahb_lite_slave_0 +"Configurator" change hash_param WDATA_WIDTH 64 +"Configurator" change hash_param RDATA_WIDTH 64 +// "Configurator" generate options +// Thu Nov 3 2022 21:32:42 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/Makefile b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..d2c21753280de6195a6ffa7f0d19209599d9c206 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/Makefile @@ -0,0 +1,105 @@ +#################### +# Common Setup. + +INCDIRS = +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + +incdir+../config_policies + +HVL_SV_SOURCE = ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + hvl_qvip_ahb_lite_slave.sv +HDL_SV_SOURCE = \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv + +UVM_OPTIONS = +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq + +#################### +# Questa support. + +all: work sv opt sim + +sv: hvl_sv hdl_sv + +vis: work sv vis_opt vis_sim + +work: + vlib work + +hvl_sv: + vlog $(INCDIRS) $(HVL_SV_SOURCE) + +hdl_sv: + vlog $(INCDIRS) $(HDL_SV_SOURCE) + +opt: + vopt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -o top_opt + +vis_opt: + vopt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -o top_opt -debug -designfile design.bin + +sim: + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -c -do "run -all; quit" + +vis_sim: + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -c -do "run -all; quit" -qwavedb=+signal+transaction+class+uvm_schematic + visualizer -designfile design.bin -wavefile qwave.db + +vis_int: work sv vis_opt + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -visualizer=design.bin -qwavedb=+signal+transaction+class+uvm_schematic + +gui: + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns + +#################### +# Incisive support. + +ius32: + env LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.3_ius:${IUS_HOME}/tools/cdsgcc/gcc/6.3/install/lib:${LD_LIBRARY_PATH} \ + xrun -sv -uvm -quiet -access +rwc -timescale 1ns/1ns $(INCDIRS) $(HVL_SV_SOURCE) $(HDL_SV_SOURCE) \ + -sv_root ${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.3_ius \ + -sv_lib libahb_IN_SystemVerilog_IUS_full \ + $(UVM_OPTIONS) + +ius64: + env LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.3_ius:${IUS_HOME}/tools/cdsgcc/gcc/6.3/install/lib64:${LD_LIBRARY_PATH} \ + xrun -sv -uvm -quiet -access +rwc -64bit -timescale 1ns/1ns $(INCDIRS) $(HVL_SV_SOURCE) $(HDL_SV_SOURCE) \ + -sv_root ${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.3_ius \ + -sv_lib libahb_IN_SystemVerilog_IUS_full \ + $(UVM_OPTIONS) + +#################### +# VCS support. + +vcs32: + env LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.2.0_vcs:${VCS_HOME}/gnu/linux/gcc-6.2.0/lib:${LD_LIBRARY_PATH} \ + vcs -sverilog -ntb_opts uvm -debug_access+w -quiet -timescale=1ns/1ns \ + -ld ${VCS_HOME}/gnu/linux/gcc-6.2.0/xbin/g++ \ + $(INCDIRS) $(HVL_SV_SOURCE) $(HDL_SV_SOURCE) \ + -syslib ${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.2.0_vcs/libahb_IN_SystemVerilog_VCS_full.so + env LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.2.0_vcs:${VCS_HOME}/gnu/linux/gcc-6.2.0/lib:${LD_LIBRARY_PATH} \ + ./simv $(UVM_OPTIONS) + +vcs64: + env LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs:${VCS_HOME}/gnu/linux/gcc-6.2.0/lib64:${LD_LIBRARY_PATH} \ + vcs -sverilog -ntb_opts uvm -debug_access+w -quiet -full64 -timescale=1ns/1ns \ + -ld ${VCS_HOME}/gnu/linux/gcc-6.2.0/xbin/g++ \ + $(INCDIRS) $(HVL_SV_SOURCE) $(HDL_SV_SOURCE) \ + -syslib ${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs/libahb_IN_SystemVerilog_VCS_full.so + env LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs:${VCS_HOME}/gnu/linux/gcc-6.2.0/lib64:${LD_LIBRARY_PATH} \ + ./simv $(UVM_OPTIONS) + +#################### +# Cleanup. + +clean: + rm -rf work transcript vsim.wlf + rm -rf csrc simv* ucli.key vc_hdrs.h + rm -rf INCA_libs xrun.log xrun.history + +.PHONY: all sv hvl_sv hdl_sv opt sim gui ius32 ius64 vcs32 vcs64 +.PHONY: vis vis_opt vis_sim vis_int diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ahb_lite_slave_0_sigs.do b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ahb_lite_slave_0_sigs.do new file mode 100644 index 0000000000000000000000000000000000000000..901be3a51da035153b11c9512806b6a490609040 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ahb_lite_slave_0_sigs.do @@ -0,0 +1,27 @@ +onerror resume +wave update off +wave tags F0 +wave spacer -backgroundcolor Salmon {AHB_LITE_SLAVE_0 Signals} +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_if -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HADDR -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HTRANS -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HWRITE -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HSIZE -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HWDATA -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HBURST -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HPROT -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HMASTLOCK -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HREADYOUT -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HRDATA -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HREADY -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HRESP -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HSEL -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HNONSEC -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HAUSER -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HWUSER -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HRUSER -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.mult_HSEL -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HEXCL -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HMASTER -tag F0 -radix hexadecimal +wave add hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.HEXOKAY -tag F0 -radix hexadecimal +wave update on diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ahb_lite_slave_0_txns.do b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ahb_lite_slave_0_txns.do new file mode 100644 index 0000000000000000000000000000000000000000..07aecb6db2be61af8d1790ab436ab3968c449d51 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ahb_lite_slave_0_txns.do @@ -0,0 +1,42 @@ +onerror resume +wave update off +wave tags F0 +wave spacer -group Transaction -backgroundcolor Salmon {AHB_LITE_SLAVE_0 Txns} +wave group Transaction -backgroundcolor #004466 +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.burst_transfer -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.single_transfer -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_request_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_control_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_wr_data_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.user_data_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.user_address_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_rd_data_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_response_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_control_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_wr_data_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.user_data_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.user_address_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.master_rd_data_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_single_transfer -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_control_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_wr_data_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_user_data_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_user_address_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_rd_data_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_response_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_response_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.slave_hsplit_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbitration -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbiter_request_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbiter_grant_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbiter_control_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.core_control_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.core_response_phase -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.core_control_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbiter_request_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbiter_grant_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.arbiter_control_cycle -tag F0 -radix string +wave add -group Transaction hdl_qvip_ahb_lite_slave.ahb_lite_slave_0.ahb_lite_slave_0_bfm.core_response_cycle -tag F0 -radix string +wave insertion [expr [wave index insertpoint] + 1] +wave update on +WaveSetStreamView diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/default_clk_gen.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/default_clk_gen.sv new file mode 100644 index 0000000000000000000000000000000000000000..f3727aae4edba57abf83e4cbf0bd3bf4a5fba99c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/default_clk_gen.sv @@ -0,0 +1,25 @@ +// +// File: default_clk_gen.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +module default_clk_gen +( + output reg CLK +); + + timeunit 1ns; + timeprecision 1ns; + + initial + begin + CLK = 0; + forever + begin + #1 CLK = ~CLK; + end + end + + +endmodule: default_clk_gen diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/default_reset_gen.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/default_reset_gen.sv new file mode 100644 index 0000000000000000000000000000000000000000..534329e8a97725d7d91f32b028c4ca75d6c3787f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/default_reset_gen.sv @@ -0,0 +1,28 @@ +// +// File: default_reset_gen.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +module default_reset_gen +( + output reg RESET, + input reg CLK_IN +); + + initial + begin + RESET = 1; + + RESET = ~RESET; + + repeat ( 2 ) + begin + @(posedge CLK_IN); + end + + RESET = ~RESET; + end + + +endmodule: default_reset_gen diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/hdl_qvip_ahb_lite_slave.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/hdl_qvip_ahb_lite_slave.sv new file mode 100644 index 0000000000000000000000000000000000000000..cea1e798b977881a30c23586c9e658477dcc3827 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/hdl_qvip_ahb_lite_slave.sv @@ -0,0 +1,87 @@ +// +// File: hdl_qvip_ahb_lite_slave.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +//Time resolution of '1ns' will be used (See Makefiles and scripts) +module hdl_qvip_ahb_lite_slave; + import uvm_pkg::*; + import qvip_ahb_lite_slave_params_pkg::*; + wire default_clk_gen_CLK; + wire default_reset_gen_RESET; + wire [(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH-1):0] ahb_lite_slave_0_HADDR; + wire [1:0] ahb_lite_slave_0_HTRANS; + wire ahb_lite_slave_0_HWRITE; + wire [2:0] ahb_lite_slave_0_HSIZE; + wire [(ahb_lite_slave_0_params::AHB_WDATA_WIDTH-1):0] ahb_lite_slave_0_HWDATA; + wire [2:0] ahb_lite_slave_0_HBURST; + wire [6:0] ahb_lite_slave_0_HPROT; + wire ahb_lite_slave_0_HMASTLOCK; + wire ahb_lite_slave_0_HREADYOUT; + wire [(ahb_lite_slave_0_params::AHB_RDATA_WIDTH-1):0] ahb_lite_slave_0_HRDATA; + wire ahb_lite_slave_0_HREADY; + wire ahb_lite_slave_0_HRESP; + wire ahb_lite_slave_0_HSEL; + wire ahb_lite_slave_0_HNONSEC; + wire [63:0] ahb_lite_slave_0_HAUSER; + wire [63:0] ahb_lite_slave_0_HWUSER; + wire [63:0] ahb_lite_slave_0_HRUSER; + wire [15:0] ahb_lite_slave_0_mult_HSEL; + wire ahb_lite_slave_0_HEXCL; + wire [15:0] ahb_lite_slave_0_HMASTER; + wire ahb_lite_slave_0_HEXOKAY; + + mgc_ahb #(.AHB_NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS),.AHB_NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS),.AHB_NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES),.AHB_ADDRESS_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH),.AHB_WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH),.AHB_RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH))ahb_lite_slave_0_bfm(.iHCLK(default_clk_gen_CLK),.iHRESETn(default_reset_gen_RESET)); + + ahb_lite_slave + #( + .NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS), + .NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS), + .NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES), + .ADDR_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH), + .WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH), + .RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH), + .SLAVE_INDEX(0) + ) + ahb_lite_slave_0 + ( + .ahb_if(ahb_lite_slave_0_bfm), + .HADDR(ahb_lite_slave_0_HADDR), + .HTRANS(ahb_lite_slave_0_HTRANS), + .HWRITE(ahb_lite_slave_0_HWRITE), + .HSIZE(ahb_lite_slave_0_HSIZE), + .HWDATA(ahb_lite_slave_0_HWDATA), + .HBURST(ahb_lite_slave_0_HBURST), + .HPROT(ahb_lite_slave_0_HPROT), + .HMASTLOCK(ahb_lite_slave_0_HMASTLOCK), + .HREADYOUT(ahb_lite_slave_0_HREADYOUT), + .HRDATA(ahb_lite_slave_0_HRDATA), + .HREADY(ahb_lite_slave_0_HREADY), + .HRESP(ahb_lite_slave_0_HRESP), + .HSEL(ahb_lite_slave_0_HSEL), + .HNONSEC(ahb_lite_slave_0_HNONSEC), + .HAUSER(ahb_lite_slave_0_HAUSER), + .HWUSER(ahb_lite_slave_0_HWUSER), + .HRUSER(ahb_lite_slave_0_HRUSER), + .mult_HSEL(ahb_lite_slave_0_mult_HSEL), + .HEXCL(ahb_lite_slave_0_HEXCL), + .HMASTER(ahb_lite_slave_0_HMASTER), + .HEXOKAY(ahb_lite_slave_0_HEXOKAY) + ); + + initial + begin + uvm_config_db #(ahb_lite_slave_0_bfm_t)::set(null,"uvm_test_top","ahb_lite_slave_0",ahb_lite_slave_0_bfm); + end + default_clk_gen default_clk_gen + ( + .CLK(default_clk_gen_CLK) + ); + default_reset_gen default_reset_gen + ( + .RESET(default_reset_gen_RESET), + .CLK_IN(default_clk_gen_CLK) + ); + +endmodule: hdl_qvip_ahb_lite_slave diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/hvl_qvip_ahb_lite_slave.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/hvl_qvip_ahb_lite_slave.sv new file mode 100644 index 0000000000000000000000000000000000000000..6169a94f3af078baa61e0c802d60e62fe217b3e5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/hvl_qvip_ahb_lite_slave.sv @@ -0,0 +1,17 @@ +// +// File: hvl_qvip_ahb_lite_slave.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +module hvl_qvip_ahb_lite_slave; + import uvm_pkg::*; + + `include "test_packages.svh" + + initial + begin + run_test(); + end + +endmodule: hvl_qvip_ahb_lite_slave diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ius_run_32 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ius_run_32 new file mode 100644 index 0000000000000000000000000000000000000000..4b12b015bc5b45683317d57bccc16a4815843d05 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ius_run_32 @@ -0,0 +1,22 @@ +#!/bin/bash + +LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.3_ius:${IUS_HOME}/tools/cdsgcc/gcc/6.3/install/lib:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH + +xrun -sv -uvm -quiet -access +rwc -timescale 1ns/1ns \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + +incdir+../config_policies \ + ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv \ + hvl_qvip_ahb_lite_slave.sv \ + -sv_root ${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.3_ius \ + -sv_lib libahb_IN_SystemVerilog_IUS_full \ + +UVM_TESTNAME=qvip_ahb_lite_slave_test_base \ + +SEQ=qvip_ahb_lite_slave_example_vseq diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ius_run_64 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ius_run_64 new file mode 100644 index 0000000000000000000000000000000000000000..a31216173d67e1ad019f52f0f6528c741528bac1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/ius_run_64 @@ -0,0 +1,22 @@ +#!/bin/bash + +LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.3_ius:${IUS_HOME}/tools/cdsgcc/gcc/6.3/install/lib64:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH + +xrun -sv -uvm -quiet -access +rwc -64bit -timescale 1ns/1ns \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + +incdir+../config_policies \ + ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv \ + hvl_qvip_ahb_lite_slave.sv \ + -sv_root ${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.3_ius \ + -sv_lib libahb_IN_SystemVerilog_IUS_full \ + +UVM_TESTNAME=qvip_ahb_lite_slave_test_base \ + +SEQ=qvip_ahb_lite_slave_example_vseq diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qrun_32.f b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qrun_32.f new file mode 100644 index 0000000000000000000000000000000000000000..8728aac7ab05475451145193b73e9b4471295b08 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qrun_32.f @@ -0,0 +1,19 @@ +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv ++incdir+../config_policies ../config_policies/qvip_ahb_lite_slave_params_pkg.sv +qvip_ahb_lite_slave_pkg.sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +default_clk_gen.sv +default_reset_gen.sv +hdl_qvip_ahb_lite_slave.sv +hvl_qvip_ahb_lite_slave.sv +-debug +-designfile design.bin +-c +-mvchome ${QUESTA_MVC_HOME} ++nowarnTSCALE -t 1ns +-do "run -all; quit" ++UVM_TESTNAME=qvip_ahb_lite_slave_test_base ++SEQ=qvip_ahb_lite_slave_example_vseq +-qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qrun_64.f b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qrun_64.f new file mode 100644 index 0000000000000000000000000000000000000000..c7cc3e66d2edd2f13390c1cab78090c228263687 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qrun_64.f @@ -0,0 +1,20 @@ +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv ++incdir+../config_policies ../config_policies/qvip_ahb_lite_slave_params_pkg.sv +qvip_ahb_lite_slave_pkg.sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +default_clk_gen.sv +default_reset_gen.sv +hdl_qvip_ahb_lite_slave.sv +hvl_qvip_ahb_lite_slave.sv +-64 +-debug +-designfile design.bin +-c +-mvchome ${QUESTA_MVC_HOME} ++nowarnTSCALE -t 1ns +-do "run -all; quit" ++UVM_TESTNAME=qvip_ahb_lite_slave_test_base ++SEQ=qvip_ahb_lite_slave_example_vseq +-qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/questa_run_32 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/questa_run_32 new file mode 100644 index 0000000000000000000000000000000000000000..a41be0913bcdb2502aff7d4d4db34c1b3618c975 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/questa_run_32 @@ -0,0 +1,19 @@ +echo "Setting up work directory" +vlib work + +vlog ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + +incdir+../config_policies ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv \ + hvl_qvip_ahb_lite_slave.sv + +echo "Optimisation step" +vopt -o top_opt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -debug -designfile design.bin + +echo "Running test" +vsim -c -mvchome ${QUESTA_MVC_HOME} top_opt +nowarnTSCALE -t 1ns -do "run -all; quit" +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq -qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/questa_run_64 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/questa_run_64 new file mode 100644 index 0000000000000000000000000000000000000000..430abf19f321b67431ced630cebcc6b033eb0712 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/questa_run_64 @@ -0,0 +1,19 @@ +echo "Setting up work directory" +vlib work + +vlog ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + +incdir+../config_policies ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv \ + hvl_qvip_ahb_lite_slave.sv + +echo "Optimisation step" +vopt -64 -o top_opt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -debug -designfile design.bin + +echo "Running test" +vsim -c -64 -mvchome ${QUESTA_MVC_HOME} top_opt +nowarnTSCALE -t 1ns -do "run -all; quit" +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq -qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_env.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_env.svh new file mode 100644 index 0000000000000000000000000000000000000000..bcfce9cbcd34ee3d3fb42bf8f29284fd9686c0d6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_env.svh @@ -0,0 +1,44 @@ +// +// File: qvip_ahb_lite_slave_env.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +`include "uvm_macros.svh" +class qvip_ahb_lite_slave_env extends uvm_env; + `uvm_component_utils(qvip_ahb_lite_slave_env) + qvip_ahb_lite_slave_env_config cfg; + // Agent handles + + ahb_lite_slave_0_agent_t ahb_lite_slave_0; + function new + ( + string name = "qvip_ahb_lite_slave_env", + uvm_component parent = null + ); + super.new(name, parent); + endfunction + + extern function void build_phase + ( + uvm_phase phase + ); + +endclass: qvip_ahb_lite_slave_env + +function void qvip_ahb_lite_slave_env::build_phase +( + uvm_phase phase +); + if ( cfg == null ) + begin + if ( !uvm_config_db #(qvip_ahb_lite_slave_env_config)::get(this, "", "env_config", cfg) ) + begin + `uvm_error("build_phase", "Unable to find the env config object in the uvm_config_db") + end + end + ahb_lite_slave_0 = ahb_lite_slave_0_agent_t::type_id::create("ahb_lite_slave_0", this ); + ahb_lite_slave_0.set_mvc_config(cfg.ahb_lite_slave_0_cfg); + +endfunction: build_phase + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_env_config.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_env_config.svh new file mode 100644 index 0000000000000000000000000000000000000000..876a6e1046bd8191638814794b1f0a26115a2458 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_env_config.svh @@ -0,0 +1,39 @@ +// +// File: qvip_ahb_lite_slave_env_config.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class qvip_ahb_lite_slave_env_config extends uvm_object; + `uvm_object_utils(qvip_ahb_lite_slave_env_config) + // Handles for vip config for each of the QVIP instances + + ahb_lite_slave_0_cfg_t ahb_lite_slave_0_cfg; + // Handles for address maps + + address_map MBOX; + + function new + ( + string name = "qvip_ahb_lite_slave_env_config" + ); + super.new(name); + endfunction + + extern function void initialize; + +endclass: qvip_ahb_lite_slave_env_config + +function void qvip_ahb_lite_slave_env_config::initialize; + begin + addr_map_entry_s addr_map_entries[] = new [3]; + addr_map_entries = '{ + '{MAP_NORMAL,"MEM",0,MAP_NS,4'h0,64'h30000000,64'h20000,MEM_NORMAL,MAP_NORM_SEC_DATA}, + '{MAP_NORMAL,"CSR",1,MAP_NS,4'h0,64'h30020000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA}, + '{MAP_NORMAL,"REG",2,MAP_NS,4'h0,64'h30030000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA}}; + MBOX = address_map::type_id::create("MBOX_addr_map"); + MBOX.addr_mask = 64'hFFF; + MBOX.set( addr_map_entries ); + end +endfunction: initialize + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_example_vseq.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_example_vseq.svh new file mode 100644 index 0000000000000000000000000000000000000000..032215726b020e3811ec5ad0510ae7d2394ee2e5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_example_vseq.svh @@ -0,0 +1,33 @@ +// +// File: qvip_ahb_lite_slave_example_vseq.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +// The purpose of this example virtual sequence is to show how the default or selected sequences for +// each QVIP can be run. The sequences are run in series in an arbitary order. +class qvip_ahb_lite_slave_example_vseq extends qvip_ahb_lite_slave_vseq_base; + `uvm_object_utils(qvip_ahb_lite_slave_example_vseq) + function new + ( + string name = "qvip_ahb_lite_slave_example_vseq" + ); + super.new(name); + endfunction + + extern task body; + +endclass: qvip_ahb_lite_slave_example_vseq + +task qvip_ahb_lite_slave_example_vseq::body; + ahb_single_wr_deparam_seq ahb_lite_slave_0_seq_0 = ahb_single_wr_deparam_seq::type_id::create("ahb_single_wr_deparam_seq"); + ahb_single_rd_deparam_seq ahb_lite_slave_0_seq_1 = ahb_single_rd_deparam_seq::type_id::create("ahb_single_rd_deparam_seq"); + + // Sequences run in the following order + + begin + ahb_lite_slave_0_seq_0.start(ahb_lite_slave_0); + ahb_lite_slave_0_seq_1.start(ahb_lite_slave_0); + end +endtask: body + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..2c3afe3b5c22a6cc903d1a5e15e0c2ca194f4ca9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_pkg.sv @@ -0,0 +1,24 @@ +// +// File: qvip_ahb_lite_slave_pkg.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +package qvip_ahb_lite_slave_pkg; + import uvm_pkg::*; + + `include "uvm_macros.svh" + + import addr_map_pkg::*; + + import qvip_ahb_lite_slave_params_pkg::*; + import mvc_pkg::*; + import mgc_ahb_seq_pkg::*; + import mgc_ahb_v2_0_pkg::*; + + `include "qvip_ahb_lite_slave_env_config.svh" + `include "qvip_ahb_lite_slave_env.svh" + `include "qvip_ahb_lite_slave_vseq_base.svh" + `include "qvip_ahb_lite_slave_test_base.svh" + `include "qvip_ahb_lite_slave_example_vseq.svh" +endpackage: qvip_ahb_lite_slave_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_test_base.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_test_base.svh new file mode 100644 index 0000000000000000000000000000000000000000..1223fe598ec2b527ab085ea39f5d23504ab31ce3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_test_base.svh @@ -0,0 +1,104 @@ +// +// File: qvip_ahb_lite_slave_test_base.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class qvip_ahb_lite_slave_test_base extends uvm_test; + `uvm_component_utils(qvip_ahb_lite_slave_test_base) + // QVIP Configuration objects = As defined in the qvip_ahb_lite_slave_params_pkg + + ahb_lite_slave_0_cfg_t ahb_lite_slave_0_cfg; + // Environment configuration object + qvip_ahb_lite_slave_env_config env_cfg; + + // Environment component + qvip_ahb_lite_slave_env env; + function new + ( + string name = "qvip_ahb_lite_slave_test_base_test_base", + uvm_component parent = null + ); + super.new(name, parent); + endfunction + + extern function void init_vseq + ( + qvip_ahb_lite_slave_vseq_base vseq + ); + + extern function void build_phase + ( + uvm_phase phase + ); + + extern task run_phase + ( + uvm_phase phase + ); + +endclass: qvip_ahb_lite_slave_test_base + +function void qvip_ahb_lite_slave_test_base::init_vseq +( + qvip_ahb_lite_slave_vseq_base vseq +); + vseq.ahb_lite_slave_0 = env.ahb_lite_slave_0.m_sequencer; +endfunction: init_vseq + +function void qvip_ahb_lite_slave_test_base::build_phase +( + uvm_phase phase +); + env_cfg = qvip_ahb_lite_slave_env_config::type_id::create("env_cfg"); + env_cfg.initialize(); + + ahb_lite_slave_0_cfg = ahb_lite_slave_0_cfg_t::type_id::create("ahb_lite_slave_0_cfg" ); + if ( !uvm_config_db #(ahb_lite_slave_0_bfm_t)::get(this, "", "ahb_lite_slave_0", ahb_lite_slave_0_cfg.m_bfm) ) + begin + `uvm_error("build_phase", "Unable to get virtual interface ahb_lite_slave_0 for ahb_lite_slave_0_cfg from uvm_config_db") + end + ahb_lite_slave_0_config_policy::configure(ahb_lite_slave_0_cfg, env_cfg.MBOX); + env_cfg.ahb_lite_slave_0_cfg = ahb_lite_slave_0_cfg; + + // Once the agent configuration objects are done build the env + env = qvip_ahb_lite_slave_env::type_id::create("env", this); + env.cfg = env_cfg; +endfunction: build_phase + +task qvip_ahb_lite_slave_test_base::run_phase +( + uvm_phase phase +); + string sequence_name; + qvip_ahb_lite_slave_vseq_base vseq; + uvm_object obj; + uvm_cmdline_processor clp; + uvm_factory factory; + clp = uvm_cmdline_processor::get_inst(); + factory = uvm_factory::get(); + if ( clp.get_arg_value("+SEQ=", sequence_name) == 0 ) + begin + `uvm_fatal(get_type_name(), "You must specify a virtual sequence to run using the +SEQ plusarg") + end + obj = factory.create_object_by_name(sequence_name); + if ( obj == null ) + begin + factory.print(); + `uvm_fatal(get_type_name(), {"Virtual sequence '",sequence_name,"' not found in factory"}) + end + + if ( !$cast(vseq, obj) ) + begin + `uvm_fatal(get_type_name(), {"Virtual sequence '",sequence_name,"' is not derived from qvip_ahb_lite_slave_vseq_base"}) + end + + //The sequence is OK to run + `uvm_info(get_type_name(), {"Running virtual sequence '",sequence_name,"'"}, UVM_LOW) + + phase.raise_objection(this); + init_vseq(vseq); + vseq.start(null); + phase.drop_objection(this); +endtask: run_phase + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_vseq_base.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_vseq_base.svh new file mode 100644 index 0000000000000000000000000000000000000000..7770cf8dcf4062f2c7e73831583eed41acddaedc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/qvip_ahb_lite_slave_vseq_base.svh @@ -0,0 +1,23 @@ +// +// File: qvip_ahb_lite_slave_vseq_base.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class qvip_ahb_lite_slave_vseq_base extends uvm_sequence; + `uvm_object_utils(qvip_ahb_lite_slave_vseq_base) + // Handles for each of the target (QVIP) sequencers + + mvc_sequencer ahb_lite_slave_0; + function new + ( + string name = "qvip_ahb_lite_slave_vseq_base" + ); + super.new(name); + endfunction + + task body; + endtask: body + +endclass: qvip_ahb_lite_slave_vseq_base + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/test_packages.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/test_packages.svh new file mode 100644 index 0000000000000000000000000000000000000000..b0baa5fccbd9c62f5d80dfcdb6ebd15e40e036c7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/test_packages.svh @@ -0,0 +1,10 @@ +// +// File: test_packages.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// + +import qvip_ahb_lite_slave_pkg::*; + +// Add other packages here as required diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/vcs_run_32 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/vcs_run_32 new file mode 100644 index 0000000000000000000000000000000000000000..04f3bde902945085ebde2c1b4dd19a14f171a1fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/vcs_run_32 @@ -0,0 +1,22 @@ +#!/bin/bash + +LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.2.0_vcs:${VCS_HOME}/gnu/linux/gcc-6.2.0/lib:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH + +vcs -sverilog -ntb_opts uvm -debug_access+w -quiet -timescale=1ns/1ns \ + -ld ${VCS_HOME}/gnu/linux/gcc-6.2.0/xbin/g++ \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + +incdir+../config_policies \ + ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv \ + hvl_qvip_ahb_lite_slave.sv \ + -syslib ${QUESTA_MVC_HOME}/questa_mvc_core/linux_gcc-6.2.0_vcs/libahb_IN_SystemVerilog_VCS_full.so + +./simv +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/vcs_run_64 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/vcs_run_64 new file mode 100644 index 0000000000000000000000000000000000000000..bccac8abc2d2eb2fa2c330c1d9e6ef6ecbafa5ca --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvm_tb/vcs_run_64 @@ -0,0 +1,22 @@ +#!/bin/bash + +LD_LIBRARY_PATH=${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs:${VCS_HOME}/gnu/linux/gcc-6.2.0/lib64:${LD_LIBRARY_PATH} +export LD_LIBRARY_PATH + +vcs -sverilog -ntb_opts uvm -debug_access+w -quiet -full64 -timescale=1ns/1ns \ + -ld ${VCS_HOME}/gnu/linux/gcc-6.2.0/xbin/g++ \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + ${QUESTA_MVC_HOME}/include/questa_mvc_svapi.sv \ + +define+MAP_PROT_ATTR ${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv \ + +incdir+../config_policies \ + ../config_policies/qvip_ahb_lite_slave_params_pkg.sv \ + qvip_ahb_lite_slave_pkg.sv \ + +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv \ + default_clk_gen.sv \ + default_reset_gen.sv \ + hdl_qvip_ahb_lite_slave.sv \ + hvl_qvip_ahb_lite_slave.sv \ + -syslib ${QUESTA_MVC_HOME}/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs/libahb_IN_SystemVerilog_VCS_full.so + +./simv +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv new file mode 100644 index 0000000000000000000000000000000000000000..f3727aae4edba57abf83e4cbf0bd3bf4a5fba99c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv @@ -0,0 +1,25 @@ +// +// File: default_clk_gen.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +module default_clk_gen +( + output reg CLK +); + + timeunit 1ns; + timeprecision 1ns; + + initial + begin + CLK = 0; + forever + begin + #1 CLK = ~CLK; + end + end + + +endmodule: default_clk_gen diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv new file mode 100644 index 0000000000000000000000000000000000000000..534329e8a97725d7d91f32b028c4ca75d6c3787f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv @@ -0,0 +1,28 @@ +// +// File: default_reset_gen.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +module default_reset_gen +( + output reg RESET, + input reg CLK_IN +); + + initial + begin + RESET = 1; + + RESET = ~RESET; + + repeat ( 2 ) + begin + @(posedge CLK_IN); + end + + RESET = ~RESET; + end + + +endmodule: default_reset_gen diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv new file mode 100644 index 0000000000000000000000000000000000000000..aba002df82771aaa90bb4e753b69d670ab43f393 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv @@ -0,0 +1,149 @@ +// +// File: hdl_qvip_ahb_lite_slave.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +//Time resolution of '1ns' will be used (See Makefiles and scripts) +module hdl_qvip_ahb_lite_slave; + parameter UNIQUE_ID = ""; + parameter AHB_LITE_SLAVE_0_ACTIVE = 1; + parameter EXT_CLK_RESET = 0; + import uvm_pkg::*; + import qvip_ahb_lite_slave_params_pkg::*; + wire default_clk_gen_CLK; + wire default_reset_gen_RESET; + wire [(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH-1):0] ahb_lite_slave_0_HADDR; + wire [1:0] ahb_lite_slave_0_HTRANS; + wire ahb_lite_slave_0_HWRITE; + wire [2:0] ahb_lite_slave_0_HSIZE; + wire [(ahb_lite_slave_0_params::AHB_WDATA_WIDTH-1):0] ahb_lite_slave_0_HWDATA; + wire [2:0] ahb_lite_slave_0_HBURST; + wire [6:0] ahb_lite_slave_0_HPROT; + wire ahb_lite_slave_0_HMASTLOCK; + wire ahb_lite_slave_0_HREADYOUT; + wire [(ahb_lite_slave_0_params::AHB_RDATA_WIDTH-1):0] ahb_lite_slave_0_HRDATA; + wire ahb_lite_slave_0_HREADY; + wire ahb_lite_slave_0_HRESP; + wire ahb_lite_slave_0_HSEL; + wire ahb_lite_slave_0_HNONSEC; + wire [63:0] ahb_lite_slave_0_HAUSER; + wire [63:0] ahb_lite_slave_0_HWUSER; + wire [63:0] ahb_lite_slave_0_HRUSER; + wire [15:0] ahb_lite_slave_0_mult_HSEL; + wire ahb_lite_slave_0_HEXCL; + wire [15:0] ahb_lite_slave_0_HMASTER; + wire ahb_lite_slave_0_HEXOKAY; + + mgc_ahb #(.AHB_NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS),.AHB_NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS),.AHB_NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES),.AHB_ADDRESS_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH),.AHB_WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH),.AHB_RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH))ahb_lite_slave_0_bfm(.iHCLK(default_clk_gen_CLK),.iHRESETn(default_reset_gen_RESET)); + + + initial + begin + uvm_config_db #(ahb_lite_slave_0_bfm_t)::set(null,"UVMF_VIRTUAL_INTERFACES",{UNIQUE_ID,"ahb_lite_slave_0"},ahb_lite_slave_0_bfm); + end + generate + if ( EXT_CLK_RESET == 0 ) + begin: generate_internal_clk_rst + default_clk_gen default_clk_gen + ( + .CLK(default_clk_gen_CLK) + ); + default_reset_gen default_reset_gen + ( + .RESET(default_reset_gen_RESET), + .CLK_IN(default_clk_gen_CLK) + ); + end + endgenerate + generate + if ( AHB_LITE_SLAVE_0_ACTIVE ) + begin: generate_active_ahb_lite_slave_0 + ahb_lite_slave + #( + .NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS), + .NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS), + .NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES), + .ADDR_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH), + .WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH), + .RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH), + .SLAVE_INDEX(0) + ) + ahb_lite_slave_0 + ( + .ahb_if(ahb_lite_slave_0_bfm), + .HADDR(ahb_lite_slave_0_HADDR), + .HTRANS(ahb_lite_slave_0_HTRANS), + .HWRITE(ahb_lite_slave_0_HWRITE), + .HSIZE(ahb_lite_slave_0_HSIZE), + .HWDATA(ahb_lite_slave_0_HWDATA), + .HBURST(ahb_lite_slave_0_HBURST), + .HPROT(ahb_lite_slave_0_HPROT), + .HMASTLOCK(ahb_lite_slave_0_HMASTLOCK), + .HREADYOUT(ahb_lite_slave_0_HREADYOUT), + .HRDATA(ahb_lite_slave_0_HRDATA), + .HREADY(ahb_lite_slave_0_HREADY), + .HRESP(ahb_lite_slave_0_HRESP), + .HSEL(ahb_lite_slave_0_HSEL), + .HNONSEC(ahb_lite_slave_0_HNONSEC), + .HAUSER(ahb_lite_slave_0_HAUSER), + .HWUSER(ahb_lite_slave_0_HWUSER), + .HRUSER(ahb_lite_slave_0_HRUSER), + .mult_HSEL(ahb_lite_slave_0_mult_HSEL), + .HEXCL(ahb_lite_slave_0_HEXCL), + .HMASTER(ahb_lite_slave_0_HMASTER), + .HEXOKAY(ahb_lite_slave_0_HEXOKAY) + ); + end + else + begin: generate_passive_ahb_lite_slave_0_monitor + logic [(ahb_lite_slave_0_params::AHB_RDATA_WIDTH-1):0] unpacked_HRDATA [ahb_lite_slave_0_params::AHB_NUM_SLAVES]; + logic unpacked_HREADY [ahb_lite_slave_0_params::AHB_NUM_SLAVES]; + logic unpacked_HRESP [ahb_lite_slave_0_params::AHB_NUM_SLAVES]; + logic unpacked_HSEL [ahb_lite_slave_0_params::AHB_NUM_SLAVES]; + logic [15:0] unpacked_mult_HSEL[ahb_lite_slave_0_params::AHB_NUM_SLAVES]; + logic unpacked_HEXOKAY [ahb_lite_slave_0_params::AHB_NUM_SLAVES]; + assign unpacked_HRDATA [0] = ahb_lite_slave_0_HRDATA; + assign unpacked_HREADY [0] = ahb_lite_slave_0_HREADY; + assign unpacked_HRESP [0] = ahb_lite_slave_0_HRESP; + assign unpacked_HSEL [0] = ahb_lite_slave_0_HSEL; + assign unpacked_mult_HSEL[0] = ahb_lite_slave_0_mult_HSEL; + assign unpacked_HEXOKAY [0] = ahb_lite_slave_0_HEXOKAY; + ahb_lite_monitor + #( + .NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS), + .NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS), + .NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES), + .ADDR_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH), + .WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH), + .RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH) + ) + ahb_lite_slave_0 + ( + .ahb_if(ahb_lite_slave_0_bfm), + .HADDR(ahb_lite_slave_0_HADDR), + .HTRANS(ahb_lite_slave_0_HTRANS), + .HWRITE(ahb_lite_slave_0_HWRITE), + .HSIZE(ahb_lite_slave_0_HSIZE), + .HWDATA(ahb_lite_slave_0_HWDATA), + .HBURST(ahb_lite_slave_0_HBURST), + .HPROT(ahb_lite_slave_0_HPROT), + .HMASTLOCK(ahb_lite_slave_0_HMASTLOCK), +// .HREADYOUT(ahb_lite_slave_0_HREADYOUT), + .HRDATA(unpacked_HRDATA), + .HREADY(unpacked_HREADY), + .HRESP(unpacked_HRESP), + .HSEL(unpacked_HSEL), + .HNONSEC(ahb_lite_slave_0_HNONSEC), + .HAUSER(ahb_lite_slave_0_HAUSER), + .HWUSER(ahb_lite_slave_0_HWUSER), + .HRUSER(ahb_lite_slave_0_HRUSER), + .mult_HSEL(unpacked_mult_HSEL), + .HEXCL(ahb_lite_slave_0_HEXCL), + .HMASTER(ahb_lite_slave_0_HMASTER), + .HEXOKAY(unpacked_HEXOKAY) + ); + end + endgenerate + +endmodule: hdl_qvip_ahb_lite_slave diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hvl_qvip_ahb_lite_slave.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hvl_qvip_ahb_lite_slave.sv new file mode 100644 index 0000000000000000000000000000000000000000..6169a94f3af078baa61e0c802d60e62fe217b3e5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hvl_qvip_ahb_lite_slave.sv @@ -0,0 +1,17 @@ +// +// File: hvl_qvip_ahb_lite_slave.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +module hvl_qvip_ahb_lite_slave; + import uvm_pkg::*; + + `include "test_packages.svh" + + initial + begin + run_test(); + end + +endmodule: hvl_qvip_ahb_lite_slave diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_env_configuration.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_env_configuration.svh new file mode 100644 index 0000000000000000000000000000000000000000..01ec867872de49bc6ab53347e6605d6b3bec536c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_env_configuration.svh @@ -0,0 +1,76 @@ +// +// File: qvip_ahb_lite_slave_env_configuration.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class qvip_ahb_lite_slave_env_configuration extends uvmf_environment_configuration_base; + `uvm_object_utils(qvip_ahb_lite_slave_env_configuration) + // Handles for vip config for each of the QVIP instances + + ahb_lite_slave_0_cfg_t ahb_lite_slave_0_cfg; + // Handles for address maps + + address_map MBOX; + + function new + ( + string name = "qvip_ahb_lite_slave_env_configuration" + ); + super.new(name); + ahb_lite_slave_0_cfg = ahb_lite_slave_0_cfg_t::type_id::create("ahb_lite_slave_0_cfg"); + endfunction + + virtual function string convert2string; + return {"qvip_ahb_lite_slave_env_configuration:",ahb_lite_slave_0_cfg.convert2string()}; + endfunction: convert2string + + extern function void initialize + ( + uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + +endclass: qvip_ahb_lite_slave_env_configuration + +function void qvip_ahb_lite_slave_env_configuration::initialize +( + uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} +); + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + if ( !uvm_config_db #(ahb_lite_slave_0_bfm_t)::get( null, "UVMF_VIRTUAL_INTERFACES", interface_names[0], ahb_lite_slave_0_cfg.m_bfm ) ) + begin + `uvm_fatal("Config Error", $sformatf("uvm_config_db #(ahb_lite_slave_0_bfm_t)::get() cannot find bfm vif handle for agent with interface_name '%s'", interface_names[0])) + end + + begin + addr_map_entry_s addr_map_entries[] = new [3]; + addr_map_entries = '{ + '{MAP_NORMAL,"MEM",0,MAP_NS,4'h0,64'h30000000,64'h20000,MEM_NORMAL,MAP_NORM_SEC_DATA}, + '{MAP_NORMAL,"CSR",1,MAP_NS,4'h0,64'h30020000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA}, + '{MAP_NORMAL,"REG",2,MAP_NS,4'h0,64'h30030000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA}}; + MBOX = address_map::type_id::create("MBOX_addr_map"); + MBOX.addr_mask = 64'hFFF; + MBOX.set( addr_map_entries ); + end + + ahb_lite_slave_0_config_policy::configure(ahb_lite_slave_0_cfg, MBOX); + if ( interface_activity.size() > 0 ) + begin + case ( interface_activity[0] ) + ACTIVE : + ahb_lite_slave_0_cfg.agent_cfg.is_active = 1; + PASSIVE : + ahb_lite_slave_0_cfg.agent_cfg.is_active = 0; + endcase + end +endfunction: initialize + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_environment.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_environment.svh new file mode 100644 index 0000000000000000000000000000000000000000..00af6ff0a451c7e61e5f491b95b329ae47155218 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_environment.svh @@ -0,0 +1,51 @@ +// +// File: qvip_ahb_lite_slave_environment.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +`include "uvm_macros.svh" +class qvip_ahb_lite_slave_environment +#( + string UNIQUE_ID = "" +) extends uvmf_environment_base #(.CONFIG_T(qvip_ahb_lite_slave_env_configuration)); + `uvm_component_param_utils(qvip_ahb_lite_slave_environment #(UNIQUE_ID)) + // Agent handles + + ahb_lite_slave_0_agent_t ahb_lite_slave_0; + function new + ( + string name = "qvip_ahb_lite_slave_environment", + uvm_component parent = null + ); + super.new(name, parent); + endfunction + + extern function void build_phase + ( + uvm_phase phase + ); + + extern function void connect_phase + ( + uvm_phase phase + ); + +endclass: qvip_ahb_lite_slave_environment + +function void qvip_ahb_lite_slave_environment::build_phase +( + uvm_phase phase +); + ahb_lite_slave_0 = ahb_lite_slave_0_agent_t::type_id::create("ahb_lite_slave_0", this ); + ahb_lite_slave_0.set_mvc_config(configuration.ahb_lite_slave_0_cfg); + +endfunction: build_phase + +function void qvip_ahb_lite_slave_environment::connect_phase +( + uvm_phase phase +); + uvm_config_db #(mvc_sequencer)::set(null,UVMF_SEQUENCERS,{UNIQUE_ID,"ahb_lite_slave_0"},ahb_lite_slave_0.m_sequencer); +endfunction: connect_phase + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_filelist.f b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_filelist.f new file mode 100644 index 0000000000000000000000000000000000000000..8a7f1549837d05b8e7b551c2ec350504e1d929e4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_filelist.f @@ -0,0 +1,16 @@ +$QUESTA_MVC_HOME/include/questa_mvc_svapi.sv ++define+MAP_PROT_ATTR $QUESTA_MVC_HOME/questa_mvc_src/sv/mvc_pkg.sv ++incdir+$UVMF_HOME/common/fli_pkg +$UVMF_HOME/common/fli_pkg/fli_pkg.sv ++incdir+$UVMF_HOME/uvmf_base_pkg +$UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +$UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.sv ++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv ++incdir+$QVIP_AHB_LITE_SLAVE_DIR_NAME ++incdir+$QVIP_AHB_LITE_SLAVE_DIR_NAME/../config_policies +$QVIP_AHB_LITE_SLAVE_DIR_NAME/../config_policies/qvip_ahb_lite_slave_params_pkg.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/qvip_ahb_lite_slave_pkg.sv ++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv ++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/default_clk_gen.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/default_reset_gen.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..852fa9f4c2bebc66e69afbe02e8c546ec7823b84 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv @@ -0,0 +1,31 @@ +// +// File: qvip_ahb_lite_slave_pkg.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +// ## The following code is used to add this qvip_configurator generated output into an +// ## encapsulating UVMF Generated environment. The addQvipSubEnv function is added to +// ## the python configuration file used by the UVMF environment generator. +// env.addQvipSubEnv('sub_env_instance_name', 'qvip_ahb_lite_slave', ['ahb_lite_slave_0']) +// +// ## The following code is used to add this qvip_configurator generated output into an +// ## encapsulating UVMF Generated test bench. The addQvipBfm function is added to +// ## the python configuration file used by the UVMF bench generator. +// ben.addQvipBfm('ahb_lite_slave_0', 'qvip_ahb_lite_slave', 'ACTIVE') +package qvip_ahb_lite_slave_pkg; + import uvm_pkg::*; + + `include "uvm_macros.svh" + + import addr_map_pkg::*; + + import uvmf_base_pkg::*; + import qvip_ahb_lite_slave_params_pkg::*; + import mvc_pkg::*; + import mgc_ahb_seq_pkg::*; + import mgc_ahb_v2_0_pkg::*; + + `include "qvip_ahb_lite_slave_env_configuration.svh" + `include "qvip_ahb_lite_slave_environment.svh" +endpackage: qvip_ahb_lite_slave_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_subenv_config.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_subenv_config.yaml new file mode 100644 index 0000000000000000000000000000000000000000..a32b5371818906168a85ad02bb85d9bad84d17ae --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_subenv_config.yaml @@ -0,0 +1,14 @@ +## To instantiate this subenv in a higher level, use this structure: +## qvip_subenvs : +## - { name: "", type: "qvip_ahb_lite_slave" } +uvmf: + qvip_library: + version: '2022.2' + date: '04/20/2022:16:06' + qvip_environments: + "qvip_ahb_lite_slave": + agents: + - name: 'ahb_lite_slave_0' + imports: + - "mvc_pkg" + - "mgc_ahb_v2_0_pkg" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/Makefile b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..27667fa2c5ae2826c8ad90eded119b6928b1c8e9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/Makefile @@ -0,0 +1,57 @@ +#################### +# Common Setup. + +INCDIRS = +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + +incdir+${UVMF_HOME}/uvmf_base_pkg \ + +incdir+../config_policies + +HVL_SV_SOURCE = ../uvmf/hvl_qvip_ahb_lite_slave.sv +HDL_SV_SOURCE = ../uvmf/hdl_qvip_ahb_lite_slave.sv + +UVM_OPTIONS = +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq + +export QVIP_AHB_LITE_SLAVE_DIR_NAME ?= $(shell pwd)/../uvmf + +#################### +# Questa support. + +all: work sv opt sim + +sv: hvl_sv hdl_sv + +work: + vlib work + +hvl_sv: + vlog -f qvip_ahb_lite_slave_test_filelist.f $(INCDIRS) $(HVL_SV_SOURCE) + +hdl_sv: + vlog -f qvip_ahb_lite_slave_test_filelist.f $(INCDIRS) $(HDL_SV_SOURCE) + +opt: + vopt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -o top_opt + +vis_opt: + vopt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -o top_opt -debug -designfile design.bin + +sim: + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -c -do "run -all; quit" + +vis_sim: + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -c -do "run -all; quit" -qwavedb=+signal+transaction+class+uvm_schematic + visualizer -designfile design.bin -wavefile qwave.db + +vis_int: work sv vis_opt + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -visualizer=design.bin -qwavedb=+signal+transaction+class+uvm_schematic + +gui: + vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns + +#################### +# Cleanup. + +clean: + rm -rf work transcript vsim.wlf + +.PHONY: all sv hvl_sv hdl_sv opt sim gui +.PHONY: vis vis_opt vis_sim vis_int diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_32.f b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_32.f new file mode 100644 index 0000000000000000000000000000000000000000..5ad392181baed88f1e0d8927e8c893125a0917c9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_32.f @@ -0,0 +1,15 @@ +export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf + +qrun -f qvip_ahb_lite_slave_test_filelist.f \ ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ +../uvmf/hdl_qvip_ahb_lite_slave.sv \ +../uvmf/hvl_qvip_ahb_lite_slave.sv \ +-debug \ +-designfile design.bin \ +-c \ +-mvchome ${QUESTA_MVC_HOME} \ ++nowarnTSCALE -t 1ns \ +-do "run -all; quit" \ ++UVM_TESTNAME=qvip_ahb_lite_slave_test_base \ ++SEQ=qvip_ahb_lite_slave_example_vseq \ +-qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_64.f b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_64.f new file mode 100644 index 0000000000000000000000000000000000000000..a521014ea61628043b7102493ab28a045a84e5da --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_64.f @@ -0,0 +1,16 @@ +export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf + +qrun -f qvip_ahb_lite_slave_test_filelist.f \ ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ +../uvmf/hdl_qvip_ahb_lite_slave.sv \ +../uvmf/hvl_qvip_ahb_lite_slave.sv \ +-64 \ +-debug \ +-designfile design.bin \ +-c \ +-mvchome ${QUESTA_MVC_HOME} \ ++nowarnTSCALE -t 1ns \ +-do "run -all; quit" \ ++UVM_TESTNAME=qvip_ahb_lite_slave_test_base \ ++SEQ=qvip_ahb_lite_slave_example_vseq \ +-qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_32 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_32 new file mode 100644 index 0000000000000000000000000000000000000000..f05aad1a617f3d0f9996656a06037d3374b7b5f2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_32 @@ -0,0 +1,13 @@ +export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf + +echo "Setting up work directory" +vlib work + +vlog -f qvip_ahb_lite_slave_test_filelist.f +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + ../uvmf/hdl_qvip_ahb_lite_slave.sv \ + ../uvmf/hvl_qvip_ahb_lite_slave.sv +echo "Optimisation step" +vopt -o top_opt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -debug -designfile design.bin + +echo "Running test" +vsim -c -mvchome ${QUESTA_MVC_HOME} top_opt +nowarnTSCALE -t 1ns -do "run -all; quit" +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq -qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_64 b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_64 new file mode 100644 index 0000000000000000000000000000000000000000..de195befc08be02603b4bb86763c4ff42052f5d3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_64 @@ -0,0 +1,13 @@ +export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf + +echo "Setting up work directory" +vlib work + +vlog -f qvip_ahb_lite_slave_test_filelist.f +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \ + ../uvmf/hdl_qvip_ahb_lite_slave.sv \ + ../uvmf/hvl_qvip_ahb_lite_slave.sv +echo "Optimisation step" +vopt -64 -o top_opt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -debug -designfile design.bin + +echo "Running test" +vsim -c -64 -mvchome ${QUESTA_MVC_HOME} top_opt +nowarnTSCALE -t 1ns -do "run -all; quit" +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq -qwavedb=+signal+transaction+class+uvm_schematic diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_example_vseq.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_example_vseq.svh new file mode 100644 index 0000000000000000000000000000000000000000..768c27bb0729088da4a5d8a77fada5e3e4367d0b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_example_vseq.svh @@ -0,0 +1,33 @@ +// +// File: qvip_ahb_lite_slave_example_vseq.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +// The purpose of this example virtual sequence is to show how the default or selected sequences for +// each QVIP can be run. The sequences are run in series in an arbitary order. +class qvip_ahb_lite_slave_example_vseq extends qvip_ahb_lite_slave_vseq_base; + `uvm_object_utils(qvip_ahb_lite_slave_example_vseq) + function new + ( + string name = "qvip_ahb_lite_slave_example_vseq" + ); + super.new(name); + endfunction + + extern task body; + +endclass: qvip_ahb_lite_slave_example_vseq + +task qvip_ahb_lite_slave_example_vseq::body; + ahb_single_wr_deparam_seq ahb_lite_slave_0_seq_0 = ahb_single_wr_deparam_seq::type_id::create("ahb_single_wr_deparam_seq"); + ahb_single_rd_deparam_seq ahb_lite_slave_0_seq_1 = ahb_single_rd_deparam_seq::type_id::create("ahb_single_rd_deparam_seq"); + + // Sequences run in the following order + + begin + ahb_lite_slave_0_seq_0.start(ahb_lite_slave_0_sqr); + ahb_lite_slave_0_seq_1.start(ahb_lite_slave_0_sqr); + end +endtask: body + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_base.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_base.svh new file mode 100644 index 0000000000000000000000000000000000000000..6f342ac6af97932abe3c34fb855644d28a3cfae0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_base.svh @@ -0,0 +1,73 @@ +// +// File: qvip_ahb_lite_slave_test_base.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class qvip_ahb_lite_slave_test_base extends uvmf_test_base #(.CONFIG_T(qvip_ahb_lite_slave_env_configuration),.ENV_T(qvip_ahb_lite_slave_environment),.TOP_LEVEL_SEQ_T(qvip_ahb_lite_slave_vseq_base)); + `uvm_component_utils(qvip_ahb_lite_slave_test_base) + function new + ( + string name = "qvip_ahb_lite_slave_test_base_test_base", + uvm_component parent = null + ); + super.new(name, parent); + endfunction + + extern function void build_phase + ( + uvm_phase phase + ); + + extern task run_phase + ( + uvm_phase phase + ); + +endclass: qvip_ahb_lite_slave_test_base + +function void qvip_ahb_lite_slave_test_base::build_phase +( + uvm_phase phase +); + string interface_names[] = { "ahb_lite_slave_0" }; + super.build_phase( phase ); + configuration.initialize( BLOCK, "uvm_test_top.qvip_ahb_lite_slave", interface_names ); +endfunction: build_phase + +task qvip_ahb_lite_slave_test_base::run_phase +( + uvm_phase phase +); + string sequence_name; + qvip_ahb_lite_slave_vseq_base vseq; + uvm_object obj; + uvm_cmdline_processor clp; + uvm_factory factory; + clp = uvm_cmdline_processor::get_inst(); + factory = uvm_factory::get(); + if ( clp.get_arg_value("+SEQ=", sequence_name) == 0 ) + begin + `uvm_fatal(get_type_name(), "You must specify a virtual sequence to run using the +SEQ plusarg") + end + obj = factory.create_object_by_name(sequence_name); + if ( obj == null ) + begin + factory.print(); + `uvm_fatal(get_type_name(), {"Virtual sequence '",sequence_name,"' not found in factory"}) + end + + if ( !$cast(vseq, obj) ) + begin + factory.print(); + `uvm_fatal(get_type_name(), {"Virtual sequence '",sequence_name,"' is not derived from qvip_ahb_lite_slave_vseq_base"}) + end + + //The sequence is OK to run + `uvm_info(get_type_name(), {"Running virtual sequence '",sequence_name,"'"}, UVM_LOW) + + phase.raise_objection(this); + vseq.start(null); + phase.drop_objection(this); +endtask: run_phase + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_filelist.f b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_filelist.f new file mode 100644 index 0000000000000000000000000000000000000000..1571265dd4d369320a370f4c90f439091d01460c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_filelist.f @@ -0,0 +1,17 @@ +$QUESTA_MVC_HOME/include/questa_mvc_svapi.sv ++define+MAP_PROT_ATTR $QUESTA_MVC_HOME/questa_mvc_src/sv/mvc_pkg.sv ++incdir+$UVMF_HOME/common/fli_pkg +$UVMF_HOME/common/fli_pkg/fli_pkg.sv ++incdir+$UVMF_HOME/uvmf_base_pkg +$UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +$UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.sv ++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv ++incdir+$QVIP_AHB_LITE_SLAVE_DIR_NAME ++incdir+$QVIP_AHB_LITE_SLAVE_DIR_NAME/../config_policies +$QVIP_AHB_LITE_SLAVE_DIR_NAME/../config_policies/qvip_ahb_lite_slave_params_pkg.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/qvip_ahb_lite_slave_pkg.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/../uvmf_tb/qvip_ahb_lite_slave_test_pkg.sv ++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv ++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/default_clk_gen.sv +$QVIP_AHB_LITE_SLAVE_DIR_NAME/default_reset_gen.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..841b22f791819d301cf4871827e572da1b06121e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_pkg.sv @@ -0,0 +1,34 @@ +// +// File: qvip_ahb_lite_slave_test_pkg.sv +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +// ## The following code is used to add this qvip_configurator generated output into an +// ## encapsulating UVMF Generated environment. The addQvipSubEnv function is added to +// ## the python configuration file used by the UVMF environment generator. +// env.addQvipSubEnv('sub_env_instance_name', 'qvip_ahb_lite_slave', ['ahb_lite_slave_0']) +// +// ## The following code is used to add this qvip_configurator generated output into an +// ## encapsulating UVMF Generated test bench. The addQvipBfm function is added to +// ## the python configuration file used by the UVMF bench generator. +// ben.addQvipBfm('ahb_lite_slave_0', 'qvip_ahb_lite_slave', 'ACTIVE') +package qvip_ahb_lite_slave_test_pkg; + import uvm_pkg::*; + + `include "uvm_macros.svh" + + import addr_map_pkg::*; + + import uvmf_base_pkg::*; + import qvip_ahb_lite_slave_params_pkg::*; + import mvc_pkg::*; + import mgc_ahb_seq_pkg::*; + import mgc_ahb_v2_0_pkg::*; + import qvip_ahb_lite_slave_pkg::*; + + `include "qvip_ahb_lite_slave_vseq_base.svh" + `include "qvip_ahb_lite_slave_test_base.svh" + `include "qvip_ahb_lite_slave_example_vseq.svh" + +endpackage: qvip_ahb_lite_slave_test_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_vseq_base.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_vseq_base.svh new file mode 100644 index 0000000000000000000000000000000000000000..31f8fdbfd1f46a1ac4e418c4efb94f026aa31f9c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_vseq_base.svh @@ -0,0 +1,29 @@ +// +// File: qvip_ahb_lite_slave_vseq_base.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// +class qvip_ahb_lite_slave_vseq_base extends uvm_sequence; + `uvm_object_utils(qvip_ahb_lite_slave_vseq_base) + // Handles for each of the target (QVIP) sequencers + + mvc_sequencer ahb_lite_slave_0_sqr; + function new + ( + string name = "qvip_ahb_lite_slave_vseq_base" + ); + super.new(name); + if ( !uvm_config_db #(mvc_sequencer)::get(null,UVMF_SEQUENCERS,"ahb_lite_slave_0", ahb_lite_slave_0_sqr) ) + begin + `uvm_error("Config Error" , "uvm_config_db #( mvc_sequencer )::get cannot find resource 'ahb_lite_slave_0'" ) + end + endfunction + + extern task body; + +endclass: qvip_ahb_lite_slave_vseq_base + +task qvip_ahb_lite_slave_vseq_base::body; +endtask: body + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/test_packages.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/test_packages.svh new file mode 100644 index 0000000000000000000000000000000000000000..9876754f603e92ad8b25d69d1786dd55953c6c79 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/test_packages.svh @@ -0,0 +1,10 @@ +// +// File: test_packages.svh +// +// Generated from Mentor VIP Configurator (20220406) +// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 ) +// + +import qvip_ahb_lite_slave_test_pkg::*; + +// Add other packages here as required diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/abr_prim.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/abr_prim.vf new file mode 100644 index 0000000000000000000000000000000000000000..9ed3e9b9c049434683afdc2b2d331ba2422ef246 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/abr_prim.vf @@ -0,0 +1,42 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/abr_prim_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/abr_prim_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..33ae05bbe5ec650ec35088cedbceb6200eae92eb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/abr_prim_pkg.vf @@ -0,0 +1,9 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..62d449d71fba4707ad9a569e26079ebfbfc4b473 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/config/compile.yml @@ -0,0 +1,66 @@ +--- +provides: [abr_prim_pkg] +schema_version: 2.4.0 +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_prim_util_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_alert_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_subreg_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_mubi_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_cipher_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_sparse_fsm_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_prim_util_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_alert_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_subreg_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_mubi_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_cipher_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_pkg.sv + - $COMPILE_ROOT/rtl/abr_prim_sparse_fsm_pkg.sv +--- +provides: [abr_prim] +schema_version: 2.4.0 +requires: + - abr_prim_pkg + - abr_prim_generic +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_prim_flop_en.sv + - $COMPILE_ROOT/rtl/abr_prim_cdc_rand_delay.sv + - $COMPILE_ROOT/rtl/abr_prim_flop_2sync.sv + - $COMPILE_ROOT/rtl/abr_prim_lfsr.sv + - $COMPILE_ROOT/rtl/abr_prim_mubi4_sync.sv + - $COMPILE_ROOT/rtl/abr_prim_diff_decode.sv + - $COMPILE_ROOT/rtl/abr_prim_sec_anchor_buf.sv + - $COMPILE_ROOT/rtl/abr_prim_slicer.sv + - $COMPILE_ROOT/rtl/abr_prim_count.sv + - $COMPILE_ROOT/rtl/abr_prim_sparse_fsm_flop.sv + - $COMPILE_ROOT/rtl/abr_prim_dom_and_2share.sv + - $COMPILE_ROOT/rtl/abr_prim_sec_anchor_flop.sv + - $COMPILE_ROOT/rtl/abr_prim_reg_we_check.sv + - $COMPILE_ROOT/rtl/abr_prim_packer_fifo.sv + - $COMPILE_ROOT/rtl/abr_prim_max_tree.sv + - $COMPILE_ROOT/rtl/abr_prim_subreg_arb.sv + - $COMPILE_ROOT/rtl/abr_prim_subreg.sv + - $COMPILE_ROOT/rtl/abr_prim_intr_hw.sv + - $COMPILE_ROOT/rtl/abr_prim_onehot_check.sv + - $COMPILE_ROOT/rtl/abr_prim_mubi8_sync.sv + - $COMPILE_ROOT/rtl/abr_prim_fifo_sync_cnt.sv + - $COMPILE_ROOT/rtl/abr_prim_buf.sv + #- $COMPILE_ROOT/rtl/abr_prim_lc_sync.sv + - $COMPILE_ROOT/rtl/abr_prim_alert_receiver.sv + - $COMPILE_ROOT/rtl/abr_prim_flop.sv + - $COMPILE_ROOT/rtl/abr_prim_alert_sender.sv + - $COMPILE_ROOT/rtl/abr_prim_fifo_sync.sv + - $COMPILE_ROOT/rtl/abr_prim_arbiter_ppc.sv + - $COMPILE_ROOT/rtl/abr_prim_sum_tree.sv + - $COMPILE_ROOT/rtl/abr_prim_subreg_ext.sv + - $COMPILE_ROOT/rtl/abr_prim_edge_detector.sv + tops: [abr_prim] diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_arbiter.vlt b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_arbiter.vlt new file mode 100644 index 0000000000000000000000000000000000000000..7d41fa42c4a9643d57022fda5acac39c08a6630e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_arbiter.vlt @@ -0,0 +1,45 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// Tell the Verilator scheduler to split up these variables into +// separate pieces when it's figuring out process scheduling. This +// avoids spurious UNOPTFLAT warnings caused by the fact that the +// arrays feed into themselves (with different bits for different +// positions in the tree). +split_var -module "abr_prim_arbiter_fixed" -var "data_tree" +split_var -module "abr_prim_arbiter_fixed" -var "gnt_tree" +split_var -module "abr_prim_arbiter_fixed" -var "idx_tree" +split_var -module "abr_prim_arbiter_fixed" -var "req_tree" + +split_var -module "abr_prim_arbiter_tree" -var "req_tree" +split_var -module "abr_prim_arbiter_tree" -var "prio_tree" +split_var -module "abr_prim_arbiter_tree" -var "sel_tree" +split_var -module "abr_prim_arbiter_tree" -var "mask_tree" +split_var -module "abr_prim_arbiter_tree" -var "idx_tree" +split_var -module "abr_prim_arbiter_tree" -var "data_tree" + +// Waive ALWCOMBORDER warnings about the tree variables. We've got +// lines like "req_tree[Pa] = req_tree[C0] | req_tree[C1];" and it +// seems that the ALWCOMBORDER warning isn't affected by the split_var +// rules above. +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_fixed.sv" -match "*data_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_fixed.sv" -match "*gnt_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_fixed.sv" -match "*idx_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_fixed.sv" -match "*req_tree*" + +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_tree.sv" -match "*req_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_tree.sv" -match "*prio_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_tree.sv" -match "*sel_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_tree.sv" -match "*mask_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_tree.sv" -match "*idx_tree*" +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_tree.sv" -match "*data_tree*" + +lint_off -rule ALWCOMBORDER -file "*/rtl/abr_prim_arbiter_ppc.sv" -match "*ppc_out*" + +// Waive unused clk and reset signals: they're just used for +// assertions (which Verilator doesn't see) +lint_off -rule UNUSED -file "*/rtl/abr_prim_arbiter_fixed.sv" -match "*clk_i*" +lint_off -rule UNUSED -file "*/rtl/abr_prim_arbiter_fixed.sv" -match "*rst_ni*" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_arbiter.waiver b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_arbiter.waiver new file mode 100644 index 0000000000000000000000000000000000000000..977c4e49ac768cce884951e0aa58b3de1162b2ba --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_arbiter.waiver @@ -0,0 +1,13 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for abr_prim_arbiter + +waive -rules PARTIAL_CONST_ASSIGN -location {abr_prim_arbiter_*.sv} -regexp {'mask.0.' is conditionally assigned a constant} \ + -comment "makes the code more readable" +waive -rules CONST_FF -location {abr_prim_arbiter_*.sv} -regexp {Flip-flop 'mask.0.' is driven by constant} \ + -comment "makes the code more readable" + +waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {abr_prim_arbiter_fixed.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'abr_prim_arbiter_fixed'.*} \ + -comment "clk_ and rst_ni are only used for assertions in this module." diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_max_tree.vlt b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_max_tree.vlt new file mode 100644 index 0000000000000000000000000000000000000000..44d8fd441846384ac258b8b7c1b98e31686d6061 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_max_tree.vlt @@ -0,0 +1,18 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// Tell the Verilator scheduler to split up these variables into +// separate pieces when it's figuring out process scheduling. This +// avoids spurious UNOPTFLAT warnings caused by the fact that the +// arrays feed into themselves (with different bits for different +// positions in the tree). +split_var -module "abr_prim_max_tree" -var "max_tree" +split_var -module "abr_prim_max_tree" -var "vld_tree" +split_var -module "abr_prim_max_tree" -var "idx_tree" + +// The clock and reset are only used for assertions in this module. +lint_off -rule UNUSED -file "*/rtl/abr_prim_max_tree.sv" -match "Signal is not used: 'clk_i'" +lint_off -rule UNUSED -file "*/rtl/abr_prim_max_tree.sv" -match "Signal is not used: 'rst_ni'" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_max_tree.waiver b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_max_tree.waiver new file mode 100644 index 0000000000000000000000000000000000000000..89779c99a4e71279f3268342c3d85a4e5e8f53f8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_max_tree.waiver @@ -0,0 +1,8 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for abr_prim_arbiter + +waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {abr_prim_max_tree.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'abr_prim_max_tree'.*} \ + -comment "clk_ and rst_ni are only used for assertions in this module." diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_onehot_check.vlt b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_onehot_check.vlt new file mode 100644 index 0000000000000000000000000000000000000000..e0bc0a957e53fa8e85e7234168fe4eb11cf09d5d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_onehot_check.vlt @@ -0,0 +1,22 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// Tell the Verilator scheduler to split up these variables into +// separate pieces when it's figuring out process scheduling. This +// avoids spurious UNOPTFLAT warnings caused by the fact that the +// arrays feed into themselves (with different bits for different +// positions in the tree). +split_var -module "abr_prim_onehot_check" -var "or_tree" +split_var -module "abr_prim_onehot_check" -var "and_tree" +split_var -module "abr_prim_onehot_check" -var "err_tree" + +// The clock and reset are only used for assertions in this module. +lint_off -rule UNUSED -file "*/rtl/abr_prim_onehot_check.sv" -match "Signal is not used: 'clk_i'" +lint_off -rule UNUSED -file "*/rtl/abr_prim_onehot_check.sv" -match "Signal is not used: 'rst_ni'" + +// The EnableAlertTriggerSVA parameter is only used by modules bound +// in for DV testing. Waive the warning that we don't read it. +lint_off -rule UNUSED -file "*/rtl/abr_prim_onehot_check.sv" -match "*EnableAlertTriggerSVA*" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_onehot_check.waiver b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_onehot_check.waiver new file mode 100644 index 0000000000000000000000000000000000000000..82b01edd5d1b0e8d7ad9636a5bd57b1e9c299a11 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_onehot_check.waiver @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for abr_prim_onehot_check + +waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {abr_prim_onehot_check.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'abr_prim_onehot_check'.*} \ + -comment "clk_ and rst_ni are only used for assertions in this module." + +waive -rules {PARAM_NOT_USED} -location {abr_prim_onehot_check.sv} -regexp {.*EnableAlertTriggerSVA.*} \ + -comment "The disable parameter is used only during DV / FPV." diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_sum_tree.vlt b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_sum_tree.vlt new file mode 100644 index 0000000000000000000000000000000000000000..e1d3ef982dfa7eb395f0478e00d21e7b25ff6157 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_sum_tree.vlt @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`verilator_config + +// Tell the Verilator scheduler to split up these variables into +// separate pieces when it's figuring out process scheduling. This +// avoids spurious UNOPTFLAT warnings caused by the fact that the +// arrays feed into themselves (with different bits for different +// positions in the tree). +split_var -module "abr_prim_sum_tree" -var "sum_tree" +split_var -module "abr_prim_sum_tree" -var "vld_tree" + +// The clock and reset are only used for assertions in this module. +lint_off -rule UNUSED -file "*/rtl/abr_prim_sum_tree.sv" -match "Signal is not used: 'clk_i'" +lint_off -rule UNUSED -file "*/rtl/abr_prim_sum_tree.sv" -match "Signal is not used: 'rst_ni'" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_sum_tree.waiver b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_sum_tree.waiver new file mode 100644 index 0000000000000000000000000000000000000000..7a563185263a79e41682a58ecbd2a33e8854c32d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/lint/abr_prim_sum_tree.waiver @@ -0,0 +1,8 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# waiver file for abr_prim_arbiter + +waive -rules {HIER_BRANCH_NOT_READ INPUT_NOT_READ} -location {abr_prim_sum_tree.sv} -regexp {.*'(clk_i|rst_ni)' is not read from in module 'abr_prim_sum_tree'.*} \ + -comment "clk_ and rst_ni are only used for assertions in this module." diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..dbd50c22b592268af8132a251b54c0d00a6eb9a9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_pkg.sv @@ -0,0 +1,29 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package abr_prim_alert_pkg; + + parameter int NumAlerts = 3; + + typedef struct packed { + logic alert_p; + logic alert_n; + } alert_tx_t; + + typedef struct packed { + logic ping_p; + logic ping_n; + logic ack_p; + logic ack_n; + } alert_rx_t; + + parameter alert_tx_t ALERT_TX_DEFAULT = '{alert_p: 1'b0, + alert_n: 1'b1}; + + parameter alert_rx_t ALERT_RX_DEFAULT = '{ping_p: 1'b0, + ping_n: 1'b1, + ack_p: 1'b0, + ack_n: 1'b1}; + +endpackage : abr_prim_alert_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_receiver.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_receiver.sv new file mode 100644 index 0000000000000000000000000000000000000000..26078fb49cc613cdae64dd83a311be3b6916a9d5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_receiver.sv @@ -0,0 +1,386 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The alert receiver primitive decodes alerts that have been differentially +// encoded and transmitted via a handshake protocol on alert_p/n and +// ack_p/n. In case an alert handshake is initiated, the output alert_o will +// immediately be asserted (even before completion of the handshake). +// +// In case the differential input is not correctly encoded, this module will +// raise an error by asserting integ_fail_o. +// +// Further, the module supports ping testing of the alert diff pair. In order to +// initiate a ping test, ping_req_i shall be set to 1'b1 until ping_ok_o is +// asserted for one cycle. The signal may be de-asserted (e.g. after a long) +// timeout period. However note that all ping responses that come in after +// deasserting ping_req_i will be treated as native alerts. +// +// The protocol works in both asynchronous and synchronous cases. In the +// asynchronous case, the parameter AsyncOn must be set to 1'b1 in order to +// instantiate additional synchronization logic. Further, it must be ensured +// that the timing skew between all diff pairs is smaller than the shortest +// clock period of the involved clocks. +// +// Note that in case of synchronous operation, alerts on the diffpair are +// decoded combinationally and forwarded on alert_o within the same cycle. +// +// See also: abr_prim_alert_sender, abr_prim_diff_decode, alert_handler + +`include "abr_prim_assert.sv" + +module abr_prim_alert_receiver + import abr_prim_alert_pkg::*; + import abr_prim_mubi_pkg::mubi4_t; +#( + // enables additional synchronization logic + parameter bit AsyncOn = 1'b0 +) ( + input clk_i, + input rst_b, + // if set to lc_ctrl_pkg::On, this triggers the in-band alert channel + // reset, which resets both the sender and receiver FSMs into IDLE. + input mubi4_t init_trig_i, + // this triggers a ping test. keep asserted + // until ping_ok_o is asserted. + input ping_req_i, + output logic ping_ok_o, + // asserted if signal integrity issue detected + output logic integ_fail_o, + // alert output (pulsed high) if a handshake is initiated + // on alert_p/n and no ping request is outstanding + output logic alert_o, + // ping input diff pair and ack diff pair + output alert_rx_t alert_rx_o, + // alert output diff pair + input alert_tx_t alert_tx_i +); + + import abr_prim_mubi_pkg::mubi4_test_true_strict; + + ///////////////////////////////// + // decode differential signals // + ///////////////////////////////// + logic alert_level, alert_sigint, alert_p, alert_n; + + // This prevents further tool optimizations of the differential signal. + abr_prim_sec_anchor_buf #( + .Width(2) + ) u_abr_prim_buf_in ( + .in_i({alert_tx_i.alert_n, + alert_tx_i.alert_p}), + .out_o({alert_n, + alert_p}) + ); + + abr_prim_diff_decode #( + .AsyncOn(AsyncOn) + ) u_decode_alert ( + .clk_i, + .rst_b, + .diff_pi ( alert_p ), + .diff_ni ( alert_n ), + .level_o ( alert_level ), + .rise_o ( ), + .fall_o ( ), + .event_o ( ), + .sigint_o ( alert_sigint ) + ); + + ///////////////////////////////////////////////////// + // main protocol FSM that drives the diff outputs // + ///////////////////////////////////////////////////// + typedef enum logic [2:0] {Idle, HsAckWait, Pause0, Pause1, InitReq, InitAckWait} state_e; + state_e state_d, state_q; + logic ping_rise; + logic ping_tog_pd, ping_tog_pq, ping_tog_dn, ping_tog_nq; + logic ack_pd, ack_pq, ack_dn, ack_nq; + logic ping_req_d, ping_req_q; + logic ping_pending_d, ping_pending_q; + logic send_init; + logic send_ping; + + // signal ping request upon positive transition on ping_req_i + // signalling is performed by a level change event on the diff output + assign ping_req_d = ping_req_i; + assign ping_rise = ping_req_d && !ping_req_q; + assign ping_tog_pd = (send_init) ? 1'b0 : + (send_ping) ? ~ping_tog_pq : ping_tog_pq; + + // in-band reset is performed by sending out an integrity error on purpose. + assign ack_dn = (send_init) ? ack_pd : ~ack_pd; + assign ping_tog_dn = ~ping_tog_pd; + + // This prevents further tool optimizations of the differential signal. + abr_prim_sec_anchor_flop #( + .Width (2), + .ResetValue(2'b10) + ) u_abr_prim_generic_flop_ack ( + .clk_i, + .rst_b, + .d_i({ack_dn, + ack_pd}), + .q_o({ack_nq, + ack_pq}) + ); + + abr_prim_sec_anchor_flop #( + .Width (2), + .ResetValue(2'b10) + ) u_abr_prim_generic_flop_ping ( + .clk_i, + .rst_b, + .d_i({ping_tog_dn, + ping_tog_pd}), + .q_o({ping_tog_nq, + ping_tog_pq}) + ); + + // the ping pending signal is used in the FSM to distinguish whether the + // incoming handshake shall be treated as an alert or a ping response. + // it is important that this is only set on a rising ping_en level change, since + // otherwise the ping enable signal could be abused to "mask" all native alerts + // as ping responses by constantly tying it to 1. + assign ping_pending_d = ping_rise | ((~ping_ok_o) & ping_req_i & ping_pending_q); + + // diff pair outputs + assign alert_rx_o.ack_p = ack_pq; + assign alert_rx_o.ack_n = ack_nq; + + assign alert_rx_o.ping_p = ping_tog_pq; + assign alert_rx_o.ping_n = ping_tog_nq; + + // this FSM receives the four phase handshakes from the alert receiver + // note that the latency of the alert_p/n input diff pair is at least one + // cycle until it enters the receiver FSM. the same holds for the ack_* diff + // pair outputs. + always_comb begin : p_fsm + // default + state_d = state_q; + ack_pd = 1'b0; + ping_ok_o = 1'b0; + integ_fail_o = 1'b0; + alert_o = 1'b0; + send_init = 1'b0; + // by default, a ping request leads to a toogle on the differential ping pair + send_ping = ping_rise; + + unique case (state_q) + Idle: begin + // wait for handshake to be initiated + if (alert_level) begin + state_d = HsAckWait; + ack_pd = 1'b1; + // signal either an alert or ping received on the output + if (ping_pending_q) begin + ping_ok_o = 1'b1; + end else begin + alert_o = 1'b1; + end + end + end + // waiting for deassertion of alert to complete HS + HsAckWait: begin + if (!alert_level) begin + state_d = Pause0; + end else begin + ack_pd = 1'b1; + end + end + // pause cycles between back-to-back handshakes + Pause0: state_d = Pause1; + Pause1: state_d = Idle; + // this state is only reached if an in-band reset is + // requested via the low-power logic. + InitReq: begin + // we deliberately place a sigint error on the ack and ping lines in this case. + send_init = 1'b1; + // suppress any toggles on the ping line while we are in the init phase. + send_ping = 1'b0; + // As long as init req is asserted, we remain in this state and acknowledge all incoming + // ping requests. As soon as the init request is dropped however, ping requests are not + // acked anymore such that the ping mechanism can also flag alert channels that got stuck + // in the initialization sequence. + if (mubi4_test_true_strict(init_trig_i)) begin + ping_ok_o = ping_pending_q; + // the sender will respond to the sigint error above with a sigint error on the alert lines. + // hence we treat the alert_sigint like an acknowledgement in this case. + end else if (alert_sigint) begin + state_d = InitAckWait; + end + end + // We get here if the sender has responded with alert_sigint, and init_trig_i==lc_ctrl_pkg::On + // has been deasserted. At this point, we need to wait for the alert_sigint to drop again + // before resuming normal operation. + InitAckWait: begin + // suppress any toggles on the ping line while we are in the init phase. + send_ping = 1'b0; + if (!alert_sigint) begin + state_d = Pause0; + // If we get a ping request in this cycle, or if we realize that there is an unhandled + // ping request that came in during initialization (but after init_trig_i has been + // deasserted), we signal this to the alert sender by toggling the request line. + send_ping = ping_rise || ping_pending_q; + end + end + default: state_d = Idle; + endcase + + // once the initialization sequence has been triggered, + // overrides are not allowed anymore until the initialization has been completed. + if (!(state_q inside {InitReq, InitAckWait})) begin + // in this case, abort and jump into the initialization sequence + if (mubi4_test_true_strict(init_trig_i)) begin + state_d = InitReq; + ack_pd = 1'b0; + ping_ok_o = 1'b0; + integ_fail_o = 1'b0; + alert_o = 1'b0; + send_init = 1'b1; + // if we're not busy with an init request, we clamp down all outputs + // and indicate an integrity failure. + end else if (alert_sigint) begin + state_d = Idle; + ack_pd = 1'b0; + ping_ok_o = 1'b0; + integ_fail_o = 1'b1; + alert_o = 1'b0; + end + end + end + + always_ff @(posedge clk_i or negedge rst_b) begin : p_reg + if (!rst_b) begin + // Reset into the init request so that an alert handler reset implicitly + // triggers an in-band reset of all alert channels. + state_q <= InitReq; + ping_req_q <= 1'b0; + ping_pending_q <= 1'b0; + end else begin + state_q <= state_d; + ping_req_q <= ping_req_d; + ping_pending_q <= ping_pending_d; + end + end + + + //////////////// + // assertions // + //////////////// + +`ifdef ABR_INC_ASSERT + import abr_prim_mubi_pkg::mubi4_test_false_loose; +`endif + + // check whether all outputs have a good known state after reset + `ABR_ASSERT_KNOWN(PingOkKnownO_A, ping_ok_o) + `ABR_ASSERT_KNOWN(IntegFailKnownO_A, integ_fail_o) + `ABR_ASSERT_KNOWN(AlertKnownO_A, alert_o) + `ABR_ASSERT_KNOWN(PingPKnownO_A, alert_rx_o) + + // check encoding of outgoing diffpairs. note that during init, the outgoing diffpairs are + // supposed to be incorrectly encoded on purpose. + // shift sequence two cycles to the right to avoid reset effects. + `ABR_ASSERT(PingDiffOk_A, alert_rx_o.ping_p ^ alert_rx_o.ping_n) + `ABR_ASSERT(AckDiffOk_A, ##2 $past(send_init) ^ alert_rx_o.ack_p ^ alert_rx_o.ack_n) + `ABR_ASSERT(InitReq_A, mubi4_test_true_strict(init_trig_i) && + !(state_q inside {InitReq, InitAckWait}) |=> send_init) + + // ping request at input -> need to see encoded ping request + `ABR_ASSERT(PingRequest0_A, ##1 $rose(ping_req_i) && !state_q inside {InitReq, InitAckWait} + |=> $changed(alert_rx_o.ping_p)) + // ping response implies it has been requested + `ABR_ASSERT(PingResponse0_A, ping_ok_o |-> ping_pending_q) + // correctly latch ping request + `ABR_ASSERT(PingPending_A, ##1 $rose(ping_req_i) |=> ping_pending_q) + + if (AsyncOn) begin : gen_async_assert + // signal integrity check propagation + `ABR_ASSERT(SigInt_A, + alert_tx_i.alert_p == alert_tx_i.alert_n [*2] ##2 + !(state_q inside {InitReq, InitAckWait}) && + mubi4_test_false_loose(init_trig_i) + |-> + integ_fail_o) + // TODO: need to add skewed cases as well, the assertions below assume no skew at the moment + // ping response + `ABR_ASSERT(PingResponse1_A, + ##1 $rose(alert_tx_i.alert_p) && + (alert_tx_i.alert_p ^ alert_tx_i.alert_n) ##2 + state_q == Idle && ping_pending_q + |-> + ping_ok_o, + clk_i, !rst_b || integ_fail_o || mubi4_test_true_strict(init_trig_i)) + // alert + `ABR_ASSERT(Alert_A, + ##1 $rose(alert_tx_i.alert_p) && + (alert_tx_i.alert_p ^ alert_tx_i.alert_n) ##2 + state_q == Idle && + !ping_pending_q + |-> + alert_o, + clk_i, !rst_b || integ_fail_o || mubi4_test_true_strict(init_trig_i)) + end else begin : gen_sync_assert + // signal integrity check propagation + `ABR_ASSERT(SigInt_A, + alert_tx_i.alert_p == alert_tx_i.alert_n && + !(state_q inside {InitReq, InitAckWait}) && + mubi4_test_false_loose(init_trig_i) + |-> + integ_fail_o) + // ping response + `ABR_ASSERT(PingResponse1_A, + ##1 $rose(alert_tx_i.alert_p) && + state_q == Idle && + ping_pending_q + |-> + ping_ok_o, + clk_i, !rst_b || integ_fail_o || mubi4_test_true_strict(init_trig_i)) + // alert + `ABR_ASSERT(Alert_A, + ##1 $rose(alert_tx_i.alert_p) && + state_q == Idle && + !ping_pending_q + |-> + alert_o, + clk_i, !rst_b || integ_fail_o || mubi4_test_true_strict(init_trig_i)) + end + + // check in-band init request is always accepted + `ABR_ASSERT(InBandInitRequest_A, + mubi4_test_true_strict(init_trig_i) && + state_q != InitAckWait + |=> + state_q == InitReq) + // check in-band init sequence moves FSM into IDLE state + `ABR_ASSERT(InBandInitSequence_A, + (state_q == InitReq && + mubi4_test_true_strict(init_trig_i)) ##1 + (alert_sigint && + mubi4_test_false_loose(init_trig_i)) [*1:$] ##1 + (!alert_sigint && + mubi4_test_false_loose(init_trig_i)) [*3] + |=> + state_q == Idle) + // check there are no spurious alerts during init + `ABR_ASSERT(NoSpuriousAlertsDuringInit_A, + mubi4_test_true_strict(init_trig_i) || + (state_q inside {InitReq, InitAckWait}) + |-> + !alert_o) + // check that there are no spurious ping OKs + `ABR_ASSERT(NoSpuriousPingOksDuringInit_A, + (mubi4_test_true_strict(init_trig_i) || + (state_q inside {InitReq, InitAckWait})) && + !ping_pending_q + |-> + !ping_ok_o) + // check ping request is bypassed when in init state + `ABR_ASSERT(PingOkBypassDuringInit_A, + $rose(ping_req_i) ##1 + state_q == InitReq && + mubi4_test_true_strict(init_trig_i) + |-> + ping_ok_o) + +endmodule : abr_prim_alert_receiver diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_sender.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_sender.sv new file mode 100644 index 0000000000000000000000000000000000000000..7c9031555dc0993cc63098ca6699039522e0406c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_alert_sender.sv @@ -0,0 +1,392 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The alert sender primitive module differentially encodes and transmits an +// alert signal to the abr_prim_alert_receiver module. An alert will be signalled +// by a full handshake on alert_p/n and ack_p/n. The alert_req_i signal may +// be continuously asserted, in which case the alert signalling handshake +// will be repeatedly initiated. +// +// The alert_req_i signal may also be used as part of req/ack. The parent module +// can keep alert_req_i asserted until it has been ack'd (transferred to the alert +// receiver). The parent module is not required to use this. +// +// In case the alert sender parameter IsFatal is set to 1, an incoming alert +// alert_req_i is latched in a local register until the next reset, causing the +// alert sender to behave as if alert_req_i were continously asserted. +// The alert_state_o output reflects the state of this internal latching register. +// +// The alert sender also exposes an alert test input, which can be used to trigger +// single alert handshakes. This input behaves exactly the same way as the +// alert_req_i input with IsFatal set to 0. Test alerts do not cause alert_ack_o +// to be asserted, nor are they latched until reset (regardless of the value of the +// IsFatal parameter). +// +// Further, this module supports in-band ping testing, which means that a level +// change on the ping_p/n diff pair will result in a full-handshake response +// on alert_p/n and ack_p/n. +// +// The protocol works in both asynchronous and synchronous cases. In the +// asynchronous case, the parameter AsyncOn must be set to 1'b1 in order to +// instantiate additional synchronization logic. Further, it must be ensured +// that the timing skew between all diff pairs is smaller than the shortest +// clock period of the involved clocks. +// +// Incorrectly encoded diff inputs can be detected and will be signalled +// to the receiver by placing an inconsistent diff value on the differential +// output (and continuously toggling it). +// +// See also: abr_prim_alert_receiver, abr_prim_diff_decode, alert_handler + +`include "abr_prim_assert.sv" + +module abr_prim_alert_sender + import abr_prim_alert_pkg::*; +#( + // enables additional synchronization logic + parameter bit AsyncOn = 1'b1, + // alert sender will latch the incoming alert event permanently and + // keep on sending alert events until the next reset. + parameter bit IsFatal = 1'b0 +) ( + input clk_i, + input rst_b, + // alert test trigger (this will never be latched, even if IsFatal == 1) + input alert_test_i, + // native alert from the peripheral + input alert_req_i, + output logic alert_ack_o, + // state of the alert latching register + output logic alert_state_o, + // ping input diff pair and ack diff pair + input alert_rx_t alert_rx_i, + // alert output diff pair + output alert_tx_t alert_tx_o +); + + + ///////////////////////////////// + // decode differential signals // + ///////////////////////////////// + logic ping_sigint, ping_event, ping_n, ping_p; + + // This prevents further tool optimizations of the differential signal. + abr_prim_sec_anchor_buf #( + .Width(2) + ) u_abr_prim_buf_ping ( + .in_i({alert_rx_i.ping_n, + alert_rx_i.ping_p}), + .out_o({ping_n, + ping_p}) + ); + + abr_prim_diff_decode #( + .AsyncOn(AsyncOn) + ) u_decode_ping ( + .clk_i, + .rst_b, + .diff_pi ( ping_p ), + .diff_ni ( ping_n ), + .level_o ( ), + .rise_o ( ), + .fall_o ( ), + .event_o ( ping_event ), + .sigint_o ( ping_sigint ) + ); + + logic ack_sigint, ack_level, ack_n, ack_p; + + // This prevents further tool optimizations of the differential signal. + abr_prim_sec_anchor_buf #( + .Width(2) + ) u_abr_prim_buf_ack ( + .in_i({alert_rx_i.ack_n, + alert_rx_i.ack_p}), + .out_o({ack_n, + ack_p}) + ); + + abr_prim_diff_decode #( + .AsyncOn(AsyncOn) + ) u_decode_ack ( + .clk_i, + .rst_b, + .diff_pi ( ack_p ), + .diff_ni ( ack_n ), + .level_o ( ack_level ), + .rise_o ( ), + .fall_o ( ), + .event_o ( ), + .sigint_o ( ack_sigint ) + ); + + + /////////////////////////////////////////////////// + // main protocol FSM that drives the diff output // + /////////////////////////////////////////////////// + typedef enum logic [2:0] { + Idle, + AlertHsPhase1, + AlertHsPhase2, + PingHsPhase1, + PingHsPhase2, + Pause0, + Pause1 + } state_e; + state_e state_d, state_q; + logic alert_pq, alert_nq, alert_pd, alert_nd; + logic sigint_detected; + + assign sigint_detected = ack_sigint | ping_sigint; + + + // diff pair output + assign alert_tx_o.alert_p = alert_pq; + assign alert_tx_o.alert_n = alert_nq; + + // alert and ping set regs + logic alert_set_d, alert_set_q, alert_clr; + logic alert_test_set_d, alert_test_set_q; + logic ping_set_d, ping_set_q, ping_clr; + logic alert_req_trigger, alert_test_trigger, ping_trigger; + + // if handshake is ongoing, capture additional alert requests. + logic alert_req; + abr_prim_sec_anchor_buf #( + .Width(1) + ) u_abr_prim_buf_in_req ( + .in_i(alert_req_i), + .out_o(alert_req) + ); + + assign alert_req_trigger = alert_req | alert_set_q; + if (IsFatal) begin : gen_fatal + assign alert_set_d = alert_req_trigger; + end else begin : gen_recov + assign alert_set_d = (alert_clr) ? 1'b0 : alert_req_trigger; + end + + // the alert test request is always cleared. + assign alert_test_trigger = alert_test_i | alert_test_set_q; + assign alert_test_set_d = (alert_clr) ? 1'b0 : alert_test_trigger; + + logic alert_trigger; + assign alert_trigger = alert_req_trigger | alert_test_trigger; + + assign ping_trigger = ping_set_q | ping_event; + assign ping_set_d = (ping_clr) ? 1'b0 : ping_trigger; + + + // alert event acknowledge and state (not affected by alert_test_i) + assign alert_ack_o = alert_clr & alert_set_q; + assign alert_state_o = alert_set_q; + + // this FSM performs a full four phase handshake upon a ping or alert trigger. + // note that the latency of the alert_p/n diff pair is at least one cycle + // until it enters the receiver FSM. the same holds for the ack_* diff pair + // input. in case a signal integrity issue is detected, the FSM bails out, + // sets the alert_p/n diff pair to the same value and toggles it in order to + // signal that condition over to the receiver. + always_comb begin : p_fsm + // default + state_d = state_q; + alert_pd = 1'b0; + alert_nd = 1'b1; + ping_clr = 1'b0; + alert_clr = 1'b0; + + unique case (state_q) + Idle: begin + // alert always takes precedence + if (alert_trigger || ping_trigger) begin + state_d = (alert_trigger) ? AlertHsPhase1 : PingHsPhase1; + alert_pd = 1'b1; + alert_nd = 1'b0; + end + end + // waiting for ack from receiver + AlertHsPhase1: begin + if (ack_level) begin + state_d = AlertHsPhase2; + end else begin + alert_pd = 1'b1; + alert_nd = 1'b0; + end + end + // wait for deassertion of ack + AlertHsPhase2: begin + if (!ack_level) begin + state_d = Pause0; + alert_clr = 1'b1; + end + end + // waiting for ack from receiver + PingHsPhase1: begin + if (ack_level) begin + state_d = PingHsPhase2; + end else begin + alert_pd = 1'b1; + alert_nd = 1'b0; + end + end + // wait for deassertion of ack + PingHsPhase2: begin + if (!ack_level) begin + ping_clr = 1'b1; + state_d = Pause0; + end + end + // pause cycles between back-to-back handshakes + Pause0: begin + state_d = Pause1; + end + // clear and ack alert request if it was set + Pause1: begin + state_d = Idle; + end + // catch parasitic states + default : state_d = Idle; + endcase + + // we have a signal integrity issue at one of the incoming diff pairs. this condition is + // signalled by setting the output diffpair to zero. If the sigint has disappeared, we clear + // the ping request state of this sender and go back to idle. + if (sigint_detected) begin + state_d = Idle; + alert_pd = 1'b0; + alert_nd = 1'b0; + ping_clr = 1'b1; + alert_clr = 1'b0; + end + end + + // This prevents further tool optimizations of the differential signal. + abr_prim_sec_anchor_flop #( + .Width (2), + .ResetValue(2'b10) + ) u_abr_prim_flop_alert ( + .clk_i, + .rst_b, + .d_i({alert_nd, alert_pd}), + .q_o({alert_nq, alert_pq}) + ); + + always_ff @(posedge clk_i or negedge rst_b) begin : p_reg + if (!rst_b) begin + state_q <= Idle; + alert_set_q <= 1'b0; + alert_test_set_q <= 1'b0; + ping_set_q <= 1'b0; + end else begin + state_q <= state_d; + alert_set_q <= alert_set_d; + alert_test_set_q <= alert_test_set_d; + ping_set_q <= ping_set_d; + end + end + + + //////////////// + // assertions // + //////////////// + +// however, since we use sequence constructs below, we need to wrap the entire block again. +// typically, the ABR_ASSERT macros already contain this ABR_INC_ASSERT macro. +`ifdef ABR_INC_ASSERT + // check whether all outputs have a good known state after reset + `ABR_ASSERT_KNOWN(AlertPKnownO_A, alert_tx_o) + + if (AsyncOn) begin : gen_async_assert + sequence PingSigInt_S; + alert_rx_i.ping_p == alert_rx_i.ping_n [*2]; + endsequence + sequence AckSigInt_S; + alert_rx_i.ping_p == alert_rx_i.ping_n [*2]; + endsequence + + `ifndef FPV_ALERT_NO_SIGINT_ERR + // check propagation of sigint issues to output within three cycles + // shift sequence to the right to avoid reset effects. + `ABR_ASSERT(SigIntPing_A, ##1 PingSigInt_S |-> + ##3 alert_tx_o.alert_p == alert_tx_o.alert_n) + `ABR_ASSERT(SigIntAck_A, ##1 AckSigInt_S |-> + ##3 alert_tx_o.alert_p == alert_tx_o.alert_n) + `endif + + // Test in-band FSM reset request (via signal integrity error) + `ABR_ASSERT(InBandInitFsm_A, PingSigInt_S or AckSigInt_S |-> ##3 state_q == Idle) + `ABR_ASSERT(InBandInitPing_A, PingSigInt_S or AckSigInt_S |-> ##3 !ping_set_q) + // output must be driven diff unless sigint issue detected + `ABR_ASSERT(DiffEncoding_A, (alert_rx_i.ack_p ^ alert_rx_i.ack_n) && + (alert_rx_i.ping_p ^ alert_rx_i.ping_n) |-> + ##[3:4] alert_tx_o.alert_p ^ alert_tx_o.alert_n) + + // handshakes can take indefinite time if blocked due to sigint on outgoing + // lines (which is not visible here). thus, we only check whether the + // handshake is correctly initiated and defer the full handshake checking to the testbench. + // TODO: add the staggered cases as well + `ABR_ASSERT(PingHs_A, ##1 $changed(alert_rx_i.ping_p) && + (alert_rx_i.ping_p ^ alert_rx_i.ping_n) ##2 state_q == Idle |=> + $rose(alert_tx_o.alert_p), clk_i, !rst_b || (alert_tx_o.alert_p == alert_tx_o.alert_n)) + end else begin : gen_sync_assert + sequence PingSigInt_S; + alert_rx_i.ping_p == alert_rx_i.ping_n; + endsequence + sequence AckSigInt_S; + alert_rx_i.ping_p == alert_rx_i.ping_n; + endsequence + + `ifndef FPV_ALERT_NO_SIGINT_ERR + // check propagation of sigint issues to output within one cycle + `ABR_ASSERT(SigIntPing_A, PingSigInt_S |=> + alert_tx_o.alert_p == alert_tx_o.alert_n) + `ABR_ASSERT(SigIntAck_A, AckSigInt_S |=> + alert_tx_o.alert_p == alert_tx_o.alert_n) + `endif + + // Test in-band FSM reset request (via signal integrity error) + `ABR_ASSERT(InBandInitFsm_A, PingSigInt_S or AckSigInt_S |=> state_q == Idle) + `ABR_ASSERT(InBandInitPing_A, PingSigInt_S or AckSigInt_S |=> !ping_set_q) + // output must be driven diff unless sigint issue detected + `ABR_ASSERT(DiffEncoding_A, (alert_rx_i.ack_p ^ alert_rx_i.ack_n) && + (alert_rx_i.ping_p ^ alert_rx_i.ping_n) |=> alert_tx_o.alert_p ^ alert_tx_o.alert_n) + // handshakes can take indefinite time if blocked due to sigint on outgoing + // lines (which is not visible here). thus, we only check whether the handshake + // is correctly initiated and defer the full handshake checking to the testbench. + `ABR_ASSERT(PingHs_A, ##1 $changed(alert_rx_i.ping_p) && state_q == Idle |=> + $rose(alert_tx_o.alert_p), clk_i, !rst_b || (alert_tx_o.alert_p == alert_tx_o.alert_n)) + end + + // Test the alert state output. + `ABR_ASSERT(AlertState0_A, alert_set_q === alert_state_o) + + if (IsFatal) begin : gen_fatal_assert + `ABR_ASSERT(AlertState1_A, alert_req_i |=> alert_state_o) + `ABR_ASSERT(AlertState2_A, alert_state_o |=> $stable(alert_state_o)) + `ABR_ASSERT(AlertState3_A, alert_ack_o |=> alert_state_o) + end else begin : gen_recov_assert + `ABR_ASSERT(AlertState1_A, alert_req_i && !alert_clr |=> alert_state_o) + `ABR_ASSERT(AlertState2_A, alert_req_i && alert_ack_o |=> !alert_state_o) + end + + // The alert test input should not set the alert state register. + `ABR_ASSERT(AlertTest1_A, alert_test_i && !alert_req_i && !alert_state_o |=> $stable(alert_state_o)) + + // if alert_req_i is true, handshakes should be continuously repeated + `ABR_ASSERT(AlertHs_A, alert_req_i && state_q == Idle |=> $rose(alert_tx_o.alert_p), + clk_i, !rst_b || (alert_tx_o.alert_p == alert_tx_o.alert_n)) + + // if alert_test_i is true, handshakes should be continuously repeated + `ABR_ASSERT(AlertTestHs_A, alert_test_i && state_q == Idle |=> $rose(alert_tx_o.alert_p), + clk_i, !rst_b || (alert_tx_o.alert_p == alert_tx_o.alert_n)) +`endif + +`ifdef FPV_ALERT_NO_SIGINT_ERR + // Assumptions for FPV security countermeasures to ensure the alert protocol functions collectly. + `ABR_ASSUME_FPV(AckPFollowsAlertP_S, alert_rx_i.ack_p == $past(alert_tx_o.alert_p)) + `ABR_ASSUME_FPV(AckNFollowsAlertN_S, alert_rx_i.ack_n == $past(alert_tx_o.alert_n)) + `ABR_ASSUME_FPV(TriggerAlertInit_S, $stable(rst_b) == 0 |=> alert_rx_i.ping_p == alert_rx_i.ping_n) + `ABR_ASSUME_FPV(PingDiffPair_S, ##2 alert_rx_i.ping_p != alert_rx_i.ping_n) +`endif +endmodule : abr_prim_alert_sender diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv new file mode 100644 index 0000000000000000000000000000000000000000..c4d4bfaad78ca86448d817d9d87dd34dfb26a722 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv @@ -0,0 +1,225 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// N:1 arbiter module +// +// Verilog parameter +// N: Number of request ports +// DW: Data width +// DataPort: Set to 1 to enable the data port. Otherwise that port will be ignored. +// +// This is the original implementation of the arbiter which relies on parallel prefix computing +// optimization to optimize the request / arbiter tree. Not all synthesis tools may support this. +// +// Note that the currently winning request is held if the data sink is not ready. This behavior is +// required by some interconnect protocols (AXI, TL). The module contains an assertion that checks +// this behavior. +// +// Also, this module contains a request stability assertion that checks that requests stay asserted +// until they have been served. This assertion can be gated by driving the req_chk_i low. This is +// a non-functional input and does not affect the designs behavior. +// +// See also: abr_prim_arbiter_tree + +`include "abr_prim_assert.sv" + +module abr_prim_arbiter_ppc #( + parameter int unsigned N = 8, + parameter int unsigned DW = 32, + + // Configurations + // EnDataPort: {0, 1}, if 0, input data will be ignored + parameter bit EnDataPort = 1, + + // Derived parameters + localparam int IdxW = $clog2(N) +) ( + input clk_i, + input rst_b, + + input req_chk_i, // Used for gating assertions. Drive to 1 during normal + // operation. + input [ N-1:0] req_i, + input [DW-1:0] data_i [N], + output logic [ N-1:0] gnt_o, + output logic [IdxW-1:0] idx_o, + + output logic valid_o, + output logic [DW-1:0] data_o, + input ready_i +); + + // req_chk_i is used for gating assertions only. + logic unused_req_chk; + assign unused_req_chk = req_chk_i; + + `ABR_ASSERT_INIT(CheckNGreaterZero_A, N > 0) + + // this case is basically just a bypass + if (N == 1) begin : gen_degenerate_case + + assign valid_o = req_i[0]; + assign data_o = data_i[0]; + assign gnt_o[0] = valid_o & ready_i; + assign idx_o = '0; + + end else begin : gen_normal_case + + logic [N-1:0] masked_req; + logic [N-1:0] ppc_out; + logic [N-1:0] arb_req; + logic [N-1:0] mask, mask_next; + logic [N-1:0] winner; + + assign masked_req = mask & req_i; + assign arb_req = (|masked_req) ? masked_req : req_i; + + // PPC + // Even below code looks O(n) but DC optimizes it to O(log(N)) + // Using Parallel Prefix Computation + always_comb begin + ppc_out[0] = arb_req[0]; + for (int i = 1 ; i < N ; i++) begin + ppc_out[i] = ppc_out[i-1] | arb_req[i]; + end + end + + // Grant Generation: Leading-One detector + assign winner = ppc_out ^ {ppc_out[N-2:0], 1'b0}; + assign gnt_o = (ready_i) ? winner : '0; + + assign valid_o = |req_i; + // Mask Generation + assign mask_next = {ppc_out[N-2:0], 1'b0}; + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + mask <= '0; + end else if (valid_o && ready_i) begin + // Latch only when requests accepted + mask <= mask_next; + end else if (valid_o && !ready_i) begin + // Downstream isn't yet ready so, keep current request alive. (First come first serve) + mask <= ppc_out; + end + end + + if (EnDataPort == 1) begin: gen_datapath + always_comb begin + data_o = '0; + for (int i = 0 ; i < N ; i++) begin + if (winner[i]) begin + data_o = data_i[i]; + end + end + end + end else begin: gen_nodatapath + assign data_o = '1; + // The following signal is used to avoid possible lint errors. + logic [DW-1:0] unused_data [N]; + assign unused_data = data_i; + end + + always_comb begin + idx_o = '0; + for (int unsigned i = 0 ; i < N ; i++) begin + if (winner[i]) begin + idx_o = i[IdxW-1:0]; + end + end + end + end + + //////////////// + // assertions // + //////////////// + + // KNOWN assertions on outputs, except for data as that may be partially X in simulation + // e.g. when used on a BUS + `ABR_ASSERT_KNOWN(ValidKnown_A, valid_o) + `ABR_ASSERT_KNOWN(GrantKnown_A, gnt_o) + `ABR_ASSERT_KNOWN(IdxKnown_A, idx_o) + + // grant index shall be higher index than previous index, unless no higher requests exist. + `ABR_ASSERT(RoundRobin_A, + ##1 valid_o && ready_i && $past(ready_i) && $past(valid_o) && + |(req_i & ~((N'(1) << $past(idx_o)+1) - 1)) |-> + idx_o > $past(idx_o)) + // we can only grant one requestor at a time + `ABR_ASSERT(CheckHotOne_A, $onehot0(gnt_o)) + // A grant implies that the sink is ready + `ABR_ASSERT(GntImpliesReady_A, |gnt_o |-> ready_i) + // A grant implies that the arbiter asserts valid as well + `ABR_ASSERT(GntImpliesValid_A, |gnt_o |-> valid_o) + // A request and a sink that is ready imply a grant + `ABR_ASSERT(ReqAndReadyImplyGrant_A, |req_i && ready_i |-> |gnt_o) + // A request and a sink that is ready imply a grant + `ABR_ASSERT(ReqImpliesValid_A, |req_i |-> valid_o) + // Both conditions above combined and reversed + `ABR_ASSERT(ReadyAndValidImplyGrant_A, ready_i && valid_o |-> |gnt_o) + // Both conditions above combined and reversed + `ABR_ASSERT(NoReadyValidNoGrant_A, !(ready_i || valid_o) |-> gnt_o == 0) + // check index / grant correspond + `ABR_ASSERT(IndexIsCorrect_A, ready_i && valid_o |-> gnt_o[idx_o] && req_i[idx_o]) + +if (EnDataPort) begin: gen_data_port_assertion + // data flow + `ABR_ASSERT(DataFlow_A, ready_i && valid_o |-> data_o == data_i[idx_o]) +end + + // requests must stay asserted until they have been granted + `ABR_ASSUME(ReqStaysHighUntilGranted0_M, |req_i && !ready_i |=> + (req_i & $past(req_i)) == $past(req_i), clk_i, !rst_b || !req_chk_i) + // check that the arbitration decision is held if the sink is not ready + `ABR_ASSERT(LockArbDecision_A, |req_i && !ready_i |=> idx_o == $past(idx_o), + clk_i, !rst_b || !req_chk_i) + +// FPV-only assertions with symbolic variables +`ifdef FPV_ON + // symbolic variables + int unsigned k; + bit ReadyIsStable; + bit ReqsAreStable; + + // constraints for symbolic variables + `ABR_ASSUME(KStable_M, ##1 $stable(k)) + `ABR_ASSUME(KRange_M, k < N) + // this is used enable checking for stable and unstable ready_i and req_i signals in the same run. + // the symbolic variables act like a switch that the solver can trun on and off. + `ABR_ASSUME(ReadyIsStable_M, ##1 $stable(ReadyIsStable)) + `ABR_ASSUME(ReqsAreStable_M, ##1 $stable(ReqsAreStable)) + `ABR_ASSUME(ReadyStable_M, ##1 !ReadyIsStable || $stable(ready_i)) + `ABR_ASSUME(ReqsStable_M, ##1 !ReqsAreStable || $stable(req_i)) + + // A grant implies a request + `ABR_ASSERT(GntImpliesReq_A, gnt_o[k] |-> req_i[k]) + + // if request and ready are constantly held at 1, we should eventually get a grant + `ABR_ASSERT(NoStarvation_A, + ReqsAreStable && ReadyIsStable && ready_i && req_i[k] |-> + strong(##[0:$] gnt_o[k])) + + // if N requests are constantly asserted and ready is constant 1, each request must + // be granted exactly once over a time window of N cycles for the arbiter to be fair. + for (genvar n = 1; n <= N; n++) begin : gen_fairness + integer gnt_cnt; + `ABR_ASSERT(Fairness_A, + ReqsAreStable && ReadyIsStable && ready_i && req_i[k] && + $countones(req_i) == n |-> + ##n gnt_cnt == $past(gnt_cnt, n) + 1) + + always_ff @(posedge clk_i or negedge rst_b) begin : p_cnt + if (!rst_b) begin + gnt_cnt <= 0; + end else begin + gnt_cnt <= gnt_cnt + gnt_o[k]; + end + end + end + + // requests must stay asserted until they have been granted + `ABR_ASSUME(ReqStaysHighUntilGranted1_M, req_i[k] && !gnt_o[k] |=> + req_i[k], clk_i, !rst_b || !req_chk_i) +`endif + +endmodule : abr_prim_arbiter_ppc diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert.sv new file mode 100644 index 0000000000000000000000000000000000000000..405e70b706da4b047650c155e726b8fe72213729 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert.sv @@ -0,0 +1,182 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macros and helper code for using assertions. +// - Provides default clk and rst options to simplify code +// - Provides boiler plate template for common assertions + +`ifndef ABR_PRIM_ASSERT_SV +`define ABR_PRIM_ASSERT_SV + +/////////////////// +// Helper macros // +/////////////////// + +`include "abr_sva.svh" +`ifndef ABR_SVA +// Default clk and reset signals used by assertion macros below. +`define ABR_ASSERT_DEFAULT_CLK clk_i +`define ABR_ASSERT_DEFAULT_RST !rst_b +`endif + +// Converts an arbitrary block of code into a Verilog string +`define ABR_PRIM_STRINGIFY(__x) `"__x`" + +// ABR_ASSERT_ERROR logs an error message with either `uvm_error or with $error. +// +// This somewhat duplicates `DV_ERROR macro defined in hw/dv/sv/dv_utils/dv_macros.svh. The reason +// for redefining it here is to avoid creating a dependency. +`define ABR_ASSERT_ERROR(__name) \ +`ifdef UVM \ + uvm_pkg::uvm_report_error("ABR_ASSERT FAILED", `ABR_PRIM_STRINGIFY(__name), uvm_pkg::UVM_NONE, \ + `__FILE__, `__LINE__, "", 1); \ +`else \ + $error("%0t: (%0s:%0d) [%m] [ABR_ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, \ + `ABR_PRIM_STRINGIFY(__name)); \ +`endif + +// This macro is suitable for conditionally triggering lint errors, e.g., if a Sec parameter takes +// on a non-default value. This may be required for pre-silicon/FPGA evaluation but we don't want +// to allow this for tapeout. +`define ABR_ASSERT_STATIC_LINT_ERROR(__name, __prop) \ + localparam int __name = (__prop) ? 1 : 2; \ + always_comb begin \ + logic unused_assert_static_lint_error; \ + unused_assert_static_lint_error = __name'(1'b1); \ + end + +// Static assertions for checks inside SV packages. If the conditions is not true, this will +// trigger an error during elaboration. +`define ABR_ASSERT_STATIC_IN_PACKAGE(__name, __prop) \ + function automatic logic assert_static_in_package_``__name(); \ + logic unused_bit [((__prop) ? 1 : -1)]; \ + unused_bit = '{default: 1'b0}; \ + return unused_bit[0]; \ + endfunction + +// The basic helper macros are actually defined in "implementation headers". The macros should do +// the same thing in each case (except for the dummy flavour), but in a way that the respective +// tools support. +// +// If the tool supports assertions in some form, we also define ABR_INC_ASSERT (which can be +// used to hide signal definitions that are only used for assertions). +// +// The list of basic macros supported is: +// +// ABR_ASSERT_I: Immediate assertion. Note that immediate assertions are sensitive to simulation +// glitches. +// +// ABR_ASSERT_INIT: Assertion in initial block. Can be used for things like parameter checking. +// +// ABR_ASSERT_INIT_NET: Assertion in initial block. Can be used for initial value of a net. +// +// ABR_ASSERT_FINAL: Assertion in final block. Can be used for things like queues being empty at end of +// sim, all credits returned at end of sim, state machines in idle at end of sim. +// +// ABR_ASSERT: Assert a concurrent property directly. It can be called as a module (or +// interface) body item. +// +// Note: We use (__rst !== '0) in the disable iff statements instead of (__rst == +// '1). This properly disables the assertion in cases when reset is X at the +// beginning of a simulation. For that case, (reset == '1) does not disable the +// assertion. +// +// ABR_ASSERT_NEVER: Assert a concurrent property NEVER happens +// +// ABR_ASSERT_KNOWN: Assert that signal has a known value (each bit is either '0' or '1') after reset. +// It can be called as a module (or interface) body item. +// +// ABR_COVER: Cover a concurrent property +// +// ABR_ASSUME: Assume a concurrent property +// +// ABR_ASSUME_I: Assume an immediate property + +`ifdef VERILATOR + `include "abr_prim_assert_dummy_macros.svh" +`elsif SYNTHESIS + `include "abr_prim_assert_dummy_macros.svh" +`elsif YOSYS + `include "abr_prim_assert_yosys_macros.svh" + `define ABR_INC_ASSERT +`else + `include "abr_prim_assert_standard_macros.svh" + `define ABR_INC_ASSERT +`endif + +////////////////////////////// +// Complex assertion macros // +////////////////////////////// + +// Assert that signal is an active-high pulse with pulse length of 1 clock cycle +`define ABR_ASSERT_PULSE(__name, __sig, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + `ABR_ASSERT(__name, $rose(__sig) |=> !(__sig), __clk, __rst) + +// Assert that a property is true only when an enable signal is set. It can be called as a module +// (or interface) body item. +`define ABR_ASSERT_IF(__name, __prop, __enable, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + `ABR_ASSERT(__name, (__enable) |-> (__prop), __clk, __rst) + +// Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is +// set. It can be called as a module (or interface) body item. +`define ABR_ASSERT_KNOWN_IF(__name, __sig, __enable, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + `ABR_ASSERT_KNOWN(__name``KnownEnable, __enable, __clk, __rst) \ + `ABR_ASSERT_IF(__name, !$isunknown(__sig), __enable, __clk, __rst) + +////////////////////////////////// +// For formal verification only // +////////////////////////////////// + +// Note that the existing set of ABR_ASSERT macros specified above shall be used for FPV, +// thereby ensuring that the assertions are evaluated during DV simulations as well. + +// ABR_ASSUME_FPV +// Assume a concurrent property during formal verification only. +`define ABR_ASSUME_FPV(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `ABR_ASSUME(__name, __prop, __clk, __rst) \ +`endif + +// ABR_ASSUME_I_FPV +// Assume a concurrent property during formal verification only. +`define ABR_ASSUME_I_FPV(__name, __prop) \ +`ifdef FPV_ON \ + `ABR_ASSUME_I(__name, __prop) \ +`endif + +// ABR_COVER_FPV +// Cover a concurrent property during formal verification +`define ABR_COVER_FPV(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ +`ifdef FPV_ON \ + `ABR_COVER(__name, __prop, __clk, __rst) \ +`endif + +// FPV assertion that proves that the FSM control flow is linear (no loops) +// The sequence triggers whenever the state changes and stores the current state as "initial_state". +// Then thereafter we must never see that state again until reset. +// It is possible for the reset to release ahead of the clock. +// Create a small "gray" window beyond the usual rst time to avoid +// checking. +`define ABR_ASSERT_FPV_LINEAR_FSM(__name, __state, __type, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + `ifdef ABR_INC_ASSERT \ + bit __name``_cond; \ + always_ff @(posedge __clk or posedge __rst) begin \ + if (__rst) begin \ + __name``_cond <= 0; \ + end else begin \ + __name``_cond <= 1; \ + end \ + end \ + property __name``_p; \ + __type initial_state; \ + (!$stable(__state) & __name``_cond, initial_state = $past(__state)) |-> \ + (__state != initial_state) until (__rst == 1'b1); \ + endproperty \ + `ABR_ASSERT(__name, __name``_p, __clk, __rst) \ + `endif + +`include "abr_prim_assert_sec_cm.svh" +`include "abr_prim_flop_macros.sv" + +`endif // PRIM_ASSERT_SV diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_dummy_macros.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_dummy_macros.svh new file mode 100644 index 0000000000000000000000000000000000000000..6d6210cbc7bb358458cbf8780a44bcbb707d6428 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_dummy_macros.svh @@ -0,0 +1,19 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macro bodies included by abr_prim_assert.sv for tools that don't support assertions. See +// abr_prim_assert.sv for documentation for each of the macros. + +`define ABR_ASSERT_I(__name, __prop) +`define ABR_ASSERT_INIT(__name, __prop) +`define ABR_ASSERT_INIT_NET(__name, __prop) +`define ABR_ASSERT_FINAL(__name, __prop) +`ifndef ABR_SVA +`define ABR_ASSERT(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) +`define ABR_ASSERT_NEVER(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) +`define ABR_ASSERT_KNOWN(__name, __sig, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) +`endif +`define ABR_COVER(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) +`define ABR_ASSUME(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) +`define ABR_ASSUME_I(__name, __prop) diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_sec_cm.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_sec_cm.svh new file mode 100644 index 0000000000000000000000000000000000000000..028f40b01ece0e01c1d0b7c22eb2bfe678dc0c74 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_sec_cm.svh @@ -0,0 +1,48 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// // Macros and helper code for security countermeasures. + +`ifndef ABR_PRIM_ASSERT_SEC_CM_SVH +`define ABR_PRIM_ASSERT_SEC_CM_SVH + +`define _ABR_SEC_CM_ALERT_MAX_CYC 30 + +// Helper macros +`define ABR_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, ERR_NAME_) \ + `ABR_ASSERT(FpvSecCm``NAME_``, \ + $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \ + |-> ##[0:MAX_CYCLES_] (ALERT_.alert_p)) \ + `ifdef ABR_INC_ASSERT \ + assign PRIM_HIER_.unused_assert_connected = 1'b1; \ + `endif \ + `ABR_ASSUME_FPV(``NAME_``TriggerAfterAlertInit_S, $stable(rst_b) == 0 |-> \ + PRIM_HIER_.ERR_NAME_ == 0 [*10]) + +`define ABR_ASSERT_ERROR_TRIGGER_ERR(NAME_, PRIM_HIER_, ERR_, GATE_, MAX_CYCLES_, ERR_NAME_, CLK_, RST_) \ + `ABR_ASSERT(FpvSecCm``NAME_``, \ + $rose(PRIM_HIER_.ERR_NAME_) && !(GATE_) \ + |-> ##[0:MAX_CYCLES_] (ERR_), CLK_, RST_) \ + `ifdef ABR_INC_ASSERT \ + assign PRIM_HIER_.unused_assert_connected = 1'b1; \ + `endif + +// macros for security countermeasures that will trigger alert +`define ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_ABR_SEC_CM_ALERT_MAX_CYC) \ + `ABR_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o) + +`define ABR_ASSERT_PRIM_DOUBLE_LFSR_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_ABR_SEC_CM_ALERT_MAX_CYC) \ + `ABR_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o) + +`define ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_ABR_SEC_CM_ALERT_MAX_CYC) \ + `ABR_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, unused_err_o) + +`define ABR_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_ABR_SEC_CM_ALERT_MAX_CYC) \ + `ABR_ASSERT_ERROR_TRIGGER_ALERT(NAME_, PRIM_HIER_, ALERT_, GATE_, MAX_CYCLES_, err_o) + +`define ABR_ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, REG_TOP_HIER_, ALERT_, GATE_ = 0, MAX_CYCLES_ = `_ABR_SEC_CM_ALERT_MAX_CYC) \ + `ABR_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT(NAME_, \ + REG_TOP_HIER_.u_abr_prim_reg_we_check.u_abr_prim_onehot_check, ALERT_, GATE_, MAX_CYCLES_) + +`endif // PRIM_ASSERT_SEC_CM_SVH diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_standard_macros.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_standard_macros.svh new file mode 100644 index 0000000000000000000000000000000000000000..f5a3fec0f62cb4be6358fc16200a3ce29bd8ba93 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_standard_macros.svh @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macro bodies included by abr_prim_assert.sv for tools that support full SystemVerilog and SVA syntax. +// See abr_prim_assert.sv for documentation for each of the macros. + +`define ABR_ASSERT_I(__name, __prop) \ + __name: assert (__prop) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end + +// Formal tools will ignore the initial construct, so use static assertion as a workaround. +// This workaround terminates design elaboration if the __prop predict is false. +// It calls $fatal() with the first argument equal to 2, it outputs the statistics about the memory +// and CPU time. +`define ABR_ASSERT_INIT(__name, __prop) \ +`ifdef FPV_ON \ + if (!(__prop)) $fatal(2, "Fatal static assertion [%s]: (%s) is not true.", \ + (__name), (__prop)); \ +`else \ + initial begin \ + __name: assert (__prop) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end \ + end \ +`endif + +`define ABR_ASSERT_INIT_NET(__name, __prop) \ + initial begin \ + // When a net is assigned with a value, the assignment is evaluated after \ + // initial in Xcelium. Add 1ps delay to check value after the assignment is \ + // completed. \ + #1ps; \ + __name: assert (__prop) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end \ + end \ + +`define ABR_ASSERT_FINAL(__name, __prop) \ + final begin \ + __name: assert (__prop || $test$plusargs("disable_assert_final_checks")) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end \ + end + +`ifndef ABR_SVA +`define ABR_ASSERT(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end + +`define ABR_ASSERT_NEVER(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + __name: assert property (@(posedge __clk) disable iff ((__rst) !== '0) not (__prop)) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end + +`define ABR_ASSERT_KNOWN(__name, __sig, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + `ABR_ASSERT(__name, !$isunknown(__sig), __clk, __rst) +`endif + +`define ABR_COVER(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + __name: cover property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)); + +`define ABR_ASSUME(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + __name: assume property (@(posedge __clk) disable iff ((__rst) !== '0) (__prop)) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end + +`define ABR_ASSUME_I(__name, __prop) \ + __name: assume (__prop) \ + else begin \ + `ABR_ASSERT_ERROR(__name) \ + end diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_yosys_macros.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_yosys_macros.svh new file mode 100644 index 0000000000000000000000000000000000000000..2ef9e7c0e549b48a90e310788b4cd41d0211453b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_assert_yosys_macros.svh @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Macro bodies included by abr_prim_assert.sv for formal verification with Yosys. See abr_prim_assert.sv +// for documentation for each of the macros. + +`define ABR_ASSERT_I(__name, __prop) \ + always_comb begin : __name \ + assert (__prop); \ + end + +`define ABR_ASSERT_INIT(__name, __prop) \ + initial begin : __name \ + assert (__prop); \ + end + +`define ABR_ASSERT_INIT_NET(__name, __prop) \ + initial begin : __name \ + #1ps assert (__prop); \ + end + +// This doesn't make much sense for a formal tool (we never get to the final block!) +`define ABR_ASSERT_FINAL(__name, __prop) + +`ifndef ABR_SVA +`define ABR_ASSERT(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + always_ff @(posedge __clk) begin \ + if (! (__rst !== '0)) __name: assert (__prop); \ + end + +`define ABR_ASSERT_NEVER(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + always_ff @(posedge __clk) begin \ + if (! (__rst !== '0)) __name: assert (! (__prop)); \ + end + +// Yosys uses 2-state logic, so this doesn't make sense here +`define ABR_ASSERT_KNOWN(__name, __sig, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) +`endif + +`define ABR_COVER(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + always_ff @(posedge __clk) begin : __name \ + cover ((! (__rst !== '0)) && (__prop)); \ + end + +`define ABR_ASSUME(__name, __prop, __clk = `ABR_ASSERT_DEFAULT_CLK, __rst = `ABR_ASSERT_DEFAULT_RST) \ + always_ff @(posedge __clk) begin \ + if (! (__rst !== '0)) __name: assume (__prop); \ + end + +`define ABR_ASSUME_I(__name, __prop) \ + always_comb begin : __name \ + assume (__prop); \ + end diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_buf.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_buf.sv new file mode 100644 index 0000000000000000000000000000000000000000..72e0e68b69e570bd73c84369aa7576b9be935c5f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_buf.sv @@ -0,0 +1,42 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is auto-generated. +// Used parser: Verible + +`ifndef ABR_PRIM_DEFAULT_IMPL + `define ABR_PRIM_DEFAULT_IMPL abr_prim_pkg::ImplGeneric +`endif + +// This is to prevent AscentLint warnings in the generated +// abstract prim wrapper. These warnings occur due to the .* +// use. TODO: we may want to move these inline waivers +// into a separate, generated waiver file for consistency. +//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ +module abr_prim_buf + +#( +parameter int Width = 1 +) ( + input [Width-1:0] in_i, + output logic [Width-1:0] out_o +); + parameter abr_prim_pkg::impl_e Impl = `ABR_PRIM_DEFAULT_IMPL; + +if (Impl == abr_prim_pkg::ImplXilinx) begin : gen_xilinx + abr_prim_xilinx_buf #( + .Width(Width) + ) u_impl_xilinx ( + .* + ); +end else begin : gen_generic + abr_prim_generic_buf #( + .Width(Width) + ) u_impl_generic ( + .* + ); +end + +endmodule +//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv new file mode 100644 index 0000000000000000000000000000000000000000..b68c79342202402502215448c443fd57b8ea5aa5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv @@ -0,0 +1,63 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This module should be instantiated within flops of CDC synchronization primitives, +// and allows DV to model real CDC delays within simulations, especially useful at the chip level +// or in IPs that communicate across clock domains. +// +// The instrumentation is very simple: when this is enabled the input into the first +// synchronizer flop has a mux where the select is randomly set. One of the mux inputs is the input +// of this module, and the other is the output of the first flop: selecting the latter models the +// effect of the first flop missing the input transition. +// +// Notice the delay should cause the input to be skipped by at most a single cycle. As a perhaps +// unnecessary precaution, the select will only be allowed to be random when the input changes. + +module abr_prim_cdc_rand_delay #( + parameter int DataWidth = 1, + parameter bit Enable = 1 +) ( + input logic clk_i, + input logic rst_b, + input logic [DataWidth-1:0] prev_data_i, + input logic [DataWidth-1:0] src_data_i, + output logic [DataWidth-1:0] dst_data_o +); +`ifdef ABR_SIMULATION + if (Enable) begin : gen_enable + + // This controls dst_data_o: any bit with its data_sel set uses prev_data_i, others use + // src_data_i. + bit [DataWidth-1:0] data_sel; + bit cdc_instrumentation_enabled; + + function automatic bit [DataWidth-1:0] fast_randomize(); + bit [DataWidth-1:0] data; + bit [31:0] urandom_result; + for (int i = 0; i < DataWidth; i += 32) begin + data = data << 32; + urandom_result = $urandom(); + data = data | urandom_result; + end + return data; + endfunction + + initial begin + void'($value$plusargs("cdc_instrumentation_enabled=%d", cdc_instrumentation_enabled)); + data_sel = '0; + end + + // Set data_sel at random combinationally when the input changes. + always @(src_data_i) begin + data_sel = cdc_instrumentation_enabled ? fast_randomize() : 0; + end + + always_comb dst_data_o = (prev_data_i & data_sel) | (src_data_i & ~data_sel); + end else begin : gen_no_enable + assign dst_data_o = src_data_i; + end +`else // ABR_SIMULATION + assign dst_data_o = src_data_i; +`endif // ABR_SIMULATION +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_cipher_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_cipher_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..0513e385831bdb1b1f58be01362d949a1528a8df --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_cipher_pkg.sv @@ -0,0 +1,397 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This package holds common constants and functions for PRESENT- and +// PRINCE-based scrambling devices. +// +// See also: abr_prim_present, abr_prim_prince +// +// References: - https://en.wikipedia.org/wiki/PRESENT +// - https://en.wikipedia.org/wiki/Prince_(cipher) +// - http://www.lightweightcrypto.org/present/present_ches2007.pdf +// - https://eprint.iacr.org/2012/529.pdf +// - https://eprint.iacr.org/2015/372.pdf +// - https://eprint.iacr.org/2014/656.pdf + +package abr_prim_cipher_pkg; + + /////////////////// + // PRINCE Cipher // + /////////////////// + + parameter logic [15:0][3:0] PRINCE_SBOX4 = {4'h4, 4'hD, 4'h5, 4'hE, + 4'h0, 4'h8, 4'h7, 4'h6, + 4'h1, 4'h9, 4'hC, 4'hA, + 4'h2, 4'h3, 4'hF, 4'hB}; + + parameter logic [15:0][3:0] PRINCE_SBOX4_INV = {4'h1, 4'hC, 4'hE, 4'h5, + 4'h0, 4'h4, 4'h6, 4'hA, + 4'h9, 4'h8, 4'hD, 4'hF, + 4'h2, 4'h3, 4'h7, 4'hB}; + // nibble permutations + parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64 = '{4'hF, 4'hA, 4'h5, 4'h0, + 4'hB, 4'h6, 4'h1, 4'hC, + 4'h7, 4'h2, 4'hD, 4'h8, + 4'h3, 4'hE, 4'h9, 4'h4}; + + parameter logic [15:0][3:0] PRINCE_SHIFT_ROWS64_INV = '{4'hF, 4'h2, 4'h5, 4'h8, + 4'hB, 4'hE, 4'h1, 4'h4, + 4'h7, 4'hA, 4'hD, 4'h0, + 4'h3, 4'h6, 4'h9, 4'hC}; + + // these are the round constants + parameter logic [11:0][63:0] PRINCE_ROUND_CONST = {64'hC0AC29B7C97C50DD, + 64'hD3B5A399CA0C2399, + 64'h64A51195E0E3610D, + 64'hC882D32F25323C54, + 64'h85840851F1AC43AA, + 64'h7EF84F78FD955CB1, + 64'hBE5466CF34E90C6C, + 64'h452821E638D01377, + 64'h082EFA98EC4E6C89, + 64'hA4093822299F31D0, + 64'h13198A2E03707344, + 64'h0000000000000000}; + + // tweak constant for key modification between enc/dec modes + parameter logic [63:0] PRINCE_ALPHA_CONST = 64'hC0AC29B7C97C50DD; + + // masking constants for shift rows function below + parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST0 = 16'h7BDE; + parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST1 = 16'hBDE7; + parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST2 = 16'hDE7B; + parameter logic [15:0] PRINCE_SHIFT_ROWS_CONST3 = 16'hE7BD; + + // nibble shifts + function automatic logic [31:0] prince_shiftrows_32bit(logic [31:0] state_in, + logic [15:0][3:0] shifts ); + logic [31:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 32/2; k++) begin + // operate on pairs of 2bit instead of nibbles + state_out[k*2 +: 2] = state_in[shifts[k]*2 +: 2]; + end + return state_out; + endfunction : prince_shiftrows_32bit + + function automatic logic [63:0] prince_shiftrows_64bit(logic [63:0] state_in, + logic [15:0][3:0] shifts ); + logic [63:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 64/4; k++) begin + state_out[k*4 +: 4] = state_in[shifts[k]*4 +: 4]; + end + return state_out; + endfunction : prince_shiftrows_64bit + + // XOR reduction of four nibbles in a 16bit subvector + function automatic logic [3:0] prince_nibble_red16(logic [15:0] vect); + return vect[0 +: 4] ^ vect[4 +: 4] ^ vect[8 +: 4] ^ vect[12 +: 4]; + endfunction : prince_nibble_red16 + + // M prime multiplication + function automatic logic [31:0] prince_mult_prime_32bit(logic [31:0] state_in); + logic [31:0] state_out; + // M0 + state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3); + state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2); + state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1); + state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0); + // M1 + state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0); + state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3); + state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2); + state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1); + return state_out; + endfunction : prince_mult_prime_32bit + + // M prime multiplication + function automatic logic [63:0] prince_mult_prime_64bit(logic [63:0] state_in); + logic [63:0] state_out; + // M0 + state_out[0 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST3); + state_out[4 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST2); + state_out[8 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST1); + state_out[12 +: 4] = prince_nibble_red16(state_in[ 0 +: 16] & PRINCE_SHIFT_ROWS_CONST0); + // M1 + state_out[16 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST0); + state_out[20 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST3); + state_out[24 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST2); + state_out[28 +: 4] = prince_nibble_red16(state_in[16 +: 16] & PRINCE_SHIFT_ROWS_CONST1); + // M1 + state_out[32 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST0); + state_out[36 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST3); + state_out[40 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST2); + state_out[44 +: 4] = prince_nibble_red16(state_in[32 +: 16] & PRINCE_SHIFT_ROWS_CONST1); + // M0 + state_out[48 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST3); + state_out[52 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST2); + state_out[56 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST1); + state_out[60 +: 4] = prince_nibble_red16(state_in[48 +: 16] & PRINCE_SHIFT_ROWS_CONST0); + return state_out; + endfunction : prince_mult_prime_64bit + + + //////////////////// + // PRESENT Cipher // + //////////////////// + + // this is the sbox from the present cipher + parameter logic [15:0][3:0] PRESENT_SBOX4 = {4'h2, 4'h1, 4'h7, 4'h4, + 4'h8, 4'hF, 4'hE, 4'h3, + 4'hD, 4'hA, 4'h0, 4'h9, + 4'hB, 4'h6, 4'h5, 4'hC}; + + parameter logic [15:0][3:0] PRESENT_SBOX4_INV = {4'hA, 4'h9, 4'h7, 4'h0, + 4'h3, 4'h6, 4'h4, 4'hB, + 4'hD, 4'h2, 4'h1, 4'hC, + 4'h8, 4'hF, 4'hE, 4'h5}; + + // these are modified permutation indices for a 32bit version that + // follow the same pattern as for the 64bit version + parameter logic [31:0][4:0] PRESENT_PERM32 = {5'd31, 5'd23, 5'd15, 5'd07, + 5'd30, 5'd22, 5'd14, 5'd06, + 5'd29, 5'd21, 5'd13, 5'd05, + 5'd28, 5'd20, 5'd12, 5'd04, + 5'd27, 5'd19, 5'd11, 5'd03, + 5'd26, 5'd18, 5'd10, 5'd02, + 5'd25, 5'd17, 5'd09, 5'd01, + 5'd24, 5'd16, 5'd08, 5'd00}; + + parameter logic [31:0][4:0] PRESENT_PERM32_INV = {5'd31, 5'd27, 5'd23, 5'd19, + 5'd15, 5'd11, 5'd07, 5'd03, + 5'd30, 5'd26, 5'd22, 5'd18, + 5'd14, 5'd10, 5'd06, 5'd02, + 5'd29, 5'd25, 5'd21, 5'd17, + 5'd13, 5'd09, 5'd05, 5'd01, + 5'd28, 5'd24, 5'd20, 5'd16, + 5'd12, 5'd08, 5'd04, 5'd00}; + + // these are the permutation indices of the present cipher + parameter logic [63:0][5:0] PRESENT_PERM64 = {6'd63, 6'd47, 6'd31, 6'd15, + 6'd62, 6'd46, 6'd30, 6'd14, + 6'd61, 6'd45, 6'd29, 6'd13, + 6'd60, 6'd44, 6'd28, 6'd12, + 6'd59, 6'd43, 6'd27, 6'd11, + 6'd58, 6'd42, 6'd26, 6'd10, + 6'd57, 6'd41, 6'd25, 6'd09, + 6'd56, 6'd40, 6'd24, 6'd08, + 6'd55, 6'd39, 6'd23, 6'd07, + 6'd54, 6'd38, 6'd22, 6'd06, + 6'd53, 6'd37, 6'd21, 6'd05, + 6'd52, 6'd36, 6'd20, 6'd04, + 6'd51, 6'd35, 6'd19, 6'd03, + 6'd50, 6'd34, 6'd18, 6'd02, + 6'd49, 6'd33, 6'd17, 6'd01, + 6'd48, 6'd32, 6'd16, 6'd00}; + + parameter logic [63:0][5:0] PRESENT_PERM64_INV = {6'd63, 6'd59, 6'd55, 6'd51, + 6'd47, 6'd43, 6'd39, 6'd35, + 6'd31, 6'd27, 6'd23, 6'd19, + 6'd15, 6'd11, 6'd07, 6'd03, + 6'd62, 6'd58, 6'd54, 6'd50, + 6'd46, 6'd42, 6'd38, 6'd34, + 6'd30, 6'd26, 6'd22, 6'd18, + 6'd14, 6'd10, 6'd06, 6'd02, + 6'd61, 6'd57, 6'd53, 6'd49, + 6'd45, 6'd41, 6'd37, 6'd33, + 6'd29, 6'd25, 6'd21, 6'd17, + 6'd13, 6'd09, 6'd05, 6'd01, + 6'd60, 6'd56, 6'd52, 6'd48, + 6'd44, 6'd40, 6'd36, 6'd32, + 6'd28, 6'd24, 6'd20, 6'd16, + 6'd12, 6'd08, 6'd04, 6'd00}; + + // forward key schedule + function automatic logic [63:0] present_update_key64(logic [63:0] key_in, + logic [4:0] round_idx); + logic [63:0] key_out; + // rotate by 61 to the left + key_out = {key_in[63-61:0], key_in[63:64-61]}; + // sbox on uppermost 4 bits + key_out[63 -: 4] = PRESENT_SBOX4[key_out[63 -: 4]]; + // xor in round counter on bits 19 to 15 + key_out[19:15] ^= round_idx; + return key_out; + endfunction : present_update_key64 + + function automatic logic [79:0] present_update_key80(logic [79:0] key_in, + logic [4:0] round_idx); + logic [79:0] key_out; + // rotate by 61 to the left + key_out = {key_in[79-61:0], key_in[79:80-61]}; + // sbox on uppermost 4 bits + key_out[79 -: 4] = PRESENT_SBOX4[key_out[79 -: 4]]; + // xor in round counter on bits 19 to 15 + key_out[19:15] ^= round_idx; + return key_out; + endfunction : present_update_key80 + + function automatic logic [127:0] present_update_key128(logic [127:0] key_in, + logic [4:0] round_idx); + logic [127:0] key_out; + // rotate by 61 to the left + key_out = {key_in[127-61:0], key_in[127:128-61]}; + // sbox on uppermost 4 bits + key_out[127 -: 4] = PRESENT_SBOX4[key_out[127 -: 4]]; + // sbox on second nibble from top + key_out[123 -: 4] = PRESENT_SBOX4[key_out[123 -: 4]]; + // xor in round counter on bits 66 to 62 + key_out[66:62] ^= round_idx; + return key_out; + endfunction : present_update_key128 + + + // inverse key schedule + function automatic logic [63:0] present_inv_update_key64(logic [63:0] key_in, + logic [4:0] round_idx); + logic [63:0] key_out = key_in; + // xor in round counter on bits 19 to 15 + key_out[19:15] ^= round_idx; + // sbox on uppermost 4 bits + key_out[63 -: 4] = PRESENT_SBOX4_INV[key_out[63 -: 4]]; + // rotate by 61 to the right + key_out = {key_out[60:0], key_out[63:61]}; + return key_out; + endfunction : present_inv_update_key64 + + function automatic logic [79:0] present_inv_update_key80(logic [79:0] key_in, + logic [4:0] round_idx); + logic [79:0] key_out = key_in; + // xor in round counter on bits 19 to 15 + key_out[19:15] ^= round_idx; + // sbox on uppermost 4 bits + key_out[79 -: 4] = PRESENT_SBOX4_INV[key_out[79 -: 4]]; + // rotate by 61 to the right + key_out = {key_out[60:0], key_out[79:61]}; + return key_out; + endfunction : present_inv_update_key80 + + function automatic logic [127:0] present_inv_update_key128(logic [127:0] key_in, + logic [4:0] round_idx); + logic [127:0] key_out = key_in; + // xor in round counter on bits 66 to 62 + key_out[66:62] ^= round_idx; + // sbox on second highest nibble + key_out[123 -: 4] = PRESENT_SBOX4_INV[key_out[123 -: 4]]; + // sbox on uppermost 4 bits + key_out[127 -: 4] = PRESENT_SBOX4_INV[key_out[127 -: 4]]; + // rotate by 61 to the right + key_out = {key_out[60:0], key_out[127:61]}; + return key_out; + endfunction : present_inv_update_key128 + + + // these functions can be used to derive the DEC key from the ENC key by + // stepping the key by the correct number of rounds using the keyschedule functions above. + function automatic logic [63:0] present_get_dec_key64(logic [63:0] key_in, + // total number of rounds employed + logic [4:0] round_cnt); + logic [63:0] key_out; + key_out = key_in; + for (int unsigned k = 0; k < round_cnt; k++) begin + key_out = present_update_key64(key_out, 5'(k + 1)); + end + return key_out; + endfunction : present_get_dec_key64 + + function automatic logic [79:0] present_get_dec_key80(logic [79:0] key_in, + // total number of rounds employed + logic [4:0] round_cnt); + logic [79:0] key_out; + key_out = key_in; + for (int unsigned k = 0; k < round_cnt; k++) begin + key_out = present_update_key80(key_out, 5'(k + 1)); + end + return key_out; + endfunction : present_get_dec_key80 + + function automatic logic [127:0] present_get_dec_key128(logic [127:0] key_in, + // total number of rounds employed + logic [4:0] round_cnt); + logic [127:0] key_out; + key_out = key_in; + for (int unsigned k = 0; k < round_cnt; k++) begin + key_out = present_update_key128(key_out, 5'(k + 1)); + end + return key_out; + endfunction : present_get_dec_key128 + + ///////////////////////// + // Common Subfunctions // + ///////////////////////// + + function automatic logic [7:0] sbox4_8bit(logic [7:0] state_in, logic [15:0][3:0] sbox4); + logic [7:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 8/4; k++) begin + state_out[k*4 +: 4] = sbox4[state_in[k*4 +: 4]]; + end + return state_out; + endfunction : sbox4_8bit + + function automatic logic [15:0] sbox4_16bit(logic [15:0] state_in, logic [15:0][3:0] sbox4); + logic [15:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 2; k++) begin + state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4); + end + return state_out; + endfunction : sbox4_16bit + + function automatic logic [31:0] sbox4_32bit(logic [31:0] state_in, logic [15:0][3:0] sbox4); + logic [31:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 4; k++) begin + state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4); + end + return state_out; + endfunction : sbox4_32bit + + function automatic logic [63:0] sbox4_64bit(logic [63:0] state_in, logic [15:0][3:0] sbox4); + logic [63:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 8; k++) begin + state_out[k*8 +: 8] = sbox4_8bit(state_in[k*8 +: 8], sbox4); + end + return state_out; + endfunction : sbox4_64bit + + function automatic logic [7:0] perm_8bit(logic [7:0] state_in, logic [7:0][2:0] perm); + logic [7:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 8; k++) begin + state_out[perm[k]] = state_in[k]; + end + return state_out; + endfunction : perm_8bit + + function automatic logic [15:0] perm_16bit(logic [15:0] state_in, logic [15:0][3:0] perm); + logic [15:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 16; k++) begin + state_out[perm[k]] = state_in[k]; + end + return state_out; + endfunction : perm_16bit + + function automatic logic [31:0] perm_32bit(logic [31:0] state_in, logic [31:0][4:0] perm); + logic [31:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 32; k++) begin + state_out[perm[k]] = state_in[k]; + end + return state_out; + endfunction : perm_32bit + + function automatic logic [63:0] perm_64bit(logic [63:0] state_in, logic [63:0][5:0] perm); + logic [63:0] state_out; + // note that if simulation performance becomes an issue, this loop can be unrolled + for (int k = 0; k < 64; k++) begin + state_out[perm[k]] = state_in[k]; + end + return state_out; + endfunction : perm_64bit + +endpackage : abr_prim_cipher_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_count.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_count.sv new file mode 100644 index 0000000000000000000000000000000000000000..9f413b4e01446cbf4483bbfd41abbe4ce2d52884 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_count.sv @@ -0,0 +1,261 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Hardened counter primitive: +// +// This internally uses a cross counter scheme with primary and a secondary counter, where the +// secondary counter counts in reverse direction. The sum of both counters must remain constant and +// equal to 2**Width-1 or otherwise an err_o will be asserted. +// +// This counter supports a generic clear / set / increment / decrement interface: +// +// clr_i: This clears the primary counter to ResetValue and adjusts the secondary counter to match +// (i.e. 2**Width-1-ResetValue). Clear has priority over set, increment and decrement. +// set_i: This sets the primary counter to set_cnt_i and adjusts the secondary counter to match +// (i.e. 2**Width-1-set_cnt_i). Set has priority over increment and decrement. +// incr_en_i: Increments the primary counter by step_i, and decrements the secondary by step_i. +// decr_en_i: Decrements the primary counter by step_i, and increments the secondary by step_i. +// +// Note that if both incr_en_i and decr_en_i are asserted at the same time, the counter remains +// unchanged. The counter is also protected against under- and overflows. + +`include "abr_prim_assert.sv" + +module abr_prim_count #( + parameter int Width = 2, + // Can be used to reset the counter to a different value than 0, for example when + // the counter is used as a down-counter. + parameter logic [Width-1:0] ResetValue = '0, + // This should only be disabled in special circumstances, for example + // in non-comportable IPs where an error does not trigger an alert. + parameter bit EnableAlertTriggerSVA = 1 +) ( + input clk_i, + input rst_b, + input clr_i, + input set_i, + input [Width-1:0] set_cnt_i, // Set value for the counter. + input incr_en_i, + input decr_en_i, + input [Width-1:0] step_i, // Increment/decrement step when enabled. + output logic [Width-1:0] cnt_o, // Current counter state + output logic [Width-1:0] cnt_next_o, // Next counter state + output logic err_o +); + + /////////////////// + // Counter logic // + /////////////////// + + // Reset Values for primary and secondary counters. + localparam int NumCnt = 2; + localparam logic [NumCnt-1:0][Width-1:0] ResetValues = {{Width{1'b1}} - ResetValue, // secondary + ResetValue}; // primary + + logic [NumCnt-1:0][Width-1:0] cnt_d, cnt_q, fpv_force; + +`ifndef FPV_SEC_CM_ON + // This becomes a free variable in FPV. + assign fpv_force = '0; +`endif + + for (genvar k = 0; k < NumCnt; k++) begin : gen_cnts + // Note that increments / decrements are reversed for the secondary counter. + logic incr_en, decr_en; + logic [Width-1:0] set_val; + if (k == 0) begin : gen_up_cnt + assign incr_en = incr_en_i; + assign decr_en = decr_en_i; + assign set_val = set_cnt_i; + end else begin : gen_dn_cnt + assign incr_en = decr_en_i; + assign decr_en = incr_en_i; + // The secondary value needs to be adjusted accordingly. + assign set_val = {Width{1'b1}} - set_cnt_i; + end + + // Main counter logic + logic [Width:0] ext_cnt; + assign ext_cnt = (decr_en) ? {1'b0, cnt_q[k]} - {1'b0, step_i} : + (incr_en) ? {1'b0, cnt_q[k]} + {1'b0, step_i} : {1'b0, cnt_q[k]}; + + // Saturation logic + logic uflow, oflow; + assign oflow = incr_en && ext_cnt[Width]; + assign uflow = decr_en && ext_cnt[Width]; + logic [Width-1:0] cnt_sat; + assign cnt_sat = (uflow) ? '0 : + (oflow) ? {Width{1'b1}} : ext_cnt[Width-1:0]; + + // Clock gate flops when in saturation, and do not + // count if both incr_en and decr_en are asserted. + logic cnt_en; + assign cnt_en = (incr_en ^ decr_en) && + ((incr_en && !(&cnt_q[k])) || + (decr_en && !(cnt_q[k] == '0))); + + // Counter muxes + assign cnt_d[k] = (clr_i) ? ResetValues[k] : + (set_i) ? set_val : + (cnt_en) ? cnt_sat : cnt_q[k]; + + logic [Width-1:0] cnt_unforced_q; + abr_prim_flop #( + .Width(Width), + .ResetValue(ResetValues[k]) + ) u_cnt_flop ( + .clk_i, + .rst_b, + .d_i(cnt_d[k]), + .q_o(cnt_unforced_q) + ); + + // fpv_force is only used during FPV. + assign cnt_q[k] = fpv_force[k] + cnt_unforced_q; + end + + // The sum of both counters must always equal the counter maximum. + logic [Width:0] sum; + assign sum = (cnt_q[0] + cnt_q[1]); + assign err_o = (sum != {1'b0, {Width{1'b1}}}); + + // Output count values + assign cnt_o = cnt_q[0]; + assign cnt_next_o = cnt_d[0]; + + //////////////// + // Assertions // + //////////////// +`ifdef ABR_INC_ASSERT + //VCS coverage off + // pragma coverage off + + // We need to disable most assertions in that case using a helper signal. + // We can't rely on err_o since some error patterns cannot be detected (e.g. all error + // patterns that still fullfill the sum constraint). + logic fpv_err_present; + assign fpv_err_present = |fpv_force; + + // Helper functions for assertions. + function automatic logic signed [Width+1:0] max(logic signed [Width+1:0] a, + logic signed [Width+1:0] b); + return (a > b) ? a : b; + endfunction + + function automatic logic signed [Width+1:0] min(logic signed [Width+1:0] a, + logic signed [Width+1:0] b); + return (a < b) ? a : b; + endfunction + //VCS coverage on + // pragma coverage on + + // Cnt next + `ABR_ASSERT(CntNext_A, + rst_b + |=> + cnt_o == $past(cnt_next_o), + clk_i, err_o || fpv_err_present || !rst_b) + + // Clear + `ABR_ASSERT(ClrFwd_A, + rst_b && clr_i + |=> + (cnt_o == ResetValue) && + (cnt_q[1] == ({Width{1'b1}} - ResetValue)), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(ClrBkwd_A, + rst_b && !(incr_en_i || decr_en_i || set_i) ##1 + $changed(cnt_o) && $changed(cnt_q[1]) + |-> + $past(clr_i), + clk_i, err_o || fpv_err_present || !rst_b) + + // Set + `ABR_ASSERT(SetFwd_A, + rst_b && set_i && !clr_i + |=> + (cnt_o == $past(set_cnt_i)) && + (cnt_q[1] == ({Width{1'b1}} - $past(set_cnt_i))), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(SetBkwd_A, + rst_b && !(incr_en_i || decr_en_i || clr_i) ##1 + $changed(cnt_o) && $changed(cnt_q[1]) + |-> + $past(set_i), + clk_i, err_o || fpv_err_present || !rst_b) + + // Do not count if both increment and decrement are asserted. + `ABR_ASSERT(IncrDecrUpDnCnt_A, + rst_b && incr_en_i && decr_en_i && !(clr_i || set_i) + |=> + $stable(cnt_o) && $stable(cnt_q[1]), + clk_i, err_o || fpv_err_present || !rst_b) + + // Up counter + `ABR_ASSERT(IncrUpCnt_A, + rst_b && incr_en_i && !(clr_i || set_i || decr_en_i) + |=> + cnt_o == min($past(cnt_o) + $past({2'b0, step_i}), {2'b0, {Width{1'b1}}}), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(IncrDnCnt_A, + rst_b && incr_en_i && !(clr_i || set_i || decr_en_i) + |=> + cnt_q[1] == max($past(signed'({2'b0, cnt_q[1]})) - $past({2'b0, step_i}), '0), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(UpCntIncrStable_A, + incr_en_i && !(clr_i || set_i || decr_en_i) && + cnt_o == {Width{1'b1}} + |=> + $stable(cnt_o), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(UpCntDecrStable_A, + decr_en_i && !(clr_i || set_i || incr_en_i) && + cnt_o == '0 + |=> + $stable(cnt_o), + clk_i, err_o || fpv_err_present || !rst_b) + + // Down counter + `ABR_ASSERT(DecrUpCnt_A, + rst_b && decr_en_i && !(clr_i || set_i || incr_en_i) + |=> + cnt_o == max($past(signed'({2'b0, cnt_o})) - $past({2'b0, step_i}), '0), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(DecrDnCnt_A, + rst_b && decr_en_i && !(clr_i || set_i || incr_en_i) + |=> + cnt_q[1] == min($past(cnt_q[1]) + $past({2'b0, step_i}), {2'b0, {Width{1'b1}}}), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(DnCntIncrStable_A, + rst_b && incr_en_i && !(clr_i || set_i || decr_en_i) && + cnt_q[1] == '0 + |=> + $stable(cnt_q[1]), + clk_i, err_o || fpv_err_present || !rst_b) + `ABR_ASSERT(DnCntDecrStable_A, + rst_b && decr_en_i && !(clr_i || set_i || incr_en_i) && + cnt_q[1] == {Width{1'b1}} + |=> + $stable(cnt_q[1]), + clk_i, err_o || fpv_err_present || !rst_b) + + // Error + `ABR_ASSERT(CntErrForward_A, + (cnt_q[1] + cnt_q[0]) != {Width{1'b1}} + |-> + err_o) + `ABR_ASSERT(CntErrBackward_A, + err_o + |-> + (cnt_q[1] + cnt_q[0]) != {Width{1'b1}}) + + // This logic that will be assign to one, when user adds macro + // ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT to check the error with alert, in case that abr_prim_count + // is used in design without adding this assertion check. + logic unused_assert_connected; + + `ABR_ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA) +`endif + +endmodule // abr_prim_count diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_diff_decode.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_diff_decode.sv new file mode 100644 index 0000000000000000000000000000000000000000..868f062d8354c5b6bf0361ff5a824bf185452978 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_diff_decode.sv @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module decodes a differentially encoded signal and detects +// incorrectly encoded differential states. +// +// In case the differential pair crosses an asynchronous boundary, it has +// to be re-synchronized to the local clock. This can be achieved by +// setting the AsyncOn parameter to 1'b1. In that case, two additional +// input registers are added (to counteract metastability), and +// a pattern detector is instantiated that detects skewed level changes on +// the differential pair (i.e., when level changes on the diff pair are +// sampled one cycle apart due to a timing skew between the two wires). +// +// See also: abr_prim_alert_sender, abr_prim_alert_receiver, alert_handler + +`include "abr_prim_assert.sv" + +module abr_prim_diff_decode #( + // enables additional synchronization logic + parameter bit AsyncOn = 1'b0 +) ( + input clk_i, + input rst_b, + // input diff pair + input diff_pi, + input diff_ni, + // logical level and + // detected edges + output logic level_o, + output logic rise_o, + output logic fall_o, + // either rise or fall + output logic event_o, + //signal integrity issue detected + output logic sigint_o +); + + logic level_d, level_q; + + /////////////////////////////////////////////////////////////// + // synchronization regs for incoming diff pair (if required) // + /////////////////////////////////////////////////////////////// + if (AsyncOn) begin : gen_async + + typedef enum logic [1:0] {IsStd, IsSkewed, SigInt} state_e; + state_e state_d, state_q; + logic diff_p_edge, diff_n_edge, diff_check_ok, level; + + // 2 sync regs, one reg for edge detection + logic diff_pq, diff_nq, diff_pd, diff_nd; + + abr_prim_flop_2sync #( + .Width(1), + .ResetValue('0) + ) i_sync_p ( + .clk_i, + .rst_b, + .d_i(diff_pi), + .q_o(diff_pd) + ); + + abr_prim_flop_2sync #( + .Width(1), + .ResetValue(1'b1) + ) i_sync_n ( + .clk_i, + .rst_b, + .d_i(diff_ni), + .q_o(diff_nd) + ); + + // detect level transitions + assign diff_p_edge = diff_pq ^ diff_pd; + assign diff_n_edge = diff_nq ^ diff_nd; + + // detect sigint issue + assign diff_check_ok = diff_pd ^ diff_nd; + + // this is the current logical level + assign level = diff_pd; + + // outputs + assign level_o = level_d; + assign event_o = rise_o | fall_o; + + // sigint detection is a bit more involved in async case since + // we might have skew on the diff pair, which can result in a + // one cycle sampling delay between the two wires + // so we need a simple pattern matcher + // the following waves are legal + // clk | | | | | | | | + // _______ _______ + // p _______/ ... \________ + // _______ ________ + // n \_______ ... _______/ + // ____ ___ + // p __________/ ... \________ + // _______ ________ + // n \_______ ... _______/ + // + // i.e., level changes may be off by one cycle - which is permissible + // as long as this condition is only one cycle long. + + + always_comb begin : p_diff_fsm + // default + state_d = state_q; + level_d = level_q; + rise_o = 1'b0; + fall_o = 1'b0; + sigint_o = 1'b0; + + unique case (state_q) + // we remain here as long as + // the diff pair is correctly encoded + IsStd: begin + if (diff_check_ok) begin + level_d = level; + if (diff_p_edge && diff_n_edge) begin + if (level) begin + rise_o = 1'b1; + end else begin + fall_o = 1'b1; + end + end + end else begin + if (diff_p_edge || diff_n_edge) begin + state_d = IsSkewed; + end else begin + state_d = SigInt; + sigint_o = 1'b1; + end + end + end + // diff pair must be correctly encoded, otherwise we got a sigint + IsSkewed: begin + if (diff_check_ok) begin + state_d = IsStd; + level_d = level; + if (level) rise_o = 1'b1; + else fall_o = 1'b1; + end else begin + state_d = SigInt; + sigint_o = 1'b1; + end + end + // Signal integrity issue detected, remain here + // until resolved + SigInt: begin + sigint_o = 1'b1; + if (diff_check_ok) begin + state_d = IsStd; + sigint_o = 1'b0; + end + end + default : ; + endcase + end + + always_ff @(posedge clk_i or negedge rst_b) begin : p_sync_reg + if (!rst_b) begin + state_q <= IsStd; + diff_pq <= 1'b0; + diff_nq <= 1'b1; + level_q <= 1'b0; + end else begin + state_q <= state_d; + diff_pq <= diff_pd; + diff_nq <= diff_nd; + level_q <= level_d; + end + end + + ////////////////////////////////////////////////////////// + // fully synchronous case, no skew present in this case // + ////////////////////////////////////////////////////////// + end else begin : gen_no_async + logic diff_pq, diff_pd; + + // one reg for edge detection + assign diff_pd = diff_pi; + + // incorrect encoding -> signal integrity issue + assign sigint_o = ~(diff_pi ^ diff_ni); + + assign level_o = (sigint_o) ? level_q : diff_pi; + assign level_d = level_o; + + // detect level transitions + assign rise_o = (~diff_pq & diff_pi) & ~sigint_o; + assign fall_o = ( diff_pq & ~diff_pi) & ~sigint_o; + assign event_o = rise_o | fall_o; + + always_ff @(posedge clk_i or negedge rst_b) begin : p_edge_reg + if (!rst_b) begin + diff_pq <= 1'b0; + level_q <= 1'b0; + end else begin + diff_pq <= diff_pd; + level_q <= level_d; + end + end + end + + //////////////// + // assertions // + //////////////// + + // shared assertions + // sigint -> level stays the same during sigint + // $isunknown is needed to avoid false assertion in first clock cycle + `ABR_ASSERT(SigintLevelCheck_A, ##1 sigint_o |-> $stable(level_o)) + // sigint -> no additional events asserted at output + `ABR_ASSERT(SigintEventCheck_A, sigint_o |-> !event_o) + `ABR_ASSERT(SigintRiseCheck_A, sigint_o |-> !rise_o) + `ABR_ASSERT(SigintFallCheck_A, sigint_o |-> !fall_o) + + if (AsyncOn) begin : gen_async_assert + // assertions for asynchronous case +`ifdef ABR_INC_ASSERT + `ifndef FPV_ALERT_NO_SIGINT_ERR + // correctly detect sigint issue (only one transition cycle of permissible due to skew) + `ABR_ASSERT(SigintCheck0_A, gen_async.diff_pd == gen_async.diff_nd [*2] |-> sigint_o) + // the synchronizer adds 2 cycles of latency with respect to input signals. + `ABR_ASSERT(SigintCheck1_A, + ##1 (gen_async.diff_pd ^ gen_async.diff_nd) && + $stable(gen_async.diff_pd) && $stable(gen_async.diff_nd) ##1 + $rose(gen_async.diff_pd) && $stable(gen_async.diff_nd) ##1 + $stable(gen_async.diff_pd) && $fell(gen_async.diff_nd) + |-> rise_o) + `ABR_ASSERT(SigintCheck2_A, + ##1 (gen_async.diff_pd ^ gen_async.diff_nd) && + $stable(gen_async.diff_pd) && $stable(gen_async.diff_nd) ##1 + $fell(gen_async.diff_pd) && $stable(gen_async.diff_nd) ##1 + $stable(gen_async.diff_pd) && $rose(gen_async.diff_nd) + |-> fall_o) + `ABR_ASSERT(SigintCheck3_A, + ##1 (gen_async.diff_pd ^ gen_async.diff_nd) && + $stable(gen_async.diff_pd) && $stable(gen_async.diff_nd) ##1 + $rose(gen_async.diff_nd) && $stable(gen_async.diff_pd) ##1 + $stable(gen_async.diff_nd) && $fell(gen_async.diff_pd) + |-> fall_o) + `ABR_ASSERT(SigintCheck4_A, + ##1 (gen_async.diff_pd ^ gen_async.diff_nd) && + $stable(gen_async.diff_pd) && $stable(gen_async.diff_nd) ##1 + $fell(gen_async.diff_nd) && $stable(gen_async.diff_pd) ##1 + $stable(gen_async.diff_nd) && $rose(gen_async.diff_pd) + |-> rise_o) + `endif + + // correctly detect edges + `ABR_ASSERT(RiseCheck_A, + !sigint_o ##1 $rose(gen_async.diff_pd) && (gen_async.diff_pd ^ gen_async.diff_nd) |-> + ##[0:1] rise_o, clk_i, !rst_b || sigint_o) + `ABR_ASSERT(FallCheck_A, + !sigint_o ##1 $fell(gen_async.diff_pd) && (gen_async.diff_pd ^ gen_async.diff_nd) |-> + ##[0:1] fall_o, clk_i, !rst_b || sigint_o) + `ABR_ASSERT(EventCheck_A, + !sigint_o ##1 $changed(gen_async.diff_pd) && (gen_async.diff_pd ^ gen_async.diff_nd) |-> + ##[0:1] event_o, clk_i, !rst_b || sigint_o) + // correctly detect level + `ABR_ASSERT(LevelCheck0_A, + !sigint_o && (gen_async.diff_pd ^ gen_async.diff_nd) [*2] |-> + gen_async.diff_pd == level_o, + clk_i, !rst_b || sigint_o) +`endif + end else begin : gen_sync_assert + // assertions for synchronous case + + `ifndef FPV_ALERT_NO_SIGINT_ERR + // correctly detect sigint issue + `ABR_ASSERT(SigintCheck_A, diff_pi == diff_ni |-> sigint_o) + `endif + + // correctly detect edges + `ABR_ASSERT(RiseCheck_A, ##1 $rose(diff_pi) && (diff_pi ^ diff_ni) |-> rise_o) + `ABR_ASSERT(FallCheck_A, ##1 $fell(diff_pi) && (diff_pi ^ diff_ni) |-> fall_o) + `ABR_ASSERT(EventCheck_A, ##1 $changed(diff_pi) && (diff_pi ^ diff_ni) |-> event_o) + // correctly detect level + `ABR_ASSERT(LevelCheck_A, (diff_pi ^ diff_ni) |-> diff_pi == level_o) + end + +endmodule : abr_prim_diff_decode diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_dom_and_2share.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_dom_and_2share.sv new file mode 100644 index 0000000000000000000000000000000000000000..e1f6eb93df5f14149f563627ee0099f325d88d73 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_dom_and_2share.sv @@ -0,0 +1,173 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Domain-Oriented Masking GF(2) Multiplier with 2-shares +// ref: Higher-Order Side-Channel Protected Implementations of Keccak +// https://eprint.iacr.org/2017/395.pdf +// +// q0 = a0 & b0 + (a0 & b1 + z) +// q1 = a1 & b1 + (a1 & b0 + z) +// () ==> registered +// +// all input should be stable for two clocks +// as the output is valid after a clock +// For z, it can use other slice from the state +// as it is fairly random w.r.t the current inputs. + +// General formula of Q in the paper +// Qi = t{i,i} + Sig(j>i,d)(t{i,j}+Z{i+j*(j-1)/2}) + Sig(j0,1)(t{0,j}+Z{j(j-1)/2}) + Sig(j<0,d)(..) +// = a0&b0 + (a0&b1 + z0 + 0) +// Q1 = t{1,1} + sig(j>1,1)(...) + sig(j<1,1)(t{1,j} + Z{j}) +// = a1&b1 + (0 + a1&b0 + z0) + +`include "abr_prim_assert.sv" + +module abr_prim_dom_and_2share #( + parameter int DW = 64, // Input width + parameter bit Pipeline = 1'b0 // Enable full pipelining +) ( + input clk_i, + input rst_b, + + input [DW-1:0] a0_i, // share0 of a + input [DW-1:0] a1_i, // share1 of a + input [DW-1:0] b0_i, // share0 of b + input [DW-1:0] b1_i, // share1 of b + input z_valid_i, // random number input validity + input [DW-1:0] z_i, // random number + + output logic [DW-1:0] q0_o, // share0 of q + output logic [DW-1:0] q1_o, // share1 of q + output logic [DW-1:0] prd_o // pseudo-random data for other instances +); + + logic [DW-1:0] t0_d, t0_q, t1_d, t1_q; + logic [DW-1:0] t_a0b0, t_a1b1; + logic [DW-1:0] t_a0b0_d, t_a1b1_d; + logic [DW-1:0] t_a0b1, t_a1b0; + + ///////////////// + // Calculation // + ///////////////// + // Inner-domain terms + assign t_a0b0_d = a0_i & b0_i; + assign t_a1b1_d = a1_i & b1_i; + + // Cross-domain terms + assign t_a0b1 = a0_i & b1_i; + assign t_a1b0 = a1_i & b0_i; + + /////////////// + // Resharing // + /////////////// + // Resharing of cross-domain terms + + // Preserve the logic sequence for XOR not to proceed cross-domain AND. + abr_prim_xor2 #( + .Width ( DW*2 ) + ) u_abr_prim_xor_t01 ( + .in0_i ( {t_a0b1, t_a1b0} ), + .in1_i ( {z_i, z_i} ), + .out_o ( {t0_d, t1_d} ) + ); + + // Register stage + abr_prim_flop_en #( + .Width ( DW*2 ), + .ResetValue ( '0 ) + ) u_abr_prim_flop_t01 ( + .clk_i ( clk_i ), + .rst_b ( rst_b ), + .en_i ( z_valid_i ), + .d_i ( {t0_d, t1_d} ), + .q_o ( {t0_q, t1_q} ) + ); + + ///////////////////////// + // Optional Pipelining // + ///////////////////////// + + if (Pipeline == 1'b1) begin : gen_inner_domain_regs + // Add pipeline registers on inner-domain terms prior to integration. This allows accepting new + // input data every clock cycle and prevents SCA leakage occurring due to the integration of + // reshared cross-domain terms with inner-domain terms derived from different input data. + + logic [DW-1:0] t_a0b0_q, t_a1b1_q; + abr_prim_flop_en #( + .Width ( DW*2 ), + .ResetValue ( '0 ) + ) u_abr_prim_flop_tab01 ( + .clk_i ( clk_i ), + .rst_b ( rst_b ), + .en_i ( z_valid_i ), + .d_i ( {t_a0b0_d, t_a1b1_d} ), + .q_o ( {t_a0b0_q, t_a1b1_q} ) + ); + + assign t_a0b0 = t_a0b0_q; + assign t_a1b1 = t_a1b1_q; + + end else begin : gen_no_inner_domain_regs + // Do not add the optional pipeline registers on the inner-domain terms. This allows to save + // some area in case the multiplier does not need to accept new data in every cycle. However, + // this can cause SCA leakage as during the clock cycle in which new data arrives, the new + // inner-domain terms are integrated with the previous, reshared cross-domain terms. + + assign t_a0b0 = t_a0b0_d; + assign t_a1b1 = t_a1b1_d; + end + + ///////////////// + // Integration // + ///////////////// + + // Preserve the logic sequence for XOR not to proceed the inner-domain AND. + abr_prim_xor2 #( + .Width ( DW*2 ) + ) u_abr_prim_xor_q01 ( + .in0_i ( {t_a0b0, t_a1b1} ), + .in1_i ( {t0_q, t1_q} ), + .out_o ( {q0_o, q1_o} ) + ); + + // Use intermediate results for remasking computations in another instance in the following + // clock cycle. Use one share only. Directly use output of flops updating with z_valid_i. + // t1_q is obtained by remasking t_a1b0 with z_i. Since z_i is uniformly distributed and + // independent of a1/b0_i, t1_q is also uniformly distributed and independent of a1/b0_i. + // For details, see Lemma 1 in Canright, "A very compact 'perfectly masked' S-box for AES + // (corrected)" available at https://eprint.iacr.org/2009/011.pdf + assign prd_o = t1_q; + + // DOM AND should be same as unmasked computation + // The correct test sequence will be: + // 1. inputs are changed + // 2. check if z_valid_i, + // 3. at the next cycle, inputs are still stable (assumption) - only in case Pipeline = 0 + // 4. and results Q == A & B (assertion) + + // To speed up the FPV process, random value is ready in less than or + // equal to two cycles. + `ABR_ASSUME_FPV(RandomReadyInShortTime_A, + $changed(a0_i) || $changed(a1_i) || $changed(b0_i) || $changed(b1_i) + |-> ##[0:2] z_valid_i, + clk_i, !rst_b) + + if (Pipeline == 0) begin: g_assert_stable + // If Pipeline is not set, the computation takes two cycles without flop + // crossing the domain. In this case, the signal should be stable for at + // least two cycles. + `ABR_ASSUME(StableTwoCycles_M, + ($changed(a0_i) || $changed(a1_i) || $changed(b0_i) || $changed(b1_i)) + ##[0:$] z_valid_i |=> + $stable(a0_i) && $stable(a1_i) && $stable(b0_i) && $stable(b1_i)) + end + + `ABR_ASSERT(UnmaskedAndMatched_A, + z_valid_i |=> (q0_o ^ q1_o) == + (($past(a0_i) ^ $past(a1_i)) & ($past(b0_i) ^ $past(b1_i))), + clk_i, !rst_b) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_edge_detector.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_edge_detector.sv new file mode 100644 index 0000000000000000000000000000000000000000..ebed8435694bd7a7855575cee88a19900508ab47 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_edge_detector.sv @@ -0,0 +1,55 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Edge Detector + +module abr_prim_edge_detector #( + parameter int unsigned Width = 1, + + parameter logic [Width-1:0] ResetValue = '0, + + // EnSync + // + // Enable Synchronizer to the input signal. + // It is assumed that the input signal is glitch free (registered input). + parameter bit EnSync = 1'b 1 +) ( + input clk_i, + input rst_b, + + input [Width-1:0] d_i, + output logic [Width-1:0] q_sync_o, + + output logic [Width-1:0] q_posedge_pulse_o, + output logic [Width-1:0] q_negedge_pulse_o +); + + logic [Width-1:0] q_sync_d, q_sync_q; + + if (EnSync) begin : g_sync + abr_prim_flop_2sync #( + .Width (Width), + .ResetValue (ResetValue) + ) u_sync ( + .clk_i, + .rst_b, + .d_i, + .q_o (q_sync_d) + ); + end : g_sync + else begin : g_nosync + assign q_sync_d = d_i; + end : g_nosync + + assign q_sync_o = q_sync_d; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) q_sync_q <= ResetValue; + else q_sync_q <= q_sync_d; + end + + assign q_posedge_pulse_o = q_sync_d & ~q_sync_q; + assign q_negedge_pulse_o = ~q_sync_d & q_sync_q; + +endmodule : abr_prim_edge_detector diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_fifo_sync.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_fifo_sync.sv new file mode 100644 index 0000000000000000000000000000000000000000..7c269ecfc6bd11b228a3846189265cb0ccddcb07 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_fifo_sync.sv @@ -0,0 +1,198 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generic synchronous fifo for use in a variety of devices. + +`include "abr_prim_assert.sv" + +module abr_prim_fifo_sync #( + parameter int unsigned Width = 16, + parameter bit Pass = 1'b1, // if == 1 allow requests to pass through empty FIFO + parameter int unsigned Depth = 4, + parameter bit OutputZeroIfEmpty = 1'b1, // if == 1 always output 0 when FIFO is empty + parameter bit Secure = 1'b0, // use prim count for pointers + // derived parameter + localparam int DepthW = abr_prim_util_pkg::vbits(Depth+1) +) ( + input clk_i, + input rst_b, + // synchronous clear / flush port + input clr_i, + // write port + input wvalid_i, + output wready_o, + input [Width-1:0] wdata_i, + // read port + output rvalid_o, + input rready_i, + output [Width-1:0] rdata_o, + // occupancy + output full_o, + output [DepthW-1:0] depth_o, + output err_o +); + + + // FIFO is in complete passthrough mode + if (Depth == 0) begin : gen_passthru_fifo + `ABR_ASSERT_INIT(paramCheckPass, Pass == 1) + + assign depth_o = 1'b0; //output is meaningless + + // devie facing + assign rvalid_o = wvalid_i; + assign rdata_o = wdata_i; + + // host facing + assign wready_o = rready_i; + assign full_o = rready_i; + + // this avoids lint warnings + logic unused_clr; + assign unused_clr = clr_i; + + // No error + assign err_o = 1'b 0; + + // Normal FIFO construction + end else begin : gen_normal_fifo + + localparam int unsigned PTRV_W = abr_prim_util_pkg::vbits(Depth); + localparam int unsigned PTR_WIDTH = PTRV_W+1; + + logic [PTR_WIDTH-1:0] fifo_wptr, fifo_rptr; + logic fifo_incr_wptr, fifo_incr_rptr, fifo_empty; + + // module under reset flag + logic under_rst; + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + under_rst <= 1'b1; + end else if (under_rst) begin + under_rst <= ~under_rst; + end + end + + // create the write and read pointers + logic full, empty; + logic wptr_msb; + logic rptr_msb; + logic [PTRV_W-1:0] wptr_value; + logic [PTRV_W-1:0] rptr_value; + + assign wptr_msb = fifo_wptr[PTR_WIDTH-1]; + assign rptr_msb = fifo_rptr[PTR_WIDTH-1]; + assign wptr_value = fifo_wptr[0+:PTRV_W]; + assign rptr_value = fifo_rptr[0+:PTRV_W]; + assign depth_o = (full) ? DepthW'(Depth) : + (wptr_msb == rptr_msb) ? DepthW'(wptr_value) - DepthW'(rptr_value) : + (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_value)) ; + + assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; + assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; + + // full and not ready for write are two different concepts. + // The latter can be '0' when under reset, while the former is an indication that no more + // entries can be written. + assign wready_o = ~full & ~under_rst; + assign full_o = full; + assign rvalid_o = ~empty & ~under_rst; + + abr_prim_fifo_sync_cnt #( + .Width(PTR_WIDTH), + .Depth(Depth), + .Secure(Secure) + ) u_fifo_cnt ( + .clk_i, + .rst_b, + .clr_i, + .incr_wptr_i(fifo_incr_wptr), + .incr_rptr_i(fifo_incr_rptr), + .wptr_o(fifo_wptr), + .rptr_o(fifo_rptr), + .err_o + ); + + //always_ff @(posedge clk_i or negedge rst_b) begin + // if (!rst_b) begin + // fifo_wptr <= {(PTR_WIDTH){1'b0}}; + // end else if (clr_i) begin + // fifo_wptr <= {(PTR_WIDTH){1'b0}}; + // end else if (fifo_incr_wptr) begin + // if (fifo_wptr[PTR_WIDTH-2:0] == (PTR_WIDTH-1)'(Depth-1)) begin + // fifo_wptr <= {~fifo_wptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}}; + // end else begin + // fifo_wptr <= fifo_wptr + {{(PTR_WIDTH-1){1'b0}},1'b1}; + // end + // end + //end + // + //always_ff @(posedge clk_i or negedge rst_b) begin + // if (!rst_b) begin + // fifo_rptr <= {(PTR_WIDTH){1'b0}}; + // end else if (clr_i) begin + // fifo_rptr <= {(PTR_WIDTH){1'b0}}; + // end else if (fifo_incr_rptr) begin + // if (fifo_rptr[PTR_WIDTH-2:0] == (PTR_WIDTH-1)'(Depth-1)) begin + // fifo_rptr <= {~fifo_rptr[PTR_WIDTH-1],{(PTR_WIDTH-1){1'b0}}}; + // end else begin + // fifo_rptr <= fifo_rptr + {{(PTR_WIDTH-1){1'b0}},1'b1}; + // end + // end + //end + + assign full = (fifo_wptr == (fifo_rptr ^ {1'b1,{(PTR_WIDTH-1){1'b0}}})); + assign fifo_empty = (fifo_wptr == fifo_rptr); + + + // the generate blocks below are needed to avoid lint errors due to array indexing + // in the where the fifo only has one storage element + logic [Depth-1:0][Width-1:0] storage; + logic [Width-1:0] storage_rdata; + if (Depth == 1) begin : gen_depth_eq1 + assign storage_rdata = storage[0]; + + always_ff @(posedge clk_i) + if (fifo_incr_wptr) begin + storage[0] <= wdata_i; + end + // fifo with more than one storage element + end else begin : gen_depth_gt1 + assign storage_rdata = storage[fifo_rptr[PTR_WIDTH-2:0]]; + + always_ff @(posedge clk_i) + if (fifo_incr_wptr) begin + storage[fifo_wptr[PTR_WIDTH-2:0]] <= wdata_i; + end + end + + logic [Width-1:0] rdata_int; + if (Pass == 1'b1) begin : gen_pass + assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; + assign empty = fifo_empty & ~wvalid_i; + end else begin : gen_nopass + assign rdata_int = storage_rdata; + assign empty = fifo_empty; + end + + if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero + assign rdata_o = empty ? 'b0 : rdata_int; + end else begin : gen_no_output_zero + assign rdata_o = rdata_int; + end + + `ABR_ASSERT(depthShallNotExceedParamDepth, !empty |-> depth_o <= DepthW'(Depth)) + end // block: gen_normal_fifo + + + ////////////////////// + // Known Assertions // + ////////////////////// + + `ABR_ASSERT(DataKnown_A, rvalid_o |-> !$isunknown(rdata_o)) + `ABR_ASSERT_KNOWN(DepthKnown_A, depth_o) + `ABR_ASSERT_KNOWN(RvalidKnown_A, rvalid_o) + `ABR_ASSERT_KNOWN(WreadyKnown_A, wready_o) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv new file mode 100644 index 0000000000000000000000000000000000000000..6649f2406a7e2b4d43cfca787a3ab578f8306a15 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv @@ -0,0 +1,102 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generic synchronous fifo for use in a variety of devices. + +`include "abr_prim_assert.sv" + +module abr_prim_fifo_sync_cnt #( + parameter int Depth = 4, + parameter int Width = 16, + parameter bit Secure = 1'b0 +) ( + input clk_i, + input rst_b, + input clr_i, + input incr_wptr_i, + input incr_rptr_i, + output logic [Width-1:0] wptr_o, + output logic [Width-1:0] rptr_o, + output logic err_o +); + + logic wptr_wrap; + logic [Width-1:0] wptr_wrap_cnt; + logic rptr_wrap; + logic [Width-1:0] rptr_wrap_cnt; + + assign wptr_wrap = incr_wptr_i & (wptr_o[Width-2:0] == unsigned'((Width-1)'(Depth-1))); + assign rptr_wrap = incr_rptr_i & (rptr_o[Width-2:0] == unsigned'((Width-1)'(Depth-1))); + + assign wptr_wrap_cnt = {~wptr_o[Width-1],{(Width-1){1'b0}}}; + assign rptr_wrap_cnt = {~rptr_o[Width-1],{(Width-1){1'b0}}}; + + if (Secure) begin : gen_secure_ptrs + logic wptr_err; + abr_prim_count #( + .Width(Width) + ) u_wptr ( + .clk_i, + .rst_b, + .clr_i, + .set_i(wptr_wrap), + .set_cnt_i(wptr_wrap_cnt), + .incr_en_i(incr_wptr_i), + .decr_en_i(1'b0), + .step_i(Width'(1'b1)), + .cnt_o(wptr_o), + .cnt_next_o(), + .err_o(wptr_err) + ); + + logic rptr_err; + abr_prim_count #( + .Width(Width) + ) u_rptr ( + .clk_i, + .rst_b, + .clr_i, + .set_i(rptr_wrap), + .set_cnt_i(rptr_wrap_cnt), + .incr_en_i(incr_rptr_i), + .decr_en_i(1'b0), + .step_i(Width'(1'b1)), + .cnt_o(rptr_o), + .cnt_next_o(), + .err_o(rptr_err) + ); + + assign err_o = wptr_err | rptr_err; + + end else begin : gen_normal_ptrs + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + wptr_o <= {(Width){1'b0}}; + end else if (clr_i) begin + wptr_o <= {(Width){1'b0}}; + end else if (wptr_wrap) begin + wptr_o <= wptr_wrap_cnt; + end else if (incr_wptr_i) begin + wptr_o <= wptr_o + {{(Width-1){1'b0}},1'b1}; + end + end + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + rptr_o <= {(Width){1'b0}}; + end else if (clr_i) begin + rptr_o <= {(Width){1'b0}}; + end else if (rptr_wrap) begin + rptr_o <= rptr_wrap_cnt; + end else if (incr_rptr_i) begin + rptr_o <= rptr_o + {{(Width-1){1'b0}},1'b1}; + end + end + + assign err_o = '0; + end + + + +endmodule // abr_prim_fifo_sync_cnt diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop.sv new file mode 100644 index 0000000000000000000000000000000000000000..e88cc3d513581834d7482494fdcc0df9b231a76f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop.sv @@ -0,0 +1,49 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is auto-generated. +// Used parser: Fallback (regex) + +`ifndef ABR_PRIM_DEFAULT_IMPL + `define ABR_PRIM_DEFAULT_IMPL abr_prim_pkg::ImplGeneric +`endif + +// This is to prevent AscentLint warnings in the generated +// abstract prim wrapper. These warnings occur due to the .* +// use. TODO: we may want to move these inline waivers +// into a separate, generated waiver file for consistency. +//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ +module abr_prim_flop + +#( + + parameter int Width = 1, + parameter logic [Width-1:0] ResetValue = 0 + +) ( + input clk_i, + input rst_b, + input [Width-1:0] d_i, + output logic [Width-1:0] q_o +); + parameter abr_prim_pkg::impl_e Impl = `ABR_PRIM_DEFAULT_IMPL; + +if (Impl == abr_prim_pkg::ImplXilinx) begin : gen_xilinx + abr_prim_xilinx_flop #( + .ResetValue(ResetValue), + .Width(Width) + ) u_impl_xilinx ( + .* + ); +end else begin : gen_generic + abr_prim_generic_flop #( + .ResetValue(ResetValue), + .Width(Width) + ) u_impl_generic ( + .* + ); +end + +endmodule +//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_2sync.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_2sync.sv new file mode 100644 index 0000000000000000000000000000000000000000..301968fbf2d060e23e6b5be33d818a16dbef472b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_2sync.sv @@ -0,0 +1,61 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Generic double-synchronizer flop +// This may need to be moved to abr_prim_generic if libraries have a specific cell +// for synchronization + +module abr_prim_flop_2sync #( + parameter int Width = 16, + parameter logic [Width-1:0] ResetValue = '0, + parameter bit EnablePrimCdcRand = 1 +) ( + input clk_i, + input rst_b, + input [Width-1:0] d_i, + output logic [Width-1:0] q_o +); + + logic [Width-1:0] d_o; + logic [Width-1:0] intq; + +`ifdef ABR_SIMULATION + + abr_prim_cdc_rand_delay #( + .DataWidth(Width), + .Enable(EnablePrimCdcRand) + ) u_abr_prim_cdc_rand_delay ( + .clk_i, + .rst_b, + .src_data_i(d_i), + .prev_data_i(intq), + .dst_data_o(d_o) + ); +`else // !`ifdef ABR_SIMULATION + logic unused_sig; + assign unused_sig = EnablePrimCdcRand; + always_comb d_o = d_i; +`endif // !`ifdef ABR_SIMULATION + + abr_prim_flop #( + .Width(Width), + .ResetValue(ResetValue) + ) u_sync_1 ( + .clk_i, + .rst_b, + .d_i(d_o), + .q_o(intq) + ); + + abr_prim_flop #( + .Width(Width), + .ResetValue(ResetValue) + ) u_sync_2 ( + .clk_i, + .rst_b, + .d_i(intq), + .q_o + ); + +endmodule : abr_prim_flop_2sync diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_en.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_en.sv new file mode 100644 index 0000000000000000000000000000000000000000..655ab0f7ee166469e879d922039c522892e52751 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_en.sv @@ -0,0 +1,53 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file is auto-generated. +// Used parser: Fallback (regex) + +`ifndef ABR_PRIM_DEFAULT_IMPL + `define ABR_PRIM_DEFAULT_IMPL abr_prim_pkg::ImplGeneric +`endif + +// This is to prevent AscentLint warnings in the generated +// abstract prim wrapper. These warnings occur due to the .* +// use. TODO: we may want to move these inline waivers +// into a separate, generated waiver file for consistency. +//ri lint_check_off OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ +module abr_prim_flop_en + +#( + + parameter int Width = 1, + parameter bit EnSecBuf = 0, + parameter logic [Width-1:0] ResetValue = 0 + +) ( + input clk_i, + input rst_b, + input en_i, + input [Width-1:0] d_i, + output logic [Width-1:0] q_o +); + parameter abr_prim_pkg::impl_e Impl = `ABR_PRIM_DEFAULT_IMPL; + +if (Impl == abr_prim_pkg::ImplXilinx) begin : gen_xilinx + abr_prim_xilinx_flop_en #( + .EnSecBuf(EnSecBuf), + .ResetValue(ResetValue), + .Width(Width) + ) u_impl_xilinx ( + .* + ); +end else begin : gen_generic + abr_prim_generic_flop_en #( + .EnSecBuf(EnSecBuf), + .ResetValue(ResetValue), + .Width(Width) + ) u_impl_generic ( + .* + ); +end + +endmodule +//ri lint_check_on OUTPUT_NOT_DRIVEN INPUT_NOT_READ HIER_BRANCH_NOT_READ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_macros.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_macros.sv new file mode 100644 index 0000000000000000000000000000000000000000..81392b445a91cb01143124b11c4802a1b342e1d9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_flop_macros.sv @@ -0,0 +1,74 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`ifndef ABR_PRIM_FLOP_MACROS_SV +`define ABR_PRIM_FLOP_MACROS_SV + +///////////////////////////////////// +// Default Values for Macros below // +///////////////////////////////////// + +`define ABR_PRIM_FLOP_CLK clk_i +`define ABR_PRIM_FLOP_RST rst_b +`define ABR_PRIM_FLOP_RESVAL '0 + +///////////////////// +// Register Macros // +///////////////////// + +// TODO: define other variations of register macros so that they can be used throughout all designs +// to make the code more concise. + +// Register with asynchronous reset. +`define ABR_PRIM_FLOP_A(__d, __q, __resval = `ABR_PRIM_FLOP_RESVAL, __clk = `ABR_PRIM_FLOP_CLK, __rst_n = `ABR_PRIM_FLOP_RST) \ + always_ff @(posedge __clk or negedge __rst_n) begin \ + if (!__rst_n) begin \ + __q <= __resval; \ + end else begin \ + __q <= __d; \ + end \ + end + +/////////////////////////// +// Macro for Sparse FSMs // +/////////////////////////// + +// Simulation tools typically infer FSMs and report coverage for these separately. However, tools +// like Xcelium and VCS seem to have problems inferring FSMs if the state register is not coded in +// a behavioral always_ff block in the same hierarchy. To that end, this uses a modified variant +// with a second behavioral register definition for RTL simulations so that FSMs can be inferred. +// Note that in this variant, the __q output is disconnected from abr_prim_sparse_fsm_flop and attached +// to the behavioral flop. An assertion is added to ensure equivalence between the +// abr_prim_sparse_fsm_flop output and the behavioral flop output in that case. +`define ABR_PRIM_FLOP_SPARSE_FSM(__name, __d, __q, __type, __resval = `ABR_PRIM_FLOP_RESVAL, __clk = `ABR_PRIM_FLOP_CLK, __rst_n = `ABR_PRIM_FLOP_RST, __alert_trigger_sva_en = 1) \ + `ifdef ABR_SIMULATION \ + abr_prim_sparse_fsm_flop #( \ + .StateEnumT(__type), \ + .Width($bits(__type)), \ + .ResetValue($bits(__type)'(__resval)), \ + .EnableAlertTriggerSVA(__alert_trigger_sva_en), \ + .CustomForceName(`ABR_PRIM_STRINGIFY(__q)) \ + ) __name ( \ + .clk_i ( __clk ), \ + .rst_b ( __rst_n ), \ + .state_i ( __d ), \ + .state_o ( ) \ + ); \ + `ABR_PRIM_FLOP_A(__d, __q, __resval, __clk, __rst_n) \ + `ABR_ASSERT(``__name``_A, __q === ``__name``.state_o) \ + `else \ + abr_prim_sparse_fsm_flop #( \ + .StateEnumT(__type), \ + .Width($bits(__type)), \ + .ResetValue($bits(__type)'(__resval)), \ + .EnableAlertTriggerSVA(__alert_trigger_sva_en) \ + ) __name ( \ + .clk_i ( __clk ), \ + .rst_b ( __rst_n ), \ + .state_i ( __d ), \ + .state_o ( __q ) \ + ); \ + `endif + +`endif // PRIM_FLOP_MACROS_SV diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_intr_hw.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_intr_hw.sv new file mode 100644 index 0000000000000000000000000000000000000000..b363fe24a42c7da28e749cf52de15e61545a5480 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_intr_hw.sv @@ -0,0 +1,100 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Primitive interrupt handler. This assumes the existence of three +// controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST. +// This module can be instantiated once per interrupt field, or +// "bussified" with all fields of the interrupt vector. + +`include "abr_sva.svh" +`include "abr_prim_assert.sv" + +module abr_prim_intr_hw # ( + parameter int unsigned Width = 1, + parameter bit FlopOutput = 1, + + // IntrT parameter is to hint the logic for the interrupt type. Module + // supports two interrupt types, *Status* and *Event*. + // + // The differences between those two types are: + // - Status is persistent. Until the root cause is alleviated, the interrupt + // keeps asserting. + // - Event remains high for a relatively short period time without SW + // intervention. One distinct example is an error (error could be status + // though). If a certain error condition is captured, HW logic may create a + // pulse. In this case the interrupt is assumed as an Event interrupt. + parameter IntrT = "Event" // Event or Status +) ( + // event + input clk_i, + input rst_b, + input [Width-1:0] event_intr_i, + + // register interface + input [Width-1:0] reg2hw_intr_enable_q_i, + input [Width-1:0] reg2hw_intr_test_q_i, + input reg2hw_intr_test_qe_i, + input [Width-1:0] reg2hw_intr_state_q_i, + output hw2reg_intr_state_de_o, + output [Width-1:0] hw2reg_intr_state_d_o, + + // outgoing interrupt + output logic [Width-1:0] intr_o +); + + logic [Width-1:0] status; // incl. test + + if (IntrT == "Event") begin : g_intr_event + logic [Width-1:0] new_event; + assign new_event = + (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); + assign hw2reg_intr_state_de_o = |new_event; + // for scalar interrupts, this resolves to '1' with new event + // for vector interrupts, new events are OR'd in to existing interrupt state + assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; + + assign status = reg2hw_intr_state_q_i ; + end : g_intr_event + else if (IntrT == "Status") begin : g_intr_status + logic [Width-1:0] test_q; // Storing test. Cleared by SW + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) test_q <= '0; + else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; + end + + // TODO: In Status type, INTR_STATE is better to be external type and RO. + assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status + assign hw2reg_intr_state_d_o = event_intr_i | test_q; + + assign status = event_intr_i | test_q; + + // To make the timing same to event type, status signal does not use CSR.q, + // rather the input of the CSR. + logic unused_reg2hw; + assign unused_reg2hw = ^reg2hw_intr_state_q_i; + end : g_intr_status + + + if (FlopOutput == 1) begin : gen_flop_intr_output + // flop the interrupt output + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + intr_o <= '0; + end else begin + intr_o <= status & reg2hw_intr_enable_q_i; + end + end + + end else begin : gen_intr_passthrough_output + logic unused_clk; + logic unused_rst_n; + assign unused_clk = clk_i; + assign unused_rst_n = rst_b; + assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i; + end + + `ABR_ASSERT_INIT(IntrTKind_A, IntrT inside {"Event", "Status"}) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_lc_sync.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_lc_sync.sv new file mode 100644 index 0000000000000000000000000000000000000000..0d9ab229e0fb2ec13c744edd26f9018265e82998 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_lc_sync.sv @@ -0,0 +1,121 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Double-synchronizer flop for life cycle control signals with additional +// output buffers and life-cycle specific assertions. +// +// Should be used exactly as recommended in the life cycle controller spec: +// https://docs.opentitan.org/hw/ip/lc_ctrl/doc/index.html#control-signal-propagation + +`include "abr_prim_assert.sv" + +module abr_prim_lc_sync + import lc_ctrl_state_pkg::*; + import lc_ctrl_reg_pkg::*; + import lc_ctrl_pkg::*; +#( + // Number of separately buffered output signals. + // The buffer cells have a don't touch constraint + // on them such that synthesis tools won't collapse + // all copies into one signal. + parameter int NumCopies = 1, + // This instantiates the synchronizer flops if set to 1. + // In special cases where the receiver is in the same clock domain as the sender, + // this can be set to 0. However, it is recommended to leave this at 1. + parameter bit AsyncOn = 1, + // 0: reset value is lc_ctrl_pkg::Off + // 1: reset value is lc_ctrl_pkg::On + parameter bit ResetValueIsOn = 0 +) ( + input clk_i, + input rst_b, + input lc_ctrl_pkg::lc_tx_t lc_en_i, + output lc_ctrl_pkg::lc_tx_t [NumCopies-1:0] lc_en_o +); + + localparam lc_ctrl_pkg::lc_tx_t LcResetValue = (ResetValueIsOn) ? lc_ctrl_pkg::On : + lc_ctrl_pkg::Off; + + `ABR_ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0) + + logic [lc_ctrl_pkg::TxWidth-1:0] lc_en; + if (AsyncOn) begin : gen_flops + abr_prim_flop_2sync #( + .Width(lc_ctrl_pkg::TxWidth), + .ResetValue(lc_ctrl_pkg::TxWidth'(LcResetValue)) + ) u_abr_prim_flop_2sync ( + .clk_i, + .rst_b, + .d_i(lc_en_i), + .q_o(lc_en) + ); + +// Note regarding SVA below: +// +// 1) Without the sampled rst_b pre-condition, this may cause false assertion failures right after +// a reset release, since the "disable iff" condition with the rst_b is sampled in the "observed" +// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page +// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_b +// on the active clock edge. This causes the assertion to evaluate although the reset was actually +// 0 when entering this simulation cycle. +// +// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may +// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly +// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock +// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make +// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no +// sampling mismatches. +`ifdef ABR_INC_ASSERT + lc_ctrl_pkg::lc_tx_t lc_en_in_sva_q; + always_ff @(posedge clk_i) begin + lc_en_in_sva_q <= lc_en_i; + end + `ABR_ASSERT(OutputDelay_A, + rst_b |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} || + ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)) || + !rst_b) +`endif + end else begin : gen_no_flops + //VCS coverage off + // pragma coverage off + + // This unused companion logic helps remove lint errors + // for modules where clock and reset are used for assertions only + // or nothing at all. + // This logic will be removed for sythesis since it is unloaded. + lc_ctrl_pkg::lc_tx_t unused_logic; + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + unused_logic <= lc_ctrl_pkg::Off; + end else begin + unused_logic <= lc_en_i; + end + end + //VCS coverage on + // pragma coverage on + + assign lc_en = lc_en_i; + + `ABR_ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}}) + end + + for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs + logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out; + for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits + abr_prim_sec_anchor_buf u_abr_prim_buf ( + .in_i(lc_en[k]), + .out_o(lc_en_out[k]) + ); + end + assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out); + end + + //////////////// + // Assertions // + //////////////// + + // The outputs should be known at all times. + `ABR_ASSERT_KNOWN(OutputsKnown_A, lc_en_o) + +endmodule : abr_prim_lc_sync diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_lfsr.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_lfsr.sv new file mode 100644 index 0000000000000000000000000000000000000000..f5c92c28ffacadf7f2ac1bfbab34d86c099844fc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_lfsr.sv @@ -0,0 +1,699 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module implements different LFSR types: +// +// 0) Galois XOR type LFSR ([1], internal XOR gates, very fast). +// Parameterizable width from 4 to 64 bits. +// Coefficients obtained from [2]. +// +// 1) Fibonacci XNOR type LFSR, parameterizable from 3 to 168 bits. +// Coefficients obtained from [3]. +// +// All flavors have an additional entropy input and lockup protection, which +// reseeds the state once it has accidentally fallen into the all-zero (XOR) or +// all-one (XNOR) state. Further, an external seed can be loaded into the LFSR +// state at runtime. If that seed is all-zero (XOR case) or all-one (XNOR case), +// the state will be reseeded in the next cycle using the lockup protection mechanism. +// Note that the external seed input takes precedence over internal state updates. +// +// All polynomials up to 34 bit in length have been verified in simulation. +// +// Refs: [1] https://en.wikipedia.org/wiki/Linear-feedback_shift_register +// [2] https://users.ece.cmu.edu/~koopman/lfsr/ +// [3] https://www.xilinx.com/support/documentation/application_notes/xapp052.pdf + +`include "abr_prim_assert.sv" + +module abr_prim_lfsr #( + // Lfsr Type, can be FIB_XNOR or GAL_XOR + parameter LfsrType = "GAL_XOR", + // Lfsr width + parameter int unsigned LfsrDw = 32, + // Derived parameter, do not override + localparam int unsigned LfsrIdxDw = $clog2(LfsrDw), + // Width of the entropy input to be XOR'd into state (lfsr_q[EntropyDw-1:0]) + parameter int unsigned EntropyDw = 8, + // Width of output tap (from lfsr_q[StateOutDw-1:0]) + parameter int unsigned StateOutDw = 8, + // Lfsr reset state, must be nonzero! + parameter logic [LfsrDw-1:0] DefaultSeed = LfsrDw'(1), + // Custom polynomial coeffs + parameter logic [LfsrDw-1:0] CustomCoeffs = '0, + // If StatePermEn is set to 1, the custom permutation specified via StatePerm is applied to the + // state output, in order to break linear shifting patterns of the LFSR. Note that this + // permutation represents a way of customizing the LFSR via a random netlist constant. This is + // different from the NonLinearOut feature below which just transforms the output non-linearly + // with a fixed function. In most cases, designers should consider enabling StatePermEn as it + // comes basically "for free" in terms of area and timing impact. NonLinearOut on the other hand + // has area and timing implications and designers should consider whether the use of that feature + // is justified. + parameter bit StatePermEn = 1'b0, + parameter logic [LfsrDw-1:0][LfsrIdxDw-1:0] StatePerm = '0, + // Enable this for DV, disable this for long LFSRs in FPV + parameter bit MaxLenSVA = 1'b1, + // Can be disabled in cases where seed and entropy + // inputs are unused in order to not distort coverage + // (the SVA will be unreachable in such cases) + parameter bit LockupSVA = 1'b1, + parameter bit ExtSeedSVA = 1'b1, + // Introduce non-linearity to lfsr output. Note, unlike StatePermEn, this feature is not "for + // free". Please double check that this feature is indeed required. Also note that this feature + // is only available for LFSRs that have a power-of-two width greater or equal 16bit. + parameter bit NonLinearOut = 1'b0 +) ( + input clk_i, + input rst_b, + input seed_en_i, // load external seed into the state (takes precedence) + input [LfsrDw-1:0] seed_i, // external seed input + input lfsr_en_i, // enables the LFSR + input [EntropyDw-1:0] entropy_i, // additional entropy to be XOR'ed into the state + output logic [StateOutDw-1:0] state_o // (partial) LFSR state output +); + + // automatically generated with util/design/get-lfsr-coeffs.py script + localparam int unsigned GAL_XOR_LUT_OFF = 4; + localparam logic [63:0] GAL_XOR_COEFFS [61] = + '{ 64'h9, + 64'h12, + 64'h21, + 64'h41, + 64'h8E, + 64'h108, + 64'h204, + 64'h402, + 64'h829, + 64'h100D, + 64'h2015, + 64'h4001, + 64'h8016, + 64'h10004, + 64'h20013, + 64'h40013, + 64'h80004, + 64'h100002, + 64'h200001, + 64'h400010, + 64'h80000D, + 64'h1000004, + 64'h2000023, + 64'h4000013, + 64'h8000004, + 64'h10000002, + 64'h20000029, + 64'h40000004, + 64'h80000057, + 64'h100000029, + 64'h200000073, + 64'h400000002, + 64'h80000003B, + 64'h100000001F, + 64'h2000000031, + 64'h4000000008, + 64'h800000001C, + 64'h10000000004, + 64'h2000000001F, + 64'h4000000002C, + 64'h80000000032, + 64'h10000000000D, + 64'h200000000097, + 64'h400000000010, + 64'h80000000005B, + 64'h1000000000038, + 64'h200000000000E, + 64'h4000000000025, + 64'h8000000000004, + 64'h10000000000023, + 64'h2000000000003E, + 64'h40000000000023, + 64'h8000000000004A, + 64'h100000000000016, + 64'h200000000000031, + 64'h40000000000003D, + 64'h800000000000001, + 64'h1000000000000013, + 64'h2000000000000034, + 64'h4000000000000001, + 64'h800000000000000D }; + + // automatically generated with get-lfsr-coeffs.py script + localparam int unsigned FIB_XNOR_LUT_OFF = 3; + localparam logic [167:0] FIB_XNOR_COEFFS [166] = + '{ 168'h6, + 168'hC, + 168'h14, + 168'h30, + 168'h60, + 168'hB8, + 168'h110, + 168'h240, + 168'h500, + 168'h829, + 168'h100D, + 168'h2015, + 168'h6000, + 168'hD008, + 168'h12000, + 168'h20400, + 168'h40023, + 168'h90000, + 168'h140000, + 168'h300000, + 168'h420000, + 168'hE10000, + 168'h1200000, + 168'h2000023, + 168'h4000013, + 168'h9000000, + 168'h14000000, + 168'h20000029, + 168'h48000000, + 168'h80200003, + 168'h100080000, + 168'h204000003, + 168'h500000000, + 168'h801000000, + 168'h100000001F, + 168'h2000000031, + 168'h4400000000, + 168'hA000140000, + 168'h12000000000, + 168'h300000C0000, + 168'h63000000000, + 168'hC0000030000, + 168'h1B0000000000, + 168'h300003000000, + 168'h420000000000, + 168'hC00000180000, + 168'h1008000000000, + 168'h3000000C00000, + 168'h6000C00000000, + 168'h9000000000000, + 168'h18003000000000, + 168'h30000000030000, + 168'h40000040000000, + 168'hC0000600000000, + 168'h102000000000000, + 168'h200004000000000, + 168'h600003000000000, + 168'hC00000000000000, + 168'h1800300000000000, + 168'h3000000000000030, + 168'h6000000000000000, + 168'hD800000000000000, + 168'h10000400000000000, + 168'h30180000000000000, + 168'h60300000000000000, + 168'h80400000000000000, + 168'h140000028000000000, + 168'h300060000000000000, + 168'h410000000000000000, + 168'h820000000001040000, + 168'h1000000800000000000, + 168'h3000600000000000000, + 168'h6018000000000000000, + 168'hC000000018000000000, + 168'h18000000600000000000, + 168'h30000600000000000000, + 168'h40200000000000000000, + 168'hC0000000060000000000, + 168'h110000000000000000000, + 168'h240000000480000000000, + 168'h600000000003000000000, + 168'h800400000000000000000, + 168'h1800000300000000000000, + 168'h3003000000000000000000, + 168'h4002000000000000000000, + 168'hC000000000000000018000, + 168'h10000000004000000000000, + 168'h30000C00000000000000000, + 168'h600000000000000000000C0, + 168'hC00C0000000000000000000, + 168'h140000000000000000000000, + 168'h200001000000000000000000, + 168'h400800000000000000000000, + 168'hA00000000001400000000000, + 168'h1040000000000000000000000, + 168'h2004000000000000000000000, + 168'h5000000000028000000000000, + 168'h8000000004000000000000000, + 168'h18600000000000000000000000, + 168'h30000000000000000C00000000, + 168'h40200000000000000000000000, + 168'hC0300000000000000000000000, + 168'h100010000000000000000000000, + 168'h200040000000000000000000000, + 168'h5000000000000000A0000000000, + 168'h800000010000000000000000000, + 168'h1860000000000000000000000000, + 168'h3003000000000000000000000000, + 168'h4010000000000000000000000000, + 168'hA000000000140000000000000000, + 168'h10080000000000000000000000000, + 168'h30000000000000000000180000000, + 168'h60018000000000000000000000000, + 168'hC0000000000000000300000000000, + 168'h140005000000000000000000000000, + 168'h200000001000000000000000000000, + 168'h404000000000000000000000000000, + 168'h810000000000000000000000000102, + 168'h1000040000000000000000000000000, + 168'h3000000000000006000000000000000, + 168'h5000000000000000000000000000000, + 168'h8000000004000000000000000000000, + 168'h18000000000000000000000000030000, + 168'h30000000030000000000000000000000, + 168'h60000000000000000000000000000000, + 168'hA0000014000000000000000000000000, + 168'h108000000000000000000000000000000, + 168'h240000000000000000000000000000000, + 168'h600000000000C00000000000000000000, + 168'h800000040000000000000000000000000, + 168'h1800000000000300000000000000000000, + 168'h2000000000000010000000000000000000, + 168'h4008000000000000000000000000000000, + 168'hC000000000000000000000000000000600, + 168'h10000080000000000000000000000000000, + 168'h30600000000000000000000000000000000, + 168'h4A400000000000000000000000000000000, + 168'h80000004000000000000000000000000000, + 168'h180000003000000000000000000000000000, + 168'h200001000000000000000000000000000000, + 168'h600006000000000000000000000000000000, + 168'hC00000000000000006000000000000000000, + 168'h1000000000000100000000000000000000000, + 168'h3000000000000006000000000000000000000, + 168'h6000000003000000000000000000000000000, + 168'h8000001000000000000000000000000000000, + 168'h1800000000000000000000000000C000000000, + 168'h20000000000001000000000000000000000000, + 168'h48000000000000000000000000000000000000, + 168'hC0000000000000006000000000000000000000, + 168'h180000000000000000000000000000000000000, + 168'h280000000000000000000000000000005000000, + 168'h60000000C000000000000000000000000000000, + 168'hC00000000000000000000000000018000000000, + 168'h1800000600000000000000000000000000000000, + 168'h3000000C00000000000000000000000000000000, + 168'h4000000080000000000000000000000000000000, + 168'hC000300000000000000000000000000000000000, + 168'h10000400000000000000000000000000000000000, + 168'h30000000000000000000006000000000000000000, + 168'h600000000000000C0000000000000000000000000, + 168'hC0060000000000000000000000000000000000000, + 168'h180000006000000000000000000000000000000000, + 168'h3000000000C0000000000000000000000000000000, + 168'h410000000000000000000000000000000000000000, + 168'hA00140000000000000000000000000000000000000 }; + + logic lockup; + logic [LfsrDw-1:0] lfsr_d, lfsr_q; + logic [LfsrDw-1:0] next_lfsr_state, coeffs; + + // Enable the randomization of DefaultSeed using DefaultSeedLocal in DV simulations. + `ifdef ABR_SIMULATION + `ifdef VERILATOR + localparam logic [LfsrDw-1:0] DefaultSeedLocal = DefaultSeed; + + `else + logic [LfsrDw-1:0] DefaultSeedLocal; + logic abr_prim_lfsr_use_default_seed; + + initial begin : p_randomize_default_seed + if (!$value$plusargs("abr_prim_lfsr_use_default_seed=%0d", abr_prim_lfsr_use_default_seed)) begin + // 30% of the time, use the DefaultSeed parameter; 70% of the time, randomize it. + `ABR_ASSERT_I(UseDefaultSeedRandomizeCheck_A, std::randomize(abr_prim_lfsr_use_default_seed) with { + abr_prim_lfsr_use_default_seed dist {0:/7, 1:/3};}) + end + if (abr_prim_lfsr_use_default_seed) begin + DefaultSeedLocal = DefaultSeed; + end else begin + // Randomize the DefaultSeedLocal ensuring its not all 0s or all 1s. + `ABR_ASSERT_I(DefaultSeedLocalRandomizeCheck_A, std::randomize(DefaultSeedLocal) with { + !(DefaultSeedLocal inside {'0, '1});}) + end + $display("%m: DefaultSeed = 0x%0h, DefaultSeedLocal = 0x%0h", DefaultSeed, DefaultSeedLocal); + end + `endif // ifdef VERILATOR + + `else + localparam logic [LfsrDw-1:0] DefaultSeedLocal = DefaultSeed; + + `endif // ifdef ABR_SIMULATION + + //////////////// + // Galois XOR // + //////////////// + if (64'(LfsrType) == 64'("GAL_XOR")) begin : gen_gal_xor + + // if custom polynomial is provided + if (CustomCoeffs > 0) begin : gen_custom + assign coeffs = CustomCoeffs[LfsrDw-1:0]; + end else begin : gen_lut + assign coeffs = GAL_XOR_COEFFS[LfsrDw-GAL_XOR_LUT_OFF][LfsrDw-1:0]; + // check that the most significant bit of polynomial is 1 + `ABR_ASSERT_INIT(MinLfsrWidth_A, LfsrDw >= $low(GAL_XOR_COEFFS)+GAL_XOR_LUT_OFF) + `ABR_ASSERT_INIT(MaxLfsrWidth_A, LfsrDw <= $high(GAL_XOR_COEFFS)+GAL_XOR_LUT_OFF) + end + + // calculate next state using internal XOR feedback and entropy input + assign next_lfsr_state = LfsrDw'(entropy_i) ^ ({LfsrDw{lfsr_q[0]}} & coeffs) ^ (lfsr_q >> 1); + + // lockup condition is all-zero + assign lockup = ~(|lfsr_q); + + // check that seed is not all-zero + `ABR_ASSERT_INIT(DefaultSeedNzCheck_A, |DefaultSeedLocal) + + + //////////////////// + // Fibonacci XNOR // + //////////////////// + end else if (64'(LfsrType) == "FIB_XNOR") begin : gen_fib_xnor + + // if custom polynomial is provided + if (CustomCoeffs > 0) begin : gen_custom + assign coeffs = CustomCoeffs[LfsrDw-1:0]; + end else begin : gen_lut + assign coeffs = FIB_XNOR_COEFFS[LfsrDw-FIB_XNOR_LUT_OFF][LfsrDw-1:0]; + // check that the most significant bit of polynomial is 1 + `ABR_ASSERT_INIT(MinLfsrWidth_A, LfsrDw >= $low(FIB_XNOR_COEFFS)+FIB_XNOR_LUT_OFF) + `ABR_ASSERT_INIT(MaxLfsrWidth_A, LfsrDw <= $high(FIB_XNOR_COEFFS)+FIB_XNOR_LUT_OFF) + end + + // calculate next state using external XNOR feedback and entropy input + assign next_lfsr_state = LfsrDw'(entropy_i) ^ {lfsr_q[LfsrDw-2:0], ~(^(lfsr_q & coeffs))}; + + // lockup condition is all-ones + assign lockup = &lfsr_q; + + // check that seed is not all-ones + `ABR_ASSERT_INIT(DefaultSeedNzCheck_A, !(&DefaultSeedLocal)) + + + ///////////// + // Unknown // + ///////////// + end else begin : gen_unknown_type + assign coeffs = '0; + assign next_lfsr_state = '0; + assign lockup = 1'b0; + `ABR_ASSERT_INIT(UnknownLfsrType_A, 0) + end + + + ////////////////// + // Shared logic // + ////////////////// + + assign lfsr_d = (seed_en_i) ? seed_i : + (lfsr_en_i && lockup) ? DefaultSeedLocal : + (lfsr_en_i) ? next_lfsr_state : + lfsr_q; + + logic [LfsrDw-1:0] sbox_out; + if (NonLinearOut) begin : gen_out_non_linear + // The "aligned" permutation ensures that adjacent bits do not go into the same SBox. It is + // different from the state permutation that can be specified via the StatePerm parameter. The + // permutation taps out 4 SBox input bits at regular stride intervals. E.g., for a 16bit + // vector, the input assignment looks as follows: + // + // SBox0: 0, 4, 8, 12 + // SBox1: 1, 5, 9, 13 + // SBox2: 2, 6, 10, 14 + // SBox3: 3, 7, 11, 15 + // + // Note that this permutation can be produced by filling the input vector into matrix columns + // and reading out the SBox inputs as matrix rows. + localparam int NumSboxes = LfsrDw / 4; + // Fill in the input vector in col-major order. + logic [3:0][NumSboxes-1:0][LfsrIdxDw-1:0] matrix_indices; + for (genvar j = 0; j < LfsrDw; j++) begin : gen_input_idx_map + assign matrix_indices[j / NumSboxes][j % NumSboxes] = j; + end + // Due to the LFSR shifting pattern, the above permutation has the property that the output of + // SBox(n) is going to be equal to SBox(n+1) in the subsequent cycle (unless the LFSR polynomial + // modifies some of the associated shifted bits via an XOR tap). + // We therefore tweak this permutation by rotating and reversing some of the assignment matrix + // columns. The rotation and reversion operations have been chosen such that this + // generalizes to all power of two widths supported by the LFSR primitive. For 16bit, this + // looks as follows: + // + // SBox0: 0, 6, 11, 14 + // SBox1: 1, 7, 10, 13 + // SBox2: 2, 4, 9, 12 + // SBox3: 3, 5, 8, 15 + // + // This can be achieved by: + // 1) down rotating the second column by NumSboxes/2 + // 2) reversing the third column + // 3) down rotating the fourth column by 1 and reversing it + // + logic [3:0][NumSboxes-1:0][LfsrIdxDw-1:0] matrix_rotrev_indices; + typedef logic [NumSboxes-1:0][LfsrIdxDw-1:0] matrix_col_t; + + // left-rotates a matrix column by the shift amount + function automatic matrix_col_t lrotcol(matrix_col_t col, integer shift); + matrix_col_t out; + for (int k = 0; k < NumSboxes; k++) begin + out[(k + shift) % NumSboxes] = col[k]; + end + return out; + endfunction : lrotcol + + // reverses a matrix column + function automatic matrix_col_t revcol(matrix_col_t col); + return {< StateOutDw) begin : gen_tieoff_unused + logic unused_sbox_out; + assign unused_sbox_out = ^sbox_out; + end + + end else begin : gen_no_state_perm + assign state_o = StateOutDw'(sbox_out); + end + + always_ff @(posedge clk_i or negedge rst_b) begin : p_reg + if (!rst_b) begin + lfsr_q <= DefaultSeedLocal; + end else begin + lfsr_q <= lfsr_d; + end + end + + + /////////////////////// + // shared assertions // + /////////////////////// + + `ABR_ASSERT_KNOWN(DataKnownO_A, state_o) + +// the code below is not meant to be synthesized, +// but it is intended to be used in simulation and FPV +`ifndef SYNTHESIS + function automatic logic [LfsrDw-1:0] compute_next_state(logic [LfsrDw-1:0] lfsrcoeffs, + logic [EntropyDw-1:0] entropy, + logic [LfsrDw-1:0] current_state); + logic state0; + logic [LfsrDw-1:0] next_state; + + next_state = current_state; + + // Galois XOR + if (64'(LfsrType) == 64'("GAL_XOR")) begin + if (next_state == 0) begin + next_state = DefaultSeedLocal; + end else begin + state0 = next_state[0]; + next_state = next_state >> 1; + if (state0) next_state ^= lfsrcoeffs; + next_state ^= LfsrDw'(entropy); + end + // Fibonacci XNOR + end else if (64'(LfsrType) == "FIB_XNOR") begin + if (&next_state) begin + next_state = DefaultSeedLocal; + end else begin + state0 = ~(^(next_state & lfsrcoeffs)); + next_state = next_state << 1; + next_state[0] = state0; + next_state ^= LfsrDw'(entropy); + end + end else begin + $error("unknown lfsr type"); + end + + return next_state; + endfunction : compute_next_state + + // check whether next state is computed correctly + // we shift the assertion by one clock cycle (##1) in order to avoid + // erroneous SVA triggers right after reset deassertion in cases where + // the precondition is true throughout the reset. + // this can happen since the disable_iff evaluates using unsampled values, + // meaning that the assertion may already read rst_b == 1 on an active + // clock edge while the flops in the design have not yet changed state. + `ABR_ASSERT(NextStateCheck_A, ##1 lfsr_en_i && !seed_en_i |=> lfsr_q == + compute_next_state(coeffs, $past(entropy_i), $past(lfsr_q))) + + // Only check this if enabled. + if (StatePermEn) begin : gen_perm_check + // Check that the supplied permutation is valid. + logic [LfsrDw-1:0] lfsr_perm_test; + initial begin : p_perm_check + lfsr_perm_test = '0; + for (int k = 0; k < LfsrDw; k++) begin + lfsr_perm_test[StatePerm[k]] = 1'b1; + end + // All bit positions must be marked with 1. + `ABR_ASSERT_I(PermutationCheck_A, &lfsr_perm_test) + end + end + +`endif + + `ABR_ASSERT_INIT(InputWidth_A, LfsrDw >= EntropyDw) + `ABR_ASSERT_INIT(OutputWidth_A, LfsrDw >= StateOutDw) + + // MSB must be one in any case + `ABR_ASSERT(CoeffCheck_A, coeffs[LfsrDw-1]) + + // output check + `ABR_ASSERT_KNOWN(OutputKnown_A, state_o) + if (!StatePermEn && !NonLinearOut) begin : gen_output_sva + `ABR_ASSERT(OutputCheck_A, state_o == StateOutDw'(lfsr_q)) + end + // if no external input changes the lfsr state, a lockup must not occur (by design) + //`ABR_ASSERT(NoLockups_A, (!entropy_i) && (!seed_en_i) |=> !lockup, clk_i, !rst_b) + `ABR_ASSERT(NoLockups_A, lfsr_en_i && !entropy_i && !seed_en_i |=> !lockup) + + // this can be disabled if unused in order to not distort coverage + if (ExtSeedSVA) begin : gen_ext_seed_sva + // check that external seed is correctly loaded into the state + // rst_b is used directly as part of the pre-condition since the usage of rst_b + // in disable_iff is unsampled. See #1985 for more details + `ABR_ASSERT(ExtDefaultSeedInputCheck_A, (seed_en_i && rst_b) |=> lfsr_q == $past(seed_i)) + end + + // if the external seed mechanism is not used, + // there is theoretically no way we end up in a lockup condition + // in order to not distort coverage, this SVA can be disabled in such cases + if (LockupSVA) begin : gen_lockup_mechanism_sva + // check that a stuck LFSR is correctly reseeded + `ABR_ASSERT(LfsrLockupCheck_A, lfsr_en_i && lockup && !seed_en_i |=> !lockup) + end + + // If non-linear output requested, the LFSR width must be a power of 2 and greater than 16. + if(NonLinearOut) begin : gen_nonlinear_align_check_sva + `ABR_ASSERT_INIT(SboxByteAlign_A, 2**$clog2(LfsrDw) == LfsrDw && LfsrDw >= 16) + end + + if (MaxLenSVA) begin : gen_max_len_sva +`ifndef SYNTHESIS + // the code below is a workaround to enable long sequences to be checked. + // some simulators do not support SVA sequences longer than 2**32-1. + logic [LfsrDw-1:0] cnt_d, cnt_q; + logic perturbed_d, perturbed_q; + logic [LfsrDw-1:0] cmp_val; + + assign cmp_val = {{(LfsrDw-1){1'b1}}, 1'b0}; // 2**LfsrDw-2 + assign cnt_d = (lfsr_en_i && lockup) ? '0 : + (lfsr_en_i && (cnt_q == cmp_val)) ? '0 : + (lfsr_en_i) ? cnt_q + 1'b1 : + cnt_q; + + assign perturbed_d = perturbed_q | (|entropy_i) | seed_en_i; + + always_ff @(posedge clk_i or negedge rst_b) begin : p_max_len + if (!rst_b) begin + cnt_q <= '0; + perturbed_q <= 1'b0; + end else begin + cnt_q <= cnt_d; + perturbed_q <= perturbed_d; + end + end + + `ABR_ASSERT(MaximalLengthCheck0_A, cnt_q == 0 |-> lfsr_q == DefaultSeedLocal, + clk_i, !rst_b || perturbed_q) + `ABR_ASSERT(MaximalLengthCheck1_A, cnt_q != 0 |-> lfsr_q != DefaultSeedLocal, + clk_i, !rst_b || perturbed_q) +`endif + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_max_tree.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_max_tree.sv new file mode 100644 index 0000000000000000000000000000000000000000..d14d157bbd554660db92f9d3ba09f4a7d85c50fa --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_max_tree.sv @@ -0,0 +1,152 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// The module implements a binary tree to find the maximal entry. the solution +// has O(N) area and O(log(N)) delay complexity, and thus scales well with +// many input sources. +// +// Note that only input values marked as "valid" are respected in the maximum computation. +// If there are multiple valid inputs with the same value, the tree will always select the input +// with the smallest index. +// +// If none of the input values are valid, the output index will be 0 and the output value will +// be equal to the input value at index 0. + + +`include "abr_prim_assert.sv" + +module abr_prim_max_tree #( + parameter int NumSrc = 32, + parameter int Width = 8, + // Derived parameters + localparam int SrcWidth = $clog2(NumSrc) +) ( + // The module is combinational - the clock and reset are only used for assertions. + input clk_i, + input rst_b, + input [NumSrc-1:0][Width-1:0] values_i, // Input values + input [NumSrc-1:0] valid_i, // Input valid bits + output logic [Width-1:0] max_value_o, // Maximum value + output logic [SrcWidth-1:0] max_idx_o, // Index of the maximum value + output logic max_valid_o // Whether any of the inputs is valid +); + + /////////////////////// + // Binary tree logic // + /////////////////////// + + // This only works with 2 or more sources. + `ABR_ASSERT_INIT(NumSources_A, NumSrc >= 2) + + // Align to powers of 2 for simplicity. + // A full binary tree with N levels has 2**N + 2**N-1 nodes. + localparam int NumLevels = $clog2(NumSrc); + logic [2**(NumLevels+1)-2:0] vld_tree; + logic [2**(NumLevels+1)-2:0][SrcWidth-1:0] idx_tree; + logic [2**(NumLevels+1)-2:0][Width-1:0] max_tree; + + for (genvar level = 0; level < NumLevels+1; level++) begin : gen_tree + // + // level+1 C0 C1 <- "Base1" points to the first node on "level+1", + // \ / these nodes are the children of the nodes one level below + // level Pa <- "Base0", points to the first node on "level", + // these nodes are the parents of the nodes one level above + // + // hence we have the following indices for the paPa, C0, C1 nodes: + // Pa = 2**level - 1 + offset = Base0 + offset + // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset + // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 + // + localparam int Base0 = (2**level)-1; + localparam int Base1 = (2**(level+1))-1; + + for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level + localparam int Pa = Base0 + offset; + localparam int C0 = Base1 + 2*offset; + localparam int C1 = Base1 + 2*offset + 1; + + // This assigns the input values, their corresponding IDs and valid signals to the tree leafs. + if (level == NumLevels) begin : gen_leafs + if (offset < NumSrc) begin : gen_assign + assign vld_tree[Pa] = valid_i[offset]; + assign idx_tree[Pa] = offset; + assign max_tree[Pa] = values_i[offset]; + end else begin : gen_tie_off + assign vld_tree[Pa] = '0; + assign idx_tree[Pa] = '0; + assign max_tree[Pa] = '0; + end + // This creates the node assignments. + end else begin : gen_nodes + logic sel; // Local helper variable + // In case only one of the parents is valid, forward that one + // In case both parents are valid, forward the one with higher value + assign sel = (~vld_tree[C0] & vld_tree[C1]) | + (vld_tree[C0] & vld_tree[C1] & logic'(max_tree[C1] > max_tree[C0])); + // Forwarding muxes + // Note: these ternaries have triggered a synthesis bug in Vivado versions older + // than 2020.2. If the problem resurfaces again, have a look at issue #1408. + assign vld_tree[Pa] = (sel) ? vld_tree[C1] : vld_tree[C0]; + assign idx_tree[Pa] = (sel) ? idx_tree[C1] : idx_tree[C0]; + assign max_tree[Pa] = (sel) ? max_tree[C1] : max_tree[C0]; + end + end : gen_level + end : gen_tree + + + // The results can be found at the tree root + assign max_valid_o = vld_tree[0]; + assign max_idx_o = idx_tree[0]; + assign max_value_o = max_tree[0]; + + //////////////// + // Assertions // + //////////////// + +`ifdef ABR_INC_ASSERT + //VCS coverage off + // pragma coverage off + + // Helper functions for assertions below. + function automatic logic [Width-1:0] max_value (input logic [NumSrc-1:0][Width-1:0] values_i, + input logic [NumSrc-1:0] valid_i); + logic [Width-1:0] value = '0; + for (int k = 0; k < NumSrc; k++) begin + if (valid_i[k] && values_i[k] > value) begin + value = values_i[k]; + end + end + return value; + endfunction : max_value + + function automatic logic [SrcWidth-1:0] max_idx (input logic [NumSrc-1:0][Width-1:0] values_i, + input logic [NumSrc-1:0] valid_i); + logic [Width-1:0] value = '0; + logic [SrcWidth-1:0] idx = '0; + for (int k = NumSrc-1; k >= 0; k--) begin + if (valid_i[k] && values_i[k] >= value) begin + value = values_i[k]; + idx = k; + end + end + return idx; + endfunction : max_idx + + logic [Width-1:0] max_value_exp; + logic [SrcWidth-1:0] max_idx_exp; + assign max_value_exp = max_value(values_i, valid_i); + assign max_idx_exp = max_idx(values_i, valid_i); + //VCS coverage on + // pragma coverage on + + // TODO(10588): Below syntax is not supported in xcelium, track xcelium cases #46591452. + // `ABR_ASSERT(ValidInImpliesValidOut_A, |valid_i <-> max_valid_o) + `ABR_ASSERT(ValidInImpliesValidOut_A, |valid_i === max_valid_o) + `ABR_ASSERT(MaxComputation_A, max_valid_o |-> max_value_o == max_value_exp) + `ABR_ASSERT(MaxComputationInvalid_A, !max_valid_o |-> max_value_o == values_i[0]) + `ABR_ASSERT(MaxIndexComputation_A, max_valid_o |-> max_idx_o == max_idx_exp) + `ABR_ASSERT(MaxIndexComputationInvalid_A, !max_valid_o |-> max_idx_o == '0) +`endif + +endmodule : abr_prim_max_tree diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi4_sync.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi4_sync.sv new file mode 100644 index 0000000000000000000000000000000000000000..35550bfeee88852a4f8e8e4400f9fe0086aff039 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi4_sync.sv @@ -0,0 +1,178 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/design/gen-mubi.py +// +// Double-synchronizer flop for multibit signals with additional output buffers. + +`include "abr_prim_assert.sv" + +module abr_prim_mubi4_sync + import abr_prim_mubi_pkg::*; +#( + // Number of separately buffered output signals. + // The buffer cells have a don't touch constraint + // on them such that synthesis tools won't collapse + // all copies into one signal. + parameter int NumCopies = 1, + // This instantiates the synchronizer flops if set to 1. + // In special cases where the receiver is in the same clock domain as the sender, + // this can be set to 0. However, it is recommended to leave this at 1. + parameter bit AsyncOn = 1, + // This controls whether the mubi module institutes stability checks when + // AsyncOn is set. If stability checks are on, a 3rd stage of storage is + // added after the synchronizers and the outputs only updated if the 3rd + // stage and sychronizer agree. If they do not agree, the ResetValue is + // output instead. + parameter bit StabilityCheck = 0, + // Reset value for the sync flops + parameter mubi4_t ResetValue = MuBi4False +) ( + input clk_i, + input rst_b, + input mubi4_t mubi_i, + output mubi4_t [NumCopies-1:0] mubi_o +); + + `ABR_ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0) + + logic [MuBi4Width-1:0] mubi; + if (AsyncOn) begin : gen_flops + logic [MuBi4Width-1:0] mubi_sync; + abr_prim_flop_2sync #( + .Width(MuBi4Width), + .ResetValue(MuBi4Width'(ResetValue)) + ) u_abr_prim_flop_2sync ( + .clk_i, + .rst_b, + .d_i(MuBi4Width'(mubi_i)), + .q_o(mubi_sync) + ); + + if (StabilityCheck) begin : gen_stable_chks + logic [MuBi4Width-1:0] mubi_q; + abr_prim_flop #( + .Width(MuBi4Width), + .ResetValue(MuBi4Width'(ResetValue)) + ) u_abr_prim_flop_3rd_stage ( + .clk_i, + .rst_b, + .d_i(mubi_sync), + .q_o(mubi_q) + ); + + logic [MuBi4Width-1:0] sig_unstable; + abr_prim_xor2 #( + .Width(MuBi4Width) + ) u_mubi_xor ( + .in0_i(mubi_sync), + .in1_i(mubi_q), + .out_o(sig_unstable) + ); + + logic [MuBi4Width-1:0] reset_value; + assign reset_value = ResetValue; + + for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bufs_muxes + logic [MuBi4Width-1:0] sig_unstable_buf; + + // each mux gets its own buffered output, this ensures the OR-ing + // cannot be defeated in one place. + abr_prim_sec_anchor_buf #( + .Width(MuBi4Width) + ) u_sig_unstable_buf ( + .in_i(sig_unstable), + .out_o(sig_unstable_buf) + ); + + // if any xor indicates signal is unstable, output the reset + // value. note that the input and output signals of this mux + // are driven/read by constrained primitive cells (regs, buffers), + // hence this mux can be implemented behaviorally. + assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; + end + +// Note regarding SVAs below: +// +// 1) Without the sampled rst_b pre-condition, this may cause false assertion failures right after +// a reset release, since the "disable iff" condition with the rst_b is sampled in the "observed" +// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page +// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_b +// on the active clock edge. This causes the assertion to evaluate although the reset was actually +// 0 when entering this simulation cycle. +// +// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may +// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly +// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock +// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make +// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no +// sampling mismatches. +`ifdef ABR_INC_ASSERT + mubi4_t mubi_in_sva_q; + always_ff @(posedge clk_i) begin + mubi_in_sva_q <= mubi_i; + end + `ABR_ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}}) + `ABR_ASSERT(OutputDelay_A, + rst_b |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}}) +`endif + end else begin : gen_no_stable_chks + assign mubi = mubi_sync; +`ifdef ABR_INC_ASSERT + mubi4_t mubi_in_sva_q; + always_ff @(posedge clk_i) begin + mubi_in_sva_q <= mubi_i; + end + `ABR_ASSERT(OutputDelay_A, + rst_b |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || + $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1))) +`endif + end + end else begin : gen_no_flops + + //VCS coverage off + // pragma coverage off + + // This unused companion logic helps remove lint errors + // for modules where clock and reset are used for assertions only + // This logic will be removed for synthesis since it is unloaded. + mubi4_t unused_logic; + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + unused_logic <= MuBi4False; + end else begin + unused_logic <= mubi_i; + end + end + + //VCS coverage on + // pragma coverage on + + assign mubi = MuBi4Width'(mubi_i); + + `ABR_ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) + end + + for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs + logic [MuBi4Width-1:0] mubi_out; + for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits + abr_prim_buf u_abr_prim_buf ( + .in_i(mubi[k]), + .out_o(mubi_out[k]) + ); + end + assign mubi_o[j] = mubi4_t'(mubi_out); + end + + //////////////// + // Assertions // + //////////////// + + // The outputs should be known at all times. + `ABR_ASSERT_KNOWN(OutputsKnown_A, mubi_o) + +endmodule : abr_prim_mubi4_sync diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi8_sync.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi8_sync.sv new file mode 100644 index 0000000000000000000000000000000000000000..120060ac88b03b71c195a45b01fb577ed2c298a4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi8_sync.sv @@ -0,0 +1,179 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/design/gen-mubi.py +// +// Double-synchronizer flop for multibit signals with additional output buffers. + +`include "abr_prim_assert.sv" + +module abr_prim_mubi8_sync + import abr_prim_mubi_pkg::*; +#( + // Number of separately buffered output signals. + // The buffer cells have a don't touch constraint + // on them such that synthesis tools won't collapse + // all copies into one signal. + parameter int NumCopies = 1, + // This instantiates the synchronizer flops if set to 1. + // In special cases where the receiver is in the same clock domain as the sender, + // this can be set to 0. However, it is recommended to leave this at 1. + parameter bit AsyncOn = 1, + // This controls whether the mubi module institutes stability checks when + // AsyncOn is set. If stability checks are on, a 3rd stage of storage is + // added after the synchronizers and the outputs only updated if the 3rd + // stage and sychronizer agree. If they do not agree, the ResetValue is + // output instead. + parameter bit StabilityCheck = 0, + // Reset value for the sync flops + parameter mubi8_t ResetValue = MuBi8False +) ( + input clk_i, + input rst_b, + input mubi8_t mubi_i, + output mubi8_t [NumCopies-1:0] mubi_o +); + + `ABR_ASSERT_INIT(NumCopiesMustBeGreaterZero_A, NumCopies > 0) + + logic [MuBi8Width-1:0] mubi; + if (AsyncOn) begin : gen_flops + logic [MuBi8Width-1:0] mubi_sync; + abr_prim_flop_2sync #( + .Width(MuBi8Width), + .ResetValue(MuBi8Width'(ResetValue)) + ) u_abr_prim_flop_2sync ( + .clk_i, + .rst_b, + .d_i(MuBi8Width'(mubi_i)), + .q_o(mubi_sync) + ); + + if (StabilityCheck) begin : gen_stable_chks + logic [MuBi8Width-1:0] mubi_q; + abr_prim_flop #( + .Width(MuBi8Width), + .ResetValue(MuBi8Width'(ResetValue)) + ) u_abr_prim_flop_3rd_stage ( + .clk_i, + .rst_b, + .d_i(mubi_sync), + .q_o(mubi_q) + ); + + logic [MuBi8Width-1:0] sig_unstable; + abr_prim_xor2 #( + .Width(MuBi8Width) + ) u_mubi_xor ( + .in0_i(mubi_sync), + .in1_i(mubi_q), + .out_o(sig_unstable) + ); + + logic [MuBi8Width-1:0] reset_value; + assign reset_value = ResetValue; + + for (genvar k = 0; k < MuBi8Width; k++) begin : gen_bufs_muxes + logic [MuBi8Width-1:0] sig_unstable_buf; + + // each mux gets its own buffered output, this ensures the OR-ing + // cannot be defeated in one place. + abr_prim_sec_anchor_buf #( + .Width(MuBi8Width) + ) u_sig_unstable_buf ( + .in_i(sig_unstable), + .out_o(sig_unstable_buf) + ); + + // if any xor indicates signal is unstable, output the reset + // value. note that the input and output signals of this mux + // are driven/read by constrained primitive cells (regs, buffers), + // hence this mux can be implemented behaviorally. + assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k]; + end + +// Note regarding SVAs below: +// +// 1) Without the sampled rst_b pre-condition, this may cause false assertion failures right after +// a reset release, since the "disable iff" condition with the rst_b is sampled in the "observed" +// SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page +// 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_b +// on the active clock edge. This causes the assertion to evaluate although the reset was actually +// 0 when entering this simulation cycle. +// +// 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may +// originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly +// at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock +// cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make +// use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no +// sampling mismatches. +`ifdef ABR_INC_ASSERT + mubi8_t mubi_in_sva_q; + always_ff @(posedge clk_i) begin + mubi_in_sva_q <= mubi_i; + end + `ABR_ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}}) + `ABR_ASSERT(OutputDelay_A, + rst_b |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}}) +`endif + end else begin : gen_no_stable_chks + assign mubi = mubi_sync; +`ifdef ABR_INC_ASSERT + mubi8_t mubi_in_sva_q; + always_ff @(posedge clk_i) begin + mubi_in_sva_q <= mubi_i; + end + `ABR_ASSERT(OutputDelay_A, + rst_b |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} || + ($past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)) || + !rst_b)) +`endif + end + end else begin : gen_no_flops + + //VCS coverage off + // pragma coverage off + + // This unused companion logic helps remove lint errors + // for modules where clock and reset are used for assertions only + // This logic will be removed for synthesis since it is unloaded. + mubi8_t unused_logic; + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + unused_logic <= MuBi8False; + end else begin + unused_logic <= mubi_i; + end + end + + //VCS coverage on + // pragma coverage on + + assign mubi = MuBi8Width'(mubi_i); + + `ABR_ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}}) + end + + for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs + logic [MuBi8Width-1:0] mubi_out; + for (genvar k = 0; k < MuBi8Width; k++) begin : gen_bits + abr_prim_buf u_abr_prim_buf ( + .in_i(mubi[k]), + .out_o(mubi_out[k]) + ); + end + assign mubi_o[j] = mubi8_t'(mubi_out); + end + + //////////////// + // Assertions // + //////////////// + + // The outputs should be known at all times. + `ABR_ASSERT_KNOWN(OutputsKnown_A, mubi_o) + +endmodule : abr_prim_mubi8_sync diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..4d1923807182fb5b2a8bfdb3e9e63a7da54d0f23 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_mubi_pkg.sv @@ -0,0 +1,545 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ------------------- W A R N I N G: A U T O - G E N E R A T E D C O D E !! -------------------// +// PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND: +// +// util/design/gen-mubi.py +// +// This package defines common multibit signal types, active high and active low values and +// the corresponding functions to test whether the values are set or not. + +`include "abr_prim_assert.sv" + +package abr_prim_mubi_pkg; + + ////////////////////////////////////////////// + // 4 Bit Multibit Type and Functions // + ////////////////////////////////////////////// + + parameter int MuBi4Width = 4; + typedef enum logic [MuBi4Width-1:0] { + MuBi4True = 4'h6, // enabled + MuBi4False = 4'h9 // disabled + } mubi4_t; + + // This is a prerequisite for the multibit functions below to work. + `ABR_ASSERT_STATIC_IN_PACKAGE(CheckMuBi4ValsComplementary_A, MuBi4True == ~MuBi4False) + + // Test whether the value is supplied is one of the valid enumerations + function automatic logic mubi4_test_invalid(mubi4_t val); + return ~(val inside {MuBi4True, MuBi4False}); + endfunction : mubi4_test_invalid + + // Convert a 1 input value to a mubi output + function automatic mubi4_t mubi4_bool_to_mubi(logic val); + return (val ? MuBi4True : MuBi4False); + endfunction : mubi4_bool_to_mubi + + // Test whether the multibit value signals an "enabled" condition. + // The strict version of this function requires + // the multibit value to equal True. + function automatic logic mubi4_test_true_strict(mubi4_t val); + return MuBi4True == val; + endfunction : mubi4_test_true_strict + + // Test whether the multibit value signals a "disabled" condition. + // The strict version of this function requires + // the multibit value to equal False. + function automatic logic mubi4_test_false_strict(mubi4_t val); + return MuBi4False == val; + endfunction : mubi4_test_false_strict + + // Test whether the multibit value signals an "enabled" condition. + // The loose version of this function interprets all + // values other than False as "enabled". + function automatic logic mubi4_test_true_loose(mubi4_t val); + return MuBi4False != val; + endfunction : mubi4_test_true_loose + + // Test whether the multibit value signals a "disabled" condition. + // The loose version of this function interprets all + // values other than True as "disabled". + function automatic logic mubi4_test_false_loose(mubi4_t val); + return MuBi4True != val; + endfunction : mubi4_test_false_loose + + + // Performs a logical OR operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | act + // !act | act | act + // act | act | act + // + function automatic mubi4_t mubi4_or(mubi4_t a, mubi4_t b, mubi4_t act); + logic [MuBi4Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi4Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] || b_in[k]; + end else begin + out[k] = a_in[k] && b_in[k]; + end + end + return mubi4_t'(out); + endfunction : mubi4_or + + // Performs a logical AND operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | !act + // !act | act | !act + // act | act | act + // + function automatic mubi4_t mubi4_and(mubi4_t a, mubi4_t b, mubi4_t act); + logic [MuBi4Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi4Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] && b_in[k]; + end else begin + out[k] = a_in[k] || b_in[k]; + end + end + return mubi4_t'(out); + endfunction : mubi4_and + + // Performs a logical OR operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi4_t mubi4_or_hi(mubi4_t a, mubi4_t b); + return mubi4_or(a, b, MuBi4True); + endfunction : mubi4_or_hi + + // Performs a logical AND operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi4_t mubi4_and_hi(mubi4_t a, mubi4_t b); + return mubi4_and(a, b, MuBi4True); + endfunction : mubi4_and_hi + + // Performs a logical OR operation between two multibit values. + // This treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi4_t mubi4_or_lo(mubi4_t a, mubi4_t b); + return mubi4_or(a, b, MuBi4False); + endfunction : mubi4_or_lo + + // Performs a logical AND operation between two multibit values. + // Tlos treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi4_t mubi4_and_lo(mubi4_t a, mubi4_t b); + return mubi4_and(a, b, MuBi4False); + endfunction : mubi4_and_lo + + ////////////////////////////////////////////// + // 8 Bit Multibit Type and Functions // + ////////////////////////////////////////////// + + parameter int MuBi8Width = 8; + typedef enum logic [MuBi8Width-1:0] { + MuBi8True = 8'h96, // enabled + MuBi8False = 8'h69 // disabled + } mubi8_t; + + // This is a prerequisite for the multibit functions below to work. + `ABR_ASSERT_STATIC_IN_PACKAGE(CheckMuBi8ValsComplementary_A, MuBi8True == ~MuBi8False) + + // Test whether the value is supplied is one of the valid enumerations + function automatic logic mubi8_test_invalid(mubi8_t val); + return ~(val inside {MuBi8True, MuBi8False}); + endfunction : mubi8_test_invalid + + // Convert a 1 input value to a mubi output + function automatic mubi8_t mubi8_bool_to_mubi(logic val); + return (val ? MuBi8True : MuBi8False); + endfunction : mubi8_bool_to_mubi + + // Test whether the multibit value signals an "enabled" condition. + // The strict version of this function requires + // the multibit value to equal True. + function automatic logic mubi8_test_true_strict(mubi8_t val); + return MuBi8True == val; + endfunction : mubi8_test_true_strict + + // Test whether the multibit value signals a "disabled" condition. + // The strict version of this function requires + // the multibit value to equal False. + function automatic logic mubi8_test_false_strict(mubi8_t val); + return MuBi8False == val; + endfunction : mubi8_test_false_strict + + // Test whether the multibit value signals an "enabled" condition. + // The loose version of this function interprets all + // values other than False as "enabled". + function automatic logic mubi8_test_true_loose(mubi8_t val); + return MuBi8False != val; + endfunction : mubi8_test_true_loose + + // Test whether the multibit value signals a "disabled" condition. + // The loose version of this function interprets all + // values other than True as "disabled". + function automatic logic mubi8_test_false_loose(mubi8_t val); + return MuBi8True != val; + endfunction : mubi8_test_false_loose + + + // Performs a logical OR operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | act + // !act | act | act + // act | act | act + // + function automatic mubi8_t mubi8_or(mubi8_t a, mubi8_t b, mubi8_t act); + logic [MuBi8Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi8Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] || b_in[k]; + end else begin + out[k] = a_in[k] && b_in[k]; + end + end + return mubi8_t'(out); + endfunction : mubi8_or + + // Performs a logical AND operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | !act + // !act | act | !act + // act | act | act + // + function automatic mubi8_t mubi8_and(mubi8_t a, mubi8_t b, mubi8_t act); + logic [MuBi8Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi8Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] && b_in[k]; + end else begin + out[k] = a_in[k] || b_in[k]; + end + end + return mubi8_t'(out); + endfunction : mubi8_and + + // Performs a logical OR operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi8_t mubi8_or_hi(mubi8_t a, mubi8_t b); + return mubi8_or(a, b, MuBi8True); + endfunction : mubi8_or_hi + + // Performs a logical AND operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi8_t mubi8_and_hi(mubi8_t a, mubi8_t b); + return mubi8_and(a, b, MuBi8True); + endfunction : mubi8_and_hi + + // Performs a logical OR operation between two multibit values. + // This treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi8_t mubi8_or_lo(mubi8_t a, mubi8_t b); + return mubi8_or(a, b, MuBi8False); + endfunction : mubi8_or_lo + + // Performs a logical AND operation between two multibit values. + // Tlos treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi8_t mubi8_and_lo(mubi8_t a, mubi8_t b); + return mubi8_and(a, b, MuBi8False); + endfunction : mubi8_and_lo + + ////////////////////////////////////////////// + // 12 Bit Multibit Type and Functions // + ////////////////////////////////////////////// + + parameter int MuBi12Width = 12; + typedef enum logic [MuBi12Width-1:0] { + MuBi12True = 12'h696, // enabled + MuBi12False = 12'h969 // disabled + } mubi12_t; + + // This is a prerequisite for the multibit functions below to work. + `ABR_ASSERT_STATIC_IN_PACKAGE(CheckMuBi12ValsComplementary_A, MuBi12True == ~MuBi12False) + + // Test whether the value is supplied is one of the valid enumerations + function automatic logic mubi12_test_invalid(mubi12_t val); + return ~(val inside {MuBi12True, MuBi12False}); + endfunction : mubi12_test_invalid + + // Convert a 1 input value to a mubi output + function automatic mubi12_t mubi12_bool_to_mubi(logic val); + return (val ? MuBi12True : MuBi12False); + endfunction : mubi12_bool_to_mubi + + // Test whether the multibit value signals an "enabled" condition. + // The strict version of this function requires + // the multibit value to equal True. + function automatic logic mubi12_test_true_strict(mubi12_t val); + return MuBi12True == val; + endfunction : mubi12_test_true_strict + + // Test whether the multibit value signals a "disabled" condition. + // The strict version of this function requires + // the multibit value to equal False. + function automatic logic mubi12_test_false_strict(mubi12_t val); + return MuBi12False == val; + endfunction : mubi12_test_false_strict + + // Test whether the multibit value signals an "enabled" condition. + // The loose version of this function interprets all + // values other than False as "enabled". + function automatic logic mubi12_test_true_loose(mubi12_t val); + return MuBi12False != val; + endfunction : mubi12_test_true_loose + + // Test whether the multibit value signals a "disabled" condition. + // The loose version of this function interprets all + // values other than True as "disabled". + function automatic logic mubi12_test_false_loose(mubi12_t val); + return MuBi12True != val; + endfunction : mubi12_test_false_loose + + + // Performs a logical OR operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | act + // !act | act | act + // act | act | act + // + function automatic mubi12_t mubi12_or(mubi12_t a, mubi12_t b, mubi12_t act); + logic [MuBi12Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi12Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] || b_in[k]; + end else begin + out[k] = a_in[k] && b_in[k]; + end + end + return mubi12_t'(out); + endfunction : mubi12_or + + // Performs a logical AND operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | !act + // !act | act | !act + // act | act | act + // + function automatic mubi12_t mubi12_and(mubi12_t a, mubi12_t b, mubi12_t act); + logic [MuBi12Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi12Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] && b_in[k]; + end else begin + out[k] = a_in[k] || b_in[k]; + end + end + return mubi12_t'(out); + endfunction : mubi12_and + + // Performs a logical OR operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi12_t mubi12_or_hi(mubi12_t a, mubi12_t b); + return mubi12_or(a, b, MuBi12True); + endfunction : mubi12_or_hi + + // Performs a logical AND operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi12_t mubi12_and_hi(mubi12_t a, mubi12_t b); + return mubi12_and(a, b, MuBi12True); + endfunction : mubi12_and_hi + + // Performs a logical OR operation between two multibit values. + // This treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi12_t mubi12_or_lo(mubi12_t a, mubi12_t b); + return mubi12_or(a, b, MuBi12False); + endfunction : mubi12_or_lo + + // Performs a logical AND operation between two multibit values. + // Tlos treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi12_t mubi12_and_lo(mubi12_t a, mubi12_t b); + return mubi12_and(a, b, MuBi12False); + endfunction : mubi12_and_lo + + ////////////////////////////////////////////// + // 16 Bit Multibit Type and Functions // + ////////////////////////////////////////////// + + parameter int MuBi16Width = 16; + typedef enum logic [MuBi16Width-1:0] { + MuBi16True = 16'h9696, // enabled + MuBi16False = 16'h6969 // disabled + } mubi16_t; + + // This is a prerequisite for the multibit functions below to work. + `ABR_ASSERT_STATIC_IN_PACKAGE(CheckMuBi16ValsComplementary_A, MuBi16True == ~MuBi16False) + + // Test whether the value is supplied is one of the valid enumerations + function automatic logic mubi16_test_invalid(mubi16_t val); + return ~(val inside {MuBi16True, MuBi16False}); + endfunction : mubi16_test_invalid + + // Convert a 1 input value to a mubi output + function automatic mubi16_t mubi16_bool_to_mubi(logic val); + return (val ? MuBi16True : MuBi16False); + endfunction : mubi16_bool_to_mubi + + // Test whether the multibit value signals an "enabled" condition. + // The strict version of this function requires + // the multibit value to equal True. + function automatic logic mubi16_test_true_strict(mubi16_t val); + return MuBi16True == val; + endfunction : mubi16_test_true_strict + + // Test whether the multibit value signals a "disabled" condition. + // The strict version of this function requires + // the multibit value to equal False. + function automatic logic mubi16_test_false_strict(mubi16_t val); + return MuBi16False == val; + endfunction : mubi16_test_false_strict + + // Test whether the multibit value signals an "enabled" condition. + // The loose version of this function interprets all + // values other than False as "enabled". + function automatic logic mubi16_test_true_loose(mubi16_t val); + return MuBi16False != val; + endfunction : mubi16_test_true_loose + + // Test whether the multibit value signals a "disabled" condition. + // The loose version of this function interprets all + // values other than True as "disabled". + function automatic logic mubi16_test_false_loose(mubi16_t val); + return MuBi16True != val; + endfunction : mubi16_test_false_loose + + + // Performs a logical OR operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | act + // !act | act | act + // act | act | act + // + function automatic mubi16_t mubi16_or(mubi16_t a, mubi16_t b, mubi16_t act); + logic [MuBi16Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi16Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] || b_in[k]; + end else begin + out[k] = a_in[k] && b_in[k]; + end + end + return mubi16_t'(out); + endfunction : mubi16_or + + // Performs a logical AND operation between two multibit values. + // This treats "act" as logical 1, and all other values are + // treated as 0. Truth table: + // + // A | B | OUT + //------+------+----- + // !act | !act | !act + // act | !act | !act + // !act | act | !act + // act | act | act + // + function automatic mubi16_t mubi16_and(mubi16_t a, mubi16_t b, mubi16_t act); + logic [MuBi16Width-1:0] a_in, b_in, act_in, out; + a_in = a; + b_in = b; + act_in = act; + for (int k = 0; k < MuBi16Width; k++) begin + if (act_in[k]) begin + out[k] = a_in[k] && b_in[k]; + end else begin + out[k] = a_in[k] || b_in[k]; + end + end + return mubi16_t'(out); + endfunction : mubi16_and + + // Performs a logical OR operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi16_t mubi16_or_hi(mubi16_t a, mubi16_t b); + return mubi16_or(a, b, MuBi16True); + endfunction : mubi16_or_hi + + // Performs a logical AND operation between two multibit values. + // This treats "True" as logical 1, and all other values are + // treated as 0. + function automatic mubi16_t mubi16_and_hi(mubi16_t a, mubi16_t b); + return mubi16_and(a, b, MuBi16True); + endfunction : mubi16_and_hi + + // Performs a logical OR operation between two multibit values. + // This treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi16_t mubi16_or_lo(mubi16_t a, mubi16_t b); + return mubi16_or(a, b, MuBi16False); + endfunction : mubi16_or_lo + + // Performs a logical AND operation between two multibit values. + // Tlos treats "False" as logical 1, and all other values are + // treated as 0. + function automatic mubi16_t mubi16_and_lo(mubi16_t a, mubi16_t b); + return mubi16_and(a, b, MuBi16False); + endfunction : mubi16_and_lo + +endpackage : abr_prim_mubi_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_onehot_check.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_onehot_check.sv new file mode 100644 index 0000000000000000000000000000000000000000..db16d3f98bd65fd21b267bbff8a16e3bc55f05d1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_onehot_check.sv @@ -0,0 +1,155 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Onehot checker. +// +// This module checks whether the input vector oh_i is onehot0 and generates an error if not. +// +// Optionally, two additional checks can be activated: +// +// 1) EnableCheck: this check performs an OR reduction of the onehot vector, and compares +// the result with en_i. If there is a mismatch, an error is generated. +// 2) AddrCheck: this checks whether the onehot bit is in the correct position. +// It requires an additional address addr_i to be supplied to the module. +// +// All checks make use of an explicit binary tree implementation in order to minimize the delay. +// + +`include "abr_prim_assert.sv" + +module abr_prim_onehot_check #( + parameter int unsigned AddrWidth = 5, + // The onehot width can be <= 2**AddrWidth and does not have to be a power of two. + parameter int unsigned OneHotWidth = 2**AddrWidth, + // If set to 0, the addr_i input will not be used for the check and can be tied off. + parameter bit AddrCheck = 1, + // If set to 0, the en_i value will not be used for the check and can be tied off. + parameter bit EnableCheck = 1, + // If set to 1, the oh_i vector must always be one hot if en_i is set to 1. + // If set to 0, the oh_i vector may be 0 if en_i is set to 1 (useful when oh_i can be masked). + parameter bit StrictCheck = 1, + // This should only be disabled in special circumstances, for example + // in non-comportable IPs where an error does not trigger an alert. + parameter bit EnableAlertTriggerSVA = 1 +) ( + // The module is combinational - the clock and reset are only used for assertions. + input clk_i, + input rst_b, + + input logic [OneHotWidth-1:0] oh_i, + input logic [AddrWidth-1:0] addr_i, + input logic en_i, + + output logic err_o +); + + /////////////////////// + // Binary tree logic // + /////////////////////// + + `ABR_ASSERT_INIT(NumSources_A, OneHotWidth >= 1) + `ABR_ASSERT_INIT(AddrWidth_A, AddrWidth >= 1) + `ABR_ASSERT_INIT(AddrRange_A, OneHotWidth <= 2**AddrWidth) + `ABR_ASSERT_INIT(AddrImpliesEnable_A, AddrCheck && EnableCheck || !AddrCheck) + + // Align to powers of 2 for simplicity. + // A full binary tree with N levels has 2**N + 2**N-1 nodes. + localparam int NumLevels = AddrWidth; + logic [2**(NumLevels+1)-2:0] or_tree; + logic [2**(NumLevels+1)-2:0] and_tree; // Used for the address check + logic [2**(NumLevels+1)-2:0] err_tree; // Used for the enable check + + for (genvar level = 0; level < NumLevels+1; level++) begin : gen_tree + // + // level+1 C0 C1 <- "Base1" points to the first node on "level+1", + // \ / these nodes are the children of the nodes one level below + // level Pa <- "Base0", points to the first node on "level", + // these nodes are the parents of the nodes one level above + // + // hence we have the following indices for the paPa, C0, C1 nodes: + // Pa = 2**level - 1 + offset = Base0 + offset + // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset + // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 + // + localparam int Base0 = (2**level)-1; + localparam int Base1 = (2**(level+1))-1; + + for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level + localparam int Pa = Base0 + offset; + localparam int C0 = Base1 + 2*offset; + localparam int C1 = Base1 + 2*offset + 1; + + // This assigns the input values, their corresponding IDs and valid signals to the tree leafs. + if (level == NumLevels) begin : gen_leafs + if (offset < OneHotWidth) begin : gen_assign + assign or_tree[Pa] = oh_i[offset]; + assign and_tree[Pa] = oh_i[offset]; + end else begin : gen_tie_off + assign or_tree[Pa] = 1'b0; + assign and_tree[Pa] = 1'b0; + end + assign err_tree[Pa] = 1'b0; + // This creates the node assignments. + end else begin : gen_nodes + assign or_tree[Pa] = or_tree[C0] || or_tree[C1]; + assign and_tree[Pa] = (!addr_i[AddrWidth-1-level] && and_tree[C0]) || + (addr_i[AddrWidth-1-level] && and_tree[C1]); + assign err_tree[Pa] = (or_tree[C0] && or_tree[C1]) || err_tree[C0] || err_tree[C1]; + end + end : gen_level + end : gen_tree + + /////////////////// + // Onehot Checks // + /////////////////// + + logic enable_err, addr_err, oh0_err; + assign err_o = oh0_err || enable_err || addr_err; + + // Check that no more than 1 bit is set in the vector. + assign oh0_err = err_tree[0]; + `ABR_ASSERT(Onehot0Check_A, !$onehot0(oh_i) |-> err_o) + + // Check that en_i agrees with (|oh_i). + // Note: if StrictCheck 0, the oh_i vector may be all-zero if en_i == 1 (but not vice versa). + if (EnableCheck) begin : gen_enable_check + if (StrictCheck) begin : gen_strict + assign enable_err = or_tree[0] ^ en_i; + `ABR_ASSERT(EnableCheck_A, (|oh_i) != en_i |-> err_o) + end else begin : gen_not_strict + assign enable_err = !en_i && or_tree[0]; + `ABR_ASSERT(EnableCheck_A, !en_i && (|oh_i) |-> err_o) + end + end else begin : gen_no_enable_check + logic unused_or_tree; + assign unused_or_tree = ^or_tree; + assign enable_err = 1'b0; + end + + // Check that the set bit is actually in the correct position. + if (AddrCheck) begin : gen_addr_check_strict + assign addr_err = or_tree[0] ^ and_tree[0]; + `ABR_ASSERT(AddrCheck_A, oh_i[addr_i] != (|oh_i) |-> err_o) + end else begin : gen_no_addr_check_strict + logic unused_and_tree; + assign unused_and_tree = ^and_tree; + assign addr_err = 1'b0; + end + + // This logic that will be assign to one, when user adds macro + // ABR_ASSERT_PRIM_ONEHOT_ERROR_TRIGGER_ALERT to check the error with alert, in case that + // abr_prim_onehot_check is used in design without adding this assertion check. + `ifdef ABR_INC_ASSERT + `ifndef PRIM_DEFAULT_IMPL + `define ABR_PRIM_DEFAULT_IMPL abr_prim_pkg::ImplGeneric + `endif + parameter abr_prim_pkg::impl_e Impl = `ABR_PRIM_DEFAULT_IMPL; + + logic unused_assert_connected; + // TODO(#13337): only check generic for now. The path of this prim in other Impl may differ + if (Impl == abr_prim_pkg::ImplGeneric) begin : gen_generic + `ABR_ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA) + end + `endif +endmodule : abr_prim_onehot_check diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_packer_fifo.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_packer_fifo.sv new file mode 100644 index 0000000000000000000000000000000000000000..287b3b4d3b293f65eb63fc030759309dbcd7332b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_packer_fifo.sv @@ -0,0 +1,180 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Supports packed and unpacked modes +// Uses FIFO timing on the control signals +// No masking or flush functions supported + +// Timings - case where InW < OutW +// clk_i __|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__ +// wvalid_i _____|~~~~|_____|~~~~|_____|~~~~|_____|~~~~|___________________ +// wdata_i Val N |Val N+1 |Val N+2 |Val N+3 |------------------- +// wready_o ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|__________|~~~~~~~~ +// rvalid_o ___________________________________________|~~~~~~~~~~|________ +// rdata_o -------------------------------------------|Val |-------- +// rready_i _________________________________________________|~~~~|________ +// depth_o 0000000000|1111111111|2222222222|3333333333|4444444444|00000000 + + +// Timings - case where InW > OutW +// clk_i __|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__ +// wvalid_i _____|~~~~|____________________________________________________ +// wdata_i -----|Val |---------------------------------------------------- +// wready_o ~~~~~~~~~~|___________________________________________|~~~~~~~~ +// rvalid_o __________|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~|________ +// rdata_o ----------|Val N |Val N+1 |Val N+2 |Val N+3 |-------- +// rready_i ________________|~~~~|_____|~~~~|_____|~~~~|_____|~~~~|________ +// depth_o 0000000000|4444444444|3333333333|2222222222|1111111111|00000000 + + +// Timings - case where InW = OutW +// clk_i __|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__~~|__|~~|__ +// wvalid_i _____|~~~~|____________________________________________________ +// wdata_i -----|Val |---------------------------------------------------- +// wready_o ~~~~~~~~~~|__________|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +// rvalid_o __________|~~~~~~~~~~|_________________________________________ +// rdata_o ----------|Val |----------------------------------------- +// rready_i ________________|~~~~|_________________________________________ +// depth_o 0000000000|1111111111|00000000000000000000000000000000000000000 + + +`include "abr_prim_assert.sv" + +module abr_prim_packer_fifo #( + parameter int InW = 32, + parameter int OutW = 8, + parameter bit ClearOnRead = 1'b1, // if == 1 always output 0 after read + // derived parameters + localparam int MaxW = (InW > OutW) ? InW : OutW, + localparam int MinW = (InW < OutW) ? InW : OutW, + localparam int DepthW = $clog2(MaxW/MinW) +) ( + input logic clk_i , + input logic rst_b, + + input logic clr_i, + input logic wvalid_i, + input logic [InW-1:0] wdata_i, + output logic wready_o, + + output logic rvalid_o, + output logic [OutW-1:0] rdata_o, + input logic rready_i, + output logic [DepthW:0] depth_o +); + + localparam int unsigned WidthRatio = MaxW / MinW; + localparam bit [DepthW:0] FullDepth = WidthRatio[DepthW:0]; + + // signals + logic load_data; + logic clear_data; + logic clear_status; + + // flops + logic [DepthW:0] depth_q, depth_d; + logic [MaxW-1:0] data_q, data_d; + logic clr_q, clr_d; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + depth_q <= '0; + data_q <= '0; + clr_q <= 1'b1; + end else begin + depth_q <= depth_d; + data_q <= data_d; + clr_q <= clr_d; + end + end + + // flop for handling reset case for clr + assign clr_d = clr_i; + + assign depth_o = depth_q; + + if (InW < OutW) begin : gen_pack_mode + logic [MaxW-1:0] wdata_shifted; + + assign wdata_shifted = {{OutW - InW{1'b0}}, wdata_i} << (depth_q*InW); + assign clear_status = (rready_i && rvalid_o) || clr_q; + assign clear_data = (ClearOnRead && clear_status) || clr_q; + assign load_data = wvalid_i && wready_o; + + assign depth_d = clear_status ? '0 : + load_data ? depth_q+1 : + depth_q; + + assign data_d = clear_data ? '0 : + load_data ? (wdata_shifted | (depth_q == 0 ? '0 : data_q)) : + data_q; + + // set outputs + assign wready_o = !(depth_q == FullDepth) && !clr_q; + assign rdata_o = data_q; + assign rvalid_o = (depth_q == FullDepth) && !clr_q; + + end else begin : gen_unpack_mode + logic [MaxW-1:0] rdata_shifted; + logic pull_data; + logic [DepthW:0] ptr_q, ptr_d; + logic [DepthW:0] lsb_is_one; + logic [DepthW:0] max_value; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + ptr_q <= '0; + end else begin + ptr_q <= ptr_d; + end + end + + assign lsb_is_one = {{DepthW{1'b0}},1'b1}; + assign max_value = FullDepth; + assign rdata_shifted = MaxW'(data_q >> ptr_q*OutW); + assign clear_status = (rready_i && (depth_q == lsb_is_one)) || clr_q; + assign clear_data = (ClearOnRead && clear_status) || clr_q; + assign load_data = wvalid_i && wready_o; + assign pull_data = rvalid_o && rready_i; + + assign depth_d = clear_status ? '0 : + load_data ? max_value : + pull_data ? depth_q-1 : + depth_q; + + assign ptr_d = clear_status ? '0 : + pull_data ? ptr_q+1 : + ptr_q; + + assign data_d = clear_data ? '0 : + load_data ? wdata_i : + data_q; + + // set outputs + assign wready_o = (depth_q == '0) && !clr_q; + assign rdata_o = rdata_shifted[OutW-1:0]; + assign rvalid_o = !(depth_q == '0) && !clr_q; + + // Avoid possible lint errors in case InW > OutW. + if (InW > OutW) begin : gen_unused + logic [MaxW-MinW-1:0] unused_rdata_shifted; + assign unused_rdata_shifted = rdata_shifted[MaxW-1:MinW]; + end + end + + + ////////////////////////////////////////////// + // Assertions, Assumptions, and Coverpoints // + ////////////////////////////////////////////// + + // If not acked, valid_o should keep asserting + `ABR_ASSERT(ValidOPairedWithReadyI_A, + rvalid_o && !rready_i && !clr_i |=> rvalid_o) + + // If output port doesn't accept the data, the data should be stable + `ABR_ASSERT(DataOStableWhenPending_A, + ##1 rvalid_o && $past(rvalid_o) + && !$past(rready_i) && !$past(clr_i) |-> $stable(rdata_o)) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..37662eca5d0ea0876395d7739ece64502371f2fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_pkg.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Constants for use in primitives + +// This file is auto-generated. + +package abr_prim_pkg; + + // Implementation target specialization + typedef enum logic [31:0] { + ImplGeneric, + ImplXilinx, + ImplBadbit + } impl_e; +endpackage : abr_prim_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_reg_we_check.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_reg_we_check.sv new file mode 100644 index 0000000000000000000000000000000000000000..1da408c7225704c5628dfae32519cb3b8832aa56 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_reg_we_check.sv @@ -0,0 +1,54 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Spurious write-enable checker for autogenerated CSR node. +// This module has additional simulation features for error injection testing. + +`include "abr_prim_assert.sv" + +module abr_prim_reg_we_check #( + parameter int unsigned OneHotWidth = 32 +) ( + // The module is combinational - the clock and reset are only used for assertions. + input clk_i, + input rst_b, + + input logic [OneHotWidth-1:0] oh_i, + input logic en_i, + + output logic err_o +); + + // Prevent optimization of the onehot input buffer. + logic [OneHotWidth-1:0] oh_buf; + abr_prim_buf #( + .Width(OneHotWidth) + ) u_abr_prim_buf ( + .in_i(oh_i), + .out_o(oh_buf) + ); + + abr_prim_onehot_check #( + .OneHotWidth(OneHotWidth), + .AddrWidth (abr_prim_util_pkg::vbits(OneHotWidth)), + .EnableCheck(1), + // Since certain peripherals may have a very large address space + // (e.g. > 20bit), the inverse address decoding check (which is + // essentially an indexing operation) does not scale well and is + // hence omitted. + .AddrCheck(0), + // Due to REGWEN masking of write enable strobes, + // we do not perform strict checks. I.e., we allow cases + // where en_i is set to 1, but the oh_i vector is all-zeroes. + .StrictCheck(0) + ) u_abr_prim_onehot_check ( + .clk_i, + .rst_b, + .oh_i(oh_buf), + .addr_i('0), + .en_i, + .err_o + ); + +endmodule : abr_prim_reg_we_check diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv new file mode 100644 index 0000000000000000000000000000000000000000..e1f403202df7b6624de5fc508f504eb318074493 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv @@ -0,0 +1,21 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "abr_prim_assert.sv" + +module abr_prim_sec_anchor_buf #( + parameter int Width = 1 +) ( + input [Width-1:0] in_i, + output logic [Width-1:0] out_o +); + + abr_prim_buf #( + .Width(Width) + ) u_secure_anchor_buf ( + .in_i, + .out_o + ); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv new file mode 100644 index 0000000000000000000000000000000000000000..671d05712ab24685d7338b7f0b93b0c4329e6b6d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv @@ -0,0 +1,27 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "abr_prim_assert.sv" + +module abr_prim_sec_anchor_flop #( + parameter int Width = 1, + parameter logic [Width-1:0] ResetValue = 0 +) ( + input clk_i, + input rst_b, + input [Width-1:0] d_i, + output logic [Width-1:0] q_o +); + + abr_prim_flop #( + .Width(Width), + .ResetValue(ResetValue) + ) u_secure_anchor_flop ( + .clk_i, + .rst_b, + .d_i, + .q_o + ); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_slicer.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_slicer.sv new file mode 100644 index 0000000000000000000000000000000000000000..6118c8414d0f7892d8bd5e0ccf043b9fdd575d14 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_slicer.sv @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Slicer chops the incoming bitstring into OutW granularity. +// It supports fractional InW/OutW which fills 0 at the end of message. + +`include "abr_prim_assert.sv" + +module abr_prim_slicer #( + parameter int InW = 64, + parameter int OutW = 8, + + parameter int IndexW = 4 +) ( + input [IndexW-1:0] sel_i, + input [InW-1:0] data_i, + output logic [OutW-1:0] data_o +); + + localparam int UnrollW = OutW*(2**IndexW); + + logic [UnrollW-1:0] unrolled_data; + + assign unrolled_data = UnrollW'(data_i); + + assign data_o = unrolled_data[sel_i*OutW+:OutW]; + + `ABR_ASSERT_INIT(ValidWidth_A, InW <= OutW*(2**IndexW)) + +endmodule + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv new file mode 100644 index 0000000000000000000000000000000000000000..49ca9ee16dfb4eadda3bf1d2482cef2d30a7d464 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv @@ -0,0 +1,69 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "abr_prim_assert.sv" + +module abr_prim_sparse_fsm_flop + import abr_prim_sparse_fsm_pkg::*; +#( + parameter int Width = 1, + parameter type StateEnumT = state_t, + parameter logic [Width-1:0] ResetValue = '0, + // This should only be disabled in special circumstances, for example + // in non-comportable IPs where an error does not trigger an alert. + parameter bit EnableAlertTriggerSVA = 1 +`ifdef ABR_SIMULATION + , + // In case this parameter is set to a non-empty string, the + // abr_prim_sparse_fsm_flop_if will also force the signal with this name + // in the parent module that instantiates abr_prim_sparse_fsm_flop. + parameter string CustomForceName = "" +`endif +) ( + input clk_i, + input rst_b, + input StateEnumT state_i, + output StateEnumT state_o +); + + logic unused_err_o; + + logic [Width-1:0] state_raw; + abr_prim_flop #( + .Width(Width), + .ResetValue(ResetValue) + ) u_state_flop ( + .clk_i, + .rst_b, + .d_i(state_i), + .q_o(state_raw) + ); + assign state_o = StateEnumT'(state_raw); + + `ifdef ABR_INC_ASSERT + assign unused_err_o = is_undefined_state(state_o); + + function automatic logic is_undefined_state(StateEnumT sig); + // This is written with a vector in order to make it amenable to x-prop analysis. + logic is_defined = 1'b0; + for (int i = 0, StateEnumT t = t.first(); i < t.num(); i += 1, t = t.next()) begin + is_defined |= (sig === t); + end + return ~is_defined; + endfunction + + `else + assign unused_err_o = 1'b0; + `endif + + // If ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT is declared, the unused_assert_connected signal will + // be set to 1 and the below check will pass. + // If the assertion is not declared however, the statement below will fail. + `ifdef ABR_INC_ASSERT + logic unused_assert_connected; + + `ABR_ASSERT_INIT_NET(AssertConnected_A, unused_assert_connected === 1'b1 || !EnableAlertTriggerSVA) + `endif + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..d6ebcd9e8a504ad2ed6f25de08030b22c302c945 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv @@ -0,0 +1,7 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package abr_prim_sparse_fsm_pkg; + typedef enum logic {Idle, Done} state_t; +endpackage : abr_prim_sparse_fsm_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg.sv new file mode 100644 index 0000000000000000000000000000000000000000..f58dff8f691b6cdc4e88ad2fc0c9b3dc8d5218ab --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg.sv @@ -0,0 +1,66 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register slice conforming to Comportibility guide. + +module abr_prim_subreg + import abr_prim_subreg_pkg::*; +#( + parameter int DW = 32, + parameter sw_access_e SwAccess = SwAccessRW, + parameter logic [DW-1:0] RESVAL = '0 // reset value +) ( + input clk_i, + input rst_b, + + // From SW: valid for RW, WO, W1C, W1S, W0C, RC + // In case of RC, Top connects Read Pulse to we + input we, + input [DW-1:0] wd, + + // From HW: valid for HRW, HWO + input de, + input [DW-1:0] d, + + // output to HW and Reg Read + output logic qe, + output logic [DW-1:0] q, + + // ds and qs have slightly different timing. + // ds is the data that will be written into the flop, + // while qs is the current flop value exposed to software. + output logic [DW-1:0] ds, + output logic [DW-1:0] qs +); + + logic wr_en; + logic [DW-1:0] wr_data; + + abr_prim_subreg_arb #( + .DW ( DW ), + .SwAccess ( SwAccess ) + ) wr_en_data_arb ( + .we, + .wd, + .de, + .d, + .q, + .wr_en, + .wr_data + ); + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + q <= RESVAL; + end else if (wr_en) begin + q <= wr_data; + end + end + + // feed back out for consolidation + assign ds = wr_en ? wr_data : qs; + assign qe = wr_en; + assign qs = q; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_arb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_arb.sv new file mode 100644 index 0000000000000000000000000000000000000000..5f0cac3cc2baf414af8db53dd3d2695453b0d76b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_arb.sv @@ -0,0 +1,81 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Write enable and data arbitration logic for register slice conforming to Comportibility guide. + +module abr_prim_subreg_arb + import abr_prim_subreg_pkg::*; +#( + parameter int DW = 32, + parameter sw_access_e SwAccess = SwAccessRW +) ( + // From SW: valid for RW, WO, W1C, W1S, W0C, RC. + // In case of RC, top connects read pulse to we. + input we, + input [DW-1:0] wd, + + // From HW: valid for HRW, HWO. + input de, + input [DW-1:0] d, + + // From register: actual reg value. + input [DW-1:0] q, + + // To register: actual write enable and write data. + output logic wr_en, + output logic [DW-1:0] wr_data +); + + if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w + assign wr_en = we | de; + assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority + // Unused q - Prevent lint errors. + logic [DW-1:0] unused_q; + assign unused_q = q; + end else if (SwAccess == SwAccessRO) begin : gen_ro + assign wr_en = de; + assign wr_data = d; + // Unused we, wd, q - Prevent lint errors. + logic unused_we; + logic [DW-1:0] unused_wd; + logic [DW-1:0] unused_q; + assign unused_we = we; + assign unused_wd = wd; + assign unused_q = q; + end else if (SwAccess == SwAccessW1S) begin : gen_w1s + // If SwAccess is W1S, then assume hw tries to clear. + // So, give a chance HW to clear when SW tries to set. + // If both try to set/clr at the same bit pos, SW wins. + assign wr_en = we | de; + assign wr_data = (de ? d : q) | (we ? wd : '0); + end else if (SwAccess == SwAccessW1C) begin : gen_w1c + // If SwAccess is W1C, then assume hw tries to set. + // So, give a chance HW to set when SW tries to clear. + // If both try to set/clr at the same bit pos, SW wins. + assign wr_en = we | de; + assign wr_data = (de ? d : q) & (we ? ~wd : '1); + end else if (SwAccess == SwAccessW0C) begin : gen_w0c + assign wr_en = we | de; + assign wr_data = (de ? d : q) & (we ? wd : '1); + end else if (SwAccess == SwAccessRC) begin : gen_rc + // This swtype is not recommended but exists for compatibility. + // WARN: we signal is actually read signal not write enable. + assign wr_en = we | de; + assign wr_data = (de ? d : q) & (we ? '0 : '1); + // Unused wd - Prevent lint errors. + logic [DW-1:0] unused_wd; + assign unused_wd = wd; + end else begin : gen_hw + assign wr_en = de; + assign wr_data = d; + // Unused we, wd, q - Prevent lint errors. + logic unused_we; + logic [DW-1:0] unused_wd; + logic [DW-1:0] unused_q; + assign unused_we = we; + assign unused_wd = wd; + assign unused_q = q; + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_ext.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_ext.sv new file mode 100644 index 0000000000000000000000000000000000000000..dd40a4472e891aa94ffccd99bcdcc0f9bc1fb629 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_ext.sv @@ -0,0 +1,32 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register slice conforming to Comportibility guide. + +module abr_prim_subreg_ext #( + parameter int unsigned DW = 32 +) ( + input re, + input we, + input [DW-1:0] wd, + + input [DW-1:0] d, + + // output to HW and Reg Read + output logic qe, + output logic qre, + output logic [DW-1:0] q, + output logic [DW-1:0] ds, + output logic [DW-1:0] qs +); + + // for external registers, there is no difference + // between qs and ds + assign ds = d; + assign qs = d; + assign q = wd; + assign qe = we; + assign qre = re; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..c42a07bab980b6bd62913a4e46aa00b4416f5045 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_subreg_pkg.sv @@ -0,0 +1,17 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +package abr_prim_subreg_pkg; + + // Register access specifier + typedef enum logic [2:0] { + SwAccessRW = 3'd0, // Read-write + SwAccessRO = 3'd1, // Read-only + SwAccessWO = 3'd2, // Write-only + SwAccessW1C = 3'd3, // Write 1 to clear + SwAccessW1S = 3'd4, // Write 1 to set + SwAccessW0C = 3'd5, // Write 0 to clear + SwAccessRC = 3'd6 // Read to clear. Do not use, only exists for compatibility. + } sw_access_e; +endpackage diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sum_tree.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sum_tree.sv new file mode 100644 index 0000000000000000000000000000000000000000..f4c5225f0e80c084eed43514f955701510aa1e58 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_sum_tree.sv @@ -0,0 +1,124 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Based on abr_prim_max_tree, this module implements an explicit binary tree to find the +// sum of this inputs. The solution has O(N) area and O(log(N)) delay complexity, and +// thus scales well with many input sources. +// +// Note that only input values marked as "valid" are respected in the maximum computation. +// Invalid values are treated as 0. +// + +`include "abr_prim_assert.sv" + +module abr_prim_sum_tree #( + parameter int NumSrc = 32, + parameter int Width = 8 +) ( + // The module is combinational - the clock and reset are only used for assertions. + input clk_i, + input rst_b, + input [NumSrc-1:0][Width-1:0] values_i, // Input values + input [NumSrc-1:0] valid_i, // Input valid bits + output logic [Width-1:0] sum_value_o, // Summation result + output logic sum_valid_o // Whether any of the inputs is valid +); + + /////////////////////// + // Binary tree logic // + /////////////////////// + + // This only works with 2 or more sources. + `ABR_ASSERT_INIT(NumSources_A, NumSrc >= 2) + + // Align to powers of 2 for simplicity. + // A full binary tree with N levels has 2**N + 2**N-1 nodes. + localparam int NumLevels = $clog2(NumSrc); + logic [2**(NumLevels+1)-2:0] vld_tree; + logic [2**(NumLevels+1)-2:0][Width-1:0] sum_tree; + + for (genvar level = 0; level < NumLevels+1; level++) begin : gen_tree + // + // level+1 C0 C1 <- "Base1" points to the first node on "level+1", + // \ / these nodes are the children of the nodes one level below + // level Pa <- "Base0", points to the first node on "level", + // these nodes are the parents of the nodes one level above + // + // hence we have the following indices for the paPa, C0, C1 nodes: + // Pa = 2**level - 1 + offset = Base0 + offset + // C0 = 2**(level+1) - 1 + 2*offset = Base1 + 2*offset + // C1 = 2**(level+1) - 1 + 2*offset + 1 = Base1 + 2*offset + 1 + // + localparam int Base0 = (2**level)-1; + localparam int Base1 = (2**(level+1))-1; + + for (genvar offset = 0; offset < 2**level; offset++) begin : gen_level + localparam int Pa = Base0 + offset; + localparam int C0 = Base1 + 2*offset; + localparam int C1 = Base1 + 2*offset + 1; + + // This assigns the input values, their corresponding IDs and valid signals to the tree leafs. + if (level == NumLevels) begin : gen_leafs + if (offset < NumSrc) begin : gen_assign + assign vld_tree[Pa] = valid_i[offset]; + assign sum_tree[Pa] = values_i[offset]; + end else begin : gen_tie_off + assign vld_tree[Pa] = '0; + assign sum_tree[Pa] = '0; + end + // This creates the node assignments. + end else begin : gen_nodes + logic [Width-1:0] node_sum; // Local helper variable + // In case only one of the parents is valid, forward that one + // In case both parents are valid, forward the one with higher value + assign node_sum = (vld_tree[C0] & vld_tree[C1]) ? sum_tree[C1] + sum_tree[C0] : + (vld_tree[C0]) ? sum_tree[C0] : + (vld_tree[C1]) ? sum_tree[C1] : + {Width'(0)}; + + // Forwarding muxes + // Note: these ternaries have triggered a synthesis bug in Vivado versions older + // than 2020.2. If the problem resurfaces again, have a look at issue #1408. + assign vld_tree[Pa] = vld_tree[C1] | vld_tree[C0]; + assign sum_tree[Pa] = node_sum; + end + end : gen_level + end : gen_tree + + + // The results can be found at the tree root + assign sum_valid_o = vld_tree[0]; + assign sum_value_o = sum_tree[0]; + + //////////////// + // Assertions // + //////////////// + +`ifdef ABR_INC_ASSERT + //VCS coverage off + // pragma coverage off + + // Helper functions for assertions below. + function automatic logic [Width-1:0] sum_value (input logic [NumSrc-1:0][Width-1:0] values_i, + input logic [NumSrc-1:0] valid_i); + logic [Width-1:0] sum = '0; + for (int k = 0; k < NumSrc; k++) begin + if (valid_i[k]) begin + sum += values_i[k]; + end + end + return sum; + endfunction : sum_value + + logic [Width-1:0] sum_value_exp; + assign sum_value_exp = sum_value(values_i, valid_i); + //VCS coverage on + // pragma coverage on + + `ABR_ASSERT(ValidInImpliesValidOut_A, |valid_i === sum_valid_o) + `ABR_ASSERT(SumComputation_A, sum_valid_o |-> sum_value_o == sum_value_exp) + `ABR_ASSERT(SumComputationInvalid_A, !sum_valid_o |-> sum_value_o == '0) +`endif + +endmodule : abr_prim_sum_tree diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_util_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_util_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..bd6ea99ed56d941c21e27b6552214135f6e9c547 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim/rtl/abr_prim_util_pkg.sv @@ -0,0 +1,100 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + + +/** + * Utility functions + */ +package abr_prim_util_pkg; + /** + * Math function: $clog2 as specified in Verilog-2005 + * + * Do not use this function if $clog2() is available. + * + * clog2 = 0 for value == 0 + * ceil(log2(value)) for value >= 1 + * + * This implementation is a synthesizable variant of the $clog2 function as + * specified in the Verilog-2005 standard (IEEE 1364-2005). + * + * To quote the standard: + * The system function $clog2 shall return the ceiling of the log + * base 2 of the argument (the log rounded up to an integer + * value). The argument can be an integer or an arbitrary sized + * vector value. The argument shall be treated as an unsigned + * value, and an argument value of 0 shall produce a result of 0. + */ + + //Function causing LINT errors. Not used in current codebase + //deprecated and replaced by $clog2() //function automatic integer _clog2(integer value); + //deprecated and replaced by $clog2() // integer result; + //deprecated and replaced by $clog2() // Use an intermediate value to avoid assigning to an input port, which produces a warning in + //deprecated and replaced by $clog2() // Synopsys DC. + //deprecated and replaced by $clog2() // integer v = value; + //deprecated and replaced by $clog2() // v = v - 1; + //deprecated and replaced by $clog2() // for (result = 0; v > 0; result++) begin + //deprecated and replaced by $clog2() // v = v >> 1; + //deprecated and replaced by $clog2() // end + //deprecated and replaced by $clog2() // return result; + //deprecated and replaced by $clog2() //endfunction + + + /** + * Math function: Number of bits needed to address |value| items. + * + * 0 for value == 0 + * vbits = 1 for value == 1 + * ceil(log2(value)) for value > 1 + * + * + * The primary use case for this function is the definition of registers/arrays + * which are wide enough to contain |value| items. + * + * This function identical to $clog2() for all input values except the value 1; + * it could be considered an "enhanced" $clog2() function. + * + * + * Example 1: + * parameter Items = 1; + * localparam ItemsWidth = vbits(Items); // 1 + * logic [ItemsWidth-1:0] item_register; // items_register is now [0:0] + * + * Example 2: + * parameter Items = 64; + * localparam ItemsWidth = vbits(Items); // 6 + * logic [ItemsWidth-1:0] item_register; // items_register is now [5:0] + * + * Note: If you want to store the number "value" inside a register, you need + * a register with size vbits(value + 1), since you also need to store + * the number 0. + * + * Example 3: + * logic [vbits(64)-1:0] store_64_logic_values; // width is [5:0] + * logic [vbits(64 + 1)-1:0] store_number_64; // width is [6:0] + */ + function automatic integer vbits(integer value); +`ifdef XCELIUM + // The use of system functions was not allowed here in Verilog-2001, but is + // valid since (System)Verilog-2005, which is also when $clog2() first + // appeared. + // Xcelium < 19.10 does not yet support the use of $clog2() here, fall back + // to an implementation without a system function. Remove this workaround + // if we require a newer Xcelium version. + // See #2579 and #2597. + return (value == 1) ? 1 : _clog2(value); +`else + return (value == 1) ? 1 : $clog2(value); +`endif + endfunction + +`ifdef ABR_INC_ASSERT + // Package-scoped variable to detect the end of simulation. + // + // Used only in DV simulations. The bit will be used by assertions in RTL to perform end-of-test + // cleanup. It is set to 1 in `dv_test_status_pkg::dv_test_status()`, which is invoked right + // before the simulation is terminated, to signal the status of the test. + bit end_of_simulation; +`endif + +endpackage diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/config/abr_prim_generic.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/config/abr_prim_generic.vf new file mode 100644 index 0000000000000000000000000000000000000000..239061664f9cdae38555d190cbef482630a1a551 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/config/abr_prim_generic.vf @@ -0,0 +1,4 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..f11c2be34416796e7ad311b817f32500eef70c66 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/config/compile.yml @@ -0,0 +1,10 @@ +--- +provides: [abr_prim_generic] +schema_version: 2.4.0 +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_prim_generic_flop_en.sv + - $COMPILE_ROOT/rtl/abr_prim_generic_flop.sv + - $COMPILE_ROOT/rtl/abr_prim_generic_buf.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv new file mode 100644 index 0000000000000000000000000000000000000000..c611138198d0f18d4ad4f8fb4a6cf6ff5fb3ceca --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv @@ -0,0 +1,18 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "abr_prim_assert.sv" + +module abr_prim_generic_buf #( + parameter int Width = 1 +) ( + input [Width-1:0] in_i, + output logic [Width-1:0] out_o +); + + logic [Width-1:0] inv; + assign inv = ~in_i; + assign out_o = ~inv; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv new file mode 100644 index 0000000000000000000000000000000000000000..1c05820ddaa12c71d1e14971a25986810240a658 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv @@ -0,0 +1,25 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "abr_prim_assert.sv" + +module abr_prim_generic_flop #( + parameter int Width = 1, + parameter logic [Width-1:0] ResetValue = 0 +) ( + input clk_i, + input rst_b, + input [Width-1:0] d_i, + output logic [Width-1:0] q_o +); + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + q_o <= ResetValue; + end else begin + q_o <= d_i; + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv new file mode 100644 index 0000000000000000000000000000000000000000..a4f711e343f0e7073f47404e7fdd46b25baa46e4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv @@ -0,0 +1,39 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +`include "abr_prim_assert.sv" + +module abr_prim_generic_flop_en #( + parameter int Width = 1, + parameter bit EnSecBuf = 0, + parameter logic [Width-1:0] ResetValue = 0 +) ( + input clk_i, + input rst_b, + input en_i, + input [Width-1:0] d_i, + output logic [Width-1:0] q_o +); + + logic en; + if (EnSecBuf) begin : gen_en_sec_buf + abr_prim_sec_anchor_buf #( + .Width(1) + ) u_en_buf ( + .in_i(en_i), + .out_o(en) + ); + end else begin : gen_en_no_sec_buf + assign en = en_i; + end + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + q_o <= ResetValue; + end else if (en) begin + q_o <= d_i; + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3.vf new file mode 100644 index 0000000000000000000000000000000000000000..d1472dc152937f89d2c71d11d5108ac72363407c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3.vf @@ -0,0 +1,80 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..3c992cb974205ee6410cd4a80d9a1c18cc037447 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..2a514a82301645455790c209222852f3288b1029 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/abr_sha3_tb.vf @@ -0,0 +1,85 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb/abr_sha3_tb_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb/abr_sha3_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..db832f92258cb3bc19713e2cd9f652dc282f1ada --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/config/compile.yml @@ -0,0 +1,49 @@ +--- +provides: [abr_sha3_pkg] +schema_version: 2.4.0 +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_sha3_pkg.sv +--- +provides: [abr_sha3] +schema_version: 2.4.0 +requires: + - abr_sha3_pkg + - abr_libs + - abr_prim + - mldsa_defines +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/abr_keccak_round.sv + - $COMPILE_ROOT/rtl/abr_keccak_2share.sv + - $COMPILE_ROOT/rtl/abr_sha3pad.sv + - $COMPILE_ROOT/rtl/abr_sha3.sv + tops: [abr_sha3] + rtl_lint: + directories: [] +--- +provides: [abr_sha3_tb] +schema_version: 2.4.0 +requires: + - mldsa_sampler_pkg + - abr_sha3 +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/abr_sha3_tb_pkg.sv + - $COMPILE_ROOT/tb/abr_sha3_tb.sv + tops: [abr_sha3_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying SHA3 vector generator to ${pwd}" && cp $COMPILE_ROOT/tb/sha3.py .' +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+ABR_ASSERT_ON + - '-noinherit_timescale=1ns/1ps' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_keccak_2share.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_keccak_2share.sv new file mode 100644 index 0000000000000000000000000000000000000000..59af71fae073c956ddbb5568585a97f16db6e326 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_keccak_2share.sv @@ -0,0 +1,636 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// This module is the single round keccak permutation module +// It supports Keccak with up to 1600b of state + +`include "abr_sva.svh" +`include "abr_prim_assert.sv" + +module abr_keccak_2share + import abr_prim_mubi_pkg::*; +#( + parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} + + // Derived + localparam int W = Width/25, + localparam int L = $clog2(W), + localparam int MaxRound = 12 + 2*L, // Keccak-f only + localparam int RndW = $clog2(MaxRound+1), // Representing up to MaxRound + + // Control parameters + parameter bit EnMasking = 0, // Enable secure hardening + localparam int Share = EnMasking ? 2 : 1 +) ( + input clk_i, + input rst_b, + + input [RndW-1:0] rnd_i, // Current round index + input mubi4_t phase_sel_i, // Output mux contol. Used when EnMasking := 1 + input [1:0] cycle_i, // Current cycle index. Used when EnMasking := 1 + input rand_aux_i, // Auxiliary randomness input. Used when EnMasking := 1 + input [Width/2-1:0] rand_i, // Randomness for remasking. Used when EnMasking := 1 + input [Width-1:0] s_i [Share], + output logic [Width-1:0] s_o [Share] +); + /////////// + // Types // + /////////// + // x y z + typedef logic [4:0][4:0][W-1:0] box_t; // (x,y,z) state + typedef logic [W-1:0] lane_t; // (z) + typedef logic [4:0] [W-1:0] plane_t; // (x,z) + typedef logic [4:0][4:0] slice_t; // (x,y) + typedef logic [4:0][W-1:0] sheet_t; // (y,z) identical to plane_t + typedef logic [4:0] row_t; // (x) + typedef logic [4:0] col_t; // (y) identical to row_t + + ////////////// + // Keccak_f // + ////////////// + box_t state_in [Share]; + box_t state_out [Share]; + box_t theta_data [Share]; + box_t rho_data [Share]; + box_t pi_data [Share]; + box_t chi_data [Share]; + box_t iota_data [Share]; + + box_t phase1_in [Share]; + box_t phase1_out [Share]; + box_t phase2_in [Share]; + box_t phase2_out [Share]; + + ///////////////// + // Unused nets // + ///////////////// + // Tie off input signals that aren't used in the unmasked implementation. + if (!EnMasking) begin : gen_tie_unused + logic unused_clk; + logic unused_rst_n; + mubi4_t unused_phase_sel; + logic [1:0] unused_cycle; + logic unused_rand_aux; + logic [Width/2-1:0] unused_rand; + assign unused_clk = clk_i; + assign unused_rst_n = rst_b; + assign unused_phase_sel = phase_sel_i; + assign unused_cycle = cycle_i; + assign unused_rand_aux = rand_aux_i; + assign unused_rand = rand_i; + end + + ////////////////////////////////////////////////// + // Input/output type conversion and interfacing // + ////////////////////////////////////////////////// + for (genvar i = 0 ; i < Share ; i++) begin : g_state_inout + assign state_in[i] = bitarray_to_box(s_i[i]); + assign s_o[i] = box_to_bitarray(state_out[i]); + end : g_state_inout + + if (EnMasking) begin : g_2share_data + assign phase1_in = state_in; + assign phase2_in = state_in; + + always_comb begin + unique case (phase_sel_i) + MuBi4False: state_out = phase1_out; + MuBi4True: state_out = phase2_out; + default: state_out = phase1_out; + endcase + end + end else begin : g_single_data + assign phase1_in = state_in; + assign phase2_in = phase1_out; + assign state_out = phase2_out; + end + + ////////////// + // Datapath // + ////////////// + // This module has two phases. First phase, it calculates Theta, Rho, Pi steps + // in SHA3. At the second phase, it computes Chi and Iota steps. If masking is + // not enabled, the two phases are completed within a single clock cycle. + // + // If masking is enabled, the first phase (Phase1) completes in one cycle. + // Then, the output should be stored in the state and given to the input of + // this module again. The second phase in the masked version needs three + // clock cycles to complete. In the first clock cycle, the first stage of Chi + // is computed for the first lane halves. In the second clock cycle, the + // module then outputs the updated first lane halves. In the third clock + // cycle, the new second lane halves are output. To aggravate SCA, we + // randomly decide which lane halves to process first on a per-round basis. + // We use additional randomness generated by the PRNG to take this decision + // (rand_aux_i). For more details, refer to the comments in the "MUX control" + // section below. + + for (genvar i = 0 ; i < Share ; i++) begin : g_datapath + + // Phase 1: + assign theta_data[i] = theta(phase1_in[i]); + // Commented out rho function as vcs complains z-Offset%W isn't constant + // assign rho_data[i] = rho(theta_data[i]); + + assign pi_data[i] = pi(rho_data[i]); + + // Phase 2 (Cycles 1, 2 and 3): + // Chi : See below + // Iota: See below + end : g_datapath + + assign phase1_out = pi_data; + + // Iota adds Round Constants(RC), so only one share should be XORed + if (EnMasking) begin : g_2share_iota + assign iota_data[0] = iota(chi_data[0], rnd_i); + assign iota_data[1] = chi_data[1]; + end else begin : g_single_iota + assign iota_data[0] = iota(chi_data[0], rnd_i); + end + + if (EnMasking) begin : g_2share_chi + // Domain-Oriented Masking + // reference: https://eprint.iacr.org/2017/395.pdf + + localparam int unsigned WSheetHalf = $bits(sheet_t)/2; + logic [4:0][WSheetHalf-1:0] in_prd, out_prd; + + logic low_then_high_d, low_then_high_q; + logic in_data_low, out_data_low; + logic in_rand_ext; + logic update_dom; + + ///////////////// + // MUX control // + ///////////////// + + // Update lane-half processing order in Phase 1 and keep the value constant + // for the entire round. + assign low_then_high_d = + mubi4_test_false_strict(phase_sel_i) ? rand_aux_i : low_then_high_q; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + low_then_high_q <= 1'b 0; + end else begin + low_then_high_q <= low_then_high_d; + end + end + + // This implementation uses both randomness provided from an external PRNG + // as well as intermediate results for remasking the DOM multipliers below. + // Per clock cycle, 800b of pseudo-random data (PRD) are required. The + // following schedule is used to only ever update the input data when also + // providing fresh randomness and vice versa. + // + // Cycle 0: Compute Theta, Rho, Pi - The DOM multipliers are not evaluated + // at all: the inputs are driven by the first lane halves (same + // values as in Cycle 3). Also the intermediate results we already + // had in Cycle 3 didn't change. + // Cycle 1: Compute first stage of Chi for first lane halves using the DOM + // multipliers. We use the fresh randomness provided from the + // PRNG for remasking. + // Cycle 2: Compute second stage of Chi and Iota for first lane halves. + // Compute first stage of Chi for second lane halves. We use the + // fresh randomness provided from the PRNG for remasking the + // DOM multipliers. + // Cycle 3: Compute second stage of Chi and Iota for second lane halves. + // Feed again first lane halves to DOM multiplier inputs (now + // the updated values become visible) together with intermediate + // results of Cycle 2. Don't update the register stage inside + // the DOM multipliers. + always_comb begin + unique case (cycle_i) + 2'h0: begin + in_data_low = low_then_high_q; + in_rand_ext = 1'b0; + update_dom = 1'b0; + end + 2'h1: begin + in_data_low = low_then_high_q; + in_rand_ext = 1'b1; + update_dom = 1'b1; + end + 2'h2: begin + in_data_low = ~low_then_high_q; + in_rand_ext = 1'b1; + update_dom = 1'b1; + end + 2'h3: begin + in_data_low = low_then_high_q; + in_rand_ext = 1'b0; + update_dom = 1'b0; + end + default: begin + in_data_low = low_then_high_q; + in_rand_ext = 1'b0; + update_dom = 1'b0; + end + endcase + end + + // When taking the lower lane halves in, the upper lane halves are output + // and vice versa. + assign out_data_low = ~in_data_low; + + ///////////////////// + // DOM multipliers // + ///////////////////// + + for (genvar x = 0 ; x < 5 ; x++) begin : g_chi_w + localparam int X1 = (x + 1) % 5; + localparam int X2 = (x + 2) % 5; + + sheet_t sheet0[Share]; // Inverted input X1 + sheet_t sheet1[Share]; // X2 + sheet_t sheet2[Share]; // DOM output + + assign sheet0[0] = ~phase2_in[0][X1]; + assign sheet0[1] = phase2_in[1][X1]; + + assign sheet1[0] = phase2_in[0][X2]; + assign sheet1[1] = phase2_in[1][X2]; + + // Convert sheet_t to 1D arrays, one for the upper and lower half lane. + logic [WSheetHalf-1:0] a0_l, a1_l, b0_l, b1_l; + logic [WSheetHalf-1:0] a0_h, a1_h, b0_h, b1_h; + logic [WSheetHalf-1:0] a0, a1, b0, b1, q0, q1; + + assign a0_l = {sheet0[0][0][W/2-1:0], + sheet0[0][1][W/2-1:0], + sheet0[0][2][W/2-1:0], + sheet0[0][3][W/2-1:0], + sheet0[0][4][W/2-1:0]}; + assign a1_l = {sheet0[1][0][W/2-1:0], + sheet0[1][1][W/2-1:0], + sheet0[1][2][W/2-1:0], + sheet0[1][3][W/2-1:0], + sheet0[1][4][W/2-1:0]}; + + assign a0_h = {sheet0[0][0][W-1:W/2], + sheet0[0][1][W-1:W/2], + sheet0[0][2][W-1:W/2], + sheet0[0][3][W-1:W/2], + sheet0[0][4][W-1:W/2]}; + assign a1_h = {sheet0[1][0][W-1:W/2], + sheet0[1][1][W-1:W/2], + sheet0[1][2][W-1:W/2], + sheet0[1][3][W-1:W/2], + sheet0[1][4][W-1:W/2]}; + + assign b0_l = {sheet1[0][0][W/2-1:0], + sheet1[0][1][W/2-1:0], + sheet1[0][2][W/2-1:0], + sheet1[0][3][W/2-1:0], + sheet1[0][4][W/2-1:0]}; + assign b1_l = {sheet1[1][0][W/2-1:0], + sheet1[1][1][W/2-1:0], + sheet1[1][2][W/2-1:0], + sheet1[1][3][W/2-1:0], + sheet1[1][4][W/2-1:0]}; + + assign b0_h = {sheet1[0][0][W-1:W/2], + sheet1[0][1][W-1:W/2], + sheet1[0][2][W-1:W/2], + sheet1[0][3][W-1:W/2], + sheet1[0][4][W-1:W/2]}; + assign b1_h = {sheet1[1][0][W-1:W/2], + sheet1[1][1][W-1:W/2], + sheet1[1][2][W-1:W/2], + sheet1[1][3][W-1:W/2], + sheet1[1][4][W-1:W/2]}; + + // Input muxing + assign a0 = in_data_low ? a0_l : a0_h; + assign a1 = in_data_low ? a1_l : a1_h; + assign b0 = in_data_low ? b0_l : b0_h; + assign b1 = in_data_low ? b1_l : b1_h; + + // Randomness muxing + // Intermediate results are rotated across rows. The new Row x depends on + // data from Rows x + 1 and x + 2. Hence we don't want to use intermediate + // results from Rows x, x + 1, and x + 2 for remasking. + assign in_prd[x] = in_rand_ext ? rand_i[x * WSheetHalf +: WSheetHalf] : + out_prd[rot_int(x, 5)]; + + abr_prim_dom_and_2share #( + .DW (WSheetHalf), // a half sheet + .Pipeline(1) // Process the full sheet in 3 clock cycles. This reduces + // SCA leakage. + ) u_dom ( + .clk_i, + .rst_b, + + .a0_i (a0), + .a1_i (a1), + .b0_i (b0), + .b1_i (b1), + .z_valid_i (update_dom), + .z_i (in_prd[x]), + .q0_o (q0), + .q1_o (q1), + .prd_o (out_prd[x]) + ); + + // Output conversion from q0, q1 to sheet_t + // For simplicity, we forward the generated lane half to both the upper + // and lower lane halves at this point. The actual output muxing/selection + // happens after the Iota step when generating phase2_out from iota_data + // and state_in below. + assign sheet2[0][4] = {2{q0[W/2*0+:W/2]}}; + assign sheet2[0][3] = {2{q0[W/2*1+:W/2]}}; + assign sheet2[0][2] = {2{q0[W/2*2+:W/2]}}; + assign sheet2[0][1] = {2{q0[W/2*3+:W/2]}}; + assign sheet2[0][0] = {2{q0[W/2*4+:W/2]}}; + + assign sheet2[1][4] = {2{q1[W/2*0+:W/2]}}; + assign sheet2[1][3] = {2{q1[W/2*1+:W/2]}}; + assign sheet2[1][2] = {2{q1[W/2*2+:W/2]}}; + assign sheet2[1][1] = {2{q1[W/2*3+:W/2]}}; + assign sheet2[1][0] = {2{q1[W/2*4+:W/2]}}; + + // Final XOR to generate the output + assign chi_data[0][x] = sheet2[0] ^ phase2_in[0][x]; + assign chi_data[1][x] = sheet2[1] ^ phase2_in[1][x]; + end : g_chi_w + + // Since Chi and thus Iota are separately applied to the lower and upper half + // lanes, we need to forward the input to the other half. + for (genvar x = 0 ; x < 5 ; x++) begin : g_2share_phase2_out_row + for (genvar y = 0 ; y < 5 ; y++) begin : g_2share_phase2_out_col + assign phase2_out[0][x][y] = out_data_low ? + { state_in[0][x][y][W-1:W/2], iota_data[0][x][y][W/2-1:0]} : + {iota_data[0][x][y][W-1:W/2], state_in[0][x][y][W/2-1:0]}; + assign phase2_out[1][x][y] = out_data_low ? + { state_in[1][x][y][W-1:W/2], iota_data[1][x][y][W/2-1:0]} : + {iota_data[1][x][y][W-1:W/2], state_in[1][x][y][W/2-1:0]}; + end + end + + end else begin : g_single_chi + assign chi_data[0] = chi(phase2_in[0]); + assign phase2_out = iota_data; + end + + // Rho ====================================================================== + // As RhoOffset[x][y] is considered as variable int in VCS, + // it is replaced with generate statement. + // Revised to meet verilator lint. Now RhoOffset is 1-D array + localparam int RhoOffset [25] = '{ + //y 0 1 2 3 4 x + 0, 36, 3, 105, 210, // 0: 0 1 2 3 4 + 1, 300, 10, 45, 66, // 1: 5 6 7 8 9 + 190, 6, 171, 15, 253, // 2: 10 11 12 13 14 + 28, 55, 153, 21, 120, // 3: 15 16 17 18 19 + 91, 276, 231, 136, 78 // 4: 20 21 22 23 24 + }; + for (genvar i = 0 ; i < Share ; i++) begin : g_rho + box_t rho_in, rho_out; + assign rho_in = theta_data[i]; + assign rho_data[i] = rho_out; + + for (genvar x = 0 ; x < 5 ; x++) begin : gen_rho_x + for (genvar y = 0 ; y < 5 ; y++) begin : gen_rho_y + localparam int Offset = RhoOffset[5*x+y]%W; + localparam int ShiftAmt = W- Offset; + if (Offset == 0) begin : gen_offset0 + assign rho_out[x][y][W-1:0] = rho_in[x][y][W-1:0]; + end else begin : gen_others + assign rho_out[x][y][W-1:0] = {rho_in[x][y][0+:ShiftAmt], + rho_in[x][y][ShiftAmt+:Offset]}; + end + end + end + end : g_rho + + //////////////// + // Assertions // + //////////////// + + `ABR_ASSERT_INIT(ValidWidth_A, + EnMasking == 0 && Width inside {25, 50, 100, 200, 400, 800, 1600} || + EnMasking == 1 && Width inside {50, 100, 200, 400, 800, 1600}) + `ABR_ASSERT_INIT(ValidW_A, W inside {1, 2, 4, 8, 16, 32, 64}) + `ABR_ASSERT_INIT(ValidL_A, L inside {0, 1, 2, 3, 4, 5, 6}) + `ABR_ASSERT_INIT(ValidRound_A, MaxRound <= 24) // Keccak-f only + + // phase_sel_i shall stay for two cycle after change to 1. + if (EnMasking) begin : gen_selperiod_chk + `ABR_ASSUME(SelStayTwoCycleIfTrue_A, + ($past(phase_sel_i) == MuBi4False) && (phase_sel_i == MuBi4True) + |=> phase_sel_i == MuBi4True, clk_i, !rst_b) + end + + /////////////// + // Functions // + /////////////// + + // Convert bitarray to 3D box + // Please take a look at FIPS PUB 202 + // https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.202.pdf + // > For all triples (x,y,z) such that 0<=x<5, 0<=y<5, and 0<=z A[x,y,z]=S[w(5y+x)+z] + function automatic box_t bitarray_to_box(logic [Width-1:0] s_in); + automatic box_t box; + for (int y = 0 ; y < 5 ; y++) begin + for (int x = 0 ; x < 5 ; x++) begin + for (int z = 0 ; z < W ; z++) begin + box[x][y][z] = s_in[W*(5*y+x) + z]; + end + end + end + return box; + endfunction : bitarray_to_box + + // Convert 3D cube to bitarray + function automatic logic [Width-1:0] box_to_bitarray(box_t state); + automatic logic [Width-1:0] bitarray; + for (int y = 0 ; y < 5 ; y++) begin + for (int x = 0 ; x < 5 ; x++) begin + for (int z = 0 ; z < W ; z++) begin + bitarray[W*(5*y+x)+z] = state[x][y][z]; + end + end + end + return bitarray; + endfunction : box_to_bitarray + + // Rotate integer indices + function automatic integer rot_int(integer in, integer num); + integer out; + if (in == 0) begin + out = num - 1; + end else begin + out = in - 1; + end + return out; + endfunction + + // Step Mapping ============================================================= + // theta + // XOR each bit in the state with the parity of two columns + // C[x,z] = A[x,0,z] ^ A[x,1,z] ^ A[x,2,z] ^ A[x,3,z] ^ A[x,4,z] + // D[x,z] = C[x-1,z] ^ C[x+1,z-1] + // theta = A[x,y,z] ^ D[x,z] + parameter logic [2:0] ThetaIndexX1 [5] = '{4, 0, 1, 2, 3}; // (x-1)%5 + parameter logic [2:0] ThetaIndexX2 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + function automatic box_t theta(box_t state); + plane_t c; + plane_t d; + box_t result; + for (int x = 0 ; x < 5 ; x++) begin + c[x] = state[x][0] ^ state[x][1] ^ state[x][2] ^ state[x][3] ^ state[x][4]; + end + for (int x = 0 ; x < 5 ; x++) begin + for (int z = 0 ; z < W ; z++) begin + logic [$clog2(W)-1:0] index_z; + index_z = (z == 0) ? W-1 : z-1; // (z+1)%W + d[x][z] = c[ThetaIndexX1[x]][z] ^ c[ThetaIndexX2[x]][index_z]; + end + end + for (int x = 0 ; x < 5 ; x++) begin + for (int y = 0 ; y < 5 ; y++) begin + result[x][y] = state[x][y] ^ d[x]; + end + end + return result; + endfunction : theta + + // rho + + // Commented out entire rho function due to VCS elaboration error. + // (z-RhoOffset[x][y]%W) isn't considered as a constant in VCS. + // Even changing it to W-RhoOffset[x][y]%W and assign to ShiftAmt + // creates same error. + + // Offset : Look at Table 2 in FIPS PUB 202 + //localparam int RhoOffset [5][5] = '{ + // //y 0 1 2 3 4 x + // '{ 0, 36, 3, 105, 210},// 0 + // '{ 1, 300, 10, 45, 66},// 1 + // '{ 190, 6, 171, 15, 253},// 2 + // '{ 28, 55, 153, 21, 120},// 3 + // '{ 91, 276, 231, 136, 78} // 4 + //}; + + // rotate bits of each lane by offset + // 1. rho[0,0,z] = A[0,0,z] + // 2. Offset swap + // a. (x,y) := (1,0) + // b. for t [0..23] + // i. rho[x,y,z] = A[x,y,z-(t+1)(t+2)/2] + // ii. (x,y) = (y, (2x+3y)) + //function automatic box_t rho(box_t state); + // box_t result; + // for (int x = 0 ; x < 5 ; x++) begin + // for (int y = 0 ; y < 5 ; y++) begin + // for (int z = 0 ; z < W ; z++) begin + // automatic int index_z; + // index_z = (z-RhoOffset[x][y])%W; + // result[x][y][z] = state[x][y][(z-RhoOffset[x][y])%W]; + // end + // end + // end + // return result; + //endfunction : rho + + // pi + // rearrange the position of lanes + // pi[x,y,z] = state[(x+3y),x,z] + localparam logic [2:0] PiRotate [5][5] = '{ + //y 0 1 2 3 4 x + '{ 0, 3, 1, 4, 2},// 0 + '{ 1, 4, 2, 0, 3},// 1 + '{ 2, 0, 3, 1, 4},// 2 + '{ 3, 1, 4, 2, 0},// 3 + '{ 4, 2, 0, 3, 1} // 4 + }; + function automatic box_t pi(box_t state); + box_t result; + for (int x = 0 ; x < 5 ; x++) begin + for (int y = 0 ; y < 5 ; y++) begin + result[x][y][W-1:0] = state[PiRotate[x][y]][x][W-1:0]; + end + end + return result; + endfunction : pi + + // chi + // chi[x,y,z] = state[x,y,z] ^ ((state[x+1,y,z] ^ 1) & state[x+2,y,z]) + parameter logic [2:0] ChiIndexX1 [5] = '{1, 2, 3, 4, 0}; // (x+1)%5 + parameter logic [2:0] ChiIndexX2 [5] = '{2, 3, 4, 0, 1}; // (x+2)%5 + function automatic box_t chi(box_t state); + box_t result; + for (int x = 0 ; x < 5 ; x++) begin + result[x] = state[x] ^ ((~state[ChiIndexX1[x]]) & state[ChiIndexX2[x]]); + end + return result; + endfunction : chi + + // iota + // XOR (x,y) = (0,0) with Round Constant (RC) + + // RC parameter: Precomputed by util/keccak_rc.py. Only up-to 0..L-1 is used + // RC = '0 + // RC[2**j-1] = rc(j+7*rnd) + // rc(t) = + // 1. t%255 == 0 -> 1 + // 2. R[0:7] = 'b10000000 + // 3. for i = [1..t%255] + // a. R = 0 || R + // b. R[0] = R[0] ^ R[8] + // c. R[4] = R[4] ^ R[8] + // d. R[5] = R[5] ^ R[8] + // e. R[6] = R[6] ^ R[8] + // f. R = R[0:7] + // 4. return R[0] + // RC has L = [0..6] + // for lower L case, only chopping lower part of 64bit RC is sufficient. + localparam logic [63:0] RC [24] = '{ + 64'h 0000_0000_0000_0001, // Round 0 + 64'h 0000_0000_0000_8082, // Round 1 + 64'h 8000_0000_0000_808A, // Round 2 + 64'h 8000_0000_8000_8000, // Round 3 + 64'h 0000_0000_0000_808B, // Round 4 + 64'h 0000_0000_8000_0001, // Round 5 + 64'h 8000_0000_8000_8081, // Round 6 + 64'h 8000_0000_0000_8009, // Round 7 + 64'h 0000_0000_0000_008A, // Round 8 + 64'h 0000_0000_0000_0088, // Round 9 + 64'h 0000_0000_8000_8009, // Round 10 + 64'h 0000_0000_8000_000A, // Round 11 + 64'h 0000_0000_8000_808B, // Round 12 + 64'h 8000_0000_0000_008B, // Round 13 + 64'h 8000_0000_0000_8089, // Round 14 + 64'h 8000_0000_0000_8003, // Round 15 + 64'h 8000_0000_0000_8002, // Round 16 + 64'h 8000_0000_0000_0080, // Round 17 + 64'h 0000_0000_0000_800A, // Round 18 + 64'h 8000_0000_8000_000A, // Round 19 + 64'h 8000_0000_8000_8081, // Round 20 + 64'h 8000_0000_0000_8080, // Round 21 + 64'h 0000_0000_8000_0001, // Round 22 + 64'h 8000_0000_8000_8008 // Round 23 + }; + + // iota: XOR with RC for (x,y) = (0,0) + function automatic box_t iota(box_t state, logic [RndW-1:0] rnd); + box_t result; + result = state; + result[0][0][W-1:0] = state[0][0][W-1:0] ^ RC[rnd][W-1:0]; + + return result; + endfunction : iota + + // Round function : Rnd(A,i_r) + // Not used due to rho function issue described above. + + //function automatic box_t keccak_rnd(box_t state, logic [RndW-1:0] rnd); + // box_t keccak_state; + // keccak_state = iota(chi(pi(rho(theta(state)))), rnd); + // + // return keccak_state; + //endfunction : keccak_rnd + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_keccak_round.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_keccak_round.sv new file mode 100644 index 0000000000000000000000000000000000000000..295fbfc19ee12192256c5f9840cee1c6b282fcc3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_keccak_round.sv @@ -0,0 +1,508 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Keccak full round logic based on given input `Width` +// e.g. Width 800 requires 22 rounds + +`include "abr_sva.svh" +`include "abr_prim_assert.sv" + +module abr_keccak_round + import abr_prim_mubi_pkg::*; +#( + parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} + parameter int RoundsPerClock = 1, + + // Derived + localparam int W = Width/25, + localparam int L = $clog2(W), + localparam int MaxRound = 12 + 2*L, // Keccak-f only + localparam int RndW = $clog2(MaxRound+1), // Representing up to MaxRound-1 + + // Control parameters + parameter bit EnMasking = 1'b0, // Enable SCA hardening, requires Width >= 50 + localparam int Share = EnMasking ? 2 : 1 +) ( + input clk_i, + input rst_b, + input logic zeroize, + + // Message Feed + input [Width-1:0] data_i [Share], + output ready_o, + + // In-process control + input logic run_i, // Pulse signal to initiates Keccak full round + input logic squeezing_i, + input logic rand_valid_i, + input logic rand_early_i, + input logic [Width/2-1:0] rand_data_i, + input logic rand_aux_i, + output logic rand_consumed_o, + + output logic complete_o, // Indicates full round is done + + // State out. This can be used as Digest + output logic [Width-1:0] state_o [Share], + + // Errors: + // sparse_fsm_error: Checking if FSM state falls into unknown value + output logic sparse_fsm_error_o, + // round_count_error: abr_prim_count checks round value consistency + output logic round_count_error_o, + // rst_storage_error: check if reset signal asserted out of the + // permitted window + output logic rst_storage_error_o, + + input abr_prim_mubi_pkg::mubi4_t clear_i // Clear internal state to '0 +); + + ///////////////////// + // Control signals // + ///////////////////// + + // Update storage register + logic update_storage; + logic update_serial_buffer; + + // Reset the storage to 0 to initiate new Hash operation + logic rst_storage; + logic rst_serial_buffer; + + // XOR message into storage register + logic xor_message; + + // Select Keccak_p datapath + // 0: Select Phase1 (Theta -> Rho -> Pi) + // 1: Select Phase2 (Chi -> Iota) + // `phase_sel` needs to be asserted until the Chi stage is consumed, + mubi4_t phase_sel; + + // Cycle index used for controlling input/output muxes and write enables inside + // keccak_2share. + logic [1:0] cycle; + + // Increase/ Reset Round number + logic inc_rnd_num; + logic rst_rnd_num; + + // Round reaches end + // This signal indicates the round reaches desired number, which is MaxRound -1. + // MaxRound is dependant on the Width. In case of SHA3/SHAKE, MaxRound is 24. + logic rnd_eq_end; + + // Complete of Keccak_f + // State machine asserts `complete_d` when it reaches at the end of round and + // operation (Phase3 if Masked). The the stage, the storage still doesn't have + // the valid states. So precisely it is not completed yet. + // State generated `complete_d` is latched with the clock and creates a pulse + // signal one cycle later. The signal is the indication of completion. + // + // Intentionally removed any intermediate step (so called StComplete) in order + // to save a clock to proceeds next round. + logic complete_d; + + ////////////////////// + // Datapath Signals // + ////////////////////// + + // Single round keccak output data + logic [Width-1:0] keccak_out [Share]; + + // Keccak Round indicator: range from 0 .. MaxRound + logic [RndW-1:0] round; + + // Random value and valid signal used in Keccak_p + logic keccak_rand_consumed; + logic [Width/2-1:0] keccak_rand_data; + logic keccak_rand_aux; + + ////////////////////// + // Keccak Round FSM // + ////////////////////// + + // state inputs + assign rnd_eq_end = (int'(round) == MaxRound - RoundsPerClock); + + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 8 -n 6 \ + // -s 1363425333 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 5 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + StIdle = 6'b011111, + + // Active state is used in Unmasked version only. + // It handles keccak round in a cycle + StActive = 6'b000100, + + // Phase1 --> Phase2Cycle1 --> Phase2Cycle2 --> Phase2Cycle3 + // Activated only in Masked version. + // Phase1 processes Theta, Rho, Pi steps in a cycle and stores the states + // into storage. It only moves to Phase2 once the randomness required for + // Phase2 is available. + StPhase1 = 6'b101101, + + // Chi Stage 1 for first lane halves. Unconditionally move to Phase2Cycle2. + StPhase2Cycle1 = 6'b000011, + + // Chi Stage 2 and Iota for first lane halves. Chi Stage 1 for second + // lane halves. We only move forward if the fresh randomness required for + // remasking is available. Otherwise, keep computing Phase2Cycle1. + StPhase2Cycle2 = 6'b011000, + + // Chi Stage 2 and Iota for second lane halves. + // This state doesn't require random value as it is XORed into the states + // in Phase1 and Phase2Cycle2. When doing the last round (MaxRound -1) + // it completes the process and goes back to Idle. If not, it repeats + // the phases again. + StPhase2Cycle3 = 6'b101010, + + // Error state. Not clearly defined yet. + // Intention is if any unexpected input in the process, state moves to + // here and report through the error fifo with debugging information. + StError = 6'b110001, + + StTerminalError = 6'b110110 + } keccak_st_e; + keccak_st_e keccak_st, keccak_st_d; + `ABR_PRIM_FLOP_SPARSE_FSM(u_state_regs, keccak_st_d, keccak_st, keccak_st_e, StIdle) + + // Next state logic and output logic + // SEC_CM: FSM.SPARSE + always_comb begin + // Default values + keccak_st_d = keccak_st; + + xor_message = 1'b 0; + update_storage = 1'b 0; + rst_storage = 1'b 0; + rst_serial_buffer = 1'b 0; + + inc_rnd_num = 1'b 0; + rst_rnd_num = 1'b 0; + + keccak_rand_consumed = 1'b 0; + + phase_sel = MuBi4False; + cycle = 2'h 0; + + complete_d = 1'b 0; + + sparse_fsm_error_o = 1'b 0; + + unique case (keccak_st) + StIdle: begin + if (abr_prim_mubi_pkg::mubi4_test_true_strict(clear_i)) begin + // Opt1. State machine allows resetting the storage only in Idle + // Opt2. storage resets regardless of states but clear_i + // Both are added in the design at this time. Will choose the + // direction later. + keccak_st_d = StIdle; + + rst_storage = 1'b 1; + rst_serial_buffer = 1'b 1; + end else if (EnMasking && run_i) begin + // Masked version of Keccak handling + keccak_st_d = StPhase1; + xor_message = ~squeezing_i; + update_storage = ~squeezing_i; + end else if (!EnMasking && run_i) begin + // Unmasked version of Keccak handling + keccak_st_d = StActive; + xor_message = ~squeezing_i; + update_storage = ~squeezing_i; + end else begin + keccak_st_d = StIdle; + end + end + + StActive: begin + // Run Keccak single round logic until it reaches MaxRound - 1 + update_storage = 1'b 1; + + if (rnd_eq_end) begin + keccak_st_d = StIdle; + + rst_rnd_num = 1'b 1; + complete_d = 1'b 1; + end else begin + keccak_st_d = StActive; + + inc_rnd_num = 1'b 1; + end + end + + StPhase1: begin + // Theta, Rho and Pi + phase_sel = MuBi4False; + cycle = 2'h 0; + + // Only update state and move on once we know the randomness required + // for Phase2 will be available in the next clock cycle. This way the + // DOM multipliers inside keccak_2share will be presented the new + // state (updated with update_storage) at the same time as the new + // randomness (updated with rand_early_i). Otherwise, stale entropy is + // paired with fresh data or vice versa. This could lead to undesired + // SCA leakage. + if (rand_early_i || rand_valid_i) begin + keccak_st_d = StPhase2Cycle1; + update_storage = 1'b 1; + end else begin + keccak_st_d = StPhase1; + end + end + + StPhase2Cycle1: begin + // Chi Stage 1 for first lane halves. + phase_sel = MuBi4True; + cycle = 2'h 1; + + // Trigger randomness update for next cycle. + keccak_rand_consumed = 1'b 1; + + // Unconditionally move to next phase/cycle. + keccak_st_d = StPhase2Cycle2; + end + + StPhase2Cycle2: begin + // Chi Stage 1 for second lane halves. + // Chi Stage 2 and Iota for first lane halves. + phase_sel = MuBi4True; + + // Only update state and move on if the required randomness is + // available. This way the DOM multipliers inside keccak_2share will be + // presented the second lane halves at the same time as the new + // randomness. Otherwise, stale entropy is paired with fresh data or + // vice versa. This could lead to undesired SCA leakage. + if (rand_valid_i) begin + cycle = 2'h 2; + + // Trigger randomness update for next round. + keccak_rand_consumed = 1'b 1; + + // Update first lane halves. + update_storage = 1'b 1; + + keccak_st_d = StPhase2Cycle3; + end else begin + cycle = 2'h 1; + keccak_st_d = StPhase2Cycle2; + end + end + + StPhase2Cycle3: begin + // Chi Stage 2 and Iota for second lane halves. + phase_sel = MuBi4True; + cycle = 2'h 3; + + // Update second lane halves. + update_storage = 1'b 1; + + if (rnd_eq_end) begin + keccak_st_d = StIdle; + + rst_rnd_num = 1'b 1; + complete_d = 1'b 1; + end else begin + keccak_st_d = StPhase1; + + inc_rnd_num = 1'b 1; + end + end + + StError: begin + keccak_st_d = StError; + end + + StTerminalError: begin + //this state is terminal + keccak_st_d = keccak_st; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + keccak_st_d = StTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + if (zeroize) keccak_st_d =StIdle; + + end + + // Ready indicates the keccak_round is able to receive new message. + // While keccak_round is processing the data, it blocks the new message to be + // XORed into the current state. + assign ready_o = (keccak_st == StIdle) ? 1'b 1 : 1'b 0; + + //////////////////////////// + // Keccak state registers // + //////////////////////////// + + // SEC_CM: LOGIC.INTEGRITY + logic rst_n; + abr_prim_sec_anchor_buf #( + .Width(1) + ) u_abr_prim_sec_anchor_buf ( + .in_i(rst_b), + .out_o(rst_n) + ); + + logic [Width-1:0] storage_datapath[RoundsPerClock:0][Share]; + logic [Width-1:0] storage [Share]; + logic [Width-1:0] storage_d [Share]; + always_ff @(posedge clk_i or negedge rst_n) begin + if (!rst_n) begin + storage <= '{default:'0}; + end else if (zeroize) begin + storage <= '{default:'0}; + end else if (rst_storage) begin + storage <= '{default:'0}; + end else if (update_storage) begin + storage <= storage_d; + end + end + + assign state_o = storage; + + // Storage register input + // The incoming message is XORed with the existing storage registers. + always_comb begin + storage_d = storage_datapath[RoundsPerClock]; + if (xor_message) begin + for (int j = 0 ; j < Share ; j++) begin + storage_d[j] = storage[j] ^ data_i[j]; + end // for j + end // if xor_message + end + + // Check the rst_storage integrity + logic rst_storage_error; + + always_comb begin : chk_rst_storage + rst_storage_error = 1'b 0; + + if (rst_storage) begin + // FSM should be in StIdle and clear_i should be high + if ((keccak_st != StIdle) || + abr_prim_mubi_pkg::mubi4_test_false_loose(clear_i)) begin + rst_storage_error = 1'b 1; + end + end + end : chk_rst_storage + + assign rst_storage_error_o = rst_storage_error ; + + ////////////// + // Datapath // + ////////////// + assign storage_datapath[0] = storage; + + generate + for (genvar inst_g = 0; inst_g < RoundsPerClock; inst_g++) begin : round_gen + abr_keccak_2share #( + .Width (Width), + .EnMasking (EnMasking) + ) u_keccak_p ( + .clk_i, + .rst_b, + + .rnd_i (RndW'(round+inst_g)), + .phase_sel_i (phase_sel), + .cycle_i (cycle), + .rand_aux_i (keccak_rand_aux), + .rand_i (keccak_rand_data), + .s_i (storage_datapath[inst_g]), + .s_o (storage_datapath[inst_g+1]) + ); + end + endgenerate + + // keccak entropy handling + assign rand_consumed_o = keccak_rand_consumed; + + assign keccak_rand_data = rand_data_i; + assign keccak_rand_aux = rand_aux_i; + + // Round number + // This primitive is used to place a hardened counter + // SEC_CM: CTR.REDUN + abr_prim_count #( + .Width(RndW) + ) u_round_count ( + .clk_i, + .rst_b, + .clr_i(rst_rnd_num | zeroize), + .set_i(1'b0), + .set_cnt_i('0), + .incr_en_i(inc_rnd_num), + .decr_en_i(1'b0), + .step_i(RndW'(RoundsPerClock)), + .cnt_o(round), + .cnt_next_o(), + .err_o(round_count_error_o) + ); + + // completion signal + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + complete_o <= 1'b 0; + end else if (zeroize) begin + complete_o <= 1'b 0; + end else begin + complete_o <= complete_d; + end + end + + //////////////// + // Assertions // + //////////////// + + // Only allow RoundsPerClock of 1-4 + `ABR_ASSERT_INIT(RoundsPerClockLTE_4_A, (RoundsPerClock > 0) && (RoundsPerClock <= 4)) + + // If `run_i` triggerred, it shall complete + //`ABR_ASSERT(RunResultComplete_A, run_i ##[MaxRound:] complete_o, clk_i, !rst_b) + + // run_i only asserted in Idle state + `ABR_ASSUME(ValidRunAssertStIdle_A, run_i |-> keccak_st == StIdle, clk_i, !rst_b) + + // clear_i is assumed to be asserted in Idle state + `ABR_ASSUME(ClearAssertStIdle_A, + abr_prim_mubi_pkg::mubi4_test_true_strict(clear_i) + |-> keccak_st == StIdle, clk_i, !rst_b) + + // EnMasking controls the valid states + if (EnMasking) begin : gen_mask_st_chk + `ABR_ASSERT(EnMaskingValidStates_A, keccak_st != StActive, clk_i, !rst_b) + end else begin : gen_unmask_st_chk + `ABR_ASSERT(UnmaskValidStates_A, !(keccak_st + inside {StPhase1, StPhase2Cycle1, StPhase2Cycle2, StPhase2Cycle3}), + clk_i, !rst_b) + end + + // If message is fed, it shall start from 0 + // TODO: Handle the case `addr_i` changes prior to `valid_i` + //`ABR_ASSUME(MsgStartFrom0_A, valid_i |-> + // (addr_i == 0) || (addr_i == $past(addr_i) + 1), + // clk_i,!rst_b) + + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3.sv new file mode 100644 index 0000000000000000000000000000000000000000..eb1205f29399f924159289159e99e91b2313cb08 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3.sv @@ -0,0 +1,490 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// SHA3 core is a fully functional SHA3/SHAKE/cSHAKE hashing module. +// +// It instantiates a keccak_round with 1600 bits of the state. + +`include "abr_sva.svh" +`include "abr_prim_assert.sv" + +module abr_sha3 + import abr_sha3_pkg::*; +#( + // Number of Keccak Rounds performed each clock cycle + parameter int RoundsPerClock = 1, + // Enable Masked Keccak if 1 + parameter bit EnMasking = 0, + // derived parameter + localparam int Share = (EnMasking) ? 2 : 1 +) ( + input logic clk_i, + input logic rst_b, + input logic zeroize, + // MSG interface + input logic msg_start_i, + input logic msg_valid_i, + input logic [MsgWidth-1:0] msg_data_i [Share], + input logic [MsgStrbW-1:0] msg_strb_i, // one strobe for shares + output logic msg_ready_o, + + // Entropy interface + input logic rand_valid_i, + input logic rand_early_i, + input logic [StateW/2-1:0] rand_data_i, + input logic rand_aux_i, + output logic rand_consumed_o, + + // N, S: Used in cSHAKE mode only + input logic [NSRegisterSize*8-1:0] ns_data_i, // See abr_sha3_pkg for details + + // configurations + input sha3_mode_e mode_i, // see abr_sha3pad for details + input keccak_strength_e strength_i, // see abr_sha3pad for details + + // controls + input logic start_i, // see abr_sha3pad for details + input logic process_i, // see abr_sha3pad for details + + // run_i is a pulse signal to trigger the keccak_round manually by SW. + // It is used to run additional keccak_f after sponge absorbing is completed. + // See `keccak_run` signal + input logic run_i, + input abr_prim_mubi_pkg::mubi4_t done_i, // see abr_sha3pad for details + + output abr_prim_mubi_pkg::mubi4_t absorbed_o, + output logic squeezing_o, + + // Indicate of one block processed. KMAC main state tracks the progression + // based on this signal. + output logic block_processed_o, + + output sha3_st_e sha3_fsm_o, + + // digest output + // This value is valid only after all absorbing process is completed. + // In invalid state, the output `state` will be zero to prevent information + // leakage. + output logic state_valid_o, + input logic state_valid_hold_i, + output logic [StateW-1:0] state_o [Share], + + // error_o value is pushed to Error FIFO at KMAC/SHA3 top and reported to SW + output err_t error_o, + + // sparse_fsm_alert + output logic sparse_fsm_error_o, + + // counter error + output logic count_error_o, + + // error on rst_storage in Keccak + output logic keccak_storage_rst_error_o + +); + ///////////////// + // Definitions // + ///////////////// + + typedef enum logic[2:0] { + MuxGuard = 3'b 010, + MuxRelease = 3'b 101 + } state_mux_sel_e; + + ///////////// + // Signals // + ///////////// + + // State --> Digest + // State is exposed to the outside if the hashing process is completed. + logic state_valid; + logic [StateW-1:0] state [Share]; + logic [StateW-1:0] state_guarded [Share]; + + // State --> digest mux select signal + state_mux_sel_e mux_sel; + + // absorbed is a pulse signal that indicates sponge absorbing is done. + // After this, sha3 core allows software to manually run until squeezing + // is completed, which is the `done_i` pulse signal. + abr_prim_mubi_pkg::mubi4_t absorbed; + + // `squeezing` is a status indicator that SHA3 core is in sponge squeezing + // stage. In this stage, the state output is valid, and software can manually + // trigger keccak_round logic to get more digest outputs in case the output + // length is bigger than the block limit. + logic squeezing; + + // If process_i is received, the logic initiates the final absorbing process. + // While absorbing, the processing inticator is turned on. This signal is used + // to check if multiple process_i is received or not. + logic processing; + + // FSM variable + sha3_st_sparse_e st, st_d; + + // Keccak control signal (filtered by State Machine) + logic keccak_start, keccak_process; + abr_prim_mubi_pkg::mubi4_t keccak_done; + + // alert signals + logic round_count_error, msg_count_error; + assign count_error_o = round_count_error | msg_count_error; + + logic sha3_state_error; + logic keccak_round_state_error; + logic sha3pad_state_error; + + assign sparse_fsm_error_o = sha3_state_error | keccak_round_state_error | sha3pad_state_error; + + // Keccak rst_storage is asserted unexpectedly + logic keccak_storage_rst_error; + assign keccak_storage_rst_error_o = keccak_storage_rst_error; + + ///////////////// + // Connections // + ///////////////// + + logic [abr_sha3_pkg::StateW-1:0] keccak_data [Share]; + logic keccak_ready; + + // Keccak round run signal can be controlled by sha3pad and also by software + // after all message feeding is done. it is mainly used for sponge squeezing + // operation after absorbing is completed when output length is longer than + // the block size. + logic keccak_run, sha3pad_keccak_run, sw_keccak_run; + logic keccak_complete; + + assign keccak_run = sha3pad_keccak_run | sw_keccak_run; + + // Absorb pulse output : used to generate interrupts + // Latch absorbed signal as kmac_keymgr asserts `CmdDone` when it sees + // `absorbed` signal. When this signal goes out, the state is still in + // `StAbsorb`. Next state is `StSqueeze`. + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) absorbed_o <= abr_prim_mubi_pkg::MuBi4False; + else if (zeroize) absorbed_o <= abr_prim_mubi_pkg::MuBi4False; + else absorbed_o <= absorbed; + end + + // Squeezing output + assign squeezing_o = squeezing; + + // processing + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) processing <= 1'b 0; + else if (zeroize) processing <= 1'b 0; + else if (process_i) processing <= 1'b 1; + else if (abr_prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin + processing <= 1'b 0; + end + end + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) state_valid <= 1'b0; + else if (zeroize) state_valid <= 1'b0; + else if ((st_d == StSqueeze_sparse) & ~state_valid) state_valid <= 1'b1; + else if (state_valid_hold_i) state_valid <= state_valid; + else state_valid <= 1'b0; + end + + assign block_processed_o = keccak_complete; + + // State connection + assign state_valid_o = state_valid; + assign state_o = state_guarded; + + assign sha3_fsm_o = sparse2logic(st); + + + + /////////////////// + // State Machine // + /////////////////// + + // State Register + `ABR_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, sha3_st_sparse_e, StIdle_sparse) + + + // Next State and Output Logic + // Mainly the FSM controls the input signal access + // StIdle: only start_i signal is allowed + // StAbsorb: only process_i signal is allowed + // StSqueeze: only run_i, done_i signal is allowed + + always_comb begin + st_d = st; + + // default output values + keccak_start = 1'b 0; + keccak_process = 1'b 0; + sw_keccak_run = 1'b 0; + keccak_done = abr_prim_mubi_pkg::MuBi4False; + + squeezing = 1'b 0; + + sha3_state_error = 1'b 0; + + unique case (st) + StIdle_sparse: begin + if (start_i) begin + st_d = StAbsorb_sparse; + + keccak_start = 1'b 1; + end else begin + st_d = StIdle_sparse; + end + end + + StAbsorb_sparse: begin + if (process_i && !processing) begin + st_d = StAbsorb_sparse; + + keccak_process = 1'b 1; + end else if (abr_prim_mubi_pkg::mubi4_test_true_strict(absorbed)) begin + st_d = StSqueeze_sparse; + end else begin + st_d = StAbsorb_sparse; + end + end + + StSqueeze_sparse: begin + + squeezing = 1'b 1; + + if (run_i) begin + st_d = StManualRun_sparse; + + sw_keccak_run = 1'b 1; + end else if (abr_prim_mubi_pkg::mubi4_test_true_strict(done_i)) begin + st_d = StFlush_sparse; + + keccak_done = done_i; + end else begin + st_d = StSqueeze_sparse; + end + end + + StManualRun_sparse: begin + squeezing = 1'b 1; + if (keccak_complete) begin + st_d = StSqueeze_sparse; + end else begin + st_d = StManualRun_sparse; + end + end + + StFlush_sparse: begin + st_d = StIdle_sparse; + end + + StTerminalError_sparse: begin + //this state is terminal + st_d = StTerminalError_sparse; + sha3_state_error = 1'b 1; + end + + default: begin + st_d = StTerminalError_sparse; + sha3_state_error = 1'b 1; + end + endcase + + if (zeroize) st_d = StIdle_sparse; + + end + + ////////////// + // Datapath // + ////////////// + + // State --> Digest output + always_comb begin + if (state_valid) mux_sel = MuxRelease; // Expose state to register interfac + else mux_sel = MuxGuard ; + end + + always_comb begin : state_guarded_mux + unique case (mux_sel) + MuxGuard: state_guarded = '{default: '0}; + MuxRelease: state_guarded = state; + default: state_guarded = '{default: '0}; // a valid, safe output + endcase + end + + + // Error Detecting + // ErrSha3SwControl: + // info[ 0]: start_i set + // info[ 1]: process_i set + // info[ 2]: run_i set + // info[ 3]: done_i set + // - Sw set process_i, run_i, done_i without start_i + + always_comb begin + error_o = '{valid: 1'b0, code: ErrNone, info: '0}; + + unique case (st) + StIdle_sparse: begin + if (process_i || run_i || + abr_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StAbsorb_sparse: begin + if (start_i || run_i || abr_prim_mubi_pkg::mubi4_test_true_loose(done_i) + || (process_i && processing)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StSqueeze_sparse: begin + if (start_i || process_i) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StManualRun_sparse: begin + if (start_i || process_i || run_i || + abr_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + StFlush_sparse: begin + if (start_i || process_i || run_i || + abr_prim_mubi_pkg::mubi4_test_true_loose(done_i)) begin + error_o = '{ + valid: 1'b 1, + code: ErrSha3SwControl, + info: 24'({done_i, run_i, process_i, start_i}) + }; + end + end + + default: begin + end + endcase + end + /////////////// + // Instances // + /////////////// + + // SHA3 pad logic + abr_sha3pad #( + .EnMasking (EnMasking) + ) u_pad ( + .clk_i, + .rst_b, + .zeroize, + + // MSG_FIFO (or from KMAC core) + .msg_valid_i, + .msg_data_i, // [Share] + .msg_strb_i, + .msg_ready_o, + + // Encoded N, S + .ns_data_i, + + // output to keccak_round: message path + .keccak_data_o (keccak_data ), // [Share] + .keccak_ready_i (keccak_ready & ~squeezing), + + .keccak_run_o (sha3pad_keccak_run), + .keccak_complete_i (keccak_complete ), + + // configurations + .mode_i, + .strength_i, + + // controls + .start_i (msg_start_i), + .process_i (keccak_process), + + // output + .absorbed_o (absorbed), + .sparse_fsm_error_o (sha3pad_state_error), + .msg_count_error_o (msg_count_error) + ); + + // Keccak round logic + abr_keccak_round #( + .Width (abr_sha3_pkg::StateW), + .RoundsPerClock(RoundsPerClock), + .EnMasking (EnMasking) + ) u_keccak ( + .clk_i, + .rst_b, + .zeroize, + + .data_i (keccak_data ), + .ready_o (keccak_ready), + + .rand_valid_i, + .rand_early_i, + .rand_data_i, + .rand_aux_i, + .rand_consumed_o, + + .run_i (keccak_run ), + .squeezing_i(squeezing ), + .complete_o (keccak_complete), + + .state_o (state), + + .sparse_fsm_error_o (keccak_round_state_error), + .round_count_error_o (round_count_error), + .rst_storage_error_o (keccak_storage_rst_error), + + .clear_i (keccak_done) + ); + + //////////////// + // Assertions // + //////////////// + + // Unknown check for case statement + `ABR_ASSERT(MuxSelKnown_A, mux_sel inside {MuxGuard, MuxRelease}) + `ABR_ASSERT(FsmKnown_A, st inside {StIdle_sparse, StAbsorb_sparse, StSqueeze_sparse, + StManualRun_sparse, StFlush_sparse, StTerminalError_sparse}) + + // `state` shall be 0 in invalid + if (EnMasking) begin: gen_chk_digest_masked + `ABR_ASSERT(StateZeroInvalid_A, !state_valid_o |-> ((|state_o[0]) | (|state_o[1])) == 1'b 0) + end else begin : gen_chk_digest_unmasked + `ABR_ASSERT(StateZeroInvalid_A, !state_valid_o |-> (|state_o[0]) == 1'b 0) + end + + // `state_valid_o` asserts only in between the completion and done + //`ABR_ASSERT(StateValidPeriod_A, state_valid_o |-> ) + + // skip the msg interface assertions as they are in abr_sha3pad.sv + + // Software run signal happens in Squeezing stage + `ABR_ASSUME(SwRunInSqueezing_a, run_i |-> error_o.valid || (st == StSqueeze_sparse)) + + // If control received but not propagated into submodules, it is error condition + `ABR_ASSERT(ErrDetection_A, error_o.valid + |-> {start_i, process_i, run_i, done_i} + != {keccak_start, keccak_process, sw_keccak_run, keccak_done}) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..17462d7f5fed8c586733e6695f61ba7fcffa0610 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3_pkg.sv @@ -0,0 +1,226 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// abr_sha3_pkg + +package abr_sha3_pkg; + + // StateW represents the width of Keccak state variable. + // As Sha3 assume the state value as 1600, this shouldn't be modified. + // Note that keccak_round is flexible. It can have any values defined in SHA3 + // specification. But sha3pad logic assumes the value as 1600. + parameter int StateW = 1600; + + // Function Name (N) and Customzation String (S) shall be + // smaller than 2**256 bits and integer divisiable by 8. + parameter int FnWidth = 32; // up to 32bit Function Name + parameter int CsWidth = 256; // up to 256bit Customization Input + + // Calculate left_encode(len( X )) bit size. + // Assume the enc_8(n) is always 1 (up to 255 byte of len(S) size) + // e.g) 248bit --> two bytes , 256bit --> three bytes + // round8bit(clog2(X+1))/8 + + parameter int MaxFnEncodeSize = ($clog2(FnWidth+1) + 8 - 1) / 8 + 1; + parameter int MaxCsEncodeSize = ($clog2(CsWidth+1) + 8 - 1) / 8 + 1; + + parameter int NSRegisterSizePre = FnWidth/8 + CsWidth/8 + + MaxFnEncodeSize + MaxCsEncodeSize; + // Round up to 32bit word base + parameter int NSRegisterSize = ((NSRegisterSizePre + 4 - 1 ) / 4) * 4; + + // Prefix represents bytepad(encode_string(N) || encode_string(S), 168 or 136) + // +2 represents left_encoding(168 or 136) which could be either: + // 10000000 || 00010101 // 168 + // 10000000 || 00010001 // 136 + parameter int PrefixSize = NSRegisterSize + 2; + + // index width for `N` and `S` + parameter int PrefixIndexW = $clog2(PrefixSize/64); + + // Datapath width in KMAC, this also affects the output of MSG_FIFO + // This is assumed as 64 in KMAC design. If this value is changed, some parts + // of the KMAC design need to be changed. + // + // 1. keccak_round logic datapath. Keccak round logic assumes MsgWidth + // divides 1600 keccak state `Width`. Choose the value accordingly. + // 2. sha3pad module has fixed width mux for funcpad logic. If MsgWidth is + // changed, the logic also need to be revised. + // 3. kmac core logic also has fixed size mux for appeding output length. + // Revise the case statement to fit into revised MsgWidth value. + parameter int MsgWidth = 64; + parameter int MsgStrbW = MsgWidth / 8; + + // Keccak module supports SHA3, SHAKE, cSHAKE function. + // This mode determines if the module uses encoded N and S or not. + // Also it chooses the padding value. + // + // mode | little-endian + // -------|---------------- + // Sha3 | 2'b 10 + // Shake | 4'b 1111 + // CShake | 2'b 00 + // + // Please remind that if input strings N and S are empty, SW shall + // choose SHAKE even for cSHAKE operation. + typedef enum logic[1:0] { + Sha3 = 2'b 00, + Shake = 2'b 10, + CShake = 2'b 11 + } sha3_mode_e; + + // keccak_strength_e determines the security strength against collision attack + // This value decides the _rate_ and _capacity_ of the keccak states. + // It affects the sha3pad module too. the padding module implements + // `bytepad(X,168)` for L128, `bytepad(X,136)` for L256 in cSHAKE + typedef enum logic [2:0] { + L128 = 3'b 000, // rate: 1344 bit / capacity: 256 bit Keccak[ 256](, 128) + L224 = 3'b 001, // rate: 1152 bit / capacity: 448 bit Keccak[ 448](, 224) + L256 = 3'b 010, // rate: 1088 bit / capacity: 512 bit Keccak[ 512](, 256) + L384 = 3'b 011, // rate: 832 bit / capacity: 768 bit Keccak[ 768](, 384) + L512 = 3'b 100 // rate: 576 bit / capacity: 1024 bit Keccak[1024](, 512) + } keccak_strength_e; + + parameter int unsigned KeccakRate [5] = '{ + (1344+MsgWidth-1)/MsgWidth, // 21 depth := (1600 - 128*2) + (1152+MsgWidth-1)/MsgWidth, // 18 depth := (1600 - 224*2) + (1088+MsgWidth-1)/MsgWidth, // 17 depth := (1600 - 256*2) + (832+MsgWidth-1)/MsgWidth, // 13 depth := (1600 - 384*2) + (576+MsgWidth-1)/MsgWidth // 9 depth := (1600 - 512*2) + }; + + parameter int unsigned MaxBlockSize = KeccakRate[0]; + + parameter int unsigned MsgEntries = (StateW+MsgWidth-1)/MsgWidth; + parameter int unsigned MsgAddrW = $clog2(MsgEntries); + + parameter int unsigned MsgCountW = $clog2(MsgEntries+1); + + // SHA3 core state. This state value is used in sha3core module + // and also in KMAC top module and the register interface for sw to track the + // sha3 status. + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 7 -n 6 \ + // -s 4082450958 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 4 + // Minimum Hamming weight: 1 + // Maximum Hamming weight: 4 + // + localparam int StateWidth = 6; + typedef enum logic [StateWidth-1:0] { + StIdle_sparse = 6'b101100, + + // Absorb stage receives the message bitstream and computes the keccak + // rounds. This internal operation is mainly done inside sha3pad module + // not sha3core. The core module and this state machine observe the status + // of the process and mainly waits until all the sponge absorbing is + // completed. The main indicator is `absorbed` signal. + StAbsorb_sparse = 6'b100001, + + // TODO: Implement StAbort later after context-switching discussion. + // Abort stage can be moved from StAbsorb stage. It basically holds the + // keccak round operation and opens up the internal state variable to the + // software. This stage is for the software to pause current operation and + // store the internal state elsewhere then initiates new KMAC/SHA3 process. + // StAbort only can be moved to _StFlush_. + //StAbort_sparse = 6'b011101, + + // Squeeze stage allows the software to read the internal state. + // If `EnMasking`, it opens the read permission of two share of the state. + // The squeezing in SHA3 specification describes the software to read up to + // the rate of SHA3 algorithm but this logic opens up the entire 1600 bits + // of the state (3200bits if `EnMasking`). + StSqueeze_sparse = 6'b001011, + + // ManualRun stage initiaties the keccak round and waits the completion. + // This state is moved from Squeeze state by writing 1 to manual_run CSR. + // When keccak round is completed, it goes back to Squeeze state. + StManualRun_sparse = 6'b010000, + + // Flush stage, the core clears out the internal variables and also + // submodules' variables too. Then moves back to Idle state. + StFlush_sparse = 6'b000110, + + StTerminalError_sparse = 6'b111010 + } sha3_st_sparse_e; + + localparam int StateWidthLogic = 3; + typedef enum logic [StateWidthLogic-1:0] { + StIdle, + StAbsorb, + //StAbort, + StSqueeze, + StManualRun, + StFlush, + StError + } sha3_st_e; + + function automatic sha3_st_e sparse2logic(sha3_st_sparse_e st); + unique case (st) + StIdle_sparse : return StIdle; + StAbsorb_sparse : return StAbsorb; + //StAbort_sparse : return StAbort; + StSqueeze_sparse : return StSqueeze; + StManualRun_sparse : return StManualRun; + StFlush_sparse : return StFlush; + default : return StError; + endcase + endfunction : sparse2logic + + ////////////////// + // Error Report // + ////////////////// + typedef enum logic [7:0] { + ErrNone = 8'h 00, + + // ErrSha3SwControl occurs when software sent wrong flow signal. + // e.g) Sw set `process_i` without `start_i`. The state machine ignores + // the signal and report through the error FIFO. + ErrSha3SwControl = 8'h 80 + } err_code_e; + + typedef struct packed { + logic valid; + err_code_e code; // Type of error + logic [23:0] info; // Additional Debug info + } err_t; + + + /////////////// + // Functions // + /////////////// + + // Bytepading function + // `encode_bytepad_len` represents the first two bytes of bytepad() + // It depends on the block size. We can reuse KeccakRate + // 10000000 || 00010101 // 168 + // 10000000 || 00010001 // 136 + function automatic logic [15:0] encode_bytepad_len(keccak_strength_e kstrength); + logic [15:0] result; + unique case (kstrength) + L128: result = 16'h A801; // cSHAKE128 + L224: result = 16'h 9001; // not used + L256: result = 16'h 8801; // cSHAKE256 + L384: result = 16'h 6801; // not used + L512: result = 16'h 4801; // not used + + default: result = 16'h 0000; + endcase + return result; + endfunction : encode_bytepad_len + + +endpackage : abr_sha3_pkg diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3pad.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3pad.sv new file mode 100644 index 0000000000000000000000000000000000000000..5f1a5ad7f0a6c3ccfd661b2c430b3e6aa5d84608 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/rtl/abr_sha3pad.sv @@ -0,0 +1,947 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// ABR_SHA3 padding logic + +`include "abr_sva.svh" +`include "abr_prim_assert.sv" + +module abr_sha3pad + import abr_sha3_pkg::*; +#( + parameter int Width = 1600, // b= {25, 50, 100, 200, 400, 800, 1600} + parameter bit EnMasking = 0, + localparam int Share = (EnMasking) ? 2 : 1 +) ( + input clk_i, + input rst_b, + input logic zeroize, + + // Message interface (FIFO) + input msg_valid_i, + input [MsgWidth-1:0] msg_data_i [Share], + input [MsgStrbW-1:0] msg_strb_i, // one strobe for shares + output logic msg_ready_o, + + // N, S: Used in cSHAKE mode only + input [NSRegisterSize*8-1:0] ns_data_i, // See abr_sha3_pkg for details + + // output to keccak_round: message path + output logic [Width-1:0] keccak_data_o [Share], + input logic keccak_ready_i, + + // keccak_round control and status + // `run` initiates the keccak_round to process full keccak_f (24rounds). + // `complete` is an input from keccak round showing the current keccak_f is + // completed. + output logic keccak_run_o, + input keccak_complete_i, + + // configurations + input sha3_mode_e mode_i, + // strength_i is used in bytepad operation. bytepad() is used in cSHAKE only. + // SHA3, SHAKE doesn't have encode_N,S + input keccak_strength_e strength_i, + + // control signal + // start_i is a pulse signal triggers the padding logic (and the rest of SHA) + // to accept the incoming messages. This signal is used in the pad module, + // to initiate the prefix transmitting to keccak_round + input start_i, + // process_i is a pulse signal triggers the pad logic to stop receiving the + // message from MSG_FIFO and pad the trailing bits specified in the SHA3 + // standard. Look at `funcpad` signal for the values. + input process_i, + + // Indication of the Keccak Sponge Absorbing is complete, it is time for SW to + // control the Keccak-round if it needs more digest, or complete by asserting + // `done_i` + output abr_prim_mubi_pkg::mubi4_t absorbed_o, + + // Indication that there was a fault in the sparse encoding + output logic sparse_fsm_error_o, + + // Indication that there was a fault in the counter + output logic msg_count_error_o +); + + ///////////////// + // Definitions // + ///////////////// + + // Padding States + // Encoding generated with: + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 10 -n 7 \ + // -s 1116691466 --language=sv + // + // Hamming distance histogram: + // + // 0: -- + // 1: -- + // 2: -- + // 3: |||||||||||||||||||| (42.22%) + // 4: |||||||||||||||||| (40.00%) + // 5: ||||| (11.11%) + // 6: || (4.44%) + // 7: | (2.22%) + // + // Minimum Hamming distance: 3 + // Maximum Hamming distance: 7 + // Minimum Hamming weight: 2 + // Maximum Hamming weight: 5 + // + localparam int StateWidthPad = 7; + typedef enum logic [StateWidthPad-1:0] { + StPadIdle = 7'b1000010, + + // Sending a block of prefix, if cSHAKE mode is turned on. For the rest + // (SHA3, SHAKE), sending prefix is not needed. FSM moves from Idle to + // Message directly in that case. + // + // As abr_prim_slicer is instantiated, zerofill after the actual prefix is done + // by the module. + StPrefix = 7'b0111100, + StPrefixWait =7'b1001100, + + // Sending Message. In this state, it directly forwards the incoming data + // to Keccak round module. If `process_i` is asserted, then the rest of the + // messages will be discarded until new `start_i` is asserted. + // + // The incoming data can be partial write. Padding logic counts the number + // of bytes received and pause if a block size is transferred. + StMessage = 7'b0100101, + StMessageWait = 7'b0001111, + + // After sending the messages, then `process_i` is set, the FSM pads at the + // end of the message based on `mode_i`. If this is the last byte of the + // block, then it pads [7] to 1 to complete `pad10*1()` function. + StPad = 7'b1111010, + StPadRun = 7'b0011001, + + // If the padding isn't the end of the block byte (which will be rare case), + // FSM moves to another zerofill state. In contrast to StZerofill, this state + StPad01 = 7'b1101001, + + // Flushing the internal packers in front of the Keccak data output port. + StPadFlush = 7'b1010111, + + StTerminalError = 7'b0110011 + } pad_st_e; + + typedef enum logic [2:0] { + MuxNone = 3'b 000, + MuxFifo = 3'b 001, + MuxPrefix = 3'b 010, + MuxFuncPad = 3'b 011, + MuxZeroEnd = 3'b 100 + } mux_sel_e; + + //////////////////// + // Configurations // + //////////////////// + + logic [MsgCountW-1:0] block_addr_limit; + + // Block size based on the address. + // This is used for bytepad() and also pad10*1() + // assign block_addr_limit = KeccakRate[strength_i]; + // but below is easier to understand + always_comb begin + unique case (strength_i) + L128: block_addr_limit = MsgCountW'(KeccakRate[L128]); + L224: block_addr_limit = MsgCountW'(KeccakRate[L224]); + L256: block_addr_limit = MsgCountW'(KeccakRate[L256]); + L384: block_addr_limit = MsgCountW'(KeccakRate[L384]); + L512: block_addr_limit = MsgCountW'(KeccakRate[L512]); + + default: block_addr_limit = '0; + endcase + end + + ///////////////////// + // Control Signals // + ///////////////////// + + // `sel_mux` selects the output data among the incoming or internally generated data. + // MuxFifo: data from external (msg_data_i) + // MuxPrefix: bytepad(encode_string(N)||encode_string(S), ) + // MuxFuncPad: function_pad with end of message + // MuxZeroEnd: all 0 + mux_sel_e sel_mux; + + // `wr_message` indicates the number of entries sent to keccak round per + // block. The value shall be enough to cover Maximum entry of the Keccak + // storage as defined in abr_sha3_pkg, `$clog2(MsgEntries+1)`. Logically, + // it is not needed to have more than MsgEntries but for safety in case of + // SHA3 context switch resuming the SHA3 from the middle of sponge + // construction. If needed, the software should be able to write whole 1600 + // bits. The `wr_message` is used to check sent_blocksize. + logic [MsgCountW-1:0] wr_message; + logic inc_wrmsg, clr_wrmsg; + + + logic update_serial_buffer; + logic rst_serial_buffer; + logic [MsgAddrW-1:0] serial_buffer_wraddr; + logic [MsgWidth-1:0] serial_buffer_wrdata [Share]; + + // This primitive is used to place a hardened counter + // SEC_CM: CTR.REDUN + abr_prim_count #( + .Width(MsgCountW) + ) u_wrmsg_count ( + .clk_i, + .rst_b, + .clr_i(clr_wrmsg | zeroize), + .set_i(1'b0), + .set_cnt_i(MsgCountW'(0)), + .incr_en_i(inc_wrmsg), + .decr_en_i(1'b0), + .step_i(MsgCountW'(1)), + .cnt_o(wr_message), + .cnt_next_o(), + .err_o(msg_count_error_o) + ); + + assign inc_wrmsg = update_serial_buffer; + assign rst_serial_buffer = clr_wrmsg | zeroize; + // Prefix index to slice the `prefix` n-bits into multiple of 64bit. + logic [MsgAddrW-1:0] prefix_index; + assign prefix_index = (wr_message < block_addr_limit) ? wr_message : '0; + + // fsm_keccak_valid is an output signal from FSM which to send data generated + // inside the pad logic to keccak_round + logic fsm_keccak_valid; + + // hold_msg to prevent message from being forwarded into keccak_round and + // acked. Mainly the usage is to hold the message and initiates the + // keccak_round for current block. + logic hold_msg; + + // latch the partial write. Latched data is used for funcpad_merged + logic en_msgbuf; + logic clr_msgbuf; + + /////////////////// + // State Machine // + /////////////////// + + // Inputs + + // FSM moves to StPrefix only when cSHAKE is enabled + logic mode_eq_cshake; + assign mode_eq_cshake = (mode_i == CShake) ? 1'b 1 : 1'b 0; + + // `sent_blocksize` indicates the pad logic pushed block size data into + // keccak round logic. + logic sent_blocksize; + + assign sent_blocksize = (wr_message == block_addr_limit) ? 1'b 1 : 1'b 0; + + // `keccak_ack` indicates the request is accepted in keccak_round + logic keccak_ack; + + assign keccak_ack = keccak_ready_i ; + + // msg_partial indicates the incoming message is partial write or not. + // This is used to check if the incoming message need to be latched inside or + // not. If no partial message is at the end, msg_buf doesn't have to latch + // msg_data_i. It is assumed that the partial message is permitted only at + // the end of the message. + // Shall be used with msg_valid_i together. + logic msg_partial; + assign msg_partial = (&msg_strb_i != 1'b 1); + + + // `process_latched` latches the `process_i` input before it is seen in the + // FSM. + logic process_latched; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + process_latched <= 1'b 0; + end else if (process_i) begin + process_latched <= 1'b 1; + end else if (start_i) begin + process_latched <= 1'b0; + end + end + + // State Register =========================================================== + pad_st_e st, st_d; + + `ABR_PRIM_FLOP_SPARSE_FSM(u_state_regs, st_d, st, pad_st_e, StPadIdle) + + // `end_of_block` indicates current beat is end of the block + // It shall set when the address reaches to the end of the block. End address + // is set by the strength_i, which is `block_addr_limit`. + logic end_of_block; + + assign end_of_block = ((wr_message + 1'b1) == block_addr_limit) ? 1'b 1 : 1'b 0; + + + // Next logic and output logic ============================================== + // SEC_CM: ABSORBED.CTRL.MUBI + abr_prim_mubi_pkg::mubi4_t absorbed_d; + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) absorbed_o <= abr_prim_mubi_pkg::MuBi4False; + else if (zeroize) absorbed_o <= abr_prim_mubi_pkg::MuBi4False; + else absorbed_o <= absorbed_d; + end + + always_comb begin + st_d = st; + + // FSM output : default values + keccak_run_o = 1'b 0; + sel_mux = MuxNone; + + fsm_keccak_valid = 1'b 0; + + hold_msg = 1'b 0; + clr_wrmsg = 1'b 0; + + en_msgbuf = 1'b 0; + clr_msgbuf = 1'b 0; + + absorbed_d = abr_prim_mubi_pkg::MuBi4False; + + sparse_fsm_error_o = 1'b 0; + + unique case (st) + + // In Idle state, the FSM checks if the software (or upper FSM) initiates + // the hash process. If `start_i` is asserted (assume it is pulse), FSM + // starts to push the data into the keccak round logic. Depending on the + // hashing mode, FSM may push additional prefex in front of the actual + // message. It means, the message could be back-pressured until the first + // prefix is processed. + StPadIdle: begin + if (start_i) begin + // If cSHAKE, move to Prefix state + if (mode_eq_cshake) begin + st_d = StPrefix; + end else begin + st_d = StMessage; + end + end else begin + st_d = StPadIdle; + end + end + + // At Prefix state, FSM pushes + // `bytepad(encode_string(N)||encode_string(S), 168or136)`. The software + // already prepared `encode_string(N) || encode_string(S)` in the regs. + // So, the FSM adds 2Byte in front of ns_data_i, which is an encoded + // block size (see `encoded_bytepad` below) + // After pushing the prefix, it initiates the hash process and move to + // Message state. + StPrefix: begin + sel_mux = MuxPrefix; + + if (sent_blocksize) begin + st_d = StPrefixWait; + + keccak_run_o = 1'b 1; + fsm_keccak_valid = 1'b 0; + clr_wrmsg = 1'b 1; + end else begin + st_d = StPrefix; + + fsm_keccak_valid = 1'b 1; + end + end + + StPrefixWait: begin + sel_mux = MuxPrefix; + + if (keccak_complete_i) begin + st_d = StMessage; + end else begin + st_d = StPrefixWait; + end + end + + // Message state pushes the incoming message into keccak round logic. + // It forwards the message while counting the data and if it reaches + // the block size, it triggers the keccak round to run. If `process` is + // set, it moves to Pad state. + StMessage: begin + sel_mux = MuxFifo; + + if (msg_valid_i && msg_partial) begin + st_d = StMessage; + + en_msgbuf = 1'b 1; + end else if (sent_blocksize & keccak_ack) begin + // Check block completion first even process is set. + st_d = StMessage; + + keccak_run_o = 1'b 1; + clr_wrmsg = 1'b 1; + hold_msg = 1'b 1; + end else if (sent_blocksize & ~keccak_ack) begin + // Check block completion first even process is set. + st_d = StMessage; + + hold_msg = 1'b 1; + end else if (process_latched || process_i) begin + st_d = StPad; + + // Not asserting the msg_ready_o + hold_msg = 1'b 1; + end else begin + st_d = StMessage; + + end + end + + // Keccak round is running, we can send another block but can't start a + // new round until the current one completes. + StMessageWait: begin + sel_mux = MuxFifo; + + if (msg_valid_i && msg_partial) begin + st_d = StMessageWait; + + en_msgbuf = 1'b 1; + end else if (sent_blocksize) begin + st_d = StMessageWait; + + hold_msg = 1'b 1; + end else if (process_i) begin + st_d = StPad; + + // Not asserting the msg_ready_o + hold_msg = 1'b 1; + end else if (keccak_complete_i) begin + st_d = StMessage; + end else begin + st_d = StMessageWait; + end + end + + // Pad state just pushes the ending suffix. Depending on the mode, the + // padding value is unique. SHA3 adds 2'b10, SHAKE adds 4'b1111, and + // cSHAKE adds 2'b 00. Refer `function_pad`. The signal has one more bit + // defined to accomodate first 1 bit of `pad10*1()` function. + StPad: begin + sel_mux = MuxFuncPad; + + fsm_keccak_valid = 1'b 1; + + if (end_of_block && keccak_ack) begin + // If padding is the last block, don't have to move to StPad01, just + // run Keccak and complete + st_d = StPadRun; + + // always clear the latched msgbuf + clr_msgbuf = 1'b 1; + //clr_wrmsg = 1'b 1; + end else if (end_of_block && ~keccak_ack) begin + // Wait until Keccak is available + st_d = StPad; + + fsm_keccak_valid = 1'b 0; + end else begin + st_d = StPad01; + clr_msgbuf = 1'b 1; + end + end + + StPadRun: begin + st_d = StPadFlush; + + keccak_run_o = 1'b 1; + clr_wrmsg = 1'b 1; + end + + // Pad01 pushes the end bit of pad10*1() function. As keccak accepts byte + // size only, StPad always pushes partial (5bits). So at this state, it + // pushes rest of 3bits. If the data pushed in StPad is the last byte of + // the block, then Pad01 pushes to the same byte, if not, it first + // zero-fill the block then pad 1 to the end. + StPad01: begin + sel_mux = MuxZeroEnd; + + // There's no chance StPad01 can be a start of the block. So can be + // discard that the sent_blocksize is set at the beginning. + if (sent_blocksize && keccak_ack) begin + st_d = StPadFlush; + + fsm_keccak_valid = 1'b 0; + keccak_run_o = 1'b 1; + clr_wrmsg = 1'b 1; + end else if (sent_blocksize && ~keccak_ack) begin + st_d = StPad01; + + fsm_keccak_valid = 1'b 0; + end else begin + st_d = StPad01; + + fsm_keccak_valid = 1'b 1; + end + end + + StPadFlush: begin + // Wait completion from keccak_round or wait SW indicator. + clr_wrmsg = 1'b 1; + clr_msgbuf = 1'b 1; + + if (keccak_complete_i) begin + st_d = StPadIdle; + + absorbed_d = abr_prim_mubi_pkg::MuBi4True; + end else begin + st_d = StPadFlush; + end + end + + StTerminalError: begin + // this state is terminal + st_d = st; + sparse_fsm_error_o = 1'b 1; + end + + default: begin + // this state is terminal + st_d = StTerminalError; + sparse_fsm_error_o = 1'b 1; + end + endcase + + if (zeroize) st_d = StPadIdle; + + end + + ////////////// + // Datapath // + ////////////// + + // `encode_bytepad` represents the first two bytes of bytepad() + // It depends on the block size. We can reuse KeccakRate + // 10000000 || 00010101 // 168 + // 10000000 || 00010001 // 136 + logic [15:0] encode_bytepad; + + assign encode_bytepad = encode_bytepad_len(strength_i); + + // Prefix size ============================================================== + // Prefix represents bytepad(encode_string(N) || encode_string(S), 168 or 136) + // encode_string(N) || encode_string(S) is prepared by the software and given + // through `ns_data_i`. The first part of bytepad is determined by the + // `strength_i` and stored into `encode_bytepad`. + + // It is assumed that the prefix always smaller than the block size. + logic [PrefixSize*8-1:0] prefix; + + assign prefix = {ns_data_i, encode_bytepad}; + + logic [MsgWidth-1:0] prefix_sliced; + logic [MsgWidth-1:0] prefix_data [Share]; + + abr_prim_slicer #( + .InW (PrefixSize*8), + .IndexW(MsgAddrW), + .OutW(MsgWidth) + ) u_prefix_slicer ( + .sel_i (prefix_index), + .data_i (prefix), + .data_o (prefix_sliced) + ); + + if (EnMasking) begin : gen_prefix_masked + // If Masking is enabled, prefix is two share. + assign prefix_data[0] = '0; + assign prefix_data[1] = prefix_sliced; + end else begin : gen_prefix_unmasked + // If Unmasked, only one share exists. + assign prefix_data[0] = prefix_sliced; + end + + // ========================================================================== + // function_pad is the unique value padded at the end of the message based on + // the function among SHA3, SHAKE, cSHAKE. The standard mentioned that SHA3 + // pads `01` , SHAKE pads `1111`, and cSHAKE pads `00`. + // + // Then pad10*1() function follows. It adds `1` first then fill 0 until it + // reaches the block size -1, then adds `1`. + // + // It means always `1` is followed by the function pad. + logic [4:0] funcpad; + + logic [MsgWidth-1:0] funcpad_data [Share]; + + always_comb begin + unique case (mode_i) + Sha3: funcpad = 5'b 00110; + Shake: funcpad = 5'b 11111; + CShake: funcpad = 5'b 00100; + + default: begin + // Just create non-padding but pad10*1 only + funcpad = 5'b 00001; + end + endcase + end + + // ========================================================================== + // `zero_with_endbit` contains all zero unless the message is for the last + // MsgWidth beat in the block. If it is the end of the block, the last bit + // will be set to complete pad10*1() functionality. + logic [MsgWidth-1:0] zero_with_endbit [Share]; + + if (EnMasking) begin : gen_zeroend_masked + assign zero_with_endbit[0] = '0; + assign zero_with_endbit[1][MsgWidth-1] = end_of_block; + assign zero_with_endbit[1][MsgWidth-2:0] = '0; + end else begin : gen_zeroend_unmasked + assign zero_with_endbit[0][MsgWidth-1] = end_of_block; + assign zero_with_endbit[0][MsgWidth-2:0] = '0; + end + + // ========================================================================== + // Data mux for writing to serial buffer + + always_comb serial_buffer_wraddr = (wr_message < block_addr_limit) ? wr_message : '0; + + always_comb begin + unique case (sel_mux) + MuxFifo: serial_buffer_wrdata = msg_data_i; + MuxPrefix: serial_buffer_wrdata = prefix_data; + MuxFuncPad: serial_buffer_wrdata = funcpad_data; + MuxZeroEnd: serial_buffer_wrdata = zero_with_endbit; + + // MuxNone + default: serial_buffer_wrdata = '{default:'0}; + endcase + end + + always_comb begin + unique case (sel_mux) + MuxFifo: update_serial_buffer = msg_valid_i & ~hold_msg & ~en_msgbuf; + MuxPrefix: update_serial_buffer = fsm_keccak_valid; + MuxFuncPad: update_serial_buffer = fsm_keccak_valid; + MuxZeroEnd: update_serial_buffer = fsm_keccak_valid; + + // MuxNone + default: update_serial_buffer = 1'b 0; + endcase + end + + always_comb begin + unique case (sel_mux) + MuxFifo: msg_ready_o = en_msgbuf | (msg_valid_i & ~hold_msg); + MuxPrefix: msg_ready_o = 1'b 0; + MuxFuncPad: msg_ready_o = 1'b 0; + MuxZeroEnd: msg_ready_o = 1'b 0; + + // MuxNone + default: msg_ready_o = 1'b 0; + endcase + end + + // abr_prim_packer : packing to 64bit to update keccak storage + // two abr_prim_packer in this module are used to pack the data received from + // upper layer (KMAC core) and also the 5bit padding bits. + // It is assumed that the message from upper layer could be partial at the + // end of the message. Then the 2 or 4bit padding is required. It can be + // handled by some custom logic or could be done by abr_prim_packer. + // If packer is used, the MSG_FIFO doesn't have to have another abr_prim_packer + // in front of the FIFO. This logic can handle the partial writes from the + // software. + // + // If a custom logic is implemented here, abr_prim_packer is necessary in front + // of the FIFO, as this logic only appends at the end of the message when + // `process_i` is asserted. Also, in this case, even abr_prim_packer is not + // needed, still 64bit registers to latch the partial write is required. + // If not, the logic has to delay the acceptance of the incoming write + // accesses. It may trigger the back-pressuring in some case which may result + // that the software(or upper layer) may not set process_i. + // + // For custom logic, it could be implemented by the 8 mux selection. + // for instance: (subject to be changed) + // unique case (sent_byte[2:0]) // generated from msg_strb_i + // 3'b 000: funcpad_merged = {end_of_block, 63'(function_pad) }; + // 3'b 001: funcpad_merged = {end_of_block, 55'(function_pad), msg_data_i[ 7:0]}; + // 3'b 010: funcpad_merged = {end_of_block, 47'(function_pad), msg_data_i[15:0]}; + // 3'b 011: funcpad_merged = {end_of_block, 39'(function_pad), msg_data_i[23:0]}; + // 3'b 100: funcpad_merged = {end_of_block, 31'(function_pad), msg_data_i[31:0]}; + // 3'b 101: funcpad_merged = {end_of_block, 23'(function_pad), msg_data_i[39:0]}; + // 3'b 110: funcpad_merged = {end_of_block, 15'(function_pad), msg_data_i[47:0]}; + // 3'b 111: funcpad_merged = {end_of_block, 7'(function_pad), msg_data_i[55:0]}; + // default: funcpad_merged = '0; + // endcase + + // internal buffer to store partial write. It doesn't have to store last byte as it + // stores only when partial write. + logic [MsgWidth-8-1:0] msg_buf [Share]; + logic [MsgStrbW-1-1:0] msg_strb; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + msg_buf <= '{default:'0}; + msg_strb <= '0; + end else if (en_msgbuf) begin + for (int i = 0 ; i < Share ; i++) begin + msg_buf[i] <= msg_data_i[i][0+:(MsgWidth-8)]; + end + msg_strb <= msg_strb_i[0+:(MsgStrbW-1)]; + end else if (clr_msgbuf) begin + msg_buf <= '{default:'0}; + msg_strb <= '0; + end + end + + //TODO Fix hardcoded mux for masking + if (EnMasking) begin : gen_funcpad_data_masked + always_comb begin + unique case (msg_strb) + 7'b 000_0000: begin + funcpad_data[0] = '0; + funcpad_data[1] = {end_of_block, 63'(funcpad) }; + end + 7'b 000_0001: begin + funcpad_data[0] = {56'h0, msg_buf[0][ 7:0]}; + funcpad_data[1] = {end_of_block, 55'(funcpad), msg_buf[1][ 7:0]}; + end + 7'b 000_0011: begin + funcpad_data[0] = {48'h0, msg_buf[0][15:0]}; + funcpad_data[1] = {end_of_block, 47'(funcpad), msg_buf[1][15:0]}; + end + 7'b 000_0111: begin + funcpad_data[0] = {40'h0, msg_buf[0][23:0]}; + funcpad_data[1] = {end_of_block, 39'(funcpad), msg_buf[1][23:0]}; + end + 7'b 000_1111: begin + funcpad_data[0] = {32'h0, msg_buf[0][31:0]}; + funcpad_data[1] = {end_of_block, 31'(funcpad), msg_buf[1][31:0]}; + end + 7'b 001_1111: begin + funcpad_data[0] = {24'h0, msg_buf[0][39:0]}; + funcpad_data[1] = {end_of_block, 23'(funcpad), msg_buf[1][39:0]}; + end + 7'b 011_1111: begin + funcpad_data[0] = {16'h0, msg_buf[0][47:0]}; + funcpad_data[1] = {end_of_block, 15'(funcpad), msg_buf[1][47:0]}; + end + 7'b 111_1111: begin + funcpad_data[0] = { 8'h0, msg_buf[0][55:0]}; + funcpad_data[1] = {end_of_block, 7'(funcpad), msg_buf[1][55:0]}; + end + + default: funcpad_data = '{default:'0}; + endcase + end + end else if (MsgWidth == 128) begin : gen_128_funcpad_data_unmasked + always_comb begin + unique case (msg_strb) + 15'b 000_0000_0000_0000: funcpad_data[0] = {end_of_block, 127'(funcpad) }; + 15'b 000_0000_0000_0001: funcpad_data[0] = {end_of_block, 119'(funcpad), msg_buf[0][ 7:0]}; + 15'b 000_0000_0000_0011: funcpad_data[0] = {end_of_block, 111'(funcpad), msg_buf[0][15:0]}; + 15'b 000_0000_0000_0111: funcpad_data[0] = {end_of_block, 103'(funcpad), msg_buf[0][23:0]}; + 15'b 000_0000_0000_1111: funcpad_data[0] = {end_of_block, 95'(funcpad), msg_buf[0][31:0]}; + 15'b 000_0000_0001_1111: funcpad_data[0] = {end_of_block, 87'(funcpad), msg_buf[0][39:0]}; + 15'b 000_0000_0011_1111: funcpad_data[0] = {end_of_block, 79'(funcpad), msg_buf[0][47:0]}; + 15'b 000_0000_0111_1111: funcpad_data[0] = {end_of_block, 71'(funcpad), msg_buf[0][55:0]}; + 15'b 000_0000_1111_1111: funcpad_data[0] = {end_of_block, 63'(funcpad), msg_buf[0][63:0]}; + 15'b 000_0001_1111_1111: funcpad_data[0] = {end_of_block, 55'(funcpad), msg_buf[0][71:0]}; + 15'b 000_0011_1111_1111: funcpad_data[0] = {end_of_block, 47'(funcpad), msg_buf[0][79:0]}; + 15'b 000_0111_1111_1111: funcpad_data[0] = {end_of_block, 39'(funcpad), msg_buf[0][87:0]}; + 15'b 000_1111_1111_1111: funcpad_data[0] = {end_of_block, 31'(funcpad), msg_buf[0][95:0]}; + 15'b 001_1111_1111_1111: funcpad_data[0] = {end_of_block, 23'(funcpad), msg_buf[0][103:0]}; + 15'b 011_1111_1111_1111: funcpad_data[0] = {end_of_block, 15'(funcpad), msg_buf[0][111:0]}; + 15'b 111_1111_1111_1111: funcpad_data[0] = {end_of_block, 7'(funcpad), msg_buf[0][119:0]}; + default: funcpad_data = '{default:'0}; + endcase + end + end else if (MsgWidth == 64) begin : gen_64_funcpad_data_unmasked + always_comb begin + unique case (msg_strb) + 7'b 000_0000: funcpad_data[0] = {end_of_block, 63'(funcpad) }; + 7'b 000_0001: funcpad_data[0] = {end_of_block, 55'(funcpad), msg_buf[0][ 7:0]}; + 7'b 000_0011: funcpad_data[0] = {end_of_block, 47'(funcpad), msg_buf[0][15:0]}; + 7'b 000_0111: funcpad_data[0] = {end_of_block, 39'(funcpad), msg_buf[0][23:0]}; + 7'b 000_1111: funcpad_data[0] = {end_of_block, 31'(funcpad), msg_buf[0][31:0]}; + 7'b 001_1111: funcpad_data[0] = {end_of_block, 23'(funcpad), msg_buf[0][39:0]}; + 7'b 011_1111: funcpad_data[0] = {end_of_block, 15'(funcpad), msg_buf[0][47:0]}; + 7'b 111_1111: funcpad_data[0] = {end_of_block, 7'(funcpad), msg_buf[0][55:0]}; + default: funcpad_data = '{default:'0}; + endcase + end + end + + logic [MsgEntries-1:0][MsgWidth-1:0] serial_buffer [Share]; + logic [MsgEntries-1:0][MsgWidth-1:0] serial_buffer_d [Share]; + + assign keccak_data_o = serial_buffer; + + // Serial input buffer + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + serial_buffer <= '{default:'0}; + end else if (rst_serial_buffer) begin + serial_buffer <= '{default:'0}; + end else if (update_serial_buffer) begin + serial_buffer <= serial_buffer_d; + end + end + + always_comb begin + serial_buffer_d = serial_buffer; + for (int j = 0 ; j < Share ; j++) begin + for (int unsigned i = 0 ; i < MsgEntries ; i++) begin + // TODO: handle If Width is not integer divisable by MsgWidth + // Currently it is not allowed to have partial write + // Please see the Assertion `WidthDivisableByMsgWidth_A` + if (serial_buffer_wraddr == i[MsgAddrW-1:0]) begin + serial_buffer_d[j][i] = serial_buffer_wrdata[j]; + end else begin + serial_buffer_d[j][i] = serial_buffer[j][i]; + end + end // for i + end // for j + end + + + //////////////// + // Assertions // + //////////////// + + // Prefix size is smaller than the smallest Keccak Block Size, which is 72 bytes. + `ABR_ASSERT_INIT(PrefixLessThanBlock_A, PrefixSize/8 < KeccakRate[4]) + + // Some part of datapath in sha3pad assumes Data width as 64bit. + // If data width need to be changed, funcpad_data part should be changed too. + // Also, The blocksize shall be divided by MsgWidth, which means, MsgWidth + // can be {16, 32, 64} even funcpad_data mux is fully flexible. + //`ABR_ASSERT_INIT(MsgWidthidth_A, MsgWidth == 64) + + // Assume pulse signals: start, process, done + `ABR_ASSUME(StartPulse_A, start_i |=> !start_i) + `ABR_ASSUME(ProcessPulse_A, process_i |=> !process_i) + + // ABR_ASSERT output pulse signals: absorbed_o, keccak_run_o + `ABR_ASSERT(AbsorbedPulse_A, + abr_prim_mubi_pkg::mubi4_test_true_strict(absorbed_o) |=> + abr_prim_mubi_pkg::mubi4_test_false_strict(absorbed_o)) + `ABR_ASSERT(KeccakRunPulse_A, keccak_run_o |=> !keccak_run_o) + + // start_i, process_i cannot set high at the same time + `ABR_ASSUME(StartProcessMutex_a, + $onehot0({ + start_i, + process_i + })) + +`ifndef SYNTHESIS + // Process only asserts after start and all message are fed. + // These valid signals are qualifier of FPV to trigger the control signal + // It is a little bit hard to specify these criteria in SVA property so creating + // qualifiers in RTL form is easier. + logic start_valid, process_valid, absorb_valid, done_valid; + + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + start_valid <= 1'b 1; + end else if (zeroize) begin + start_valid <= 1'b 1; + end else if (start_i) begin + start_valid <= 1'b 0; + end else if (process_i) begin + start_valid <= 1'b 1; + end + end + always_ff @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + process_valid <= 1'b 0; + end else if (zeroize) begin + process_valid <= 1'b 0; + end else if (start_i) begin + process_valid <= 1'b 1; + end else if (process_i) begin + process_valid <= 1'b 0; + end + end + + // Message can be fed in between start_i and process_i. + `ABR_ASSUME(MessageCondition_M, msg_valid_i && msg_ready_o |-> process_valid && !process_i) + + // Message ready should be asserted only in between start_i and process_i + `ABR_ASSERT(MsgReadyCondition_A, msg_ready_o |-> process_valid && !process_i) + + `ABR_ASSUME(ProcessCondition_M, process_i |-> process_valid) + `ABR_ASSUME(StartCondition_M, start_i |-> start_valid) + + // Assume mode_i and strength_i are stable during the operation + // This will be guarded at the kmac top level + `ABR_ASSUME(ModeStableDuringOp_M, + $changed(mode_i) |-> start_valid) + `ABR_ASSUME(StrengthStableDuringOp_M, + $changed(strength_i) |-> start_valid) + +`endif // SYNTHESIS + + // If `process_i` is asserted, eventually sha3pad trigger run signal + `ABR_ASSERT(ProcessToRun_A, process_i |-> strong(##[2:$] keccak_run_o), + clk_i, !rst_b) + + // If process_i asserted, completion shall be asserted shall be asserted + //`ABR_ASSERT(ProcessToAbsorbed_A, process_i |=> strong(##[24*Share:$] absorbed_o)) + + + // Assumption of input mode_i and strength_i + // SHA3 variants: SHA3-224, SHA3-256, SHA3-384, SHA3-512 + // SHAKE, cSHAKE variants: SHAKE128, SHAKE256, cSHAKE128, cSHAKE256 + `ABR_ASSUME_FPV(ModeStrengthCombinations_M, + start_i |-> + (mode_i == Sha3 && (strength_i inside {L224, L256, L384, L512})) || + ((mode_i == Shake || mode_i == CShake) && (strength_i inside {L128, L256})), + clk_i, !rst_b) + + // Keccak control interface + // Keccak run triggered -> completion should come + `ABR_ASSUME(RunThenComplete_M, + keccak_run_o |-> strong(##[24*Share:$] keccak_complete_i), + clk_i, !rst_b) + + // No partial write is allowed for Message FIFO interface + `ABR_ASSUME(NoPartialMsgFifo_M, + update_serial_buffer && (sel_mux == MuxFifo) |-> (&msg_strb_i) == 1'b1, + clk_i, !rst_b) + + // When transaction is stored into msg_buf, it shall be partial write. + `ABR_ASSUME(AlwaysPartialMsgBuf_M, + en_msgbuf |-> msg_valid_i && (msg_strb_i[MsgStrbW-1] == 1'b0), + clk_i, !rst_b) + + // if partial write comes and is acked, then no more msg_valid_i until + // next message + `ABR_ASSUME(PartialEndOfMsg_M, + msg_valid_i && msg_ready_o && msg_partial |=> + !msg_valid_i ##[1:$] $stable(msg_valid_i) ##1 start_i, + clk_i, !rst_b) + + // At the first clock in StPad01 state, sent_blocksize shall not be set + `ABR_ASSERT(Pad01NotAttheEndOfBlock_A, + (st == StPad && st_d == StPad01) |-> !end_of_block, + clk_i, !rst_b) + + // When data sent to the keccak_round, the address should be in the range + `ABR_ASSERT(KeccakAddrInRange_A, + update_serial_buffer |-> serial_buffer_wraddr < KeccakRate[strength_i], + clk_i, !rst_b) + + // NS data shall be stable during the operation. + //`ABR_ASSUME(NsStableInProcess_A, + // $stable(ns_data_i) throughout(start_i ##[1:$] process_i ##[1:$] absorbed_o), + // clk_i, !rst_b) + + // Functional Coverage + `ABR_COVER(StMessageFeed_C, st == StMessage) + `ABR_COVER(StPad_C, st == StPad01 && sent_blocksize) + `ABR_COVER(StPadSendMsg_C, st == StPad01 && keccak_ack) + `ABR_COVER(StComplete_C, st == StPadFlush) +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/stimulus/tests/directed/abr_sha3_rand_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/stimulus/tests/directed/abr_sha3_rand_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..0238a737413919fe219dcc80997988e5b54fb446 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/stimulus/tests/directed/abr_sha3_rand_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: abr_sha3_rand_test +seed: ${PLAYBOOK_RANDOM_SEED} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/stimulus/tests/directed/five_squeeze_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/stimulus/tests/directed/five_squeeze_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..81bf5aa48cd0f1982c021cf8f8e98a52100dca91 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/stimulus/tests/directed/five_squeeze_test.yml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +plusargs: + - +SHA3_TEST='five_squeeze_test' + +testname: five_squeeze_test +seed: ${PLAYBOOK_RANDOM_SEED} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3.py b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3.py new file mode 100644 index 0000000000000000000000000000000000000000..2bbafd33549d6e343dd9f4bea4f5f80a946a2b48 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3.py @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import hashlib +import sys +import os +import binascii +import re + +def sha3_256(m_hex_str): + #m_hex_str = hex(m)[2:] + #if len(m_hex_str) & 1 == 1: + # m_hex_str="0"+m_hex_str + m_ascii_str = binascii.unhexlify(m_hex_str) + m_hashed = hashlib.sha3_256(m_ascii_str).digest() + return format(int.from_bytes( m_hashed , byteorder='little', signed=False ), 'x') + +def sha3_512(m_hex_str): + #m_hex_str = hex(m)[2:] + #if len(m_hex_str) & 1 == 1: + # m_hex_str="0"+m_hex_str + m_ascii_str = binascii.unhexlify(m_hex_str) + m_hashed = hashlib.sha3_512(m_ascii_str).digest() + return format(int.from_bytes( m_hashed , byteorder='little', signed=False ), 'x') + +def shake_128(m_hex_str,byte_num): + #m_hex_str = hex(m)[2:] + #if len(m_hex_str) & 1 == 1: + # m_hex_str="0"+m_hex_str + m_ascii_str = binascii.unhexlify(m_hex_str) + m_hashed = hashlib.shake_128(m_ascii_str).digest(byte_num) + return format(int.from_bytes( m_hashed , byteorder='little', signed=False ), 'x') + +def shake_256(m_hex_str,byte_num): + #m_hex_str = hex(m)[2:] + #if len(m_hex_str) & 1 == 1: + # m_hex_str="0"+m_hex_str + m_ascii_str = binascii.unhexlify(m_hex_str) + m_hashed = hashlib.shake_256(m_ascii_str).digest(byte_num) + return format(int.from_bytes( m_hashed , byteorder='little', signed=False ), 'x') + +#open the input vector file for reading +input_vectors = open("input_vectors.txt", "r") +exp_results = open("exp_results.txt", "w") + +Lines = input_vectors.readlines() + +for line in Lines: + fields = line.split() + mode = fields[0] + strength = fields[1] + valid_bytes_hex = fields[2] + vector_raw = fields[3] + valid_bytes_onehot = int(valid_bytes_hex, 16) + valid_bytes_onehot = bin(valid_bytes_onehot)[2:] + valid_bytes = valid_bytes_onehot.count('1') + slice_start = (len(vector_raw)-(valid_bytes*2)) + vector = vector_raw[slice_start:] + vector_ba = bytearray.fromhex(vector) + vector_ba.reverse() + m = vector_ba.hex() + if ((mode == "Shake") & (strength == "L256")): + digest = shake_256(m,1008) + elif ((mode == "Shake") & (strength == "L128")): + digest = shake_128(m,1008) + elif ((mode == "Sha3") & (strength == "L512")): + digest = sha3_512(m) + elif ((mode == "Sha3") & (strength == "L256")): + digest = sha3_256(m) + exp_results.write(str(mode)+" "+str(strength)+" "+str(digest)+"\n") diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..ca98e62059a340e33da60ef2cee20040843e9e26 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3_tb.sv @@ -0,0 +1,594 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// abr_sha3_tb.sv +// -------- +// +//====================================================================== + +import "DPI-C" function string getenv(input string env_name); + +module abr_sha3_tb + import abr_sha3_pkg::*; + import abr_sha3_tb_pkg::*; + import abr_prim_alert_pkg::*; + import mldsa_sampler_pkg::*; +( +`ifdef VERILATOR + input bit clk_tb +`endif + ); + + //----------------------- + // SHA3parameters + //----------------------- + // Keccak Rounds per clock + localparam int RoundsPerClock = 2; + // Do not enable masking + localparam bit Sha3EnMasking = 0; + // derived parameter + localparam int Sha3Share = (Sha3EnMasking) ? 2 : 1; + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + `ifndef VERILATOR + int MAX_CYCLES; + int VEC_CNT; + string sha3_testname; + + initial begin + // To use this from the command line, add "+MAX_CYCLES=" + // to override the sim timeout + if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin + $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES); + end else begin + MAX_CYCLES = 20_0000; + $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES); + end + if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin + $info("Received argument +VEC_CNT, with value %d", VEC_CNT); + end else begin + VEC_CNT = 10; + $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT); + end + end + `else + parameter MAX_CYCLES = 20_0000; + `endif + + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 5; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; + +`ifndef VERILATOR + reg clk_tb; +`endif + reg clk_i; + reg reset_n_tb; + reg rst_b; + reg [31 : 0] read_data; + + logic msg_start; + logic msg_valid; + logic [MsgStrbW-1:0] msg_strobe; + logic [MsgWidth-1:0] msg_data[Sha3Share]; + logic sha3_msg_rdy; + logic sha3_start; + logic sha3_process; + logic sha3_run; + + abr_prim_mubi_pkg::mubi4_t sha3_done; + abr_prim_mubi_pkg::mubi4_t sha3_absorbed; + + logic sha3_squeezing; + + logic sha3_block_processed; + + abr_sha3_pkg::sha3_st_e sha3_fsm; + abr_sha3_pkg::err_t sha3_err; + + abr_sha3_pkg::sha3_mode_e mode; + abr_sha3_pkg::keccak_strength_e strength; + + logic sha3_state_vld; + logic [abr_sha3_pkg::StateW-1:0] sha3_state[Sha3Share]; + + logic sha3_state_error; + logic sha3_count_error; + logic sha3_rst_storage_err; + + assign clk_i = clk_tb; + assign rst_b = reset_n_tb; + + + string vector_filename,exp_res_filename; + assign exp_res_filename = "exp_results.txt"; + assign vector_filename = "input_vectors.txt"; + + keccak_test_vector_t test_vector_q[$]; + exp_results_u exp_result; + string exp_strength, exp_mode; + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + + // SHA3 hashing engine + abr_sha3 #( + .RoundsPerClock(RoundsPerClock), + .EnMasking (Sha3EnMasking) + ) dut ( + .clk_i (clk_tb), + .rst_b (reset_n_tb), + .zeroize (1'b0), + // MSG_FIFO interface + .msg_start_i (msg_start), + .msg_valid_i (msg_valid), + .msg_data_i (msg_data), + .msg_strb_i (msg_strobe), + .msg_ready_o (sha3_msg_rdy), + + // Entropy interface - not using + .rand_valid_i (1'b0), + .rand_early_i (1'b0), + .rand_data_i ('0), + .rand_aux_i ('0), + .rand_consumed_o (), + + // N, S: Used in cSHAKE mode + .ns_data_i ('0), // ns_prefix), + + // Configurations + .mode_i (mode), + .strength_i (strength), + + // Controls (CMD register) + .start_i (sha3_start ), + .process_i (sha3_process ), + .run_i (sha3_run ), // For squeeze + .done_i (sha3_done ), + + .absorbed_o (sha3_absorbed), + .squeezing_o (sha3_squeezing), + + .block_processed_o (sha3_block_processed), + + .sha3_fsm_o (sha3_fsm), + + .state_valid_o (sha3_state_vld), + .state_valid_hold_i('0), + .state_o (sha3_state), + + .error_o (sha3_err), + .sparse_fsm_error_o (sha3_state_error), + .count_error_o (sha3_count_error), + .keccak_storage_rst_error_o (sha3_rst_storage_err) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- +`ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen +`endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + + // Test timeout monitor + if(cycle_ctr == MAX_CYCLES) begin + $error("Hit max cycle count (%0d) .. stopping",cycle_ctr); + $finish; + end + end + + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + + repeat (2) @(posedge clk_tb); + + $display(""); + end + endtask // reset_dut + + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + error_ctr = '0; + tc_ctr = '0; +`ifndef VERILATOR + clk_tb = 0; +`endif + reset_n_tb = 0; + + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L256; + + msg_start = 0; + msg_valid = 0; + msg_strobe = '0; + msg_data[0] = '0; + + sha3_start = 0; + sha3_process = 0; + sha3_done = abr_prim_mubi_pkg::MuBi4False; + sha3_run = 0; + end + endtask // init_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + //---------------------------------------------------------------- + // write_single_msg() + // + // Write the given msg to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_single_msg(input [MsgWidth-1:0] msg_i, input [MsgStrbW-1:0] msg_strobe_i); + begin + //$display("[%t] write_single_msg(msg=0x%x)", $time, msg_i); + //$display("[%t] write_single_msg(msg_strobe=0x%x)", $time, msg_strobe_i); + + msg_valid <= 1; + msg_data[0] <= msg_i; + msg_strobe <= msg_strobe_i; + + //don't like this, but solves the timing issue + @(negedge clk_tb); + //Wait until msg rdy gets asserted + wait (sha3_msg_rdy == 1); + + @(posedge clk_tb); + msg_valid <= 0; + msg_data[0] <= 'x; + msg_strobe <= 'x; + + end + endtask // write_single_msg + + //---------------------------------------------------------------- + // gen_rand_test_vectors() + //---------------------------------------------------------------- + task gen_rand_test_vectors; + int fd_w; + + test test0; + test0 = new(); + + fd_w = $fopen(vector_filename, "a"); + if (fd_w == 0) $error("Cannot open file %s for writing", vector_filename); + + for (int i = 0; i < VEC_CNT; i++) begin + assert(test0.randomize()); + + test0.vector.input_valid = '1 >> (MAX_MSG_WR*(MsgWidth/8)-test0.vector_length); + + test_vector_q.push_back(test0.vector); + + //Write vectors to the file + $fwrite(fd_w, "%s ", test0.vector.mode.name()); + $fwrite(fd_w, "%s ", test0.vector.strength.name()); + $fwrite(fd_w, "%h ", test0.vector.input_valid); + $fwrite(fd_w, "%0h \n", test0.vector.input_vector); + end + $fclose(fd_w); + + $system($sformatf("python abr_sha3.py")); + + endtask + + //---------------------------------------------------------------- + // gen_five_squeeze_test_vectors() + //---------------------------------------------------------------- + task gen_five_squeeze_test_vectors; + int fd_w; + + test test0; + test0 = new(); + + fd_w = $fopen(vector_filename, "a"); + if (fd_w == 0) $error("Cannot open file %s for writing", vector_filename); + + for (int i = 0; i < VEC_CNT; i++) begin + assert(test0.randomize() with { vector.mode == abr_sha3_pkg::Shake; + }); + + test0.vector.input_valid = '1 >> (MAX_MSG_WR*(MsgWidth/8)-test0.vector_length); + + test_vector_q.push_back(test0.vector); + + //Write vectors to the file + $fwrite(fd_w, "%s ", test0.vector.mode.name()); + $fwrite(fd_w, "%s ", test0.vector.strength.name()); + $fwrite(fd_w, "%h ", test0.vector.input_valid); + $fwrite(fd_w, "%0h \n", test0.vector.input_vector); + end + $fclose(fd_w); + + $system($sformatf("python abr_sha3.py")); + + endtask + + + //---------------------------------------------------------------- + // check_results() + //---------------------------------------------------------------- + task check_results(input logic squeeze=0, input int squeeze_iter=0); + + //strength and mode fields determine how many valid bits we need to check from output + if (exp_mode == "Shake") begin + if (squeeze == 1'b1) begin + if (exp_strength == "L256") begin + if (exp_result.shake256.squeeze[squeeze_iter] != sha3_state[0][1088-1:0]) begin + $display("[%t] Checking Squeeze Iter %d for %s %s", $time, squeeze_iter, exp_mode, exp_strength); + $display("[%t] Actual: %x", $time,sha3_state[0][1088-1:0]); + $display("[%t] Expected: %x", $time,exp_result.shake256.squeeze[squeeze_iter]); + error_ctr += 1; + end + end else if (exp_strength == "L128" ) begin + if (exp_result.shake128.squeeze[squeeze_iter] != sha3_state[0][1344-1:0]) begin + $display("[%t] Checking Squeeze Iter %d for %s %s", $time, squeeze_iter, exp_mode, exp_strength); + $display("[%t] Checking %s %s", $time, exp_mode, exp_strength); + $display("[%t] Actual: %x", $time,sha3_state[0][1344-1:0]); + $display("[%t] Expected: %x", $time,exp_result.shake128.squeeze[squeeze_iter]); + error_ctr += 1; + end + end else begin + $display("[%t] Invalid strength field %s not supported in Shake mode", $time, exp_strength); + error_ctr += 1; + end + end else begin + if (exp_strength == "L256") begin + if (exp_result.shake256.absorb != sha3_state[0][1088-1:0]) begin + $display("[%t] Checking Absorb for %s %s", $time, exp_mode, exp_strength); + $display("[%t] Actual: %x", $time,sha3_state[0][1088-1:0]); + $display("[%t] Expected: %x", $time,exp_result.shake256.absorb); + error_ctr += 1; + end + end else if (exp_strength == "L128" ) begin + if (exp_result.shake128.absorb != sha3_state[0][1344-1:0]) begin + $display("[%t] Checking Absorb for %s %s", $time, exp_mode, exp_strength); + $display("[%t] Actual: %x", $time,sha3_state[0][1344-1:0]); + $display("[%t] Expected: %x", $time,exp_result.shake128.absorb); + error_ctr += 1; + end + end else begin + $display("[%t] Invalid strength field %s not supported in Shake mode", $time, exp_strength); + error_ctr += 1; + end + end + end else if (exp_mode == "Sha3") begin + if (exp_strength == "L512") begin + if (exp_result.sha3_512.digest != sha3_state[0][512-1:0]) begin + $display("[%t] Checking %s %s", $time, exp_mode, exp_strength); + $display("[%t] Actual: %x", $time,sha3_state[0][512-1:0]); + $display("[%t] Expected: %x", $time,exp_result.sha3_512.digest); + error_ctr += 1; + end + end else if (exp_strength == "L256" ) begin + if (exp_result.sha3_256.digest != sha3_state[0][256-1:0]) begin + $display("[%t] Checking %s %s", $time, exp_mode, exp_strength); + $display("[%t] Actual: %x", $time,sha3_state[0][256-1:0]); + $display("[%t] Expected: %x", $time,exp_result.sha3_256.digest); + error_ctr += 1; + end + end else begin + $display("[%t] Invalid strength field %s not supported in Sha3 mode", $time, exp_strength); + error_ctr += 1; + end + end + + endtask + //---------------------------------------------------------------- + // run_rand_test() + //---------------------------------------------------------------- + + task run_rand_test; + int fd_r_exp; + string line_read; + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + for (int iter = 0; iter < VEC_CNT; iter++) begin + //get the next exp result + if (!($fgets(line_read, fd_r_exp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + void'($sscanf(line_read, "%s %s %h", exp_mode, exp_strength, exp_result)); + + mode <= test_vector_q[0].mode; + strength <= test_vector_q[0].strength; + + //start keccak + @(posedge clk_tb); + sha3_start <= 1; + @(posedge clk_tb); + sha3_start <= 0; + + //new message start + @(posedge clk_tb); + msg_start <= 1; + @(posedge clk_tb); + msg_start <= 0; + + //send the input vector + for (int i = 0; i < MAX_MSG_WR; i++) begin + if ( |test_vector_q[0].input_valid[i] ) begin + write_single_msg(test_vector_q[0].input_vector[i], test_vector_q[0].input_valid[i]); + end + end + + //process the block + sha3_process <= 1; + @(posedge clk_tb); + sha3_process <= 0; + + //$display("[%t] Waiting for state valid)", $time); + + wait (sha3_state_vld == 1'b1); + + //check absorb + @(negedge clk_tb); + check_results(1'b0, 0); + + //Do a squeeze for Shake + if (test_vector_q[0].mode == abr_sha3_pkg::Shake) begin + sha3_run <= 1'b1; + @(posedge clk_tb); + sha3_run <= 1'b0; + @(posedge clk_tb); + + wait (sha3_state_vld == 1'b1); + + //check squeeze + @(negedge clk_tb); + check_results(1'b1); + end + + @(posedge clk_tb); + sha3_done = abr_prim_mubi_pkg::MuBi4True; + @(posedge clk_tb); + sha3_done = abr_prim_mubi_pkg::MuBi4False; + + test_vector_q.pop_front(); + tc_ctr++; + end + + $fclose(fd_r_exp); + + endtask // run_hw_if_test + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + `include "five_squeeze_test.svh" + + initial + begin : main + $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED")); + $display(" -- Testbench for SHA3 started --"); + + init_sim(); + reset_dut(); + + if ($value$plusargs("SHA3_TEST=%s", sha3_testname)) begin : alternate_test + $display(" ================================================================="); + $display(" Running SHA3_TEST = %s", sha3_testname); + $display(" ================================================================="); + + if (sha3_testname == "five_squeeze_test") begin + gen_five_squeeze_test_vectors(); + five_squeeze_test(); + end else begin + //default rand test + gen_rand_test_vectors(); + run_rand_test(); + end + //default rand test + end else begin + gen_rand_test_vectors(); + run_rand_test(); + end + + @(posedge clk_tb); + display_test_result(); + + $display(" -- Testbench for SHA3 done. --"); + $finish; + end // main + + abr_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o; + + `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3FsmCheck_A, + dut.u_state_regs, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KeccakRoundFsmCheck_A, + dut.u_keccak.u_state_regs, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3padFsmCheck_A, + dut.u_pad.u_state_regs, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(WrMsgCountCheck_A, + dut.u_pad.u_wrmsg_count, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RoundCountCheck_A, + dut.u_keccak.u_round_count, alert_tx_o[1]) + +endmodule // sha3_tb + +//====================================================================== +// EOF sha3_tb.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3_tb_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3_tb_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..f13610bb26c283a654f2b639d460bd375b714ee9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/abr_sha3_tb_pkg.sv @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +`ifndef ABR_SHA3_TB_PKG +`define ABR_SHA3_TB_PKG + +package abr_sha3_tb_pkg; + + import abr_sha3_pkg::*; + + //input vector size in bytes + parameter INPUT_VECTOR_W = 2592; + parameter MAX_MSG_WR = INPUT_VECTOR_W/(MsgWidth/8); + + parameter MAX_SQUEEZE = 5; + parameter SHAKE256_W = 1088; + parameter SHAKE128_W = 1344; + parameter SHAKE128_SIZE = SHAKE128_W + SHAKE128_W*MAX_SQUEEZE; + parameter SHAKE256_SIZE = SHAKE256_W + SHAKE256_W*MAX_SQUEEZE; + //Expected results structs + typedef struct packed { + logic [MAX_SQUEEZE-1:0][SHAKE128_W-1:0] squeeze; + logic [SHAKE128_W-1:0] absorb; + } shake128_res_t; + typedef struct packed { + logic [SHAKE128_SIZE-SHAKE256_SIZE-1:0] rsvd; + logic [MAX_SQUEEZE-1:0][SHAKE256_W-1:0] squeeze; + logic [SHAKE256_W-1:0] absorb; + } shake256_res_t; + typedef struct packed { + logic [SHAKE128_SIZE-512-1:0] rsvd; + logic [512-1:0] digest; + } sha3_512_res_t; + typedef struct packed { + logic [SHAKE128_SIZE-256-1:0] rsvd; + logic [256-1:0] digest; + } sha3_256_res_t; + + typedef union packed { + shake256_res_t shake256; + shake128_res_t shake128; + sha3_512_res_t sha3_512; + sha3_256_res_t sha3_256; + } exp_results_u; + + //test vector struct + typedef struct { + rand abr_sha3_pkg::sha3_mode_e mode; + rand abr_sha3_pkg::keccak_strength_e strength; + rand logic [MAX_MSG_WR-1:0][MsgWidth-1:0] input_vector; + logic [MAX_MSG_WR-1:0][MsgStrbW-1:0] input_valid; + } keccak_test_vector_t; + + class test; + rand keccak_test_vector_t vector; + rand int vector_length; + + constraint length_c { vector_length inside {[1:MAX_MSG_WR*(MsgWidth/8)]}; } + + constraint mode_c { vector.mode inside {abr_sha3_pkg::Shake, abr_sha3_pkg::Sha3}; } + + constraint strength_c { + (vector.mode == abr_sha3_pkg::Sha3) -> vector.strength inside {abr_sha3_pkg::L256, abr_sha3_pkg::L512}; + (vector.mode == abr_sha3_pkg::Shake) -> vector.strength inside {abr_sha3_pkg::L256, abr_sha3_pkg::L128}; + solve vector.mode before vector.strength; + } + + endclass + +endpackage +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/five_squeeze_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/five_squeeze_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..e34eb7074926e0ebcbc30638ff37b8b233417468 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/abr_sha3/tb/five_squeeze_test.svh @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== + +//---------------------------------------------------------------- +// five_squeeze_test(...) +// +// Simulates generation of Matrix A coefficients +//---------------------------------------------------------------- +task five_squeeze_test(); + int fd_r_exp; + string line_read; + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + for (int iter = 0; iter < VEC_CNT; iter++) begin + //get the next exp result + if (!($fgets(line_read, fd_r_exp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + void'($sscanf(line_read, "%h", exp_result)); + + //start keccak + @(posedge clk_tb); + sha3_start <= 1; + @(posedge clk_tb); + sha3_start <= 0; + + if (iter == 0) begin + mode <= test_vector_q[0].mode; + strength <= test_vector_q[0].strength; + + //start new message + @(posedge clk_tb); + msg_start <= 1; + @(posedge clk_tb); + msg_start <= 0; + + //send the input vector + for (int i = 0; i < MAX_MSG_WR; i++) begin + if ( |test_vector_q[0].input_valid[i] ) begin + write_single_msg(test_vector_q[0].input_vector[i], test_vector_q[0].input_valid[i]); + end + end + test_vector_q.pop_front(); + + end + + //process the block + sha3_process <= 1; + @(posedge clk_tb); + sha3_process <= 0; + + wait (sha3_state_vld == 1'b1); + + //check absorb + check_results(); + + fork + begin + //Do 5 squeeze + for (int i = 0; i < 5; i++) begin + sha3_run <= 1'b1; + @(posedge clk_tb); + sha3_run <= 1'b0; + @(posedge clk_tb); + + + wait (sha3_state_vld == 1'b1); + + //check squeeze + check_results(1'b1, i); + end + + @(posedge clk_tb); + sha3_done = abr_prim_mubi_pkg::MuBi4True; + @(posedge clk_tb); + sha3_done = abr_prim_mubi_pkg::MuBi4False; + + end + begin + //send the next vector while squeezing + //start msg buffer + if (iter != VEC_CNT-1) begin + mode <= test_vector_q[0].mode; + strength <= test_vector_q[0].strength; + end + + @(posedge clk_tb); + msg_start <= 1; + @(posedge clk_tb); + msg_start <= 0; + + //send the input vector + for (int i = 0; i < MAX_MSG_WR; i++) begin + if ( |test_vector_q[0].input_valid[i] ) begin + write_single_msg(test_vector_q[0].input_vector[i], test_vector_q[0].input_valid[i]); + end + end + test_vector_q.pop_front(); + end + join + + tc_ctr++; + end + + $fclose(fd_r_exp); +endtask \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..dc88b4343a25a4b3f6c9efcab74a0b110d6aa019 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/compile.yml @@ -0,0 +1,59 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [decompose_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/decompose_defines_pkg.sv + # tb: + # directories: + # - $COMPILE_ROOT/rtl + # files: + # - $COMPILE_ROOT/rtl/ecc_defines_pkg.sv +--- +provides: [decompose] +schema_version: 2.4.0 +requires: + - mldsa_defines + - ntt_pkg + - decompose_pkg + - ntt_top +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/decompose.sv + - $COMPILE_ROOT/rtl/decompose_r1_lut.sv + - $COMPILE_ROOT/rtl/decompose_w1_mem.sv + - $COMPILE_ROOT/rtl/decompose_mod_2gamma2.sv + - $COMPILE_ROOT/rtl/decompose_ctrl.sv + - $COMPILE_ROOT/rtl/decompose_w1_encode.sv + - $COMPILE_ROOT/rtl/decompose_usehint.sv + + tops: [decompose] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/decompose/config/design_lint/decompose/sglint_waivers +--- +provides: [decompose_tb] +schema_version: 2.4.0 +requires: + - decompose + - decompose_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/decompose_tb.sv + tops: [decompose_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying decompose hex to $PWD" && cp $COMPILE_ROOT/tb/test_vector.hex . && cp $COMPILE_ROOT/tb/dcmp_usehint_test_vector.hex .' + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose.vf new file mode 100644 index 0000000000000000000000000000000000000000..219b38e0f96eb46f2020c31928a1ed34186b52b8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose.vf @@ -0,0 +1,62 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_r1_lut.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_mem.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_mod_2gamma2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_encode.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_usehint.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..9c77de3f9598ebc4e76f1db4418026af5f022d43 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/rtl +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..6c7ffe56d1299feae2d302b2b00f72673035556c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/decompose_tb.vf @@ -0,0 +1,64 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_r1_lut.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_mem.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_mod_2gamma2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_encode.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_usehint.sv +${ADAMSBRIDGE_ROOT}/src/decompose/tb/decompose_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/design_lint/decompose/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/config/design_lint/decompose/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose.sv new file mode 100644 index 0000000000000000000000000000000000000000..3b148a0d5d0b4e874696070eef86b135ef31ff63 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose.sv @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose.sv +// -------- +// Breaks down r coefficient into high and low bits such that +// r = r1*(2*GAMMA2) + r0 mod q where +// r0 is between -GAMMA2 and +GAMMA2. For a corner case where +// r-r0 = q-1, r1 is made 0 and r0 is reduced by 1 i.e., +// r0 = r0 - 1 == r mod q (See HW spec for more details) +// Decompose unit also optimizes makehint arch by generating a bit that +// computes z = (r1 != 0) check and directly stores the result in a buffer. +// Makehint is able to read the buffer during hint gen and receives 4 bits per 4 coeff per cycle + +// Output of mod_2gamma2 goes through further calc to compute r0 mod+- (2gamma2) mod q. This is the +// final r0 output to be stored in memory. + +// Decompose unit produces 3 outputs: +// 1. r0 --> store in memory +// 2. r1 --> pass to sample inball/hash interface +// 3. z_neq_z --> store in a buffer that is ready by makehint simultaneously when it reads main mem + +`include "abr_prim_assert.sv" + +module decompose + import mldsa_params_pkg::*; + import decompose_defines_pkg::*; + #( + parameter Q_MINUS_2GAMMA2 = MLDSA_Q - (2*MLDSA_GAMMA2) + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire decompose_enable, + input dcmp_mode_t dcmp_mode, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] hint_src_base_addr, + + //Output to memory - r0 + output mem_if_t mem_rd_req, + output mem_if_t mem_wr_req, + input wire [(4*REG_SIZE)-1:0] mem_rd_data, + output logic [(4*REG_SIZE)-1:0] mem_wr_data, + + //Output to memory - h (sigDecode) + output mem_if_t mem_hint_rd_req, + input wire [(4*REG_SIZE)-1:0] mem_hint_rd_data, + + //Output to z mem - z != 0 + output mem_if_t z_mem_wr_req, + output logic [3:0] z_neq_z, + + //Output of w1_encode - r1 + output logic [63:0] w1_o, + output logic buffer_en, + + output logic decompose_done + + + ); + + //Coefficient wires + logic [3:0][3:0] r1, r1_reg, r1_usehint, r1_mux; + logic [3:0] r_corner, r_corner_reg; + logic [3:0][18:0] r0_mod_2gamma2; + logic [3:0][REG_SIZE-2:0] r0_mod_q, r0, r0_reg; //23-bit value + logic [(4*REG_SIZE)-1:0] mem_rd_data_reg, mem_hint_rd_data_reg, mem_wr_data_int; + mem_if_t mem_wr_req_int, mem_hint_rd_req_int, z_mem_wr_req_int; + logic [3:0] z_neq_z_d1, z_neq_z_d2, z_neq_z_int, z_neq_z_mux; + + //Control wires + logic mod_enable; + logic [1:0] enable_reg; + logic [3:0] mod_ready; + logic verify; + logic [3:0] usehint_ready; + + always_comb verify = (dcmp_mode == verify_op); + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + enable_reg <= 'b0; + z_neq_z_d1 <= 'h0; + z_neq_z_d2 <= 'h0; + end + else if (zeroize) begin + enable_reg <= 'b0; + z_neq_z_d1 <= 'h0; + z_neq_z_d2 <= 'h0; + end + else begin + enable_reg <= {mod_enable, enable_reg[1]}; + z_neq_z_d1 <= z_neq_z_int; + z_neq_z_d2 <= z_neq_z_d1; + end + end + + decompose_ctrl + dcmp_ctrl_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .decompose_enable(decompose_enable), + .src_base_addr(src_base_addr), + .dest_base_addr(dest_base_addr), + .r0_ready(&mod_ready), //all redux units must be ready at the same time + .mem_rd_req(mem_rd_req), + .mem_wr_req(mem_wr_req_int), + .mod_enable(mod_enable), + .decompose_done(decompose_done) + ); + + generate + for (genvar i = 0; i < 4; i++) begin + decompose_r1_lut #( + .REG_SIZE(REG_SIZE-1) + ) + r1_lut_inst ( + .r(mem_rd_data[(REG_SIZE-2)+(i*REG_SIZE):i*REG_SIZE]), + .r1(r1[i]), + .r_corner(r_corner[i]), + .z_nez(z_neq_z_int[i]) + ); + end + endgenerate + + generate + for(genvar i = 0; i < 4; i++) begin + decompose_mod_2gamma2 #( + .REG_SIZE(REG_SIZE-1) + ) + dcmp_redux_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .add_en_i(enable_reg[1]), //delayed by 1 clk + .opa_i(mem_rd_data[(REG_SIZE-2)+(i*REG_SIZE):i*REG_SIZE]), + .res_o(r0_mod_2gamma2[i]), + .ready_o(mod_ready[i]) + ); + end + endgenerate + + generate + for (genvar i = 0; i < 4; i++) begin + always_comb begin + r0_mod_q[i] = (r0_mod_2gamma2[i] <= MLDSA_GAMMA2) ? {4'h0, r0_mod_2gamma2[i]} : (REG_SIZE-1)'(r0_mod_2gamma2[i] + Q_MINUS_2GAMMA2); + end + end + endgenerate + + //Delay flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + r_corner_reg <= 'h0; + mem_rd_data_reg <= 'h0; + r0_reg <= 'h0; + r1_reg <= 'h0; + mem_hint_rd_data_reg <= 'h0; + end + else if (zeroize) begin + r_corner_reg <= 'h0; + mem_rd_data_reg <= 'h0; + r0_reg <= 'h0; + r1_reg <= 'h0; + mem_hint_rd_data_reg <= 'h0; + end + else begin + r_corner_reg <= r_corner; + mem_rd_data_reg <= mem_rd_data; + r0_reg <= r0; + r1_reg <= r1; + mem_hint_rd_data_reg <= mem_hint_rd_data; + end + end + + generate + for (genvar i = 0; i < 4; i++) begin + always_comb begin + r0[i] = r_corner_reg[i] ? mem_rd_data_reg[i*REG_SIZE+(REG_SIZE-2):i*REG_SIZE] : r0_mod_q[i]; + mem_wr_data_int[i*REG_SIZE+(REG_SIZE-1):i*REG_SIZE] = verify ? 'h0 : {1'b0, r0_reg[i]}; + end + end + endgenerate + + generate + for (genvar i = 0; i < 4; i++) begin + decompose_usehint #( + .REG_SIZE(REG_SIZE-1) + ) + usehint_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .usehint_enable(verify & enable_reg[0]), //delayed by 2 clks to match addr input flops + .w0_i(r0[i]), + .w1_i(r1_reg[i]), + .hint_i(mem_hint_rd_data_reg[i*REG_SIZE]), //LSB is the hint, rest are 0s + .w1_o(r1_usehint[i]), + .ready_o(usehint_ready[i]) + + ); + end + endgenerate + + always_comb begin + z_neq_z_mux = verify ? 'h0 : z_neq_z_d2; + z_mem_wr_req_int.rd_wr_en = verify ? RW_IDLE : mem_wr_req_int.rd_wr_en; + z_mem_wr_req_int.addr = verify ? 'h0 : MLDSA_MEM_ADDR_WIDTH'(mem_wr_req_int.addr - dest_base_addr); + r1_mux = verify & (&usehint_ready) ? r1_usehint : r1_reg; + + mem_hint_rd_req.addr = verify ? MLDSA_MEM_ADDR_WIDTH'(mem_rd_req.addr - src_base_addr + hint_src_base_addr) : 'h0; + mem_hint_rd_req.rd_wr_en = verify ? mem_rd_req.rd_wr_en : RW_IDLE; + end + + //Output flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + z_mem_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + + z_neq_z <= '0; + mem_wr_data <= '0; + end + else if (zeroize) begin + z_mem_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + + z_neq_z <= '0; + mem_wr_data <= '0; + end + else begin + z_mem_wr_req <= z_mem_wr_req_int; + mem_wr_req.addr <= verify ? 'h0 : mem_wr_req_int.addr; + mem_wr_req.rd_wr_en <= verify ? RW_IDLE : mem_wr_req_int.rd_wr_en; + + z_neq_z <= z_neq_z_mux; + mem_wr_data <= mem_wr_data_int; + end + end + + //w1 Encode + decompose_w1_encode w1_enc_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .w1_encode_enable(verify ? &usehint_ready : &mod_ready), + .r1_i(r1_mux), + .w1_o(w1_o), + .buffer_en(buffer_en) + ); + + + `ABR_ASSERT_MUTEX(ASSERT_R0_CORNER_MUTEX, {r_corner[0], r1[0]}, clk, reset_n) + `ABR_ASSERT_MUTEX(ASSERT_R1_CORNER_MUTEX, {r_corner[1], r1[1]}, clk, reset_n) + `ABR_ASSERT_MUTEX(ASSERT_R2_CORNER_MUTEX, {r_corner[2], r1[2]}, clk, reset_n) + `ABR_ASSERT_MUTEX(ASSERT_R3_CORNER_MUTEX, {r_corner[3], r1[3]}, clk, reset_n) +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..7e4a2574dad2695648da3fbbdbe5d02f1cf60886 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_ctrl.sv @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_ctrl.sv +// ----------- +// Takes care of memory accesses during decompose function + +module decompose_ctrl + import mldsa_params_pkg::*; + import decompose_defines_pkg::*; + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire decompose_enable, //Assumes polynomials are stored in contiguous locations and 1 enable will trig all 8 at once + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire r0_ready, + + output mem_if_t mem_rd_req, + output mem_if_t mem_wr_req, + output logic mod_enable, + output logic decompose_done + ); + + //Internals + logic [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr_reg, dest_base_addr_reg; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr_nxt, mem_wr_addr_nxt; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr, mem_wr_addr; + logic incr_rd_addr, incr_wr_addr; + logic rst_rd_addr, rst_wr_addr; + logic last_poly_last_addr_rd; //TODO: confirm that decompose take 8 polys. If there's a case with 7 polys, need to change code + logic last_poly_last_addr_wr; + logic decompose_busy; + + dcmp_read_state_e read_fsm_state_ps, read_fsm_state_ns; + dcmp_write_state_e write_fsm_state_ps, write_fsm_state_ns; + + logic arc_DCMP_RD_IDLE_DCMP_RD_MEM; + logic arc_DCMP_RD_MEM_DCMP_RD_IDLE; + + logic arc_DCMP_WR_IDLE_DCMP_WR_MEM; + logic arc_DCMP_WR_MEM_DCMP_WR_IDLE; + + //Read addr counter + always_comb mem_rd_addr_nxt = mem_rd_addr + 'h1; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_rd_addr <= 'h0; + src_base_addr_reg <= 'h0; + end + else if (zeroize) begin + mem_rd_addr <= 'h0; + src_base_addr_reg <= 'h0; + end + else if (rst_rd_addr) begin + mem_rd_addr <= src_base_addr; + src_base_addr_reg <= src_base_addr; + end + else if (incr_rd_addr) begin + mem_rd_addr <= last_poly_last_addr_rd ? 'h0 : mem_rd_addr_nxt; + end + end + + //Write addr counter + always_comb mem_wr_addr_nxt = mem_wr_addr + 'h1; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_wr_addr <= 'h0; + dest_base_addr_reg <= 'h0; + end + else if (zeroize) begin + mem_wr_addr <= 'h0; + dest_base_addr_reg <= 'h0; + end + else if (rst_wr_addr) begin + mem_wr_addr <= dest_base_addr; + dest_base_addr_reg <= dest_base_addr; + end + else if (incr_wr_addr) begin + mem_wr_addr <= last_poly_last_addr_wr ? 'h0 : mem_wr_addr_nxt; + end + end + + //Flags + assign last_poly_last_addr_rd = (mem_rd_addr == src_base_addr_reg + (MLDSA_K * (MLDSA_N/4))-1); + assign last_poly_last_addr_wr = (mem_wr_addr == dest_base_addr_reg + (MLDSA_K * (MLDSA_N/4))-1); + assign decompose_busy = (read_fsm_state_ps != DCMP_RD_IDLE); + assign decompose_done = (read_fsm_state_ps == DCMP_RD_IDLE) & (write_fsm_state_ps == DCMP_WR_IDLE); + + //Read fsm + always_comb begin + arc_DCMP_RD_IDLE_DCMP_RD_MEM = (read_fsm_state_ps == DCMP_RD_IDLE) && decompose_enable; + arc_DCMP_RD_MEM_DCMP_RD_IDLE = (read_fsm_state_ps == DCMP_RD_MEM) && last_poly_last_addr_rd; + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= DCMP_RD_IDLE; + else if (zeroize) + read_fsm_state_ps <= DCMP_RD_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; + end + + always_comb begin + incr_rd_addr = 'b0; + rst_rd_addr = 'b0; + mod_enable = 'b0; + + case(read_fsm_state_ps) + DCMP_RD_IDLE: begin + read_fsm_state_ns = arc_DCMP_RD_IDLE_DCMP_RD_MEM ? DCMP_RD_MEM : DCMP_RD_IDLE; + rst_rd_addr = 'b1; + end + DCMP_RD_MEM: begin + read_fsm_state_ns = arc_DCMP_RD_MEM_DCMP_RD_IDLE ? DCMP_RD_IDLE : DCMP_RD_MEM; + incr_rd_addr = 'b1; + mod_enable = 'b1; + end + endcase + end + + //Write fsm + always_comb begin + //Move to write mem state when reads are ongoing and mod 2gamma2 block has valid outputs + arc_DCMP_WR_IDLE_DCMP_WR_MEM = (write_fsm_state_ps == DCMP_WR_IDLE) && decompose_busy && r0_ready; + arc_DCMP_WR_MEM_DCMP_WR_IDLE = (write_fsm_state_ps == DCMP_WR_MEM) && last_poly_last_addr_wr; + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + write_fsm_state_ps <= DCMP_WR_IDLE; + else if (zeroize) + write_fsm_state_ps <= DCMP_WR_IDLE; + else + write_fsm_state_ps <= write_fsm_state_ns; + end + + always_comb begin + incr_wr_addr = 'b0; + rst_wr_addr = 'b0; + + case(write_fsm_state_ps) + DCMP_WR_IDLE: begin + write_fsm_state_ns = arc_DCMP_WR_IDLE_DCMP_WR_MEM ? DCMP_WR_MEM : DCMP_WR_IDLE; + rst_wr_addr = 'b1; + end + DCMP_WR_MEM: begin + write_fsm_state_ns = arc_DCMP_WR_MEM_DCMP_WR_IDLE ? DCMP_WR_IDLE : DCMP_WR_MEM; + incr_wr_addr = 'b1; + end + endcase + end + + //Assign outputs + always_comb begin + mem_rd_req.rd_wr_en = (read_fsm_state_ps == DCMP_RD_MEM) ? RW_READ : RW_IDLE; + mem_rd_req.addr = mem_rd_addr; + + mem_wr_req.rd_wr_en = (write_fsm_state_ps == DCMP_WR_MEM) ? RW_WRITE : RW_IDLE; + mem_wr_req.addr = mem_wr_addr; + end + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..c6eb6014021125026f9cd17021dbca1a7b734a66 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_defines_pkg.sv @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_defines_pkg.sv +// -------- +// Decompose parameters for Mldsa +//====================================================================== + +`ifndef MLDSA_DECOMPOSE_DEFINES +`define MLDSA_DECOMPOSE_DEFINES + +package decompose_defines_pkg; + + typedef enum logic {DCMP_RD_IDLE, DCMP_RD_MEM} dcmp_read_state_e; + typedef enum logic {DCMP_WR_IDLE, DCMP_WR_MEM} dcmp_write_state_e; + + localparam sign_op = 'h0, + verify_op = 'h1; + + typedef logic dcmp_mode_t; +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_mod_2gamma2.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_mod_2gamma2.sv new file mode 100644 index 0000000000000000000000000000000000000000..d70a1f2da0a9372495d5ea5a09abde376eed9283 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_mod_2gamma2.sv @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_mod_2gamma2.sv +// ------------ +// computes r0 mod (2gamma2). Input is 23 bit and produces r0 mod 2gamma2 is 19 bits + + +module decompose_mod_2gamma2 + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = mldsa_params_pkg::REG_SIZE-1, + localparam MLDSA_2GAMMA2_SIZE = $clog2(2*MLDSA_GAMMA2) + ) + ( + // Clock and reset. + input wire clk, + input wire reset_n, + input wire zeroize, + + // DATA PORT + input wire add_en_i, + input wire [REG_SIZE-1:0] opa_i, + output logic [MLDSA_2GAMMA2_SIZE-1:0] res_o, + output logic ready_o +); + + logic [12:0] opa0; + logic [MLDSA_2GAMMA2_SIZE-1:0] opb0; + logic [MLDSA_2GAMMA2_SIZE-1:0] opb1; + logic [MLDSA_2GAMMA2_SIZE-1:0] r0; + logic [MLDSA_2GAMMA2_SIZE-1:0] r1; + logic carry0; + + logic [MLDSA_2GAMMA2_SIZE-1:0] r0_reg; + logic carry0_reg; + + logic carry1; + + assign opa0 = 13'(opa_i[22:19] << 9); + assign opb0 = opa_i[MLDSA_2GAMMA2_SIZE-1:0]; + + abr_adder #( + .RADIX(MLDSA_2GAMMA2_SIZE) + ) + adder_inst_0( + .a_i({6'h0,opa0}), + .b_i(opb0), + .cin_i(1'b0), + .s_o(r0), + .cout_o(carry0) + ); + + abr_adder #( + .RADIX(MLDSA_2GAMMA2_SIZE) + ) + adder_inst_1( + .a_i(r0_reg), + .b_i(opb1), + .cin_i(1'b1), + .s_o(r1), + .cout_o(carry1) + ); + + + always_ff @(posedge clk or negedge reset_n) + begin + if(!reset_n) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + end + else if (zeroize) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + end + else if (add_en_i) begin + r0_reg <= r0; + carry0_reg <= carry0; + opb1 <= ~MLDSA_2GAMMA2_SIZE'(2*MLDSA_GAMMA2); + end + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) ready_o <= 'b0; + else if (zeroize) ready_o <= 'b0; + else ready_o <= add_en_i; + end + + assign res_o = (carry0_reg ^ carry1) ? r1 : r0_reg; + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_r1_lut.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_r1_lut.sv new file mode 100644 index 0000000000000000000000000000000000000000..ac4a56a7725b3a5469bb40e04106cb627dcee3c2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_r1_lut.sv @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_r1_lut.sv +// -------- +// Breaks down input coefficient r into highbits(r) +// Follows a look up table to determine the value of r1 based on input r +// In a corner case, when r is greater than 31γ2+1 and less than q-1, r1 is made 0 +//====================================================================== + +module decompose_r1_lut + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = 23 + ) + ( + input wire [REG_SIZE-1:0] r, + output logic [3:0] r1, + output logic r_corner, //Indicates if coeff r is in the corner case range + output logic z_nez + ); + + always_comb begin + r_corner = 'b0; + if (r <= MLDSA_GAMMA2) r1 = 'd0; + else if (r <= 3*MLDSA_GAMMA2) r1 = 'd1; + else if (r <= 5*MLDSA_GAMMA2) r1 = 'd2; + else if (r <= 7*MLDSA_GAMMA2) r1 = 'd3; + else if (r <= 9*MLDSA_GAMMA2) r1 = 'd4; + else if (r <= 11*MLDSA_GAMMA2) r1 = 'd5; + else if (r <= 13*MLDSA_GAMMA2) r1 = 'd6; + else if (r <= 15*MLDSA_GAMMA2) r1 = 'd7; + else if (r <= 17*MLDSA_GAMMA2) r1 = 'd8; + else if (r <= 19*MLDSA_GAMMA2) r1 = 'd9; + else if (r <= 21*MLDSA_GAMMA2) r1 = 'd10; + else if (r <= 23*MLDSA_GAMMA2) r1 = 'd11; + else if (r <= 25*MLDSA_GAMMA2) r1 = 'd12; + else if (r <= 27*MLDSA_GAMMA2) r1 = 'd13; + else if (r <= 29*MLDSA_GAMMA2) r1 = 'd14; + else if (r <= 31*MLDSA_GAMMA2) r1 = 'd15; + else + begin + r1 = 'd0; + r_corner = 'b1; + end + end + + always_comb z_nez = (r1 != 'h0); + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_usehint.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_usehint.sv new file mode 100644 index 0000000000000000000000000000000000000000..6ad5191e511be084e73c7b6a140d35eddbd78818 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_usehint.sv @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_usehint.sv +// ------------ +// Consumes output of decompose and hint bit from makehint to modify w1 component +// before performing w1Encode on it +// This unit performs the following calc: +// (w0 == 0 || w0 > gamma2) ? (w1 = (w1-1) mod 16) : (w1 = (w1 + 1) mod 16) +// If makehint hint bit is 0, w1 is directly passed onto w1 encode. If makehint hint bit is 1, +// above modified w1 is passed onto w1 encode + +module decompose_usehint + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = 23 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire usehint_enable, + input wire [REG_SIZE-1:0] w0_i, + input wire [3:0] w1_i, + input wire hint_i, + + //output to w1 encode + output logic [3:0] w1_o, + output logic ready_o + ); + + logic [3:0] w1_plus_one, w1_minus_one; + logic [3:0] w1_mux; + logic ready; + logic [REG_SIZE-1:0] w0_reg; + logic [3:0] w1_reg; + logic hint_reg; + + //Delay flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + w0_reg <= 'h0; + w1_reg <= 'h0; + hint_reg <= 'h0; + end + else if (zeroize) begin + w0_reg <= 'h0; + w1_reg <= 'h0; + hint_reg <= 'h0; + end + else begin + w0_reg <= w0_i; + w1_reg <= w1_i; + hint_reg <= hint_i; + end + end + + abr_add_sub_mod #( + .REG_SIZE(4) + ) + usehint_add_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .add_en_i(usehint_enable), + .sub_i(1'b0), + .opa_i(w1_i), + .opb_i(4'(1)), + .prime_i(4'(16)), + .res_o(w1_plus_one), + .ready_o() + ); + + abr_add_sub_mod #( + .REG_SIZE(4) + ) + usehint_sub_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .add_en_i(usehint_enable), + .sub_i(1'b1), + .opa_i(w1_i), + .opb_i(4'(1)), + .prime_i(4'(16)), + .res_o(w1_minus_one), + .ready_o() + ); + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + ready <= 'b0; + else if (zeroize) + ready <= 'b0; + else + ready <= usehint_enable; + end + + always_comb begin + if (ready) begin + w1_mux = ((w0_reg == 'h0) | (w0_reg > MLDSA_GAMMA2)) ? w1_minus_one : w1_plus_one; + w1_o = hint_reg ? w1_mux : w1_reg; + end + else begin + w1_mux = 'h0; + w1_o = 'h0; + end + end + + always_comb ready_o = ready; +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_w1_encode.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_w1_encode.sv new file mode 100644 index 0000000000000000000000000000000000000000..beb5ff941f4ab981afda988d2b1b189e229f1715 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_w1_encode.sv @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_w1_encode.sv +// -------- +// 1. Decompose produces 4-bits * 4 = 16-bits of r1 per cycle. This needs to be +// consumed by Keccak which takes 64-bits per cycle. w1_encode block buffers +// 16-bits per cycle and asserts a valid every 4 cycles indicating 64-bits are ready +// for Keccak to sample. +// 2. Keccak also needs an enable once every 1088 bits (block length) to process the buffered +// data. w1_encode also provides this enable by counting 17 iterations of buffer valid +// i.e., 17 * 64-bits = 1088 bits. For every 17 4-cycle loops, keccak is enabled. +// 3. Corner case: the 1st iteration of Keccak takes mu || w1 as input where mu is 512 bits +// So, only 576 bits of w1 are needed and then Keccak can be enabled. In this case, +// the keccak_en is asserted after 9 loops (9*64-bits = 576 bits). +// 4. w1_encode must be performed on 8 input polynomials. Once 8-rounds are Keccak are done, +// high level controller issues the last round with padding and enables Keccak. + +module decompose_w1_encode + import mldsa_params_pkg::*; + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire w1_encode_enable, //level not pulse. Indicates r1 lut is valid from decompose block + input wire [3:0][3:0] r1_i, + + output logic [63:0] w1_o, + output logic buffer_en + ); + + localparam BUFFER_CYC = 4; + + //Enable counter + logic [1:0] buffer_count; + + //Flags + logic w1_en_reg; + logic init_count_first; + logic decr_buf_count; + + //Generate a pulse to init counters + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + w1_en_reg <= 'b0; + else if (zeroize) + w1_en_reg <= 'b0; + else + w1_en_reg <= w1_encode_enable; + end + assign init_count_first = w1_encode_enable & ~w1_en_reg; + + //Decr logic + assign decr_buf_count = w1_en_reg; + + //Buffer enable counter + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + buffer_count <= 'h0; + else if (zeroize) + buffer_count <= 'h0; + else if (init_count_first) + buffer_count <= BUFFER_CYC-1; + else if (decr_buf_count) + buffer_count <= buffer_count - 'h1; + end + + assign buffer_en = w1_en_reg && (buffer_count == 'h0); + + //r1 shift reg + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + w1_o <= 'h0; + else if (zeroize) + w1_o <= 'h0; + else if (w1_encode_enable) + w1_o <= {r1_i, w1_o[63:16]}; + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_w1_mem.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_w1_mem.sv new file mode 100644 index 0000000000000000000000000000000000000000..0e8abd77fb04069157f77951bb88df657589b101 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/rtl/decompose_w1_mem.sv @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// decompose_w1_mem.sv +// -------- +// Stores 256-bit z components for 8 polynomials (256*8 = 2048 bits) +// z value is derived from r1 of decompose unit. z = (r1 != 0) +// Decompose unit writes to this buffer. Makehint reads from this buffer +// to calculate hint as needed. +// To align with main memory access pattern, this buffer also stores 4 bits per addr +// that represent 4 coeffs. Hence, 64 locations are needed per poly + +module decompose_w1_mem #( + parameter ADDR_WIDTH = 9, //8 poly * 64 addr per poly = 512 locations + parameter DATA_WIDTH = 4 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire rden, //read en + input wire wren, //write en + input wire [ADDR_WIDTH-1 : 0] addr, + input wire [DATA_WIDTH-1 : 0] din, + output logic [DATA_WIDTH-1 : 0] dout + ); + + // Declare the RAM variable + localparam ADDR_LENGTH = 2**ADDR_WIDTH; + reg [DATA_WIDTH-1:0] mem[ADDR_LENGTH-1:0]; + + + always_ff @ (posedge clk or negedge reset_n) + begin : reading_memory + if (!reset_n) begin + dout <= '0; + end + else if (zeroize) begin + dout <= '0; + end + else begin + if (rden) + dout <= mem[addr]; + end + end // reading_memory + + always_ff @ (posedge clk or negedge reset_n) + begin : writing_memory + if (!reset_n) begin + for (int i0 = 0; i0 < ADDR_LENGTH; i0++) + mem[i0] <= '0; + end + else if (zeroize) begin + for (int i0 = 0; i0 < ADDR_LENGTH; i0++) + mem[i0] <= '0; + end + else begin + if (wren) + mem[addr] <= din; + end + end // writing_memory + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/stimulus/tests/directed/decompose_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/stimulus/tests/directed/decompose_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..21105e375b0d955d16a0bf7abf54d0ac0f07b239 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/stimulus/tests/directed/decompose_normal_test.yml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +# plusargs: +# - +ECC_TEST_VECTOR_FILE='${CALIPTRA_ROOT}/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex' +# - +ECC_TEST='ECC_normal_test' + +testname: decompose_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/dcmp_usehint_test_vector.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/dcmp_usehint_test_vector.hex new file mode 100644 index 0000000000000000000000000000000000000000..cdea4088856fcf4dbd0db3806fb4aa593c0a7e0e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/dcmp_usehint_test_vector.hex @@ -0,0 +1,256 @@ +6E6BD3 00000E 7E67D4 00000D 00000D 000001 +60D809 00000C 00F009 00000D 00000D 000001 +2D24E0 000006 7D10E1 000005 000005 000001 +308DEF 000006 0099EF 000007 000007 000001 +1C1BC0 000004 7C03C1 000003 000003 000001 +325828 000006 026428 000007 000007 000001 +34FE9D 000007 7CEC9E 000006 000006 000001 +1CFF67 000004 7CE768 000003 000004 000000 +08B6C5 000001 00B8C5 000002 000002 000001 +38BB15 000007 00C915 000008 000008 000001 +0C15E5 000002 7BF9E6 000001 000002 000000 +56D4C1 00000B 7ECAC2 00000A 00000A 000001 +18B814 000003 00BE14 000004 000004 000001 +4D792D 00000A 7D6D2E 000009 00000A 000000 +07335C 000001 7F155D 000000 000000 000001 +11291A 000002 012D1A 000003 000002 000000 +296F17 000005 017917 000006 000006 000001 +1236A3 000002 023AA3 000003 000002 000000 +792729 00000F 014529 000000 00000F 000000 +413804 000008 014804 000009 000008 000000 +7EECEC 000000 7EECEC 00000F 00000F 000001 +1BEED9 000003 03F4D9 000004 000003 000000 +570086 00000B 7EF687 00000A 00000A 000001 +6A5397 00000D 026D97 00000E 00000E 000001 +49E9A2 000009 01FBA2 00000A 000009 000000 +5FFEE6 00000C 0016E6 00000D 00000C 000000 +1F078C 000004 7EEF8D 000003 000003 000001 +08B0E9 000001 00B2E9 000002 000002 000001 +789A67 00000F 00B867 000000 00000F 000000 +5C6A5F 00000C 7C6260 00000B 00000C 000000 +246955 000005 7C5356 000004 000005 000000 +293053 000005 013A53 000006 000006 000001 +56B0A5 00000B 7EA6A6 00000A 00000A 000001 +4BB5CE 000009 03C7CE 00000A 00000A 000001 +5A2E38 00000B 024438 00000C 00000C 000001 +4C21BA 00000A 7C15BB 000009 000009 000001 +1958E2 000003 015EE2 000004 000004 000001 +505AFE 00000A 006EFE 00000B 00000B 000001 +36D626 000007 7EC427 000006 000007 000000 +797675 00000F 019475 000000 00000F 000000 +1876AB 000003 007CAB 000004 000004 000001 +36BE16 000007 7EAC17 000006 000007 000000 +5A7C1F 00000B 02921F 00000C 00000B 000000 +62AB67 00000C 02C367 00000D 00000C 000000 +6265FF 00000C 027DFF 00000D 00000D 000001 +6EB874 00000E 7EB475 00000D 00000E 000000 +2EDD27 000006 7EC928 000005 000005 000001 +60D62E 00000C 00EE2E 00000D 00000D 000001 +58EE09 00000B 010409 00000C 00000C 000001 +709C56 00000E 00B856 00000F 00000F 000001 +28B502 000005 00BF02 000006 000006 000001 +097F61 000001 018161 000002 000002 000001 +14D502 000003 7CBB03 000002 000002 000001 +7308ED 00000E 0324ED 00000F 00000E 000000 +61CD67 00000C 01E567 00000D 00000D 000001 +1E28AA 000004 7E10AB 000003 000004 000000 +5CEAC6 00000C 7CE2C7 00000B 00000B 000001 +52C96F 00000A 02DD6F 00000B 00000B 000001 +1D99B2 000004 7D81B3 000003 000004 000000 +225C0D 000004 02640D 000005 000005 000001 +280F3C 000005 00193C 000006 000006 000001 +1204CB 000002 0208CB 000003 000002 000000 +2D397B 000006 7D257C 000005 000005 000001 +60C355 00000C 00DB55 00000D 00000D 000001 +7ABE2E 00000F 02DC2E 000000 000000 000001 +7E0AAC 000000 7E0AAC 00000F 000000 000000 +0A3DC1 000001 023FC1 000002 000001 000000 +0033FA 000000 0033FA 000001 000001 000001 +2FB872 000006 7FA473 000005 000006 000000 +4C4D22 00000A 7C4123 000009 000009 000001 +555401 00000B 7D4A02 00000A 00000B 000000 +635E91 00000C 037691 00000D 00000C 000000 +1F9365 000004 7F7B66 000003 000003 000001 +1B701B 000003 03761B 000004 000004 000001 +2E4560 000006 7E3161 000005 000006 000000 +08C604 000001 00C804 000002 000002 000001 +41C9F8 000008 01D9F8 000009 000008 000000 +192DAA 000003 0133AA 000004 000004 000001 +5D226F 00000C 7D1A70 00000B 00000C 000000 +362EE7 000007 7E1CE8 000006 000006 000001 +4C9ECD 00000A 7C92CE 000009 00000A 000000 +08B4BF 000001 00B6BF 000002 000002 000001 +3B2BF2 000007 0339F2 000008 000008 000001 +04F319 000001 7CD51A 000000 000001 000000 +52168E 00000A 022A8E 00000B 00000A 000000 +0700EB 000001 7EE2EC 000000 000001 000000 +316BE5 000006 0177E5 000007 000006 000000 +7D34DF 000000 7D34DF 00000F 00000F 000001 +036526 000000 036526 000001 000000 000000 +7F63E2 000000 7F63E2 00000F 00000F 000001 +7265A3 00000E 0281A3 00000F 00000F 000001 +3246AD 000006 0252AD 000007 000007 000001 +42536E 000008 02636E 000009 000009 000001 +44EE70 000009 7CE071 000008 000009 000000 +105814 000002 005C14 000003 000002 000000 +140697 000003 7BEC98 000002 000003 000000 +54B3D2 00000B 7CA9D3 00000A 00000A 000001 +237465 000004 037C65 000005 000005 000001 +44F770 000009 7CE971 000008 000008 000001 +7BA3C3 00000F 03C1C3 000000 00000F 000000 +5A6876 00000B 027E76 00000C 00000B 000000 +535DB9 00000A 0371B9 00000B 00000A 000000 +26ECF9 000005 7ED6FA 000004 000005 000000 +1733C5 000003 7F19C6 000002 000002 000001 +56D56B 00000B 7ECB6C 00000A 00000B 000000 +651D82 00000D 7D1783 00000C 00000D 000000 +295105 000005 015B05 000006 000006 000001 +43711F 000008 03811F 000009 000009 000001 +2E701F 000006 7E5C20 000005 000006 000000 +27F991 000005 000391 000006 000006 000001 +723D7A 00000E 02597A 00000F 00000E 000000 +553C15 00000B 7D3216 00000A 00000B 000000 +640327 00000D 7BFD28 00000C 00000C 000001 +1EFE24 000004 7EE625 000003 000003 000001 +67D9EC 00000D 7FD3ED 00000C 00000C 000001 +4A4627 000009 025827 00000A 00000A 000001 +1116A0 000002 011AA0 000003 000002 000000 +64EF2D 00000D 7CE92E 00000C 00000C 000001 +2A7EDF 000005 0288DF 000006 000006 000001 +522716 00000A 023B16 00000B 00000B 000001 +7ACDDF 00000F 02EBDF 000000 000000 000001 +3D68B0 000008 7D58B1 000007 000007 000001 +53774B 00000A 038B4B 00000B 00000A 000000 +082310 000001 002510 000002 000002 000001 +788CFD 00000F 00AAFD 000000 00000F 000000 +34BD3E 000007 7CAB3F 000006 000007 000000 +628E2A 00000C 02A62A 00000D 00000D 000001 +0CC172 000002 7CA573 000001 000001 000001 +026465 000000 026465 000001 000001 000001 +24A035 000005 7C8A36 000004 000005 000000 +047AF0 000001 7C5CF1 000000 000000 000001 +5819E4 00000B 002FE4 00000C 00000B 000000 +161D56 000003 7E0357 000002 000002 000001 +0D0368 000002 7CE769 000001 000002 000000 +4CB264 00000A 7CA665 000009 000009 000001 +2C8940 000006 7C7541 000005 000006 000000 +73B746 00000E 03D346 00000F 00000E 000000 +7C28E3 000000 7C28E3 00000F 000000 000000 +5EE227 00000C 7EDA28 00000B 00000B 000001 +44B4CE 000009 7CA6CF 000008 000008 000001 +758639 00000F 7D843A 00000E 00000E 000001 +6A3635 00000D 025035 00000E 00000E 000001 +27B9B8 000005 7FA3B9 000004 000004 000001 +7E5CCA 000000 7E5CCA 00000F 000000 000000 +003F83 000000 003F83 000001 000000 000000 +1197A6 000002 019BA6 000003 000003 000001 +4561A9 000009 7D53AA 000008 000008 000001 +3CF24C 000008 7CE24D 000007 000008 000000 +4F2282 00000A 7F1683 000009 00000A 000000 +68DC90 00000D 00F690 00000E 00000D 000000 +125228 000002 025628 000003 000003 000001 +75BD46 00000F 7DBB47 00000E 00000E 000001 +4C5026 00000A 7C4427 000009 00000A 000000 +43AC3A 000008 03BC3A 000009 000008 000000 +634A94 00000C 036294 00000D 00000C 000000 +496DBB 000009 017FBB 00000A 00000A 000001 +1DB590 000004 7D9D91 000003 000003 000001 +3BA6DB 000007 03B4DB 000008 000008 000001 +109036 000002 009436 000003 000002 000000 +5EEF83 00000C 7EE784 00000B 00000C 000000 +456B12 000009 7D5D13 000008 000008 000001 +1A39EC 000003 023FEC 000004 000004 000001 +649B3A 00000D 7C953B 00000C 00000D 000000 +152C42 000003 7D1243 000002 000003 000000 +1F2E05 000004 7F1606 000003 000004 000000 +0345F3 000000 0345F3 000001 000000 000000 +0AA64C 000001 02A84C 000002 000001 000000 +0C79A7 000002 7C5DA8 000001 000002 000000 +358FCC 000007 7D7DCD 000006 000007 000000 +535992 00000A 036D92 00000B 00000B 000001 +308B45 000006 009745 000007 000007 000001 +342FD8 000007 7C1DD9 000006 000007 000000 +475BC4 000009 7F4DC5 000008 000008 000001 +292139 000005 012B39 000006 000006 000001 +7A6B93 00000F 028993 000000 00000F 000000 +4E98E2 00000A 7E8CE3 000009 00000A 000000 +662EBF 00000D 7E28C0 00000C 00000D 000000 +3B0B00 000007 031900 000008 000007 000000 +5564F3 00000B 7D5AF4 00000A 00000B 000000 +0A4F25 000001 025125 000002 000002 000001 +4D24A3 00000A 7D18A4 000009 000009 000001 +6E2925 00000E 7E2526 00000D 00000E 000000 +08911E 000001 00931E 000002 000002 000001 +515C3E 00000A 01703E 00000B 00000A 000000 +294EE5 000005 0158E5 000006 000005 000000 +73D809 00000E 03F409 00000F 00000F 000001 +529810 00000A 02AC10 00000B 00000B 000001 +5487FE 00000B 7C7DFF 00000A 00000B 000000 +3E4224 000008 7E3225 000007 000007 000001 +1E8528 000004 7E6D29 000003 000003 000001 +33C627 000006 03D227 000007 000006 000000 +56F614 00000B 7EEC15 00000A 00000B 000000 +168D81 000003 7E7382 000002 000003 000000 +417E71 000008 018E71 000009 000008 000000 +3DB3A5 000008 7DA3A6 000007 000007 000001 +063246 000001 7E1447 000000 000001 000000 +68D3B7 00000D 00EDB7 00000E 00000D 000000 +2F89FB 000006 7F75FC 000005 000005 000001 +21035D 000004 010B5D 000005 000004 000000 +5E2B30 00000C 7E2331 00000B 00000B 000001 +7D2BF4 000000 7D2BF4 00000F 000000 000000 +21BD0A 000004 01C50A 000005 000004 000000 +076144 000001 7F4345 000000 000001 000000 +258EB3 000005 7D78B4 000004 000004 000001 +315BD6 000006 0167D6 000007 000006 000000 +65D543 00000D 7DCF44 00000C 00000D 000000 +6253F8 00000C 026BF8 00000D 00000D 000001 +19ADC1 000003 01B3C1 000004 000004 000001 +363CBA 000007 7E2ABB 000006 000006 000001 +40DAF5 000008 00EAF5 000009 000009 000001 +3FC096 000008 7FB097 000007 000008 000000 +27AC35 000005 7F9636 000004 000005 000000 +140E7D 000003 7BF47E 000002 000003 000000 +59129E 00000B 01289E 00000C 00000B 000000 +04D338 000001 7CB539 000000 000000 000001 +30FA4C 000006 01064C 000007 000006 000000 +548E85 00000B 7C8486 00000A 00000B 000000 +6E1EAD 00000E 7E1AAE 00000D 00000D 000001 +1E7A30 000004 7E6231 000003 000003 000001 +1D7D0E 000004 7D650F 000003 000004 000000 +52E06C 00000A 02F46C 00000B 00000A 000000 +70AA7D 00000E 00C67D 00000F 00000F 000001 +771446 00000F 7F1247 00000E 00000F 000000 +2AE301 000005 02ED01 000006 000005 000000 +093E19 000001 014019 000002 000001 000000 +2D83F7 000006 7D6FF8 000005 000006 000000 +562BF7 00000B 7E21F8 00000A 00000B 000000 +7E1774 000000 7E1774 00000F 00000F 000001 +427359 000008 028359 000009 000008 000000 +4F1743 00000A 7F0B44 000009 000009 000001 +12A921 000002 02AD21 000003 000002 000000 +61C4D8 00000C 01DCD8 00000D 00000D 000001 +699FFF 00000D 01B9FF 00000E 00000D 000000 +436307 000008 037307 000009 000008 000000 +31CB8C 000006 01D78C 000007 000006 000000 +76BC34 00000F 7EBA35 00000E 00000F 000000 +720F5C 00000E 022B5C 00000F 00000E 000000 +61389B 00000C 01509B 00000D 00000C 000000 +090882 000001 010A82 000002 000002 000001 +5B59AE 00000B 036FAE 00000C 00000C 000001 +453736 000009 7D2937 000008 000008 000001 +67E493 00000D 7FDE94 00000C 00000D 000000 +1702DC 000003 7EE8DD 000002 000003 000000 +5261D9 00000A 0275D9 00000B 00000B 000001 +303B1C 000006 00471C 000007 000007 000001 +54AAED 00000B 7CA0EE 00000A 00000A 000001 +7792A1 00000F 7F90A2 00000E 00000F 000000 +631DFC 00000C 0335FC 00000D 00000C 000000 +53F5DC 00000B 7BEBDD 00000A 00000A 000001 +226393 000004 026B93 000005 000004 000000 +514419 00000A 015819 00000B 00000B 000001 +4D41C9 00000A 7D35CA 000009 000009 000001 +2E6488 000006 7E5089 000005 000006 000000 +6730CA 00000D 7F2ACB 00000C 00000C 000001 +6E39E6 00000E 7E35E7 00000D 00000E 000000 +792F30 00000F 014D30 000000 000000 000001 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/decompose_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/decompose_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..fcf1622295854e713442e0c723d2228c957fddeb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/decompose_tb.sv @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// decompose_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module decompose_tb + import decompose_defines_pkg::*; + import mldsa_params_pkg::*; +#( + parameter NUM_WR = 4, //TODO: sample_buffer needs more writes than reads? + parameter NUM_RD = 4, + parameter BUFFER_DATA_W = 8, + parameter REG_SIZE = 24 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg en_tb; +reg [4*REG_SIZE-1:0] coeff_tb, mem_wr_data_o, hint_tb; +reg [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_tb, dest_base_tb; +reg r0_rdy_tb; +logic [255:0][REG_SIZE-1:0] coeff_array, coeff_high, coeff_low, coeff_high_usehint, coeff_high_final, hint_array; +logic [3:0][3:0] coeff_high_tb; +logic kdone_tb; +logic verify_tb; +logic mode_tb; +decompose dut( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .decompose_enable(en_tb), + .src_base_addr(src_base_tb), + .dest_base_addr(dest_base_tb), + .hint_src_base_addr(src_base_tb), + .mem_rd_req(), + .mem_wr_req(), + .mem_hint_rd_req(), + .mem_hint_rd_data(hint_tb), + .dcmp_mode(mode_tb), + .mem_rd_data(coeff_tb), + .mem_wr_data(mem_wr_data_o), + .z_mem_wr_req(), + .z_neq_z(), + .w1_o(), + .buffer_en(), + .decompose_done(), + .w1_encode_done() +); + +// w1_encode dut( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .w1_encode_enable(en_tb), +// .r1_i(coeff_high_tb), +// .w1_o(), +// .buffer_en(), +// .keccak_en(), +// .w1_encode_done(), +// .keccak_done(kdone_tb) +// ); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + // hint_4bit_tb = 0; + // index_tb = 0; + zeroize_tb = 0; + en_tb = 0; + coeff_tb = 0; + hint_tb = 0; + src_base_tb = 'h0; + dest_base_tb = 'h0; + r0_rdy_tb = 'b0; + coeff_high_tb = 'h0; + kdone_tb = 'b0; + verify_tb = 'b0; + mode_tb = 'h0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + // cptra_pwrgood_tb = '0; + reset_n_tb = 0; + + // #(2 * CLK_PERIOD); + // cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + + +task r1_lut_test; + $display("Starting r1 lut test\n"); + @(posedge clk_tb); + en_tb = 1; + @(posedge clk_tb); + // en_tb = 0; //comment back in for r1_lut_test + // @(posedge clk_tb); + for (int poly = 0; poly < 8; poly++) begin + $display("Starting Poly %0d", poly); + for (int i = 0; i < 64; i++) begin + coeff_tb = REG_SIZE'($random); + @(posedge clk_tb); + end + end + @(posedge clk_tb); + $display("Test done\n"); +endtask + +task ctrl_test; + $display("Starting decompose ctrl test\n"); + @(posedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + en_tb = 1'b0; + src_base_tb = 'h0; + dest_base_tb = 'h40; + r0_rdy_tb = 1'b1; +endtask + +task read_test_vectors(); + // string fname = "test_vector.hex"; + string fname = "dcmp_usehint_test_vector.hex"; + integer file; + string line; + integer i, ret; + + i = 0; + file = $fopen(fname, "r"); + if (file == 0) $error("Cannot open %s for reading\n", fname); + + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h %h %h %h %h %h", coeff_array[i], coeff_high[i], coeff_low[i], coeff_high_usehint[i], coeff_high_final[i], hint_array[i]); + i = i+1; + end + end + $fclose(file); +endtask + +task dcmp_test(logic vfy); + logic error_flag; + + $display("Reading hex file\n"); + read_test_vectors(); + + $display("Starting dcmp test\n"); + @(posedge clk_tb); + en_tb = 1; + @(posedge clk_tb); + en_tb = 1'b0; + src_base_tb = 'h0; + dest_base_tb = 'h40; + error_flag = 'b0; + + @(posedge clk_tb); //Emulate mem reads by waiting a cycle + + fork + begin + for (int poly = 0; poly < 1; poly++) begin + $display("Starting Poly %0d", poly); + for (int i = 0; i < 256; i=i+4) begin + coeff_tb <= {coeff_array[i+3], coeff_array[i+2], coeff_array[i+1], coeff_array[i]}; //{{1'b0,(REG_SIZE-1)'($random)}, {1'b0,(REG_SIZE-1)'($random)}, {1'b0,(REG_SIZE-1)'($random)}, {1'b0,(REG_SIZE-1)'($random)}}; + hint_tb <= {hint_array[i+3], hint_array[i+2], hint_array[i+1], hint_array[i]}; + @(posedge clk_tb); + end + end + @(posedge clk_tb); + end + begin + // @(posedge clk_tb); //wait for mod_ready to go high + //Check decompose outputs w0 and w1 + while(dut.mod_ready != 'hf) @(posedge clk_tb); + for(int i = 0; i < 256; i = i+4) begin + if ({REG_SIZE'(dut.r1_reg[i%4]), REG_SIZE'(dut.r1_reg[i%4+1]), REG_SIZE'(dut.r1_reg[i%4+2]), REG_SIZE'(dut.r1_reg[i%4+3])} != {coeff_high[i], coeff_high[i+1], coeff_high[i+2], coeff_high[i+3]}) begin + $error("r1 does not match. Expected = %h %h %h %h, observed = %h %h %h %h at index %0d\n", coeff_high[i], coeff_high[i+1], coeff_high[i+2], coeff_high[i+3], dut.r1_reg[i%4], dut.r1_reg[i%4+1], dut.r1_reg[i%4+2], dut.r1_reg[i%4+3], i); + error_flag = 'b1; + end + if (~vfy) begin + // if (mem_wr_data_o != {coeff_low[i+3], coeff_low[i+2], coeff_low[i+1], coeff_low[i]}) begin + if ({REG_SIZE'(dut.r0[i%4+3]), REG_SIZE'(dut.r0[i%4+2]), REG_SIZE'(dut.r0[i%4+1]), REG_SIZE'(dut.r0[i%4])}!= {coeff_low[i+3], coeff_low[i+2], coeff_low[i+1], coeff_low[i]}) begin + $error("r0 does not match. Expected = %h %h %h %h, observed = %h %h %h %h at index %0d\n", coeff_low[i+3], coeff_low[i+2], coeff_low[i+1], coeff_low[i], dut.r0[3], dut.r0[2], dut.r0[1], dut.r0[0], i); + error_flag = 'b1; + end + end + @(posedge clk_tb); + end + end + begin + //Check final output (with or without usehint) + if (vfy) begin + while(dut.usehint_ready != 'hf) @(posedge clk_tb); + for(int i = 0; i < 256; i = i+4) begin + if ({REG_SIZE'(dut.r1_mux[i%4]), REG_SIZE'(dut.r1_mux[i%4+1]), REG_SIZE'(dut.r1_mux[i%4+2]), REG_SIZE'(dut.r1_mux[i%4+3])} != {coeff_high_final[i], coeff_high_final[i+1], coeff_high_final[i+2], coeff_high_final[i+3]}) begin + $error("r1 final does not match in verify mode. Expected = %h %h %h %h, observed = %h %h %h %h at index %0d\n", coeff_high_final[i], coeff_high_final[i+1], coeff_high_final[i+2], coeff_high_final[i+3], dut.r1_mux[i%4], dut.r1_mux[i%4+1], dut.r1_mux[i%4+2], dut.r1_mux[i%4+3],i); + error_flag = 'b1; + end + @(posedge clk_tb); + end + end + else begin + while(dut.mod_ready != 'hf) @(posedge clk_tb); + for(int i = 0; i < 256; i = i+4) begin + if ({REG_SIZE'(dut.r1_mux[i%4]), REG_SIZE'(dut.r1_mux[i%4+1]), REG_SIZE'(dut.r1_mux[i%4+2]), REG_SIZE'(dut.r1_mux[i%4+3])} != {coeff_high[i], coeff_high[i+1], coeff_high[i+2], coeff_high[i+3]}) begin + $error("r1 final does not match in sign mode. Expected = %h %h %h %h, observed = %h %h %h %h at index %0d\n", coeff_high[i], coeff_high[i+1], coeff_high[i+2], coeff_high[i+3], dut.r1_mux[i%4], dut.r1_mux[i%4+1],dut.r1_mux[i%4+2],dut.r1_mux[i%4+3],i); + error_flag = 'b1; + end + @(posedge clk_tb); + end + //TODO: enable below check. genblk needs naming for this to work + // if (vfy) begin + // if (dut.usehint_inst[i].w1_mux[i%4] != coeff_high_usehint[i]) begin + // $error("r1 usehint does not match. Expected = %h, observed = %h at index %0d\n", coeff_high_usehint[i], dut.r1_usehint[i%4], i); + // error_flag = 'b1; + // end + // end + @(posedge clk_tb); + end + end + join + + //Wait for decompose done (i.e., w1 encode done) + //Then wait for a fixed time to emulate keccak done and assert it + while(dut.decompose_done != 1) @(posedge clk_tb); + repeat(100) @(posedge clk_tb); + kdone_tb = 'b1; //emulate keccak done + @(posedge clk_tb); + kdone_tb = 'b0; + if (error_flag) begin + if (vfy) + $display("Decompose + usehint failed\n"); + else if (~vfy) + $display("Decompose failed\n"); + end + else begin + if (vfy) $display("Decompose + usehint success\n"); + else $display("Decompose success\n"); + end + + coeff_tb = 'h0; + hint_tb = 'h0; + +endtask + +task encode_test; + + $display("Reading hex file\n"); + read_test_vectors(); + + $display("Starting w1 encode test\n"); + @(posedge clk_tb); + en_tb <= 1; + for (int poly = 0; poly < 8; poly++) begin + $display("Starting Poly %0d", poly); + for (int i = 0; i < 256; i = i+4) begin + coeff_high_tb <= {$random, $random, $random, $random}; //{coeff_high[i+3], coeff_high[i+2], coeff_high[i+1], coeff_high[i]}; + @(posedge clk_tb); + end + // @(posedge clk_tb); + if (poly == 7) en_tb <= 1'b0; + end + + + kdone_tb <= 'b1; + @(posedge clk_tb); + kdone_tb <= 'b0; + $display("Test done\n"); +endtask + + +initial begin + init_sim(); + reset_dut(); + // sample_buffer_test(); + // r1_lut_test(); + // ctrl_test(); + $display("Signing decompose\n"); + mode_tb = sign_op; + dcmp_test(0); + $display("Verify decompose\n"); + mode_tb = verify_op; + dcmp_test(1); + // encode_test(); + repeat(1000) @(posedge clk_tb); + $finish; +end +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/test_vector.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/test_vector.hex new file mode 100644 index 0000000000000000000000000000000000000000..ed4e9ae24ba0d2915366daaea1eeca9ea732f8ab --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/decompose/tb/test_vector.hex @@ -0,0 +1,256 @@ +0868D2 000001 006AD2 +257616 000005 7D6017 +5F1B16 00000C 7F1317 +1B6C76 000003 037276 +698C42 00000D 01A642 +458FB3 000009 7D81B4 +412E6D 000008 013E6D +6B88FC 00000D 03A2FC +027572 000000 027572 +621086 00000C 022886 +237219 000004 037A19 +7E6B22 000000 7E6B22 +6C6B8D 00000E 7C678E +2F7CA9 000006 7F68AA +77B7CC 00000F 7FB5CD +21F400 000004 01FC00 +2B0E66 000005 031866 +37A9AE 000007 7F97AF +0E58D5 000002 7E3CD6 +5B9C77 00000B 03B277 +46C283 000009 7EB484 +2D4CCF 000006 7D38D0 +2FDE8B 000006 7FCA8C +5C7998 00000C 7C7199 +70FF5E 00000E 011B5E +739890 00000E 03B490 +26018E 000005 7DEB8F +213F5B 000004 01475B +54A629 00000B 7C9C2A +5E64BE 00000C 7E5CBF +2D6803 000006 7D5404 +4AD500 000009 02E700 +5458FC 00000B 7C4EFD +396964 000007 017764 +3128F4 000006 0134F4 +550B06 00000B 7D0107 +64E895 00000D 7CE296 +35FB58 000007 7DE959 +2FBF73 000006 7FAB74 +13D06E 000002 03D46E +1F78A1 000004 7F60A2 +77FB1E 00000F 00191E +507174 00000A 008574 +157753 000003 7D5D54 +2688FA 000005 7E72FB +754830 00000F 7D4631 +62B7AD 00000C 02CFAD +697E2D 00000D 01982D +16A172 000003 7E8773 +5DCA86 00000C 7DC287 +66941D 00000D 7E8E1E +4D74A1 00000A 7D68A2 +770679 00000F 7F047A +1E4A13 000004 7E3214 +1EB32B 000004 7E9B2C +0C78F7 000002 7C5CF8 +2D57BE 000006 7D43BF +7B3D4F 00000F 035B4F +418A83 000008 019A83 +3C7FFA 000008 7C6FFB +3150D6 000006 015CD6 +65DFF0 00000D 7DD9F1 +3F4A2C 000008 7F3A2D +079A9A 000001 7F7C9B +0C357A 000002 7C197B +25A5AE 000005 7D8FAF +7DE8F7 000000 7DE8F7 +392F5D 000007 013D5D +2C0356 000006 7BEF57 +5E29D5 00000C 7E21D6 +72BDA5 00000E 02D9A5 +49147F 000009 01267F +371E4D 000007 7F0C4E +2E0628 000006 7DF229 +0C1983 000002 7BFD84 +7C5491 000000 7C5491 +10C3E9 000002 00C7E9 +0D72EC 000002 7D56ED +115B4E 000002 015F4E +62EC06 00000C 030406 +2D61C4 000006 7D4DC5 +4E35E2 00000A 7E29E3 +563EDF 00000B 7E34E0 +4EE4CF 00000A 7ED8D0 +26BD55 000005 7EA756 +4432DC 000009 7C24DD +63F16A 00000D 7BEB6B +038A5E 000000 038A5E +04F953 000001 7CDB54 +30113C 000006 001D3C +36C8B5 000007 7EB6B6 +6F6888 00000E 7F6489 +738392 00000E 039F92 +67DA88 00000D 7FD489 +343F4D 000007 7C2D4E +0210D2 000000 0210D2 +6D95EF 00000E 7D91F0 +47E409 000009 7FD60A +2DE2FF 000006 7DCF00 +5FCCF4 00000C 7FC4F5 +5EB3B7 00000C 7EABB8 +32E4B7 000006 02F0B7 +007DC1 000000 007DC1 +22B2E4 000004 02BAE4 +12ECB1 000002 02F0B1 +72805E 00000E 029C5E +274140 000005 7F2B41 +695C30 00000D 017630 +3BEFFC 000007 03FDFC +6BB9D4 00000D 03D3D4 +63363C 00000C 034E3C +2F7F29 000006 7F6B2A +5AF391 00000B 030991 +157EB9 000003 7D64BA +63646E 00000C 037C6E +1EFBF6 000004 7EE3F7 +705424 00000E 007024 +51619D 00000A 01759D +044B9F 000001 7C2DA0 +0B927C 000001 03947C +4FB857 00000A 7FAC58 +7CAAEF 000000 7CAAEF +1CD228 000004 7CBA29 +222679 000004 022E79 +5DDB76 00000C 7DD377 +29E79B 000005 01F19B +1F8264 000004 7F6A65 +0C56EB 000002 7C3AEC +600D44 00000C 002544 +620220 00000C 021A20 +166389 000003 7E498A +604CFC 00000C 0064FC +55B44D 00000B 7DAA4E +76720E 00000F 7E700F +0E6AAA 000002 7E4EAB +3F846E 000008 7F746F +250B62 000005 7CF563 +0E6986 000002 7E4D87 +334F5A 000006 035B5A +7F2563 000000 7F2563 +626F43 00000C 028743 +6F6037 00000E 7F5C38 +518511 00000A 019911 +4EC567 00000A 7EB968 +0C49AB 000002 7C2DAC +5B834B 00000B 03994B +195AF6 000003 0160F6 +4878B4 000009 008AB4 +1BFFBB 000004 7BE7BC +66570B 00000D 7E510C +380907 000007 001707 +158874 000003 7D6E75 +241448 000005 7BFE49 +654333 00000D 7D3D34 +1C649A 000004 7C4C9B +6D4CA9 00000E 7D48AA +2AFB83 000005 030583 +3473B0 000007 7C61B1 +77EBAE 00000F 0009AE +4A476C 000009 02596C +2ADF5D 000005 02E95D +7F6DD5 000000 7F6DD5 +4B0A12 000009 031C12 +141D24 000003 7C0325 +168EDF 000003 7E74E0 +24BC09 000005 7CA60A +5F6840 00000C 7F6041 +1E03CD 000004 7DEBCE +732B51 00000E 034751 +3F1F92 000008 7F0F93 +64F99B 00000D 7CF39C +3BF480 000008 7BE481 +0BEF2A 000001 03F12A +14925E 000003 7C785F +29CFD0 000005 01D9D0 +4F3A82 00000A 7F2E83 +65881C 00000D 7D821D +784B73 00000F 006973 +1AD014 000003 02D614 +74C873 00000F 7CC674 +74CCB8 00000F 7CCAB9 +2231B6 000004 0239B6 +20E878 000004 00F078 +597052 00000B 018652 +203805 000004 004005 +19B990 000003 01BF90 +45F2CA 000009 7DE4CB +10AB32 000002 00AF32 +1C37F1 000004 7C1FF2 +7C0298 000000 7C0298 +02C250 000000 02C250 +705F04 00000E 007B04 +49EC44 000009 01FE44 +4F40D2 00000A 7F34D3 +193C2D 000003 01422D +361F18 000007 7E0D19 +426C58 000008 027C58 +11B3C1 000002 01B7C1 +0FD88B 000002 7FBC8C +058CA0 000001 7D6EA1 +0CC11F 000002 7CA520 +0D775E 000002 7D5B5F +0F24B4 000002 7F08B5 +6D42FD 00000E 7D3EFE +1833E3 000003 0039E3 +3E9BB5 000008 7E8BB6 +71757A 00000E 01917A +4FCC21 00000A 7FC022 +7D243C 000000 7D243C +60F523 00000C 010D23 +3450F5 000007 7C3EF6 +1BB5E7 000003 03BBE7 +5C9D3E 00000C 7C953F +250619 000005 7CF01A +31D042 000006 01DC42 +46D65C 000009 7EC85D +33BFF9 000006 03CBF9 +18F9D9 000003 00FFD9 +13DD98 000002 03E198 +64070B 00000D 7C010C +32F637 000006 030237 +5571CC 00000B 7D67CD +57F9F5 00000B 000FF5 +43FBAD 000009 7BEDAE +3BC5BB 000007 03D3BB +2C1667 000006 7C0268 +2821D4 000005 002BD4 +21F3F5 000004 01FBF5 +6D4674 00000E 7D4275 +767CEE 00000F 7E7AEF +2226A7 000004 022EA7 +603DFA 00000C 0055FA +1C00DC 000004 7BE8DD +105444 000002 005844 +446B18 000009 7C5D19 +17B322 000003 7F9923 +38134C 000007 00214C +211248 000004 011A48 +55F87D 00000B 7DEE7E +48F68E 000009 01088E +2ABC8A 000005 02C68A +5F6CCE 00000C 7F64CF +484ACA 000009 005CCA +3C6A72 000008 7C5A73 +5A8AAF 00000B 02A0AF +6B834A 00000D 039D4A +72F837 00000E 031437 +037661 000000 037661 +68854E 00000D 009F4E +0079D0 000000 0079D0 +5D5DC8 00000C 7D55C9 +0ABBE0 000001 02BDE0 +778658 00000F 7F8459 +19E65B 000003 01EC5B +016601 000000 016601 +6D0C16 00000E 7D0817 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/embedded_top/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/embedded_top/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..ecccfd2171f11ec103b265f256f4f5924335fee2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/embedded_top/config/compile.yml @@ -0,0 +1,40 @@ +--- +provides: [mldsa_defines] +schema_version: 2.4.0 +targets: + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_config_defines.svh + - $COMPILE_ROOT/rtl/mldsa_reg_pkg.sv + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_config_defines.svh + - $COMPILE_ROOT/rtl/mldsa_reg_pkg.sv +--- +provides: [embedded_top] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - rej_bounded + - rej_sampler + - exp_mask + - sample_in_ball + - sha3 +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/embedded_top.sv + - $COMPILE_ROOT/rtl/mldsa_reg.sv + tops: [embedded_top] + rtl_lint: + waiver_files: [] + options: [] +global: + tool: + vcs: + default: + - '-assert svaext' \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..f5c6ae18d166b007db65f4ae30ceabcfb05dd3c7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/compile.yml @@ -0,0 +1,34 @@ +--- +provides: [exp_mask] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/exp_mask_ctrl.sv + - $COMPILE_ROOT/rtl/exp_mask.sv + tops: [exp_mask_ctrl] +--- +provides: [exp_mask_tb] +schema_version: 2.4.0 +requires: + - exp_mask + - mldsa_sampler_pkg +targets: + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/exp_mask_tb.sv + tops: [exp_mask_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ref model to ${pwd}" && cp $COMPILE_ROOT/tb/exp_mask.py .' +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+ABR_ASSERT_ON + - '-noinherit_timescale=1ns/1ps' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/exp_mask.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/exp_mask.vf new file mode 100644 index 0000000000000000000000000000000000000000..14bf8cd9fba80ea78298fe8ed4db2814bb5ec9f6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/exp_mask.vf @@ -0,0 +1,35 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/exp_mask_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/exp_mask_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..b9cbed97f5e2c3f02fecda1f3f60e7f5d3974857 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/config/exp_mask_tb.vf @@ -0,0 +1,40 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/tb ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/tb/exp_mask_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/rtl/exp_mask.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/rtl/exp_mask.sv new file mode 100644 index 0000000000000000000000000000000000000000..0b80865bafd90841f74f8354f39f7abaa299a4fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/rtl/exp_mask.sv @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Expand Mask function takes in a sample from the Keccak core +//and returns a coefficient calculated by the function 2^19-a%q + +module exp_mask + import mldsa_params_pkg::*; + #( + parameter EXP_SAMPLE_W = 20 + ,parameter EXP_VLD_SAMPLE_W = 23 + ) + ( + //input data + input logic [EXP_SAMPLE_W-1:0] data_i, + + //output data + output logic [EXP_VLD_SAMPLE_W-1:0] data_o + + ); + + logic [22:0] r0, r1; + logic c0, c1; + + //compute 2^19 - a + always_comb {c0,r0} = (24'd1 << 19) - data_i; + //compute potential % q value + always_comb {c1,r1} = r0 + MLDSA_Q; + //determine if we can take 2^19-a or need to take + q value + always_comb data_o = (c0 & c1) ? {1'b0,r1} : {1'b0,r0}; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/rtl/exp_mask_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/rtl/exp_mask_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..8530e90f18be562756847a0b04ba4d213d5da717 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/rtl/exp_mask_ctrl.sv @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +module exp_mask_ctrl + import mldsa_params_pkg::*; + #( + parameter EXP_NUM_SAMPLERS = 4 + ,parameter EXP_SAMPLE_W = 20 + ,parameter EXP_VLD_SAMPLES = 4 + ,parameter EXP_VLD_SAMPLE_W = 23 + ) + ( + input logic clk, + input logic rst_b, + input logic zeroize, + //input data + input logic data_valid_i, + output logic data_hold_o, + input logic [EXP_NUM_SAMPLERS-1:0][EXP_SAMPLE_W-1:0] data_i, + + //output data + output logic data_valid_o, + output logic [EXP_VLD_SAMPLES-1:0][EXP_VLD_SAMPLE_W-1:0] data_o + + ); + + //No hold here, remove this + always_comb data_hold_o = '0; + + generate + for (genvar inst_g = 0; inst_g < EXP_NUM_SAMPLERS; inst_g++) begin : exp_mask_inst + exp_mask #( + .EXP_SAMPLE_W(EXP_SAMPLE_W), + .EXP_VLD_SAMPLE_W(EXP_VLD_SAMPLE_W) + ) exp_mask_i ( + .data_i(data_i[inst_g]), + .data_o(data_o[inst_g]) + ); + end + endgenerate + +always_comb data_valid_o = data_valid_i & ~zeroize; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/stimulus/tests/directed/exp_rand_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/stimulus/tests/directed/exp_rand_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..acdeb797a2122c2a85dd806971f8d6260521ac6e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/stimulus/tests/directed/exp_rand_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: exp_rand_test +seed: ${PLAYBOOK_RANDOM_SEED} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/tb/exp_mask.py b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/tb/exp_mask.py new file mode 100644 index 0000000000000000000000000000000000000000..bc4e306a14434f6103deb47bf781a82ef68fb9ed --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/tb/exp_mask.py @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import sys +import os +import binascii +from hashlib import shake_128, shake_256 + +DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1 +DILITHIUM_N = 256 +DILITHIUM_LOGN = 8 +DILITHIUM_ROOT_OF_UNITY = 1753 + +## Category 5 parameters: +DILITHIUM_ETA = 2 +DILITHIUM_ETA_BOUND = 15 +DILITHIUM_TAU = 60 +DILITHIUM_GAMMA1 = 2**19 + + +class Shake(): + def __init__(self, algorithm, block_length): + self.algorithm = algorithm + self.block_length = block_length + self.read_blocks = 0 + self.read_data = b"" + + def absorb(self, input_bytes): + self.read_blocks = 0 + self.read_data = b"" + self.xof = self.algorithm(input_bytes) + + def digest(self, input_bytes, length): + return self.algorithm(input_bytes).digest(length) + + def get_n_blocks(self, n): + byte_count = self.block_length * (self.read_blocks + n) + xof_data = self.xof.digest(byte_count) + self.read_blocks += n + self.read_data = xof_data[-self.block_length*n:] + + def read(self, n): + if n > len(self.read_data): + self.get_n_blocks(5*n) + send = self.read_data[:n] + self.read_data = self.read_data[n:] + return send + +Shake128 = Shake(shake_128, 168) +Shake256 = Shake(shake_256, 136) + +def expand_mask(seed): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_GAMMA1 + + if DILITHIUM_GAMMA1 == (1 << 17): + bit_count = 18 + total_bytes = 576 # (256 * 18) / 8 + else: + bit_count = 20 + total_bytes = 680 # multiple of Shake256 640 # (256 * 20) / 8 + + # Initialise the XOF + xof_bytes = Shake256.digest(seed, total_bytes) + r = int.from_bytes(xof_bytes, 'little') + input_vectors.write(f"{r:01360x}") + mask = (1 << bit_count) - 1 + coeffs = [((DILITHIUM_GAMMA1 - ((r >> bit_count*i) & mask)) % DILITHIUM_Q) for i in range(DILITHIUM_N)] + + return coeffs + +#open the input vector file for reading +input_seeds = open("input_seeds.txt", "r") +input_vectors = open("input_vectors.txt", "w") +exp_results = open("exp_results.txt", "w") +log_file = open("rej_sampler.log", "w") +Lines = input_seeds.readlines() + +for line in Lines: + Coeffs = expand_mask( bytes(line.strip(),'utf-8') ) + for coeff in Coeffs: + exp_results.write(f"{coeff:06x}"+" ") + input_vectors.write("\n") + exp_results.write("\n") + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/tb/exp_mask_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/tb/exp_mask_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..1bfe8b897d1fd88e1fbbf981c7f30df7e3a35534 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/exp_mask/tb/exp_mask_tb.sv @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// exp_mask_tb.sv +// -------- +// +//====================================================================== + +import "DPI-C" function string getenv(input string env_name); + +`include "mldsa_config_defines.svh" + +module exp_mask_tb + import mldsa_sampler_pkg::*; + import mldsa_params_pkg::*; +( +`ifdef VERILATOR + input bit clk_tb +`endif + ); + + `ifndef VERILATOR + int MAX_CYCLES; + int VEC_CNT; + + initial begin + // To use this from the command line, add "+MAX_CYCLES=" + // to override the sim timeout + if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin + $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES); + end else begin + MAX_CYCLES = 20_0000; + $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES); + end + if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin + $info("Received argument +VEC_CNT, with value %d", VEC_CNT); + end else begin + VEC_CNT = 10; + $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT); + end + end + `else + parameter MAX_CYCLES = 20_0000; + `endif + + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 5; + + //input data to piso + logic data_valid_i; + logic data_hold_o; + logic [EXP_PISO_INPUT_RATE-1:0] data_i; + + //input data + logic piso_valid; + logic piso_hold; + logic [EXP_NUM_SAMPLERS-1:0][EXP_SAMPLE_W-1:0] piso_data; + + //output data + logic data_valid_o; + logic [EXP_VLD_SAMPLES-1:0][EXP_VLD_SAMPLE_W-1:0] data_o; + + logic zeroize; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] vld_coeff_ctr; + reg [31 : 0] tc_ctr; + +`ifndef VERILATOR + reg clk_tb; +`endif + reg clk_i; + reg reset_n_tb; + reg rst_ni; + reg [31 : 0] read_data; + + assign clk_i = clk_tb; + assign rst_ni = reset_n_tb; + + logic [MLDSA_Q_WIDTH-1:0] exp_result; + logic [MLDSA_Q_WIDTH-1:0] expected_results[$]; // queue of results + + string seed_filename, vector_filename, exp_res_filename; + assign exp_res_filename = "exp_results.txt"; + assign seed_filename = "input_seeds.txt"; + assign vector_filename = "input_vectors.txt"; + + int fd_r_exp; + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + abr_piso #( + .PISO_BUFFER_W(EXP_PISO_BUFFER_W), + .PISO_INPUT_RATE(EXP_PISO_INPUT_RATE), + .PISO_OUTPUT_RATE(EXP_PISO_OUTPUT_RATE) + ) piso_i ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + .valid_i(data_valid_i), + .hold_o(data_hold_o), + .data_i(data_i), + .valid_o(piso_valid), + .hold_i(piso_hold), + .data_o(piso_data) + ); + + + exp_mask_ctrl #( + .EXP_NUM_SAMPLERS(EXP_NUM_SAMPLERS), + .EXP_SAMPLE_W(EXP_SAMPLE_W), + .EXP_VLD_SAMPLES(EXP_VLD_SAMPLES), + .EXP_VLD_SAMPLE_W(EXP_VLD_SAMPLE_W) + ) dut ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + //input data + .data_valid_i(piso_valid), + .data_hold_o(piso_hold), + .data_i(piso_data), + + //output data + .data_valid_o(data_valid_o), + .data_o(data_o) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- +`ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen +`endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + + // Test timeout monitor + if(cycle_ctr == MAX_CYCLES) begin + $error("Hit max cycle count (%0d) .. stopping",cycle_ctr); + $finish; + end + end + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + + repeat (2) @(posedge clk_tb); + + $display(""); + end + endtask // reset_dut + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + error_ctr = '0; + tc_ctr = '0; + vld_coeff_ctr = '0; +`ifndef VERILATOR + clk_tb = 0; +`endif + reset_n_tb = 0; + + zeroize = 0; + data_valid_i = '0; + data_i = '0; + + end + endtask // init_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + //---------------------------------------------------------------- + // Scoreboard + //---------------------------------------------------------------- + + initial begin + forever begin + @(posedge clk_tb) + if (data_valid_o) begin + if (expected_results.size() >= EXP_VLD_SAMPLES) begin + for (int i = 0; i < EXP_VLD_SAMPLES; i++) begin + vld_coeff_ctr += 1; //increment vld coeff ctr + if (expected_results[0] != data_o[i]) begin + //ERROR + $display("[%t] Expected results mismatch for output index %d", $time, i); + $display("[%t] Actual: %x", $time,data_o[i]); + $display("[%t] Expected: %x", $time,expected_results[0]); + error_ctr += 1; + end + expected_results.pop_front(); + end + end else begin + //ERROR + $display("[%t] Not enough valid samples in the queue", $time); + error_ctr += 1; + end + end + end + + end + + initial begin + forever begin + @(posedge clk_tb) + if (vld_coeff_ctr == 256) begin + zeroize <= 1; + @(posedge clk_tb) + zeroize <= 0; + end + end + end + + initial begin + forever begin + @(posedge zeroize) + vld_coeff_ctr = '0; + expected_results = {}; + end + end + + //---------------------------------------------------------------- + // write_single_msg() + // + // Write the given msg to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_single_msg(logic [EXP_PISO_INPUT_RATE-1:0] rand_samples); + begin + data_valid_i <= 1; + data_i <= rand_samples; + + + @(posedge clk_tb); + //Make sure no hold + //drop this transaction if zeroize is set + while ((data_hold_o == 1) & (zeroize == 0)) @(posedge clk_tb); + + //@(posedge clk_tb); + data_valid_i <= 0; + data_i <= 'x; + + end + endtask // write_single_msg + + //---------------------------------------------------------------- + // gen_rand_test_vectors() + //---------------------------------------------------------------- + task gen_rand_test_vectors; + int fd_w; + + fd_w = $fopen(seed_filename, "a"); + if (fd_w == 0) $error("Cannot open file %s for writing", seed_filename); + + for (int i = 0; i < VEC_CNT; i++) begin + //Write random_ eeds + $fwrite(fd_w, "%0d \n", $urandom()); + end + $fclose(fd_w); + //generate input vectors and expected results + $system($sformatf("python exp_mask.py")); + + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + endtask + + + //---------------------------------------------------------------- + // run_rand_test() + //---------------------------------------------------------------- + parameter PISO_INPUT_CHARS = EXP_PISO_INPUT_RATE/4; + parameter PISO_INPUT_DWORDS = EXP_PISO_INPUT_RATE/32; + task run_rand_test; + int fd_r_inp; + string line_read; + string line_substr; + int num_states; + logic [PISO_INPUT_DWORDS-1:0][31:0] test_data; + + //open input vectors + fd_r_inp = $fopen(vector_filename, "r"); + if (fd_r_inp == 0) begin + $error("Cannot open file %s for reading", vector_filename); + error_ctr++; + end + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + for (int iter = 0; iter < VEC_CNT; iter++) begin + //get the next exp result + if (!($fgets(line_read, fd_r_exp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + for (int res = 0; res < MLDSA_N; res++) begin + exp_result = line_read.substr(res*7, res*7 + 7-2).atohex(); + expected_results.push_back(exp_result); + end + + //get the next input vector + if (!($fgets(line_read, fd_r_inp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + + num_states = (line_read.len()/PISO_INPUT_CHARS); + //$display("Vector Length: %d", line_read.len()); + //$display("Number of states: %d", num_states); + for (int state = num_states-1; state >= 0; state--) begin + line_substr = line_read.substr(state*PISO_INPUT_CHARS , (state*PISO_INPUT_CHARS)+PISO_INPUT_CHARS-1); + //$display("State: %s", line_substr); + for (int dword = 0; dword < PISO_INPUT_DWORDS; dword++) begin + test_data[dword] = line_substr.substr((PISO_INPUT_CHARS - dword*8 - 8), (PISO_INPUT_CHARS - dword*8 - 1)).atohex(); + //$display("Dword: %d - %h", dword, test_data[dword]); + end + write_single_msg(test_data); + end + + wait (zeroize == 1); + wait (zeroize == 0); + + tc_ctr++; + + end + + $fclose(fd_r_inp); + + endtask // run_hw_if_test + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + + initial + begin : main + $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED")); + $display(" -- Testbench for EXP_MASK started --"); + + init_sim(); + reset_dut(); + + gen_rand_test_vectors(); + run_rand_test(); + + @(posedge clk_tb); + display_test_result(); + + $display(" -- Testbench for EXP_MASK done. --"); + $finish; + end // main + +endmodule // exp_mask_tb + +//====================================================================== +// EOF exp_mask_tb.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..bb592bd4dcdc16e7ebe97c2d49de39e92c612c7f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/compile.yml @@ -0,0 +1,49 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [makehint_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/makehint_defines_pkg.sv +--- +provides: [makehint] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - makehint_pkg + - ntt_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/hintgen.sv + - $COMPILE_ROOT/rtl/makehint.sv + + tops: [makehint] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/makehint/config/design_lint/makehint/sglint_waivers +--- +provides: [makehint_tb] +schema_version: 2.4.0 +requires: + - makehint + - makehint_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/makehint_tb.sv + tops: [makehint_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying r hex to $PWD" && cp $COMPILE_ROOT/tb/r.hex . && cp $COMPILE_ROOT/tb/z.hex .' + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/design_lint/makehint/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/design_lint/makehint/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint.vf new file mode 100644 index 0000000000000000000000000000000000000000..f5d79f09db62ed2db2db97c57ec52e9fe1c346c8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint.vf @@ -0,0 +1,38 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/hintgen.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..3c814494b45a46c785d0e43fef5d8469cbeb2661 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/rtl +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..c6a0d623d4d610cf0cf43f962c8e9c458a8824d1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/config/makehint_tb.vf @@ -0,0 +1,40 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/hintgen.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint.sv +${ADAMSBRIDGE_ROOT}/src/makehint/tb/makehint_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/hintgen.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/hintgen.sv new file mode 100644 index 0000000000000000000000000000000000000000..ccda574e06fc64f1382d863a967fc55fd25b444f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/hintgen.sv @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// hintgen.sv +// -------- +// Processes (r, z) inputs and produces a 4-bit hint vector per coefficient +// of a given polynomial. +//====================================================================== + +module hintgen + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 23'd8380417, + // parameter GAMMA2 = (MLDSA_Q-1)/32, + parameter Q_MINUS_GAMMA2 = MLDSA_Q - MLDSA_GAMMA2 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire enable, + input wire [REG_SIZE-1:0] r, + input wire z_neq_z, + output logic h + + ); + + logic r_lt_gamma2; + logic r_gt_q_minus_gamma2; + logic r_eq_q_minus_gamma2; + logic or1_res, or2_res, and_res, not_res; + + //TODO: need flop here? commenting out for now + // always_ff @(posedge clk or negedge reset_n) begin + // if (!reset_n) + // h <= 'b0; + // else if (zeroize) + // h <= 'b0; + // else if (enable) + // h <= or2_res; + // else + // h <= 'b0; + // end + + assign h = (enable & ~zeroize) ? or2_res : 'b0; + + always_comb begin + r_lt_gamma2 = (r <= MLDSA_GAMMA2) ? 1'b1 : 1'b0; + r_gt_q_minus_gamma2 = (r >= Q_MINUS_GAMMA2) ? 1'b1 : 1'b0; + r_eq_q_minus_gamma2 = (r == Q_MINUS_GAMMA2) ? 1'b1 : 1'b0; + end + + always_comb begin + or1_res = r_lt_gamma2 | r_gt_q_minus_gamma2; + and_res = r_eq_q_minus_gamma2 & z_neq_z; + not_res = ~or1_res; + or2_res = not_res | and_res; + end +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/makehint.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/makehint.sv new file mode 100644 index 0000000000000000000000000000000000000000..b264baf75d743bbb0315e4c57b98d8a410774598 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/makehint.sv @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// makehint.sv +// -------- +// Processes (r, z) inputs and produces a 4-bit hint vector per coefficient +// of a given polynomial. The hint is then checked and the index corresponding +// to 1 in the hint vector is captured in the sample buffer. 1 dword at a time +// is written to reg API +// 1. For the last poly, buffer data_o is written irrespective of number of index +// 2. If only a few indices were captured, we still need to fill rest of bytes of +// 'h' component of signature with 0s. (Length of h is 84 bytes). +// So, we need a check to see how many dwords were written and fill in rest with 0s +// 3. At the end of all polys, another write is required to 83rd byte with max index +// vector +// 4. Generate an invalid flag if any of the max indices is > 75 and keep it set until +// a zeroize or restart is given (TODO: check how restart is given - in the form of a zeroize? Or do we keep track here) +// TODO: we need a separate restart bit that is HW driven while zeroize is SW driven +// Restart bit is asserted for every signing iteration to reset sensitive flops +//====================================================================== + +module makehint + import mldsa_params_pkg::*; + import makehint_defines_pkg::*; + #( + parameter REG_SIZE = 24, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_N = 256, + parameter MLDSA_K = 8, + parameter OMEGA = 75, + parameter BUFFER_DATA_W = 8 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire makehint_enable, + input wire [(4*REG_SIZE)-1:0] r, + input wire [3:0] z, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] mem_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, //reg API base addr - TODO: finalize size + + output logic invalid_h, + output mem_if_t mem_rd_req, + output mem_if_t z_rd_req, + output logic makehint_done, + output logic reg_wren, + output logic [3:0][7:0] reg_wrdata, + output logic [MLDSA_MEM_ADDR_WIDTH-1:0] reg_wr_addr + ); + + //Internal wires + logic hintgen_enable, hintgen_enable_reg; + logic [3:0] hint; + logic [MLDSA_K-1:0][7:0] max_index_buffer; + logic [31:0] max_index_buffer_data; + logic max_index_buffer_rd_lo, max_index_buffer_rd_mid, max_index_buffer_rd_hi; + logic max_index_buffer_rd; + + //Sample buffer wires + //Flush buffer will perform last write of last polynomial irrespective of data_valid from sample buffer. + //This will take care of the case where at the end of index count, if buffer has < NUM_WR values, we still want to capture into reg API, padded with 0s + //For each poly_done, sample_buffer continues to capture values as they come in and this extra write is not required until the end + logic flush_buffer, flush_buffer_reg; + logic sample_valid; + logic [3:0][BUFFER_DATA_W-1:0] sample_data; + + //Index counter + logic [3:0][7:0] index; + logic [7:0] index_count; + logic incr_index, incr_index_d1, incr_index_d2; + + //Polynomial counter + logic [$clog2(MLDSA_K)-1:0] poly_count; + logic incr_poly; + logic poly_done; + logic poly_last, poly_last_reg; + + //Read addr counter + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr, reg_wr_addr_nxt, z_rd_addr; + logic incr_mem_rd_addr; + logic rst_rd_addr; + logic last_addr_read; + + //Read fsm + mh_read_state_e read_fsm_state_ps, read_fsm_state_ns; + logic arc_MH_IDLE_MH_RD_MEM; + logic arc_MH_RD_MEM_MH_WAIT1; + logic arc_MH_WAIT2_MH_IDLE; + // logic arc_MH_WAIT_MH_RD_MEM; //TODO don't need wait if we do all polys back to back? check this later + logic arc_MH_WAIT2_MH_FLUSH; + + //Hint sum + logic [7:0] hintsum; + logic busy_reg; + logic latch_hintsum_addr; + + //Busy flag + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + busy_reg <= 'b0; + else if (zeroize) + busy_reg <= 'b0; + else + busy_reg <= (read_fsm_state_ps != MH_IDLE); + end + + //Delay adjustment + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + hintgen_enable_reg <= 'b0; + else if (zeroize) + hintgen_enable_reg <= 'b0; + else + hintgen_enable_reg <= hintgen_enable; + end + + //Keep count of index. Input is 4 coeffs per cycle. Have a vector that counts + //(0, 1, 2, 3), (4, 5, 6, 7), etc + //Flop incr_index twice to account for 1 cycle of mem read latency + 1 cycle of hintgen latency + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + incr_index_d1 <= 'h0; + incr_index_d2 <= 'h0; + end + else if (zeroize | makehint_done) begin + incr_index_d1 <= 'h0; + incr_index_d2 <= 'h0; + end + else begin + incr_index_d1 <= incr_index; + incr_index_d2 <= incr_index_d1; + end + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + index_count <= 'h0; + end + else if (zeroize | makehint_done) begin + index_count <= 'h0; + end + else if (incr_index_d1) begin + index_count <= index_count + 'h4; + end + end + + always_comb begin + index[0] = incr_index_d1 ? index_count : 'h0; + index[1] = incr_index_d1 ? index_count + 'h1 : 'h0; + index[2] = incr_index_d1 ? index_count + 'h2 : 'h0; + index[3] = incr_index_d1 ? index_count + 'h3 : 'h0; + end + + //Keep count of polynomial. 1 polynomial needs 64 memory addr accesses == 256 index count (0 to 255) + //After each poly_done, record the last index into max_index_buffer + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + poly_count <= 'h0; + else if (zeroize | makehint_done) + poly_count <= 'h0; + else if (incr_poly) + poly_count <= poly_count + 'h1; + end + + always_comb begin + poly_done = incr_poly; //last_addr_read; + poly_last = (poly_count == 'h7); + flush_buffer = (read_fsm_state_ps == MH_FLUSH_SBUF); //poly_last & poly_done; //TODO: check to make sure all indexes have been processed before this flag goes high + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + poly_last_reg <= 'b0; + flush_buffer_reg <= 'b0; + end + else if (zeroize | makehint_done) begin + poly_last_reg <= 'b0; + flush_buffer_reg <= 'b0; + end + else begin + poly_last_reg <= poly_last; + flush_buffer_reg <= flush_buffer; + end + end + + //----------------------- + //Count number of 1s in each poly + //----------------------- + //Sample_data from sample buffer also gives this, but we don't know where the last index would be in the 4 bytes of data received from the buffer + //Instead count 1s manually and store sum into max_index_buffer for every poly_done + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + hintsum <= 'h0; + else if (zeroize | makehint_done) + hintsum <= 'h0; + else + hintsum <= hintsum + hint[3] + hint[2] + hint[1] + hint[0]; + end + + + //----------------------- + //Populate max_index_buffer + //----------------------- + always_comb max_index_buffer_rd = max_index_buffer_rd_lo | max_index_buffer_rd_mid | max_index_buffer_rd_hi; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + max_index_buffer <= 'h0; + else if (zeroize | makehint_done) + max_index_buffer <= 'h0; + else if (poly_done) + max_index_buffer <= {hintsum, max_index_buffer[MLDSA_K-1:1]}; + end + assign max_index_buffer_data = max_index_buffer_rd_lo ? {max_index_buffer[0], 24'h0} : + max_index_buffer_rd_mid ? max_index_buffer[4:1] : + max_index_buffer_rd_hi ? {8'h0, max_index_buffer[7:5]} : 'h0; + + //Reg API + //Write from sample buffer for each dword captured per polynomial. + //If last poly is done, flush buffer and write to reg API + //After that, write the max_index_buffer contents to reg API - using delayed poly_last as the wren in this case + assign reg_wren = sample_valid | flush_buffer | max_index_buffer_rd; + assign reg_wrdata = max_index_buffer_rd ? max_index_buffer_data : (sample_valid | flush_buffer) ? sample_data : 'h0; + + always_comb reg_wr_addr_nxt = latch_hintsum_addr ? (OMEGA/4) : reg_wr_addr + 'h1; //Latch hintsum dword addr at the end of hint processing + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + reg_wr_addr <= 'h0; + end + else if (zeroize | makehint_done) begin + reg_wr_addr <= 'h0; + end + else if (sample_valid | flush_buffer | max_index_buffer_rd) begin + reg_wr_addr <= dest_base_addr + reg_wr_addr_nxt; + end + end + + assign invalid_h = (hintsum > OMEGA); + + //---------------------------- + //Read addr counter + //---------------------------- + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_rd_addr <= 'h0; + z_rd_addr <= 'h0; + end + else if (zeroize) begin + mem_rd_addr <= 'h0; + z_rd_addr <= 'h0; + end + else if (rst_rd_addr) begin + mem_rd_addr <= mem_base_addr; + z_rd_addr <= 'h0; + end + else if (incr_mem_rd_addr) begin + mem_rd_addr <= (poly_last && last_addr_read) ? mem_base_addr : mem_rd_addr + 'h1; + z_rd_addr <= (poly_last && last_addr_read) ? 'h0 : z_rd_addr + 'h1; + end + end + + assign last_addr_read = (mem_rd_addr == mem_base_addr + MLDSA_MEM_ADDR_WIDTH'(((poly_count+1) * (MLDSA_N/4))-1)); + + //---------------------------- + //Read fsm + //---------------------------- + //State machine to control memory rd addr/en and buffer read + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= MH_IDLE; + else if (zeroize) + read_fsm_state_ps <= MH_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; + end + + //Arc assignment + always_comb begin + //Start makehint upon seeing enable trigger + arc_MH_IDLE_MH_RD_MEM = (read_fsm_state_ps == MH_IDLE) && makehint_enable; + //When any poly is done (last or not), wait for 1 cyc to give time for sample buffer to process last coeffs + arc_MH_RD_MEM_MH_WAIT1 = (read_fsm_state_ps == MH_RD_MEM) && last_addr_read; + //When non-last poly is done, move to IDLE and wait for next enable. Opt - if we know all 8 poly will be back to back, we can remain in RD_MEM and wrap addr around + take new base addr if needed, calc hints and continue execution without waiting in IDLE for HLC to give enable + arc_MH_WAIT2_MH_IDLE = (read_fsm_state_ps == MH_WAIT2) && !poly_last; + //When non-last poly is done, go back to RD_MEM and continue executing + arc_MH_WAIT2_MH_FLUSH = (read_fsm_state_ps == MH_WAIT2) && (poly_count == MLDSA_K-1); + end + + always_comb begin + read_fsm_state_ns = read_fsm_state_ps; + incr_mem_rd_addr = 'b0; + incr_index = 'b0; + rst_rd_addr = 'b0; + hintgen_enable = 'b0; + max_index_buffer_rd_lo = 'b0; + max_index_buffer_rd_mid = 'b0; + max_index_buffer_rd_hi = 'b0; + incr_poly = 'b0; + latch_hintsum_addr = 'b0; + unique case(read_fsm_state_ps) + MH_IDLE: begin + read_fsm_state_ns = arc_MH_IDLE_MH_RD_MEM ? MH_RD_MEM : MH_IDLE; + rst_rd_addr = 'b1; + end + MH_RD_MEM: begin + //Read memory and produce hints for (r,z) + read_fsm_state_ns = arc_MH_RD_MEM_MH_WAIT1 ? MH_WAIT1 : MH_RD_MEM; + incr_mem_rd_addr = 'b1; + incr_index = 'b1; + hintgen_enable = 'b1; + end + MH_WAIT1: begin + read_fsm_state_ns = MH_WAIT2; + end + MH_WAIT2: begin + //After all 64 addr are done, wait for 1 clk to let sample buffer finish last coeff + read_fsm_state_ns = arc_MH_WAIT2_MH_FLUSH ? MH_FLUSH_SBUF : MH_RD_MEM; //arc_MH_WAIT2_MH_RD_MEM ? MH_RD_MEM : MH_FLUSH_SBUF_LOW; + incr_poly = 'b1; + end + MH_FLUSH_SBUF: begin + //If last poly, flush sample buffer + read_fsm_state_ns = MH_RD_IBUF_LOW; + latch_hintsum_addr = 'b1; //prepare for next state + end + MH_RD_IBUF_LOW: begin + //last poly, write lower dword of max idx buf to reg API + read_fsm_state_ns = MH_RD_IBUF_MID; + max_index_buffer_rd_lo = 'b1; + end + MH_RD_IBUF_MID: begin + read_fsm_state_ns = MH_RD_IBUF_HIGH; + max_index_buffer_rd_mid = 'b1; + end + MH_RD_IBUF_HIGH: begin + //last poly, write higher dword of max idx buf to reg API + read_fsm_state_ns = MH_IDLE; + max_index_buffer_rd_hi = 'b1; + end + default: begin + read_fsm_state_ns = MH_IDLE; + end + endcase + end + + //Assign output + assign mem_rd_req.rd_wr_en = (read_fsm_state_ps == MH_RD_MEM) ? RW_READ : RW_IDLE; + assign mem_rd_req.addr = mem_rd_addr; + assign z_rd_req.rd_wr_en = (read_fsm_state_ps == MH_RD_MEM) ? RW_READ : RW_IDLE; + assign z_rd_req.addr = z_rd_addr; + assign makehint_done = (read_fsm_state_ps == MH_IDLE); + + generate + for (genvar i = 0; i < 4; i++) begin + hintgen #( + .REG_SIZE(REG_SIZE-1) + ) + hint_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .enable(hintgen_enable_reg), + .r(r[(REG_SIZE*i)+(REG_SIZE-2):(REG_SIZE*i)]), //remove MSB 0 since coeff coming from memory is 24 bit + .z_neq_z(z[i]), + .h(hint[i]) + ); + end + endgenerate + + abr_sample_buffer #( + .NUM_WR(4), + .NUM_RD(4), + .BUFFER_DATA_W(BUFFER_DATA_W) + ) + hint_index_buffer_inst ( + .clk(clk), + .rst_b(reset_n), + .zeroize(zeroize | flush_buffer), + .data_valid_i(hint), + .data_i(index), + .buffer_full_o(), + .data_valid_o(sample_valid), + .data_o(sample_data) + ); + + + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/makehint_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/makehint_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..e401ae9cf0f579aec5af1005e49954a5d52511a9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/rtl/makehint_defines_pkg.sv @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// makehint_defines_pkg.sv +// -------- +// Makehint parameters for Mldsa +//====================================================================== + +`ifndef MLDSA_MAKEHINT_DEFINES +`define MLDSA_MAKEHINT_DEFINES + +package makehint_defines_pkg; + + typedef enum logic [2:0] {MH_IDLE, MH_RD_MEM, MH_WAIT1, MH_WAIT2, MH_FLUSH_SBUF, MH_RD_IBUF_LOW, MH_RD_IBUF_HIGH, MH_RD_IBUF_MID} mh_read_state_e; + +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/stimulus/tests/directed/makehint_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/stimulus/tests/directed/makehint_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..42f6c39333fe33853fb262a59af67051ebc480b1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/stimulus/tests/directed/makehint_normal_test.yml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- + +testname: makehint_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/makehint_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/makehint_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..4cabc3c2fd015b20754f2cff8f4372baf65a4a6d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/makehint_tb.sv @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// makehint_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module makehint_tb + import makehint_defines_pkg::*; + import mldsa_params_pkg::*; +#( + parameter NUM_WR = 4, + parameter NUM_RD = 4, + parameter BUFFER_DATA_W = 8, + parameter REG_SIZE = 24 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg en_tb; +reg [(4*24)-1:0] coeff_tb; +reg [NUM_WR-1:0] z_tb; +reg [NUM_WR-1:0] hint_4bit_tb; +reg [NUM_WR-1:0][BUFFER_DATA_W] index_tb; +reg [(64*8)-1:0][4*REG_SIZE-1:0] coeff_array; //8 polys with 64 addr each +reg [(64*8)-1:0][3:0] z_array; + + + +makehint #( + .BUFFER_DATA_W(BUFFER_DATA_W) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .makehint_enable(en_tb), + .r(coeff_tb), + .z(z_tb), + .mem_base_addr(MLDSA_MEM_ADDR_WIDTH'(0)), + .dest_base_addr(MLDSA_MEM_ADDR_WIDTH'(0)), + .invalid_h(), + .mem_rd_req(), + .z_rd_req(), + .makehint_done(), + .reg_wren(), + .reg_wrdata(), + .reg_wr_addr() + +); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + // hint_4bit_tb = 0; + // index_tb = 0; + zeroize_tb = 0; + en_tb = 0; + coeff_tb = 0; + z_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + // cptra_pwrgood_tb = '0; + reset_n_tb = 0; + + // #(2 * CLK_PERIOD); + // cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + + +task read_test_vectors(); + string fname; + integer file; + string line; + integer i, ret, j; + + for (j = 0; j < 2; j++) begin + i = 0; + if (j == 0) begin + $display("reading coeffs\n"); + fname = "r.hex"; + end + else if (j == 1) begin + $display("reading z vector\n"); + fname = "z.hex"; + end + + file = $fopen(fname, "r"); + if (file == 0) $error("Cannot open %s for reading\n", fname); + + while (!$feof(file)) begin + if ($fgets(line, file)) begin + if (j == 0) + ret = $sscanf(line, "%h", coeff_array[i]); + else if (j == 1) + ret = $sscanf(line, "%b", z_array[i]); + i = i + 1; + end + end + + $fclose(file); + end + + +endtask + +task sample_buffer_test; + $display("Starting buffer test\n"); + @(posedge clk_tb); + for (int i = 0; i < 64; i++) begin + hint_4bit_tb = i; + index_tb = {BUFFER_DATA_W'(i*4+7), BUFFER_DATA_W'(i*4+6), BUFFER_DATA_W'(i*4+5), BUFFER_DATA_W'(i*4+4), BUFFER_DATA_W'(i*4+3), BUFFER_DATA_W'(i*4+2), BUFFER_DATA_W'(i*4+1), BUFFER_DATA_W'(i*4)}; + @(posedge clk_tb); + end + @(posedge clk_tb); +endtask + +task makehint_test; + $display("Starting makehint test\n"); + en_tb = 1; + @(posedge clk_tb); + en_tb = 0; + @(posedge clk_tb); + for (int poly = 0; poly < 8; poly++) begin + $display("Starting Poly %0d", poly); + for (int i = 0; i < 64; i++) begin + coeff_tb = coeff_array[(64*poly)+i]; + z_tb = z_array[(64*poly)+i]; + @(posedge clk_tb); + end + $display("Wait 2 cycles to let poly finish\n"); //To emulate 1 cycle transition between polynomials + @(posedge clk_tb); + @(posedge clk_tb); + end + @(posedge clk_tb); + $display("Wait for done signal from makehint\n"); + while(!dut.makehint_done) + @(posedge clk_tb); + $display("Hint sum = %d, invalid_h = %0d", dut.hintsum, dut.invalid_h); + $display("Test done\n"); +endtask + +initial begin + init_sim(); + reset_dut(); + read_test_vectors(); + makehint_test(); + repeat(1000) @(posedge clk_tb); + $finish; +end +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/r.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/r.hex new file mode 100644 index 0000000000000000000000000000000000000000..b384a07c359d86d77e424e98bb820dd2889aab61 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/r.hex @@ -0,0 +1,512 @@ +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 +00B8C000E64900ED3401FB9F +01A33001BD2301606402DDA0 +031E8B0311A9002883021FB6 +02976B0283C203BF11009E87 +00850E02F5AB026F19039D74 +00635D021580028694023C9F +03B20B02E9D30009F7014205 +01B9DA0328F702C395035B44 +0147DE008D94032E5B01522F +0114CD007CB003DCF803473C +003C8C03011D001F7B00D292 +029B6C0124270277AA02C340 +03BA570036E80257A100F662 +020A0D02512302D046014620 +012A2503974D000EF602AD98 +0209170173D001ABC30396B5 +007096013D5D00A09E02655B +0274A7010EA003887F0259C9 +03FECB02C43902FF0E02D6C0 +0193BE01662E01CB85025E3D +01B5FC01A2D801DC9F02467B +0142D6023230036B1C017D0D +019CD402722F03F14801FFD6 +0234B500D5C40342ED01CF38 +03F65001B1F803991400494A +005E0101E2CA03F74B03C6F7 +0384E5028F8A026F60027DB5 +01BE4302B5A2015E3402625F +02146A01FEF4004A6702083E +01B4E400C70600BD77015B5B +02C2920250DE00045700F5FC +0114AA033AAD010FFD00E9BC +001B2200DCC50368C000D833 +0081EF022BBC02654200A559 +01062801A2B203DBA0008246 +00505E00D7D10153DB02302C +020F8E03685C039BFB031EAE +03AB840027E50240670263CC +0227ED00B616006330030AD6 +03E40702831602A1CE00B501 +025020022679022311011EDF +015F53024125004579035F69 +035E5803365602C02500B9CB +0169560194C300CAE803D111 +03AB8E00FB8900AE3A00A69A +0312CE03F4E202BF09011E6D +000B2A008BFC0310B102F08F +0011490017C701602103FC72 +0255380237A903FD8D02F978 +006D7E03E025000E8B00B31B +0023740252970364B5020ECB +00C1C301EF64012FA30205B3 +02AB4A01E42C02E94102B9A7 +02967D023B3100F589035F28 +02D9C203345703764E026614 +0308D802D1D403864A013AED +019FED01EB14000E35001F26 +00948A003D910350CA018DAB +00029600CB4A03B05D020FAE +029CE2007B1A0268D502CE0E +034B6E01F795011A7501C259 +01992A00D1210093AE0360C1 +4FDE4303901001B7830244DE +151E9D12C0EA12E76D71C0E4 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/z.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/z.hex new file mode 100644 index 0000000000000000000000000000000000000000..fb5b42862f4275c968ba203658a13b1d10f6ac0f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/makehint/tb/z.hex @@ -0,0 +1,512 @@ +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +0111 +1111 +1101 +1101 +1010 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +0111 +1111 +1111 +1111 +1101 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1011 +1111 +1111 +1111 +1111 +1100 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +0111 +1111 +1111 +1011 +1111 +1110 +1111 +1111 +1111 +1111 +1111 +1011 +1111 +0111 +1111 +1111 +1111 +0111 +1111 +1011 +1111 +1110 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +0111 +1111 +1110 +1101 +1100 +1111 +1111 +1111 +1101 +1111 +1111 +1101 +1111 +1111 +1111 +1111 +1111 +1101 +1011 +1110 +1111 +1111 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +0111 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1110 +1101 +1111 +1101 +1001 +1111 +1111 +1110 +0011 +1110 +1111 +1111 +1111 +1110 +1111 +1110 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1001 +1111 +1101 +1111 +1111 +0111 +1111 +1011 +1101 +1111 +1111 +1111 +1111 +1110 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1011 +1011 +1111 +1111 +1111 +1110 +1111 +0111 +1111 +1111 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +0110 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1011 +0111 +1111 +1111 +1111 +0111 +1111 +1011 +1111 +1111 +1111 +1111 +1011 +1101 +1111 +1111 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +1111 +1111 +1011 +1110 +1111 +1111 +1111 +0110 +1111 +1111 +1111 +1111 +1111 +0111 +0111 +1111 +1011 +1111 +1111 +1001 +1110 +1111 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1011 +1111 +1011 +0111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1101 +1111 +1110 +1111 +1011 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +1111 +1111 +1111 +1111 +1110 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1100 +1111 +1111 +1011 +1110 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1101 +1101 +1011 +1111 +1111 +1111 +1111 +1101 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1101 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +0111 +1111 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1010 +1011 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +0111 +1111 +1011 +1111 +1111 +1111 +1111 +1011 +1111 +1111 +1111 +1111 +1111 +1111 +1111 +1111 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..7cd95d64e40b7a333b0f86cdd371928d0ead1282 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/compile.yml @@ -0,0 +1,32 @@ +--- +provides: [mldsa_sampler_pkg] +schema_version: 2.4.0 +requires: + - mldsa_defines +targets: + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_sampler_pkg.sv + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_sampler_pkg.sv +--- +provides: [mldsa_sampler_top] +schema_version: 2.4.0 +requires: + - mldsa_sampler_pkg + - mldsa_defines + - abr_libs + - rej_bounded + - rej_sampler + - exp_mask + - sample_in_ball + - abr_sha3 +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_sampler_top.sv + tops: [mldsa_sampler_top] diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/mldsa_sampler_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/mldsa_sampler_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..e4be8de90526ad018be929222e752b480c2adb6a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/mldsa_sampler_pkg.vf @@ -0,0 +1,7 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/mldsa_sampler_top.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/mldsa_sampler_top.vf new file mode 100644 index 0000000000000000000000000000000000000000..ffe264f9487ce0759c15c80a614f625db5497dbf --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/config/mldsa_sampler_top.vf @@ -0,0 +1,98 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded2.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..31c7164d3f9d2ded233c646e952788e248f71f73 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// mldsa_sampler_pkg.sv +// -------- +// required parameters for sampler top +// +//====================================================================== + +`ifndef MLDSA_SAMPLER_PKG +`define MLDSA_SAMPLER_PKG + +package mldsa_sampler_pkg; + import mldsa_params_pkg::*; + + parameter MLDSA_COEFF_CNT = 256; + +//SHA3 Configuration +// Keccak Rounds per clock + parameter RoundsPerClock = 2; +// Do not enable masking //TODO + parameter Sha3EnMasking = 0; + parameter Sha3Share = (Sha3EnMasking) ? 2 : 1; + +//Sampler Configurations +//Rej Sampler + parameter REJS_NUM_SAMPLERS = 5; + parameter REJS_SAMPLE_W = 24; + parameter REJS_VLD_SAMPLES = COEFF_PER_CLK; + parameter REJS_PISO_BUFFER_W = 1440; + parameter REJS_PISO_INPUT_RATE = 1344; + parameter REJS_PISO_OUTPUT_RATE = 120; + +//Rej Bounded + parameter REJB_NUM_SAMPLERS = 8; + parameter REJB_SAMPLE_W = 4; + parameter REJB_VLD_SAMPLES = COEFF_PER_CLK; + parameter REJB_VLD_SAMPLES_W = 24; + parameter REJB_VALUE = 15; + parameter REJB_VLD_SAMPLE_W = $clog2(REJB_VALUE); + parameter REJB_PISO_BUFFER_W = 1334; + parameter REJB_PISO_INPUT_RATE = 1088; + parameter REJB_PISO_OUTPUT_RATE = 32; + +//Exp Mask + parameter EXP_NUM_SAMPLERS = 4; + parameter EXP_SAMPLE_W = 20; + parameter EXP_VLD_SAMPLES = COEFF_PER_CLK; + parameter EXP_VLD_SAMPLE_W = 24; + parameter EXP_PISO_BUFFER_W = 1152; + parameter EXP_PISO_INPUT_RATE = 1088; + parameter EXP_PISO_OUTPUT_RATE = 80; + +//Sample In Ball + parameter SIB_NUM_SAMPLERS = 4; + parameter SIB_SAMPLE_W = 8; + parameter SIB_TAU = 60; + parameter SIB_PISO_BUFFER_W = 1344; + parameter SIB_PISO_INPUT_RATE = 1088; + parameter SIB_PISO_OUTPUT_RATE = 32; + + //common structures + typedef enum logic [3:0] { + MLDSA_SAMPLER_NONE, + //SHA/SHAKE only modes + MLDSA_SHAKE256, + MLDSA_SHAKE128, + //SAMPLER MODES + MLDSA_REJ_SAMPLER, + MLDSA_EXP_MASK, + MLDSA_REJ_BOUNDED, + MLDSA_SAMPLE_IN_BALL + } mldsa_sampler_mode_e; + +endpackage + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..7c821eb5221ca5b6e4d92f9b8117a4332cf703e4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`include "mldsa_config_defines.svh" + +module mldsa_sampler_top + import mldsa_sampler_pkg::*; + import abr_sha3_pkg::*; + import mldsa_params_pkg::*; + import abr_prim_alert_pkg::*; + #( + //top level params + ) + ( + input logic clk, + input logic rst_b, + input logic zeroize, + + //input + input mldsa_sampler_mode_e sampler_mode_i, + + input logic sha3_start_i, + + input logic msg_start_i, + input logic msg_valid_i, + output logic msg_rdy_o, + input logic [MsgStrbW-1:0] msg_strobe_i, + input logic [MsgWidth-1:0] msg_data_i[Sha3Share], + + input logic sampler_start_i, + + input logic [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr_i, + + //NTT read from sib_mem + input mem_if_t sib_mem_rd_req_i, + output logic [MLDSA_MEM_DATA_WIDTH-1:0] sib_mem_rd_data_o, + + //output + output logic sampler_busy_o, + + output logic sampler_ntt_dv_o, + output logic [COEFF_PER_CLK-1:0][MLDSA_Q_WIDTH-1:0] sampler_ntt_data_o, + + output logic sampler_mem_dv_o, + output logic [COEFF_PER_CLK-1:0][MLDSA_Q_WIDTH-1:0] sampler_mem_data_o, + output logic [MLDSA_MEM_ADDR_WIDTH-1:0] sampler_mem_addr_o, + + output logic sampler_state_dv_o, + output logic [abr_sha3_pkg::StateW-1:0] sampler_state_data_o [Sha3Share] + + ); + +//Signal Declarations + logic sha3_process; + logic sha3_run; + + abr_prim_mubi_pkg::mubi4_t sha3_done; + abr_prim_mubi_pkg::mubi4_t sha3_absorbed; + + logic sha3_squeezing; + + logic sha3_block_processed; + + abr_sha3_pkg::sha3_st_e sha3_fsm; + abr_sha3_pkg::err_t sha3_err; + + abr_sha3_pkg::sha3_mode_e mode; + abr_sha3_pkg::keccak_strength_e strength; + + logic sha3_state_dv; + logic sha3_state_hold; + logic [abr_sha3_pkg::StateW-1:0] sha3_state[Sha3Share]; + + logic sha3_state_error; + logic sha3_count_error; + logic sha3_rst_storage_err; + + //rej sampler + logic rejs_piso_dv; + logic rejs_piso_hold; + logic [REJS_NUM_SAMPLERS-1:0][REJS_SAMPLE_W-1:0] rejs_piso_data; + + logic rejs_dv; + logic [REJS_VLD_SAMPLES-1:0][MLDSA_Q_WIDTH-1:0] rejs_data; + logic [REJS_VLD_SAMPLES-1:0][MLDSA_Q_WIDTH-1:0] rejs_data_q; + + //rej bounded + logic rejb_piso_dv; + logic rejb_piso_hold; + logic [REJB_NUM_SAMPLERS-1:0][REJB_SAMPLE_W-1:0] rejb_piso_data; + + logic rejb_dv; + logic [REJB_VLD_SAMPLES-1:0][MLDSA_Q_WIDTH-1:0] rejb_data; + + //exp mask + logic exp_piso_dv; + logic exp_piso_hold; + logic [EXP_NUM_SAMPLERS-1:0][EXP_SAMPLE_W-1:0] exp_piso_data; + + logic exp_dv; + logic [EXP_VLD_SAMPLES-1:0][EXP_VLD_SAMPLE_W-1:0] exp_data; + + //sample in ball + logic sib_piso_dv; + logic sib_piso_hold; + logic [SIB_NUM_SAMPLERS-1:0][SIB_SAMPLE_W-1:0] sib_piso_data; + + logic sib_done; + + logic [1:0] sib_mem_cs, sib_mem_cs_mux; + logic [1:0] sib_mem_we; + logic [1:0][7:2] sib_mem_addr, sib_mem_addr_mux; + logic [1:0][3:0][MLDSA_Q_WIDTH-2:0] sib_mem_wrdata; + logic [1:0][3:0][MLDSA_Q_WIDTH-2:0] sib_mem_rddata; + + logic [MLDSA_MEM_ADDR_WIDTH-1:0] dest_addr; + logic [$clog2(MLDSA_COEFF_CNT/4):0] coeff_cnt; + logic vld_cycle; + logic sampler_done; + + logic zeroize_sha3, zeroize_rejb, zeroize_rejs, zeroize_sib, zeroize_exp_mask; + logic zeroize_sib_mem; + logic zeroize_piso; + + logic [1:0] piso_mode; + logic piso_dv, piso_hold; + logic [REJS_PISO_OUTPUT_RATE-1:0] piso_data; + + //Sampler mode muxes + always_comb begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L256; + vld_cycle = 0; + sampler_done = 0; + sampler_mem_dv_o = 0; + sampler_mem_data_o = 0; + sampler_mem_addr_o = 0; + sampler_state_dv_o = 0; + sampler_state_data_o[0] = 0; + zeroize_rejb = zeroize; + zeroize_rejs = zeroize; + zeroize_exp_mask = zeroize; + zeroize_sib = zeroize; + zeroize_sib_mem = zeroize; + zeroize_sha3 = zeroize; + zeroize_piso = zeroize; + piso_mode = 0; + + unique case (sampler_mode_i) inside + MLDSA_SHAKE256: begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L256; + sampler_state_dv_o = sha3_state_dv; + sampler_state_data_o[0] = sha3_state[0]; + sampler_done = sha3_state_dv; + zeroize_sha3 |= sha3_state_dv; + end + MLDSA_SHAKE128: begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L128; + sampler_state_dv_o = sha3_state_dv; + sampler_state_data_o [0]= sha3_state[0]; + sampler_done = sha3_state_dv; + zeroize_sha3 |= sha3_state_dv; + end + MLDSA_REJ_SAMPLER: begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L128; + vld_cycle = rejs_dv; + sampler_done = (coeff_cnt == (MLDSA_COEFF_CNT/4)); + zeroize_rejs |= sampler_done; + zeroize_sha3 |= sampler_done; + zeroize_piso |= sampler_done; + piso_mode = 0; + end + MLDSA_EXP_MASK: begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L256; + vld_cycle = exp_dv; + sampler_mem_dv_o = exp_dv; + sampler_mem_data_o = exp_data; + sampler_mem_addr_o = dest_addr; + sampler_done = (coeff_cnt == (MLDSA_COEFF_CNT/4)); + zeroize_exp_mask |= sampler_done; + zeroize_sha3 |= sampler_done; + zeroize_piso |= sampler_done; + piso_mode = 2; + end + MLDSA_REJ_BOUNDED: begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L256; + vld_cycle = rejb_dv; + sampler_mem_dv_o = rejb_dv; + sampler_mem_data_o = rejb_data; + sampler_mem_addr_o = dest_addr; + sampler_done = (coeff_cnt == (MLDSA_COEFF_CNT/4)); + zeroize_rejb |= sampler_done; + zeroize_sha3 |= sampler_done; + zeroize_piso |= sampler_done; + piso_mode = 1; + end + MLDSA_SAMPLE_IN_BALL: begin + mode = abr_sha3_pkg::Shake; + strength = abr_sha3_pkg::L256; + zeroize_sib_mem = sampler_start_i; + sampler_done = sib_done; + zeroize_sib |= sampler_done; + zeroize_sha3 |= sampler_done; + zeroize_piso |= sampler_done; + piso_mode = 3; + end + default: begin + + end + endcase + end + +//FSM Controller +//declare fsm state variables +typedef enum logic [2:0] { + MLDSA_SAMPLER_IDLE = 3'b000, + MLDSA_SAMPLER_PROC = 3'b001, + MLDSA_SAMPLER_WAIT = 3'b010, + MLDSA_SAMPLER_RUN = 3'b011, + MLDSA_SAMPLER_DONE = 3'b100 +} mldsa_sampler_fsm_state_e; + +mldsa_sampler_fsm_state_e sampler_fsm_ps, sampler_fsm_ns; + +//Count coefficients +//Load and increment dest address +always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + coeff_cnt <= 0; + dest_addr <= 0; + end + else if (zeroize | sampler_done) begin + coeff_cnt <= 0; + dest_addr <= 0; + end + else begin + coeff_cnt <= sampler_start_i ? 'd0 : + vld_cycle ? coeff_cnt + 'd1 : coeff_cnt; + dest_addr <= sampler_start_i ? dest_base_addr_i : + vld_cycle ? dest_addr + 'd1 : dest_addr; + end +end + +always_comb sampler_busy_o = sampler_start_i | (sampler_fsm_ps != MLDSA_SAMPLER_IDLE); + +//State logic +always_comb begin : sampler_fsm_out_comb + sampler_fsm_ns = sampler_fsm_ps; + sha3_process = 0; + sha3_run = 0; + sha3_done = abr_prim_mubi_pkg::MuBi4False; + + unique case (sampler_fsm_ps) + MLDSA_SAMPLER_IDLE: begin + //wait for start + if (sampler_start_i) + sampler_fsm_ns = MLDSA_SAMPLER_PROC; + end + MLDSA_SAMPLER_PROC: begin + sampler_fsm_ns = MLDSA_SAMPLER_WAIT; + //drive process signal + sha3_process = 1; + end + MLDSA_SAMPLER_WAIT: begin + if (sampler_done) begin + sampler_fsm_ns = MLDSA_SAMPLER_DONE; + end else if (sha3_state_dv & ~sha3_state_hold) begin + sampler_fsm_ns = MLDSA_SAMPLER_RUN; + end + end + MLDSA_SAMPLER_RUN: begin + if (sampler_done) begin + sampler_fsm_ns = MLDSA_SAMPLER_DONE; + end else begin + sampler_fsm_ns = MLDSA_SAMPLER_WAIT; + //drive run signal + sha3_run = 1; + end + end + MLDSA_SAMPLER_DONE: begin + //drive done + if (sha3_fsm == abr_sha3_pkg::StSqueeze) begin + sha3_done = abr_prim_mubi_pkg::MuBi4True; + end + //Go to IDLE when sha3 resets + if (~sha3_squeezing) begin + sampler_fsm_ns = MLDSA_SAMPLER_IDLE; + end + end + default: begin + end + endcase +end + +//State flop +always_ff @(posedge clk or negedge rst_b) begin : sampler_fsm_flops + if (!rst_b) begin + sampler_fsm_ps <= MLDSA_SAMPLER_IDLE; + end + else if (zeroize) begin + sampler_fsm_ps <= MLDSA_SAMPLER_IDLE; + end + else begin + sampler_fsm_ps <= sampler_fsm_ns; + end +end + +//rej sampler output gets sent to NTT +always_comb sampler_ntt_dv_o = rejs_dv; +always_comb sampler_ntt_data_o = rejs_data; + +//SHA3 instance + abr_sha3 #( + .RoundsPerClock(RoundsPerClock), + .EnMasking (Sha3EnMasking) + ) sha3_inst ( + .clk_i (clk), + .rst_b (rst_b), + .zeroize (zeroize_sha3), + + // MSG_FIFO interface + .msg_start_i (msg_start_i), + .msg_valid_i (msg_valid_i), + .msg_data_i (msg_data_i), + .msg_strb_i (msg_strobe_i), + .msg_ready_o (msg_rdy_o), + + // Entropy interface - not using + .rand_valid_i (1'b0), + .rand_early_i (1'b0), + .rand_data_i ('0), + .rand_aux_i ('0), + .rand_consumed_o (), + + // N, S: Used in cSHAKE mode + .ns_data_i ('0), + + // Configurations + .mode_i (mode), + .strength_i (strength), + + // Controls (CMD register) + .start_i (sha3_start_i), + .process_i (sha3_process), + .run_i (sha3_run), // For squeeze + .done_i (sha3_done), + + .absorbed_o (sha3_absorbed), + .squeezing_o (sha3_squeezing), + + .block_processed_o (sha3_block_processed), + + .sha3_fsm_o (sha3_fsm), + + .state_valid_o (sha3_state_dv), + .state_valid_hold_i (sha3_state_hold), + .state_o (sha3_state), + + .error_o (sha3_err), + .sparse_fsm_error_o (sha3_state_error), + .count_error_o (sha3_count_error), + .keccak_storage_rst_error_o (sha3_rst_storage_err) + ); + +//one piso + abr_piso_4 #( + .PISO_BUFFER_W(REJS_PISO_BUFFER_W), + .PISO_INPUT_RATE0(REJS_PISO_INPUT_RATE), + .PISO_INPUT_RATE1(REJB_PISO_INPUT_RATE), + .PISO_INPUT_RATE2(EXP_PISO_INPUT_RATE), + .PISO_INPUT_RATE3(SIB_PISO_INPUT_RATE), + .PISO_OUTPUT_RATE0(REJS_PISO_OUTPUT_RATE), + .PISO_OUTPUT_RATE1(REJB_PISO_OUTPUT_RATE), + .PISO_OUTPUT_RATE2(EXP_PISO_OUTPUT_RATE), + .PISO_OUTPUT_RATE3(SIB_PISO_OUTPUT_RATE), + .PISO_ACT_INPUT_RATE(REJS_PISO_INPUT_RATE), + .PISO_ACT_OUTPUT_RATE(REJS_PISO_OUTPUT_RATE) + ) abr_piso_inst ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_piso), + .mode(piso_mode), + .valid_i(sha3_state_dv & sampler_mode_i inside {MLDSA_REJ_SAMPLER,MLDSA_REJ_BOUNDED,MLDSA_EXP_MASK,MLDSA_SAMPLE_IN_BALL}), + .hold_o(sha3_state_hold), + .data_i(sha3_state[0][REJS_PISO_INPUT_RATE-1:0]), + .valid_o(piso_dv), + .hold_i(piso_hold), + .data_o(piso_data) + ); + + always_comb rejs_piso_dv = piso_dv & (sampler_mode_i == MLDSA_REJ_SAMPLER); + always_comb rejb_piso_dv = piso_dv & (sampler_mode_i == MLDSA_REJ_BOUNDED); + always_comb exp_piso_dv = piso_dv & (sampler_mode_i == MLDSA_EXP_MASK); + always_comb sib_piso_dv = piso_dv & (sampler_mode_i == MLDSA_SAMPLE_IN_BALL); + + always_comb piso_hold = ((sampler_mode_i == MLDSA_REJ_SAMPLER) & rejs_piso_hold) | + ((sampler_mode_i == MLDSA_REJ_BOUNDED) & rejb_piso_hold) | + ((sampler_mode_i == MLDSA_EXP_MASK) & exp_piso_hold) | + ((sampler_mode_i == MLDSA_SAMPLE_IN_BALL) & sib_piso_hold); + + always_comb rejs_piso_data = piso_data[REJS_PISO_OUTPUT_RATE-1:0]; + always_comb rejb_piso_data = piso_data[REJB_PISO_OUTPUT_RATE-1:0]; + always_comb exp_piso_data = piso_data[EXP_PISO_OUTPUT_RATE-1:0]; + always_comb sib_piso_data = piso_data[SIB_PISO_OUTPUT_RATE-1:0]; + + rej_sampler_ctrl#( + .REJ_NUM_SAMPLERS(REJS_NUM_SAMPLERS), + .REJ_SAMPLE_W(REJS_SAMPLE_W), + .REJ_VLD_SAMPLES(REJS_VLD_SAMPLES), + .REJ_VALUE(MLDSA_Q) + ) rej_sampler_inst ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_rejs), + //input data + .data_valid_i(rejs_piso_dv), + .data_hold_o(rejs_piso_hold), + .data_i(rejs_piso_data), + + //output data + .data_valid_o(rejs_dv), + .data_o(rejs_data_q) + ); + + //FIXME HACK +always_ff @(posedge clk or negedge rst_b) begin : delay_rejs_data + if (!rst_b) begin + rejs_data <= 0; + end + else if (zeroize) begin + rejs_data <= 0; + end + else begin + rejs_data <= rejs_data_q; + end +end + +//rej bounded + rej_bounded_ctrl #( + .REJ_NUM_SAMPLERS(REJB_NUM_SAMPLERS), + .REJ_SAMPLE_W(REJB_SAMPLE_W), + .REJ_VLD_SAMPLES(REJB_VLD_SAMPLES), + .REJ_VALUE(REJB_VALUE) + ) rej_bounded_inst ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_rejb), + //input data + .data_valid_i(rejb_piso_dv), + .data_hold_o(rejb_piso_hold), + .data_i(rejb_piso_data), + + //output data + .data_valid_o(rejb_dv), + .data_o(rejb_data) + ); + +//exp mask + exp_mask_ctrl #( + .EXP_NUM_SAMPLERS(EXP_NUM_SAMPLERS), + .EXP_SAMPLE_W(EXP_SAMPLE_W), + .EXP_VLD_SAMPLES(EXP_VLD_SAMPLES), + .EXP_VLD_SAMPLE_W(EXP_VLD_SAMPLE_W) + ) exp_mask_inst ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_exp_mask), + //input data + .data_valid_i(exp_piso_dv), + .data_hold_o(exp_piso_hold), + .data_i(exp_piso_data), + + //output data + .data_valid_o(exp_dv), + .data_o(exp_data) + ); + +//sample in ball + //Mux read from NTT in here + always_comb sib_mem_addr_mux[0] = (sib_mem_rd_req_i.rd_wr_en == RW_READ) ? sib_mem_rd_req_i.addr[5:0] : sib_mem_addr[0]; + always_comb sib_mem_addr_mux[1] = sib_mem_addr[1]; + always_comb sib_mem_cs_mux[0] = (sib_mem_rd_req_i.rd_wr_en == RW_READ) | sib_mem_cs[0]; + always_comb sib_mem_cs_mux[1] = sib_mem_cs[1]; + + //ugly expansion of 23->24 bits FIXME + assign sib_mem_rd_data_o = {1'b0,sib_mem_rddata[0][3],1'b0,sib_mem_rddata[0][2],1'b0,sib_mem_rddata[0][1],1'b0,sib_mem_rddata[0][0]}; + + sib_mem + #( + .DATA_WIDTH((MLDSA_Q_WIDTH-1)*4), + .DEPTH (MLDSA_N/4), + .NUM_PORTS (2) + ) + sib_mem_inst + ( + .clk_i(clk), + .rst_b(rst_b), + .zeroize(zeroize_sib_mem), + .cs_i(sib_mem_cs_mux), + .we_i(sib_mem_we), + .addr_i(sib_mem_addr_mux), + .wdata_i(sib_mem_wrdata), + + .rdata_o(sib_mem_rddata) + ); + + sample_in_ball_ctrl #( + .SIB_NUM_SAMPLERS(SIB_NUM_SAMPLERS), + .SIB_SAMPLE_W(SIB_SAMPLE_W), + .SIB_TAU(SIB_TAU) + ) sib_inst ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_sib), + //input data + .data_valid_i(sib_piso_dv), + .data_hold_o(sib_piso_hold), + .data_i(sib_piso_data), + .sib_done_o(sib_done), + + //memory_if + .cs_o(sib_mem_cs), + .we_o(sib_mem_we), + .addr_o(sib_mem_addr), + .wrdata_o(sib_mem_wrdata), + .rddata_i(sib_mem_rddata) + ); + + + `ABR_ASSERT_MUTEX(ERR_SAMPLER_O_MUTEX, {sampler_ntt_dv_o,sampler_mem_dv_o,sampler_state_dv_o}, clk, !rst_b) + + `ABR_ASSERT_NEVER(ERR_SIBMEM_ACCESS, (sib_mem_rd_req_i.rd_wr_en == RW_READ) && |sib_mem_cs, clk, !rst_b) + + `ABR_ASSERT_KNOWN(ERR_SAMPLER_FSM_X, sampler_fsm_ps, clk, !rst_b) + `ABR_ASSERT_KNOWN(ERR_SAMPLER_MODE_X, sampler_mode_i, clk, !rst_b) + `ABR_ASSERT_KNOWN(ERR_SAMPLER_NTT_DATA_X, sampler_ntt_data_o, clk, !rst_b, sampler_ntt_dv_o) + `ABR_ASSERT_KNOWN(ERR_SAMPLER_MEM_DATA_X, sampler_mem_data_o, clk, !rst_b, sampler_mem_dv_o) + `ABR_ASSERT_KNOWN(ERR_SAMPLER_STATE_DATA_X, sampler_state_data_o[0], clk, !rst_b, sampler_state_dv_o) + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..9f177ec588617176ba9608af3607a566626d9cc9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/compile.yml @@ -0,0 +1,97 @@ +--- +provides: [mldsa_defines] +schema_version: 2.4.0 +targets: + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_config_defines.svh + - $COMPILE_ROOT/rtl/mldsa_params_pkg.sv + - $COMPILE_ROOT/rtl/mldsa_reg_pkg.sv + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_config_defines.svh + - $COMPILE_ROOT/rtl/mldsa_params_pkg.sv + - $COMPILE_ROOT/rtl/mldsa_reg_pkg.sv +--- +provides: [mldsa_top] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - mldsa_sampler_top + - ntt_top + - decompose + - skencode + - skdecode + - makehint + - norm_check + - sigencode_z + - sigdecode_h + - sigdecode_z + - pkdecode + - power2round +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/mldsa_ctrl_pkg.sv + - $COMPILE_ROOT/rtl/mldsa_mem_if.sv + - $COMPILE_ROOT/rtl/mldsa_mem_top.sv + - $COMPILE_ROOT/rtl/mldsa_seq_prim.sv + - $COMPILE_ROOT/rtl/mldsa_seq_sec.sv + - $COMPILE_ROOT/rtl/mldsa_ctrl.sv + - $COMPILE_ROOT/rtl/mldsa_top.sv + - $COMPILE_ROOT/rtl/mldsa_reg.sv + tops: [mldsa_top] +global: + tool: + vcs: + default: + - '-assert svaext' +--- +provides: [mldsa_top_tb] +schema_version: 2.4.0 +requires: + - mldsa_top + - mldsa_defines + - abr_libs + - mldsa_sampler_top +targets: + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/mldsa_top_tb.sv + tops: [mldsa_top_tb] +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+ABR_ASSERT_ON + - '-noinherit_timescale=1ns/1ps' +--- +provides: [mldsa_coverage] +schema_version: 2.4.0 +requires: + - mldsa_top +targets: + tb: + directories: + - $COMPILE_ROOT/coverage + files: + - $COMPILE_ROOT/coverage/mldsa_top_cov_if.sv + - $COMPILE_ROOT/coverage/mldsa_top_cov_bind.sv +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+CLP_ASSERT_ON + #- '-v2k_generate' + #- '-timescale=1ns/1ps' + - '-noinherit_timescale=1ns/1ps' + #- '-ucli -i dump.ucli' + #sim: + #- '-ucli -i dump.ucli' \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_defines.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_defines.vf new file mode 100644 index 0000000000000000000000000000000000000000..52fd357a448d3fd009cf8a5da99e5ec44759c75f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_defines.vf @@ -0,0 +1,5 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_top.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_top.vf new file mode 100644 index 0000000000000000000000000000000000000000..da10f3671322aa93df7f2272e67e8d291df1334f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_top.vf @@ -0,0 +1,173 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded2.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_r1_lut.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_mem.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_mod_2gamma2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_encode.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_usehint.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_top.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_s1s2_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_t0_unpack.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/hintgen.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl/pkdecode.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_top.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_core.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_skencode.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_ctrl_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_mem_if.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_mem_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_seq_prim.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_seq_sec.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_top_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_top_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..6efb810374d7d0dfedb7f1e65794ebc9dc0bc870 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/config/mldsa_top_tb.vf @@ -0,0 +1,175 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/tb ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/tb/mldsa_top_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded2.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_r1_lut.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_mem.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_mod_2gamma2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_encode.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_usehint.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_top.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_s1s2_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_t0_unpack.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/hintgen.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl/pkdecode.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_top.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_core.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_skencode.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_ctrl_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_mem_if.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_mem_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_seq_prim.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_seq_sec.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/config/mldsa_cm_hier.cfg b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/config/mldsa_cm_hier.cfg new file mode 100644 index 0000000000000000000000000000000000000000..956cf08d435f2fa270cc3bccc8b99873404f8c40 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/config/mldsa_cm_hier.cfg @@ -0,0 +1,4 @@ +begin line+tgl+fsm+cond+branch + +tree mldsa_top_tb.dut 0 +end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/mldsa_top_cov_bind.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/mldsa_top_cov_bind.sv new file mode 100644 index 0000000000000000000000000000000000000000..86a77f98165409065ab7f7e1ffe85d0be9c2d8eb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/mldsa_top_cov_bind.sv @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +module mldsa_top_cov_bind; + `ifdef FCOV + bind mldsa_top mldsa_top_cov_if i_mldsa_top_cov_if(.*); + `endif +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/mldsa_top_cov_if.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/mldsa_top_cov_if.sv new file mode 100644 index 0000000000000000000000000000000000000000..711635177532068f8f1dec2e896561c7048fba08 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/coverage/mldsa_top_cov_if.sv @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef VERILATOR + +interface mldsa_top_cov_if + ( + input logic clk, + input logic rst_b + +); + + logic [2 : 0] mldsa_cmd; + logic [2 : 0] mldsa_sw_cmd; + logic zeroize; + logic pcr_sign_mode; + logic ready; + logic valid; + + logic mldsa_privkey_lock; + + logic error_flag; + logic pcr_sign_input_invalid; + logic skdecode_error; + logic keygen_process; + logic signing_process; + logic verifying_process; + logic keygen_signing_process; + + logic verify_failure; + logic normcheck_failure; + logic [2 : 0] normcheck_mode_failure; + logic makehint_failure; + logic invalid_hint; + + + assign mldsa_cmd = mldsa_top.mldsa_ctrl_inst.cmd_reg; + assign pcr_sign_mode = mldsa_top.mldsa_ctrl_inst.pcr_sign_mode; + assign zeroize = mldsa_top.mldsa_ctrl_inst.zeroize; + assign ready = mldsa_top.mldsa_ctrl_inst.mldsa_ready; + assign valid = mldsa_top.mldsa_ctrl_inst.mldsa_valid_reg; + + always_ff @(posedge clk) begin + if (!rst_b) begin + mldsa_sw_cmd <= '0; + end + else if (mldsa_top.mldsa_reg_inst.decoded_reg_strb.MLDSA_CTRL && mldsa_top.mldsa_reg_inst.decoded_req_is_wr) begin // SW write + mldsa_sw_cmd <= (mldsa_top.mldsa_reg_inst.field_storage.MLDSA_CTRL.CTRL.value & ~mldsa_top.mldsa_reg_inst.decoded_wr_biten[2:0]) | (mldsa_top.mldsa_reg_inst.decoded_wr_data[2:0] & mldsa_top.mldsa_reg_inst.decoded_wr_biten[2:0]); + end + end + + assign mldsa_privkey_lock = mldsa_top.mldsa_ctrl_inst.mldsa_privkey_lock; + + assign error_flag = mldsa_top.mldsa_ctrl_inst.error_flag; + assign pcr_sign_input_invalid = mldsa_top.mldsa_ctrl_inst.pcr_sign_input_invalid; + assign skdecode_error = mldsa_top.mldsa_ctrl_inst.skdecode_error_i; + + assign keygen_process = mldsa_top.mldsa_ctrl_inst.keygen_process; + assign signing_process = mldsa_top.mldsa_ctrl_inst.signing_process; + assign verifying_process = mldsa_top.mldsa_ctrl_inst.verifying_process; + assign keygen_signing_process = mldsa_top.mldsa_ctrl_inst.keygen_signing_process; + + assign verify_failure = mldsa_top.mldsa_ctrl_inst.clear_verify_valid; + assign normcheck_failure = mldsa_top.mldsa_ctrl_inst.normcheck_done_i & mldsa_top.mldsa_ctrl_inst.normcheck_invalid_i; + assign normcheck_mode_failure[0] = normcheck_failure & (mldsa_top.mldsa_ctrl_inst.normcheck_mode_o == 2'b00); + assign normcheck_mode_failure[1] = normcheck_failure & (mldsa_top.mldsa_ctrl_inst.normcheck_mode_o == 2'b01); + assign normcheck_mode_failure[2] = normcheck_failure & (mldsa_top.mldsa_ctrl_inst.normcheck_mode_o == 2'b10); + assign makehint_failure = mldsa_top.mldsa_ctrl_inst.makehint_done_i & mldsa_top.mldsa_ctrl_inst.makehint_invalid_i; + assign invalid_hint = mldsa_top.mldsa_ctrl_inst.sigdecode_h_invalid_i; + + covergroup mldsa_top_cov_grp @(posedge clk); + reset_cp: coverpoint rst_b; + + mldsa_cmd_cp: coverpoint mldsa_cmd; + pcr_sign_cp: coverpoint pcr_sign_mode; + zeroize_cp: coverpoint zeroize; + ready_cp: coverpoint ready; + valid_cp: coverpoint valid; + + mldsa_privkey_lock_cp: coverpoint mldsa_privkey_lock; + + error_flag_cp: coverpoint error_flag; + pcr_sign_input_invalid_cp: coverpoint pcr_sign_input_invalid; + skdecode_error_cp: coverpoint skdecode_error; + verify_failure_cp: coverpoint verify_failure; + normcheck_mode_failure_sign_cp: coverpoint normcheck_mode_failure { + bins mode_0 = {0}; + bins mode_1 = {1}; + bins mode_2 = {2}; + } + normcheck_mode_failure_verify_cp: coverpoint normcheck_mode_failure { + bins mode_0 = {0}; + } + makehint_failure_cp: coverpoint makehint_failure; + invalid_hint_cp: coverpoint invalid_hint; + + cmd_ready_cp: cross mldsa_sw_cmd, ready; + cmd_kv_cp: cross mldsa_cmd, mldsa_privkey_lock; + pcr_ready_cp: cross ready, pcr_sign_mode; + pcr_cmd_cp: cross pcr_sign_mode, mldsa_cmd; + zeroize_pcr_cp: cross zeroize, pcr_sign_mode; + zeroize_cmd_cp: cross zeroize, mldsa_cmd; + zeroize_error_cp: cross zeroize, error_flag; + zeroize_ready_cp: cross ready, zeroize; + pcr_sign_input_invalid_cmd_cp: cross error_flag, mldsa_cmd; + error_keygen_cp: cross error_flag, keygen_process; + error_signing_cp: cross error_flag, signing_process; + error_verifying_cp: cross error_flag, verifying_process; + error_keygen_signing_cp: cross error_flag, keygen_signing_process; + + normcheck_signing_failure_cp: cross normcheck_mode_failure_sign_cp, signing_process; + normcheck_verifying_failure_cp: cross normcheck_mode_failure_verify_cp, verifying_process; + normcheck_pcr_failure_cp: cross normcheck_mode_failure_sign_cp, pcr_sign_mode; + makehint_pcr_failure_cp: cross makehint_failure, pcr_sign_mode; + + endgroup + + mldsa_top_cov_grp mldsa_top_cov_grp1 = new(); + +endinterface + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/kv_def.rdl b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/kv_def.rdl new file mode 100644 index 0000000000000000000000000000000000000000..b12a85bd59a693d22f563a8a408260446b5881ae --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/kv_def.rdl @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + reg kv_status_reg { + name = "Key Vault Status Register"; + desc = "Reports the Key Vault flow status for this engine"; + + field {desc = "Key Vault control is ready for use"; sw=r; hw=w;} READY = 1'b0; + field {desc = "Key Vault flow is done"; sw=r; hw=na; hwset; hwclr;} VALID = 1'b0; + field { + name = "Key Vault Error"; + desc = "Indicates the error status of a key vault flow"; + + enum kv_error_e { + SUCCESS = 8'h00 { + desc = "Key Vault flow was successful"; + }; + KV_READ_FAIL = 8'h01 { + desc = "Key Vault Read flow failed"; + }; + KV_WRITE_FAIL = 8'h02 { + desc = "Key Vault Write flow failed"; + }; + }; + sw=r; hw=w; encode = kv_error_e;} ERROR[8]=0; + }; + + reg kv_read_ctrl_reg #(longint unsigned KV_ENTRY_ADDRESS_W = 5) { + name = "Key Vault Read Control Register"; + desc = "Controls the Key Vault read access for this engine"; + + default sw = rw; + default hw = r; + + field {desc = "Indicates that the read data is to come from the key vault. + Setting this bit to 1 initiates copying of data from the key vault."; hwclr;} read_en = 0; + field {desc = "Key Vault entry to retrieve the read data from for the engine";} read_entry[KV_ENTRY_ADDRESS_W] = 0; + field {desc = "Requested entry is a PCR. This is used only for SHA to hash extend, it's NOP in all other engines";} pcr_hash_extend = 0; + field {desc = "Reserved field";} rsvd[25] = 0; + + }; + + reg kv_write_ctrl_reg #(longint unsigned KV_ENTRY_ADDRESS_W = 5) { + name = "Key Vault Write Control Register"; + desc = "Controls the Key Vault write access for this engine"; + + default sw = rw; + default hw = r; + + field {desc = "Indicates that the result is to be stored in the key vault. + Setting this bit to 1 will copy the result to the keyvault when it is ready."; hwclr;} write_en = 0; + field {desc = "Key Vault entry to store the result";} write_entry[KV_ENTRY_ADDRESS_W] = 0; + field {desc = "HMAC KEY is a valid destination";} hmac_key_dest_valid = 0; + field {desc = "HMAC BLOCK is a valid destination";} hmac_block_dest_valid = 0; + field {desc = "MLDSA SEED";} mldsa_seed_dest_valid = 0; + field {desc = "ECC PKEY is a valid destination";} ecc_pkey_dest_valid = 0; + field {desc = "ECC SEED is a valid destination";} ecc_seed_dest_valid = 0; + field {desc = "Reserved field";} rsvd[21] = 0; + + }; diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_config_defines.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_config_defines.svh new file mode 100644 index 0000000000000000000000000000000000000000..37552c530485d6165465c4f6faca534dbe8e45ad --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_config_defines.svh @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +`ifndef ABR_CFG_SV +`define ABR_CFG_SV + + `include "abr_sva.svh" + // `define RV_FPGA_OPTIMIZE + // `define RV_FPGA_SCA + `define MLDSA_MASKING + + `define ABR_ICG abr_clk_gate + + `define ABR_MEM(_depth, _width, _mem_name) \ + abr_1r1w_ram \ + #( .DEPTH(``_depth``), \ + .DATA_WIDTH(``_width``)) \ + mldsa_``_mem_name``_inst\ + (\ + .clk_i(clk_i),\ + .we_i(mldsa_memory_export.``_mem_name``_we_i),\ + .waddr_i(mldsa_memory_export.``_mem_name``_waddr_i),\ + .wdata_i(mldsa_memory_export.``_mem_name``_wdata_i),\ + .re_i(mldsa_memory_export.``_mem_name``_re_i),\ + .raddr_i(mldsa_memory_export.``_mem_name``_raddr_i),\ + .rdata_o(mldsa_memory_export.``_mem_name``_rdata_o)\ + ); + + `define ABR_MEM_BE(_depth, _width, _mem_name) \ + abr_1r1w_be_ram \ + #( .DEPTH(``_depth``), \ + .DATA_WIDTH(``_width``)) \ + mldsa_``_mem_name``_inst\ + (\ + .clk_i(clk_i),\ + .we_i(mldsa_memory_export.``_mem_name``_we_i),\ + .waddr_i(mldsa_memory_export.``_mem_name``_waddr_i),\ + .wdata_i(mldsa_memory_export.``_mem_name``_wdata_i),\ + .wstrobe_i(mldsa_memory_export.``_mem_name``_wstrobe_i),\ + .re_i(mldsa_memory_export.``_mem_name``_re_i),\ + .raddr_i(mldsa_memory_export.``_mem_name``_raddr_i),\ + .rdata_o(mldsa_memory_export.``_mem_name``_rdata_o)\ + ); + + + `define MLDSA_CUSTOM_INF // KV interface\ + output kv_read_t kv_read,\ + input kv_rd_resp_t kv_rd_resp,\ + //PCR Signing\ + input pcr_signing_t pcr_signing_data, +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..5b925c354e9bca1bf769ac71c37541e6ca0bbb08 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_ctrl.sv @@ -0,0 +1,1823 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//High level controller block for executing +//Adams Bridge functions +// Keygen +// Signing + +`include "mldsa_config_defines.svh" + +module mldsa_ctrl + import mldsa_reg_pkg::*; + import abr_sha3_pkg::*; + import mldsa_sampler_pkg::*; + import mldsa_ctrl_pkg::*; + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; + `ifdef CALIPTRA + import kv_defines_pkg::*; + `endif + #( + ) + ( + input logic clk, + input logic rst_b, + output logic zeroize, + +`ifdef RV_FPGA_SCA + output logic NTT_trigger, + output logic PWM_trigger, + output logic PWA_trigger, + output logic INTT_trigger, +`endif + + output mldsa_reg__in_t mldsa_reg_hwif_in_o, + input mldsa_reg__out_t mldsa_reg_hwif_out_i, + + //sampler interface + output mldsa_sampler_mode_e sampler_mode_o, + output logic sha3_start_o, + output logic msg_start_o, + output logic msg_valid_o, + input logic msg_rdy_i, + output logic [MsgStrbW-1:0] msg_strobe_o, + output logic [MsgWidth-1:0] msg_data_o[Sha3Share], + output logic sampler_start_o, + + input logic sampler_busy_i, + input logic sampler_state_dv_i, + input logic [abr_sha3_pkg::StateW-1:0] sampler_state_data_i [Sha3Share], + + output logic [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr_o, + + //ntt interfaces + output logic [1:0] ntt_enable_o, + output mldsa_ntt_mode_e [1:0] ntt_mode_o, + output ntt_mem_addr_t [1:0] ntt_mem_base_addr_o, + output pwo_mem_addr_t [1:0] pwo_mem_base_addr_o, + output logic [1:0] ntt_masking_en_o, + output logic [1:0] ntt_shuffling_en_o, + input logic [1:0] ntt_busy_i, + + //aux interfaces + output logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] aux_src0_base_addr_o, + output logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] aux_src1_base_addr_o, + output logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] aux_dest_base_addr_o, + + output logic power2round_enable_o, + input mem_if_t [1:0] pwr2rnd_keymem_if_i, + input logic [1:0] [DATA_WIDTH-1:0] pwr2rnd_wr_data_i, + input logic pk_t1_wren_i, + input logic [7:0][9:0] pk_t1_wrdata_i, // TODO: change to parameter + input logic [7:0] pk_t1_wr_addr_i, // TODO: change to parameter + input logic power2round_done_i, + + output logic decompose_enable_o, + output logic decompose_mode_o, + input logic decompose_done_i, + + output logic skencode_enable_o, + input mem_if_t skencode_keymem_if_i, + input logic [DATA_WIDTH-1:0] skencode_wr_data_i, + input logic skencode_done_i, + + output logic skdecode_enable_o, + input mem_if_t [1:0] skdecode_keymem_if_i, + output logic [1:0][DATA_WIDTH-1:0] skdecode_rd_data_o, + input logic skdecode_done_i, + input logic skdecode_error_i, + + output logic makehint_enable_o, + input logic makehint_invalid_i, + input logic makehint_done_i, + input logic makehint_reg_wren_i, + input logic [3:0][7:0] makehint_reg_wrdata_i, + input logic [MLDSA_MEM_ADDR_WIDTH-1:0] makehint_reg_wr_addr_i, + + output logic normcheck_enable_o, + output logic [1:0] normcheck_mode_o, + output logic [MLDSA_MEM_ADDR_WIDTH-1:0] normcheck_src_addr_o, + input logic normcheck_invalid_i, + input logic normcheck_done_i, + + output logic sigencode_enable_o, + input mem_if_t sigencode_wr_req_i, + input logic [1:0][3:0][19:0] sigencode_wr_data_i, + input logic sigencode_done_i, + + output logic pkdecode_enable_o, + input logic [7:0] pkdecode_rd_addr_i, + output logic [7:0][T1_COEFF_W-1:0] pkdecode_rd_data_o, + input logic pkdecode_done_i, + + + output logic sigdecode_h_enable_o, + output logic [SIGNATURE_H_VALID_NUM_BYTES-1:0][7:0] signature_h_o, + input logic sigdecode_h_invalid_i, + input logic sigdecode_h_done_i, + + output logic sigdecode_z_enable_o, + input mem_if_t sigdecode_z_rd_req_i, + output logic [1:0][3:0][19:0] sigdecode_z_rd_data_o, + input logic sigdecode_z_done_i, + + output logic lfsr_enable_o, + output logic [1:0][LFSR_W-1:0] lfsr_seed_o, + + //Memory interface export + mldsa_sram_if.req sk_bank0_mem_if, + mldsa_sram_if.req sk_bank1_mem_if, + mldsa_sram_be_if.req sig_z_mem_if, + mldsa_sram_be_if.req pk_mem_if, + + output mem_if_t zeroize_mem_o, + + `ifdef CALIPTRA + // KV interface + output kv_read_t kv_read, + input kv_rd_resp_t kv_rd_resp, + //PCR Signing + input pcr_signing_t pcr_signing_data, + `endif + + input logic debugUnlock_or_scan_mode_switch, + output logic busy_o, + + //Interrupts + output logic error_intr, + output logic notif_intr + + ); + + mldsa_reg__in_t mldsa_reg_hwif_in; + mldsa_reg__out_t mldsa_reg_hwif_out; + logic mldsa_ready; + logic mldsa_valid_reg; + logic mldsa_privkey_lock; + + logic external_mu; + logic external_mu_mode, external_mu_mode_nxt; + + `ifdef CALIPTRA +//Custom keyvault logic for Caliptra + + logic kv_seed_write_en; + logic [$clog2(SEED_NUM_DWORDS)-1:0] kv_seed_write_offset; + logic [DATA_WIDTH-1:0] kv_seed_write_data; + kv_read_ctrl_reg_t kv_seed_read_ctrl_reg; + kv_error_code_e kv_seed_error; + logic kv_seed_ready, kv_seed_done; + //KV Seed Data Present + logic kv_seed_data_present; + logic kv_seed_data_present_set, kv_seed_data_present_reset; + logic pcr_sign_mode; + logic pcr_sign_input_invalid; + + always_comb begin: mldsa_kv_ctrl_reg + //ready when fsm is not busy + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.ERROR.next = kv_seed_error; + //ready when fsm is not busy + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.READY.next = kv_seed_ready; + //set valid when fsm is done + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.VALID.hwset = kv_seed_done; + //clear valid when new request is made + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.VALID.hwclr = kv_seed_read_ctrl_reg.read_en; + //clear enable when busy + mldsa_reg_hwif_in.mldsa_kv_rd_seed_ctrl.read_en.hwclr = ~kv_seed_ready; + end + + `CALIPTRA_KV_READ_CTRL_REG2STRUCT(kv_seed_read_ctrl_reg, mldsa_kv_rd_seed_ctrl, mldsa_reg_hwif_out) + + //Detect keyvault data coming in to lock api registers and protect outputs + always_comb kv_seed_data_present_set = kv_seed_read_ctrl_reg.read_en | pcr_sign_mode; + always_comb kv_seed_data_present_reset = kv_seed_data_present & mldsa_valid_reg; + + //Read SEED + kv_read_client #( + .DATA_WIDTH(SEED_NUM_DWORDS*32), + .PAD(0) + ) + mldsa_seed_kv_read + ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize), + + //client control register + .read_ctrl_reg(kv_seed_read_ctrl_reg), + + //interface with kv + .kv_read(kv_read), + .kv_resp(kv_rd_resp), + + //interface with client + .write_en(kv_seed_write_en), + .write_offset(kv_seed_write_offset), + .write_data(kv_seed_write_data), + + .error_code(kv_seed_error), + .kv_ready(kv_seed_ready), + .read_done(kv_seed_done) +); + +always_ff @(posedge clk or negedge rst_b) begin : mldsa_kv_reg + if (!rst_b) + kv_seed_data_present <= '0; + else if (zeroize) + kv_seed_data_present <= '0; + else begin + kv_seed_data_present <= kv_seed_data_present_set ? '1 : + kv_seed_data_present_reset ? '0 : kv_seed_data_present; + end +end + +always_comb pcr_sign_mode = mldsa_reg_hwif_out.MLDSA_CTRL.PCR_SIGN.value; + +always_ff @(posedge clk or negedge rst_b) begin : mldsa_privkey_lock_reg + if (!rst_b) + mldsa_privkey_lock <= '0; + else if (zeroize) + mldsa_privkey_lock <= '0; + else if (kv_seed_data_present_set) + mldsa_privkey_lock <= '1; +end + +`else +always_comb begin: mldsa_kv_ctrl_reg + //ready when fsm is not busy + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.ERROR.next = '0; + //ready when fsm is not busy + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.READY.next = '0; + //set valid when fsm is done + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.VALID.hwset = '0; + //clear valid when new request is made + mldsa_reg_hwif_in.mldsa_kv_rd_seed_status.VALID.hwclr = '0; + //clear enable when busy + mldsa_reg_hwif_in.mldsa_kv_rd_seed_ctrl.read_en.hwclr = '0; +end + +always_comb mldsa_privkey_lock = '0; +`endif + + logic [2:0] cmd_reg; + + logic keygen_process, keygen_process_nxt; + logic signing_process, signing_process_nxt; + logic verifying_process, verifying_process_nxt; + logic keygen_signing_process, keygen_signing_process_nxt; + logic keygen_done; + logic signature_done; + logic verify_done; + logic signature_validity_chk_done; + logic process_done; + + //assign appropriate data to msg interface + logic [MLDSA_OPR_WIDTH-1:0] sampler_src; + logic [15:0] sampler_src_offset; + logic [2:0] sampler_src_offset_f; + logic [15:0] sampler_imm; + + logic [ENTROPY_NUM_DWORDS-1 : 0][DATA_WIDTH-1:0] entropy_reg; + logic [SEED_NUM_DWORDS-1 : 0][DATA_WIDTH-1:0] seed_reg; + logic [MSG_NUM_DWORDS-1 : 0][DATA_WIDTH-1:0] msg_reg; + logic internal_mu_we; + logic [MU_NUM_DWORDS-1 : 0][DATA_WIDTH-1:0] internal_mu_reg; + logic [MU_NUM_DWORDS-1 : 0][DATA_WIDTH-1:0] external_mu_reg; + logic [SIGN_RND_NUM_DWORDS-1 : 0][DATA_WIDTH-1:0] sign_rnd_reg; + logic [7:0][63:0] rho_p_reg; + logic [3:0][63:0] rho_reg; + logic [7:0][63:0] mu_reg; + logic [15:0] kappa_reg; + logic update_kappa; + + logic [MsgWidth-1:0] msg_data, msg_data_nxt; + + logic prim_seq_en; + logic sec_seq_en; + logic [MLDSA_PROG_ADDR_W-1 : 0] prim_prog_cntr, prim_prog_cntr_nxt; + mldsa_seq_instr_t prim_instr_o, prim_instr; + logic [MLDSA_PROG_ADDR_W-1 : 0] sec_prog_cntr, sec_prog_cntr_nxt; + mldsa_seq_instr_t sec_instr_o, sec_instr; + + logic msg_done; + logic [MsgStrbW-1:0] last_msg_strobe; + logic [MLDSA_OPR_WIDTH-1:$clog2(MsgStrbW)] msg_cnt; + logic msg_hold; + + logic error_flag; + logic error_flag_reg; + logic error_flag_edge; + logic subcomponent_busy; + logic sign_subcomponent_busy; + + mldsa_ctrl_fsm_state_e ctrl_fsm_ps, ctrl_fsm_ns; + logic msg_valid; + mldsa_ctrl_fsm_state_e sign_ctrl_fsm_ps, sign_ctrl_fsm_ns; + + mldsa_privkey_u privatekey_reg; + mldsa_signature_u signature_reg; + mldsa_pubkey_u publickey_reg; + + //sync points for dual sequencers + logic y_valid, set_y_valid, clear_y_valid; + logic w0_valid, set_w0_valid, clear_w0_valid; + logic c_valid, set_c_valid, clear_c_valid; + + //signature and verify validity checks + logic signature_valid, set_signature_valid, clear_signature_valid; + logic verify_valid, set_verify_valid, clear_verify_valid; + + //shared aux functions + logic [1:0] normcheck_enable; + + logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] ntt_temp_address; + + //Interrupts + logic mldsa_status_done_d, mldsa_status_done_p; + + logic set_entropy; + logic [7:0][63:0] lfsr_entropy_reg; + logic [MsgWidth-1:0] counter_reg; + + logic zeroize_mem_we; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] zeroize_mem_addr; + logic zeroize_mem_done; + + assign mldsa_reg_hwif_in_o = mldsa_reg_hwif_in; + assign mldsa_reg_hwif_out = mldsa_reg_hwif_out_i; + + always_comb mldsa_ready = (prim_prog_cntr == MLDSA_RESET); + + //without zeroize to make it more complex + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) + counter_reg <= '0; + else + counter_reg <= counter_reg + 1; + end + + //Set busy when engine is in progress + always_comb busy_o = ~mldsa_ready; + +//HWIF to reg block + always_comb mldsa_reg_hwif_in.reset_b = rst_b; + always_comb mldsa_reg_hwif_in.hard_reset_b = rst_b; //FIXME interface needs a hard reset signal? + always_comb mldsa_reg_hwif_in.mldsa_ready = mldsa_ready; + always_comb cmd_reg = mldsa_reg_hwif_out.MLDSA_CTRL.CTRL.value; + always_comb mldsa_reg_hwif_in.MLDSA_CTRL.CTRL.hwclr = |cmd_reg; + `ifdef CALIPTRA + always_comb mldsa_reg_hwif_in.MLDSA_CTRL.PCR_SIGN.hwclr = mldsa_reg_hwif_out.MLDSA_CTRL.PCR_SIGN.value; + `else + always_comb mldsa_reg_hwif_in.MLDSA_CTRL.PCR_SIGN.hwclr = '0; + `endif + + always_comb mldsa_reg_hwif_in.MLDSA_NAME[0].NAME.next = '0; + always_comb mldsa_reg_hwif_in.MLDSA_NAME[1].NAME.next = '0; + always_comb mldsa_reg_hwif_in.MLDSA_VERSION[0].VERSION.next = '0; + always_comb mldsa_reg_hwif_in.MLDSA_VERSION[1].VERSION.next = '0; + + always_comb mldsa_reg_hwif_in.MLDSA_STATUS.READY.next = mldsa_ready; + always_comb mldsa_reg_hwif_in.MLDSA_STATUS.VALID.next = mldsa_valid_reg; + + always_comb zeroize = mldsa_reg_hwif_out.MLDSA_CTRL.ZEROIZE.value || debugUnlock_or_scan_mode_switch; + + always_comb external_mu = 0; //mldsa_reg_hwif_out.MLDSA_CTRL.EXTERNAL_MU.value; //TODO: enable after ExternalMu validation + always_comb mldsa_reg_hwif_in.MLDSA_CTRL.EXTERNAL_MU.hwclr = mldsa_reg_hwif_out.MLDSA_CTRL.EXTERNAL_MU.value; + + always_comb begin // mldsa reg writing + + for (int dword=0; dword < ENTROPY_NUM_DWORDS; dword++)begin + entropy_reg[dword] = mldsa_reg_hwif_out.MLDSA_ENTROPY[ENTROPY_NUM_DWORDS-1-dword].ENTROPY.value; + mldsa_reg_hwif_in.MLDSA_ENTROPY[dword].ENTROPY.hwclr = zeroize; + end + + for (int dword=0; dword < SEED_NUM_DWORDS; dword++)begin + seed_reg[dword] = mldsa_reg_hwif_out.MLDSA_SEED[SEED_NUM_DWORDS-1-dword].SEED.value; + + `ifdef CALIPTRA + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.we = (pcr_sign_mode | (kv_seed_write_en & (kv_seed_write_offset == dword))) & ~zeroize; + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.next = pcr_sign_mode ? pcr_signing_data.pcr_mldsa_signing_seed[dword] : + kv_seed_write_data; + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.hwclr = zeroize | kv_seed_data_present_reset | (kv_seed_error == KV_READ_FAIL); + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.swwe = mldsa_ready & ~kv_seed_data_present; + `else + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.we = '0; + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.next = '0; + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.hwclr = zeroize; + mldsa_reg_hwif_in.MLDSA_SEED[dword].SEED.swwe = mldsa_ready; + `endif + end + + for (int dword=0; dword < MSG_NUM_DWORDS; dword++)begin + msg_reg[dword] = external_mu_mode? '0 : mldsa_reg_hwif_out.MLDSA_MSG[MSG_NUM_DWORDS-1-dword].MSG.value; + `ifdef CALIPTRA + mldsa_reg_hwif_in.MLDSA_MSG[dword].MSG.we = pcr_sign_mode & !external_mu & !zeroize; + mldsa_reg_hwif_in.MLDSA_MSG[dword].MSG.next = pcr_signing_data.pcr_hash[dword]; + mldsa_reg_hwif_in.MLDSA_MSG[dword].MSG.hwclr = zeroize; + `else + mldsa_reg_hwif_in.MLDSA_MSG[dword].MSG.we = '0; + mldsa_reg_hwif_in.MLDSA_MSG[dword].MSG.next = '0; + mldsa_reg_hwif_in.MLDSA_MSG[dword].MSG.hwclr = zeroize; + `endif + end + + for (int dword=0; dword < MU_NUM_DWORDS; dword++)begin + external_mu_reg[dword] = mldsa_reg_hwif_out.MLDSA_EXTERNAL_MU[MU_NUM_DWORDS-1-dword].EXTERNAL_MU.value; + mldsa_reg_hwif_in.MLDSA_EXTERNAL_MU[dword].EXTERNAL_MU.we = internal_mu_we & !external_mu & !zeroize; + mldsa_reg_hwif_in.MLDSA_EXTERNAL_MU[dword].EXTERNAL_MU.next = internal_mu_reg[MU_NUM_DWORDS-1-dword]; + mldsa_reg_hwif_in.MLDSA_EXTERNAL_MU[dword].EXTERNAL_MU.hwclr = zeroize; + end + + for (int dword=0; dword < SIGN_RND_NUM_DWORDS; dword++)begin + sign_rnd_reg[dword] = mldsa_reg_hwif_out.MLDSA_SIGN_RND[SIGN_RND_NUM_DWORDS-1-dword].SIGN_RND.value; + mldsa_reg_hwif_in.MLDSA_SIGN_RND[dword].SIGN_RND.hwclr = zeroize; + end + + for (int dword=0; dword < VERIFY_RES_NUM_DWORDS; dword++)begin + mldsa_reg_hwif_in.MLDSA_VERIFY_RES[dword].VERIFY_RES.we = verify_valid & sampler_state_dv_i & (prim_instr.operand3 == MLDSA_DEST_VERIFY_RES_REG_ID); + mldsa_reg_hwif_in.MLDSA_VERIFY_RES[VERIFY_RES_NUM_DWORDS-1-dword].VERIFY_RES.next = sampler_state_data_i[0][dword*32 +: 32]; + mldsa_reg_hwif_in.MLDSA_VERIFY_RES[dword].VERIFY_RES.hwclr = zeroize | clear_verify_valid; + end + + for (int dword=0; dword < ENTROPY_NUM_DWORDS; dword++)begin + mldsa_reg_hwif_in.MLDSA_ENTROPY[dword].ENTROPY.hwclr = zeroize; + end + end + + //Generate a pulse to trig the interrupt after finishing the operation + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) + mldsa_status_done_d <= 1'b0; + else if (zeroize) + mldsa_status_done_d <= 1'b0; + else + mldsa_status_done_d <= mldsa_reg_hwif_in.MLDSA_STATUS.VALID.next; + end + + always_comb mldsa_status_done_p = mldsa_reg_hwif_in.MLDSA_STATUS.VALID.next & !mldsa_status_done_d; + + assign error_intr = mldsa_reg_hwif_out.intr_block_rf.error_global_intr_r.intr; + assign notif_intr = mldsa_reg_hwif_out.intr_block_rf.notif_global_intr_r.intr; + + always_comb begin + mldsa_reg_hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset = error_flag_edge; //TODO + mldsa_reg_hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset = mldsa_status_done_p; + end + + //Private Key External Memory + + //Request muxing + logic [1:0] sk_ram_we_bank, sk_ram_re_bank; + logic [1:0][SK_MEM_BANK_ADDR_W-1:0] sk_ram_waddr_bank, sk_ram_raddr_bank; + logic [1:0][DATA_WIDTH-1:0] sk_ram_wdata, sk_ram_rdata; + + logic [1:0] skencode_keymem_we_bank, pwr2rnd_keymem_we_bank, api_keymem_we_bank; + logic [SK_MEM_BANK_ADDR_W:0] api_sk_waddr, api_sk_raddr; + logic [SK_MEM_BANK_ADDR_W:0] api_sk_mem_waddr, api_sk_mem_raddr; + logic [4:0] api_sk_reg_waddr, api_sk_reg_raddr; + + logic [1:0] api_keymem_re_bank, api_keymem_re_bank_f; + logic [1:0] skdecode_re_bank; + logic [1:0][SK_MEM_BANK_ADDR_W:0] skdecode_rdaddr; + + logic api_keymem_wr_dec, api_sk_reg_wr_dec; + logic api_keymem_rd_dec, api_sk_reg_rd_dec, api_sk_reg_rd_dec_f; + logic [DATA_WIDTH-1:0] privkey_reg_rdata; + logic [DATA_WIDTH-1:0] privkey_out_rdata; + + always_comb api_sk_waddr = PRIVKEY_NUM_DWORDS-1-mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.addr[12:2]; + always_comb api_sk_raddr = PRIVKEY_NUM_DWORDS-1-mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.addr[12:2]; + + always_comb api_sk_reg_wr_dec = mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.req & api_sk_waddr inside {[0:31]}; + always_comb api_keymem_wr_dec = mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.req & api_sk_waddr inside {[31:PRIVKEY_NUM_DWORDS-1]}; + + always_comb api_sk_reg_rd_dec = mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & api_sk_raddr inside {[0:31]}; + always_comb api_keymem_rd_dec = mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & api_sk_raddr inside {[32:PRIVKEY_NUM_DWORDS-1]}; + + assign api_sk_reg_waddr = api_sk_waddr[4:0]; + assign api_sk_reg_raddr = api_sk_raddr[4:0]; + + assign api_sk_mem_waddr = api_sk_waddr - 'd32; + assign api_sk_mem_raddr = api_sk_raddr - 'd32; + + always_comb begin + for (int i = 0; i < 2; i++) begin + skencode_keymem_we_bank[i] = ((skencode_keymem_if_i.rd_wr_en == RW_WRITE) & (skencode_keymem_if_i.addr[0] == i)); + pwr2rnd_keymem_we_bank[i] = (pwr2rnd_keymem_if_i[i].rd_wr_en == RW_WRITE); + api_keymem_we_bank[i] = mldsa_reg_hwif_in.MLDSA_PRIVKEY_IN.wr_ack & mldsa_ready & api_keymem_wr_dec & (api_sk_mem_waddr[0] == i); + + sk_ram_we_bank[i] = skencode_keymem_we_bank[i] | pwr2rnd_keymem_we_bank[i] | api_keymem_we_bank[i] | zeroize_mem_we; + + sk_ram_waddr_bank[i] = ({SK_MEM_BANK_ADDR_W{skencode_keymem_we_bank[i]}} & skencode_keymem_if_i.addr[SK_MEM_BANK_ADDR_W:1]) | + ({SK_MEM_BANK_ADDR_W{pwr2rnd_keymem_we_bank[i]}} & pwr2rnd_keymem_if_i[i].addr[SK_MEM_BANK_ADDR_W:1] ) | + ({SK_MEM_BANK_ADDR_W{api_keymem_we_bank[i]}} & api_sk_mem_waddr[SK_MEM_BANK_ADDR_W:1]) | + ({SK_MEM_BANK_ADDR_W{zeroize_mem_we}} & zeroize_mem_addr[SK_MEM_BANK_ADDR_W-1:0]); + + sk_ram_wdata[i] = ({DATA_WIDTH{skencode_keymem_we_bank[i]}} & skencode_wr_data_i) | + ({DATA_WIDTH{pwr2rnd_keymem_we_bank[i]}} & pwr2rnd_wr_data_i[i]) | + ({DATA_WIDTH{api_keymem_we_bank[i]}} & mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.wr_data); + end + end + + always_comb begin + for (int i = 0; i < 2; i++) begin + api_keymem_re_bank[i] = mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & ~mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr & + mldsa_valid_reg & keygen_process & + api_keymem_rd_dec & (api_sk_mem_raddr[0] == i); + + skdecode_re_bank[i] = (skdecode_keymem_if_i[i].rd_wr_en == RW_READ); + + skdecode_rdaddr[i] = skdecode_keymem_if_i[i].addr[SK_MEM_BANK_ADDR_W:0]; + + sk_ram_re_bank[i] = skdecode_re_bank[i] | api_keymem_re_bank[i]; + + sk_ram_raddr_bank[i] = ({SK_MEM_BANK_ADDR_W{skdecode_re_bank[i]}} & skdecode_rdaddr[i][SK_MEM_BANK_ADDR_W:1]) | + ({SK_MEM_BANK_ADDR_W{api_keymem_re_bank[i]}} & api_sk_mem_raddr[SK_MEM_BANK_ADDR_W:1]); + + end + end + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + api_keymem_re_bank_f <= '0; + api_sk_reg_rd_dec_f <= '0; + end else begin + api_keymem_re_bank_f <= api_keymem_re_bank; + api_sk_reg_rd_dec_f <= api_sk_reg_rd_dec; + end + end + + always_comb skdecode_rd_data_o = sk_ram_rdata; + always_comb privkey_out_rdata = {DATA_WIDTH{api_keymem_re_bank_f[0]}} & sk_ram_rdata[0] | + {DATA_WIDTH{api_keymem_re_bank_f[1]}} & sk_ram_rdata[1] | + {DATA_WIDTH{api_sk_reg_rd_dec_f}} & privkey_reg_rdata; + + always_comb sk_bank0_mem_if.we_i = (sk_ram_we_bank[0]); + always_comb sk_bank0_mem_if.waddr_i = (sk_ram_waddr_bank[0]); + always_comb sk_bank0_mem_if.wdata_i = (sk_ram_wdata[0]); + always_comb sk_bank0_mem_if.re_i = (sk_ram_re_bank[0]); + always_comb sk_bank0_mem_if.raddr_i = (sk_ram_raddr_bank[0]); + always_comb sk_ram_rdata[0] = sk_bank0_mem_if.rdata_o; + + always_comb sk_bank1_mem_if.we_i = (sk_ram_we_bank[1]); + always_comb sk_bank1_mem_if.waddr_i = (sk_ram_waddr_bank[1]); + always_comb sk_bank1_mem_if.wdata_i = (sk_ram_wdata[1]); + always_comb sk_bank1_mem_if.re_i = (sk_ram_re_bank[1]); + always_comb sk_bank1_mem_if.raddr_i = (sk_ram_raddr_bank[1]); + always_comb sk_ram_rdata[1] = sk_bank1_mem_if.rdata_o; + + //Private Key External Memory + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + privatekey_reg <= '0; + end else if (zeroize) begin + privatekey_reg <= '0; + end else begin + if (sampler_state_dv_i) begin + if (prim_instr.operand3 == MLDSA_DEST_K_RHO_REG_ID) begin + //HW write rho + privatekey_reg.enc.rho <= sampler_state_data_i[0][255:0]; //FIXME optimize this to be shared with pubkey? + //HW write K + privatekey_reg.enc.K <= sampler_state_data_i[0][1023:768]; + end else if (prim_instr.operand3 == MLDSA_DEST_TR_REG_ID) begin + //HW write tr + privatekey_reg.enc.tr <= sampler_state_data_i[0][511:0]; + end + end else if (mldsa_reg_hwif_in.MLDSA_PRIVKEY_IN.wr_ack & mldsa_ready & api_sk_reg_wr_dec) begin + //SW write port + privatekey_reg.raw[api_sk_reg_waddr] <= mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.wr_data; + end + end + end + + //private key read ports + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + privkey_reg_rdata <= '0; + end else if (zeroize) begin + privkey_reg_rdata <= '0; + end else begin + if (mldsa_valid_reg & mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & ~mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr & api_sk_reg_rd_dec) begin + privkey_reg_rdata <= privatekey_reg.raw[api_sk_reg_raddr]; + end + end + end + + assign mldsa_reg_hwif_in.MLDSA_PRIVKEY_IN.wr_ack = mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.req & mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.req_is_wr; + //no reads to PRIVKEY_IN allowed - just ack it + assign mldsa_reg_hwif_in.MLDSA_PRIVKEY_IN.rd_ack = mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.req & ~mldsa_reg_hwif_out.MLDSA_PRIVKEY_IN.req_is_wr; + assign mldsa_reg_hwif_in.MLDSA_PRIVKEY_IN.rd_data = '0; + + + logic privkey_out_rd_ack, signature_rd_ack, pubkey_rd_ack; + + always_comb mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_ack = privkey_out_rd_ack; + always_comb mldsa_reg_hwif_in.MLDSA_SIGNATURE.rd_ack = signature_rd_ack; + always_comb mldsa_reg_hwif_in.MLDSA_PUBKEY.rd_ack = pubkey_rd_ack; + + //ack the read request one clock later + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + privkey_out_rd_ack <= 0; + signature_rd_ack <= 0; + pubkey_rd_ack <= 0; + end + else if (zeroize) begin + privkey_out_rd_ack <= 0; + signature_rd_ack <= 0; + pubkey_rd_ack <= 0; + end + else begin + privkey_out_rd_ack <= mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & ~mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr; + signature_rd_ack <= mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & ~mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr; + pubkey_rd_ack <= mldsa_reg_hwif_out.MLDSA_PUBKEY.req & ~mldsa_reg_hwif_out.MLDSA_PUBKEY.req_is_wr; + end + end + + always_comb mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.rd_data = privkey_out_rd_ack & mldsa_valid_reg & keygen_process & ~mldsa_privkey_lock ? privkey_out_rdata : 0; + + //No write to PRIVKEY_OUT allowed - just ack it + assign mldsa_reg_hwif_in.MLDSA_PRIVKEY_OUT.wr_ack = mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req & mldsa_reg_hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr; + + //Signature external mem + logic sig_z_ram_we, sig_z_ram_re; + logic [SIG_Z_MEM_ADDR_W-1:0] sig_z_ram_waddr, sig_z_ram_raddr; + logic [SIG_Z_MEM_NUM_DWORD-1:0][31:0] sig_z_ram_wdata, sig_z_ram_rdata; + logic [SIG_Z_MEM_WSTROBE_W-1:0] sig_z_ram_wstrobe; + logic api_sig_z_dec, api_sig_h_dec, api_sig_c_dec; + logic api_sig_z_re, api_sig_z_re_f, api_sig_z_we; + logic [SIG_ADDR_W-1:0] api_sig_addr; + mldsa_signature_z_addr_t api_sig_z_addr; + mldsa_signature_z_addr_t api_sig_z_addr_f; + logic [SIG_C_REG_ADDR_W-1:0] api_sig_c_addr; + logic [SIG_H_REG_ADDR_W-1:0] api_sig_h_addr; + logic [DATA_WIDTH-1:0] signature_reg_rdata; + + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + api_sig_z_re_f <= '0; + api_sig_z_addr_f <= '0; + end else if (zeroize) begin + api_sig_z_re_f <= '0; + api_sig_z_addr_f <= '0; + end else begin + api_sig_z_re_f <= api_sig_z_re; + api_sig_z_addr_f <= api_sig_z_addr; + end + end + + always_comb api_sig_addr = SIGNATURE_NUM_DWORDS-1-mldsa_reg_hwif_out.MLDSA_SIGNATURE.addr[SIG_ADDR_W+1:2]; + + always_comb api_sig_c_dec = mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & api_sig_addr inside {[0:SIGNATURE_C_NUM_DWORDS-1]}; + always_comb api_sig_z_dec = mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & api_sig_addr inside {[SIGNATURE_C_NUM_DWORDS:SIGNATURE_C_NUM_DWORDS+SIGNATURE_Z_NUM_DWORDS-1]}; + always_comb api_sig_h_dec = mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & api_sig_addr inside {[SIGNATURE_C_NUM_DWORDS+SIGNATURE_Z_NUM_DWORDS:SIGNATURE_NUM_DWORDS-1]}; + + always_comb api_sig_z_addr.addr = SIG_Z_MEM_ADDR_W'( (api_sig_addr - SIGNATURE_C_NUM_DWORDS)/SIG_Z_MEM_NUM_DWORD ); + always_comb api_sig_z_addr.offset = (api_sig_addr - SIGNATURE_C_NUM_DWORDS)%SIG_Z_MEM_NUM_DWORD; //FIXME can this be done better? + always_comb api_sig_c_addr = api_sig_addr[SIG_C_REG_ADDR_W-1:0]; + always_comb api_sig_h_addr = SIG_H_REG_ADDR_W'( api_sig_addr - (SIGNATURE_C_NUM_DWORDS+SIGNATURE_Z_NUM_DWORDS) ); + + always_comb mldsa_reg_hwif_in.MLDSA_SIGNATURE.wr_ack = mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr; + always_comb api_sig_z_we = mldsa_ready & api_sig_z_dec & mldsa_reg_hwif_in.MLDSA_SIGNATURE.wr_ack; + + always_comb api_sig_z_re = mldsa_valid_reg & api_sig_z_dec & ~mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr; + + always_comb sig_z_mem_if.we_i = (sig_z_ram_we); + always_comb sig_z_mem_if.waddr_i = (sig_z_ram_waddr); + always_comb sig_z_mem_if.wstrobe_i = (sig_z_ram_wstrobe); + always_comb sig_z_mem_if.wdata_i = (sig_z_ram_wdata); + always_comb sig_z_mem_if.re_i = (sig_z_ram_re); + always_comb sig_z_mem_if.raddr_i = (sig_z_ram_raddr); + always_comb sig_z_ram_rdata = sig_z_mem_if.rdata_o; + + //read requests + always_comb sig_z_ram_re = (sigdecode_z_rd_req_i.rd_wr_en == RW_READ) | api_sig_z_re; + always_comb sig_z_ram_raddr = ({SIG_Z_MEM_ADDR_W{(sigdecode_z_rd_req_i.rd_wr_en == RW_READ)}} & sigdecode_z_rd_req_i.addr[SIG_Z_MEM_ADDR_W:1]) | + ({SIG_Z_MEM_ADDR_W{api_sig_z_re}} & api_sig_z_addr.addr); + + always_comb sigdecode_z_rd_data_o = sig_z_ram_rdata; + always_comb mldsa_reg_hwif_in.MLDSA_SIGNATURE.rd_data = api_sig_z_re_f ? sig_z_ram_rdata[api_sig_z_addr_f.offset] : signature_reg_rdata; + + //write requests + always_comb sig_z_ram_we = (sigencode_wr_req_i.rd_wr_en == RW_WRITE) | api_sig_z_we | zeroize_mem_we; + always_comb sig_z_ram_waddr = ({SIG_Z_MEM_ADDR_W{(sigencode_wr_req_i.rd_wr_en == RW_WRITE)}} & sigencode_wr_req_i.addr[SIG_Z_MEM_ADDR_W:1]) | + ({SIG_Z_MEM_ADDR_W{api_sig_z_we}} & api_sig_z_addr.addr) | + ({SIG_Z_MEM_ADDR_W{zeroize_mem_we}} & zeroize_mem_addr[SIG_Z_MEM_ADDR_W-1:0]); + + always_comb sig_z_ram_wstrobe = ({SIG_Z_MEM_WSTROBE_W{(sigencode_wr_req_i.rd_wr_en == RW_WRITE)}}) | + ({SIG_Z_MEM_WSTROBE_W{api_sig_z_we}} & ('hF << api_sig_z_addr.offset*4)) | + ({SIG_Z_MEM_WSTROBE_W{zeroize_mem_we}}); + + + always_comb sig_z_ram_wdata = ({SIG_Z_MEM_DATA_W{(sigencode_wr_req_i.rd_wr_en == RW_WRITE)}} & sigencode_wr_data_i) | + ({SIG_Z_MEM_DATA_W{(api_sig_z_we)}} & SIG_Z_MEM_DATA_W'(mldsa_reg_hwif_out.MLDSA_SIGNATURE.wr_data << api_sig_z_addr.offset*32)); + + //signature reg read flop + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + signature_reg_rdata <= '0; + end else if (zeroize) begin + signature_reg_rdata <= '0; + end else begin + if (mldsa_valid_reg & mldsa_reg_hwif_out.MLDSA_SIGNATURE.req & ~mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr) + signature_reg_rdata <= {DATA_WIDTH{api_sig_c_dec}} & signature_reg.enc.c[api_sig_c_addr] | + {DATA_WIDTH{api_sig_h_dec}} & signature_reg.enc.h[api_sig_h_addr]; + end + end + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + signature_reg <= '0; + end else if (zeroize) begin + signature_reg <= '0; + end else begin + //HW write c + if (sampler_state_dv_i & (prim_instr.operand3 == MLDSA_DEST_SIG_C_REG_ID)) begin + signature_reg.enc.c <= sampler_state_data_i[0][511:0]; + end else if (mldsa_ready & api_sig_c_dec & mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr) begin + for (int dword = 0; dword < SIGNATURE_NUM_DWORDS; dword++) begin + signature_reg.enc.c[api_sig_c_addr] <= mldsa_reg_hwif_out.MLDSA_SIGNATURE.wr_data; + end + end + //HW write h + if (set_signature_valid) begin + signature_reg.enc.h <= '0; + end else if (makehint_reg_wren_i) begin + for (int dword = 0; dword < SIGNATURE_H_NUM_DWORDS; dword++) begin + if (makehint_reg_wr_addr_i == dword) + signature_reg.enc.h[dword] <= signature_reg.enc.h[dword] | makehint_reg_wrdata_i; + end + end else if (mldsa_ready & api_sig_h_dec & mldsa_reg_hwif_out.MLDSA_SIGNATURE.req_is_wr) begin + signature_reg.enc.h[api_sig_h_addr] <= mldsa_reg_hwif_out.MLDSA_SIGNATURE.wr_data; + end + end + end + + always_comb begin + //HW read h + for (int i = 0; i < SIGNATURE_H_VALID_NUM_BYTES; i++) begin + signature_h_o[i] = signature_reg.enc.h[i/4][(i%4)*8 +: 8]; + end + end + + +//public key memory + logic pubkey_ram_we, pubkey_ram_re; + logic [PK_MEM_ADDR_W-1:0] pubkey_ram_waddr, pubkey_ram_raddr; + logic [PK_MEM_NUM_DWORDS-1:0][31:0] pubkey_ram_wdata, pubkey_ram_rdata; + logic [31:0][T1_COEFF_W-1:0] pubkey_ram_rdata_t1; + logic [PK_MEM_WSTROBE_W-1:0] pubkey_ram_wstrobe; + logic api_pubkey_dec, api_pubkey_rho_dec; + logic api_pubkey_re, api_pubkey_re_f, api_pubkey_we; + logic [PK_ADDR_W-1:0] api_pubkey_addr; + mldsa_pubkey_mem_addr_t api_pubkey_mem_addr; + mldsa_pubkey_mem_addr_t api_pubkey_mem_addr_f; + mldsa_pubkey_mem_addr_t sampler_pubkey_mem_addr; + logic [PK_RHO_REG_ADDR_W-1:0] api_pk_rho_addr; + logic [DATA_WIDTH-1:0] pk_reg_rdata; + logic sampler_pk_rd_en, sampler_pk_rd_en_f, pkdecode_rd_en; + logic [1:0] pkdecode_rd_offset_f; + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + api_pubkey_re_f <= '0; + api_pubkey_mem_addr_f <= '0; + sampler_pk_rd_en_f <= '0; + sampler_src_offset_f <= '0; + pkdecode_rd_offset_f <= '0; + end else if (zeroize) begin + api_pubkey_re_f <= '0; + api_pubkey_mem_addr_f <= '0; + sampler_pk_rd_en_f <= '0; + sampler_src_offset_f <= '0; + pkdecode_rd_offset_f <= '0; + end else begin + api_pubkey_re_f <= api_pubkey_re; + api_pubkey_mem_addr_f <= api_pubkey_mem_addr; + sampler_pk_rd_en_f <= msg_hold ? sampler_pk_rd_en_f : sampler_pk_rd_en; + sampler_src_offset_f <= msg_hold ? sampler_src_offset_f : sampler_pubkey_mem_addr.offset[2:0]; + pkdecode_rd_offset_f <= pkdecode_rd_addr_i[1:0]; + end + end + + always_comb api_pubkey_addr = PUBKEY_NUM_DWORDS-1-mldsa_reg_hwif_out.MLDSA_PUBKEY.addr[PK_ADDR_W+1:2]; + + always_comb api_pubkey_rho_dec = mldsa_reg_hwif_out.MLDSA_PUBKEY.req & api_pubkey_addr inside {[0:7]}; + always_comb api_pubkey_dec = mldsa_reg_hwif_out.MLDSA_PUBKEY.req & api_pubkey_addr inside {[8:PUBKEY_NUM_DWORDS-1]}; + + always_comb api_pubkey_mem_addr.addr = PK_MEM_ADDR_W'( (api_pubkey_addr - 8)/PK_MEM_NUM_DWORDS ); + always_comb api_pubkey_mem_addr.offset = (api_pubkey_addr - 8)%PK_MEM_NUM_DWORDS; //FIXME can this be done better? + + always_comb sampler_pubkey_mem_addr.addr = PK_MEM_ADDR_W'((sampler_src_offset- 4)/(PK_MEM_NUM_DWORDS/2)); + always_comb sampler_pubkey_mem_addr.offset = (sampler_src_offset- 4)%(PK_MEM_NUM_DWORDS/2); + always_comb api_pk_rho_addr = api_pubkey_addr[2:0]; + + always_comb mldsa_reg_hwif_in.MLDSA_PUBKEY.wr_ack = mldsa_reg_hwif_out.MLDSA_PUBKEY.req & mldsa_reg_hwif_out.MLDSA_PUBKEY.req_is_wr; + always_comb api_pubkey_we = mldsa_ready & api_pubkey_dec & mldsa_reg_hwif_in.MLDSA_PUBKEY.wr_ack; + + always_comb api_pubkey_re = mldsa_valid_reg & api_pubkey_dec & ~mldsa_reg_hwif_out.MLDSA_PUBKEY.req_is_wr; + + + always_comb pk_mem_if.we_i = (pubkey_ram_we); + always_comb pk_mem_if.waddr_i = (pubkey_ram_waddr); + always_comb pk_mem_if.wstrobe_i = (pubkey_ram_wstrobe); + always_comb pk_mem_if.wdata_i = (pubkey_ram_wdata); + always_comb pk_mem_if.re_i = (pubkey_ram_re); + always_comb pk_mem_if.raddr_i = (pubkey_ram_raddr); + always_comb pubkey_ram_rdata = pk_mem_if.rdata_o; + + assign pubkey_ram_rdata_t1 = pubkey_ram_rdata; + + always_comb pkdecode_rd_en = prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_PKDECODE); + + always_comb sampler_pk_rd_en = (sampler_src == MLDSA_PK_REG_ID) & (sampler_src_offset inside {[4:342]}) & ~msg_hold; + + //read requests + always_comb pubkey_ram_re = sampler_pk_rd_en | pkdecode_rd_en | api_pubkey_re; + always_comb pubkey_ram_raddr = ({PK_MEM_ADDR_W{sampler_pk_rd_en}} & sampler_pubkey_mem_addr.addr) | + ({PK_MEM_ADDR_W{pkdecode_rd_en}} & pkdecode_rd_addr_i[PK_MEM_ADDR_W+1:2]) | + ({PK_MEM_ADDR_W{api_pubkey_re}} & api_pubkey_mem_addr.addr); + + always_comb begin + unique case (pkdecode_rd_offset_f[1:0]) + 2'b00: pkdecode_rd_data_o = pubkey_ram_rdata_t1[7:0]; + 2'b01: pkdecode_rd_data_o = pubkey_ram_rdata_t1[15:8]; + 2'b10: pkdecode_rd_data_o = pubkey_ram_rdata_t1[23:16]; + 2'b11: pkdecode_rd_data_o = pubkey_ram_rdata_t1[31:24]; + endcase + end + + always_comb mldsa_reg_hwif_in.MLDSA_PUBKEY.rd_data = api_pubkey_re_f ? pubkey_ram_rdata[api_pubkey_mem_addr_f.offset] : pk_reg_rdata; + + //write requests + always_comb pubkey_ram_we = (pk_t1_wren_i) | api_pubkey_we | zeroize_mem_we; + always_comb pubkey_ram_waddr = ({PK_MEM_ADDR_W{pk_t1_wren_i}} & pk_t1_wr_addr_i[PK_MEM_ADDR_W+1:2]) | + ({PK_MEM_ADDR_W{api_pubkey_we}} & api_pubkey_mem_addr.addr) | + ({PK_MEM_ADDR_W{zeroize_mem_we}} & zeroize_mem_addr[PK_MEM_ADDR_W-1:0]); + + always_comb pubkey_ram_wstrobe = ({PK_MEM_WSTROBE_W{pk_t1_wren_i}} & 'h3FF << pk_t1_wr_addr_i[1:0]*10) | + ({PK_MEM_WSTROBE_W{api_pubkey_we}} & ('hF << api_pubkey_mem_addr.offset*4)) | + ({PK_MEM_WSTROBE_W{zeroize_mem_we}}); + + + always_comb pubkey_ram_wdata = ({PK_MEM_DATA_W{pk_t1_wren_i}} & PK_MEM_DATA_W'(pk_t1_wrdata_i << pk_t1_wr_addr_i[1:0]*80)) | + ({PK_MEM_DATA_W{(api_pubkey_we)}} & PK_MEM_DATA_W'(mldsa_reg_hwif_out.MLDSA_PUBKEY.wr_data << api_pubkey_mem_addr.offset*32)); + + + //pk reg read flop + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + pk_reg_rdata <= '0; + end else if (zeroize) begin + pk_reg_rdata <= '0; + end else begin + if (mldsa_valid_reg & api_pubkey_rho_dec) + pk_reg_rdata <= publickey_reg.enc.rho[api_pk_rho_addr]; + end + end + + //Public Key rho + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + publickey_reg <= '0; + end else if (zeroize) begin + publickey_reg <= '0; + end else begin + //HW write rho + if (sampler_state_dv_i & (prim_instr.operand3 == MLDSA_DEST_K_RHO_REG_ID)) begin + publickey_reg.enc.rho <= sampler_state_data_i[0][255:0]; + end else if (mldsa_ready & api_pubkey_rho_dec & mldsa_reg_hwif_out.MLDSA_PUBKEY.req_is_wr) begin + publickey_reg.enc.rho[api_pk_rho_addr] <= mldsa_reg_hwif_out.MLDSA_PUBKEY.wr_data; + end + end + end + + //pure-MLDSA assuming 512-bit input msg and empty ctx + logic [MSG_NUM_DWORDS-1+1 : 0][DATA_WIDTH-1:0] msg_p_reg; + always_comb msg_p_reg = {16'h0, msg_reg, 8'h00, 8'h00}; + + always_comb rho_reg = verifying_process ? publickey_reg.enc.rho : privatekey_reg.enc.rho; + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + msg_data <= '0; + end else if (zeroize) begin + msg_data <= '0; + end else begin + unique case (sampler_src) inside + MLDSA_SEED_ID: msg_data <= msg_done ? {48'b0,sampler_imm} : {seed_reg[{sampler_src_offset[1:0],1'b1}],seed_reg[{sampler_src_offset[1:0],1'b0}]}; + MLDSA_RHO_ID: msg_data <= msg_done ? {48'b0,sampler_imm} : rho_reg[sampler_src_offset[1:0]]; + MLDSA_RHO_P_ID: msg_data <= msg_done ? {48'b0,sampler_imm} : rho_p_reg[sampler_src_offset[2:0]]; + MLDSA_TR_ID: msg_data <= privatekey_reg.enc.tr[sampler_src_offset[2:0]]; + MLDSA_MSG_ID: msg_data <= {msg_p_reg[{sampler_src_offset[3:0],1'b1}],msg_p_reg[{sampler_src_offset[3:0],1'b0}]}; + MLDSA_K_ID: msg_data <= privatekey_reg.enc.K[sampler_src_offset[1:0]]; + MLDSA_MU_ID: msg_data <= mu_reg[sampler_src_offset[2:0]]; + MLDSA_SIGN_RND_ID: msg_data <= {sign_rnd_reg[{sampler_src_offset[1:0],1'b1}],sign_rnd_reg[{sampler_src_offset[1:0],1'b0}]}; + MLDSA_RHO_P_KAPPA_ID: msg_data <= msg_done ? {48'b0,(kappa_reg + sampler_imm[2:0])} : rho_p_reg[sampler_src_offset[2:0]]; + MLDSA_SIG_C_REG_ID: msg_data <= {signature_reg.enc.c[{sampler_src_offset[2:0],1'b1}], signature_reg.enc.c[{sampler_src_offset[2:0],1'b0}]}; + MLDSA_PK_REG_ID: msg_data <= {publickey_reg.enc.rho[{sampler_src_offset[1:0],1'b1}],publickey_reg.enc.rho[{sampler_src_offset[1:0],1'b0}]}; + MLDSA_ENTROPY_ID: msg_data <= lfsr_entropy_reg[sampler_src_offset[2:0]]; + MLDSA_CNT_ID: msg_data <= counter_reg; + default: msg_data <= '0; + endcase + end + end + + always_comb begin + msg_data_o[0] = sampler_pk_rd_en_f ? {pubkey_ram_rdata[{sampler_src_offset_f[2:0],1'b1}],pubkey_ram_rdata[{sampler_src_offset_f[2:0],1'b0}]} : + msg_data; + end + + //If we're storing state directly into registers, do that here + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + rho_p_reg <= 0; + end + else if (zeroize) begin + rho_p_reg <= 0; + end + else if (sampler_state_dv_i) begin + if (prim_instr.operand3 == MLDSA_DEST_K_RHO_REG_ID) begin + rho_p_reg <= sampler_state_data_i[0][767:256]; + end + else if (prim_instr.operand3 == MLDSA_DEST_RHO_P_REG_ID) begin + rho_p_reg <= sampler_state_data_i[0][511:0]; + end + end + end + + always_comb begin + internal_mu_we = sampler_state_dv_i & (prim_instr.operand3 == MLDSA_DEST_MU_REG_ID); + internal_mu_reg = sampler_state_data_i[0][511:0]; + mu_reg = external_mu_reg; + end + + // without zeroize to make it more complex + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + lfsr_seed_o <= '0; + lfsr_entropy_reg <= '0; + end + else if (set_entropy) begin + lfsr_entropy_reg <= lfsr_entropy_reg ^ entropy_reg; + end + else if (sampler_state_dv_i) begin + if (prim_instr.operand3 == MLDSA_DEST_LFSR_SEED_REG_ID) begin + lfsr_seed_o <= sampler_state_data_i[0][2*LFSR_W-1:0]; + lfsr_entropy_reg <= sampler_state_data_i[0][2*LFSR_W+511:2*LFSR_W]; + end + end + end + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + kappa_reg <= '0; + end + else if (zeroize) begin + kappa_reg <= '0; + end + else if (update_kappa) begin + kappa_reg <= kappa_reg + 7; + end + end + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + mldsa_valid_reg <= '0; + y_valid <= '0; + w0_valid <= '0; + c_valid <= '0; + signature_valid <= 0; + verify_valid <= 0; + keygen_process <= 0; + signing_process <= 0; + verifying_process <= 0; + keygen_signing_process <= 0; + end + else if (zeroize) begin + mldsa_valid_reg <= '0; + y_valid <= '0; + w0_valid <= '0; + c_valid <= '0; + signature_valid <= 0; + verify_valid <= 0; + keygen_process <= 0; + signing_process <= 0; + verifying_process <= 0; + keygen_signing_process <= 0; + end + else begin + mldsa_valid_reg <= mldsa_valid_reg | process_done; + y_valid <= set_y_valid ? 1 : + clear_y_valid ? 0 : + y_valid; + w0_valid <= set_w0_valid ? 1 : + clear_w0_valid ? 0 : + w0_valid; + c_valid <= set_c_valid ? 1 : + clear_c_valid ? 0 : + c_valid; + signature_valid <= set_signature_valid ? 1 : + clear_signature_valid ? 0 : + signature_valid; + verify_valid <= set_verify_valid ? 1 : + clear_verify_valid ? 0 : + verify_valid; + keygen_process <= process_done ? '0 : keygen_process | keygen_process_nxt; + signing_process <= process_done ? '0 : signing_process | signing_process_nxt; + verifying_process <= process_done ? '0 : verifying_process | verifying_process_nxt; + keygen_signing_process <= process_done ? '0 : keygen_signing_process | keygen_signing_process_nxt; + end + end + + always_comb process_done = (keygen_process & keygen_done) | + (signing_process & signature_done) | + (verifying_process & verify_done); + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) + external_mu_mode <= 0; + else if (zeroize | process_done) + external_mu_mode <= 0; + else if (process_done) + external_mu_mode <= 0; + else + external_mu_mode <= external_mu_mode | external_mu_mode_nxt; + end + + //Clear signature if makehint or normcheck fail + always_comb clear_signature_valid = signing_process & ((makehint_done_i & makehint_invalid_i) | (normcheck_done_i & normcheck_invalid_i)); + + //FIXME jump to done if this happens, could cause x reads (or fix sigdecode to not stop early) + always_comb clear_verify_valid = verifying_process & ((normcheck_done_i & normcheck_invalid_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_SIGDEC_H) & sigdecode_h_invalid_i)); + +//Primary sequencer for keygen, signing, and verify + always_comb subcomponent_busy = !(ctrl_fsm_ns inside {MLDSA_CTRL_IDLE, MLDSA_CTRL_MSG_WAIT}) | + sampler_busy_i | + ntt_busy_i[0]; +`ifdef CALIPTRA + always_comb pcr_sign_input_invalid = (cmd_reg inside {MLDSA_KEYGEN, MLDSA_SIGN, MLDSA_VERIFY}) & pcr_sign_mode; + always_comb error_flag = skdecode_error_i | pcr_sign_input_invalid; +`else + always_comb error_flag = skdecode_error_i; +`endif + + always_ff @(posedge clk or negedge rst_b) + begin : error_detection + if(!rst_b) + error_flag_reg <= 1'b0; + else if(zeroize) + error_flag_reg <= 1'b0; + else if (error_flag) + error_flag_reg <= 1'b1; + end // error_detection + + always_comb error_flag_edge = error_flag & (!error_flag_reg); + + //program counter + always_ff @(posedge clk or negedge rst_b) begin + if(!rst_b) begin + prim_prog_cntr <= MLDSA_RESET; + end + else if(zeroize) begin + prim_prog_cntr <= MLDSA_ZEROIZE; + end + else begin + if (error_flag_edge) begin + prim_prog_cntr <= MLDSA_ERROR; + end + else begin + prim_prog_cntr <= prim_prog_cntr_nxt; + end + end + end + //Subroutine decode + always_comb begin + keygen_process_nxt = 0; + signing_process_nxt = 0; + verifying_process_nxt = 0; + keygen_signing_process_nxt = 0; + keygen_done = 0; + signature_done = 0; + verify_done = 0; + set_y_valid = 0; + set_w0_valid = 0; + set_c_valid = 0; + update_kappa = 0; + set_verify_valid = 0; + set_entropy = 0; + prim_prog_cntr_nxt = MLDSA_RESET; + prim_seq_en = !zeroize; + external_mu_mode_nxt = 0; + + unique case (prim_prog_cntr) inside + MLDSA_RESET : begin + // Waiting for new valid command + unique case (cmd_reg) inside + MLDSA_KEYGEN : begin // keygen + prim_prog_cntr_nxt = MLDSA_KG_S; + keygen_process_nxt = 1; + set_entropy = 1; + external_mu_mode_nxt = 0; + end + MLDSA_SIGN : begin // signing + prim_prog_cntr_nxt = MLDSA_SIGN_S; + signing_process_nxt = 1; + set_entropy = 1; + external_mu_mode_nxt = external_mu; + end + MLDSA_VERIFY : begin // verifying + prim_prog_cntr_nxt = MLDSA_VERIFY_S; + verifying_process_nxt = 1; + set_verify_valid = 1; + external_mu_mode_nxt = external_mu; + end + MLDSA_KEYGEN_SIGN : begin // KEYGEN + SIGNING + prim_prog_cntr_nxt = MLDSA_KG_S; + keygen_signing_process_nxt = 1; + set_entropy = 1; + external_mu_mode_nxt = external_mu; + end + default : begin + prim_prog_cntr_nxt = MLDSA_RESET; + prim_seq_en = 0; + external_mu_mode_nxt = 0; + end + endcase + end + MLDSA_ZEROIZE : begin + if (zeroize_mem_done) + prim_prog_cntr_nxt = MLDSA_RESET; + else + prim_prog_cntr_nxt = MLDSA_ZEROIZE; + prim_seq_en = 0; + end + MLDSA_KG_JUMP_SIGN : begin + //Jump to signing process + if (keygen_signing_process) begin + prim_prog_cntr_nxt = MLDSA_SIGN_CHECK_MODE; + signing_process_nxt = 1; + end + else begin + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + end + MLDSA_KG_E : begin // end of keygen + //prim_prog_cntr_nxt = MLDSA_RESET; + keygen_done = 1; + end + MLDSA_SIGN_CHECK_MODE : begin + if (external_mu_mode) + prim_prog_cntr_nxt = MLDSA_SIGN_H_RHO_P; + else + prim_prog_cntr_nxt = MLDSA_SIGN_H_MU; + end + //START of Y access - check if Y is still valid + MLDSA_SIGN_CHECK_Y_CLR : begin + if (signature_validity_chk_done) + prim_prog_cntr_nxt = MLDSA_SIGN_E; + else if (y_valid | w0_valid) begin //Stalled until Y and w0 can be overwritten + prim_prog_cntr_nxt = prim_prog_cntr; + end + else begin + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + end + //END of Y access - SET Y valid + MLDSA_SIGN_SET_Y : begin + set_y_valid = 1; + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + //START of W0 access - check if W0 is still valid + MLDSA_SIGN_CHECK_W0_CLR : begin + if (signature_validity_chk_done) + prim_prog_cntr_nxt = MLDSA_SIGN_E; + else if (w0_valid) begin //Stalled until W0 can be overwritten + prim_prog_cntr_nxt = prim_prog_cntr; + end + else begin + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + end + //END of W0 access - SET W0 valid + MLDSA_SIGN_SET_W0 : begin + set_w0_valid = 1; + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + //START of C access - check if C is still valid + MLDSA_SIGN_CHECK_C_CLR : begin + if (c_valid) begin //Stalled until C can be overwritten + prim_prog_cntr_nxt = prim_prog_cntr; + end + else begin + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + end + //END of C access - SET C valid + MLDSA_SIGN_SET_C : begin + set_c_valid = 1; + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + MLDSA_SIGN_CHL_E : begin // end of challenge generation + if (signature_validity_chk_done) + prim_prog_cntr_nxt = MLDSA_SIGN_E; + else begin + //increment kappa value + update_kappa = 1; + //restart challenge generation + prim_prog_cntr_nxt = MLDSA_SIGN_CHECK_Y_CLR; + end + end + MLDSA_SIGN_E : begin // end of signature + signature_done = 1; + end + MLDSA_VERIFY_CHECK_MODE : begin + if (external_mu_mode) + prim_prog_cntr_nxt = MLDSA_VERIFY_MAKE_C; + else + prim_prog_cntr_nxt = MLDSA_VERIFY_H_MU; + end + MLDSA_VERIFY_E : begin // end of verify flow + verify_done = 1; + end + default : begin + if (signature_validity_chk_done) + prim_prog_cntr_nxt = MLDSA_SIGN_E; + else if (subcomponent_busy) begin //Stalled until sub-component is done + prim_prog_cntr_nxt = prim_prog_cntr; + end + else begin + prim_prog_cntr_nxt = prim_prog_cntr + 1; + end + end + endcase + end + +//Controller prim_instr decode - drives sampler and primary ntt +//FIXME latch the sampler mode here + always_comb begin + sampler_mode_o = MLDSA_SAMPLER_NONE; + if (prim_instr.opcode.sampler_en) begin + if (prim_instr.opcode.ntt_en & prim_instr.opcode.mode.ntt_mode inside {MLDSA_PWM_SMPL, MLDSA_PWM_ACCUM_SMPL}) begin + sampler_mode_o = MLDSA_REJ_SAMPLER; + end else begin + sampler_mode_o = prim_instr.opcode.mode.sampler_mode; + end + end else if (prim_instr.opcode.keccak_en) begin + sampler_mode_o = prim_instr.opcode.mode.sampler_mode; + end else if (prim_instr.opcode.aux_en) begin + if (prim_instr.opcode.mode.aux_mode == MLDSA_DECOMP) begin + sampler_mode_o = MLDSA_SHAKE256; + end + end + end + + always_comb begin + ntt_mode_o[0] = MLDSA_NTT_NONE; + ntt_masking_en_o[0] = 0; + ntt_shuffling_en_o[0] = 0; + if (prim_instr.opcode.ntt_en) begin + ntt_mode_o[0] = prim_instr.opcode.mode.ntt_mode; + ntt_masking_en_o[0] = prim_instr.opcode.masking_en; + ntt_shuffling_en_o[0] = prim_instr.opcode.shuffling_en; + end + end + + always_comb sampler_src_offset = {4'b0, msg_cnt}; //fixme + + //passing a bit on the immediate field to mux between temp address locations + always_comb ntt_temp_address[0] = prim_instr.imm[0] ? MLDSA_TEMP3_BASE : MLDSA_TEMP0_BASE; + + //FIXME one interface here? + always_comb ntt_mem_base_addr_o[0] = '{src_base_addr:prim_instr.operand1[MLDSA_MEM_ADDR_WIDTH-1:0], + interim_base_addr:ntt_temp_address[0], + dest_base_addr:prim_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]}; + + always_comb pwo_mem_base_addr_o[0] = '{pw_base_addr_b:prim_instr.operand1[MLDSA_MEM_ADDR_WIDTH-1:0], //FIXME PWO src + pw_base_addr_a:prim_instr.operand2[MLDSA_MEM_ADDR_WIDTH-1:0], //FIXME PWO src or sampler src + pw_base_addr_c:prim_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]}; + + always_comb dest_base_addr_o = prim_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]; + always_comb aux_src0_base_addr_o[0] = prim_instr.operand1[MLDSA_MEM_ADDR_WIDTH-1:0]; + always_comb aux_src1_base_addr_o[0] = prim_instr.operand2[MLDSA_MEM_ADDR_WIDTH-1:0]; + always_comb aux_dest_base_addr_o[0] = prim_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]; + +//determine the number of bytes in the last message +//operand 2 contains the length of the message being fed to sha3 +//shift a zero into the strobe for each byte, and invert to get the valid bytes +always_comb last_msg_strobe = ~(MsgStrbW'('1) << prim_instr.length[$clog2(MsgStrbW)-1:0]); + +always_comb msg_hold = msg_valid_o & ~msg_rdy_i; + +//Done when msg count is equal to length +//length is in bytes - compare against MSB from strobe width gets us the length in msg interface chunks +always_comb msg_done = (msg_cnt >= prim_instr.length[MLDSA_OPR_WIDTH-1:$clog2(MsgStrbW)]); + +always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + msg_cnt <= 0; + msg_valid_o <= 0; + msg_strobe_o <= 0; + end + else if (zeroize) begin + msg_cnt <= 0; + msg_valid_o <= 0; + msg_strobe_o <= 0; + end + else begin + msg_cnt <= msg_hold ? msg_cnt : + msg_done ? 'd0 : + msg_valid ? msg_cnt + 'd1 : msg_cnt; + msg_valid_o <= msg_hold ? msg_valid_o : msg_valid; + msg_strobe_o <= msg_hold ? msg_strobe_o : + msg_done ? last_msg_strobe : '1; + end +end + +always_comb decompose_mode_o = prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_USEHINT); + +//State logic +always_comb begin : primary_ctrl_fsm_out_combo + ctrl_fsm_ns = ctrl_fsm_ps; + sha3_start_o = 0; + msg_start_o = 0; + msg_valid = 0; + sampler_start_o = 0; + sampler_src = 0; + sampler_imm = 0; + ntt_enable_o[0] = 0; + power2round_enable_o = 0; + decompose_enable_o = 0; + skencode_enable_o = 0; + pkdecode_enable_o = 0; + sigdecode_h_enable_o = 0; + sigdecode_z_enable_o = 0; + normcheck_enable[0] = 0; + lfsr_enable_o = 0; + + unique case (ctrl_fsm_ps) + MLDSA_CTRL_IDLE: begin + //load keccak data to SIPO + if (prim_instr.opcode.keccak_en) + ctrl_fsm_ns = MLDSA_CTRL_SHA3_START; + //start sampler flow, data already driven to SIPO + else if (prim_instr.opcode.sampler_en | prim_instr.opcode.ntt_en | prim_instr.opcode.aux_en) + ctrl_fsm_ns = MLDSA_CTRL_FUNC_START; + end + MLDSA_CTRL_SHA3_START: begin + ctrl_fsm_ns = MLDSA_CTRL_MSG_START; + //drive start + sha3_start_o = 1; + end + MLDSA_CTRL_MSG_START: begin + ctrl_fsm_ns = MLDSA_CTRL_MSG_LOAD; + msg_start_o = 1; + end + MLDSA_CTRL_MSG_LOAD: begin + msg_valid = 1; + sampler_src = prim_instr.operand1; + sampler_imm = prim_instr.imm; + if (msg_done & ~msg_hold) begin + if (prim_instr.opcode.sampler_en) ctrl_fsm_ns = MLDSA_CTRL_FUNC_START; + else ctrl_fsm_ns = MLDSA_CTRL_MSG_WAIT; + end + end + MLDSA_CTRL_MSG_WAIT: begin + //load another message + if (prim_instr.opcode.keccak_en) ctrl_fsm_ns = MLDSA_CTRL_MSG_LOAD; + //kick off the sampler + else if (prim_instr.opcode.sampler_en | prim_instr.opcode.aux_en | prim_instr.opcode.ntt_en) ctrl_fsm_ns = MLDSA_CTRL_FUNC_START; + else ctrl_fsm_ns = MLDSA_CTRL_MSG_LOAD; + end + MLDSA_CTRL_FUNC_START: begin + ctrl_fsm_ns = MLDSA_CTRL_DONE; + sampler_start_o = prim_instr.opcode.sampler_en; + ntt_enable_o[0] = prim_instr.opcode.ntt_en; + if (prim_instr.opcode.aux_en) begin + power2round_enable_o = (prim_instr.opcode.mode.aux_mode == MLDSA_PWR2RND); + decompose_enable_o = (prim_instr.opcode.mode.aux_mode inside {MLDSA_DECOMP,MLDSA_USEHINT}); + skencode_enable_o = (prim_instr.opcode.mode.aux_mode == MLDSA_SKENCODE); + pkdecode_enable_o = (prim_instr.opcode.mode.aux_mode == MLDSA_PKDECODE); + sigdecode_h_enable_o = (prim_instr.opcode.mode.aux_mode == MLDSA_SIGDEC_H); + sigdecode_z_enable_o = (prim_instr.opcode.mode.aux_mode == MLDSA_SIGDEC_Z); + normcheck_enable[0] = (prim_instr.opcode.mode.aux_mode == MLDSA_NORMCHK); + lfsr_enable_o = (prim_instr.opcode.mode.aux_mode == MLDSA_LFSR); + end + end + MLDSA_CTRL_DONE: begin + if ((~sampler_busy_i & ~ntt_busy_i[0] & ~prim_instr.opcode.aux_en) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode inside {MLDSA_DECOMP,MLDSA_USEHINT}) & decompose_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_PWR2RND) & power2round_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_SKENCODE) & skencode_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_PKDECODE) & pkdecode_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_SIGDEC_H) & sigdecode_h_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_SIGDEC_Z) & sigdecode_z_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_NORMCHK) & normcheck_done_i) | + (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_LFSR)) ) begin + + ctrl_fsm_ns = MLDSA_CTRL_IDLE; + + end + end + default: begin + end + endcase +end + +//State flop +always_ff @(posedge clk or negedge rst_b) begin : primary_ctrl_fsm_flops + if (!rst_b) begin + ctrl_fsm_ps <= MLDSA_CTRL_IDLE; + end + else if (zeroize) begin + ctrl_fsm_ps <= MLDSA_CTRL_IDLE; + end + else begin + ctrl_fsm_ps <= ctrl_fsm_ns; + end +end + +mldsa_seq_prim mldsa_seq_prim_inst +( + .clk(clk), + + .en_i(prim_seq_en), + .addr_i(prim_prog_cntr_nxt), + .data_o(prim_instr_o) +); + + //Second sequencer for simultaneous signing operations + always_comb sign_subcomponent_busy = !(sign_ctrl_fsm_ns inside {MLDSA_CTRL_IDLE}) | + ntt_busy_i[1]; + //program counter + always_ff @(posedge clk or negedge rst_b) begin + if(!rst_b) begin + sec_prog_cntr <= MLDSA_RESET; + end + else if(zeroize) begin + sec_prog_cntr <= MLDSA_ZEROIZE; + end + else begin + if (error_flag_edge) begin + sec_prog_cntr <= MLDSA_ERROR; + end + else begin + sec_prog_cntr <= sec_prog_cntr_nxt; + end + end + end + + //subroutine decode + always_comb begin + sec_prog_cntr_nxt = MLDSA_RESET; + clear_c_valid = 0; + clear_y_valid = 0; + clear_w0_valid = 0; + set_signature_valid = 0; + signature_validity_chk_done = 0; + sec_seq_en = !zeroize; + + unique case (sec_prog_cntr) inside + MLDSA_RESET : begin + // Waiting for new valid command + unique case (cmd_reg) inside + MLDSA_KEYGEN : begin // keygen + sec_prog_cntr_nxt = MLDSA_RESET; + sec_seq_en = 0; + end + MLDSA_SIGN : begin // signing + sec_prog_cntr_nxt = MLDSA_SIGN_INIT_S; + end + MLDSA_VERIFY : begin // verifying + sec_prog_cntr_nxt = MLDSA_RESET; + sec_seq_en = 0; + end + MLDSA_KEYGEN_SIGN : begin // KEYGEN + SIGNING + sec_prog_cntr_nxt = MLDSA_RESET; + end + default : begin + sec_prog_cntr_nxt = MLDSA_RESET; + sec_seq_en = 0; + end + endcase + if (keygen_signing_process & (prim_prog_cntr == MLDSA_KG_JUMP_SIGN)) begin + sec_prog_cntr_nxt = MLDSA_SIGN_INIT_S; + sec_seq_en = 1; + end + end + MLDSA_ZEROIZE : begin + if (zeroize_mem_done) + sec_prog_cntr_nxt = MLDSA_RESET; + else + sec_prog_cntr_nxt = MLDSA_ZEROIZE; + sec_seq_en = 0; + end + //START of C access - check if C is valid + MLDSA_SIGN_CHECK_C_VLD : begin + if (c_valid) begin + set_signature_valid = 1; + sec_prog_cntr_nxt = sec_prog_cntr + 1; + end + else begin + sec_prog_cntr_nxt = sec_prog_cntr; + end + end + //END of C access - SET C valid + //Need to protect C the entire validity checks so that challenge generation doesn't overwrite the valid c~ + //FIXME another place to consider odd/even counter on challenge/validity + MLDSA_SIGN_CLEAR_C : begin + clear_c_valid = 1; + sec_prog_cntr_nxt = MLDSA_SIGN_CHECK_C_VLD; + end + //START of Y access - check if Y is valid + MLDSA_SIGN_CHECK_Y_VLD : begin + if (y_valid & w0_valid) begin + sec_prog_cntr_nxt = sec_prog_cntr + 1; + end + else begin + sec_prog_cntr_nxt = sec_prog_cntr; + end + end + //END of Y access - SET Y valid + MLDSA_SIGN_CLEAR_Y : begin + clear_y_valid = 1; + sec_prog_cntr_nxt = sec_prog_cntr + 1; + end + //START of W0 access - check if W0 is valid + MLDSA_SIGN_CHECK_W0_VLD : begin + if (w0_valid) begin + sec_prog_cntr_nxt = sec_prog_cntr + 1; + end + else begin + sec_prog_cntr_nxt = sec_prog_cntr ; + end + end + //END of W0 access - SET W0 valid + MLDSA_SIGN_CLEAR_W0 : begin + clear_w0_valid = 1; + sec_prog_cntr_nxt = sec_prog_cntr + 1; + end + MLDSA_SIGN_GEN_S : begin // end of validity checks + if (signature_valid) begin + sec_prog_cntr_nxt = MLDSA_SIGN_GEN_E; //Jump to end + end else begin + //restart + sec_prog_cntr_nxt = MLDSA_SIGN_CLEAR_C; + end + end + MLDSA_SIGN_GEN_E : begin // Successful signature generation + signature_validity_chk_done = 1; + if (signature_done) + sec_prog_cntr_nxt = MLDSA_RESET; + else + sec_prog_cntr_nxt = sec_prog_cntr; + end + default : begin + if (sign_subcomponent_busy) begin //Stalled until sub-component is done + sec_prog_cntr_nxt = sec_prog_cntr; + end + else begin + sec_prog_cntr_nxt = sec_prog_cntr + 1; + end + end + endcase + end + + //instruciton decode - drives secondary ntt + always_comb begin + ntt_mode_o[1] = MLDSA_NTT_NONE; + ntt_masking_en_o[1] = 0; + ntt_shuffling_en_o[1] = 0; + if (sec_instr.opcode.ntt_en) begin + ntt_mode_o[1] = sec_instr.opcode.mode.ntt_mode; + ntt_masking_en_o[1] = sec_instr.opcode.masking_en; + ntt_shuffling_en_o[1] = sec_instr.opcode.shuffling_en; + end + end + //passing a bit on the immediate field to mux between temp address locations + always_comb ntt_temp_address[1] = sec_instr.imm[0] ? MLDSA_TEMP3_BASE : MLDSA_TEMP0_BASE; + + //FIXME one interface here? + always_comb ntt_mem_base_addr_o[1] = '{src_base_addr:sec_instr.operand1[MLDSA_MEM_ADDR_WIDTH-1:0], + interim_base_addr:ntt_temp_address[1], + dest_base_addr:sec_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]}; + + always_comb pwo_mem_base_addr_o[1] = '{pw_base_addr_b:sec_instr.operand1[MLDSA_MEM_ADDR_WIDTH-1:0], //FIXME PWO src + pw_base_addr_a:sec_instr.operand2[MLDSA_MEM_ADDR_WIDTH-1:0], //FIXME PWO src or sampler src + pw_base_addr_c:sec_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]}; + + always_comb aux_src0_base_addr_o[1] = sec_instr.operand1[MLDSA_MEM_ADDR_WIDTH-1:0]; + always_comb aux_src1_base_addr_o[1] = sec_instr.operand2[MLDSA_MEM_ADDR_WIDTH-1:0]; + always_comb aux_dest_base_addr_o[1] = sec_instr.operand3[MLDSA_MEM_ADDR_WIDTH-1:0]; + + always_comb normcheck_mode_o = (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_NORMCHK)) ? prim_instr.imm[1:0] : + (sec_instr.opcode.aux_en & (sec_instr.opcode.mode.aux_mode == MLDSA_NORMCHK)) ? sec_instr.imm[1:0] : '0; + always_comb normcheck_src_addr_o = (prim_instr.opcode.aux_en & (prim_instr.opcode.mode.aux_mode == MLDSA_NORMCHK)) ? aux_src0_base_addr_o[0] : + (sec_instr.opcode.aux_en & (sec_instr.opcode.mode.aux_mode == MLDSA_NORMCHK)) ? aux_src0_base_addr_o[1] : '0; + always_comb normcheck_enable_o = |normcheck_enable; + +//State logic +always_comb begin : secpondary_ctrl_fsm_out_combo + sign_ctrl_fsm_ns = sign_ctrl_fsm_ps; + ntt_enable_o[1] = 0; + skdecode_enable_o = 0; + makehint_enable_o = 0; + normcheck_enable[1] = 0; + sigencode_enable_o = 0; + + unique case (sign_ctrl_fsm_ps) + MLDSA_CTRL_IDLE: begin + //Start function + if (sec_instr.opcode.sampler_en) + sign_ctrl_fsm_ns = MLDSA_CTRL_ERROR; + if (sec_instr.opcode.ntt_en | sec_instr.opcode.aux_en) + sign_ctrl_fsm_ns = MLDSA_CTRL_FUNC_START; + end + MLDSA_CTRL_FUNC_START: begin + sign_ctrl_fsm_ns = MLDSA_CTRL_DONE; + ntt_enable_o[1] = sec_instr.opcode.ntt_en; + if (sec_instr.opcode.aux_en) begin + skdecode_enable_o = (sec_instr.opcode.mode.aux_mode == MLDSA_SKDECODE); + makehint_enable_o = (sec_instr.opcode.mode.aux_mode == MLDSA_MAKEHINT); + normcheck_enable[1] = (sec_instr.opcode.mode.aux_mode == MLDSA_NORMCHK); + sigencode_enable_o = (sec_instr.opcode.mode.aux_mode == MLDSA_SIGENC); + end + end + MLDSA_CTRL_DONE: begin + if ((sec_instr.opcode.ntt_en & ~ntt_busy_i[1]) | + (sec_instr.opcode.aux_en & (sec_instr.opcode.mode.aux_mode == MLDSA_SKDECODE) & skdecode_done_i) | + (sec_instr.opcode.aux_en & (sec_instr.opcode.mode.aux_mode == MLDSA_MAKEHINT) & makehint_done_i) | + (sec_instr.opcode.aux_en & (sec_instr.opcode.mode.aux_mode == MLDSA_NORMCHK) & normcheck_done_i) | + (sec_instr.opcode.aux_en & (sec_instr.opcode.mode.aux_mode == MLDSA_SIGENC) & sigencode_done_i) ) begin + sign_ctrl_fsm_ns = MLDSA_CTRL_IDLE; + end + end + default: begin + end + endcase +end + +//State flop +always_ff @(posedge clk or negedge rst_b) begin : secondary_ctrl_fsm_flops + if (!rst_b) begin + sign_ctrl_fsm_ps <= MLDSA_CTRL_IDLE; + end + else if (zeroize) begin + sign_ctrl_fsm_ps <= MLDSA_CTRL_IDLE; + end + else begin + sign_ctrl_fsm_ps <= sign_ctrl_fsm_ns; + end +end + +mldsa_seq_sec mldsa_seq_sec_inst +( + .clk(clk), + + .en_i(sec_seq_en), + .addr_i(sec_prog_cntr_nxt), + .data_o(sec_instr_o) +); + +always_comb prim_instr = ((prim_prog_cntr == MLDSA_ZEROIZE) | (prim_prog_cntr == MLDSA_RESET))? '0 : prim_instr_o; +always_comb sec_instr = ((sec_prog_cntr == MLDSA_ZEROIZE) | (sec_prog_cntr == MLDSA_RESET))? '0 : sec_instr_o; + +always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + zeroize_mem_addr <= 0; + zeroize_mem_done <= 0; + end + else if (zeroize) begin + zeroize_mem_addr <= 0; + zeroize_mem_done <= 0; + end + else if (prim_prog_cntr == MLDSA_ZEROIZE) begin + if (zeroize_mem_addr == MLDSA_MEM_MAX_DEPTH) begin + zeroize_mem_addr <= 0; + zeroize_mem_done <= 1; + end else begin + zeroize_mem_addr <= zeroize_mem_addr + 1; + end + end else begin + zeroize_mem_addr <= 0; + zeroize_mem_done <= 0; + end +end + +always_comb zeroize_mem_we = (prim_prog_cntr == MLDSA_ZEROIZE); + +always_comb zeroize_mem_o.rd_wr_en = zeroize_mem_we? RW_WRITE : RW_IDLE; +always_comb zeroize_mem_o.addr = zeroize_mem_addr; + +`ifdef RV_FPGA_SCA + //=========================================================================== + // + // ************** TRIGER Functionality ************** + // + //=========================================================================== + logic NTT_raw_signal, PWM_raw_signal, PWA_raw_signal, INTT_raw_signal; + gen_pulse_custom NTT_pulse + ( + .clk(clk), + .reset_n(rst_b), + .raw_signal(NTT_raw_signal), + .trigger_pulse(NTT_trigger) + ); + + gen_pulse_custom PWM_pulse + ( + .clk(clk), + .reset_n(rst_b), + .raw_signal(PWM_raw_signal), + .trigger_pulse(PWM_trigger) + ); + + gen_pulse_custom PWA_pulse + ( + .clk(clk), + .reset_n(rst_b), + .raw_signal(PWA_raw_signal), + .trigger_pulse(PWA_trigger) + ); + + gen_pulse_custom INTT_pulse + ( + .clk(clk), + .reset_n(rst_b), + .raw_signal(INTT_raw_signal), + .trigger_pulse(INTT_trigger) + ); + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + NTT_raw_signal <= 'h0; + PWM_raw_signal <= 'h0; + PWA_raw_signal <= 'h0; + INTT_raw_signal <= 'h0; + end + else if (zeroize) begin + NTT_raw_signal <= 'h0; + PWM_raw_signal <= 'h0; + PWA_raw_signal <= 'h0; + INTT_raw_signal <= 'h0; + end + else begin + if (sec_seq_en) begin + unique case(sec_prog_cntr_nxt) + MLDSA_SIGN_VALID_S : begin //NTT(C) + NTT_raw_signal <= 'h1; + PWM_raw_signal <= 'h0; + PWA_raw_signal <= 'h0; + INTT_raw_signal <= 'h0; + end + MLDSA_SIGN_VALID_S+2 : begin + NTT_raw_signal <= 'h0; + PWM_raw_signal <= 'h1; + PWA_raw_signal <= 'h0; + INTT_raw_signal <= 'h0; + end + MLDSA_SIGN_VALID_S+4 : begin + NTT_raw_signal <= 'h0; + PWM_raw_signal <= 'h0; + PWA_raw_signal <= 'h1; + INTT_raw_signal <= 'h0; + end + MLDSA_SIGN_VALID_S+3 : begin + NTT_raw_signal <= 'h0; + PWM_raw_signal <= 'h0; + PWA_raw_signal <= 'h0; + INTT_raw_signal <= 'h1; + end + default : begin + NTT_raw_signal <= 'h0; + PWM_raw_signal <= 'h0; + PWA_raw_signal <= 'h0; + INTT_raw_signal <= 'h0; + end + endcase + end + end + end +`endif + + `ABR_ASSERT_KNOWN(ERR_CTRL_FSM_X, {ctrl_fsm_ps}, clk, !rst_b) + `ABR_ASSERT_KNOWN(ERR_SIGN_CTRL_FSM_X, {sign_ctrl_fsm_ps}, clk, !rst_b) + `ABR_ASSERT_KNOWN(ERR_NTT_MEM_X, {ntt_mem_base_addr_o}, clk, !rst_b) + `ABR_ASSERT_KNOWN(ERR_PWO_MEM_X, {pwo_mem_base_addr_o}, clk, !rst_b) + `ABR_ASSERT_KNOWN(ERR_REG_HWIF_X, {mldsa_reg_hwif_in_o}, clk, !rst_b) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_ctrl_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_ctrl_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..f1592423588dd8bf97bd7a128b2371d9e952a00e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_ctrl_pkg.sv @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// mldsa_seq_pkg.sv +// -------- +// MLDSA instructions for MLDSA. +// +// +//====================================================================== + +`ifndef MLDSA_CTRL_PKG +`define MLDSA_CTRL_PKG + +package mldsa_ctrl_pkg; + import mldsa_params_pkg::*; + import mldsa_sampler_pkg::*; + + localparam integer MLDSA_OPR_WIDTH = 15; + localparam integer MLDSA_IMM_WIDTH = 16; + localparam MLDSA_PROG_ADDR_W = 9; + + localparam SEED_NUM_DWORDS = 8; + localparam MSG_NUM_DWORDS = 16; + localparam MU_NUM_DWORDS = 16; + localparam PRIVKEY_NUM_DWORDS = 1224; + localparam PRIVKEY_REG_NUM_DWORDS = 32; + localparam PRIVKEY_REG_RHO_NUM_DWORDS = 8; + localparam PRIVKEY_MEM_NUM_DWORDS = PRIVKEY_NUM_DWORDS - PRIVKEY_REG_NUM_DWORDS; + localparam SIGN_RND_NUM_DWORDS = 8; + localparam PUBKEY_NUM_DWORDS = 648; + localparam PUBKEY_NUM_BYTES = PUBKEY_NUM_DWORDS * 4; + localparam SIGNATURE_H_NUM_DWORDS = 21; + localparam SIGNATURE_H_VALID_NUM_BYTES = 83; + localparam SIGNATURE_Z_NUM_DWORDS = 1120; + localparam SIGNATURE_C_NUM_DWORDS = 16; + localparam SIGNATURE_NUM_DWORDS = SIGNATURE_H_NUM_DWORDS + SIGNATURE_Z_NUM_DWORDS + SIGNATURE_C_NUM_DWORDS; + localparam SIGNATURE_REG_NUM_DWORDS = SIGNATURE_H_NUM_DWORDS + SIGNATURE_C_NUM_DWORDS; + localparam VERIFY_RES_NUM_DWORDS = 16; + localparam ENTROPY_NUM_DWORDS = 16; + + localparam T1_NUM_COEFF = 2048; + localparam T1_COEFF_W = 10; + + localparam RND_W = 236; //5*46 + 6 + localparam LFSR_W = RND_W / 2; + + localparam SK_MEM_DEPTH = 1192; + localparam SK_MEM_BANK_DEPTH = SK_MEM_DEPTH/2; + localparam SK_MEM_BANK_ADDR_W = $clog2(SK_MEM_BANK_DEPTH); + localparam SK_MEM_BANK_DATA_W = DATA_WIDTH; + + localparam SIG_Z_MEM_DATA_W = 160; + localparam SIG_Z_MEM_NUM_DWORD = SIG_Z_MEM_DATA_W/32; + localparam SIG_Z_MEM_WSTROBE_W = SIG_Z_MEM_DATA_W/8; + localparam SIG_Z_MEM_DEPTH = (SIGNATURE_Z_NUM_DWORDS*32)/SIG_Z_MEM_DATA_W; + localparam SIG_ADDR_W = $clog2(SIGNATURE_NUM_DWORDS); + localparam SIG_Z_MEM_ADDR_W = $clog2(SIG_Z_MEM_DEPTH); + localparam SIG_Z_MEM_OFFSET_W = $clog2(SIG_Z_MEM_DATA_W/32); + localparam SIG_H_REG_ADDR_W = $clog2(SIGNATURE_H_NUM_DWORDS); + localparam SIG_C_REG_ADDR_W = $clog2(SIGNATURE_C_NUM_DWORDS); + + localparam PK_MEM_DEPTH = 64; + localparam PK_MEM_DATA_W = 320; + localparam PK_MEM_NUM_DWORDS = (PK_MEM_DATA_W)/32; + localparam PK_MEM_WSTROBE_W = PK_MEM_DATA_W/8; + localparam PK_ADDR_W = $clog2(PUBKEY_NUM_DWORDS); + localparam PK_MEM_ADDR_W = $clog2(PK_MEM_DEPTH); + localparam PK_MEM_OFFSET_W = $clog2(PK_MEM_DATA_W/32); + localparam PK_RHO_REG_ADDR_W = $clog2(PRIVKEY_REG_RHO_NUM_DWORDS); + + typedef struct packed { + logic [7:0][63:0] tr; + logic [3:0][63:0] K; + logic [3:0][63:0] rho; + } mldsa_privkey_t; + + typedef union packed { + mldsa_privkey_t enc; + logic [PRIVKEY_REG_NUM_DWORDS-1:0][31:0] raw; + } mldsa_privkey_u; + + typedef struct packed { + logic [SIG_Z_MEM_ADDR_W-1:0] addr; + logic [SIG_Z_MEM_OFFSET_W-1:0] offset; + } mldsa_signature_z_addr_t; + + typedef struct packed { + logic [SIGNATURE_H_NUM_DWORDS-1:0][31:0] h; + logic [SIGNATURE_C_NUM_DWORDS-1:0][31:0] c; + } mldsa_signature_t; + + typedef union packed { + mldsa_signature_t enc; + logic [SIGNATURE_REG_NUM_DWORDS-1:0][31:0] raw; + } mldsa_signature_u; + + typedef struct packed { + logic [PK_MEM_ADDR_W-1:0] addr; + logic [PK_MEM_OFFSET_W-1:0] offset; + } mldsa_pubkey_mem_addr_t; + + typedef struct packed { + logic [7:0][31:0] rho; + } mldsa_pubkey_t; + + typedef union packed { + mldsa_pubkey_t enc; + logic [7:0][31:0] raw; + } mldsa_pubkey_u; + + //FSM Controller for driving sampler + typedef enum logic [2:0] { + MLDSA_CTRL_IDLE, + MLDSA_CTRL_SHA3_START, + MLDSA_CTRL_MSG_START, + MLDSA_CTRL_MSG_LOAD, + MLDSA_CTRL_MSG_WAIT, + MLDSA_CTRL_FUNC_START, + MLDSA_CTRL_DONE, + MLDSA_CTRL_ERROR + } mldsa_ctrl_fsm_state_e; + + typedef enum logic[3:0] { + MLDSA_NTT_NONE, + MLDSA_NTT, + MLDSA_INTT, + MLDSA_PWM, + MLDSA_PWM_ACCUM, + MLDSA_PWM_SMPL, + MLDSA_PWM_ACCUM_SMPL, + MLDSA_PWA, + MLDSA_PWS, + MLDSA_PWM_INTT + } mldsa_ntt_mode_e; + + typedef enum logic[3:0] { + MLDSA_AUX_NONE, + MLDSA_SKDECODE, + MLDSA_SKENCODE, + MLDSA_PKDECODE, + MLDSA_MAKEHINT, + MLDSA_USEHINT, + MLDSA_NORMCHK, + MLDSA_PWR2RND, + MLDSA_SIGENC, + MLDSA_SIGDEC_H, + MLDSA_SIGDEC_Z, + MLDSA_HINTSUM, + MLDSA_DECOMP, + MLDSA_LFSR + } mldsa_aux_mode_e; + + + typedef union packed { + mldsa_sampler_mode_e sampler_mode; + mldsa_aux_mode_e aux_mode; + mldsa_ntt_mode_e ntt_mode; + } mldsa_opcode_mode_u; + + typedef struct packed { + logic keccak_en; + logic sampler_en; + logic ntt_en; + logic aux_en; + mldsa_opcode_mode_u mode; + logic masking_en; + logic shuffling_en; + } mldsa_opcode_t; + + typedef struct packed { + mldsa_opcode_t opcode; + logic [MLDSA_IMM_WIDTH-1 : 0] imm; + logic [MLDSA_OPR_WIDTH-1 : 0] length; + logic [MLDSA_OPR_WIDTH-1 : 0] operand1; + logic [MLDSA_OPR_WIDTH-1 : 0] operand2; + logic [MLDSA_OPR_WIDTH-1 : 0] operand3; + } mldsa_seq_instr_t; + + // MLDSA ISA + localparam mldsa_opcode_t MLDSA_UOP_NOP = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SAMPLER_NONE, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SHAKE256 = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SHAKE256, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SHAKE128 = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SHAKE128, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_REJB = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_REJ_BOUNDED, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_REJS_PWM = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWM_SMPL, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_REJS_PWMA = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWM_ACCUM_SMPL, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SIB = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SAMPLE_IN_BALL, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_EXP_MASK = '{keccak_en: 1'b1, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_EXP_MASK, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_NTT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_NTT, masking_en:1'b0, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_INTT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_INTT, masking_en:1'b0, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_PWM = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWM, masking_en:1'b0, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_PWA = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWA, masking_en:1'b0, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_PWS = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWS, masking_en:1'b0, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_MASKED_NTT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_NTT, masking_en:1'b1, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_MASKED_INTT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_INTT, masking_en:1'b1, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_MASKED_PWM = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWM, masking_en:1'b1, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_MASKED_PWA = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWA, masking_en:1'b1, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_MASKED_PWS = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWS, masking_en:1'b1, shuffling_en:1'b1}; + localparam mldsa_opcode_t MLDSA_UOP_MASKED_PWM_INTT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b1, aux_en: 1'b0, mode:MLDSA_PWM_INTT,masking_en:1'b1, shuffling_en:1'b1}; + //Load Keccak with data but don't run it yet + localparam mldsa_opcode_t MLDSA_UOP_LD_SHAKE256 = '{keccak_en: 1'b1, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SHAKE256, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_LD_SHAKE128 = '{keccak_en: 1'b1, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SHAKE128, masking_en:1'b0, shuffling_en:1'b0}; + //Run Keccak but don't load it + localparam mldsa_opcode_t MLDSA_UOP_RUN_SHAKE256 = '{keccak_en: 1'b0, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SHAKE256, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_RUN_SHAKE128 = '{keccak_en: 1'b0, sampler_en:1'b1, ntt_en:1'b0, aux_en: 1'b0, mode:MLDSA_SHAKE128, masking_en:1'b0, shuffling_en:1'b0}; + // Aux functions + localparam mldsa_opcode_t MLDSA_UOP_DECOMP = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_DECOMP, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SKDECODE = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_SKDECODE, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SKENCODE = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_SKENCODE, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_MAKEHINT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_MAKEHINT, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_NORMCHK = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_NORMCHK, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SIGENCODE = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_SIGENC, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_PKDECODE = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_PKDECODE, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SIGDEC_H = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_SIGDEC_H, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_SIGDEC_Z = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_SIGDEC_Z, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_HINTSUM = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_HINTSUM, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_USEHINT = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_USEHINT, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_PWR2RND = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_PWR2RND, masking_en:1'b0, shuffling_en:1'b0}; + localparam mldsa_opcode_t MLDSA_UOP_LFSR = '{keccak_en: 1'b0, sampler_en:1'b0, ntt_en:1'b0, aux_en: 1'b1, mode:MLDSA_LFSR, masking_en:1'b0, shuffling_en:1'b0}; + + //Immediate encodings + localparam [MLDSA_IMM_WIDTH-1:0] MLDSA_NORMCHK_Z = 'h0000; + localparam [MLDSA_IMM_WIDTH-1:0] MLDSA_NORMCHK_R0 = 'h0001; + localparam [MLDSA_IMM_WIDTH-1:0] MLDSA_NORMCHK_CT0 = 'h0002; + + + // MLDSA REGISTERS ID listing + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_NOP = 'd0; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CONST_ZERO_ID = 'd0; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CONST_ONE_ID = 'd1; + + // DEST register IDs + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_K_RHO_REG_ID = 'd2; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_MU_REG_ID = 'd3; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_RHO_P_REG_ID = 'd4; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_SIG_C_REG_ID = 'd5; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_TR_REG_ID = 'd6; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_VERIFY_RES_REG_ID = 'd7; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_DEST_LFSR_SEED_REG_ID = 'd8; + + //SRC register IDs + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_MSG_ID = 'd15; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_SEED_ID = 'd16; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_SIGN_RND_ID = 'd17; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_K_ID = 'd18; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_RHO_ID = 'd19; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_RHO_P_ID = 'd20; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_MU_ID = 'd21; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_TR_ID = 'd22; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_RHO_P_KAPPA_ID = 'd23; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_SIG_C_REG_ID = 'd24; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_PK_REG_ID = 'd25; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_ENTROPY_ID = 'd26; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CNT_ID = 'd27; + + //SK offsets in dwords + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_SK_S1_OFFSET = 'd32; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_SK_T0_OFFSET = 'd360; + + // MLDSA MEMORY LOCATIONS + //COEFF DEPTH is 256/4 + localparam MLDSA_COEFF_DEPTH = MLDSA_N/COEFF_PER_CLK; + //MEMORY INST 0 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_INST0_BASE = 0 << (MLDSA_MEM_ADDR_WIDTH-3); + //S1 / NTT(S1) + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_0_BASE = MLDSA_INST0_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_1_BASE = MLDSA_S1_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_2_BASE = MLDSA_S1_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_3_BASE = MLDSA_S1_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_4_BASE = MLDSA_S1_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_5_BASE = MLDSA_S1_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_6_BASE = MLDSA_S1_5_BASE + MLDSA_COEFF_DEPTH; + // z for VERIFY + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_0_BASE = MLDSA_INST0_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_1_BASE = MLDSA_Z_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_2_BASE = MLDSA_Z_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_3_BASE = MLDSA_Z_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_4_BASE = MLDSA_Z_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_5_BASE = MLDSA_Z_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_6_BASE = MLDSA_Z_5_BASE + MLDSA_COEFF_DEPTH; + // z NTT for VERIFY + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_0_BASE = MLDSA_INST0_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_1_BASE = MLDSA_Z_NTT_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_2_BASE = MLDSA_Z_NTT_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_3_BASE = MLDSA_Z_NTT_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_4_BASE = MLDSA_Z_NTT_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_5_BASE = MLDSA_Z_NTT_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_NTT_6_BASE = MLDSA_Z_NTT_5_BASE + MLDSA_COEFF_DEPTH; + //s2 / NTT(s2) + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_0_BASE = MLDSA_S1_6_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_1_BASE = MLDSA_S2_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_2_BASE = MLDSA_S2_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_3_BASE = MLDSA_S2_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_4_BASE = MLDSA_S2_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_5_BASE = MLDSA_S2_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_6_BASE = MLDSA_S2_5_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S2_7_BASE = MLDSA_S2_6_BASE + MLDSA_COEFF_DEPTH; + //t0 / NTT(t0) t1 / NTT(t1) + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T0_BASE = MLDSA_S2_7_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T1_BASE = MLDSA_T0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T2_BASE = MLDSA_T1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T3_BASE = MLDSA_T2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T4_BASE = MLDSA_T3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T5_BASE = MLDSA_T4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T6_BASE = MLDSA_T5_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_T7_BASE = MLDSA_T6_BASE + MLDSA_COEFF_DEPTH; + //c.s1 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CS1_BASE = MLDSA_T7_BASE + MLDSA_COEFF_DEPTH; + // z + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Z_BASE = MLDSA_T7_BASE + MLDSA_COEFF_DEPTH; + // CT for VERIFY + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_BASE = MLDSA_T7_BASE + MLDSA_COEFF_DEPTH; + //c.s2 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CS2_BASE = MLDSA_CS1_BASE + MLDSA_COEFF_DEPTH; + // R0 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_R0_BASE = MLDSA_CS1_BASE + MLDSA_COEFF_DEPTH; + //TEMP storage for NTT ops + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_TEMP0_BASE = MLDSA_CS2_BASE + MLDSA_COEFF_DEPTH; + + //MEMORY INST 1 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_INST1_BASE = 1 << (MLDSA_MEM_ADDR_WIDTH-3); + // NTT(C) + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_C_NTT_BASE = MLDSA_INST1_BASE; + // NTT(s1) for KEYGEN + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_0_NTT_BASE = MLDSA_C_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_1_NTT_BASE = MLDSA_S1_0_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_2_NTT_BASE = MLDSA_S1_1_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_3_NTT_BASE = MLDSA_S1_2_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_4_NTT_BASE = MLDSA_S1_3_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_5_NTT_BASE = MLDSA_S1_4_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_S1_6_NTT_BASE = MLDSA_S1_5_NTT_BASE + MLDSA_COEFF_DEPTH; + // c.t0 for SIGNING + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_0_BASE = MLDSA_C_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_1_BASE = MLDSA_CT_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_2_BASE = MLDSA_CT_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_3_BASE = MLDSA_CT_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_4_BASE = MLDSA_CT_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_5_BASE = MLDSA_CT_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_6_BASE = MLDSA_CT_5_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_CT_7_BASE = MLDSA_CT_6_BASE + MLDSA_COEFF_DEPTH; + //hint_r + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_0_BASE = MLDSA_C_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_1_BASE = MLDSA_HINT_R_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_2_BASE = MLDSA_HINT_R_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_3_BASE = MLDSA_HINT_R_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_4_BASE = MLDSA_HINT_R_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_5_BASE = MLDSA_HINT_R_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_6_BASE = MLDSA_HINT_R_5_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_HINT_R_7_BASE = MLDSA_HINT_R_6_BASE + MLDSA_COEFF_DEPTH; + + //MEMORY INST 2 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_INST2_BASE = 2 << (MLDSA_MEM_ADDR_WIDTH-3); + //Y + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_0_BASE = MLDSA_INST2_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_1_BASE = MLDSA_Y_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_2_BASE = MLDSA_Y_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_3_BASE = MLDSA_Y_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_4_BASE = MLDSA_Y_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_5_BASE = MLDSA_Y_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_6_BASE = MLDSA_Y_5_BASE + MLDSA_COEFF_DEPTH; + //NTT(Y) + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_0_NTT_BASE = MLDSA_Y_6_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_1_NTT_BASE = MLDSA_Y_0_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_2_NTT_BASE = MLDSA_Y_1_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_3_NTT_BASE = MLDSA_Y_2_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_4_NTT_BASE = MLDSA_Y_3_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_5_NTT_BASE = MLDSA_Y_4_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_Y_6_NTT_BASE = MLDSA_Y_5_NTT_BASE + MLDSA_COEFF_DEPTH; + //W0 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_0_BASE = MLDSA_Y_6_NTT_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_1_BASE = MLDSA_W0_0_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_2_BASE = MLDSA_W0_1_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_3_BASE = MLDSA_W0_2_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_4_BASE = MLDSA_W0_3_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_5_BASE = MLDSA_W0_4_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_6_BASE = MLDSA_W0_5_BASE + MLDSA_COEFF_DEPTH; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_W0_7_BASE = MLDSA_W0_6_BASE + MLDSA_COEFF_DEPTH; + + //MEMORY INST 3 + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_INST3_BASE = 3 << (MLDSA_MEM_ADDR_WIDTH-3); + + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_AS0_BASE = MLDSA_INST3_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_AS0_INTT_BASE = MLDSA_AS0_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_AY0_BASE = MLDSA_INST3_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_AZ0_BASE = MLDSA_INST3_BASE; + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_TEMP3_BASE = MLDSA_INST3_BASE + MLDSA_COEFF_DEPTH; + + //SIB MEMORY + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_INST4_BASE = 4 << (MLDSA_MEM_ADDR_WIDTH-3); + //C + localparam [MLDSA_OPR_WIDTH-1 : 0] MLDSA_C_BASE = MLDSA_INST4_BASE; + + // MLDSA Subroutine listing + //KG + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_RESET = 'd0; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_ZEROIZE = MLDSA_RESET + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_KG_S = MLDSA_ZEROIZE + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_KG_JUMP_SIGN = MLDSA_KG_S + 101; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_KG_E = MLDSA_KG_JUMP_SIGN + 1; + //Signing + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_S = MLDSA_KG_E + 2; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_MODE = MLDSA_SIGN_S + 3; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_H_MU = MLDSA_SIGN_CHECK_MODE + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_H_RHO_P = MLDSA_SIGN_H_MU + 2; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_Y_CLR = MLDSA_SIGN_H_RHO_P + 3; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_LFSR_S = MLDSA_SIGN_CHECK_Y_CLR + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_MAKE_Y_S = MLDSA_SIGN_LFSR_S + 3; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_W0_CLR = MLDSA_SIGN_MAKE_Y_S+ 14; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_MAKE_W_S = MLDSA_SIGN_CHECK_W0_CLR+ 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_SET_Y = MLDSA_SIGN_MAKE_W_S+ 64; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_MAKE_W = MLDSA_SIGN_MAKE_W_S+ 66; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_SET_W0 = MLDSA_SIGN_MAKE_W+ 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_C_CLR = MLDSA_SIGN_SET_W0+ 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_MAKE_C = MLDSA_SIGN_CHECK_C_CLR+ 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_SET_C = MLDSA_SIGN_MAKE_C+ 2; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHL_E = MLDSA_SIGN_SET_C + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_E = MLDSA_SIGN_CHL_E + 1; + //Verify + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_S = MLDSA_SIGN_E + 2; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_H_TR = MLDSA_VERIFY_S + 9; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_CHECK_MODE = MLDSA_VERIFY_H_TR + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_H_MU = MLDSA_VERIFY_CHECK_MODE + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_MAKE_C = MLDSA_VERIFY_H_MU + 2; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_NTT_C = MLDSA_VERIFY_MAKE_C + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_NTT_T1 = MLDSA_VERIFY_NTT_C + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_NTT_Z = MLDSA_VERIFY_NTT_T1 + 8; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_EXP_A = MLDSA_VERIFY_NTT_Z + 7; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_RES = MLDSA_VERIFY_EXP_A + 80; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_VERIFY_E = MLDSA_VERIFY_RES + 4; + + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_ERROR = '1; + + //Signing Sequencer Subroutine listing + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_INIT_S = MLDSA_ZEROIZE + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_C_VLD = MLDSA_SIGN_INIT_S + 24; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_VALID_S = MLDSA_SIGN_CHECK_C_VLD + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_Y_VLD = MLDSA_SIGN_VALID_S + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CLEAR_Y = MLDSA_SIGN_VALID_S + 30; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CHECK_W0_VLD = MLDSA_SIGN_VALID_S + 39; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CLEAR_W0 = MLDSA_SIGN_VALID_S + 80; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_GEN_S = MLDSA_SIGN_VALID_S + 82; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_CLEAR_C = MLDSA_SIGN_GEN_S + 1; + localparam [MLDSA_PROG_ADDR_W-1 : 0] MLDSA_SIGN_GEN_E = MLDSA_SIGN_GEN_S + 2; + + +endpackage + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_mem_if.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_mem_if.sv new file mode 100644 index 0000000000000000000000000000000000000000..dd22fe2b485c5e7e7f8bc7f8b49b4f439a0a0399 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_mem_if.sv @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Description: +// Signals for SRAM interfaces needed for mldsa +// + +import mldsa_params_pkg::*; +import mldsa_ctrl_pkg::*; + +`define MLDSA_MEM_IF_SIGNALS(_PARAM_PREFIX, _signal_prefix)\ +logic ``_signal_prefix``_we_i;\ +logic [``_PARAM_PREFIX``_ADDR_W-1:0] ``_signal_prefix``_waddr_i;\ +logic [``_PARAM_PREFIX``_DATA_W-1:0] ``_signal_prefix``_wdata_i;\ +logic ``_signal_prefix``_re_i;\ +logic [``_PARAM_PREFIX``_ADDR_W-1:0] ``_signal_prefix``_raddr_i;\ +logic [``_PARAM_PREFIX``_DATA_W-1:0] ``_signal_prefix``_rdata_o; + +`define MLDSA_MEM_BE_IF_SIGNALS(_PARAM_PREFIX, _signal_prefix)\ +logic ``_signal_prefix``_we_i;\ +logic [``_PARAM_PREFIX``_ADDR_W-1:0] ``_signal_prefix``_waddr_i;\ +logic [``_PARAM_PREFIX``_DATA_W-1:0] ``_signal_prefix``_wdata_i;\ +logic [``_PARAM_PREFIX``_WSTROBE_W-1:0] ``_signal_prefix``_wstrobe_i;\ +logic ``_signal_prefix``_re_i;\ +logic [``_PARAM_PREFIX``_ADDR_W-1:0] ``_signal_prefix``_raddr_i;\ +logic [``_PARAM_PREFIX``_DATA_W-1:0] ``_signal_prefix``_rdata_o; + +`define MLDSA_MEM_IF_REQ_PORTS(_signal_prefix)\ + output ``_signal_prefix``_we_i, ``_signal_prefix``_waddr_i, ``_signal_prefix``_wdata_i, ``_signal_prefix``_re_i, ``_signal_prefix``_raddr_i,\ + input ``_signal_prefix``_rdata_o + +`define MLDSA_MEM_BE_IF_REQ_PORTS(_signal_prefix)\ + output ``_signal_prefix``_we_i, ``_signal_prefix``_waddr_i, ``_signal_prefix``_wdata_i, ``_signal_prefix``_wstrobe_i, ``_signal_prefix``_re_i, ``_signal_prefix``_raddr_i,\ + input ``_signal_prefix``_rdata_o + +`define MLDSA_MEM_IF_RESP_PORTS(_signal_prefix)\ + input ``_signal_prefix``_we_i, ``_signal_prefix``_waddr_i, ``_signal_prefix``_wdata_i, ``_signal_prefix``_re_i, ``_signal_prefix``_raddr_i,\ + output ``_signal_prefix``_rdata_o + +`define MLDSA_MEM_BE_IF_RESP_PORTS(_signal_prefix)\ + input ``_signal_prefix``_we_i, ``_signal_prefix``_waddr_i, ``_signal_prefix``_wdata_i, ``_signal_prefix``_wstrobe_i, ``_signal_prefix``_re_i, ``_signal_prefix``_raddr_i,\ + output ``_signal_prefix``_rdata_o + +interface mldsa_mem_if; + + `MLDSA_MEM_IF_SIGNALS(MLDSA_MEM_W1, w1_mem) + `MLDSA_MEM_IF_SIGNALS(MLDSA_MEM_INST0, mem_inst0_bank0) + `MLDSA_MEM_IF_SIGNALS(MLDSA_MEM_INST0, mem_inst0_bank1) + `MLDSA_MEM_IF_SIGNALS(MLDSA_MEM_INST1, mem_inst1) + `MLDSA_MEM_IF_SIGNALS(MLDSA_MEM_INST2, mem_inst2) + `MLDSA_MEM_IF_SIGNALS(MLDSA_MEM_INST3, mem_inst3) + `MLDSA_MEM_IF_SIGNALS(SK_MEM_BANK, sk_mem_bank0) + `MLDSA_MEM_IF_SIGNALS(SK_MEM_BANK, sk_mem_bank1) + `MLDSA_MEM_BE_IF_SIGNALS(SIG_Z_MEM, sig_z_mem) + `MLDSA_MEM_BE_IF_SIGNALS(PK_MEM, pk_mem) + + modport req ( + `MLDSA_MEM_IF_REQ_PORTS(w1_mem), + `MLDSA_MEM_IF_REQ_PORTS(mem_inst0_bank0), + `MLDSA_MEM_IF_REQ_PORTS(mem_inst0_bank1), + `MLDSA_MEM_IF_REQ_PORTS(mem_inst1), + `MLDSA_MEM_IF_REQ_PORTS(mem_inst2), + `MLDSA_MEM_IF_REQ_PORTS(mem_inst3), + `MLDSA_MEM_IF_REQ_PORTS(sk_mem_bank0), + `MLDSA_MEM_IF_REQ_PORTS(sk_mem_bank1), + `MLDSA_MEM_BE_IF_REQ_PORTS(sig_z_mem), + `MLDSA_MEM_BE_IF_REQ_PORTS(pk_mem) + ); + + modport resp ( + `MLDSA_MEM_IF_RESP_PORTS(w1_mem), + `MLDSA_MEM_IF_RESP_PORTS(mem_inst0_bank0), + `MLDSA_MEM_IF_RESP_PORTS(mem_inst0_bank1), + `MLDSA_MEM_IF_RESP_PORTS(mem_inst1), + `MLDSA_MEM_IF_RESP_PORTS(mem_inst2), + `MLDSA_MEM_IF_RESP_PORTS(mem_inst3), + `MLDSA_MEM_IF_RESP_PORTS(sk_mem_bank0), + `MLDSA_MEM_IF_RESP_PORTS(sk_mem_bank1), + `MLDSA_MEM_BE_IF_RESP_PORTS(sig_z_mem), + `MLDSA_MEM_BE_IF_RESP_PORTS(pk_mem) + ); + +endinterface + +interface mldsa_sram_if #(parameter integer ADDR_W = 16, parameter integer DATA_W = 32); + +logic we_i; +logic [ADDR_W-1:0] waddr_i; +logic [DATA_W-1:0] wdata_i; +logic re_i; +logic [ADDR_W-1:0] raddr_i; +logic [DATA_W-1:0] rdata_o; + + modport req ( + output we_i, waddr_i, wdata_i, re_i, raddr_i, + input rdata_o + ); + + modport resp ( + input we_i, waddr_i, wdata_i, re_i, raddr_i, + output rdata_o + ); + +endinterface + +interface mldsa_sram_be_if #(parameter integer ADDR_W = 16, parameter integer DATA_W = 32); + + logic we_i; + logic [ADDR_W-1:0] waddr_i; + logic [DATA_W-1:0] wdata_i; + logic [DATA_W/8-1:0] wstrobe_i; + logic re_i; + logic [ADDR_W-1:0] raddr_i; + logic [DATA_W-1:0] rdata_o; + + modport req ( + output we_i, waddr_i, wdata_i, wstrobe_i, re_i, raddr_i, + input rdata_o + ); + + modport resp ( + input we_i, waddr_i, wdata_i, re_i, raddr_i, + output rdata_o + ); + + endinterface \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_mem_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_mem_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..962dbd5bb030969b306f2d53ee545185f9f146e5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_mem_top.sv @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2019 Western Digital Corporation or its affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +`include "mldsa_config_defines.svh" +module mldsa_mem_top + import mldsa_params_pkg::*; + import mldsa_ctrl_pkg::*; +( + input logic clk_i, + mldsa_mem_if.resp mldsa_memory_export +); + +`ABR_MEM(MLDSA_MEM_W1_DEPTH,MLDSA_MEM_W1_DATA_W,w1_mem) +`ABR_MEM(MLDSA_MEM_INST0_DEPTH,MLDSA_MEM_DATA_WIDTH,mem_inst0_bank0) +`ABR_MEM(MLDSA_MEM_INST0_DEPTH,MLDSA_MEM_DATA_WIDTH,mem_inst0_bank1) +`ABR_MEM(MLDSA_MEM_INST1_DEPTH,MLDSA_MEM_DATA_WIDTH,mem_inst1) +`ABR_MEM(MLDSA_MEM_INST2_DEPTH,MLDSA_MEM_DATA_WIDTH,mem_inst2) +`ABR_MEM(MLDSA_MEM_INST3_DEPTH,MLDSA_MEM_DATA_WIDTH,mem_inst3) +`ABR_MEM(SK_MEM_BANK_DEPTH,SK_MEM_BANK_DATA_W,sk_mem_bank0) +`ABR_MEM(SK_MEM_BANK_DEPTH,SK_MEM_BANK_DATA_W,sk_mem_bank1) +`ABR_MEM_BE(SIG_Z_MEM_DEPTH,SIG_Z_MEM_DATA_W,sig_z_mem) +`ABR_MEM_BE(PK_MEM_DEPTH,PK_MEM_DATA_W,pk_mem) + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_params_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_params_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..ff0e63e4017b29dedb0b3dd01fd5be0b033a0264 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_params_pkg.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// mldsa_params_pkg.sv +// -------- +// Common params and defines for ML-DSA 87 +// +//====================================================================== + +`ifndef MLDSA_PARAMS_PKG +`define MLDSA_PARAMS_PKG + +package mldsa_params_pkg; + + //---------------------------------------------------------------- + // Internal constant and parameter definitions. + //---------------------------------------------------------------- + parameter MLDSA_Q = 23'd8380417; + parameter MLDSA_Q_WIDTH = $clog2(MLDSA_Q) + 1; + parameter REG_SIZE = 24; //FIXME + parameter MLDSA_N = 256; + parameter MLDSA_GAMMA2 = (MLDSA_Q-1)/32; + parameter MLDSA_K = 8; + parameter [10:0][7:0] PREHASH_OID = 88'h0302040365014886600906; + + parameter COEFF_PER_CLK = 4; + + + + //Memory interface + parameter MLDSA_MEM_MAX_DEPTH = 1408; + parameter MLDSA_MEM_DATA_WIDTH = COEFF_PER_CLK * MLDSA_Q_WIDTH; + parameter MLDSA_MEM_ADDR_WIDTH = $clog2(MLDSA_MEM_MAX_DEPTH) + 3; //+ 3 bits for bank selection + + //parameter MLDSA_MEM_INST0_DEPTH = 1664; //19.5 KB + //parameter MLDSA_MEM_INST0_ADDR_W = $clog2(MLDSA_MEM_INST0_DEPTH); + parameter MLDSA_MEM_INST0_DEPTH = 1664/2; //9.75 KB + parameter MLDSA_MEM_INST0_ADDR_W = $clog2(MLDSA_MEM_INST0_DEPTH); + parameter MLDSA_MEM_INST0_DATA_W = MLDSA_MEM_DATA_WIDTH; + parameter MLDSA_MEM_INST1_DEPTH = 576; //6.75 KB + parameter MLDSA_MEM_INST1_ADDR_W = $clog2(MLDSA_MEM_INST1_DEPTH); + parameter MLDSA_MEM_INST1_DATA_W = MLDSA_MEM_DATA_WIDTH; + parameter MLDSA_MEM_INST2_DEPTH = 1408; //16.5 KB + parameter MLDSA_MEM_INST2_ADDR_W = $clog2(MLDSA_MEM_INST2_DEPTH); + parameter MLDSA_MEM_INST2_DATA_W = MLDSA_MEM_DATA_WIDTH; + parameter MLDSA_MEM_INST3_DEPTH = 128; //1.5 KB + parameter MLDSA_MEM_INST3_ADDR_W = $clog2(MLDSA_MEM_INST3_DEPTH); + parameter MLDSA_MEM_INST3_DATA_W = MLDSA_MEM_DATA_WIDTH; + parameter MLDSA_MEM_W1_DEPTH = 512; + parameter MLDSA_MEM_W1_ADDR_W = $clog2(MLDSA_MEM_W1_DEPTH); + parameter MLDSA_MEM_W1_DATA_W = 4; + + parameter MLDSA_KEYGEN = 3'b001; + parameter MLDSA_SIGN = 3'b010; + parameter MLDSA_VERIFY = 3'b011; + parameter MLDSA_KEYGEN_SIGN = 3'b100; + + parameter [63 : 0] MLDSA_CORE_NAME = 64'h30; //FIXME + parameter [63 : 0] MLDSA_CORE_VERSION = 64'h0; //FIXME + + // Implementation parameters + parameter DATA_WIDTH = 32; + + //Common structs + typedef enum logic [1:0] {RW_IDLE = 2'b00, RW_READ = 2'b01, RW_WRITE = 2'b10} mem_rw_mode_e; + + typedef struct packed { + mem_rw_mode_e rd_wr_en; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] addr; + } mem_if_t; + +endpackage + +`endif +//====================================================================== +// EOF mldsa_params_pkg.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg.rdl b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg.rdl new file mode 100644 index 0000000000000000000000000000000000000000..f18170e622bfb282d12e5da950e55a976d0952f5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg.rdl @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +addrmap mldsa_reg { + desc="address maps for adams bridge register space"; + + + addressing = regalign; // This is the default if not specified + lsb0 = true; // lsb0 property is implicit/default. See docs for + // SystemRDL 2.0 sections 9.1 and 13.4 + + default hw = na; + signal {activelow; async; cpuif_reset; field_reset;} reset_b; + signal {activelow; async;} hard_reset_b; + signal {} mldsa_ready; + + + /* ----------------------- + * Register definitive definitions + * ----------------------- */ + + /* ---- MLDSA Component Name ---- */ + reg { + name = "MLDSA component name register type definition"; + desc = "Two 32-bit read-only registers representing of the name + of MLDSA component."; + + default sw = r; + default hw = w; + field {desc = "Name field";} NAME[32]; + + } MLDSA_NAME[2]; + + + + /* ---- MLDSA Component Version ---- */ + reg { + name = "MLDSA component version register type definition"; + desc = "Two 32-bit read-only registers representing of the version + of MLDSA component."; + + default sw = r; + default hw = w; + field {desc = "Version field";} VERSION[32]; + + } MLDSA_VERSION[2]; + + + + /* ---- MLDSA Component Control ---- */ + reg { + name = "MLDSA component control register type definition"; + desc = "Control register to set the type of MLDSA operations."; + + default sw = w; + default hw = r; + default resetsignal = reset_b; + field {desc = "Control command field. This can be: + [br] 000 for NONE + [br] 001 for KEYGEN + [br] 010 for SIGNING + [br] 011 for VERIFYING + [br] 100 for KEYGEN+SIGN + + [br] After each software write, hardware will erase the register"; swwe = mldsa_ready; hwclr;} CTRL[3] = 3'b0; + field {desc = "Zeroize all internal registers: Zeroize all internal registers and memories to avoid SCA leakage. + [br] Software write generates only a single-cycle pulse on the + hardware interface and then will be erased"; singlepulse;} ZEROIZE = 1'b0; + field {desc = "Run PCR Signing flow: Run MLDSA KeyGen+Signing flow to sign PCRs."; swwe = mldsa_ready; hwclr;} PCR_SIGN = 1'b0; + field {desc = "ExternalMu Mode"; swwe = mldsa_ready; hwclr;} EXTERNAL_MU = 1'b0; + + } MLDSA_CTRL; + + + + /* ---- MLDSA Component Status ---- */ + reg { + name = "MLDSA component status register type definition"; + desc = "One 2-bit register including the following flags: + bit #0: READY : ​Indicates if the core is ready to take + a control command and process the inputs. + bit #1: VALID : ​Indicates if the process is done and the + result is valid. + "; + + default sw = r; + default hw = w; + default resetsignal = reset_b; + field {desc = "Status ready bit";} READY = 1'b0; + field {desc = "Status valid bit";} VALID = 1'b0; + + } MLDSA_STATUS; + + + /* ---- MLDSA Component Input ENTROPY ---- */ + reg { + name = "MLDSA component entropy register type definition"; + desc = "16 32-bit registers storing the 512-bit entropy in big-endian representation + required for SCA countermeasures with no change on the outputs. + The entropy can be any 512-bit value in [0 : 2^512-1]."; + + default sw = w; + default hw = r; + default resetsignal = reset_b; + field {desc = "Input entropy field"; swwe = mldsa_ready; hwclr;} ENTROPY[32] = 32'b0; + + } MLDSA_ENTROPY[16]; + + /* ---- MLDSA Component Input SEED ---- */ + reg { + name = "MLDSA component seed register type definition"; + desc = "8 32-bit registers storing the 256-bit seed for keygen in big-endian representation. + The seed can be any 256-bit value in [0 : 2^256-1]."; + + default sw = w; + default hw = rw; + default we = true; + default resetsignal = reset_b; + field {desc = "Input seed field"; swwe; hwclr;} SEED[32] = 32'b0; + + } MLDSA_SEED[8]; + + + /* ---- MLDSA Component Input sign_rnd ---- */ + reg { + name = "MLDSA component sign_rnd register type definition"; + desc = "8 32-bit registers storing the 256-bit sign_rnd for signing in big-endian representation. + The sign_rnd can be any 256-bit value in [0 : 2^256-1]. + sign_rnd should be all zero for deterministic variant."; + + default sw = w; + default hw = r; + default resetsignal = reset_b; + field {desc = "Input sign_rnd field"; swwe = mldsa_ready; hwclr;} SIGN_RND[32] = 32'b0; + + } MLDSA_SIGN_RND[8]; + + + /* ---- MLDSA Component Input Message ---- */ + reg { + name = "MLDSA component hashed message register type definition"; + desc = "16 32-bit registers storing the hash of the message in big-endian representation. + The hashed message can be any 512-bit value in [0 : 2^512-1]."; + + default sw = w; + default hw = rw; + default we = true; + default resetsignal = reset_b; + field {desc = "Input message field"; swwe = mldsa_ready; hwclr;} MSG[32] = 32'b0; + + } MLDSA_MSG[16]; + + + /* ---- MLDSA Component Verify Result ---- */ + reg { + name = "MLDSA component verify result register type definition"; + desc = "16 32-bit registers storing the result of verifying operation in big-endian representation. + If this register is equal to the first part of the given signature, i.e. c~, + the signature is verified."; + + default sw = r; + default hw = rw; + default we = true; + default resetsignal = reset_b; + field {desc = "Output verify result field"; hwclr;} VERIFY_RES[32] = 32'b0; + + } MLDSA_VERIFY_RES[16]; + + /* ---- MLDSA Component Input EXTERNAL_MU ---- */ + reg { + name = "MLDSA component external_mu register type definition"; + desc = "16 32-bit registers storing the external_mu in big-endian representation. + The external_mu can be any 512-bit value in [0 : 2^512-1]."; + + default sw = w; + default hw = rw; + default we = true; + default resetsignal = reset_b; + field {desc = "Input message field"; swwe = mldsa_ready; hwclr;} EXTERNAL_MU[32] = 32'b0; + + } MLDSA_EXTERNAL_MU[16]; + + /* ---- MLDSA Component Public Key ---- */ + external mem { + name = "MLDSA component public key register type definition"; + desc = "648 32-bit registers storing the public key in big-endian representation. + These registers are read by MLDSA user after keygen operation, + or set before verifying operation."; + + sw = rw; + mementries = 648; + memwidth = 32; + } MLDSA_PUBKEY; + + /* ---- MLDSA Component Signature ---- */ + external mem { + name = "MLDSA component signature register type definition"; + desc = "1157 32-bit registers storing the signature of the message in big-endian representation. + These registers are read by MLDSA user after signing operation, + or set before verifying operation."; + + sw = rw; + mementries = 1157; + memwidth = 32; + } MLDSA_SIGNATURE; + + /* ---- MLDSA Component Private Key OUT---- */ + external mem { + name = "MLDSA component private key output register type definition"; + desc = "1224 32-bit registers storing the private key for keygen in big-endian representation. + These registers are read by MLDSA user after keygen operation."; + + sw = r; + mementries = 1224; + memwidth = 32; + } MLDSA_PRIVKEY_OUT; + + /* ---- MLDSA Component Private Key IN---- */ + external mem { + name = "MLDSA component private key input register type definition"; + desc = "1224 32-bit entries storing the private key for signing in big-endian representation. + These entries must be set before signing operation."; + + sw = w; + mementries = 1224; + memwidth = 32; + } MLDSA_PRIVKEY_IN; + + kv_read_ctrl_reg mldsa_kv_rd_seed_ctrl @0x8000; + kv_status_reg mldsa_kv_rd_seed_status; + + //////////////////////////////////////////////////////////////// + // Interrupts + /* ----------------------- + * Register File definitive definition + * ----------------------- */ + + // Notifications are non-error events that occur during normal operation of the module. + // E.g. a completion of a job may produce a notification. + // Error and notification events are separated into separate status/trigger registers + // to allow effective priority allocation by software + regfile intr_block_t { + + + /* ----------------------- + * Default properties for Register File + * ----------------------- */ + + name = "Interrupt Register Block"; + desc = "Set of registers to implement interrupt functionality + for MLDSA"; + + default regwidth = 32; // reg property + default accesswidth = 32; // reg property + default hw = na; // field property + + + /* ----------------------- + * Register definitive definitions + * ----------------------- */ + + /* ---- Global Interrupt Enable ---- */ + reg global_intr_en_t { + name = "Per-Type Interrupt Enable Register"; + desc = "Dedicated register with one bit for each event type that may produce an interrupt."; + + default hw = na; + default sw = rw; + + // Global enablement (for interrupts of the event types defined for this module) + field {desc = "Global enable bit for all events of type 'Error'"; } error_en = 1'b0; + field {desc = "Global enable bit for all events of type 'Notification'";} notif_en = 1'b0; + }; + + /* ---- Error Interrupt Enable ---- */ + reg error_intr_en_t { + name = "Per-Event Interrupt Enable Register"; + desc = "Dedicated register with one bit for each event that may produce an interrupt."; + + default hw = na; + default sw = rw; + + // Specific enables for the events defined in this + // event type in the instantiating peripheral. + // TODO: Add en, sts, trig, cnt for all tracked errors + field {desc = "Enable bit for Internal Errors"; } error_internal_en = 1'b0; + }; + + /* ---- Notification Interrupt Enable ---- */ + reg notif_intr_en_t { + name = "Per-Event Interrupt Enable Register"; + desc = "Dedicated register with one bit for each event that may produce an interrupt."; + + default hw = na; + default sw = rw; + + // Specific enables for the events defined in this + // event type in the instantiating peripheral. + field {desc = "Enable bit for Command Done";} notif_cmd_done_en = 1'b0; + }; + + /* ---- Error Interrupt Status ---- */ + reg error_intr_t { + name = "Interrupt Status Register type definition"; + desc = "Single bit indicating occurrence of each interrupt event. + Sticky, level assertion, write-1-to-clear."; + + default precedence = hw; + default hw = w; + default hwset = true; + default sw = rw; + default woclr = true; + default level intr; + + field {desc = "Internal Errors status bit"; } error_internal_sts = 1'b0; + }; + + /* ---- Notification Interrupt Status ---- */ + reg notif_intr_t { + name = "Interrupt Status Register type definition"; + desc = "Single bit indicating occurrence of each interrupt event. + Sticky, level assertion, write-1-to-clear."; + + default precedence = hw; + default hw = w; + default hwset = true; + default sw = rw; + default woclr = true; + default level intr; + + field {desc = "Command Done status bit";} notif_cmd_done_sts = 1'b0; + }; + + /* ---- Aggregated Interrupt Status ---- */ + reg global_intr_t { + name = "Interrupt Status Aggregation Register type definition"; + desc = "Single bit indicating occurrence of any interrupt event + of a given type. E.g. Notifications and Errors may drive + to two separate interrupt registers. There may be + multiple sources of Notifications or Errors that are + aggregated into a single interrupt pin for that + respective type. That pin feeds through this register + in order to apply a global enablement of that interrupt + event type. + Nonsticky assertion."; + + default hw = w; + default sw = r; + default nonsticky intr; + + field {desc = "Interrupt Event Aggregation status bit";} agg_sts = 1'b0; + }; + + /* ---- Error Interrupt Trigger ---- */ + reg error_intr_trig_t { + name = "Interrupt Trigger Register type definition"; + desc = "Single bit for each interrupt event allows SW to manually + trigger occurrence of that event. Upon SW write, the trigger bit + will pulse for 1 cycle then clear to 0. The pulse on the + trigger register bit results in the corresponding interrupt + status bit being set to 1."; + + default hw = na; + default sw = rw; + default woset = true; + default singlepulse = true; + + // Instantiate triggers bit-by-bit. + field {desc = "Internal Errors trigger bit"; } error_internal_trig = 1'b0; + }; + + /* ---- Notification Interrupt Trigger ---- */ + reg notif_intr_trig_t { + name = "Interrupt Trigger Register type definition"; + desc = "Single bit for each interrupt event allows SW to manually + trigger occurrence of that event. Upon SW write, the trigger bit + will pulse for 1 cycle then clear to 0. The pulse on the + trigger register bit results in the corresponding interrupt + status bit being set to 1."; + + default hw = na; + default sw = rw; + default woset = true; + default singlepulse = true; + + // Instantiate triggers bit-by-bit. + field {desc = "Command Done trigger bit";} notif_cmd_done_trig = 1'b0; + }; + + /* ---- Interrupt Statistics Counter Incrementor ---- */ + reg intr_count_incr_t { + name = "Interrupt Event Count Incrementor"; + desc = "Trigger the event counter to increment based on observing + the rising edge of an interrupt event input from the + Hardware. The same input signal that causes an interrupt + event to be set (sticky) also causes this signal to pulse + for 1 clock cycle, resulting in the event counter + incrementing by 1 for every interrupt event. + This is implemented as a down-counter (1-bit) that will + decrement immediately on being set - resulting in a pulse"; + + default hw = w; + default sw = r; // Has to have some access.... ideally SW wouldn't even see this + default hwset = true; + default decrvalue = 1; + default counter; + + field {desc = "Pulse mirrors interrupt event occurrence";} pulse = 1'b0; + }; + + /* ---- Interrupt Statistics Counter ---- */ + reg intr_count_t { + name = "Interrupt Event Counter"; + desc = "Provides statistics about the number of events that have + occurred. + Will not overflow ('incrsaturate')."; + + default sw = rw; + default hw = na; + default incrvalue = 1; + default incrsaturate = true; + default counter; + + field {desc = "Count field";} cnt[32] = 32'h0; + }; + + + /* ------------------------------------------------- Registers ------------------------------------------------- */ + // First 9 registers are static and always defined // + global_intr_en_t global_intr_en_r; /* 1-bit per event type */ // + error_intr_en_t error_intr_en_r; /* 1-bit per error */ // + notif_intr_en_t notif_intr_en_r; /* 1-bit per notification */ // + global_intr_t error_global_intr_r; /* 1-bit aggregating all error interrupts with global enable */ // + global_intr_t notif_global_intr_r; /* 1-bit aggregating all notification interrupts with global enable */ // + error_intr_t error_internal_intr_r; /* Error pending, SW write 1 to clear */ // + notif_intr_t notif_internal_intr_r; /* Notification pending, SW write 1 to clear */ // + error_intr_trig_t error_intr_trig_r; /* SW sets error bit for interrupt testing */ // + notif_intr_trig_t notif_intr_trig_r; /* SW sets notification bit for interrupt testing */ // + // + // Align this set of registers; number of counters is based on peripheral event requirements // + intr_count_t error_internal_intr_count_r @0x100; /* Per error */ // + intr_count_t notif_cmd_done_intr_count_r @0x180; /* Per notification */ // + // + // These registers should be treated by SW as reserved, and ignored. // + // Offset at 0x200 gives enough space for 32 Errors and 32 Notifications // + // to be implemented (requiring 2*32 32-bit registers starting at // + // offset 0x100), and still allowing the entire regfile to fit // + // inside a 1024-byte space. // + intr_count_incr_t error_internal_intr_count_incr_r @0x200; /* Per error count incrementor pulse */ // + intr_count_incr_t notif_cmd_done_intr_count_incr_r; /* Per notification count incrementor pulse */ // + /* ------------------------------------------------------------------------------------------------------------- */ + + /* ---- Reset assignment for Error Events ---- */ + error_internal_intr_r.error_internal_sts -> resetsignal = hard_reset_b; + error_internal_intr_count_r.cnt -> resetsignal = hard_reset_b; + // TODO: Use this same reset for the error incrementor pulse too? + + /* ---- Interrupt Event Dynamic Assignments ---- */ + error_internal_intr_r.error_internal_sts -> enable = error_intr_en_r.error_internal_en; + notif_internal_intr_r.notif_cmd_done_sts -> enable = notif_intr_en_r.notif_cmd_done_en; + + error_internal_intr_r.error_internal_sts -> next = error_intr_trig_r.error_internal_trig; + notif_internal_intr_r.notif_cmd_done_sts -> next = notif_intr_trig_r.notif_cmd_done_trig; + + // NOTE: hwset for events is implicitly defined as module input + + /* ---- Global Interrupt Dynamic Assignments ---- */ + error_global_intr_r.agg_sts -> enable = global_intr_en_r.error_en; + notif_global_intr_r.agg_sts -> enable = global_intr_en_r.notif_en; + + error_global_intr_r.agg_sts -> next = error_internal_intr_r -> intr; + notif_global_intr_r.agg_sts -> next = notif_internal_intr_r -> intr; + + /* ---- Event Statistics Tracker Assignments ---- */ + // NOTE: This method relies upon a "counter" that is set using the + // same events that trigger an interrupt, then immediately + // self-clearing, which results in a pulse. Must be configured + // to be sensitive to the interrupt trigger events for each event. + // The output pulse is then used to increment the ACTUAL counter + error_internal_intr_count_incr_r.pulse -> hwset = error_internal_intr_r.error_internal_sts -> hwset; // \_____ Capture both firmware and hardware triggered events + error_internal_intr_count_incr_r.pulse -> next = error_internal_intr_r.error_internal_sts -> next; // / as a pulse to increment the intr_count_r register + error_internal_intr_count_incr_r.pulse -> we = error_internal_intr_r.error_internal_sts -> next; // Generate a pulse from SW trigger, if set, or default to use the hwset input + error_internal_intr_count_incr_r.pulse -> decr = error_internal_intr_count_incr_r.pulse; // Auto-clear to generate pulse output + error_internal_intr_count_r.cnt -> incr = error_internal_intr_count_incr_r.pulse; // Increment coincides with rising edge of interrupt sts bit + + notif_cmd_done_intr_count_incr_r.pulse -> hwset = notif_internal_intr_r.notif_cmd_done_sts -> hwset; // \_____ Capture both firmware and hardware triggered events + notif_cmd_done_intr_count_incr_r.pulse -> next = notif_internal_intr_r.notif_cmd_done_sts -> next; // / as a pulse to increment the intr_count_r register + notif_cmd_done_intr_count_incr_r.pulse -> we = notif_internal_intr_r.notif_cmd_done_sts -> next; // Generate a pulse from SW trigger, if set, or default to use the hwset input + notif_cmd_done_intr_count_incr_r.pulse -> decr = notif_cmd_done_intr_count_incr_r.pulse; // Auto-clear to generate pulse output + notif_cmd_done_intr_count_r.cnt -> incr = notif_cmd_done_intr_count_incr_r.pulse; // Increment coincides with rising edge of interrupt sts bit + + }; + + /* ----------------------- + * Register File instance + * ----------------------- */ + intr_block_t intr_block_rf @0x8100; +}; diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg.sv new file mode 100644 index 0000000000000000000000000000000000000000..a0f7b61e64c8bb87d94b3ab31f09f4f4c0855f26 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg.sv @@ -0,0 +1,1361 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +module mldsa_reg ( + input wire clk, + input wire rst, + + input wire s_cpuif_req, + input wire s_cpuif_req_is_wr, + input wire [15:0] s_cpuif_addr, + input wire [31:0] s_cpuif_wr_data, + input wire [31:0] s_cpuif_wr_biten, + output wire s_cpuif_req_stall_wr, + output wire s_cpuif_req_stall_rd, + output wire s_cpuif_rd_ack, + output wire s_cpuif_rd_err, + output wire [31:0] s_cpuif_rd_data, + output wire s_cpuif_wr_ack, + output wire s_cpuif_wr_err, + + input mldsa_reg_pkg::mldsa_reg__in_t hwif_in, + output mldsa_reg_pkg::mldsa_reg__out_t hwif_out + ); + + //-------------------------------------------------------------------------- + // CPU Bus interface logic + //-------------------------------------------------------------------------- + logic cpuif_req; + logic cpuif_req_is_wr; + logic [15:0] cpuif_addr; + logic [31:0] cpuif_wr_data; + logic [31:0] cpuif_wr_biten; + logic cpuif_req_stall_wr; + logic cpuif_req_stall_rd; + + logic cpuif_rd_ack; + logic cpuif_rd_err; + logic [31:0] cpuif_rd_data; + + logic cpuif_wr_ack; + logic cpuif_wr_err; + + assign cpuif_req = s_cpuif_req; + assign cpuif_req_is_wr = s_cpuif_req_is_wr; + assign cpuif_addr = s_cpuif_addr; + assign cpuif_wr_data = s_cpuif_wr_data; + assign cpuif_wr_biten = s_cpuif_wr_biten; + assign s_cpuif_req_stall_wr = cpuif_req_stall_wr; + assign s_cpuif_req_stall_rd = cpuif_req_stall_rd; + assign s_cpuif_rd_ack = cpuif_rd_ack; + assign s_cpuif_rd_err = cpuif_rd_err; + assign s_cpuif_rd_data = cpuif_rd_data; + assign s_cpuif_wr_ack = cpuif_wr_ack; + assign s_cpuif_wr_err = cpuif_wr_err; + + logic cpuif_req_masked; + logic external_req; + logic external_pending; + logic external_wr_ack; + logic external_rd_ack; + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + external_pending <= '0; + end else begin + if(external_req & ~external_wr_ack & ~external_rd_ack) external_pending <= '1; + else if(external_wr_ack | external_rd_ack) external_pending <= '0; + assert(!external_wr_ack || (external_pending | external_req)) + else $error("An external wr_ack strobe was asserted when no external request was active"); + assert(!external_rd_ack || (external_pending | external_req)) + else $error("An external rd_ack strobe was asserted when no external request was active"); + end + end + + // Read & write latencies are balanced. Stalls not required + // except if external + assign cpuif_req_stall_rd = external_pending; + assign cpuif_req_stall_wr = external_pending; + assign cpuif_req_masked = cpuif_req + & !(!cpuif_req_is_wr & cpuif_req_stall_rd) + & !(cpuif_req_is_wr & cpuif_req_stall_wr); + + //-------------------------------------------------------------------------- + // Address Decode + //-------------------------------------------------------------------------- + typedef struct packed{ + logic [2-1:0]MLDSA_NAME; + logic [2-1:0]MLDSA_VERSION; + logic MLDSA_CTRL; + logic MLDSA_STATUS; + logic [16-1:0]MLDSA_ENTROPY; + logic [8-1:0]MLDSA_SEED; + logic [8-1:0]MLDSA_SIGN_RND; + logic [16-1:0]MLDSA_MSG; + logic [16-1:0]MLDSA_VERIFY_RES; + logic [16-1:0]MLDSA_EXTERNAL_MU; + logic MLDSA_PUBKEY; + logic MLDSA_SIGNATURE; + logic MLDSA_PRIVKEY_OUT; + logic MLDSA_PRIVKEY_IN; + logic mldsa_kv_rd_seed_ctrl; + logic mldsa_kv_rd_seed_status; + struct packed{ + logic global_intr_en_r; + logic error_intr_en_r; + logic notif_intr_en_r; + logic error_global_intr_r; + logic notif_global_intr_r; + logic error_internal_intr_r; + logic notif_internal_intr_r; + logic error_intr_trig_r; + logic notif_intr_trig_r; + logic error_internal_intr_count_r; + logic notif_cmd_done_intr_count_r; + logic error_internal_intr_count_incr_r; + logic notif_cmd_done_intr_count_incr_r; + } intr_block_rf; + } decoded_reg_strb_t; + decoded_reg_strb_t decoded_reg_strb; + logic decoded_strb_is_external; + + logic [15:0] decoded_addr; + + logic decoded_req; + logic decoded_req_is_wr; + logic [31:0] decoded_wr_data; + logic [31:0] decoded_wr_biten; + + always_comb begin + automatic logic is_external; + is_external = '0; + for(int i0=0; i0<2; i0++) begin + decoded_reg_strb.MLDSA_NAME[i0] = cpuif_req_masked & (cpuif_addr == 16'h0 + i0*16'h4); + end + for(int i0=0; i0<2; i0++) begin + decoded_reg_strb.MLDSA_VERSION[i0] = cpuif_req_masked & (cpuif_addr == 16'h8 + i0*16'h4); + end + decoded_reg_strb.MLDSA_CTRL = cpuif_req_masked & (cpuif_addr == 16'h10); + decoded_reg_strb.MLDSA_STATUS = cpuif_req_masked & (cpuif_addr == 16'h14); + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.MLDSA_ENTROPY[i0] = cpuif_req_masked & (cpuif_addr == 16'h18 + i0*16'h4); + end + for(int i0=0; i0<8; i0++) begin + decoded_reg_strb.MLDSA_SEED[i0] = cpuif_req_masked & (cpuif_addr == 16'h58 + i0*16'h4); + end + for(int i0=0; i0<8; i0++) begin + decoded_reg_strb.MLDSA_SIGN_RND[i0] = cpuif_req_masked & (cpuif_addr == 16'h78 + i0*16'h4); + end + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.MLDSA_MSG[i0] = cpuif_req_masked & (cpuif_addr == 16'h98 + i0*16'h4); + end + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.MLDSA_VERIFY_RES[i0] = cpuif_req_masked & (cpuif_addr == 16'hd8 + i0*16'h4); + end + for(int i0=0; i0<16; i0++) begin + decoded_reg_strb.MLDSA_EXTERNAL_MU[i0] = cpuif_req_masked & (cpuif_addr == 16'h118 + i0*16'h4); + end + decoded_reg_strb.MLDSA_PUBKEY = cpuif_req_masked & (cpuif_addr >= 16'h1000) & (cpuif_addr <= 16'h1000 + 16'ha1f); + is_external |= cpuif_req_masked & (cpuif_addr >= 16'h1000) & (cpuif_addr <= 16'h1000 + 16'ha1f); + decoded_reg_strb.MLDSA_SIGNATURE = cpuif_req_masked & (cpuif_addr >= 16'h2000) & (cpuif_addr <= 16'h2000 + 16'h1213); + is_external |= cpuif_req_masked & (cpuif_addr >= 16'h2000) & (cpuif_addr <= 16'h2000 + 16'h1213); + decoded_reg_strb.MLDSA_PRIVKEY_OUT = cpuif_req_masked & (cpuif_addr >= 16'h4000) & (cpuif_addr <= 16'h4000 + 16'h131f); + is_external |= cpuif_req_masked & (cpuif_addr >= 16'h4000) & (cpuif_addr <= 16'h4000 + 16'h131f); + decoded_reg_strb.MLDSA_PRIVKEY_IN = cpuif_req_masked & (cpuif_addr >= 16'h6000) & (cpuif_addr <= 16'h6000 + 16'h131f); + is_external |= cpuif_req_masked & (cpuif_addr >= 16'h6000) & (cpuif_addr <= 16'h6000 + 16'h131f); + decoded_reg_strb.mldsa_kv_rd_seed_ctrl = cpuif_req_masked & (cpuif_addr == 16'h8000); + decoded_reg_strb.mldsa_kv_rd_seed_status = cpuif_req_masked & (cpuif_addr == 16'h8004); + decoded_reg_strb.intr_block_rf.global_intr_en_r = cpuif_req_masked & (cpuif_addr == 16'h8100); + decoded_reg_strb.intr_block_rf.error_intr_en_r = cpuif_req_masked & (cpuif_addr == 16'h8104); + decoded_reg_strb.intr_block_rf.notif_intr_en_r = cpuif_req_masked & (cpuif_addr == 16'h8108); + decoded_reg_strb.intr_block_rf.error_global_intr_r = cpuif_req_masked & (cpuif_addr == 16'h810c); + decoded_reg_strb.intr_block_rf.notif_global_intr_r = cpuif_req_masked & (cpuif_addr == 16'h8110); + decoded_reg_strb.intr_block_rf.error_internal_intr_r = cpuif_req_masked & (cpuif_addr == 16'h8114); + decoded_reg_strb.intr_block_rf.notif_internal_intr_r = cpuif_req_masked & (cpuif_addr == 16'h8118); + decoded_reg_strb.intr_block_rf.error_intr_trig_r = cpuif_req_masked & (cpuif_addr == 16'h811c); + decoded_reg_strb.intr_block_rf.notif_intr_trig_r = cpuif_req_masked & (cpuif_addr == 16'h8120); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_r = cpuif_req_masked & (cpuif_addr == 16'h8200); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r = cpuif_req_masked & (cpuif_addr == 16'h8280); + decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 16'h8300); + decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r = cpuif_req_masked & (cpuif_addr == 16'h8304); + decoded_strb_is_external = is_external; + external_req = is_external; + end + + // Pass down signals to next stage + assign decoded_addr = cpuif_addr; + + assign decoded_req = cpuif_req_masked; + assign decoded_req_is_wr = cpuif_req_is_wr; + assign decoded_wr_data = cpuif_wr_data; + assign decoded_wr_biten = cpuif_wr_biten; + + //-------------------------------------------------------------------------- + // Field logic + //-------------------------------------------------------------------------- + typedef struct packed{ + struct packed{ + struct packed{ + logic [2:0] next; + logic load_next; + } CTRL; + struct packed{ + logic next; + logic load_next; + } ZEROIZE; + struct packed{ + logic next; + logic load_next; + } PCR_SIGN; + struct packed{ + logic next; + logic load_next; + } EXTERNAL_MU; + } MLDSA_CTRL; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } ENTROPY; + } [16-1:0]MLDSA_ENTROPY; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } SEED; + } [8-1:0]MLDSA_SEED; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } SIGN_RND; + } [8-1:0]MLDSA_SIGN_RND; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } MSG; + } [16-1:0]MLDSA_MSG; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } VERIFY_RES; + } [16-1:0]MLDSA_VERIFY_RES; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + } EXTERNAL_MU; + } [16-1:0]MLDSA_EXTERNAL_MU; + struct packed{ + struct packed{ + logic next; + logic load_next; + } read_en; + struct packed{ + logic [4:0] next; + logic load_next; + } read_entry; + struct packed{ + logic next; + logic load_next; + } pcr_hash_extend; + struct packed{ + logic [24:0] next; + logic load_next; + } rsvd; + } mldsa_kv_rd_seed_ctrl; + struct packed{ + struct packed{ + logic next; + logic load_next; + } VALID; + } mldsa_kv_rd_seed_status; + struct packed{ + struct packed{ + struct packed{ + logic next; + logic load_next; + } error_en; + struct packed{ + logic next; + logic load_next; + } notif_en; + } global_intr_en_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } error_internal_en; + } error_intr_en_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } notif_cmd_done_en; + } notif_intr_en_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } agg_sts; + } error_global_intr_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } agg_sts; + } notif_global_intr_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } error_internal_sts; + } error_internal_intr_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } notif_cmd_done_sts; + } notif_internal_intr_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } error_internal_trig; + } error_intr_trig_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + } notif_cmd_done_trig; + } notif_intr_trig_r; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + logic incrthreshold; + logic incrsaturate; + } cnt; + } error_internal_intr_count_r; + struct packed{ + struct packed{ + logic [31:0] next; + logic load_next; + logic incrthreshold; + logic incrsaturate; + } cnt; + } notif_cmd_done_intr_count_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + logic decrthreshold; + logic underflow; + } pulse; + } error_internal_intr_count_incr_r; + struct packed{ + struct packed{ + logic next; + logic load_next; + logic decrthreshold; + logic underflow; + } pulse; + } notif_cmd_done_intr_count_incr_r; + } intr_block_rf; + } field_combo_t; + field_combo_t field_combo; + + typedef struct packed{ + struct packed{ + struct packed{ + logic [2:0] value; + } CTRL; + struct packed{ + logic value; + } ZEROIZE; + struct packed{ + logic value; + } PCR_SIGN; + struct packed{ + logic value; + } EXTERNAL_MU; + } MLDSA_CTRL; + struct packed{ + struct packed{ + logic [31:0] value; + } ENTROPY; + } [16-1:0]MLDSA_ENTROPY; + struct packed{ + struct packed{ + logic [31:0] value; + } SEED; + } [8-1:0]MLDSA_SEED; + struct packed{ + struct packed{ + logic [31:0] value; + } SIGN_RND; + } [8-1:0]MLDSA_SIGN_RND; + struct packed{ + struct packed{ + logic [31:0] value; + } MSG; + } [16-1:0]MLDSA_MSG; + struct packed{ + struct packed{ + logic [31:0] value; + } VERIFY_RES; + } [16-1:0]MLDSA_VERIFY_RES; + struct packed{ + struct packed{ + logic [31:0] value; + } EXTERNAL_MU; + } [16-1:0]MLDSA_EXTERNAL_MU; + struct packed{ + struct packed{ + logic value; + } read_en; + struct packed{ + logic [4:0] value; + } read_entry; + struct packed{ + logic value; + } pcr_hash_extend; + struct packed{ + logic [24:0] value; + } rsvd; + } mldsa_kv_rd_seed_ctrl; + struct packed{ + struct packed{ + logic value; + } VALID; + } mldsa_kv_rd_seed_status; + struct packed{ + struct packed{ + struct packed{ + logic value; + } error_en; + struct packed{ + logic value; + } notif_en; + } global_intr_en_r; + struct packed{ + struct packed{ + logic value; + } error_internal_en; + } error_intr_en_r; + struct packed{ + struct packed{ + logic value; + } notif_cmd_done_en; + } notif_intr_en_r; + struct packed{ + struct packed{ + logic value; + } agg_sts; + } error_global_intr_r; + struct packed{ + struct packed{ + logic value; + } agg_sts; + } notif_global_intr_r; + struct packed{ + struct packed{ + logic value; + } error_internal_sts; + } error_internal_intr_r; + struct packed{ + struct packed{ + logic value; + } notif_cmd_done_sts; + } notif_internal_intr_r; + struct packed{ + struct packed{ + logic value; + } error_internal_trig; + } error_intr_trig_r; + struct packed{ + struct packed{ + logic value; + } notif_cmd_done_trig; + } notif_intr_trig_r; + struct packed{ + struct packed{ + logic [31:0] value; + } cnt; + } error_internal_intr_count_r; + struct packed{ + struct packed{ + logic [31:0] value; + } cnt; + } notif_cmd_done_intr_count_r; + struct packed{ + struct packed{ + logic value; + } pulse; + } error_internal_intr_count_incr_r; + struct packed{ + struct packed{ + logic value; + } pulse; + } notif_cmd_done_intr_count_incr_r; + } intr_block_rf; + } field_storage_t; + field_storage_t field_storage; + + // Field: mldsa_reg.MLDSA_CTRL.CTRL + always_comb begin + automatic logic [2:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_CTRL.CTRL.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_CTRL && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_CTRL.CTRL.value & ~decoded_wr_biten[2:0]) | (decoded_wr_data[2:0] & decoded_wr_biten[2:0]); + load_next_c = '1; + end else if(hwif_in.MLDSA_CTRL.CTRL.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_CTRL.CTRL.next = next_c; + field_combo.MLDSA_CTRL.CTRL.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_CTRL.CTRL.value <= 3'h0; + end else if(field_combo.MLDSA_CTRL.CTRL.load_next) begin + field_storage.MLDSA_CTRL.CTRL.value <= field_combo.MLDSA_CTRL.CTRL.next; + end + end + assign hwif_out.MLDSA_CTRL.CTRL.value = field_storage.MLDSA_CTRL.CTRL.value; + // Field: mldsa_reg.MLDSA_CTRL.ZEROIZE + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_CTRL.ZEROIZE.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_CTRL && decoded_req_is_wr) begin // SW write + next_c = (field_storage.MLDSA_CTRL.ZEROIZE.value & ~decoded_wr_biten[3:3]) | (decoded_wr_data[3:3] & decoded_wr_biten[3:3]); + load_next_c = '1; + end else begin // singlepulse clears back to 0 + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_CTRL.ZEROIZE.next = next_c; + field_combo.MLDSA_CTRL.ZEROIZE.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_CTRL.ZEROIZE.value <= 1'h0; + end else if(field_combo.MLDSA_CTRL.ZEROIZE.load_next) begin + field_storage.MLDSA_CTRL.ZEROIZE.value <= field_combo.MLDSA_CTRL.ZEROIZE.next; + end + end + assign hwif_out.MLDSA_CTRL.ZEROIZE.value = field_storage.MLDSA_CTRL.ZEROIZE.value; + // Field: mldsa_reg.MLDSA_CTRL.PCR_SIGN + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_CTRL.PCR_SIGN.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_CTRL && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_CTRL.PCR_SIGN.value & ~decoded_wr_biten[4:4]) | (decoded_wr_data[4:4] & decoded_wr_biten[4:4]); + load_next_c = '1; + end else if(hwif_in.MLDSA_CTRL.PCR_SIGN.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_CTRL.PCR_SIGN.next = next_c; + field_combo.MLDSA_CTRL.PCR_SIGN.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_CTRL.PCR_SIGN.value <= 1'h0; + end else if(field_combo.MLDSA_CTRL.PCR_SIGN.load_next) begin + field_storage.MLDSA_CTRL.PCR_SIGN.value <= field_combo.MLDSA_CTRL.PCR_SIGN.next; + end + end + assign hwif_out.MLDSA_CTRL.PCR_SIGN.value = field_storage.MLDSA_CTRL.PCR_SIGN.value; + // Field: mldsa_reg.MLDSA_CTRL.EXTERNAL_MU + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_CTRL.EXTERNAL_MU.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_CTRL && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_CTRL.EXTERNAL_MU.value & ~decoded_wr_biten[5:5]) | (decoded_wr_data[5:5] & decoded_wr_biten[5:5]); + load_next_c = '1; + end else if(hwif_in.MLDSA_CTRL.EXTERNAL_MU.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_CTRL.EXTERNAL_MU.next = next_c; + field_combo.MLDSA_CTRL.EXTERNAL_MU.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_CTRL.EXTERNAL_MU.value <= 1'h0; + end else if(field_combo.MLDSA_CTRL.EXTERNAL_MU.load_next) begin + field_storage.MLDSA_CTRL.EXTERNAL_MU.value <= field_combo.MLDSA_CTRL.EXTERNAL_MU.next; + end + end + assign hwif_out.MLDSA_CTRL.EXTERNAL_MU.value = field_storage.MLDSA_CTRL.EXTERNAL_MU.value; + for(genvar i0=0; i0<16; i0++) begin + // Field: mldsa_reg.MLDSA_ENTROPY[].ENTROPY + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_ENTROPY[i0].ENTROPY.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_ENTROPY[i0] && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_ENTROPY[i0].ENTROPY.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end else if(hwif_in.MLDSA_ENTROPY[i0].ENTROPY.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_ENTROPY[i0].ENTROPY.next = next_c; + field_combo.MLDSA_ENTROPY[i0].ENTROPY.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_ENTROPY[i0].ENTROPY.value <= 32'h0; + end else if(field_combo.MLDSA_ENTROPY[i0].ENTROPY.load_next) begin + field_storage.MLDSA_ENTROPY[i0].ENTROPY.value <= field_combo.MLDSA_ENTROPY[i0].ENTROPY.next; + end + end + assign hwif_out.MLDSA_ENTROPY[i0].ENTROPY.value = field_storage.MLDSA_ENTROPY[i0].ENTROPY.value; + end + for(genvar i0=0; i0<8; i0++) begin + // Field: mldsa_reg.MLDSA_SEED[].SEED + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_SEED[i0].SEED.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_SEED[i0] && decoded_req_is_wr && hwif_in.MLDSA_SEED[i0].SEED.swwe) begin // SW write + next_c = (field_storage.MLDSA_SEED[i0].SEED.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end else if(hwif_in.MLDSA_SEED[i0].SEED.we) begin // HW Write - we + next_c = hwif_in.MLDSA_SEED[i0].SEED.next; + load_next_c = '1; + end else if(hwif_in.MLDSA_SEED[i0].SEED.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_SEED[i0].SEED.next = next_c; + field_combo.MLDSA_SEED[i0].SEED.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_SEED[i0].SEED.value <= 32'h0; + end else if(field_combo.MLDSA_SEED[i0].SEED.load_next) begin + field_storage.MLDSA_SEED[i0].SEED.value <= field_combo.MLDSA_SEED[i0].SEED.next; + end + end + assign hwif_out.MLDSA_SEED[i0].SEED.value = field_storage.MLDSA_SEED[i0].SEED.value; + end + for(genvar i0=0; i0<8; i0++) begin + // Field: mldsa_reg.MLDSA_SIGN_RND[].SIGN_RND + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_SIGN_RND[i0].SIGN_RND.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_SIGN_RND[i0] && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_SIGN_RND[i0].SIGN_RND.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end else if(hwif_in.MLDSA_SIGN_RND[i0].SIGN_RND.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_SIGN_RND[i0].SIGN_RND.next = next_c; + field_combo.MLDSA_SIGN_RND[i0].SIGN_RND.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_SIGN_RND[i0].SIGN_RND.value <= 32'h0; + end else if(field_combo.MLDSA_SIGN_RND[i0].SIGN_RND.load_next) begin + field_storage.MLDSA_SIGN_RND[i0].SIGN_RND.value <= field_combo.MLDSA_SIGN_RND[i0].SIGN_RND.next; + end + end + assign hwif_out.MLDSA_SIGN_RND[i0].SIGN_RND.value = field_storage.MLDSA_SIGN_RND[i0].SIGN_RND.value; + end + for(genvar i0=0; i0<16; i0++) begin + // Field: mldsa_reg.MLDSA_MSG[].MSG + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_MSG[i0].MSG.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_MSG[i0] && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_MSG[i0].MSG.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end else if(hwif_in.MLDSA_MSG[i0].MSG.we) begin // HW Write - we + next_c = hwif_in.MLDSA_MSG[i0].MSG.next; + load_next_c = '1; + end else if(hwif_in.MLDSA_MSG[i0].MSG.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_MSG[i0].MSG.next = next_c; + field_combo.MLDSA_MSG[i0].MSG.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_MSG[i0].MSG.value <= 32'h0; + end else if(field_combo.MLDSA_MSG[i0].MSG.load_next) begin + field_storage.MLDSA_MSG[i0].MSG.value <= field_combo.MLDSA_MSG[i0].MSG.next; + end + end + assign hwif_out.MLDSA_MSG[i0].MSG.value = field_storage.MLDSA_MSG[i0].MSG.value; + end + for(genvar i0=0; i0<16; i0++) begin + // Field: mldsa_reg.MLDSA_VERIFY_RES[].VERIFY_RES + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_VERIFY_RES[i0].VERIFY_RES.value; + load_next_c = '0; + if(hwif_in.MLDSA_VERIFY_RES[i0].VERIFY_RES.we) begin // HW Write - we + next_c = hwif_in.MLDSA_VERIFY_RES[i0].VERIFY_RES.next; + load_next_c = '1; + end else if(hwif_in.MLDSA_VERIFY_RES[i0].VERIFY_RES.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_VERIFY_RES[i0].VERIFY_RES.next = next_c; + field_combo.MLDSA_VERIFY_RES[i0].VERIFY_RES.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_VERIFY_RES[i0].VERIFY_RES.value <= 32'h0; + end else if(field_combo.MLDSA_VERIFY_RES[i0].VERIFY_RES.load_next) begin + field_storage.MLDSA_VERIFY_RES[i0].VERIFY_RES.value <= field_combo.MLDSA_VERIFY_RES[i0].VERIFY_RES.next; + end + end + assign hwif_out.MLDSA_VERIFY_RES[i0].VERIFY_RES.value = field_storage.MLDSA_VERIFY_RES[i0].VERIFY_RES.value; + end + for(genvar i0=0; i0<16; i0++) begin + // Field: mldsa_reg.MLDSA_EXTERNAL_MU[].EXTERNAL_MU + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.value; + load_next_c = '0; + if(decoded_reg_strb.MLDSA_EXTERNAL_MU[i0] && decoded_req_is_wr && hwif_in.mldsa_ready) begin // SW write + next_c = (field_storage.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end else if(hwif_in.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.we) begin // HW Write - we + next_c = hwif_in.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.next; + load_next_c = '1; + end else if(hwif_in.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.next = next_c; + field_combo.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.value <= 32'h0; + end else if(field_combo.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.load_next) begin + field_storage.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.value <= field_combo.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.next; + end + end + assign hwif_out.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.value = field_storage.MLDSA_EXTERNAL_MU[i0].EXTERNAL_MU.value; + end + assign hwif_out.MLDSA_PUBKEY.req = decoded_reg_strb.MLDSA_PUBKEY; + assign hwif_out.MLDSA_PUBKEY.addr = decoded_addr[11:0]; + assign hwif_out.MLDSA_PUBKEY.req_is_wr = decoded_req_is_wr; + assign hwif_out.MLDSA_PUBKEY.wr_data = decoded_wr_data; + assign hwif_out.MLDSA_PUBKEY.wr_biten = decoded_wr_biten; + assign hwif_out.MLDSA_SIGNATURE.req = decoded_reg_strb.MLDSA_SIGNATURE; + assign hwif_out.MLDSA_SIGNATURE.addr = decoded_addr[12:0]; + assign hwif_out.MLDSA_SIGNATURE.req_is_wr = decoded_req_is_wr; + assign hwif_out.MLDSA_SIGNATURE.wr_data = decoded_wr_data; + assign hwif_out.MLDSA_SIGNATURE.wr_biten = decoded_wr_biten; + assign hwif_out.MLDSA_PRIVKEY_OUT.req = decoded_reg_strb.MLDSA_PRIVKEY_OUT; + assign hwif_out.MLDSA_PRIVKEY_OUT.addr = decoded_addr[12:0]; + assign hwif_out.MLDSA_PRIVKEY_OUT.req_is_wr = decoded_req_is_wr; + assign hwif_out.MLDSA_PRIVKEY_OUT.wr_data = decoded_wr_data; + assign hwif_out.MLDSA_PRIVKEY_OUT.wr_biten = decoded_wr_biten; + assign hwif_out.MLDSA_PRIVKEY_IN.req = decoded_reg_strb.MLDSA_PRIVKEY_IN; + assign hwif_out.MLDSA_PRIVKEY_IN.addr = decoded_addr[12:0]; + assign hwif_out.MLDSA_PRIVKEY_IN.req_is_wr = decoded_req_is_wr; + assign hwif_out.MLDSA_PRIVKEY_IN.wr_data = decoded_wr_data; + assign hwif_out.MLDSA_PRIVKEY_IN.wr_biten = decoded_wr_biten; + // Field: mldsa_reg.mldsa_kv_rd_seed_ctrl.read_en + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mldsa_kv_rd_seed_ctrl.read_en.value; + load_next_c = '0; + if(decoded_reg_strb.mldsa_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write + next_c = (field_storage.mldsa_kv_rd_seed_ctrl.read_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end else if(hwif_in.mldsa_kv_rd_seed_ctrl.read_en.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.mldsa_kv_rd_seed_ctrl.read_en.next = next_c; + field_combo.mldsa_kv_rd_seed_ctrl.read_en.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.mldsa_kv_rd_seed_ctrl.read_en.value <= 1'h0; + end else if(field_combo.mldsa_kv_rd_seed_ctrl.read_en.load_next) begin + field_storage.mldsa_kv_rd_seed_ctrl.read_en.value <= field_combo.mldsa_kv_rd_seed_ctrl.read_en.next; + end + end + assign hwif_out.mldsa_kv_rd_seed_ctrl.read_en.value = field_storage.mldsa_kv_rd_seed_ctrl.read_en.value; + // Field: mldsa_reg.mldsa_kv_rd_seed_ctrl.read_entry + always_comb begin + automatic logic [4:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mldsa_kv_rd_seed_ctrl.read_entry.value; + load_next_c = '0; + if(decoded_reg_strb.mldsa_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write + next_c = (field_storage.mldsa_kv_rd_seed_ctrl.read_entry.value & ~decoded_wr_biten[5:1]) | (decoded_wr_data[5:1] & decoded_wr_biten[5:1]); + load_next_c = '1; + end + field_combo.mldsa_kv_rd_seed_ctrl.read_entry.next = next_c; + field_combo.mldsa_kv_rd_seed_ctrl.read_entry.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.mldsa_kv_rd_seed_ctrl.read_entry.value <= 5'h0; + end else if(field_combo.mldsa_kv_rd_seed_ctrl.read_entry.load_next) begin + field_storage.mldsa_kv_rd_seed_ctrl.read_entry.value <= field_combo.mldsa_kv_rd_seed_ctrl.read_entry.next; + end + end + assign hwif_out.mldsa_kv_rd_seed_ctrl.read_entry.value = field_storage.mldsa_kv_rd_seed_ctrl.read_entry.value; + // Field: mldsa_reg.mldsa_kv_rd_seed_ctrl.pcr_hash_extend + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value; + load_next_c = '0; + if(decoded_reg_strb.mldsa_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write + next_c = (field_storage.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value & ~decoded_wr_biten[6:6]) | (decoded_wr_data[6:6] & decoded_wr_biten[6:6]); + load_next_c = '1; + end + field_combo.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.next = next_c; + field_combo.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value <= 1'h0; + end else if(field_combo.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.load_next) begin + field_storage.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value <= field_combo.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.next; + end + end + assign hwif_out.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value = field_storage.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value; + // Field: mldsa_reg.mldsa_kv_rd_seed_ctrl.rsvd + always_comb begin + automatic logic [24:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mldsa_kv_rd_seed_ctrl.rsvd.value; + load_next_c = '0; + if(decoded_reg_strb.mldsa_kv_rd_seed_ctrl && decoded_req_is_wr) begin // SW write + next_c = (field_storage.mldsa_kv_rd_seed_ctrl.rsvd.value & ~decoded_wr_biten[31:7]) | (decoded_wr_data[31:7] & decoded_wr_biten[31:7]); + load_next_c = '1; + end + field_combo.mldsa_kv_rd_seed_ctrl.rsvd.next = next_c; + field_combo.mldsa_kv_rd_seed_ctrl.rsvd.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.mldsa_kv_rd_seed_ctrl.rsvd.value <= 25'h0; + end else if(field_combo.mldsa_kv_rd_seed_ctrl.rsvd.load_next) begin + field_storage.mldsa_kv_rd_seed_ctrl.rsvd.value <= field_combo.mldsa_kv_rd_seed_ctrl.rsvd.next; + end + end + assign hwif_out.mldsa_kv_rd_seed_ctrl.rsvd.value = field_storage.mldsa_kv_rd_seed_ctrl.rsvd.value; + // Field: mldsa_reg.mldsa_kv_rd_seed_status.VALID + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.mldsa_kv_rd_seed_status.VALID.value; + load_next_c = '0; + if(hwif_in.mldsa_kv_rd_seed_status.VALID.hwset) begin // HW Set + next_c = '1; + load_next_c = '1; + end else if(hwif_in.mldsa_kv_rd_seed_status.VALID.hwclr) begin // HW Clear + next_c = '0; + load_next_c = '1; + end + field_combo.mldsa_kv_rd_seed_status.VALID.next = next_c; + field_combo.mldsa_kv_rd_seed_status.VALID.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.mldsa_kv_rd_seed_status.VALID.value <= 1'h0; + end else if(field_combo.mldsa_kv_rd_seed_status.VALID.load_next) begin + field_storage.mldsa_kv_rd_seed_status.VALID.value <= field_combo.mldsa_kv_rd_seed_status.VALID.next; + end + end + // Field: mldsa_reg.intr_block_rf.global_intr_en_r.error_en + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.error_en.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write + next_c = (field_storage.intr_block_rf.global_intr_en_r.error_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.intr_block_rf.global_intr_en_r.error_en.next = next_c; + field_combo.intr_block_rf.global_intr_en_r.error_en.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= 1'h0; + end else if(field_combo.intr_block_rf.global_intr_en_r.error_en.load_next) begin + field_storage.intr_block_rf.global_intr_en_r.error_en.value <= field_combo.intr_block_rf.global_intr_en_r.error_en.next; + end + end + // Field: mldsa_reg.intr_block_rf.global_intr_en_r.notif_en + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.global_intr_en_r.notif_en.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.global_intr_en_r && decoded_req_is_wr) begin // SW write + next_c = (field_storage.intr_block_rf.global_intr_en_r.notif_en.value & ~decoded_wr_biten[1:1]) | (decoded_wr_data[1:1] & decoded_wr_biten[1:1]); + load_next_c = '1; + end + field_combo.intr_block_rf.global_intr_en_r.notif_en.next = next_c; + field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= 1'h0; + end else if(field_combo.intr_block_rf.global_intr_en_r.notif_en.load_next) begin + field_storage.intr_block_rf.global_intr_en_r.notif_en.value <= field_combo.intr_block_rf.global_intr_en_r.notif_en.next; + end + end + // Field: mldsa_reg.intr_block_rf.error_intr_en_r.error_internal_en + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.error_intr_en_r && decoded_req_is_wr) begin // SW write + next_c = (field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.intr_block_rf.error_intr_en_r.error_internal_en.next = next_c; + field_combo.intr_block_rf.error_intr_en_r.error_internal_en.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= 1'h0; + end else if(field_combo.intr_block_rf.error_intr_en_r.error_internal_en.load_next) begin + field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value <= field_combo.intr_block_rf.error_intr_en_r.error_internal_en.next; + end + end + // Field: mldsa_reg.intr_block_rf.notif_intr_en_r.notif_cmd_done_en + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.notif_intr_en_r && decoded_req_is_wr) begin // SW write + next_c = (field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next = next_c; + field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= 1'h0; + end else if(field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.load_next) begin + field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value <= field_combo.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.next; + end + end + // Field: mldsa_reg.intr_block_rf.error_global_intr_r.agg_sts + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.error_internal_intr_r.intr; + load_next_c = '1; + field_combo.intr_block_rf.error_global_intr_r.agg_sts.next = next_c; + field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= 1'h0; + end else if(field_combo.intr_block_rf.error_global_intr_r.agg_sts.load_next) begin + field_storage.intr_block_rf.error_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.error_global_intr_r.agg_sts.next; + end + end + assign hwif_out.intr_block_rf.error_global_intr_r.intr = + |(field_storage.intr_block_rf.error_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.error_en.value); + // Field: mldsa_reg.intr_block_rf.notif_global_intr_r.agg_sts + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value; + load_next_c = '0; + + // HW Write + next_c = hwif_out.intr_block_rf.notif_internal_intr_r.intr; + load_next_c = '1; + field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next = next_c; + field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= 1'h0; + end else if(field_combo.intr_block_rf.notif_global_intr_r.agg_sts.load_next) begin + field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value <= field_combo.intr_block_rf.notif_global_intr_r.agg_sts.next; + end + end + assign hwif_out.intr_block_rf.notif_global_intr_r.intr = + |(field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value & field_storage.intr_block_rf.global_intr_en_r.notif_en.value); + // Field: mldsa_reg.intr_block_rf.error_internal_intr_r.error_internal_sts + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value != '0) begin // stickybit + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value | field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '1; + end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset) begin // HW Set + next_c = '1; + load_next_c = '1; + end else if(decoded_reg_strb.intr_block_rf.error_internal_intr_r && decoded_req_is_wr) begin // SW write 1 clear + next_c = field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.next = next_c; + field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin + if(~hwif_in.hard_reset_b) begin + field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= 1'h0; + end else if(field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.load_next) begin + field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value <= field_combo.intr_block_rf.error_internal_intr_r.error_internal_sts.next; + end + end + assign hwif_out.intr_block_rf.error_internal_intr_r.intr = + |(field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value & field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value); + // Field: mldsa_reg.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value != '0) begin // stickybit + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value | field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '1; + end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set + next_c = '1; + load_next_c = '1; + end else if(decoded_reg_strb.intr_block_rf.notif_internal_intr_r && decoded_req_is_wr) begin // SW write 1 clear + next_c = field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & ~(decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end + field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next = next_c; + field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= 1'h0; + end else if(field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.load_next) begin + field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value <= field_combo.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.next; + end + end + assign hwif_out.intr_block_rf.notif_internal_intr_r.intr = + |(field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value & field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value); + // Field: mldsa_reg.intr_block_rf.error_intr_trig_r.error_internal_trig + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.error_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end else begin // singlepulse clears back to 0 + next_c = '0; + load_next_c = '1; + end + field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.next = next_c; + field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= 1'h0; + end else if(field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.load_next) begin + field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value <= field_combo.intr_block_rf.error_intr_trig_r.error_internal_trig.next; + end + end + // Field: mldsa_reg.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.notif_intr_trig_r && decoded_req_is_wr) begin // SW write 1 set + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]); + load_next_c = '1; + end else begin // singlepulse clears back to 0 + next_c = '0; + load_next_c = '1; + end + field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next = next_c; + field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= 1'h0; + end else if(field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.load_next) begin + field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value <= field_combo.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.next; + end + end + // Field: mldsa_reg.intr_block_rf.error_internal_intr_count_r.cnt + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && decoded_req_is_wr) begin // SW write + next_c = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // increment + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; + end else begin + next_c = next_c + 32'h1; + end + load_next_c = '1; + end + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; + load_next_c = '1; + end + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next = next_c; + field_combo.intr_block_rf.error_internal_intr_count_r.cnt.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.hard_reset_b) begin + if(~hwif_in.hard_reset_b) begin + field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= 32'h0; + end else if(field_combo.intr_block_rf.error_internal_intr_count_r.cnt.load_next) begin + field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value <= field_combo.intr_block_rf.error_internal_intr_count_r.cnt.next; + end + end + // Field: mldsa_reg.intr_block_rf.notif_cmd_done_intr_count_r.cnt + always_comb begin + automatic logic [31:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value; + load_next_c = '0; + if(decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && decoded_req_is_wr) begin // SW write + next_c = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]); + load_next_c = '1; + end + if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // increment + if(((33)'(next_c) + 32'h1) > 32'hffffffff) begin // up-counter saturated + next_c = 32'hffffffff; + end else begin + next_c = next_c + 32'h1; + end + load_next_c = '1; + end + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.incrsaturate = (field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value >= 32'hffffffff); + if(next_c > 32'hffffffff) begin + next_c = 32'hffffffff; + load_next_c = '1; + end + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next = next_c; + field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= 32'h0; + end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.load_next) begin + field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_r.cnt.next; + end + end + // Field: mldsa_reg.intr_block_rf.error_internal_intr_count_incr_r.pulse + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value; + load_next_c = '0; + if(field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value) begin // HW Write - we + next_c = field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value; + load_next_c = '1; + end else if(hwif_in.intr_block_rf.error_internal_intr_r.error_internal_sts.hwset) begin // HW Set + next_c = '1; + load_next_c = '1; + end + if(field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value) begin // decrement + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; + load_next_c = '1; + end else begin + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.underflow = '0; + end + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'd0); + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next = next_c; + field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= 1'h0; + end else if(field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.load_next) begin + field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.error_internal_intr_count_incr_r.pulse.next; + end + end + // Field: mldsa_reg.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse + always_comb begin + automatic logic [0:0] next_c; + automatic logic load_next_c; + next_c = field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value; + load_next_c = '0; + if(field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value) begin // HW Write - we + next_c = field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value; + load_next_c = '1; + end else if(hwif_in.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.hwset) begin // HW Set + next_c = '1; + load_next_c = '1; + end + if(field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value) begin // decrement + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = (next_c < (1'h1)); + next_c = next_c - 1'h1; + load_next_c = '1; + end else begin + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.underflow = '0; + end + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.decrthreshold = (field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'd0); + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next = next_c; + field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next = load_next_c; + end + always_ff @(posedge clk or negedge hwif_in.reset_b) begin + if(~hwif_in.reset_b) begin + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= 1'h0; + end else if(field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.load_next) begin + field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value <= field_combo.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.next; + end + end + + //-------------------------------------------------------------------------- + // Write response + //-------------------------------------------------------------------------- + always_comb begin + automatic logic wr_ack; + wr_ack = '0; + wr_ack |= hwif_in.MLDSA_PUBKEY.wr_ack; + wr_ack |= hwif_in.MLDSA_SIGNATURE.wr_ack; + wr_ack |= hwif_in.MLDSA_PRIVKEY_OUT.wr_ack; + wr_ack |= hwif_in.MLDSA_PRIVKEY_IN.wr_ack; + external_wr_ack = wr_ack; + end + assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_strb_is_external); + // Writes are always granted with no error response + assign cpuif_wr_err = '0; + + //-------------------------------------------------------------------------- + // Readback + //-------------------------------------------------------------------------- + logic readback_external_rd_ack_c; + always_comb begin + automatic logic rd_ack; + rd_ack = '0; + rd_ack |= hwif_in.MLDSA_PUBKEY.rd_ack; + rd_ack |= hwif_in.MLDSA_SIGNATURE.rd_ack; + rd_ack |= hwif_in.MLDSA_PRIVKEY_OUT.rd_ack; + rd_ack |= hwif_in.MLDSA_PRIVKEY_IN.rd_ack; + readback_external_rd_ack_c = rd_ack; + end + + logic readback_external_rd_ack; + + assign readback_external_rd_ack = readback_external_rd_ack_c; + + logic readback_err; + logic readback_done; + logic [31:0] readback_data; + + // Assign readback values to a flattened array + logic [40-1:0][31:0] readback_array; + for(genvar i0=0; i0<2; i0++) begin + assign readback_array[i0*1 + 0][31:0] = (decoded_reg_strb.MLDSA_NAME[i0] && !decoded_req_is_wr) ? hwif_in.MLDSA_NAME[i0].NAME.next : '0; + end + for(genvar i0=0; i0<2; i0++) begin + assign readback_array[i0*1 + 2][31:0] = (decoded_reg_strb.MLDSA_VERSION[i0] && !decoded_req_is_wr) ? hwif_in.MLDSA_VERSION[i0].VERSION.next : '0; + end + assign readback_array[4][0:0] = (decoded_reg_strb.MLDSA_STATUS && !decoded_req_is_wr) ? hwif_in.MLDSA_STATUS.READY.next : '0; + assign readback_array[4][1:1] = (decoded_reg_strb.MLDSA_STATUS && !decoded_req_is_wr) ? hwif_in.MLDSA_STATUS.VALID.next : '0; + assign readback_array[4][31:2] = '0; + for(genvar i0=0; i0<16; i0++) begin + assign readback_array[i0*1 + 5][31:0] = (decoded_reg_strb.MLDSA_VERIFY_RES[i0] && !decoded_req_is_wr) ? field_storage.MLDSA_VERIFY_RES[i0].VERIFY_RES.value : '0; + end + assign readback_array[21] = hwif_in.MLDSA_PUBKEY.rd_ack ? hwif_in.MLDSA_PUBKEY.rd_data : '0; + assign readback_array[22] = hwif_in.MLDSA_SIGNATURE.rd_ack ? hwif_in.MLDSA_SIGNATURE.rd_data : '0; + assign readback_array[23] = hwif_in.MLDSA_PRIVKEY_OUT.rd_ack ? hwif_in.MLDSA_PRIVKEY_OUT.rd_data : '0; + assign readback_array[24] = hwif_in.MLDSA_PRIVKEY_IN.rd_ack ? hwif_in.MLDSA_PRIVKEY_IN.rd_data : '0; + assign readback_array[25][0:0] = (decoded_reg_strb.mldsa_kv_rd_seed_ctrl && !decoded_req_is_wr) ? field_storage.mldsa_kv_rd_seed_ctrl.read_en.value : '0; + assign readback_array[25][5:1] = (decoded_reg_strb.mldsa_kv_rd_seed_ctrl && !decoded_req_is_wr) ? field_storage.mldsa_kv_rd_seed_ctrl.read_entry.value : '0; + assign readback_array[25][6:6] = (decoded_reg_strb.mldsa_kv_rd_seed_ctrl && !decoded_req_is_wr) ? field_storage.mldsa_kv_rd_seed_ctrl.pcr_hash_extend.value : '0; + assign readback_array[25][31:7] = (decoded_reg_strb.mldsa_kv_rd_seed_ctrl && !decoded_req_is_wr) ? field_storage.mldsa_kv_rd_seed_ctrl.rsvd.value : '0; + assign readback_array[26][0:0] = (decoded_reg_strb.mldsa_kv_rd_seed_status && !decoded_req_is_wr) ? hwif_in.mldsa_kv_rd_seed_status.READY.next : '0; + assign readback_array[26][1:1] = (decoded_reg_strb.mldsa_kv_rd_seed_status && !decoded_req_is_wr) ? field_storage.mldsa_kv_rd_seed_status.VALID.value : '0; + assign readback_array[26][9:2] = (decoded_reg_strb.mldsa_kv_rd_seed_status && !decoded_req_is_wr) ? hwif_in.mldsa_kv_rd_seed_status.ERROR.next : '0; + assign readback_array[26][31:10] = '0; + assign readback_array[27][0:0] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.error_en.value : '0; + assign readback_array[27][1:1] = (decoded_reg_strb.intr_block_rf.global_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.global_intr_en_r.notif_en.value : '0; + assign readback_array[27][31:2] = '0; + assign readback_array[28][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_en_r.error_internal_en.value : '0; + assign readback_array[28][31:1] = '0; + assign readback_array[29][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_en_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_en_r.notif_cmd_done_en.value : '0; + assign readback_array[29][31:1] = '0; + assign readback_array[30][0:0] = (decoded_reg_strb.intr_block_rf.error_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_global_intr_r.agg_sts.value : '0; + assign readback_array[30][31:1] = '0; + assign readback_array[31][0:0] = (decoded_reg_strb.intr_block_rf.notif_global_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_global_intr_r.agg_sts.value : '0; + assign readback_array[31][31:1] = '0; + assign readback_array[32][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_r.error_internal_sts.value : '0; + assign readback_array[32][31:1] = '0; + assign readback_array[33][0:0] = (decoded_reg_strb.intr_block_rf.notif_internal_intr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_internal_intr_r.notif_cmd_done_sts.value : '0; + assign readback_array[33][31:1] = '0; + assign readback_array[34][0:0] = (decoded_reg_strb.intr_block_rf.error_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_intr_trig_r.error_internal_trig.value : '0; + assign readback_array[34][31:1] = '0; + assign readback_array[35][0:0] = (decoded_reg_strb.intr_block_rf.notif_intr_trig_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_intr_trig_r.notif_cmd_done_trig.value : '0; + assign readback_array[35][31:1] = '0; + assign readback_array[36][31:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_r.cnt.value : '0; + assign readback_array[37][31:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_done_intr_count_r.cnt.value : '0; + assign readback_array[38][0:0] = (decoded_reg_strb.intr_block_rf.error_internal_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.error_internal_intr_count_incr_r.pulse.value : '0; + assign readback_array[38][31:1] = '0; + assign readback_array[39][0:0] = (decoded_reg_strb.intr_block_rf.notif_cmd_done_intr_count_incr_r && !decoded_req_is_wr) ? field_storage.intr_block_rf.notif_cmd_done_intr_count_incr_r.pulse.value : '0; + assign readback_array[39][31:1] = '0; + + // Reduce the array + always_comb begin + automatic logic [31:0] readback_data_var; + readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_strb_is_external; + readback_err = '0; + readback_data_var = '0; + for(int i=0; i<40; i++) readback_data_var |= readback_array[i]; + readback_data = readback_data_var; + end + + assign external_rd_ack = readback_external_rd_ack; + assign cpuif_rd_ack = readback_done | readback_external_rd_ack; + assign cpuif_rd_data = readback_data; + assign cpuif_rd_err = readback_err; + +`ABR_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !hwif_in.hard_reset_b) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..5522210af904a1fffc79b5b07fd6c4efbe3c23fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg_pkg.sv @@ -0,0 +1,381 @@ +// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator +// https://github.com/SystemRDL/PeakRDL-regblock + +package mldsa_reg_pkg; + + localparam MLDSA_REG_DATA_WIDTH = 32; + localparam MLDSA_REG_MIN_ADDR_WIDTH = 16; + + typedef struct packed{ + logic [31:0] next; + } mldsa_reg__MLDSA_NAME__NAME__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_NAME__NAME__in_t NAME; + } mldsa_reg__MLDSA_NAME__in_t; + + typedef struct packed{ + logic [31:0] next; + } mldsa_reg__MLDSA_VERSION__VERSION__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_VERSION__VERSION__in_t VERSION; + } mldsa_reg__MLDSA_VERSION__in_t; + + typedef struct packed{ + logic hwclr; + } mldsa_reg__MLDSA_CTRL__CTRL__in_t; + + typedef struct packed{ + logic hwclr; + } mldsa_reg__MLDSA_CTRL__PCR_SIGN__in_t; + + typedef struct packed{ + logic hwclr; + } mldsa_reg__MLDSA_CTRL__EXTERNAL_MU__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_CTRL__CTRL__in_t CTRL; + mldsa_reg__MLDSA_CTRL__PCR_SIGN__in_t PCR_SIGN; + mldsa_reg__MLDSA_CTRL__EXTERNAL_MU__in_t EXTERNAL_MU; + } mldsa_reg__MLDSA_CTRL__in_t; + + typedef struct packed{ + logic next; + } mldsa_reg__MLDSA_STATUS__READY__in_t; + + typedef struct packed{ + logic next; + } mldsa_reg__MLDSA_STATUS__VALID__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_STATUS__READY__in_t READY; + mldsa_reg__MLDSA_STATUS__VALID__in_t VALID; + } mldsa_reg__MLDSA_STATUS__in_t; + + typedef struct packed{ + logic hwclr; + } mldsa_reg__MLDSA_ENTROPY__ENTROPY__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_ENTROPY__ENTROPY__in_t ENTROPY; + } mldsa_reg__MLDSA_ENTROPY__in_t; + + typedef struct packed{ + logic [31:0] next; + logic we; + logic swwe; + logic hwclr; + } mldsa_reg__MLDSA_SEED__SEED__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_SEED__SEED__in_t SEED; + } mldsa_reg__MLDSA_SEED__in_t; + + typedef struct packed{ + logic hwclr; + } mldsa_reg__MLDSA_SIGN_RND__SIGN_RND__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_SIGN_RND__SIGN_RND__in_t SIGN_RND; + } mldsa_reg__MLDSA_SIGN_RND__in_t; + + typedef struct packed{ + logic [31:0] next; + logic we; + logic hwclr; + } mldsa_reg__MLDSA_MSG__MSG__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_MSG__MSG__in_t MSG; + } mldsa_reg__MLDSA_MSG__in_t; + + typedef struct packed{ + logic [31:0] next; + logic we; + logic hwclr; + } mldsa_reg__MLDSA_VERIFY_RES__VERIFY_RES__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_VERIFY_RES__VERIFY_RES__in_t VERIFY_RES; + } mldsa_reg__MLDSA_VERIFY_RES__in_t; + + typedef struct packed{ + logic [31:0] next; + logic we; + logic hwclr; + } mldsa_reg__MLDSA_EXTERNAL_MU__EXTERNAL_MU__in_t; + + typedef struct packed{ + mldsa_reg__MLDSA_EXTERNAL_MU__EXTERNAL_MU__in_t EXTERNAL_MU; + } mldsa_reg__MLDSA_EXTERNAL_MU__in_t; + + typedef struct packed{ + logic rd_ack; + logic [31:0] rd_data; + logic wr_ack; + } mldsa_reg__MLDSA_PUBKEY__external__in_t; + + typedef struct packed{ + logic rd_ack; + logic [31:0] rd_data; + logic wr_ack; + } mldsa_reg__MLDSA_SIGNATURE__external__in_t; + + typedef struct packed{ + logic rd_ack; + logic [31:0] rd_data; + logic wr_ack; + } mldsa_reg__MLDSA_PRIVKEY_OUT__external__in_t; + + typedef struct packed{ + logic rd_ack; + logic [31:0] rd_data; + logic wr_ack; + } mldsa_reg__MLDSA_PRIVKEY_IN__external__in_t; + + typedef struct packed{ + logic hwclr; + } kv_read_ctrl_reg__read_en__in_t; + + typedef struct packed{ + kv_read_ctrl_reg__read_en__in_t read_en; + } kv_read_ctrl_reg__in_t; + + typedef struct packed{ + logic next; + } kv_status_reg__READY__in_t; + + typedef struct packed{ + logic hwclr; + logic hwset; + } kv_status_reg__VALID__in_t; + + typedef struct packed{ + logic [7:0] next; + } kv_status_reg__ERROR__in_t; + + typedef struct packed{ + kv_status_reg__READY__in_t READY; + kv_status_reg__VALID__in_t VALID; + kv_status_reg__ERROR__in_t ERROR; + } kv_status_reg__in_t; + + typedef struct packed{ + logic hwset; + } mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t; + + typedef struct packed{ + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__error_internal_sts_enable_d33001bb_next_52b75ffa_resetsignal_0d7eaa27__in_t error_internal_sts; + } mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__in_t; + + typedef struct packed{ + logic hwset; + } mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t; + + typedef struct packed{ + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__notif_cmd_done_sts_enable_dabe0b8b_next_540fa3b7__in_t notif_cmd_done_sts; + } mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t; + + typedef struct packed{ + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__in_t error_internal_intr_r; + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__in_t notif_internal_intr_r; + } mldsa_reg__intr_block_t__in_t; + + typedef struct packed{ + logic reset_b; + logic hard_reset_b; + logic mldsa_ready; + mldsa_reg__MLDSA_NAME__in_t [2-1:0]MLDSA_NAME; + mldsa_reg__MLDSA_VERSION__in_t [2-1:0]MLDSA_VERSION; + mldsa_reg__MLDSA_CTRL__in_t MLDSA_CTRL; + mldsa_reg__MLDSA_STATUS__in_t MLDSA_STATUS; + mldsa_reg__MLDSA_ENTROPY__in_t [16-1:0]MLDSA_ENTROPY; + mldsa_reg__MLDSA_SEED__in_t [8-1:0]MLDSA_SEED; + mldsa_reg__MLDSA_SIGN_RND__in_t [8-1:0]MLDSA_SIGN_RND; + mldsa_reg__MLDSA_MSG__in_t [16-1:0]MLDSA_MSG; + mldsa_reg__MLDSA_VERIFY_RES__in_t [16-1:0]MLDSA_VERIFY_RES; + mldsa_reg__MLDSA_EXTERNAL_MU__in_t [16-1:0]MLDSA_EXTERNAL_MU; + mldsa_reg__MLDSA_PUBKEY__external__in_t MLDSA_PUBKEY; + mldsa_reg__MLDSA_SIGNATURE__external__in_t MLDSA_SIGNATURE; + mldsa_reg__MLDSA_PRIVKEY_OUT__external__in_t MLDSA_PRIVKEY_OUT; + mldsa_reg__MLDSA_PRIVKEY_IN__external__in_t MLDSA_PRIVKEY_IN; + kv_read_ctrl_reg__in_t mldsa_kv_rd_seed_ctrl; + kv_status_reg__in_t mldsa_kv_rd_seed_status; + mldsa_reg__intr_block_t__in_t intr_block_rf; + } mldsa_reg__in_t; + + typedef struct packed{ + logic [2:0] value; + } mldsa_reg__MLDSA_CTRL__CTRL__out_t; + + typedef struct packed{ + logic value; + } mldsa_reg__MLDSA_CTRL__ZEROIZE__out_t; + + typedef struct packed{ + logic value; + } mldsa_reg__MLDSA_CTRL__PCR_SIGN__out_t; + + typedef struct packed{ + logic value; + } mldsa_reg__MLDSA_CTRL__EXTERNAL_MU__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_CTRL__CTRL__out_t CTRL; + mldsa_reg__MLDSA_CTRL__ZEROIZE__out_t ZEROIZE; + mldsa_reg__MLDSA_CTRL__PCR_SIGN__out_t PCR_SIGN; + mldsa_reg__MLDSA_CTRL__EXTERNAL_MU__out_t EXTERNAL_MU; + } mldsa_reg__MLDSA_CTRL__out_t; + + typedef struct packed{ + logic [31:0] value; + } mldsa_reg__MLDSA_ENTROPY__ENTROPY__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_ENTROPY__ENTROPY__out_t ENTROPY; + } mldsa_reg__MLDSA_ENTROPY__out_t; + + typedef struct packed{ + logic [31:0] value; + } mldsa_reg__MLDSA_SEED__SEED__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_SEED__SEED__out_t SEED; + } mldsa_reg__MLDSA_SEED__out_t; + + typedef struct packed{ + logic [31:0] value; + } mldsa_reg__MLDSA_SIGN_RND__SIGN_RND__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_SIGN_RND__SIGN_RND__out_t SIGN_RND; + } mldsa_reg__MLDSA_SIGN_RND__out_t; + + typedef struct packed{ + logic [31:0] value; + } mldsa_reg__MLDSA_MSG__MSG__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_MSG__MSG__out_t MSG; + } mldsa_reg__MLDSA_MSG__out_t; + + typedef struct packed{ + logic [31:0] value; + } mldsa_reg__MLDSA_VERIFY_RES__VERIFY_RES__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_VERIFY_RES__VERIFY_RES__out_t VERIFY_RES; + } mldsa_reg__MLDSA_VERIFY_RES__out_t; + + typedef struct packed{ + logic [31:0] value; + } mldsa_reg__MLDSA_EXTERNAL_MU__EXTERNAL_MU__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_EXTERNAL_MU__EXTERNAL_MU__out_t EXTERNAL_MU; + } mldsa_reg__MLDSA_EXTERNAL_MU__out_t; + + typedef struct packed{ + logic req; + logic [11:0] addr; + logic req_is_wr; + logic [31:0] wr_data; + logic [31:0] wr_biten; + } mldsa_reg__MLDSA_PUBKEY__external__out_t; + + typedef struct packed{ + logic req; + logic [12:0] addr; + logic req_is_wr; + logic [31:0] wr_data; + logic [31:0] wr_biten; + } mldsa_reg__MLDSA_SIGNATURE__external__out_t; + + typedef struct packed{ + logic req; + logic [12:0] addr; + logic req_is_wr; + logic [31:0] wr_data; + logic [31:0] wr_biten; + } mldsa_reg__MLDSA_PRIVKEY_OUT__external__out_t; + + typedef struct packed{ + logic req; + logic [12:0] addr; + logic req_is_wr; + logic [31:0] wr_data; + logic [31:0] wr_biten; + } mldsa_reg__MLDSA_PRIVKEY_IN__external__out_t; + + typedef struct packed{ + logic value; + } kv_read_ctrl_reg__read_en__out_t; + + typedef struct packed{ + logic [4:0] value; + } kv_read_ctrl_reg__read_entry__out_t; + + typedef struct packed{ + logic value; + } kv_read_ctrl_reg__pcr_hash_extend__out_t; + + typedef struct packed{ + logic [24:0] value; + } kv_read_ctrl_reg__rsvd__out_t; + + typedef struct packed{ + kv_read_ctrl_reg__read_en__out_t read_en; + kv_read_ctrl_reg__read_entry__out_t read_entry; + kv_read_ctrl_reg__pcr_hash_extend__out_t pcr_hash_extend; + kv_read_ctrl_reg__rsvd__out_t rsvd; + } kv_read_ctrl_reg__out_t; + + typedef struct packed{ + logic intr; + } mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a__out_t; + + typedef struct packed{ + logic intr; + } mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a__out_t; + + typedef struct packed{ + logic intr; + } mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__out_t; + + typedef struct packed{ + logic intr; + } mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__out_t; + + typedef struct packed{ + mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a__out_t error_global_intr_r; + mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a__out_t notif_global_intr_r; + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02__out_t error_internal_intr_r; + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e__out_t notif_internal_intr_r; + } mldsa_reg__intr_block_t__out_t; + + typedef struct packed{ + mldsa_reg__MLDSA_CTRL__out_t MLDSA_CTRL; + mldsa_reg__MLDSA_ENTROPY__out_t [16-1:0]MLDSA_ENTROPY; + mldsa_reg__MLDSA_SEED__out_t [8-1:0]MLDSA_SEED; + mldsa_reg__MLDSA_SIGN_RND__out_t [8-1:0]MLDSA_SIGN_RND; + mldsa_reg__MLDSA_MSG__out_t [16-1:0]MLDSA_MSG; + mldsa_reg__MLDSA_VERIFY_RES__out_t [16-1:0]MLDSA_VERIFY_RES; + mldsa_reg__MLDSA_EXTERNAL_MU__out_t [16-1:0]MLDSA_EXTERNAL_MU; + mldsa_reg__MLDSA_PUBKEY__external__out_t MLDSA_PUBKEY; + mldsa_reg__MLDSA_SIGNATURE__external__out_t MLDSA_SIGNATURE; + mldsa_reg__MLDSA_PRIVKEY_OUT__external__out_t MLDSA_PRIVKEY_OUT; + mldsa_reg__MLDSA_PRIVKEY_IN__external__out_t MLDSA_PRIVKEY_IN; + kv_read_ctrl_reg__out_t mldsa_kv_rd_seed_ctrl; + mldsa_reg__intr_block_t__out_t intr_block_rf; + } mldsa_reg__out_t; + + typedef enum logic [31:0] { + kv_status_reg__ERROR__kv_error_e__SUCCESS = 'h0, + kv_status_reg__ERROR__kv_error_e__KV_READ_FAIL = 'h1, + kv_status_reg__ERROR__kv_error_e__KV_WRITE_FAIL = 'h2 + } kv_status_reg__ERROR__kv_error_e_e; + + localparam MLDSA_REG_ADDR_WIDTH = 32'd16; + +endpackage \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg_uvm.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg_uvm.sv new file mode 100644 index 0000000000000000000000000000000000000000..35c7e63671a73bc0998b98415c5435f487cffab1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_reg_uvm.sv @@ -0,0 +1,1087 @@ + +// This file was autogenerated by PeakRDL-uvm +package mldsa_reg_uvm; + `include "uvm_macros.svh" + import uvm_pkg::*; + `include "mldsa_reg_covergroups.svh" + // Reg - mldsa_reg::MLDSA_NAME + class mldsa_reg__MLDSA_NAME extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_NAME_bit_cg NAME_bit_cg[32]; + mldsa_reg__MLDSA_NAME_fld_cg fld_cg; + rand uvm_reg_field NAME; + + function new(string name = "mldsa_reg__MLDSA_NAME"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.NAME = new("NAME"); + this.NAME.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(NAME_bit_cg[bt]) NAME_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_NAME + + // Reg - mldsa_reg::MLDSA_VERSION + class mldsa_reg__MLDSA_VERSION extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_VERSION_bit_cg VERSION_bit_cg[32]; + mldsa_reg__MLDSA_VERSION_fld_cg fld_cg; + rand uvm_reg_field VERSION; + + function new(string name = "mldsa_reg__MLDSA_VERSION"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.VERSION = new("VERSION"); + this.VERSION.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERSION_bit_cg[bt]) VERSION_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_VERSION + + // Reg - mldsa_reg::MLDSA_CTRL + class mldsa_reg__MLDSA_CTRL extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_CTRL_bit_cg CTRL_bit_cg[3]; + mldsa_reg__MLDSA_CTRL_bit_cg ZEROIZE_bit_cg[1]; + mldsa_reg__MLDSA_CTRL_bit_cg PCR_SIGN_bit_cg[1]; + mldsa_reg__MLDSA_CTRL_bit_cg EXTERNAL_MU_bit_cg[1]; + mldsa_reg__MLDSA_CTRL_fld_cg fld_cg; + rand uvm_reg_field CTRL; + rand uvm_reg_field ZEROIZE; + rand uvm_reg_field PCR_SIGN; + rand uvm_reg_field EXTERNAL_MU; + + function new(string name = "mldsa_reg__MLDSA_CTRL"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.CTRL = new("CTRL"); + this.CTRL.configure(this, 3, 0, "WO", 1, 'h0, 1, 1, 0); + this.ZEROIZE = new("ZEROIZE"); + this.ZEROIZE.configure(this, 1, 3, "WO", 0, 'h0, 1, 1, 0); + this.PCR_SIGN = new("PCR_SIGN"); + this.PCR_SIGN.configure(this, 1, 4, "WO", 1, 'h0, 1, 1, 0); + this.EXTERNAL_MU = new("EXTERNAL_MU"); + this.EXTERNAL_MU.configure(this, 1, 5, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(CTRL_bit_cg[bt]) CTRL_bit_cg[bt] = new(); + foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new(); + foreach(PCR_SIGN_bit_cg[bt]) PCR_SIGN_bit_cg[bt] = new(); + foreach(EXTERNAL_MU_bit_cg[bt]) EXTERNAL_MU_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_CTRL + + // Reg - mldsa_reg::MLDSA_STATUS + class mldsa_reg__MLDSA_STATUS extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_STATUS_bit_cg READY_bit_cg[1]; + mldsa_reg__MLDSA_STATUS_bit_cg VALID_bit_cg[1]; + mldsa_reg__MLDSA_STATUS_fld_cg fld_cg; + rand uvm_reg_field READY; + rand uvm_reg_field VALID; + + function new(string name = "mldsa_reg__MLDSA_STATUS"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.READY = new("READY"); + this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + this.VALID = new("VALID"); + this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new(); + foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_STATUS + + // Reg - mldsa_reg::MLDSA_ENTROPY + class mldsa_reg__MLDSA_ENTROPY extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_ENTROPY_bit_cg ENTROPY_bit_cg[32]; + mldsa_reg__MLDSA_ENTROPY_fld_cg fld_cg; + rand uvm_reg_field ENTROPY; + + function new(string name = "mldsa_reg__MLDSA_ENTROPY"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.ENTROPY = new("ENTROPY"); + this.ENTROPY.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(ENTROPY_bit_cg[bt]) ENTROPY_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_ENTROPY + + // Reg - mldsa_reg::MLDSA_SEED + class mldsa_reg__MLDSA_SEED extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_SEED_bit_cg SEED_bit_cg[32]; + mldsa_reg__MLDSA_SEED_fld_cg fld_cg; + rand uvm_reg_field SEED; + + function new(string name = "mldsa_reg__MLDSA_SEED"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.SEED = new("SEED"); + this.SEED.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(SEED_bit_cg[bt]) SEED_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_SEED + + // Reg - mldsa_reg::MLDSA_SIGN_RND + class mldsa_reg__MLDSA_SIGN_RND extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_SIGN_RND_bit_cg SIGN_RND_bit_cg[32]; + mldsa_reg__MLDSA_SIGN_RND_fld_cg fld_cg; + rand uvm_reg_field SIGN_RND; + + function new(string name = "mldsa_reg__MLDSA_SIGN_RND"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.SIGN_RND = new("SIGN_RND"); + this.SIGN_RND.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(SIGN_RND_bit_cg[bt]) SIGN_RND_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_SIGN_RND + + // Reg - mldsa_reg::MLDSA_MSG + class mldsa_reg__MLDSA_MSG extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_MSG_bit_cg MSG_bit_cg[32]; + mldsa_reg__MLDSA_MSG_fld_cg fld_cg; + rand uvm_reg_field MSG; + + function new(string name = "mldsa_reg__MLDSA_MSG"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.MSG = new("MSG"); + this.MSG.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(MSG_bit_cg[bt]) MSG_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_MSG + + // Reg - mldsa_reg::MLDSA_VERIFY_RES + class mldsa_reg__MLDSA_VERIFY_RES extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_VERIFY_RES_bit_cg VERIFY_RES_bit_cg[32]; + mldsa_reg__MLDSA_VERIFY_RES_fld_cg fld_cg; + rand uvm_reg_field VERIFY_RES; + + function new(string name = "mldsa_reg__MLDSA_VERIFY_RES"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.VERIFY_RES = new("VERIFY_RES"); + this.VERIFY_RES.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERIFY_RES_bit_cg[bt]) VERIFY_RES_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_VERIFY_RES + + // Reg - mldsa_reg::MLDSA_EXTERNAL_MU + class mldsa_reg__MLDSA_EXTERNAL_MU extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_EXTERNAL_MU_bit_cg EXTERNAL_MU_bit_cg[32]; + mldsa_reg__MLDSA_EXTERNAL_MU_fld_cg fld_cg; + rand uvm_reg_field EXTERNAL_MU; + + function new(string name = "mldsa_reg__MLDSA_EXTERNAL_MU"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.EXTERNAL_MU = new("EXTERNAL_MU"); + this.EXTERNAL_MU.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(EXTERNAL_MU_bit_cg[bt]) EXTERNAL_MU_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_EXTERNAL_MU + + // Mem - mldsa_reg::MLDSA_PUBKEY + class mldsa_reg__MLDSA_PUBKEY extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_PUBKEY"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 648, 32, "RW"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_PUBKEY + + // Mem - mldsa_reg::MLDSA_SIGNATURE + class mldsa_reg__MLDSA_SIGNATURE extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_SIGNATURE"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 1157, 32, "RW"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_SIGNATURE + + // Mem - mldsa_reg::MLDSA_PRIVKEY_OUT + class mldsa_reg__MLDSA_PRIVKEY_OUT extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_PRIVKEY_OUT"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 1224, 32, "RO"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_PRIVKEY_OUT + + // Mem - mldsa_reg::MLDSA_PRIVKEY_IN + class mldsa_reg__MLDSA_PRIVKEY_IN extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_PRIVKEY_IN"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 1224, 32, "RW"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_PRIVKEY_IN + + // Reg - kv_read_ctrl_reg + class kv_read_ctrl_reg extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + kv_read_ctrl_reg_bit_cg read_en_bit_cg[1]; + kv_read_ctrl_reg_bit_cg read_entry_bit_cg[5]; + kv_read_ctrl_reg_bit_cg pcr_hash_extend_bit_cg[1]; + kv_read_ctrl_reg_bit_cg rsvd_bit_cg[25]; + kv_read_ctrl_reg_fld_cg fld_cg; + rand uvm_reg_field read_en; + rand uvm_reg_field read_entry; + rand uvm_reg_field pcr_hash_extend; + rand uvm_reg_field rsvd; + + function new(string name = "kv_read_ctrl_reg"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.read_en = new("read_en"); + this.read_en.configure(this, 1, 0, "RW", 1, 'h0, 1, 1, 0); + this.read_entry = new("read_entry"); + this.read_entry.configure(this, 5, 1, "RW", 0, 'h0, 1, 1, 0); + this.pcr_hash_extend = new("pcr_hash_extend"); + this.pcr_hash_extend.configure(this, 1, 6, "RW", 0, 'h0, 1, 1, 0); + this.rsvd = new("rsvd"); + this.rsvd.configure(this, 25, 7, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(read_en_bit_cg[bt]) read_en_bit_cg[bt] = new(); + foreach(read_entry_bit_cg[bt]) read_entry_bit_cg[bt] = new(); + foreach(pcr_hash_extend_bit_cg[bt]) pcr_hash_extend_bit_cg[bt] = new(); + foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : kv_read_ctrl_reg + + // Reg - kv_status_reg + class kv_status_reg extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + kv_status_reg_bit_cg READY_bit_cg[1]; + kv_status_reg_bit_cg VALID_bit_cg[1]; + kv_status_reg_bit_cg ERROR_bit_cg[8]; + kv_status_reg_fld_cg fld_cg; + rand uvm_reg_field READY; + rand uvm_reg_field VALID; + rand uvm_reg_field ERROR; + + function new(string name = "kv_status_reg"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.READY = new("READY"); + this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + this.VALID = new("VALID"); + this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0); + this.ERROR = new("ERROR"); + this.ERROR.configure(this, 8, 2, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new(); + foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new(); + foreach(ERROR_bit_cg[bt]) ERROR_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : kv_status_reg + + // Reg - mldsa_reg::intr_block_t::global_intr_en_t + class mldsa_reg__intr_block_t__global_intr_en_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__global_intr_en_t_bit_cg error_en_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_en_t_bit_cg notif_en_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_en_t_fld_cg fld_cg; + rand uvm_reg_field error_en; + rand uvm_reg_field notif_en; + + function new(string name = "mldsa_reg__intr_block_t__global_intr_en_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_en = new("error_en"); + this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0); + this.notif_en = new("notif_en"); + this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new(); + foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__global_intr_en_t + + // Reg - mldsa_reg::intr_block_t::error_intr_en_t + class mldsa_reg__intr_block_t__error_intr_en_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__error_intr_en_t_bit_cg error_internal_en_bit_cg[1]; + mldsa_reg__intr_block_t__error_intr_en_t_fld_cg fld_cg; + rand uvm_reg_field error_internal_en; + + function new(string name = "mldsa_reg__intr_block_t__error_intr_en_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_internal_en = new("error_internal_en"); + this.error_internal_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_en_bit_cg[bt]) error_internal_en_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__error_intr_en_t + + // Reg - mldsa_reg::intr_block_t::notif_intr_en_t + class mldsa_reg__intr_block_t__notif_intr_en_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1]; + mldsa_reg__intr_block_t__notif_intr_en_t_fld_cg fld_cg; + rand uvm_reg_field notif_cmd_done_en; + + function new(string name = "mldsa_reg__intr_block_t__notif_intr_en_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.notif_cmd_done_en = new("notif_cmd_done_en"); + this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__notif_intr_en_t + + // Reg - mldsa_reg::intr_block_t::global_intr_t_agg_sts_dd3dcf0a + class mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg; + rand uvm_reg_field agg_sts; + + function new(string name = "mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.agg_sts = new("agg_sts"); + this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a + + // Reg - mldsa_reg::intr_block_t::global_intr_t_agg_sts_e6399b4a + class mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg; + rand uvm_reg_field agg_sts; + + function new(string name = "mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.agg_sts = new("agg_sts"); + this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a + + // Reg - mldsa_reg::intr_block_t::error_intr_t_error_internal_sts_83adab02 + class mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_bit_cg error_internal_sts_bit_cg[1]; + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_fld_cg fld_cg; + rand uvm_reg_field error_internal_sts; + + function new(string name = "mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_internal_sts = new("error_internal_sts"); + this.error_internal_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_sts_bit_cg[bt]) error_internal_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 + + // Reg - mldsa_reg::intr_block_t::notif_intr_t_notif_cmd_done_sts_1c68637e + class mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1]; + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg; + rand uvm_reg_field notif_cmd_done_sts; + + function new(string name = "mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.notif_cmd_done_sts = new("notif_cmd_done_sts"); + this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e + + // Reg - mldsa_reg::intr_block_t::error_intr_trig_t + class mldsa_reg__intr_block_t__error_intr_trig_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__error_intr_trig_t_bit_cg error_internal_trig_bit_cg[1]; + mldsa_reg__intr_block_t__error_intr_trig_t_fld_cg fld_cg; + rand uvm_reg_field error_internal_trig; + + function new(string name = "mldsa_reg__intr_block_t__error_intr_trig_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_internal_trig = new("error_internal_trig"); + this.error_internal_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_trig_bit_cg[bt]) error_internal_trig_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__error_intr_trig_t + + // Reg - mldsa_reg::intr_block_t::notif_intr_trig_t + class mldsa_reg__intr_block_t__notif_intr_trig_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1]; + mldsa_reg__intr_block_t__notif_intr_trig_t_fld_cg fld_cg; + rand uvm_reg_field notif_cmd_done_trig; + + function new(string name = "mldsa_reg__intr_block_t__notif_intr_trig_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.notif_cmd_done_trig = new("notif_cmd_done_trig"); + this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__notif_intr_trig_t + + // Reg - mldsa_reg::intr_block_t::intr_count_t_cnt_60ddff93 + class mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93 extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93_bit_cg cnt_bit_cg[32]; + mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93_fld_cg fld_cg; + rand uvm_reg_field cnt; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.cnt = new("cnt"); + this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93 + + // Reg - mldsa_reg::intr_block_t::intr_count_t_cnt_be67d6d5 + class mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5 extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32]; + mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5_fld_cg fld_cg; + rand uvm_reg_field cnt; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.cnt = new("cnt"); + this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5 + + // Reg - mldsa_reg::intr_block_t::intr_count_incr_t_pulse_15e6ed7e + class mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_bit_cg pulse_bit_cg[1]; + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_fld_cg fld_cg; + rand uvm_reg_field pulse; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.pulse = new("pulse"); + this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e + + // Reg - mldsa_reg::intr_block_t::intr_count_incr_t_pulse_6173128e + class mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1]; + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg; + rand uvm_reg_field pulse; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.pulse = new("pulse"); + this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e + + // Regfile - mldsa_reg::intr_block_t + class mldsa_reg__intr_block_t extends uvm_reg_block; + rand mldsa_reg__intr_block_t__global_intr_en_t global_intr_en_r; + rand mldsa_reg__intr_block_t__error_intr_en_t error_intr_en_r; + rand mldsa_reg__intr_block_t__notif_intr_en_t notif_intr_en_r; + rand mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a error_global_intr_r; + rand mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a notif_global_intr_r; + rand mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 error_internal_intr_r; + rand mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e notif_internal_intr_r; + rand mldsa_reg__intr_block_t__error_intr_trig_t error_intr_trig_r; + rand mldsa_reg__intr_block_t__notif_intr_trig_t notif_intr_trig_r; + rand mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93 error_internal_intr_count_r; + rand mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5 notif_cmd_done_intr_count_r; + rand mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e error_internal_intr_count_incr_r; + rand mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e notif_cmd_done_intr_count_incr_r; + + function new(string name = "mldsa_reg__intr_block_t"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4, UVM_NO_ENDIAN); + this.global_intr_en_r = new("global_intr_en_r"); + this.global_intr_en_r.configure(this); + + this.global_intr_en_r.build(); + this.default_map.add_reg(this.global_intr_en_r, 'h0); + this.error_intr_en_r = new("error_intr_en_r"); + this.error_intr_en_r.configure(this); + + this.error_intr_en_r.build(); + this.default_map.add_reg(this.error_intr_en_r, 'h4); + this.notif_intr_en_r = new("notif_intr_en_r"); + this.notif_intr_en_r.configure(this); + + this.notif_intr_en_r.build(); + this.default_map.add_reg(this.notif_intr_en_r, 'h8); + this.error_global_intr_r = new("error_global_intr_r"); + this.error_global_intr_r.configure(this); + + this.error_global_intr_r.build(); + this.default_map.add_reg(this.error_global_intr_r, 'hc); + this.notif_global_intr_r = new("notif_global_intr_r"); + this.notif_global_intr_r.configure(this); + + this.notif_global_intr_r.build(); + this.default_map.add_reg(this.notif_global_intr_r, 'h10); + this.error_internal_intr_r = new("error_internal_intr_r"); + this.error_internal_intr_r.configure(this); + + this.error_internal_intr_r.build(); + this.default_map.add_reg(this.error_internal_intr_r, 'h14); + this.notif_internal_intr_r = new("notif_internal_intr_r"); + this.notif_internal_intr_r.configure(this); + + this.notif_internal_intr_r.build(); + this.default_map.add_reg(this.notif_internal_intr_r, 'h18); + this.error_intr_trig_r = new("error_intr_trig_r"); + this.error_intr_trig_r.configure(this); + + this.error_intr_trig_r.build(); + this.default_map.add_reg(this.error_intr_trig_r, 'h1c); + this.notif_intr_trig_r = new("notif_intr_trig_r"); + this.notif_intr_trig_r.configure(this); + + this.notif_intr_trig_r.build(); + this.default_map.add_reg(this.notif_intr_trig_r, 'h20); + this.error_internal_intr_count_r = new("error_internal_intr_count_r"); + this.error_internal_intr_count_r.configure(this); + + this.error_internal_intr_count_r.build(); + this.default_map.add_reg(this.error_internal_intr_count_r, 'h100); + this.notif_cmd_done_intr_count_r = new("notif_cmd_done_intr_count_r"); + this.notif_cmd_done_intr_count_r.configure(this); + + this.notif_cmd_done_intr_count_r.build(); + this.default_map.add_reg(this.notif_cmd_done_intr_count_r, 'h180); + this.error_internal_intr_count_incr_r = new("error_internal_intr_count_incr_r"); + this.error_internal_intr_count_incr_r.configure(this); + + this.error_internal_intr_count_incr_r.build(); + this.default_map.add_reg(this.error_internal_intr_count_incr_r, 'h200); + this.notif_cmd_done_intr_count_incr_r = new("notif_cmd_done_intr_count_incr_r"); + this.notif_cmd_done_intr_count_incr_r.configure(this); + + this.notif_cmd_done_intr_count_incr_r.build(); + this.default_map.add_reg(this.notif_cmd_done_intr_count_incr_r, 'h204); + endfunction : build + endclass : mldsa_reg__intr_block_t + + // Addrmap - mldsa_reg + class mldsa_reg extends uvm_reg_block; + rand mldsa_reg__MLDSA_NAME MLDSA_NAME[2]; + rand mldsa_reg__MLDSA_VERSION MLDSA_VERSION[2]; + rand mldsa_reg__MLDSA_CTRL MLDSA_CTRL; + rand mldsa_reg__MLDSA_STATUS MLDSA_STATUS; + rand mldsa_reg__MLDSA_ENTROPY MLDSA_ENTROPY[16]; + rand mldsa_reg__MLDSA_SEED MLDSA_SEED[8]; + rand mldsa_reg__MLDSA_SIGN_RND MLDSA_SIGN_RND[8]; + rand mldsa_reg__MLDSA_MSG MLDSA_MSG[16]; + rand mldsa_reg__MLDSA_VERIFY_RES MLDSA_VERIFY_RES[16]; + rand mldsa_reg__MLDSA_EXTERNAL_MU MLDSA_EXTERNAL_MU[16]; + rand mldsa_reg__MLDSA_PUBKEY MLDSA_PUBKEY; + rand mldsa_reg__MLDSA_SIGNATURE MLDSA_SIGNATURE; + rand mldsa_reg__MLDSA_PRIVKEY_OUT MLDSA_PRIVKEY_OUT; + rand mldsa_reg__MLDSA_PRIVKEY_IN MLDSA_PRIVKEY_IN; + rand kv_read_ctrl_reg mldsa_kv_rd_seed_ctrl; + rand kv_status_reg mldsa_kv_rd_seed_status; + rand mldsa_reg__intr_block_t intr_block_rf; + + function new(string name = "mldsa_reg"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4, UVM_NO_ENDIAN); + foreach(this.MLDSA_NAME[i0]) begin + this.MLDSA_NAME[i0] = new($sformatf("MLDSA_NAME[%0d]", i0)); + this.MLDSA_NAME[i0].configure(this); + + this.MLDSA_NAME[i0].build(); + this.default_map.add_reg(this.MLDSA_NAME[i0], 'h0 + i0*'h4); + end + foreach(this.MLDSA_VERSION[i0]) begin + this.MLDSA_VERSION[i0] = new($sformatf("MLDSA_VERSION[%0d]", i0)); + this.MLDSA_VERSION[i0].configure(this); + + this.MLDSA_VERSION[i0].build(); + this.default_map.add_reg(this.MLDSA_VERSION[i0], 'h8 + i0*'h4); + end + this.MLDSA_CTRL = new("MLDSA_CTRL"); + this.MLDSA_CTRL.configure(this); + + this.MLDSA_CTRL.build(); + this.default_map.add_reg(this.MLDSA_CTRL, 'h10); + this.MLDSA_STATUS = new("MLDSA_STATUS"); + this.MLDSA_STATUS.configure(this); + + this.MLDSA_STATUS.build(); + this.default_map.add_reg(this.MLDSA_STATUS, 'h14); + foreach(this.MLDSA_ENTROPY[i0]) begin + this.MLDSA_ENTROPY[i0] = new($sformatf("MLDSA_ENTROPY[%0d]", i0)); + this.MLDSA_ENTROPY[i0].configure(this); + + this.MLDSA_ENTROPY[i0].build(); + this.default_map.add_reg(this.MLDSA_ENTROPY[i0], 'h18 + i0*'h4); + end + foreach(this.MLDSA_SEED[i0]) begin + this.MLDSA_SEED[i0] = new($sformatf("MLDSA_SEED[%0d]", i0)); + this.MLDSA_SEED[i0].configure(this); + + this.MLDSA_SEED[i0].build(); + this.default_map.add_reg(this.MLDSA_SEED[i0], 'h58 + i0*'h4); + end + foreach(this.MLDSA_SIGN_RND[i0]) begin + this.MLDSA_SIGN_RND[i0] = new($sformatf("MLDSA_SIGN_RND[%0d]", i0)); + this.MLDSA_SIGN_RND[i0].configure(this); + + this.MLDSA_SIGN_RND[i0].build(); + this.default_map.add_reg(this.MLDSA_SIGN_RND[i0], 'h78 + i0*'h4); + end + foreach(this.MLDSA_MSG[i0]) begin + this.MLDSA_MSG[i0] = new($sformatf("MLDSA_MSG[%0d]", i0)); + this.MLDSA_MSG[i0].configure(this); + + this.MLDSA_MSG[i0].build(); + this.default_map.add_reg(this.MLDSA_MSG[i0], 'h98 + i0*'h4); + end + foreach(this.MLDSA_VERIFY_RES[i0]) begin + this.MLDSA_VERIFY_RES[i0] = new($sformatf("MLDSA_VERIFY_RES[%0d]", i0)); + this.MLDSA_VERIFY_RES[i0].configure(this); + + this.MLDSA_VERIFY_RES[i0].build(); + this.default_map.add_reg(this.MLDSA_VERIFY_RES[i0], 'hd8 + i0*'h4); + end + foreach(this.MLDSA_EXTERNAL_MU[i0]) begin + this.MLDSA_EXTERNAL_MU[i0] = new($sformatf("MLDSA_EXTERNAL_MU[%0d]", i0)); + this.MLDSA_EXTERNAL_MU[i0].configure(this); + + this.MLDSA_EXTERNAL_MU[i0].build(); + this.default_map.add_reg(this.MLDSA_EXTERNAL_MU[i0], 'h118 + i0*'h4); + end + this.MLDSA_PUBKEY = new("MLDSA_PUBKEY"); + this.MLDSA_PUBKEY.configure(this); + this.MLDSA_PUBKEY.build(); + this.default_map.add_submap(this.MLDSA_PUBKEY.default_map, 'h1000); + this.MLDSA_SIGNATURE = new("MLDSA_SIGNATURE"); + this.MLDSA_SIGNATURE.configure(this); + this.MLDSA_SIGNATURE.build(); + this.default_map.add_submap(this.MLDSA_SIGNATURE.default_map, 'h2000); + this.MLDSA_PRIVKEY_OUT = new("MLDSA_PRIVKEY_OUT"); + this.MLDSA_PRIVKEY_OUT.configure(this); + this.MLDSA_PRIVKEY_OUT.build(); + this.default_map.add_submap(this.MLDSA_PRIVKEY_OUT.default_map, 'h4000); + this.MLDSA_PRIVKEY_IN = new("MLDSA_PRIVKEY_IN"); + this.MLDSA_PRIVKEY_IN.configure(this); + this.MLDSA_PRIVKEY_IN.build(); + this.default_map.add_submap(this.MLDSA_PRIVKEY_IN.default_map, 'h6000); + this.mldsa_kv_rd_seed_ctrl = new("mldsa_kv_rd_seed_ctrl"); + this.mldsa_kv_rd_seed_ctrl.configure(this); + + this.mldsa_kv_rd_seed_ctrl.build(); + this.default_map.add_reg(this.mldsa_kv_rd_seed_ctrl, 'h8000); + this.mldsa_kv_rd_seed_status = new("mldsa_kv_rd_seed_status"); + this.mldsa_kv_rd_seed_status.configure(this); + + this.mldsa_kv_rd_seed_status.build(); + this.default_map.add_reg(this.mldsa_kv_rd_seed_status, 'h8004); + this.intr_block_rf = new("intr_block_rf"); + this.intr_block_rf.configure(this); + this.intr_block_rf.build(); + this.default_map.add_submap(this.intr_block_rf.default_map, 'h8100); + endfunction : build + endclass : mldsa_reg + + `include "mldsa_reg_sample.svh" +endpackage: mldsa_reg_uvm diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_seq_prim.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_seq_prim.sv new file mode 100644 index 0000000000000000000000000000000000000000..96610268fabff5567c6e0fb1b0e017c89d675eee --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_seq_prim.sv @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Sequencer for MLDSA +//MLDSA functions +// Keygen +// Signing - challenge generation +// Verify + +`include "mldsa_config_defines.svh" + +module mldsa_seq_prim + import mldsa_ctrl_pkg::*; + ( + input logic clk, + + input logic en_i, + input logic [MLDSA_PROG_ADDR_W-1 : 0] addr_i, + output mldsa_seq_instr_t data_o + ); + + +`ifdef RV_FPGA_OPTIMIZE + (*rom_style = "block" *) mldsa_seq_instr_t data_o_rom; +`else + mldsa_seq_instr_t data_o_rom; +`endif + assign data_o = data_o_rom; + + //---------------------------------------------------------------- + // ROM content + //---------------------------------------------------------------- + + always_ff @(posedge clk) begin + if (en_i) begin + unique case(addr_i) + //RESET + MLDSA_RESET : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //ZEROIZE + MLDSA_ZEROIZE : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //KEYGEN + //rnd_seed=Keccak(entropy||counter) + MLDSA_KG_S : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_ENTROPY_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_KG_S+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:'d08, operand1:MLDSA_CNT_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_LFSR_SEED_REG_ID}; + MLDSA_KG_S+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_LFSR, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //(p,p',K)=Keccak(seed) + // //SHAKE256 operation //SRC //SRC2 //DEST + MLDSA_KG_S+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0708, length:'d34, operand1:MLDSA_SEED_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_K_RHO_REG_ID}; + //s1=expandS + // //Rej Bounded op //SRC imm //SRC1 //SRC2 //DEST + MLDSA_KG_S+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0000, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_0_BASE}; + MLDSA_KG_S+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0001, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_1_BASE}; + MLDSA_KG_S+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0002, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_2_BASE}; + MLDSA_KG_S+ 7 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0003, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_3_BASE}; + MLDSA_KG_S+ 8 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0004, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_4_BASE}; + MLDSA_KG_S+ 9 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0005, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_5_BASE}; + MLDSA_KG_S+ 10 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0006, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S1_6_BASE}; + //s1=expandS + MLDSA_KG_S+ 11 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0007, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_0_BASE}; + MLDSA_KG_S+ 12 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0008, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_1_BASE}; + MLDSA_KG_S+ 13 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h0009, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_2_BASE}; + MLDSA_KG_S+ 14 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h000A, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_3_BASE}; + MLDSA_KG_S+ 15 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h000B, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_4_BASE}; + MLDSA_KG_S+ 16 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h000C, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_5_BASE}; + MLDSA_KG_S+ 17 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h000D, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_6_BASE}; + MLDSA_KG_S+ 18 : data_o_rom <= '{opcode:MLDSA_UOP_REJB, imm:'h000E, length:'d66, operand1:MLDSA_RHO_P_ID, operand2:MLDSA_NOP, operand3:MLDSA_S2_7_BASE}; + //NTT(s1) + MLDSA_KG_S+ 19 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_0_NTT_BASE}; + MLDSA_KG_S+ 20 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_1_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_1_NTT_BASE}; + MLDSA_KG_S+ 21 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_2_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_2_NTT_BASE}; + MLDSA_KG_S+ 22 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_3_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_3_NTT_BASE}; + MLDSA_KG_S+ 23 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_4_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_4_NTT_BASE}; + MLDSA_KG_S+ 24 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_5_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_5_NTT_BASE}; + MLDSA_KG_S+ 25 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_6_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_6_NTT_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 26 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0000, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 27 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0001, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 28 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0002, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 29 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0003, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 30 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0004, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 31 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0005, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 32 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0006, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 33 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 34 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_0_BASE, operand3:MLDSA_T0_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 35 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0100, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 36 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0101, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 37 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0102, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 38 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0103, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 39 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0104, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 40 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0105, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 41 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0106, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 42 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 43 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_1_BASE, operand3:MLDSA_T1_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 44 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0200, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 45 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0201, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 46 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0202, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 47 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0203, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 48 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0204, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 49 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0205, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 50 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0206, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 51 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 52 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_2_BASE, operand3:MLDSA_T2_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 53 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0300, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 54 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0301, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 55 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0302, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 56 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0303, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 57 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0304, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 58 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0305, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 59 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0306, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 60 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 61 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_3_BASE, operand3:MLDSA_T3_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 62 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0400, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 63 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0401, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 64 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0402, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 65 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0403, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 66 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0404, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 67 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0405, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 68 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0406, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 69 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 70 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_4_BASE, operand3:MLDSA_T4_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 71 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0500, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 72 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0501, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 73 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0502, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 74 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0503, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 75 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0504, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 76 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0505, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 77 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0506, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 78 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 79 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_5_BASE, operand3:MLDSA_T5_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 80 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0600, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 81 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0601, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 82 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0602, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 83 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0603, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 84 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0604, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 85 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0605, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 86 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0606, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 87 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 88 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_6_BASE, operand3:MLDSA_T6_BASE}; + //ExpandA(ρ) AND Aˆ NTT(s1) + MLDSA_KG_S+ 89 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0700, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_0_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 90 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0701, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_1_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 91 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0702, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_2_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 92 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0703, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_3_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 93 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0704, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_4_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 94 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0705, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_5_NTT_BASE, operand3:MLDSA_AS0_BASE}; + MLDSA_KG_S+ 95 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0706, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_S1_6_NTT_BASE, operand3:MLDSA_AS0_BASE}; + //NTT−1(Aˆ ◦NTT(s1)) + MLDSA_KG_S+ 96 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'d01, length:'d00, operand1:MLDSA_AS0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_AS0_INTT_BASE}; + //t ←NTT−1(Aˆ ◦NTT(s1))+s2 + MLDSA_KG_S+ 97 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'d00, length:'d00, operand1:MLDSA_AS0_INTT_BASE, operand2:MLDSA_S2_7_BASE, operand3:MLDSA_T7_BASE}; + //(t1,t0)←Power2Round(t,d) AND pk ←pkEncode(ρ,t1) + MLDSA_KG_S+ 98 : data_o_rom <= '{opcode:MLDSA_UOP_PWR2RND, imm:'h0000, length:'d00, operand1:MLDSA_T0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_SK_T0_OFFSET}; + //tr ←H(BytesToBits(pk),512) + MLDSA_KG_S+ 99 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:PUBKEY_NUM_BYTES, operand1:MLDSA_PK_REG_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_TR_REG_ID}; + //sk ←skEncode(ρ,K,tr,s1,s2,t0) + MLDSA_KG_S+ 100 : data_o_rom <= '{opcode:MLDSA_UOP_SKENCODE, imm:'h0000, length:'d00, operand1:MLDSA_S1_0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_KG_JUMP_SIGN : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //KG end + MLDSA_KG_E : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //Signing start + //rnd_seed=Keccak(entropy||counter) + MLDSA_SIGN_S : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_ENTROPY_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_S+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:'d08, operand1:MLDSA_CNT_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_LFSR_SEED_REG_ID}; + MLDSA_SIGN_S+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_LFSR, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_CHECK_MODE : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //μ ←H(tr||M,512) + MLDSA_SIGN_H_MU : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_TR_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_H_MU + 1 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:'d66, operand1:MLDSA_MSG_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_MU_REG_ID}; + //ρ′=Keccak(K||rnd|| μ) + MLDSA_SIGN_H_RHO_P : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d32, operand1:MLDSA_K_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_H_RHO_P+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d32, operand1:MLDSA_SIGN_RND_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_H_RHO_P+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_MU_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_RHO_P_REG_ID}; + //Check Y valid + MLDSA_SIGN_CHECK_Y_CLR : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_UOP_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //lfsr_seed=Keccak(re_entropy||counter) + MLDSA_SIGN_LFSR_S : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_ENTROPY_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_LFSR_S+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:'d08, operand1:MLDSA_CNT_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_LFSR_SEED_REG_ID}; + MLDSA_SIGN_LFSR_S+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_LFSR, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //y=ExpandMask(ρ’ ,κ) + MLDSA_SIGN_MAKE_Y_S : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0000, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_0_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0001, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_1_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0002, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_2_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0003, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_3_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0004, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_4_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0005, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_5_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_EXP_MASK, imm:'h0006, length:'d66, operand1:MLDSA_RHO_P_KAPPA_ID, operand2:MLDSA_NOP, operand3:MLDSA_Y_6_BASE}; + //NTT(Y) + MLDSA_SIGN_MAKE_Y_S+ 7 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_0_NTT_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 8 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_1_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_1_NTT_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 9 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_2_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_2_NTT_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 10 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_3_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_3_NTT_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 11 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_4_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_4_NTT_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 12 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_5_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_5_NTT_BASE}; + MLDSA_SIGN_MAKE_Y_S+ 13 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0001, length:'d00, operand1:MLDSA_Y_6_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_Y_6_NTT_BASE}; + //Check W0 clear + MLDSA_SIGN_CHECK_W0_CLR : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //Aˆ ←ExpandA(ρ) AND Aˆ ◦NTT(y) + MLDSA_SIGN_MAKE_W_S : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0000, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0001, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0002, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0003, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0004, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0005, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0006, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 7 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 8 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0100, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 9 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0101, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 10 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0102, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 11 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0103, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 12 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0104, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 13 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0105, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 14 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0106, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 15 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_1_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 16 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0200, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 17 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0201, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 18 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0202, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 19 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0203, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 20 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0204, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 21 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0205, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 22 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0206, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 23 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_2_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 24 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0300, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 25 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0301, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 26 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0302, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 27 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0303, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 28 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0304, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 29 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0305, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 30 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0306, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 31 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_3_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 32 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0400, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 33 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0401, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 34 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0402, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 35 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0403, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 36 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0404, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 37 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0405, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 38 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0406, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 39 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_4_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 40 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0500, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 41 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0501, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 42 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0502, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 43 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0503, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 44 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0504, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 45 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0505, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 46 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0506, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 47 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_5_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 48 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0600, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 49 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0601, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 50 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0602, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 51 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0603, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 52 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0604, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 53 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0605, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 54 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0606, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 55 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_6_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 56 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0700, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_0_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 57 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0701, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_1_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 58 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0702, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_2_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 59 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0703, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_3_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 60 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0704, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_4_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 61 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0705, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_5_NTT_BASE, operand3:MLDSA_AY0_BASE}; + MLDSA_SIGN_MAKE_W_S+ 62 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0706, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Y_6_NTT_BASE, operand3:MLDSA_AY0_BASE}; + + MLDSA_SIGN_MAKE_W_S+ 63 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0001, length:'d00, operand1:MLDSA_AY0_BASE, operand2:MLDSA_TEMP3_BASE, operand3:MLDSA_W0_7_BASE}; + + //Set Y valid //FIXME this can move before MAKE_W if we opt accumulator to not have to read dest + MLDSA_SIGN_SET_Y : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_UOP_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //(w1,w0) ←Decompose(w) AND c˜←H(μ||w1Encode(w1),2λ) + MLDSA_SIGN_MAKE_W_S+ 65 : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_MU_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_MAKE_W : data_o_rom <= '{opcode:MLDSA_UOP_DECOMP, imm:'h0000, length:'d00, operand1:MLDSA_W0_0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_W0_0_BASE}; + MLDSA_SIGN_SET_W0 : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + // c ←SampleInBall(c˜1) + //Check C clear + MLDSA_SIGN_CHECK_C_CLR : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_MAKE_C : data_o_rom <= '{opcode:MLDSA_UOP_RUN_SHAKE256, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_DEST_SIG_C_REG_ID}; + MLDSA_SIGN_MAKE_C+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_SIB, imm:'h0000, length:'d64, operand1:MLDSA_SIG_C_REG_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_SET_C : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + MLDSA_SIGN_CHL_E : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_E : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //Verify flow + //(ρ,t1)←pkDecode(pk) + MLDSA_VERIFY_S : data_o_rom <= '{opcode:MLDSA_UOP_PKDECODE, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_T0_BASE}; + //(c˜,z,h)←sigDecode(σ) + MLDSA_VERIFY_S+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_SIGDEC_Z, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_Z_0_BASE}; + //||z||∞ ≥ γ1 −β + MLDSA_VERIFY_S+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_S+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_1_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_S+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_2_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_S+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_3_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_S+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_4_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_S+ 7 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_5_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_S+ 8 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_6_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //tr ←H(pk,512) + MLDSA_VERIFY_H_TR : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:PUBKEY_NUM_BYTES, operand1:MLDSA_PK_REG_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_TR_REG_ID}; + MLDSA_VERIFY_CHECK_MODE : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //μ ←H(tr||M,512) + MLDSA_VERIFY_H_MU : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_TR_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_H_MU+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_SHAKE256, imm:'h0000, length:'d66, operand1:MLDSA_MSG_ID, operand2:MLDSA_NOP, operand3:MLDSA_DEST_MU_REG_ID}; + //c ←SampleInBall(c˜1) + MLDSA_VERIFY_MAKE_C : data_o_rom <= '{opcode:MLDSA_UOP_SIB, imm:'h0000, length:'d64, operand1:MLDSA_SIG_C_REG_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //cˆ ←NTT(c) + MLDSA_VERIFY_NTT_C : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_C_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_C_NTT_BASE}; + //t1 ←NTT(t1) + MLDSA_VERIFY_NTT_T1 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T0_BASE}; + MLDSA_VERIFY_NTT_T1+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T1_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T1_BASE}; + MLDSA_VERIFY_NTT_T1+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T2_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T2_BASE}; + MLDSA_VERIFY_NTT_T1+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T3_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T3_BASE}; + MLDSA_VERIFY_NTT_T1+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T4_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T4_BASE}; + MLDSA_VERIFY_NTT_T1+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T5_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T5_BASE}; + MLDSA_VERIFY_NTT_T1+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T6_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T6_BASE}; + MLDSA_VERIFY_NTT_T1+ 7 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T7_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T7_BASE}; + + //z ←NTT(z) + MLDSA_VERIFY_NTT_Z : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_0_BASE}; + MLDSA_VERIFY_NTT_Z+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_1_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_1_BASE}; + MLDSA_VERIFY_NTT_Z+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_2_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_2_BASE}; + MLDSA_VERIFY_NTT_Z+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_3_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_3_BASE}; + MLDSA_VERIFY_NTT_Z+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_4_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_4_BASE}; + MLDSA_VERIFY_NTT_Z+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_5_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_5_BASE}; + MLDSA_VERIFY_NTT_Z+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_Z_6_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_Z_NTT_6_BASE}; + //Aˆ ←ExpandA(ρ) AND Aˆ ◦NTT(z) + MLDSA_VERIFY_EXP_A+ 0 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0000, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0001, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0002, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0003, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 4 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0004, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 5 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0005, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 6 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0006, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 7 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T0_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 8 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 9 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_0_BASE}; + + MLDSA_VERIFY_EXP_A+ 10 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0100, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 11 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0101, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 12 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0102, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 13 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0103, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 14 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0104, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 15 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0105, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 16 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0106, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 17 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T1_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 18 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 19 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_1_BASE}; + + MLDSA_VERIFY_EXP_A+ 20 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0200, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 21 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0201, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 22 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0202, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 23 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0203, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 24 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0204, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 25 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0205, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 26 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0206, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 27 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T2_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 28 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 29 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_2_BASE}; + + MLDSA_VERIFY_EXP_A+ 30 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0300, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 31 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0301, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 32 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0302, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 33 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0303, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 34 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0304, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 35 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0305, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 36 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0306, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 37 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T3_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 38 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 39 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_3_BASE}; + + MLDSA_VERIFY_EXP_A+ 40 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0400, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 41 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0401, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 42 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0402, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 43 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0403, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 44 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0404, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 45 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0405, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 46 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0406, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 47 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T4_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 48 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 49 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_4_BASE}; + + MLDSA_VERIFY_EXP_A+ 50 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0500, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 51 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0501, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 52 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0502, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 53 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0503, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 54 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0504, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 55 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0505, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 56 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0506, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 57 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T5_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 58 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 59 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_5_BASE}; + + MLDSA_VERIFY_EXP_A+ 60 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0600, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 61 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0601, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 62 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0602, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 63 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0603, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 64 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0604, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 65 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0605, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 66 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0606, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 67 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T6_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 68 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 69 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_6_BASE}; + + MLDSA_VERIFY_EXP_A+ 70 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWM, imm:'h0700, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 71 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0701, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_1_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 72 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0702, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_2_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 73 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0703, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_3_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 74 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0704, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_4_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 75 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0705, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_5_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 76 : data_o_rom <= '{opcode:MLDSA_UOP_REJS_PWMA, imm:'h0706, length:'d34, operand1:MLDSA_RHO_ID, operand2:MLDSA_Z_NTT_6_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 77 : data_o_rom <= '{opcode:MLDSA_UOP_PWM, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T7_BASE, operand3:MLDSA_CT_BASE}; + MLDSA_VERIFY_EXP_A+ 78 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CT_BASE, operand2:MLDSA_AZ0_BASE, operand3:MLDSA_AZ0_BASE}; + MLDSA_VERIFY_EXP_A+ 79 : data_o_rom <= '{opcode:MLDSA_UOP_INTT, imm:'h0000, length:'d00, operand1:MLDSA_AZ0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_W0_7_BASE}; + + MLDSA_VERIFY_RES+ 0 : data_o_rom <= '{opcode:MLDSA_UOP_SIGDEC_H, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_HINT_R_0_BASE}; + MLDSA_VERIFY_RES+ 1 : data_o_rom <= '{opcode:MLDSA_UOP_LD_SHAKE256, imm:'h0000, length:'d64, operand1:MLDSA_MU_ID, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_VERIFY_RES+ 2 : data_o_rom <= '{opcode:MLDSA_UOP_USEHINT, imm:'h0000, length:'d00, operand1:MLDSA_W0_0_BASE, operand2:MLDSA_HINT_R_0_BASE, operand3:MLDSA_NOP}; + MLDSA_VERIFY_RES+ 3 : data_o_rom <= '{opcode:MLDSA_UOP_RUN_SHAKE256, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_DEST_VERIFY_RES_REG_ID}; + MLDSA_VERIFY_E : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + default : data_o_rom <= '{opcode: MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + endcase + end + else begin + data_o_rom <= '{opcode: MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + end +end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_seq_sec.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_seq_sec.sv new file mode 100644 index 0000000000000000000000000000000000000000..a7da1faf8084a01bf7c9c040d8425e3aecab1549 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_seq_sec.sv @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Sequencer for MLDSA +//MLDSA functions +// Signing initial steps +// Signing validity checks +// Signing signature generation + +`include "mldsa_config_defines.svh" + +module mldsa_seq_sec + import mldsa_ctrl_pkg::*; + ( + input logic clk, + + input logic en_i, + input logic [MLDSA_PROG_ADDR_W-1 : 0] addr_i, + output mldsa_seq_instr_t data_o + ); + + +`ifdef RV_FPGA_OPTIMIZE + (*rom_style = "block" *) mldsa_seq_instr_t data_o_rom; +`else + mldsa_seq_instr_t data_o_rom; +`endif + assign data_o = data_o_rom; + + + //---------------------------------------------------------------- + // ROM content + //---------------------------------------------------------------- + + always_ff @(posedge clk) begin + if (en_i) begin + unique case(addr_i) + //RESET + MLDSA_RESET : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //ZEROIZE + MLDSA_ZEROIZE : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //Signing initial steps start + MLDSA_SIGN_INIT_S : data_o_rom <= '{opcode:MLDSA_UOP_SKDECODE, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_S1_0_BASE}; + //NTT(t0) + MLDSA_SIGN_INIT_S+1 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T0_BASE}; + MLDSA_SIGN_INIT_S+2 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T1_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T1_BASE}; + MLDSA_SIGN_INIT_S+3 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T2_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T2_BASE}; + MLDSA_SIGN_INIT_S+4 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T3_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T3_BASE}; + MLDSA_SIGN_INIT_S+5 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T4_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T4_BASE}; + MLDSA_SIGN_INIT_S+6 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T5_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T5_BASE}; + MLDSA_SIGN_INIT_S+7 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T6_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T6_BASE}; + MLDSA_SIGN_INIT_S+8 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_T7_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_T7_BASE}; + //NTT(s1) + MLDSA_SIGN_INIT_S+9 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_0_BASE}; + MLDSA_SIGN_INIT_S+10 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_1_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_1_BASE}; + MLDSA_SIGN_INIT_S+11: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_2_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_2_BASE}; + MLDSA_SIGN_INIT_S+12: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_3_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_3_BASE}; + MLDSA_SIGN_INIT_S+13: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_4_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_4_BASE}; + MLDSA_SIGN_INIT_S+14: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_5_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_5_BASE}; + MLDSA_SIGN_INIT_S+15: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S1_6_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S1_6_BASE}; + //NTT(s2) + MLDSA_SIGN_INIT_S+16: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_0_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_0_BASE}; + MLDSA_SIGN_INIT_S+17: data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_1_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_1_BASE}; + MLDSA_SIGN_INIT_S+18 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_2_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_2_BASE}; + MLDSA_SIGN_INIT_S+19 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_3_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_3_BASE}; + MLDSA_SIGN_INIT_S+20 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_4_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_4_BASE}; + MLDSA_SIGN_INIT_S+21 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_5_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_5_BASE}; + MLDSA_SIGN_INIT_S+22 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_6_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_6_BASE}; + MLDSA_SIGN_INIT_S+23 : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_S2_7_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_S2_7_BASE}; + //Signing validity checks + MLDSA_SIGN_CHECK_C_VLD : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + //NTT(C) + MLDSA_SIGN_VALID_S : data_o_rom <= '{opcode:MLDSA_UOP_NTT, imm:'h0000, length:'d00, operand1:MLDSA_C_BASE, operand2:MLDSA_TEMP0_BASE, operand3:MLDSA_C_NTT_BASE}; + + //Compute Z and perform norm check + MLDSA_SIGN_CHECK_Y_VLD : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+2 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_0_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+3 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_0_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+4 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+5 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h000}; + + MLDSA_SIGN_VALID_S+6 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_1_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+7 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_1_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+8 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+9 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h040}; + + MLDSA_SIGN_VALID_S+10 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_2_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+11 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_2_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+12 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+13 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h080}; + + MLDSA_SIGN_VALID_S+14 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_3_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+15 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_3_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+16 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+17 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h0C0}; + + MLDSA_SIGN_VALID_S+18 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_4_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+19 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_4_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+20 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+21 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h100}; + + MLDSA_SIGN_VALID_S+22 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_5_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+23 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_5_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+24 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+25 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h140}; + + MLDSA_SIGN_VALID_S+26 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S1_6_BASE, operand3:MLDSA_CS1_BASE}; + MLDSA_SIGN_VALID_S+27 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_Y_6_BASE, operand2:MLDSA_CS1_BASE, operand3:MLDSA_Z_BASE}; + MLDSA_SIGN_VALID_S+28 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_Z, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+29 : data_o_rom <= '{opcode:MLDSA_UOP_SIGENCODE, imm:'h0000, length:'d00, operand1:MLDSA_Z_BASE, operand2:MLDSA_NOP, operand3:15'h180}; + + MLDSA_SIGN_CLEAR_Y : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + MLDSA_SIGN_VALID_S+31 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T0_BASE, operand3:MLDSA_CT_0_BASE}; + MLDSA_SIGN_VALID_S+32 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T1_BASE, operand3:MLDSA_CT_1_BASE}; + MLDSA_SIGN_VALID_S+33 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T2_BASE, operand3:MLDSA_CT_2_BASE}; + MLDSA_SIGN_VALID_S+34 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T3_BASE, operand3:MLDSA_CT_3_BASE}; + MLDSA_SIGN_VALID_S+35 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T4_BASE, operand3:MLDSA_CT_4_BASE}; + MLDSA_SIGN_VALID_S+36 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T5_BASE, operand3:MLDSA_CT_5_BASE}; + MLDSA_SIGN_VALID_S+37 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T6_BASE, operand3:MLDSA_CT_6_BASE}; + MLDSA_SIGN_VALID_S+38 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_T7_BASE, operand3:MLDSA_CT_7_BASE}; + + MLDSA_SIGN_CHECK_W0_VLD : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + //Make R0, CT0 and Hint_r + MLDSA_SIGN_VALID_S+40 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_0_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+41 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_0_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+42 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+43 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+44 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_0_BASE, operand3:MLDSA_HINT_R_0_BASE}; + + MLDSA_SIGN_VALID_S+45 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_1_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+46 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_1_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+47 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+48 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_1_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+49 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_1_BASE, operand3:MLDSA_HINT_R_1_BASE}; + + MLDSA_SIGN_VALID_S+50 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_2_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+51 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_2_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+52 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+53 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_2_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+54 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_2_BASE, operand3:MLDSA_HINT_R_2_BASE}; + + MLDSA_SIGN_VALID_S+55 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_3_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+56 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_3_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+57 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+58 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_3_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+59 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_3_BASE, operand3:MLDSA_HINT_R_3_BASE}; + + MLDSA_SIGN_VALID_S+60 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_4_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+61 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_4_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+62 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+63 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_4_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+64 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_4_BASE, operand3:MLDSA_HINT_R_4_BASE}; + + MLDSA_SIGN_VALID_S+65 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_5_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+66 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_5_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+67 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+68 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_5_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+69 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_5_BASE, operand3:MLDSA_HINT_R_5_BASE}; + + MLDSA_SIGN_VALID_S+70 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_6_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+71 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_6_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+72 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+73 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_6_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+74 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_6_BASE, operand3:MLDSA_HINT_R_6_BASE}; + + MLDSA_SIGN_VALID_S+75 : data_o_rom <= '{opcode:MLDSA_UOP_MASKED_PWM_INTT, imm:'h0000, length:'d00, operand1:MLDSA_C_NTT_BASE, operand2:MLDSA_S2_7_BASE, operand3:MLDSA_CS2_BASE}; + MLDSA_SIGN_VALID_S+76 : data_o_rom <= '{opcode:MLDSA_UOP_PWS, imm:'h0000, length:'d00, operand1:MLDSA_CS2_BASE, operand2:MLDSA_W0_7_BASE, operand3:MLDSA_R0_BASE}; + MLDSA_SIGN_VALID_S+77 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_R0, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+78 : data_o_rom <= '{opcode:MLDSA_UOP_NORMCHK, imm:MLDSA_NORMCHK_CT0, length:'d00, operand1:MLDSA_CT_7_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_VALID_S+79 : data_o_rom <= '{opcode:MLDSA_UOP_PWA, imm:'h0000, length:'d00, operand1:MLDSA_R0_BASE, operand2:MLDSA_CT_7_BASE, operand3:MLDSA_HINT_R_7_BASE}; + + MLDSA_SIGN_CLEAR_W0 : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + MLDSA_SIGN_VALID_S+81 : data_o_rom <= '{opcode:MLDSA_UOP_MAKEHINT, imm:'h0000, length:'d00, operand1:MLDSA_HINT_R_0_BASE, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + + MLDSA_SIGN_GEN_S : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_CLEAR_C : data_o_rom <= '{opcode:MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + MLDSA_SIGN_GEN_E : data_o_rom <= '{opcode: MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + default : data_o_rom <= '{opcode: MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + endcase + end + else begin + data_o_rom <= '{opcode: MLDSA_UOP_NOP, imm:'h0000, length:'d00, operand1:MLDSA_NOP, operand2:MLDSA_NOP, operand3:MLDSA_NOP}; + end +end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..35d6132ec2c91f7f6716011c354760098bfc3879 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/rtl/mldsa_top.sv @@ -0,0 +1,1280 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Initial top level module +`include "mldsa_config_defines.svh" +`include "abr_prim_assert.sv" + +module mldsa_top + import abr_prim_alert_pkg::*; + import mldsa_reg_pkg::*; + import mldsa_params_pkg::*; + import mldsa_ctrl_pkg::*; + import mldsa_sampler_pkg::*; + import abr_sha3_pkg::*; + import ntt_defines_pkg::*; + import decompose_defines_pkg::*; + `ifdef CALIPTRA + import kv_defines_pkg::*; + `endif + #( + //top level params + parameter AHB_ADDR_WIDTH = 32, + parameter AHB_DATA_WIDTH = 64, + parameter CLIENT_DATA_WIDTH = 32 + ) + ( + input logic clk, + input logic rst_b, + +`ifdef RV_FPGA_SCA + output wire NTT_trigger, + output wire PWM_trigger, + output wire PWA_trigger, + output wire INTT_trigger, +`endif + + + //ahb input + input logic [AHB_ADDR_WIDTH-1:0] haddr_i, + input logic [AHB_DATA_WIDTH-1:0] hwdata_i, + input logic hsel_i, + input logic hwrite_i, + input logic hready_i, + input logic [1:0] htrans_i, + input logic [2:0] hsize_i, + + //ahb output + output logic hresp_o, + output logic hreadyout_o, + output logic [AHB_DATA_WIDTH-1:0] hrdata_o, + + mldsa_mem_if.req mldsa_memory_export, + + `ifdef CALIPTRA + // KV interface + output kv_read_t kv_read, + input kv_rd_resp_t kv_rd_resp, + //PCR Signing + input pcr_signing_t pcr_signing_data, + `endif + //Zeroize the engine if entering debug or scan mode + input logic debugUnlock_or_scan_mode_switch, + + output logic busy_o, + + output logic error_intr, + output logic notif_intr + + + ); + + localparam DATA_WIDTH = 32; + +//Signal Declarations + logic zeroize_reg; + + mldsa_sampler_mode_e sampler_mode; + logic sha3_start; + logic msg_start; + logic msg_valid; + logic msg_rdy; + logic [MsgStrbW-1:0] msg_strobe; + logic [MsgWidth-1:0] msg_data[Sha3Share]; + logic sampler_start; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr; + + logic sampler_busy; + logic sampler_state_dv; + logic [abr_sha3_pkg::StateW-1:0] sampler_state_data[Sha3Share]; + + logic sampler_mem_dv; + logic [MLDSA_MEM_DATA_WIDTH-1:0] sampler_mem_data; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] sampler_mem_addr; + + logic [1:0] sampler_ntt_dv, sampler_ntt_dv_f; + logic [1:0] sampler_ntt_mode; + logic [1:0] sampler_valid; + logic [COEFF_PER_CLK-1:0][MLDSA_Q_WIDTH-1:0] sampler_ntt_data; + + mldsa_ntt_mode_e [1:0] ntt_mode; + mode_t [1:0] mode; + logic [1:0] accumulate; + logic [1:0] ntt_enable; + ntt_mem_addr_t [1:0] ntt_mem_base_addr; + pwo_mem_addr_t [1:0] pwo_mem_base_addr; + mem_if_t [1:0] ntt_mem_wr_req; + mem_if_t [1:0] ntt_mem_rd_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_wr_data; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_rd_data; + mem_if_t [1:0] pwm_a_rd_req; + mem_if_t [1:0] pwm_b_rd_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] pwm_a_rd_data; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] pwm_b_rd_data; + logic [1:0] ntt_done; + logic [1:0] ntt_busy; + logic [1:0] ntt_random_en; + logic [1:0] ntt_shuffling_en; + logic [1:0] ntt_masking_en; + + mem_if_t w1_mem_wr_req; + logic [MLDSA_MEM_W1_DATA_W-1:0] w1_mem_wr_data; + mem_if_t w1_mem_rd_req; + logic [MLDSA_MEM_W1_DATA_W-1:0] w1_mem_rd_data; + + logic decomp_msg_valid; + logic [MsgWidth-1:0] decomp_msg_data[Sha3Share]; + + logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] aux_src0_base_addr; + logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] aux_src1_base_addr; + logic [1:0][MLDSA_MEM_ADDR_WIDTH-1:0] aux_dest_base_addr; + + logic power2round_enable, power2round_done; + mem_if_t [1:0] pwr2rnd_mem_rd_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] pwr2rnd_mem_rd_data; + mem_if_t [1:0] pwr2rnd_keymem_if; + logic [1:0] [DATA_WIDTH-1:0] pwr2rnd_wr_data; + logic pk_t1_wren; + logic [7:0][9:0] pk_t1_wrdata; // TODO: change to parameter + logic [7:0] pk_t1_wr_addr; // TODO: change to parameter + + logic decompose_enable, decompose_done; + mem_if_t decomp_mem_wr_req; + mem_if_t [1:0] decomp_mem_rd_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] decomp_mem_wr_data; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] decomp_mem_rd_data; + logic decompose_mode; + + logic skencode_enable, skencode_done; + mem_if_t skencode_keymem_if; + logic [DATA_WIDTH-1:0] skencode_wr_data; + mem_if_t [1:0] skencode_mem_rd_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] skencode_mem_rd_data; + + logic skdecode_enable, skdecode_done; + mem_if_t [1:0] skdecode_keymem_if; + logic [1:0][DATA_WIDTH-1:0] skdecode_rd_data; + mem_if_t [1:0] skdecode_mem_wr_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] skdecode_mem_wr_data; + logic skdecode_error; + + logic makehint_enable, makehint_done; + logic makehint_invalid; + mem_if_t makehint_mem_rd_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] makehint_mem_rd_data; + logic makehint_reg_wren; + logic [3:0][7:0] makehint_reg_wrdata; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] makehint_reg_wr_addr; + + logic normcheck_enable; + logic normcheck_done; + logic [1:0] normcheck_mode; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] normcheck_src_addr; + logic normcheck_invalid; + mem_if_t normcheck_mem_rd_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] normcheck_mem_rd_data; + + logic sigencode_enable, sigencode_done; + mem_if_t [1:0] sigencode_mem_rd_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] sigencode_mem_rd_data; + mem_if_t sigencode_mem_wr_req; + logic [1:0][3:0][19:0] sigencode_mem_wr_data; + + logic pkdecode_enable, pkdecode_done; + mem_if_t [1:0] pkdecode_mem_wr_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] pkdecode_mem_wr_data; + logic [7:0] pkdecode_rd_addr; + logic [7:0][T1_COEFF_W-1:0] pkdecode_rd_data; + + logic sigdecode_z_enable, sigdecode_z_done; + mem_if_t [1:0] sigdecode_z_mem_wr_req; + logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] sigdecode_z_mem_wr_data; + mem_if_t sigdecode_z_mem_rd_req; + logic [1:0][3:0][19:0] sigdecode_z_mem_rd_data; + + logic sigdecode_h_enable, sigdecode_h_done; + logic [SIGNATURE_H_VALID_NUM_BYTES-1:0][7:0] signature_h; + logic sigdecode_h_invalid; + mem_if_t sigdecode_h_mem_wr_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] sigdecode_h_mem_wr_data; + + mem_if_t sib_mem_rd_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] sib_mem_rd_data; + + logic lfsr_enable; + logic [1:0][LFSR_W-1:0] lfsr_seed; + logic [RND_W-1:0] rand_bits; + logic [RND_W-7:0] ntt_rand_bits; + + //gasket to assemble reg requests + logic mldsa_reg_dv; + logic mldsa_reg_hold; + logic mldsa_reg_rd_ack, mldsa_reg_wr_ack; + logic [CLIENT_DATA_WIDTH-1:0] mldsa_reg_rdata; + logic [AHB_ADDR_WIDTH-1:0] mldsa_reg_addr; + logic [CLIENT_DATA_WIDTH-1:0] mldsa_reg_wdata; + logic mldsa_reg_write; + + logic mldsa_reg_err, mldsa_reg_read_err, mldsa_reg_write_err; + + mldsa_reg__in_t mldsa_reg_hwif_in; + mldsa_reg__out_t mldsa_reg_hwif_out; + + mem_if_t zeroize_mem; + logic zeroize_mem_we; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] zeroize_mem_addr; + + //memory interfaces + mldsa_sram_if #(.ADDR_W(SK_MEM_BANK_ADDR_W), .DATA_W(SK_MEM_BANK_DATA_W)) sk_bank0_mem_if(); + mldsa_sram_if #(.ADDR_W(SK_MEM_BANK_ADDR_W), .DATA_W(SK_MEM_BANK_DATA_W)) sk_bank1_mem_if(); + mldsa_sram_be_if #(.ADDR_W(SIG_Z_MEM_ADDR_W), .DATA_W(SIG_Z_MEM_DATA_W)) sig_z_mem_if(); + mldsa_sram_be_if #(.ADDR_W(PK_MEM_ADDR_W), .DATA_W(PK_MEM_DATA_W)) pk_mem_if(); + + `ifdef MLDSA_MASKING + assign ntt_rand_bits = rand_bits[RND_W-1:6]; + `else + assign ntt_rand_bits = (RND_W-6)'(0); + `endif + + abr_ahb_slv_sif #( + .AHB_ADDR_WIDTH(AHB_ADDR_WIDTH), + .AHB_DATA_WIDTH(AHB_DATA_WIDTH), + .CLIENT_DATA_WIDTH(CLIENT_DATA_WIDTH) +) + mldsa_ahb_slv_inst ( + //AMBA AHB Lite INF + .hclk(clk), + .hreset_n(rst_b), + .haddr_i(haddr_i), + .hwdata_i(hwdata_i), + .hsel_i(hsel_i), + .hwrite_i(hwrite_i), + .hready_i(hready_i), + .htrans_i(htrans_i), + .hsize_i(hsize_i), + + .hresp_o(hresp_o), + .hreadyout_o(hreadyout_o), + .hrdata_o(hrdata_o), + + //COMPONENT INF + .dv(mldsa_reg_dv), + .hld(mldsa_reg_hold), + .err(mldsa_reg_err), + .write(mldsa_reg_write), + .wdata(mldsa_reg_wdata), + .addr(mldsa_reg_addr[AHB_ADDR_WIDTH-1:0]), + + .rdata(mldsa_reg_rdata) +); + +always_comb mldsa_reg_err = (mldsa_reg_rd_ack & mldsa_reg_read_err) | (mldsa_reg_wr_ack & mldsa_reg_write_err); +always_comb mldsa_reg_hold = mldsa_reg_dv & ~(mldsa_reg_rd_ack | mldsa_reg_wr_ack); //FIXME can we do this without dv? + +mldsa_reg mldsa_reg_inst ( + .clk(clk), + .rst(rst_b), + + .s_cpuif_req(mldsa_reg_dv), + .s_cpuif_req_is_wr(mldsa_reg_write), + .s_cpuif_addr(mldsa_reg_addr[MLDSA_REG_ADDR_WIDTH-1:0]), + .s_cpuif_wr_data(mldsa_reg_wdata), + .s_cpuif_wr_biten('1), + .s_cpuif_req_stall_wr(), + .s_cpuif_req_stall_rd(), + .s_cpuif_rd_ack(mldsa_reg_rd_ack), + .s_cpuif_rd_err(mldsa_reg_read_err), + .s_cpuif_rd_data(mldsa_reg_rdata), + .s_cpuif_wr_ack(mldsa_reg_wr_ack), + .s_cpuif_wr_err(mldsa_reg_write_err), + + .hwif_in(mldsa_reg_hwif_in), + .hwif_out(mldsa_reg_hwif_out) +); + +mldsa_ctrl mldsa_ctrl_inst +( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_reg), + + .sk_bank0_mem_if(sk_bank0_mem_if.req), + .sk_bank1_mem_if(sk_bank1_mem_if.req), + .sig_z_mem_if(sig_z_mem_if.req), + .pk_mem_if(pk_mem_if.req), + +`ifdef RV_FPGA_SCA + .NTT_trigger(NTT_trigger), + .PWM_trigger(PWM_trigger), + .PWA_trigger(PWA_trigger), + .INTT_trigger(INTT_trigger), +`endif + +`ifdef CALIPTRA + .kv_read(kv_read), + .kv_rd_resp(kv_rd_resp), + .pcr_signing_data(pcr_signing_data), +`endif + + //control interface + .mldsa_reg_hwif_in_o(mldsa_reg_hwif_in), + .mldsa_reg_hwif_out_i(mldsa_reg_hwif_out), + + //sampler interface + .sampler_mode_o(sampler_mode), + .sha3_start_o(sha3_start), //start the sha3 engine + .msg_start_o(msg_start), //start a new message + .msg_valid_o(msg_valid), //msg interface valid + .msg_rdy_i(msg_rdy), //msg interface rdy (~hold) + .msg_strobe_o(msg_strobe), //msg byte enables + .msg_data_o(msg_data), + + .sampler_start_o(sampler_start), + .dest_base_addr_o(dest_base_addr), + + .sampler_state_dv_i(sampler_state_dv), + .sampler_state_data_i(sampler_state_data), + .sampler_busy_i(sampler_busy), + + //ntt interface + .ntt_enable_o(ntt_enable), + .ntt_mode_o(ntt_mode), + .ntt_mem_base_addr_o(ntt_mem_base_addr), + .pwo_mem_base_addr_o(pwo_mem_base_addr), + .ntt_masking_en_o(ntt_masking_en), + .ntt_shuffling_en_o(ntt_shuffling_en), + .ntt_busy_i(ntt_busy), + + //aux interface + .aux_src0_base_addr_o(aux_src0_base_addr), + .aux_src1_base_addr_o(aux_src1_base_addr), + .aux_dest_base_addr_o(aux_dest_base_addr), + + .power2round_enable_o(power2round_enable), + .pwr2rnd_keymem_if_i(pwr2rnd_keymem_if), + .pwr2rnd_wr_data_i(pwr2rnd_wr_data), + .pk_t1_wren_i(pk_t1_wren), + .pk_t1_wr_addr_i(pk_t1_wr_addr), + .pk_t1_wrdata_i(pk_t1_wrdata), + .power2round_done_i(power2round_done), + + .decompose_enable_o(decompose_enable), + .decompose_mode_o(decompose_mode), + .decompose_done_i(decompose_done), + + .skdecode_enable_o(skdecode_enable), + .skdecode_keymem_if_i(skdecode_keymem_if), + .skdecode_rd_data_o(skdecode_rd_data), + .skdecode_done_i(skdecode_done), + .skdecode_error_i(skdecode_error), + + .skencode_enable_o(skencode_enable), + .skencode_keymem_if_i(skencode_keymem_if), + .skencode_wr_data_i(skencode_wr_data), + .skencode_done_i(skencode_done), + + .makehint_enable_o(makehint_enable), + .makehint_invalid_i(makehint_invalid), + .makehint_done_i(makehint_done), + .makehint_reg_wren_i(makehint_reg_wren), + .makehint_reg_wr_addr_i(makehint_reg_wr_addr), + .makehint_reg_wrdata_i(makehint_reg_wrdata), + + .normcheck_enable_o(normcheck_enable), + .normcheck_mode_o(normcheck_mode), + .normcheck_src_addr_o(normcheck_src_addr), + .normcheck_invalid_i(normcheck_invalid), + .normcheck_done_i(normcheck_done), + + .sigencode_enable_o(sigencode_enable), + .sigencode_wr_req_i(sigencode_mem_wr_req), + .sigencode_wr_data_i(sigencode_mem_wr_data), + .sigencode_done_i(sigencode_done), + + .pkdecode_enable_o(pkdecode_enable), + .pkdecode_rd_addr_i(pkdecode_rd_addr), + .pkdecode_rd_data_o(pkdecode_rd_data), + .pkdecode_done_i(pkdecode_done), + + .sigdecode_h_enable_o(sigdecode_h_enable), + .signature_h_o(signature_h), + .sigdecode_h_invalid_i(sigdecode_h_invalid), + .sigdecode_h_done_i(sigdecode_h_done), + + .sigdecode_z_enable_o(sigdecode_z_enable), + .sigdecode_z_rd_req_i(sigdecode_z_mem_rd_req), + .sigdecode_z_rd_data_o(sigdecode_z_mem_rd_data), + .sigdecode_z_done_i(sigdecode_z_done), + + .lfsr_enable_o(lfsr_enable), + .lfsr_seed_o(lfsr_seed), + + .busy_o(busy_o), + .zeroize_mem_o(zeroize_mem), + + .error_intr(error_intr), + .notif_intr(notif_intr), + .debugUnlock_or_scan_mode_switch(debugUnlock_or_scan_mode_switch) +); + +always_comb zeroize_mem_we = (zeroize_mem.rd_wr_en == RW_WRITE); +always_comb zeroize_mem_addr = zeroize_mem.addr; + +logic [MsgWidth-1:0] msg_data_i[Sha3Share]; +assign msg_data_i = decomp_msg_valid ? decomp_msg_data : msg_data; + +mldsa_sampler_top sampler_top_inst +( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize_reg), + + .sampler_mode_i(sampler_mode), + .sha3_start_i(sha3_start), //start the sha3 engine + .msg_start_i(msg_start), //start a new message + .msg_valid_i(msg_valid | decomp_msg_valid), //msg interface valid //FIXME + .msg_rdy_o(msg_rdy), //msg interface rdy (~hold) + .msg_strobe_i(decomp_msg_valid ? '1 : msg_strobe), //msg byte enables //FIXME + .msg_data_i(msg_data_i), //msg data/ /FIXME + + .sib_mem_rd_req_i(sib_mem_rd_req), + .sib_mem_rd_data_o(sib_mem_rd_data), + + .sampler_start_i(sampler_start), + .dest_base_addr_i(dest_base_addr), + + .sampler_busy_o(sampler_busy), + + .sampler_ntt_dv_o(sampler_ntt_dv[0]), + .sampler_ntt_data_o(sampler_ntt_data), + + .sampler_mem_dv_o(sampler_mem_dv), + .sampler_mem_data_o(sampler_mem_data), + .sampler_mem_addr_o(sampler_mem_addr), + + .sampler_state_dv_o(sampler_state_dv), + .sampler_state_data_o(sampler_state_data) +); + +always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + sampler_ntt_dv_f <= 0; + end + else if (zeroize_reg) begin + sampler_ntt_dv_f <= 0; + end + else begin + sampler_ntt_dv_f <= sampler_ntt_dv; + end +end + +assign sampler_ntt_dv[1] = 0; //no sampler interface to secondary ntt + +generate + for (genvar g_inst = 0; g_inst < 2; g_inst++) begin : ntt_gen + //NTT + //gasket here, create common interfaces? + always_comb begin + mode[g_inst] = '0; + accumulate[g_inst] = '0; + sampler_valid[g_inst] = 0; + sampler_ntt_mode[g_inst] = 0; + ntt_random_en[g_inst] = 0; //Turn off random in NTT for all ops except PWM, INTT + + unique case (ntt_mode[g_inst]) inside + MLDSA_NTT_NONE: begin + end + MLDSA_NTT: begin + mode[g_inst] = ct; + end + MLDSA_INTT: begin + mode[g_inst] = gs; + ntt_random_en[g_inst] = 1; + end + MLDSA_PWM_SMPL: begin + mode[g_inst] = pwm; + sampler_valid[g_inst] = sampler_ntt_dv[g_inst]; + sampler_ntt_mode[g_inst] = 1; + end + MLDSA_PWM_ACCUM_SMPL: begin + mode[g_inst] = pwm; + accumulate[g_inst] = 1; + sampler_valid[g_inst] = sampler_ntt_dv[g_inst]; + sampler_ntt_mode[g_inst] = 1; + end + MLDSA_PWM: begin + mode[g_inst] = pwm; + sampler_valid[g_inst] = 1; + ntt_random_en[g_inst] = 1; + end + MLDSA_PWM_ACCUM: begin + mode[g_inst] = pwm; + accumulate[g_inst] = 1; + sampler_valid[g_inst] = 1; + ntt_random_en[g_inst] = 1; + end + MLDSA_PWA: begin + mode[g_inst] = pwa; + sampler_valid[g_inst] = 1; + end + MLDSA_PWS: begin + mode[g_inst] = pws; + sampler_valid[g_inst] = 1; + end + MLDSA_PWM_INTT: begin + mode[g_inst] = pwm_intt; + ntt_random_en[g_inst] = 1; + sampler_valid[g_inst] = 1; + end + default: begin + end + endcase + + + end + + ntt_top #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q), + .MLDSA_N(MLDSA_N), + .MEM_ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH) + ) + ntt_top_inst0 ( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .mode(mode[g_inst]), + .ntt_enable(ntt_enable[g_inst]), + .ntt_mem_base_addr(ntt_mem_base_addr[g_inst]), + .pwo_mem_base_addr(pwo_mem_base_addr[g_inst]), + .accumulate(accumulate[g_inst]), + .sampler_valid(sampler_valid[g_inst]), + .shuffle_en(ntt_shuffling_en[g_inst]), + .random(rand_bits[5:0]), + .masking_en(ntt_masking_en[g_inst]), + .rnd_i(ntt_random_en[g_inst] ? ntt_rand_bits : (RND_W-6)'(0)), //(ntt_rand_bits & {(RND_W-6){ntt_random_en[g_inst]}}), + //NTT mem IF + .mem_wr_req(ntt_mem_wr_req[g_inst]), + .mem_rd_req(ntt_mem_rd_req[g_inst]), + .mem_wr_data(ntt_mem_wr_data[g_inst]), + .mem_rd_data(ntt_mem_rd_data[g_inst]), + //PWM mem IF + .pwm_a_rd_req(pwm_a_rd_req[g_inst]), + .pwm_b_rd_req(pwm_b_rd_req[g_inst]), + .pwm_a_rd_data(pwm_a_rd_data[g_inst]), + .pwm_b_rd_data(sampler_ntt_mode[g_inst] ? sampler_ntt_data : pwm_b_rd_data[g_inst]), + .ntt_busy(ntt_busy[g_inst]), + .ntt_done(ntt_done[g_inst]) + ); + end +endgenerate + +//aux functions +power2round_top +power2round_inst ( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .enable(power2round_enable), + .done(power2round_done), + + .src_base_addr(aux_src0_base_addr[0]), + .mem_a_rd_req(pwr2rnd_mem_rd_req[0]), + .mem_rd_data_a(pwr2rnd_mem_rd_data[0]), + .mem_b_rd_req(pwr2rnd_mem_rd_req[1]), + .mem_rd_data_b(pwr2rnd_mem_rd_data[1]), + + .pk_t1_wren(pk_t1_wren), + .pk_t1_wr_addr(pk_t1_wr_addr), + .pk_t1_wrdata(pk_t1_wrdata), + + .skmem_dest_base_addr(aux_dest_base_addr[0]), + .skmem_a_wr_req(pwr2rnd_keymem_if[0]), + .skmem_wr_data_a(pwr2rnd_wr_data[0]), + .skmem_b_wr_req(pwr2rnd_keymem_if[1]), + .skmem_wr_data_b(pwr2rnd_wr_data[1]) +); + +decompose +decompose_inst ( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .decompose_enable(decompose_enable), + .dcmp_mode(decompose_mode), + .src_base_addr(aux_src0_base_addr[0]), + .dest_base_addr(aux_dest_base_addr[0]), + .hint_src_base_addr(aux_src1_base_addr[0]), + + //Output to memory - r0 + .mem_rd_req(decomp_mem_rd_req[0]), + .mem_wr_req(decomp_mem_wr_req), + .mem_rd_data(decomp_mem_rd_data[0]), + .mem_wr_data(decomp_mem_wr_data), + + //Output to memory - h (sigDecode) + .mem_hint_rd_req(decomp_mem_rd_req[1]), + .mem_hint_rd_data(decomp_mem_rd_data[1]), + + //Output to z mem - z != 0 + .z_mem_wr_req(w1_mem_wr_req), + .z_neq_z(w1_mem_wr_data), + + //Output of w1_encode - r1 + .w1_o(decomp_msg_data[0]), + .buffer_en(decomp_msg_valid), + + //TODO: check what high level controller requirement is + .decompose_done(decompose_done) +); + +skencode +#( + .MEM_ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH) +) +skencode_inst +( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .src_base_addr(aux_src0_base_addr[0]), + .dest_base_addr(aux_dest_base_addr[0]), + + .skencode_enable(skencode_enable), + .skencode_done(skencode_done), + + .keymem_a_wr_req(skencode_keymem_if), + .keymem_a_wr_data(skencode_wr_data), + .mem_a_rd_req(skencode_mem_rd_req[0]), + .mem_a_rd_data(skencode_mem_rd_data[0]), + .mem_b_rd_req(skencode_mem_rd_req[1]), + .mem_b_rd_data(skencode_mem_rd_data[1]) +); + +skdecode_top +skdecode_inst +( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .skdecode_enable(skdecode_enable), + .skdecode_done(skdecode_done), + + .keymem_src_base_addr(aux_src0_base_addr[1]), + .dest_base_addr(aux_dest_base_addr[1]), + + .keymem_a_rd_req(skdecode_keymem_if[0]), + .keymem_a_rd_data(skdecode_rd_data[0]), + .keymem_b_rd_req(skdecode_keymem_if[1]), + .keymem_b_rd_data(skdecode_rd_data[1]), + + .mem_a_wr_req(skdecode_mem_wr_req[0]), + .mem_a_wr_data(skdecode_mem_wr_data[0]), + .mem_b_wr_req(skdecode_mem_wr_req[1]), + .mem_b_wr_data(skdecode_mem_wr_data[1]), + + .s1_done(), + .s2_done(), + .t0_done(), + .skdecode_error(skdecode_error) +); + +makehint +makehint_inst +( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .makehint_enable(makehint_enable), + .makehint_done(makehint_done), + + .mem_base_addr(aux_src0_base_addr[1]), + .dest_base_addr('0), + + .mem_rd_req(makehint_mem_rd_req), + .r(makehint_mem_rd_data), + + .reg_wren(makehint_reg_wren), + .reg_wr_addr(makehint_reg_wr_addr), + .reg_wrdata(makehint_reg_wrdata), + + .z_rd_req(w1_mem_rd_req), + .z(w1_mem_rd_data), + + .invalid_h(makehint_invalid) +); + +norm_check_top +norm_check_inst +( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .mode(normcheck_mode), + .norm_check_enable(normcheck_enable), + + .shuffling_enable(1'b1), // This signal can be controlled by the controller + .randomness(rand_bits[5:0]), + + .norm_check_ready(), + .norm_check_done(normcheck_done), + + .mem_base_addr(normcheck_src_addr), + .mem_rd_req(normcheck_mem_rd_req), + .mem_rd_data(normcheck_mem_rd_data), + + .invalid(normcheck_invalid) + +); + +sigencode_z_top +sigencode_z_inst +( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .sigencode_z_enable(sigencode_enable), + .sigencode_z_done(sigencode_done), + + .src_base_addr(aux_src0_base_addr[1]), + .sigmem_dest_base_addr(aux_dest_base_addr[1]), + + .mem_a_rd_req(sigencode_mem_rd_req[0]), + .mem_a_rd_data(sigencode_mem_rd_data[0]), + .mem_b_rd_req(sigencode_mem_rd_req[1]), + .mem_b_rd_data(sigencode_mem_rd_data[1]), + + .sigmem_a_wr_req(sigencode_mem_wr_req), + .sigmem_a_wr_data(sigencode_mem_wr_data[0]), + .sigmem_b_wr_req(), //fixme single interface + .sigmem_b_wr_data(sigencode_mem_wr_data[1]) +); + +pkdecode +#( + .API_ADDR_WIDTH(8) //FIXME +) +pkdecode_inst ( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .pkdecode_enable(pkdecode_enable), + .pkdecode_done(pkdecode_done), + + .src_base_addr('0), //fixme remove - api register reads, no need for base address + .dest_base_addr(aux_dest_base_addr[0]), + + .API_rd_address(pkdecode_rd_addr), + .API_rd_data(pkdecode_rd_data), + + .mem_a_wr_req(pkdecode_mem_wr_req[0]), + .mem_a_wr_data(pkdecode_mem_wr_data[0]), + .mem_b_wr_req(pkdecode_mem_wr_req[1]), + .mem_b_wr_data(pkdecode_mem_wr_data[1]) +); + +sigdecode_z_top +sigdecode_z_inst ( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .sigdecode_z_enable(sigdecode_z_enable), + .sigdecode_z_done(sigdecode_z_done), + + .sigmem_src_base_addr('0), //fixme remove, reads dedicated memory + .dest_base_addr(aux_dest_base_addr[0]), + + .mem_a_wr_req(sigdecode_z_mem_wr_req[0]), + .mem_a_wr_data(sigdecode_z_mem_wr_data[0]), + .mem_b_wr_req(sigdecode_z_mem_wr_req[1]), + .mem_b_wr_data(sigdecode_z_mem_wr_data[1]), + + .sigmem_a_rd_req(sigdecode_z_mem_rd_req), + .sigmem_a_rd_data(sigdecode_z_mem_rd_data[0]), + .sigmem_b_rd_req(), //fixme switch to single interface + .sigmem_b_rd_data(sigdecode_z_mem_rd_data[1]) +); + +sigdecode_h +sigdecode_h_inst ( + .clk(clk), + .reset_n(rst_b), + .zeroize(zeroize_reg), + + .sigdecode_h_enable(sigdecode_h_enable), + .sigdecode_h_done(sigdecode_h_done), + + .dest_base_addr(aux_dest_base_addr[0]), + + .encoded_h_i(signature_h), + .mem_wr_req(sigdecode_h_mem_wr_req), + .mem_wr_data(sigdecode_h_mem_wr_data), + + .sigdecode_h_error(sigdecode_h_invalid) +); + + +abr_prim_lfsr +#( + .LfsrType("FIB_XNOR"), + .LfsrDw(LFSR_W), + .StateOutDw(LFSR_W) +) abr_prim_lfsr_inst0 +( + .clk_i(clk), + .rst_b(rst_b), + .seed_en_i(lfsr_enable), + .seed_i(lfsr_seed[0]), + .lfsr_en_i(1'b1), + .entropy_i('0), + .state_o(rand_bits[LFSR_W-1:0]) +); + +abr_prim_lfsr +#( + .LfsrType("FIB_XNOR"), + .LfsrDw(LFSR_W), + .StateOutDw(LFSR_W) +) abr_prim_lfsr_inst1 +( + .clk_i(clk), + .rst_b(rst_b), + .seed_en_i(lfsr_enable), + .seed_i(lfsr_seed[1]), + .lfsr_en_i(1'b1), + .entropy_i('0), + .state_o(rand_bits[RND_W-1 : LFSR_W]) +); + +always_comb begin + mldsa_memory_export.w1_mem_we_i = (w1_mem_wr_req.rd_wr_en == RW_WRITE) | zeroize_mem_we; + mldsa_memory_export.w1_mem_waddr_i = (w1_mem_wr_req.addr[MLDSA_MEM_W1_ADDR_W-1:0]) | + ({MLDSA_MEM_W1_ADDR_W{zeroize_mem_we}} & zeroize_mem_addr[MLDSA_MEM_W1_ADDR_W-1:0]); + mldsa_memory_export.w1_mem_wdata_i = zeroize_mem_we ? '0 : w1_mem_wr_data; + mldsa_memory_export.w1_mem_re_i = w1_mem_rd_req.rd_wr_en == RW_READ; + mldsa_memory_export.w1_mem_raddr_i = w1_mem_rd_req.addr[MLDSA_MEM_W1_ADDR_W-1:0]; + w1_mem_rd_data = mldsa_memory_export.w1_mem_rdata_o; +end + +//Decode request to sample in ball memory +logic [1:0] sib_mem_re, sib_mem_re_f; +always_comb sib_mem_re[0] = (ntt_mem_rd_req[0].rd_wr_en == RW_READ) & (ntt_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == 3'b100); +always_comb sib_mem_re[1] = (ntt_mem_rd_req[1].rd_wr_en == RW_READ) & (ntt_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == 3'b100); + +always_comb sib_mem_rd_req.addr = sib_mem_re[0] ? ntt_mem_rd_req[0].addr : + sib_mem_re[1] ? ntt_mem_rd_req[1].addr : '0; +always_comb sib_mem_rd_req.rd_wr_en = sib_mem_re[0] ? ntt_mem_rd_req[0].rd_wr_en : + sib_mem_re[1] ? ntt_mem_rd_req[1].rd_wr_en : RW_IDLE; + + +//MUX memory accesses +logic [3:1] mldsa_mem_re; +logic [3:1][MLDSA_MEM_ADDR_WIDTH-4:0] mldsa_mem_raddr; +logic [3:1][MLDSA_MEM_DATA_WIDTH-1:0] mldsa_mem_rdata; +logic [1:0] mldsa_mem_re0_bank; +logic [1:0][MLDSA_MEM_ADDR_WIDTH-5:0] mldsa_mem_raddr0_bank; +logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] mldsa_mem_rdata0_bank; +logic [3:1] mldsa_mem_we; +logic [3:1][MLDSA_MEM_ADDR_WIDTH-4:0] mldsa_mem_waddr; +logic [3:1][MLDSA_MEM_DATA_WIDTH-1:0] mldsa_mem_wdata; +logic [1:0] mldsa_mem_we0_bank; +logic [1:0][MLDSA_MEM_ADDR_WIDTH-5:0] mldsa_mem_waddr0_bank; +logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] mldsa_mem_wdata0_bank; + +//FIXME common memory ports to make muxing easier +//this is better - common interfaces will help clean this up further + +logic [3:1] sampler_mem_we; +logic [1:0][3:1] ntt_mem_we; +logic [3:1] decomp_mem_we; +logic [1:0] sampler_mem_we0_bank; +logic [1:0][1:0] ntt_mem_we0_bank; +logic [1:0] decomp_mem_we0_bank; +logic [1:0] skdecode_mem_we0_bank; +logic [1:0] pkdecode_mem_we0_bank; +logic [1:0] sigdecode_z_mem_we0_bank; +logic [3:1] sigdecode_h_mem_we; +logic [1:0] sigdecode_h_mem_we0_bank; + +logic [1:0][3:1] ntt_mem_re,ntt_mem_re_f; +logic [1:0][3:1] pwo_a_mem_re,pwo_a_mem_re_f; +logic [1:0][3:1] pwo_b_mem_re,pwo_b_mem_re_f; +logic [1:0][3:1] decomp_mem_re,decomp_mem_re_f; +logic [3:1] normcheck_mem_re,normcheck_mem_re_f; +logic [3:1] makehint_mem_re; +logic [1:0][1:0] ntt_mem_re0_bank,ntt_mem_re0_bank_f; +logic [1:0][1:0] pwo_a_mem_re0_bank,pwo_a_mem_re0_bank_f; +logic [1:0][1:0] pwo_b_mem_re0_bank,pwo_b_mem_re0_bank_f; +logic [1:0][1:0] decomp_mem_re0_bank,decomp_mem_re0_bank_f; +logic [1:0] normcheck_mem_re0_bank,normcheck_mem_re0_bank_f; +logic [1:0] skencode_mem_re0_bank; +logic [1:0] sigencode_mem_re0_bank; +logic [1:0] pwr2rnd_mem_re0_bank; + +//Write Muxes +always_comb begin + for (int i = 0; i < 4; i++) begin + if (i == 0) begin + for (int bank = 0; bank < 2; bank++) begin + sampler_mem_we0_bank[bank] = sampler_mem_dv & (sampler_mem_addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (sampler_mem_addr[0] == bank); + ntt_mem_we0_bank[0][bank] = (ntt_mem_wr_req[0].rd_wr_en == RW_WRITE) & (ntt_mem_wr_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (ntt_mem_wr_req[0].addr[0] == bank); + ntt_mem_we0_bank[1][bank] = (ntt_mem_wr_req[1].rd_wr_en == RW_WRITE) & (ntt_mem_wr_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (ntt_mem_wr_req[1].addr[0] == bank); + decomp_mem_we0_bank[bank] = (decomp_mem_wr_req.rd_wr_en == RW_WRITE) & (decomp_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (decomp_mem_wr_req.addr[0] == bank); + sigdecode_h_mem_we0_bank[bank] = (sigdecode_h_mem_wr_req.rd_wr_en == RW_WRITE) & (sigdecode_h_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (sigdecode_h_mem_wr_req.addr[0] == bank); + skdecode_mem_we0_bank[bank] = (skdecode_mem_wr_req[bank].rd_wr_en == RW_WRITE); + pkdecode_mem_we0_bank[bank] = (pkdecode_mem_wr_req[bank].rd_wr_en == RW_WRITE); + sigdecode_z_mem_we0_bank[bank] = (sigdecode_z_mem_wr_req[bank].rd_wr_en == RW_WRITE); + + mldsa_mem_we0_bank[bank] = sampler_mem_we0_bank[bank] | ntt_mem_we0_bank[0][bank] | ntt_mem_we0_bank[1][bank] | + decomp_mem_we0_bank[bank] | skdecode_mem_we0_bank[bank] | pkdecode_mem_we0_bank[bank] | + sigdecode_h_mem_we0_bank[bank] | sigdecode_z_mem_we0_bank[bank] | zeroize_mem_we; + + mldsa_mem_waddr0_bank[bank] = ({MLDSA_MEM_ADDR_WIDTH-4{sampler_mem_we0_bank[bank] }} & sampler_mem_addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{ntt_mem_we0_bank[0][bank] }} & ntt_mem_wr_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{ntt_mem_we0_bank[1][bank] }} & ntt_mem_wr_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{decomp_mem_we0_bank[bank] }} & decomp_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{sigdecode_h_mem_we0_bank[bank] }} & sigdecode_h_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{skdecode_mem_we0_bank[bank]}} & skdecode_mem_wr_req[bank].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{pkdecode_mem_we0_bank[bank]}} & pkdecode_mem_wr_req[bank].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{sigdecode_z_mem_we0_bank[bank]}} & sigdecode_z_mem_wr_req[bank].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{zeroize_mem_we}} & (zeroize_mem_addr[MLDSA_MEM_ADDR_WIDTH-5:0])); + + mldsa_mem_wdata0_bank[bank] = ({MLDSA_MEM_DATA_WIDTH{sampler_mem_we0_bank[bank] }} & sampler_mem_data) | + ({MLDSA_MEM_DATA_WIDTH{ntt_mem_we0_bank[0][bank] }} & ntt_mem_wr_data[0]) | + ({MLDSA_MEM_DATA_WIDTH{ntt_mem_we0_bank[1][bank] }} & ntt_mem_wr_data[1]) | + ({MLDSA_MEM_DATA_WIDTH{decomp_mem_we0_bank[bank] }} & decomp_mem_wr_data) | + ({MLDSA_MEM_DATA_WIDTH{sigdecode_h_mem_we0_bank[bank]}} & sigdecode_h_mem_wr_data) | + ({MLDSA_MEM_DATA_WIDTH{skdecode_mem_we0_bank[bank]}} & skdecode_mem_wr_data[bank]) | + ({MLDSA_MEM_DATA_WIDTH{pkdecode_mem_we0_bank[bank]}} & pkdecode_mem_wr_data[bank]) | + ({MLDSA_MEM_DATA_WIDTH{sigdecode_z_mem_we0_bank[bank]}} & sigdecode_z_mem_wr_data[bank]); + end + end else begin + sampler_mem_we[i] = sampler_mem_dv & (sampler_mem_addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + ntt_mem_we[0][i] = (ntt_mem_wr_req[0].rd_wr_en == RW_WRITE) & (ntt_mem_wr_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + ntt_mem_we[1][i] = (ntt_mem_wr_req[1].rd_wr_en == RW_WRITE) & (ntt_mem_wr_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + decomp_mem_we[i] = (decomp_mem_wr_req.rd_wr_en == RW_WRITE) & (decomp_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + sigdecode_h_mem_we[i] = (sigdecode_h_mem_wr_req.rd_wr_en == RW_WRITE) & (sigdecode_h_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + + mldsa_mem_we[i] = sampler_mem_we[i] | ntt_mem_we[0][i] | ntt_mem_we[1][i] | decomp_mem_we[i] | sigdecode_h_mem_we[i] | zeroize_mem_we; + mldsa_mem_waddr[i] = ({MLDSA_MEM_ADDR_WIDTH-3{sampler_mem_we[i]}} & sampler_mem_addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{ntt_mem_we[0][i]}} & ntt_mem_wr_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{ntt_mem_we[1][i]}} & ntt_mem_wr_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{decomp_mem_we[i]}} & decomp_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{sigdecode_h_mem_we[i]}} & sigdecode_h_mem_wr_req.addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{zeroize_mem_we}} & zeroize_mem_addr[MLDSA_MEM_ADDR_WIDTH-4:0]); + + mldsa_mem_wdata[i] = ({MLDSA_MEM_DATA_WIDTH{sampler_mem_we[i]}} & sampler_mem_data) | + ({MLDSA_MEM_DATA_WIDTH{ntt_mem_we[0][i]}} & ntt_mem_wr_data[0]) | + ({MLDSA_MEM_DATA_WIDTH{ntt_mem_we[1][i]}} & ntt_mem_wr_data[1]) | + ({MLDSA_MEM_DATA_WIDTH{decomp_mem_we[i]}} & decomp_mem_wr_data) | + ({MLDSA_MEM_DATA_WIDTH{sigdecode_h_mem_we[i]}} & sigdecode_h_mem_wr_data); + end + end +end + +//Read Muxes +always_comb begin + for (int i = 0; i < 4; i++) begin + if (i == 0) begin + for (int bank = 0; bank < 2; bank++) begin + ntt_mem_re0_bank[0][bank] = (ntt_mem_rd_req[0].rd_wr_en == RW_READ) & (ntt_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (ntt_mem_rd_req[0].addr[0] == bank); + pwo_a_mem_re0_bank[0][bank] = (pwm_a_rd_req[0].rd_wr_en == RW_READ) & (pwm_a_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (pwm_a_rd_req[0].addr[0] == bank); + pwo_b_mem_re0_bank[0][bank] = (ntt_shuffling_en[0] ? ~sampler_ntt_dv_f : ~sampler_ntt_dv) & (pwm_b_rd_req[0].rd_wr_en == RW_READ) & (pwm_b_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (pwm_b_rd_req[0].addr[0] == bank); + + ntt_mem_re0_bank[1][bank] = (ntt_mem_rd_req[1].rd_wr_en == RW_READ) & (ntt_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (ntt_mem_rd_req[1].addr[0] == bank); + pwo_a_mem_re0_bank[1][bank] = (pwm_a_rd_req[1].rd_wr_en == RW_READ) & (pwm_a_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (pwm_a_rd_req[1].addr[0] == bank); + pwo_b_mem_re0_bank[1][bank] = (pwm_b_rd_req[1].rd_wr_en == RW_READ) & (pwm_b_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (pwm_b_rd_req[1].addr[0] == bank); + + decomp_mem_re0_bank[0][bank] = (decomp_mem_rd_req[0].rd_wr_en == RW_READ) & (decomp_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (decomp_mem_rd_req[0].addr[0] == bank); + decomp_mem_re0_bank[1][bank] = (decomp_mem_rd_req[1].rd_wr_en == RW_READ) & (decomp_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (decomp_mem_rd_req[1].addr[0] == bank); + normcheck_mem_re0_bank[bank] = (normcheck_mem_rd_req.rd_wr_en == RW_READ) & (normcheck_mem_rd_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]) & (normcheck_mem_rd_req.addr[0] == bank); + skencode_mem_re0_bank[bank] = (skencode_mem_rd_req[bank].rd_wr_en == RW_READ); + sigencode_mem_re0_bank[bank] = (sigencode_mem_rd_req[bank].rd_wr_en == RW_READ); + pwr2rnd_mem_re0_bank[bank] = (pwr2rnd_mem_rd_req[bank].rd_wr_en == RW_READ); + + mldsa_mem_re0_bank[bank] = ntt_mem_re0_bank[0][bank] | pwo_a_mem_re0_bank[0][bank] | pwo_b_mem_re0_bank[0][bank] | + ntt_mem_re0_bank[1][bank] | pwo_a_mem_re0_bank[1][bank] | pwo_b_mem_re0_bank[1][bank] | + decomp_mem_re0_bank[0][bank] | decomp_mem_re0_bank[1][bank] | + skencode_mem_re0_bank[bank] | normcheck_mem_re0_bank[bank] | + sigencode_mem_re0_bank[bank] | pwr2rnd_mem_re0_bank[bank]; + mldsa_mem_raddr0_bank[bank] = ({MLDSA_MEM_ADDR_WIDTH-4{ntt_mem_re0_bank[0][bank]}} & ntt_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{pwo_a_mem_re0_bank[0][bank]}} & pwm_a_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{pwo_b_mem_re0_bank[0][bank]}} & pwm_b_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{ntt_mem_re0_bank[1][bank]}} & ntt_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{pwo_a_mem_re0_bank[1][bank]}} & pwm_a_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{pwo_b_mem_re0_bank[1][bank]}} & pwm_b_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{decomp_mem_re0_bank[0][bank]}} & decomp_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{decomp_mem_re0_bank[1][bank]}} & decomp_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{skencode_mem_re0_bank[bank]}} & skencode_mem_rd_req[bank].addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{normcheck_mem_re0_bank[bank]}} & normcheck_mem_rd_req.addr[MLDSA_MEM_ADDR_WIDTH-4:1]) | + ({MLDSA_MEM_ADDR_WIDTH-4{sigencode_mem_re0_bank[bank]}} & sigencode_mem_rd_req[bank].addr[MLDSA_MEM_ADDR_WIDTH-4:1])| + ({MLDSA_MEM_ADDR_WIDTH-4{pwr2rnd_mem_re0_bank[bank]}} & pwr2rnd_mem_rd_req[bank].addr[MLDSA_MEM_ADDR_WIDTH-4:1]); + end + end else begin + ntt_mem_re[0][i] = (ntt_mem_rd_req[0].rd_wr_en == RW_READ) & (ntt_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + pwo_a_mem_re[0][i] = (pwm_a_rd_req[0].rd_wr_en == RW_READ) & (pwm_a_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + pwo_b_mem_re[0][i] = (ntt_shuffling_en[0] ? ~sampler_ntt_dv_f : ~sampler_ntt_dv) & (pwm_b_rd_req[0].rd_wr_en == RW_READ) & (pwm_b_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + + ntt_mem_re[1][i] = (ntt_mem_rd_req[1].rd_wr_en == RW_READ) & (ntt_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + pwo_a_mem_re[1][i] = (pwm_a_rd_req[1].rd_wr_en == RW_READ) & (pwm_a_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + pwo_b_mem_re[1][i] = (pwm_b_rd_req[1].rd_wr_en == RW_READ) & (pwm_b_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + + decomp_mem_re[0][i] = (decomp_mem_rd_req[0].rd_wr_en == RW_READ) & (decomp_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + decomp_mem_re[1][i] = (decomp_mem_rd_req[1].rd_wr_en == RW_READ) & (decomp_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + normcheck_mem_re[i] = (normcheck_mem_rd_req.rd_wr_en == RW_READ) & (normcheck_mem_rd_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + makehint_mem_re[i] = (makehint_mem_rd_req.rd_wr_en == RW_READ) & (makehint_mem_rd_req.addr[MLDSA_MEM_ADDR_WIDTH-1:MLDSA_MEM_ADDR_WIDTH-3] == i[2:0]); + + mldsa_mem_re[i] = ntt_mem_re[0][i] | pwo_a_mem_re[0][i] | pwo_b_mem_re[0][i] | + ntt_mem_re[1][i] | pwo_a_mem_re[1][i] | pwo_b_mem_re[1][i] | + decomp_mem_re[0][i] | decomp_mem_re[1][i] | + normcheck_mem_re[i] | makehint_mem_re[i]; + mldsa_mem_raddr[i] = ({MLDSA_MEM_ADDR_WIDTH-3{ntt_mem_re[0][i]}} & ntt_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{pwo_a_mem_re[0][i]}} & pwm_a_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{pwo_b_mem_re[0][i]}} & pwm_b_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{ntt_mem_re[1][i]}} & ntt_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{pwo_a_mem_re[1][i]}} & pwm_a_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{pwo_b_mem_re[1][i]}} & pwm_b_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{decomp_mem_re[0][i]}} & decomp_mem_rd_req[0].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{decomp_mem_re[1][i]}} & decomp_mem_rd_req[1].addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{normcheck_mem_re[i]}} & normcheck_mem_rd_req.addr[MLDSA_MEM_ADDR_WIDTH-4:0]) | + ({MLDSA_MEM_ADDR_WIDTH-3{makehint_mem_re[i]}} & makehint_mem_rd_req.addr[MLDSA_MEM_ADDR_WIDTH-4:0]); + end + end +end + +//Align read enables +always_ff @(posedge clk or negedge rst_b) begin : read_mux_flops + if (!rst_b) begin + ntt_mem_re_f <= 0; + pwo_a_mem_re_f <= 0; + pwo_b_mem_re_f <= 0; + decomp_mem_re_f <= 0; + normcheck_mem_re_f <= 0; + ntt_mem_re0_bank_f <= 0; + pwo_a_mem_re0_bank_f <= 0; + pwo_b_mem_re0_bank_f <= 0; + decomp_mem_re0_bank_f <= 0; + normcheck_mem_re0_bank_f <= 0; + sib_mem_re_f <= 0; + end + else if (zeroize_reg) begin + ntt_mem_re_f <= 0; + pwo_a_mem_re_f <= 0; + pwo_b_mem_re_f <= 0; + decomp_mem_re_f <= 0; + normcheck_mem_re_f <= 0; + ntt_mem_re0_bank_f <= 0; + pwo_a_mem_re0_bank_f <= 0; + pwo_b_mem_re0_bank_f <= 0; + decomp_mem_re0_bank_f <= 0; + normcheck_mem_re0_bank_f <= 0; + sib_mem_re_f <= 0; + end + else begin + ntt_mem_re_f <= ntt_mem_re; + pwo_a_mem_re_f<= pwo_a_mem_re; + pwo_b_mem_re_f <= pwo_b_mem_re; + decomp_mem_re_f <= decomp_mem_re; + normcheck_mem_re_f <= normcheck_mem_re; + ntt_mem_re0_bank_f <= ntt_mem_re0_bank; + pwo_a_mem_re0_bank_f <= pwo_a_mem_re0_bank; + pwo_b_mem_re0_bank_f <= pwo_b_mem_re0_bank; + decomp_mem_re0_bank_f <= decomp_mem_re0_bank; + normcheck_mem_re0_bank_f <= normcheck_mem_re0_bank; + sib_mem_re_f <= sib_mem_re; + end +end + +//Read data muxes +always_comb begin + ntt_mem_rd_data = 0; + pwm_a_rd_data = 0; + pwm_b_rd_data = 0; + decomp_mem_rd_data = 0; + normcheck_mem_rd_data = 0; + + for (int i = 0; i < 4; i++) begin + if (i == 0) begin + for (int bank = 0; bank < 2; bank++) begin + for (int j = 0; j < 2; j++) begin + ntt_mem_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{ntt_mem_re0_bank_f[j][bank]}} & mldsa_mem_rdata0_bank[bank]); + pwm_a_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{pwo_a_mem_re0_bank_f[j][bank]}} & mldsa_mem_rdata0_bank[bank]); + pwm_b_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{pwo_b_mem_re0_bank_f[j][bank]}} & mldsa_mem_rdata0_bank[bank]); + end + decomp_mem_rd_data[0] |= ({MLDSA_MEM_DATA_WIDTH{decomp_mem_re0_bank_f[0][bank]}} & mldsa_mem_rdata0_bank[bank]); + decomp_mem_rd_data[1] |= ({MLDSA_MEM_DATA_WIDTH{decomp_mem_re0_bank_f[1][bank]}} & mldsa_mem_rdata0_bank[bank]); + normcheck_mem_rd_data |= ({MLDSA_MEM_DATA_WIDTH{normcheck_mem_re0_bank_f[bank]}} & mldsa_mem_rdata0_bank[bank]); + end + end else begin + for (int j = 0; j < 2; j++) begin + ntt_mem_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{ntt_mem_re_f[j][i]}} & mldsa_mem_rdata[i]); + pwm_a_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{pwo_a_mem_re_f[j][i]}} & mldsa_mem_rdata[i]); + pwm_b_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{pwo_b_mem_re_f[j][i]}} & mldsa_mem_rdata[i]); + end + decomp_mem_rd_data[0] |= ({MLDSA_MEM_DATA_WIDTH{decomp_mem_re_f[0][i]}} & mldsa_mem_rdata[i]); + decomp_mem_rd_data[1] |= ({MLDSA_MEM_DATA_WIDTH{decomp_mem_re_f[1][i]}} & mldsa_mem_rdata[i]); + normcheck_mem_rd_data |= ({MLDSA_MEM_DATA_WIDTH{normcheck_mem_re_f[i]}} & mldsa_mem_rdata[i]); + end + end + for (int j = 0; j < 2; j++) begin + ntt_mem_rd_data[j] |= ({MLDSA_MEM_DATA_WIDTH{sib_mem_re_f[j]}} & sib_mem_rd_data); + end +end + +always_comb skencode_mem_rd_data = mldsa_mem_rdata0_bank; +always_comb makehint_mem_rd_data = mldsa_mem_rdata[1]; +always_comb sigencode_mem_rd_data = mldsa_mem_rdata0_bank; +always_comb pwr2rnd_mem_rd_data = mldsa_mem_rdata0_bank; + +//Memory instance 0 bank 0 +always_comb mldsa_memory_export.mem_inst0_bank0_we_i = (mldsa_mem_we0_bank[0]); +always_comb mldsa_memory_export.mem_inst0_bank0_waddr_i = (mldsa_mem_waddr0_bank[0][MLDSA_MEM_INST0_ADDR_W-1:0]); +always_comb mldsa_memory_export.mem_inst0_bank0_wdata_i = (mldsa_mem_wdata0_bank[0]); +always_comb mldsa_memory_export.mem_inst0_bank0_re_i = (mldsa_mem_re0_bank[0]); +always_comb mldsa_memory_export.mem_inst0_bank0_raddr_i = (mldsa_mem_raddr0_bank[0][MLDSA_MEM_INST0_ADDR_W-1:0]); +always_comb mldsa_mem_rdata0_bank[0] = mldsa_memory_export.mem_inst0_bank0_rdata_o; + +//Memory instance 0 bank 1 +always_comb mldsa_memory_export.mem_inst0_bank1_we_i = (mldsa_mem_we0_bank[1]); +always_comb mldsa_memory_export.mem_inst0_bank1_waddr_i = (mldsa_mem_waddr0_bank[1][MLDSA_MEM_INST0_ADDR_W-1:0]); +always_comb mldsa_memory_export.mem_inst0_bank1_wdata_i = (mldsa_mem_wdata0_bank[1]); +always_comb mldsa_memory_export.mem_inst0_bank1_re_i = (mldsa_mem_re0_bank[1]); +always_comb mldsa_memory_export.mem_inst0_bank1_raddr_i = (mldsa_mem_raddr0_bank[1][MLDSA_MEM_INST0_ADDR_W-1:0]); +always_comb mldsa_mem_rdata0_bank[1] = mldsa_memory_export.mem_inst0_bank1_rdata_o; + +//Memory instance 1 +always_comb mldsa_memory_export.mem_inst1_we_i = (mldsa_mem_we[1]); +always_comb mldsa_memory_export.mem_inst1_waddr_i = (mldsa_mem_waddr[1][MLDSA_MEM_INST1_ADDR_W-1:0]); +always_comb mldsa_memory_export.mem_inst1_wdata_i = (mldsa_mem_wdata[1]); +always_comb mldsa_memory_export.mem_inst1_re_i = (mldsa_mem_re[1]); +always_comb mldsa_memory_export.mem_inst1_raddr_i = (mldsa_mem_raddr[1][MLDSA_MEM_INST1_ADDR_W-1:0]); +always_comb mldsa_mem_rdata[1] = mldsa_memory_export.mem_inst1_rdata_o; + +//Memory instance 2 +always_comb mldsa_memory_export.mem_inst2_we_i = (mldsa_mem_we[2]); +always_comb mldsa_memory_export.mem_inst2_waddr_i = (mldsa_mem_waddr[2][MLDSA_MEM_INST2_ADDR_W-1:0]); +always_comb mldsa_memory_export.mem_inst2_wdata_i = (mldsa_mem_wdata[2]); +always_comb mldsa_memory_export.mem_inst2_re_i = (mldsa_mem_re[2]); +always_comb mldsa_memory_export.mem_inst2_raddr_i = (mldsa_mem_raddr[2][MLDSA_MEM_INST2_ADDR_W-1:0]); +always_comb mldsa_mem_rdata[2] = mldsa_memory_export.mem_inst2_rdata_o; + +//Memory instance 3 +always_comb mldsa_memory_export.mem_inst3_we_i = (mldsa_mem_we[3]); +always_comb mldsa_memory_export.mem_inst3_waddr_i = (mldsa_mem_waddr[3][MLDSA_MEM_INST3_ADDR_W-1:0]); +always_comb mldsa_memory_export.mem_inst3_wdata_i = (mldsa_mem_wdata[3]); +always_comb mldsa_memory_export.mem_inst3_re_i = (mldsa_mem_re[3]); +always_comb mldsa_memory_export.mem_inst3_raddr_i = (mldsa_mem_raddr[3][MLDSA_MEM_INST3_ADDR_W-1:0]); +always_comb mldsa_mem_rdata[3] = mldsa_memory_export.mem_inst3_rdata_o; + +//SK Memory Bank 0 +always_comb mldsa_memory_export.sk_mem_bank0_we_i = sk_bank0_mem_if.we_i; +always_comb mldsa_memory_export.sk_mem_bank0_waddr_i = sk_bank0_mem_if.waddr_i; +always_comb mldsa_memory_export.sk_mem_bank0_wdata_i = sk_bank0_mem_if.wdata_i; +always_comb mldsa_memory_export.sk_mem_bank0_re_i = sk_bank0_mem_if.re_i; +always_comb mldsa_memory_export.sk_mem_bank0_raddr_i = sk_bank0_mem_if.raddr_i; +always_comb sk_bank0_mem_if.rdata_o = mldsa_memory_export.sk_mem_bank0_rdata_o; + +//SK Memory Bank 1 +always_comb mldsa_memory_export.sk_mem_bank1_we_i = sk_bank1_mem_if.we_i; +always_comb mldsa_memory_export.sk_mem_bank1_waddr_i = sk_bank1_mem_if.waddr_i; +always_comb mldsa_memory_export.sk_mem_bank1_wdata_i = sk_bank1_mem_if.wdata_i; +always_comb mldsa_memory_export.sk_mem_bank1_re_i = sk_bank1_mem_if.re_i; +always_comb mldsa_memory_export.sk_mem_bank1_raddr_i = sk_bank1_mem_if.raddr_i; +always_comb sk_bank1_mem_if.rdata_o = mldsa_memory_export.sk_mem_bank1_rdata_o; + +//Sig Z Memory +always_comb mldsa_memory_export.sig_z_mem_we_i = sig_z_mem_if.we_i; +always_comb mldsa_memory_export.sig_z_mem_waddr_i = sig_z_mem_if.waddr_i; +always_comb mldsa_memory_export.sig_z_mem_wdata_i = sig_z_mem_if.wdata_i; +always_comb mldsa_memory_export.sig_z_mem_wstrobe_i = sig_z_mem_if.wstrobe_i; +always_comb mldsa_memory_export.sig_z_mem_re_i = sig_z_mem_if.re_i; +always_comb mldsa_memory_export.sig_z_mem_raddr_i = sig_z_mem_if.raddr_i; +always_comb sig_z_mem_if.rdata_o = mldsa_memory_export.sig_z_mem_rdata_o; + +//PK Memory +always_comb mldsa_memory_export.pk_mem_we_i = pk_mem_if.we_i; +always_comb mldsa_memory_export.pk_mem_waddr_i = pk_mem_if.waddr_i; +always_comb mldsa_memory_export.pk_mem_wdata_i = pk_mem_if.wdata_i; +always_comb mldsa_memory_export.pk_mem_wstrobe_i = pk_mem_if.wstrobe_i; +always_comb mldsa_memory_export.pk_mem_re_i = pk_mem_if.re_i; +always_comb mldsa_memory_export.pk_mem_raddr_i = pk_mem_if.raddr_i; +always_comb pk_mem_if.rdata_o = mldsa_memory_export.pk_mem_rdata_o; + +`ABR_ASSERT_MUTEX(ERR_MEM_0_0_RD_ACCESS_MUTEX, {ntt_mem_re0_bank[0][0],pwo_a_mem_re0_bank[0][0],pwo_b_mem_re0_bank[0][0],ntt_mem_re0_bank[1][0], + pwo_a_mem_re0_bank[1][0],pwo_b_mem_re0_bank[1][0],decomp_mem_re0_bank[0][0],decomp_mem_re0_bank[1][0], + skencode_mem_re0_bank[0], normcheck_mem_re0_bank[0], sigencode_mem_re0_bank[0], pwr2rnd_mem_re0_bank[0]}, clk, !rst_b) +`ABR_ASSERT_MUTEX(ERR_MEM_0_1_RD_ACCESS_MUTEX, {ntt_mem_re0_bank[0][1],pwo_a_mem_re0_bank[0][1],pwo_b_mem_re0_bank[0][1],ntt_mem_re0_bank[1][1], + pwo_a_mem_re0_bank[1][1],pwo_b_mem_re0_bank[1][1],decomp_mem_re0_bank[0][1],decomp_mem_re0_bank[1][1], + skencode_mem_re0_bank[1],normcheck_mem_re0_bank[1],sigencode_mem_re0_bank[1], pwr2rnd_mem_re0_bank[1]}, clk, !rst_b) + +`ABR_ASSERT_MUTEX(ERR_MEM_1_RD_ACCESS_MUTEX, {ntt_mem_re[0][1],pwo_a_mem_re[0][1],pwo_b_mem_re[0][1],ntt_mem_re[1][1],pwo_a_mem_re[1][1],pwo_b_mem_re[1][1], + normcheck_mem_re[1], decomp_mem_re[0][1],decomp_mem_re[1][1],makehint_mem_re[1]}, clk, !rst_b) +`ABR_ASSERT_MUTEX(ERR_MEM_2_RD_ACCESS_MUTEX, {ntt_mem_re[0][2],pwo_a_mem_re[0][2],pwo_b_mem_re[0][2],ntt_mem_re[1][2],pwo_a_mem_re[1][2],pwo_b_mem_re[1][2], + normcheck_mem_re[2], decomp_mem_re[0][2],decomp_mem_re[1][2],makehint_mem_re[2]}, clk, !rst_b) +`ABR_ASSERT_MUTEX(ERR_MEM_3_RD_ACCESS_MUTEX, {ntt_mem_re[0][3],pwo_a_mem_re[0][3],pwo_b_mem_re[0][3],ntt_mem_re[1][3],pwo_a_mem_re[1][3],pwo_b_mem_re[1][3], + normcheck_mem_re[3], decomp_mem_re[0][3],decomp_mem_re[1][3],makehint_mem_re[3]}, clk, !rst_b) + +`ABR_ASSERT_MUTEX(ERR_MEM_0_0_WR_ACCESS_MUTEX, {sampler_mem_we0_bank[0],ntt_mem_we0_bank[0][0],ntt_mem_we0_bank[1][0],decomp_mem_we0_bank[0], + skdecode_mem_we0_bank[0], pkdecode_mem_we0_bank[0], sigdecode_h_mem_we0_bank[0], + sigdecode_z_mem_we0_bank[0]}, clk, !rst_b) +`ABR_ASSERT_MUTEX(ERR_MEM_0_1_WR_ACCESS_MUTEX, {sampler_mem_we0_bank[1],ntt_mem_we0_bank[0][1],ntt_mem_we0_bank[1][1],decomp_mem_we0_bank[1], + skdecode_mem_we0_bank[1], pkdecode_mem_we0_bank[1], sigdecode_h_mem_we0_bank[1], + sigdecode_z_mem_we0_bank[1]}, clk, !rst_b) + +`ABR_ASSERT_MUTEX(ERR_MEM_1_WR_ACCESS_MUTEX, {sampler_mem_we[1],ntt_mem_we[0][1],ntt_mem_we[1][1],decomp_mem_we[1], sigdecode_h_mem_we[1]}, clk, !rst_b) +`ABR_ASSERT_MUTEX(ERR_MEM_2_WR_ACCESS_MUTEX, {sampler_mem_we[2],ntt_mem_we[0][2],ntt_mem_we[1][2],decomp_mem_we[2], sigdecode_h_mem_we[2]}, clk, !rst_b) +`ABR_ASSERT_MUTEX(ERR_MEM_3_WR_ACCESS_MUTEX, {sampler_mem_we[3],ntt_mem_we[0][3],ntt_mem_we[1][3],decomp_mem_we[3], sigdecode_h_mem_we[3]}, clk, !rst_b) + +`ABR_ASSERT_KNOWN(ERR_MEM_0_0_WDATA_X, {mldsa_mem_wdata0_bank[0]}, clk, !rst_b, mldsa_mem_we0_bank[0]) +`ABR_ASSERT_KNOWN(ERR_MEM_0_1_WDATA_X, {mldsa_mem_wdata0_bank[1]}, clk, !rst_b, mldsa_mem_we0_bank[1]) +`ABR_ASSERT_KNOWN(ERR_MEM_1_WDATA_X, {mldsa_mem_wdata[1]}, clk, !rst_b, mldsa_mem_we[1]) +`ABR_ASSERT_KNOWN(ERR_MEM_2_WDATA_X, {mldsa_mem_wdata[2]}, clk, !rst_b, mldsa_mem_we[2]) +`ABR_ASSERT_KNOWN(ERR_MEM_3_WDATA_X, {mldsa_mem_wdata[3]}, clk, !rst_b, mldsa_mem_we[3]) + +`ABR_ASSERT_KNOWN(ERR_MEM_0_RDATA_X, {ntt_mem_rd_data}, clk, !rst_b) +`ABR_ASSERT_KNOWN(ERR_MEM_1_RDATA_X, {pwm_a_rd_data}, clk, !rst_b) +`ABR_ASSERT_KNOWN(ERR_MEM_2_RDATA_X, {pwm_b_rd_data}, clk, !rst_b) + + + abr_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o; + logic clk_i; + + assign clk_i = clk; + + `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3FsmCheck_A, + sampler_top_inst.sha3_inst.u_state_regs, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KeccakRoundFsmCheck_A, + sampler_top_inst.sha3_inst.u_keccak.u_state_regs, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3padFsmCheck_A, + sampler_top_inst.sha3_inst.u_pad.u_state_regs, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(WrMsgCountCheck_A, + sampler_top_inst.sha3_inst.u_pad.u_wrmsg_count, alert_tx_o[1]) + + `ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RoundCountCheck_A, + sampler_top_inst.sha3_inst.u_keccak.u_round_count, alert_tx_o[1]) + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/stimulus/testsuites/mldsa_top_nightly_random_regression.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/stimulus/testsuites/mldsa_top_nightly_random_regression.yml new file mode 100644 index 0000000000000000000000000000000000000000..4132096732474c9d1503fee3581bdb29c258916f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/stimulus/testsuites/mldsa_top_nightly_random_regression.yml @@ -0,0 +1,15 @@ +document: + schema: 1.0 + +contents: + - generator: + tags: ["L1", "MLDSA_TOP", "random"] + path: "" + weight: 100 + generations: 1020 + formats: + generate: "reseed {template}.yml -seed {seed}" + path: "{template_basename}__{seed}.yml" + templates: + $ADAMSBRIDGE_ROOT/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test : { weight 65 } + $ADAMSBRIDGE_ROOT/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test : { weight 35 } diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/stimulus/uvmf_mldsa_top_promote_regression.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/stimulus/uvmf_mldsa_top_promote_regression.yml new file mode 100644 index 0000000000000000000000000000000000000000..345970eb6698e918de8b4e206405a6c7a55d6dcb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/stimulus/uvmf_mldsa_top_promote_regression.yml @@ -0,0 +1,24 @@ +document: + schema: 1.0 + +contents: + - generator: + tags: ["L0", "uvmf_mldsa", "directed", "smoke_test"] + path: "" + weight: 100 + generations: 1 + formats: + generate: "reseed {template}.yml -seed 1" + path: "{template_basename}__1.yml" + templates: + - $ADAMSBRIDGE_ROOT/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test + - generator: + tags: ["L0", "uvmf_mldsa", "directed", "smoke_test"] + path: "" + weight: 100 + generations: 1 + formats: + generate: "reseed {template}.yml -seed 1" + path: "{template_basename}__1.yml" + templates: + - $ADAMSBRIDGE_ROOT/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/tb/PQCgenKAT_mldsa87.exe b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/tb/PQCgenKAT_mldsa87.exe new file mode 100644 index 0000000000000000000000000000000000000000..362d7358a5581f993ae4eae9dae02dfd258e3020 Binary files /dev/null and b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/tb/PQCgenKAT_mldsa87.exe differ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/tb/mldsa_top_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/tb/mldsa_top_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..d224cdbfd3212b86020849b34d351ddab6f23772 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/tb/mldsa_top_tb.sv @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// mldsa_top_tb.sv +// -------- +// +//====================================================================== + +import "DPI-C" function string getenv(input string env_name); + +`include "mldsa_config_defines.svh" + +module mldsa_top_tb + import mldsa_params_pkg::*; + import abr_prim_alert_pkg::*; +( +`ifdef VERILATOR + input bit clk_tb +`endif + ); + + `ifndef VERILATOR + int MAX_CYCLES; + int VEC_CNT; + int TEST_CMD; + + initial begin + // To use this from the command line, add "+MAX_CYCLES=" + // to override the sim timeout + if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin + $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES); + end else begin + MAX_CYCLES = 20_0000; + $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES); + end + if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin + $info("Received argument +VEC_CNT, with value %d", VEC_CNT); + end else begin + VEC_CNT = 10; + $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT); + end + if ($value$plusargs("TEST_CMD=%d", TEST_CMD)) begin + $info("Received argument +TEST_CMD, with value %d", TEST_CMD); + end else begin + TEST_CMD = 'd1; + $info("No argument provided for TEST_CMD, defaulting to %d", TEST_CMD); + end + end + `else + parameter MAX_CYCLES = 20_0000; + `endif + + parameter AHB_ADDR_WIDTH = 32; + parameter AHB_DATA_WIDTH = 64; + + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 5; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] tc_ctr; + +`ifndef VERILATOR + reg clk_tb; +`endif + reg clk_i; + reg reset_n_tb; + reg rst_b; + reg [31 : 0] read_data; + + reg [AHB_ADDR_WIDTH-1:0] haddr_i_tb; + reg [AHB_DATA_WIDTH-1:0] hwdata_i_tb; + reg hsel_i_tb; + reg hwrite_i_tb; + reg hready_i_tb; + reg [1:0] htrans_i_tb; + reg [2:0] hsize_i_tb; + + wire hresp_o_tb; + wire hreadyout_o_tb; + wire [AHB_DATA_WIDTH-1:0] hrdata_o_tb; + + reg [31:0] write_data; + + assign clk_i = clk_tb; + assign rst_b = reset_n_tb; + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + + assign hready_i_tb = hreadyout_o_tb; + + mldsa_top + dut ( + .clk(clk_i), + .rst_b(rst_b), + .haddr_i(haddr_i_tb), + .hready_i(hready_i_tb), + .hsel_i(hsel_i_tb), + .hsize_i(hsize_i_tb), + .htrans_i(htrans_i_tb), + .hwdata_i(hwdata_i_tb), + .hwrite_i(hwrite_i_tb), + + .hresp_o(hresp_o_tb), + .hrdata_o(hrdata_o_tb), + .hreadyout_o(hreadyout_o_tb) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- +`ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen +`endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + + // Test timeout monitor + if(cycle_ctr == MAX_CYCLES) begin + $error("Hit max cycle count (%0d) .. stopping",cycle_ctr); + $finish; + end + end + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + + repeat (2) @(posedge clk_tb); + + $display(""); + end + endtask // reset_dut + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + error_ctr = '0; + tc_ctr = '0; +`ifndef VERILATOR + clk_tb = 0; +`endif + reset_n_tb = 0; + + haddr_i_tb = 'Z; + hwdata_i_tb = 'Z; + hsel_i_tb = 0; + hwrite_i_tb = 0; + htrans_i_tb = 0; + hsize_i_tb = 3'b011; + + end + endtask // init_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + //---------------------------------------------------------------- + // write_single_msg() + // + // Write the given msg to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_single_word_ahb(input [31 : 0] address, input [31 : 0] word); + begin + hsel_i_tb <= 1; + haddr_i_tb <= address; + hwrite_i_tb <= 1; + htrans_i_tb <= 2; + hsize_i_tb <= 3'b010; + + @(posedge clk_tb); + haddr_i_tb <= 'Z; + hwdata_i_tb <= address[2] ? {word, 32'h0}: {32'h0, word}; + hwrite_i_tb <= 0; + htrans_i_tb <= 0; + wait(hreadyout_o_tb == 1'b1); + + @(posedge clk_tb); + hsel_i_tb <= 0; + + end + endtask // write_single_word_ahb + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + + initial + begin : main + $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED")); + $display(" -- Testbench for MLDSA started --"); + + init_sim(); + reset_dut(); + + if (TEST_CMD == 2) begin + //Write PRIVKEY_IN + for (int key_loop = 0; key_loop < 1224; key_loop++) begin + write_data = $urandom(); + write_single_word_ahb((32'h4000 + key_loop*4), write_data); + end + end + + write_single_word_ahb('h10, TEST_CMD); + + $display(" -- Testbench for MLDSA done. --"); + + wait(0) + + $finish; + end // main + + // abr_prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o; + + // `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3FsmCheck_A, + // dut.sampler_top_inst.sha3_inst.u_state_regs, alert_tx_o[1]) + + // `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(KeccakRoundFsmCheck_A, + // dut.sampler_top_inst.sha3_inst.u_keccak.u_state_regs, alert_tx_o[1]) + + // `ABR_ASSERT_PRIM_FSM_ERROR_TRIGGER_ALERT(SHA3padFsmCheck_A, + // dut.sampler_top_inst.sha3_inst.u_pad.u_state_regs, alert_tx_o[1]) + + // `ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(WrMsgCountCheck_A, + // dut.sampler_top_inst.sha3_inst.u_pad.u_wrmsg_count, alert_tx_o[1]) + + // `ABR_ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(RoundCountCheck_A, + // dut.sampler_top_inst.sha3_inst.u_keccak.u_round_count, alert_tx_o[1]) + +endmodule // mldsa_tb + +//====================================================================== +// EOF mldsa_tb.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/CMakeLists.txt b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..b6f76e02e24b2e2a7feb53b699e7b5141af8b188 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/CMakeLists.txt @@ -0,0 +1,95 @@ +set(DILITHIUM_SRCS sign.c packing.c polyvec.c poly.c ntt.c reduce.c rounding.c) +set(DILITHIUM_FIPS202_SRCS ${DILITHIUM_SRCS} symmetric-shake.c) +set(DILITHIUM_AES_SRCS ${DILITHIUM_SRCS} symmetric-aes.c) +set(FIPS202_SRCS fips202.c) +set(AES256CTR_SRCS aes256ctr.c) +set(TEST_DILITHIUM_SRCS test/test_dilithium.c randombytes.c) +set(TEST_VECTORS_SRCS test/test_vectors.c) +set(TEST_SPEED_SRCS test/test_speed.c test/speed_print.c test/cpucycles.c randombytes.c) + +if(MSVC) + add_compile_options(/nologo /O2 /W4 /wd4146 /wd4244) +else() + add_compile_options(-Wall -Wextra -Wpedantic -Werror) + add_compile_options(-Wmissing-prototypes -Wredundant-decls -Wshadow -Wpointer-arith) + add_compile_options(-O3 -fomit-frame-pointer) +endif() + +add_library(fips202_ref ${FIPS202_SRCS}) +add_library(aes256ctr_ref ${AES256CTR_SRCS}) + +# Dilithium 2 +add_library(dilithium2_ref ${DILITHIUM_FIPS202_SRCS}) +add_library(dilithium2aes_ref ${DILITHIUM_AES_SRCS}) +target_compile_definitions(dilithium2_ref PUBLIC DILITHIUM_MODE=2) +target_compile_definitions(dilithium2aes_ref PUBLIC DILITHIUM_MODE=2 DILITHIUM_USE_AES) +target_link_libraries(dilithium2_ref INTERFACE fips202_ref) +target_link_libraries(dilithium2aes_ref INTERFACE fips202_ref aes256ctr_ref) + +add_executable(test_dilithium2_ref ${TEST_DILITHIUM_SRCS}) +add_executable(test_vectors2_ref ${TEST_VECTORS_SRCS}) +add_executable(test_dilithium2aes_ref ${TEST_DILITHIUM_SRCS}) +add_executable(test_vectors2aes_ref ${TEST_VECTORS_SRCS}) +target_link_libraries(test_dilithium2_ref dilithium2_ref) +target_link_libraries(test_vectors2_ref dilithium2_ref) +target_link_libraries(test_dilithium2aes_ref dilithium2aes_ref) +target_link_libraries(test_vectors2aes_ref dilithium2aes_ref) + +# Dilithium 3 +add_library(dilithium3_ref ${DILITHIUM_FIPS202_SRCS}) +add_library(dilithium3aes_ref ${DILITHIUM_AES_SRCS}) +target_compile_definitions(dilithium3_ref PUBLIC DILITHIUM_MODE=3) +target_compile_definitions(dilithium3aes_ref PUBLIC DILITHIUM_MODE=3 DILITHIUM_USE_AES) +target_link_libraries(dilithium3_ref INTERFACE fips202_ref) +target_link_libraries(dilithium3aes_ref INTERFACE fips202_ref aes256ctr_ref) + +add_executable(test_dilithium3_ref ${TEST_DILITHIUM_SRCS}) +add_executable(test_vectors3_ref ${TEST_VECTORS_SRCS}) +add_executable(test_dilithium3aes_ref ${TEST_DILITHIUM_SRCS}) +add_executable(test_vectors3aes_ref ${TEST_VECTORS_SRCS}) +target_link_libraries(test_dilithium3_ref dilithium3_ref) +target_link_libraries(test_vectors3_ref dilithium3_ref) +target_link_libraries(test_dilithium3aes_ref dilithium3aes_ref) +target_link_libraries(test_vectors3aes_ref dilithium3aes_ref) + +# Dilithium 5 +add_library(dilithium5_ref ${DILITHIUM_FIPS202_SRCS}) +add_library(dilithium5aes_ref ${DILITHIUM_AES_SRCS}) +target_compile_definitions(dilithium5_ref PUBLIC DILITHIUM_MODE=5) +target_compile_definitions(dilithium5aes_ref PUBLIC DILITHIUM_MODE=5 DILITHIUM_USE_AES) +target_link_libraries(dilithium5_ref INTERFACE fips202_ref) +target_link_libraries(dilithium5aes_ref INTERFACE fips202_ref aes256ctr_ref) + +add_executable(test_dilithium5_ref ${TEST_DILITHIUM_SRCS}) +add_executable(test_vectors5_ref ${TEST_VECTORS_SRCS}) +add_executable(test_dilithium5aes_ref ${TEST_DILITHIUM_SRCS}) +add_executable(test_vectors5aes_ref ${TEST_VECTORS_SRCS}) +target_link_libraries(test_dilithium5_ref dilithium5_ref) +target_link_libraries(test_vectors5_ref dilithium5_ref) +target_link_libraries(test_dilithium5aes_ref dilithium5aes_ref) +target_link_libraries(test_vectors5aes_ref dilithium5aes_ref) + +add_test(NAME dilithium2_ref COMMAND test_dilithium2_ref) +add_test(NAME dilithium2aes_ref COMMAND test_dilithium2aes_ref) +add_test(NAME dilithium3_ref COMMAND test_dilithium3_ref) +add_test(NAME dilithium3aes_ref COMMAND test_dilithium3aes_ref) +add_test(NAME dilithium5_ref COMMAND test_dilithium5_ref) +add_test(NAME dilithium5aes_ref COMMAND test_dilithium5aes_ref) + +if(WIN32) + add_test(NAME vectors2_ref COMMAND PowerShell -Command "$ | dos2unix > tvecs2") + add_test(NAME vectors2aes_ref COMMAND PowerShell -Command "$ | dos2unix > tvecs2aes") + add_test(NAME vectors3_ref COMMAND PowerShell -Command "$ | dos2unix > tvecs3") + add_test(NAME vectors3aes_ref COMMAND PowerShell -Command "$ | dos2unix > tvecs3aes") + add_test(NAME vectors5_ref COMMAND PowerShell -Command "$ | dos2unix > tvecs5") + add_test(NAME vectors5aes_ref COMMAND PowerShell -Command "$ | dos2unix > tvecs5aes") +else() + add_test(NAME vectors2_ref COMMAND sh -c "\"$\" > tvecs2") + add_test(NAME vectors2aes_ref COMMAND sh -c "\"$\" > tvecs2aes") + add_test(NAME vectors3_ref COMMAND sh -c "\"$\" > tvecs3") + add_test(NAME vectors3aes_ref COMMAND sh -c "\"$\" > tvecs3aes") + add_test(NAME vectors5_ref COMMAND sh -c "\"$\" > tvecs5") + add_test(NAME vectors5aes_ref COMMAND sh -c "\"$\" > tvecs5aes") +endif() + +add_test(NAME hashes COMMAND sha256sum -c ../../SHA256SUMS) diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/Makefile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..f871404ea5fe45fd7e3d3fbdde8c38637b6aae70 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/Makefile @@ -0,0 +1,249 @@ +CC ?= /usr/bin/cc +CFLAGS += -Wall -Wextra -Wpedantic -Wmissing-prototypes -Wredundant-decls \ + -Wshadow -Wvla -Wpointer-arith -O3 -fomit-frame-pointer +NISTFLAGS += -Wno-unused-result -O3 -fomit-frame-pointer +SOURCES = sign.c packing.c polyvec.c poly.c ntt.c reduce.c rounding.c +HEADERS = config.h params.h api.h sign.h packing.h polyvec.h poly.h ntt.h \ + reduce.h rounding.h symmetric.h randombytes.h +KECCAK_SOURCES = $(SOURCES) fips202.c symmetric-shake.c +KECCAK_HEADERS = $(HEADERS) fips202.h +AES_SOURCES = $(SOURCES) fips202.c aes256ctr.c symmetric-aes.c +AES_HEADERS = $(HEADERS) fips202.h aes256ctr.h + +.PHONY: all speed shared clean + +all: \ + test/test_dilithium2 \ + test/test_dilithium3 \ + test/test_dilithium5 \ + test/test_dilithium2aes \ + test/test_dilithium3aes \ + test/test_dilithium5aes \ + test/test_vectors2 \ + test/test_vectors3 \ + test/test_vectors5 \ + test/test_vectors2aes \ + test/test_vectors3aes \ + test/test_vectors5aes \ + PQCgenKAT_sign2 \ + PQCgenKAT_sign3 \ + PQCgenKAT_sign5 \ + PQCgenKAT_sign2aes \ + PQCgenKAT_sign3aes \ + PQCgenKAT_sign5aes + +speed: \ + test/test_mul \ + test/test_speed2 \ + test/test_speed3 \ + test/test_speed5 \ + test/test_speed2aes \ + test/test_speed3aes \ + test/test_speed5aes + +shared: \ + libpqcrystals_dilithium2_ref.so \ + libpqcrystals_dilithium3_ref.so \ + libpqcrystals_dilithium5_ref.so \ + libpqcrystals_dilithium2aes_ref.so \ + libpqcrystals_dilithium3aes_ref.so \ + libpqcrystals_dilithium5aes_ref.so \ + libpqcrystals_fips202_ref.so \ + libpqcrystals_aes256ctr_ref.so + +libpqcrystals_fips202_ref.so: fips202.c fips202.h + $(CC) -shared -fPIC $(CFLAGS) -o $@ $< + +libpqcrystals_aes256ctr_ref.so: aes256ctr.c aes256ctr.h + $(CC) -shared -fPIC $(CFLAGS) -o $@ $< + +libpqcrystals_dilithium2_ref.so: $(SOURCES) $(HEADERS) symmetric-shake.c + $(CC) -shared -fPIC $(CFLAGS) -DDILITHIUM_MODE=2 \ + -o $@ $(SOURCES) symmetric-shake.c + +libpqcrystals_dilithium3_ref.so: $(SOURCES) $(HEADERS) symmetric-shake.c + $(CC) -shared -fPIC $(CFLAGS) -DDILITHIUM_MODE=3 \ + -o $@ $(SOURCES) symmetric-shake.c + +libpqcrystals_dilithium5_ref.so: $(SOURCES) $(HEADERS) symmetric-shake.c + $(CC) -shared -fPIC $(CFLAGS) -DDILITHIUM_MODE=5 \ + -o $@ $(SOURCES) symmetric-shake.c + +libpqcrystals_dilithium2aes_ref.so: $(SOURCES) $(HEADERS) symmetric-aes.c + $(CC) -shared -fPIC $(CFLAGS) -DDILITHIUM_MODE=2 -DDILITHIUM_USE_AES \ + -o $@ $(SOURCES) symmetric-aes.c + +libpqcrystals_dilithium3aes_ref.so: $(SOURCES) $(HEADERS) symmetric-aes.c + $(CC) -shared -fPIC $(CFLAGS) -DDILITHIUM_MODE=3 -DDILITHIUM_USE_AES \ + -o $@ $(SOURCES) symmetric-aes.c + +libpqcrystals_dilithium5aes_ref.so: $(SOURCES) $(HEADERS) symmetric-aes.c + $(CC) -shared -fPIC $(CFLAGS) -DDILITHIUM_MODE=5 -DDILITHIUM_USE_AES \ + -o $@ $(SOURCES) symmetric-aes.c + +test/test_dilithium2: test/test_dilithium.c randombytes.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=2 \ + -o $@ $< randombytes.c $(KECCAK_SOURCES) + +test/test_dilithium3: test/test_dilithium.c randombytes.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=3 \ + -o $@ $< randombytes.c $(KECCAK_SOURCES) + +test/test_dilithium5: test/test_dilithium.c randombytes.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=5 \ + -o $@ $< randombytes.c $(KECCAK_SOURCES) + +test/test_dilithium2aes: test/test_dilithium.c randombytes.c $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=2 -DDILITHIUM_USE_AES \ + -o $@ $< randombytes.c $(AES_SOURCES) + +test/test_dilithium3aes: test/test_dilithium.c randombytes.c $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=3 -DDILITHIUM_USE_AES \ + -o $@ $< randombytes.c $(AES_SOURCES) + +test/test_dilithium5aes: test/test_dilithium.c randombytes.c $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=5 -DDILITHIUM_USE_AES \ + -o $@ $< randombytes.c $(AES_SOURCES) + +test/test_vectors2: test/test_vectors.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=2 \ + -o $@ $< $(KECCAK_SOURCES) + +test/test_vectors3: test/test_vectors.c $(KECCAK_SOURCES) $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=3 \ + -o $@ $< $(KECCAK_SOURCES) + +test/test_vectors5: test/test_vectors.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=5 \ + -o $@ $< $(KECCAK_SOURCES) + +test/test_vectors2aes: test/test_vectors.c $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=2 -DDILITHIUM_USE_AES \ + -o $@ $< $(AES_SOURCES) + +test/test_vectors3aes: test/test_vectors.c $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=3 -DDILITHIUM_USE_AES \ + -o $@ $< $(AES_SOURCES) + +test/test_vectors5aes: test/test_vectors.c $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=5 -DDILITHIUM_USE_AES \ + -o $@ $< $(AES_SOURCES) + +test/test_speed2: test/test_speed.c test/speed_print.c test/speed_print.h \ + test/cpucycles.c test/cpucycles.h randombytes.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=2 \ + -o $@ $< test/speed_print.c test/cpucycles.c randombytes.c \ + $(KECCAK_SOURCES) + +test/test_speed3: test/test_speed.c test/speed_print.c test/speed_print.h \ + test/cpucycles.c test/cpucycles.h randombytes.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=3 \ + -o $@ $< test/speed_print.c test/cpucycles.c randombytes.c \ + $(KECCAK_SOURCES) + +test/test_speed5: test/test_speed.c test/speed_print.c test/speed_print.h \ + test/cpucycles.c test/cpucycles.h randombytes.c $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=5 \ + -o $@ $< test/speed_print.c test/cpucycles.c randombytes.c \ + $(KECCAK_SOURCES) + +test/test_speed2aes: test/test_speed.c test/speed_print.c test/speed_print.h \ + test/cpucycles.c test/cpucycles.h randombytes.c $(AES_SOURCES) $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=2 -DDILITHIUM_USE_AES \ + -o $@ $< test/speed_print.c test/cpucycles.c randombytes.c \ + $(AES_SOURCES) + +test/test_speed3aes: test/test_speed.c test/speed_print.c test/speed_print.h \ + test/cpucycles.c test/cpucycles.h randombytes.c $(AES_SOURCES) $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=3 -DDILITHIUM_USE_AES \ + -o $@ $< test/speed_print.c test/cpucycles.c randombytes.c \ + $(AES_SOURCES) + +test/test_speed5aes: test/test_speed.c test/speed_print.c test/speed_print.h \ + test/cpucycles.c test/cpucycles.h randombytes.c $(AES_SOURCES) $(AES_HEADERS) + $(CC) $(CFLAGS) -DDILITHIUM_MODE=5 -DDILITHIUM_USE_AES \ + -o $@ $< test/speed_print.c test/cpucycles.c randombytes.c \ + $(AES_SOURCES) + +test/test_mul: test/test_mul.c randombytes.c $(KECCAK_SOURCES) $(KECCAK_HEADERS) + $(CC) $(CFLAGS) -UDBENCH -o $@ $< randombytes.c $(KECCAK_SOURCES) + +PQCgenKAT_sign2: PQCgenKAT_sign.c rng.c rng.h $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=2 \ + -o $@ $< rng.c $(KECCAK_SOURCES) $(LDFLAGS) -lcrypto + +PQCgenKAT_sign3: PQCgenKAT_sign.c rng.c rng.h $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=3 \ + -o $@ $< rng.c $(KECCAK_SOURCES) $(LDFLAGS) -lcrypto + +PQCgenKAT_sign5: PQCgenKAT_sign.c rng.c rng.h $(KECCAK_SOURCES) \ + $(KECCAK_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=5 \ + -o $@ $< rng.c $(KECCAK_SOURCES) $(LDFLAGS) -lcrypto + +PQCgenKAT_sign2aes: PQCgenKAT_sign.c rng.c rng.h $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=2 -DDILITHIUM_USE_AES \ + -o $@ $< rng.c $(AES_SOURCES) $(LDFLAGS) -lcrypto + +PQCgenKAT_sign3aes: PQCgenKAT_sign.c rng.c rng.h $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=3 -DDILITHIUM_USE_AES \ + -o $@ $< rng.c $(AES_SOURCES) $(LDFLAGS) -lcrypto + +PQCgenKAT_sign5aes: PQCgenKAT_sign.c rng.c rng.h $(AES_SOURCES) \ + $(AES_HEADERS) + $(CC) $(NISTFLAGS) -DDILITHIUM_MODE=5 -DDILITHIUM_USE_AES \ + -o $@ $< rng.c $(AES_SOURCES) $(LDFLAGS) -lcrypto + +clean: + rm -f *~ test/*~ *.gcno *.gcda *.lcov + rm -f libpqcrystals_dilithium2_ref.so + rm -f libpqcrystals_dilithium3_ref.so + rm -f libpqcrystals_dilithium5_ref.so + rm -f libpqcrystals_dilithium2aes_ref.so + rm -f libpqcrystals_dilithium3aes_ref.so + rm -f libpqcrystals_dilithium5aes_ref.so + rm -f libpqcrystals_fips202_ref.so + rm -f libpqcrystals_aes256ctr_ref.so + rm -f test/test_dilithium2 + rm -f test/test_dilithium3 + rm -f test/test_dilithium5 + rm -f test/test_dilithium2aes + rm -f test/test_dilithium3aes + rm -f test/test_dilithium5aes + rm -f test/test_vectors2 + rm -f test/test_vectors3 + rm -f test/test_vectors5 + rm -f test/test_vectors2aes + rm -f test/test_vectors3aes + rm -f test/test_vectors5aes + rm -f test/test_speed2 + rm -f test/test_speed3 + rm -f test/test_speed5 + rm -f test/test_speed2aes + rm -f test/test_speed3aes + rm -f test/test_speed5aes + rm -f test/test_mul + rm -f PQCgenKAT_sign2 + rm -f PQCgenKAT_sign3 + rm -f PQCgenKAT_sign5 + rm -f PQCgenKAT_sign2aes + rm -f PQCgenKAT_sign3aes + rm -f PQCgenKAT_sign5aes diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/PQCgenKAT_sign.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/PQCgenKAT_sign.c new file mode 100644 index 0000000000000000000000000000000000000000..4004df61a4b4c6fa4938c1ef557137b71c6004f0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/PQCgenKAT_sign.c @@ -0,0 +1,261 @@ +// +// PQCgenKAT_sign.c +// +// Created by Bassham, Lawrence E (Fed) on 8/29/17. +// Copyright © 2017 Bassham, Lawrence E (Fed). All rights reserved. +// +#include +#include +#include +#include +#include +#include "rng.h" +#include "sign.h" + +#define MAX_MARKER_LEN 50 + +#define KAT_SUCCESS 0 +#define KAT_FILE_OPEN_ERROR -1 +#define KAT_DATA_ERROR -3 +#define KAT_CRYPTO_FAILURE -4 + +int FindMarker(FILE *infile, const char *marker); +int ReadHex(FILE *infile, unsigned char *a, int Length, char *str); +void fprintBstr(FILE *fp, char *s, unsigned char *a, unsigned long long l); + +int +main() +{ + char fn_req[32], fn_rsp[32]; + FILE *fp_req, *fp_rsp; + uint8_t seed[48]; + uint8_t msg[3300]; + uint8_t entropy_input[48]; + uint8_t *m, *sm, *m1; + size_t mlen, smlen, mlen1; + int count; + int done; + uint8_t pk[CRYPTO_PUBLICKEYBYTES], sk[CRYPTO_SECRETKEYBYTES]; + int ret_val; + + // Create the REQUEST file + sprintf(fn_req, "PQCsignKAT_%.16s.req", CRYPTO_ALGNAME); + if ( (fp_req = fopen(fn_req, "w")) == NULL ) { + printf("Couldn't open <%s> for write\n", fn_req); + return KAT_FILE_OPEN_ERROR; + } + sprintf(fn_rsp, "PQCsignKAT_%.16s.rsp", CRYPTO_ALGNAME); + if ( (fp_rsp = fopen(fn_rsp, "w")) == NULL ) { + printf("Couldn't open <%s> for write\n", fn_rsp); + return KAT_FILE_OPEN_ERROR; + } + + for (int i=0; i<48; i++) + entropy_input[i] = i; + + randombytes_init(entropy_input, NULL, 256); + for (int i=0; i<100; i++) { + fprintf(fp_req, "count = %d\n", i); + randombytes(seed, 48); + fprintBstr(fp_req, "seed = ", seed, 48); + mlen = 33*(i+1); + fprintf(fp_req, "mlen = %lu\n", mlen); + randombytes(msg, mlen); + fprintBstr(fp_req, "msg = ", msg, mlen); + fprintf(fp_req, "pk =\n"); + fprintf(fp_req, "sk =\n"); + fprintf(fp_req, "smlen =\n"); + fprintf(fp_req, "sm =\n\n"); + } + fclose(fp_req); + + //Create the RESPONSE file based on what's in the REQUEST file + if ( (fp_req = fopen(fn_req, "r")) == NULL ) { + printf("Couldn't open <%s> for read\n", fn_req); + return KAT_FILE_OPEN_ERROR; + } + + fprintf(fp_rsp, "# %s\n\n", CRYPTO_ALGNAME); + done = 0; + do { + if ( FindMarker(fp_req, "count = ") ) + fscanf(fp_req, "%d", &count); + else { + done = 1; + break; + } + fprintf(fp_rsp, "count = %d\n", count); + + if ( !ReadHex(fp_req, seed, 48, "seed = ") ) { + printf("ERROR: unable to read 'seed' from <%s>\n", fn_req); + return KAT_DATA_ERROR; + } + fprintBstr(fp_rsp, "seed = ", seed, 48); + + randombytes_init(seed, NULL, 256); + + if ( FindMarker(fp_req, "mlen = ") ) + fscanf(fp_req, "%lu", &mlen); + else { + printf("ERROR: unable to read 'mlen' from <%s>\n", fn_req); + return KAT_DATA_ERROR; + } + fprintf(fp_rsp, "mlen = %lu\n", mlen); + + m = (uint8_t *)calloc(mlen, sizeof(uint8_t)); + m1 = (uint8_t *)calloc(mlen+CRYPTO_BYTES, sizeof(uint8_t)); + sm = (uint8_t *)calloc(mlen+CRYPTO_BYTES, sizeof(uint8_t)); + + if ( !ReadHex(fp_req, m, (int)mlen, "msg = ") ) { + printf("ERROR: unable to read 'msg' from <%s>\n", fn_req); + return KAT_DATA_ERROR; + } + fprintBstr(fp_rsp, "msg = ", m, mlen); + + // Generate the public/private keypair + if ( (ret_val = crypto_sign_keypair(pk, sk)) != 0) { + printf("crypto_sign_keypair returned <%d>\n", ret_val); + return KAT_CRYPTO_FAILURE; + } + fprintBstr(fp_rsp, "pk = ", pk, CRYPTO_PUBLICKEYBYTES); + fprintBstr(fp_rsp, "sk = ", sk, CRYPTO_SECRETKEYBYTES); + + if ( (ret_val = crypto_sign(sm, &smlen, m, mlen, sk)) != 0) { + printf("crypto_sign returned <%d>\n", ret_val); + return KAT_CRYPTO_FAILURE; + } + fprintf(fp_rsp, "smlen = %lu\n", smlen); + fprintBstr(fp_rsp, "sm = ", sm, smlen); + fprintf(fp_rsp, "\n"); + + if ( (ret_val = crypto_sign_open(m1, &mlen1, sm, smlen, pk)) != 0) { + printf("crypto_sign_open returned <%d>\n", ret_val); + return KAT_CRYPTO_FAILURE; + } + + if ( mlen != mlen1 ) { + printf("crypto_sign_open returned bad 'mlen': Got <%lu>, expected <%lu>\n", mlen1, mlen); + return KAT_CRYPTO_FAILURE; + } + + if ( memcmp(m, m1, mlen) ) { + printf("crypto_sign_open returned bad 'm' value\n"); + return KAT_CRYPTO_FAILURE; + } + + free(m); + free(m1); + free(sm); + + } while ( !done ); + + fclose(fp_req); + fclose(fp_rsp); + + return KAT_SUCCESS; +} + +// +// ALLOW TO READ HEXADECIMAL ENTRY (KEYS, DATA, TEXT, etc.) +// +int +FindMarker(FILE *infile, const char *marker) +{ + char line[MAX_MARKER_LEN]; + int i, len; + int curr_line; + + len = (int)strlen(marker); + if ( len > MAX_MARKER_LEN-1 ) + len = MAX_MARKER_LEN-1; + + for ( i=0; i= '0') && (ch <= '9') ) + ich = ch - '0'; + else if ( (ch >= 'A') && (ch <= 'F') ) + ich = ch - 'A' + 10; + else if ( (ch >= 'a') && (ch <= 'f') ) + ich = ch - 'a' + 10; + else // shouldn't ever get here + ich = 0; + + for ( i=0; i> 4); + a[Length-1] = (a[Length-1] << 4) | ich; + } + else + return 0; + + return 1; +} + +void +fprintBstr(FILE *fp, char *s, unsigned char *a, unsigned long long l) +{ + unsigned long long i; + + fprintf(fp, "%s", s); + + for ( i=0; i + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include "aes256ctr.h" + +static inline uint32_t br_dec32le(const uint8_t *src) +{ + return (uint32_t)src[0] + | ((uint32_t)src[1] << 8) + | ((uint32_t)src[2] << 16) + | ((uint32_t)src[3] << 24); +} + +static void br_range_dec32le(uint32_t *v, size_t num, const uint8_t *src) +{ + while (num-- > 0) { + *v ++ = br_dec32le(src); + src += 4; + } +} + +static inline uint32_t br_swap32(uint32_t x) +{ + x = ((x & (uint32_t)0x00FF00FF) << 8) + | ((x >> 8) & (uint32_t)0x00FF00FF); + return (x << 16) | (x >> 16); +} + +static inline void br_enc32le(uint8_t *dst, uint32_t x) +{ + dst[0] = (uint8_t)x; + dst[1] = (uint8_t)(x >> 8); + dst[2] = (uint8_t)(x >> 16); + dst[3] = (uint8_t)(x >> 24); +} + +static void br_range_enc32le(uint8_t *dst, const uint32_t *v, size_t num) +{ + while (num-- > 0) { + br_enc32le(dst, *v ++); + dst += 4; + } +} + +static void br_aes_ct64_bitslice_Sbox(uint64_t *q) +{ + /* + * This S-box implementation is a straightforward translation of + * the circuit described by Boyar and Peralta in "A new + * combinational logic minimization technique with applications + * to cryptology" (https://eprint.iacr.org/2009/191.pdf). + * + * Note that variables x* (input) and s* (output) are numbered + * in "reverse" order (x0 is the high bit, x7 is the low bit). + */ + + uint64_t x0, x1, x2, x3, x4, x5, x6, x7; + uint64_t y1, y2, y3, y4, y5, y6, y7, y8, y9; + uint64_t y10, y11, y12, y13, y14, y15, y16, y17, y18, y19; + uint64_t y20, y21; + uint64_t z0, z1, z2, z3, z4, z5, z6, z7, z8, z9; + uint64_t z10, z11, z12, z13, z14, z15, z16, z17; + uint64_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9; + uint64_t t10, t11, t12, t13, t14, t15, t16, t17, t18, t19; + uint64_t t20, t21, t22, t23, t24, t25, t26, t27, t28, t29; + uint64_t t30, t31, t32, t33, t34, t35, t36, t37, t38, t39; + uint64_t t40, t41, t42, t43, t44, t45, t46, t47, t48, t49; + uint64_t t50, t51, t52, t53, t54, t55, t56, t57, t58, t59; + uint64_t t60, t61, t62, t63, t64, t65, t66, t67; + uint64_t s0, s1, s2, s3, s4, s5, s6, s7; + + x0 = q[7]; + x1 = q[6]; + x2 = q[5]; + x3 = q[4]; + x4 = q[3]; + x5 = q[2]; + x6 = q[1]; + x7 = q[0]; + + /* + * Top linear transformation. + */ + y14 = x3 ^ x5; + y13 = x0 ^ x6; + y9 = x0 ^ x3; + y8 = x0 ^ x5; + t0 = x1 ^ x2; + y1 = t0 ^ x7; + y4 = y1 ^ x3; + y12 = y13 ^ y14; + y2 = y1 ^ x0; + y5 = y1 ^ x6; + y3 = y5 ^ y8; + t1 = x4 ^ y12; + y15 = t1 ^ x5; + y20 = t1 ^ x1; + y6 = y15 ^ x7; + y10 = y15 ^ t0; + y11 = y20 ^ y9; + y7 = x7 ^ y11; + y17 = y10 ^ y11; + y19 = y10 ^ y8; + y16 = t0 ^ y11; + y21 = y13 ^ y16; + y18 = x0 ^ y16; + + /* + * Non-linear section. + */ + t2 = y12 & y15; + t3 = y3 & y6; + t4 = t3 ^ t2; + t5 = y4 & x7; + t6 = t5 ^ t2; + t7 = y13 & y16; + t8 = y5 & y1; + t9 = t8 ^ t7; + t10 = y2 & y7; + t11 = t10 ^ t7; + t12 = y9 & y11; + t13 = y14 & y17; + t14 = t13 ^ t12; + t15 = y8 & y10; + t16 = t15 ^ t12; + t17 = t4 ^ t14; + t18 = t6 ^ t16; + t19 = t9 ^ t14; + t20 = t11 ^ t16; + t21 = t17 ^ y20; + t22 = t18 ^ y19; + t23 = t19 ^ y21; + t24 = t20 ^ y18; + + t25 = t21 ^ t22; + t26 = t21 & t23; + t27 = t24 ^ t26; + t28 = t25 & t27; + t29 = t28 ^ t22; + t30 = t23 ^ t24; + t31 = t22 ^ t26; + t32 = t31 & t30; + t33 = t32 ^ t24; + t34 = t23 ^ t33; + t35 = t27 ^ t33; + t36 = t24 & t35; + t37 = t36 ^ t34; + t38 = t27 ^ t36; + t39 = t29 & t38; + t40 = t25 ^ t39; + + t41 = t40 ^ t37; + t42 = t29 ^ t33; + t43 = t29 ^ t40; + t44 = t33 ^ t37; + t45 = t42 ^ t41; + z0 = t44 & y15; + z1 = t37 & y6; + z2 = t33 & x7; + z3 = t43 & y16; + z4 = t40 & y1; + z5 = t29 & y7; + z6 = t42 & y11; + z7 = t45 & y17; + z8 = t41 & y10; + z9 = t44 & y12; + z10 = t37 & y3; + z11 = t33 & y4; + z12 = t43 & y13; + z13 = t40 & y5; + z14 = t29 & y2; + z15 = t42 & y9; + z16 = t45 & y14; + z17 = t41 & y8; + + /* + * Bottom linear transformation. + */ + t46 = z15 ^ z16; + t47 = z10 ^ z11; + t48 = z5 ^ z13; + t49 = z9 ^ z10; + t50 = z2 ^ z12; + t51 = z2 ^ z5; + t52 = z7 ^ z8; + t53 = z0 ^ z3; + t54 = z6 ^ z7; + t55 = z16 ^ z17; + t56 = z12 ^ t48; + t57 = t50 ^ t53; + t58 = z4 ^ t46; + t59 = z3 ^ t54; + t60 = t46 ^ t57; + t61 = z14 ^ t57; + t62 = t52 ^ t58; + t63 = t49 ^ t58; + t64 = z4 ^ t59; + t65 = t61 ^ t62; + t66 = z1 ^ t63; + s0 = t59 ^ t63; + s6 = t56 ^ ~t62; + s7 = t48 ^ ~t60; + t67 = t64 ^ t65; + s3 = t53 ^ t66; + s4 = t51 ^ t66; + s5 = t47 ^ t65; + s1 = t64 ^ ~s3; + s2 = t55 ^ ~t67; + + q[7] = s0; + q[6] = s1; + q[5] = s2; + q[4] = s3; + q[3] = s4; + q[2] = s5; + q[1] = s6; + q[0] = s7; +} + +static void br_aes_ct64_ortho(uint64_t *q) +{ +#define SWAPN(cl, ch, s, x, y) do { \ + uint64_t a, b; \ + a = (x); \ + b = (y); \ + (x) = (a & (uint64_t)cl) | ((b & (uint64_t)cl) << (s)); \ + (y) = ((a & (uint64_t)ch) >> (s)) | (b & (uint64_t)ch); \ + } while (0) + +#define SWAP2(x, y) SWAPN(0x5555555555555555, 0xAAAAAAAAAAAAAAAA, 1, x, y) +#define SWAP4(x, y) SWAPN(0x3333333333333333, 0xCCCCCCCCCCCCCCCC, 2, x, y) +#define SWAP8(x, y) SWAPN(0x0F0F0F0F0F0F0F0F, 0xF0F0F0F0F0F0F0F0, 4, x, y) + + SWAP2(q[0], q[1]); + SWAP2(q[2], q[3]); + SWAP2(q[4], q[5]); + SWAP2(q[6], q[7]); + + SWAP4(q[0], q[2]); + SWAP4(q[1], q[3]); + SWAP4(q[4], q[6]); + SWAP4(q[5], q[7]); + + SWAP8(q[0], q[4]); + SWAP8(q[1], q[5]); + SWAP8(q[2], q[6]); + SWAP8(q[3], q[7]); +} + +static void br_aes_ct64_interleave_in(uint64_t *q0, uint64_t *q1, const uint32_t *w) +{ + uint64_t x0, x1, x2, x3; + + x0 = w[0]; + x1 = w[1]; + x2 = w[2]; + x3 = w[3]; + x0 |= (x0 << 16); + x1 |= (x1 << 16); + x2 |= (x2 << 16); + x3 |= (x3 << 16); + x0 &= (uint64_t)0x0000FFFF0000FFFF; + x1 &= (uint64_t)0x0000FFFF0000FFFF; + x2 &= (uint64_t)0x0000FFFF0000FFFF; + x3 &= (uint64_t)0x0000FFFF0000FFFF; + x0 |= (x0 << 8); + x1 |= (x1 << 8); + x2 |= (x2 << 8); + x3 |= (x3 << 8); + x0 &= (uint64_t)0x00FF00FF00FF00FF; + x1 &= (uint64_t)0x00FF00FF00FF00FF; + x2 &= (uint64_t)0x00FF00FF00FF00FF; + x3 &= (uint64_t)0x00FF00FF00FF00FF; + *q0 = x0 | (x2 << 8); + *q1 = x1 | (x3 << 8); +} + +static void br_aes_ct64_interleave_out(uint32_t *w, uint64_t q0, uint64_t q1) +{ + uint64_t x0, x1, x2, x3; + + x0 = q0 & (uint64_t)0x00FF00FF00FF00FF; + x1 = q1 & (uint64_t)0x00FF00FF00FF00FF; + x2 = (q0 >> 8) & (uint64_t)0x00FF00FF00FF00FF; + x3 = (q1 >> 8) & (uint64_t)0x00FF00FF00FF00FF; + x0 |= (x0 >> 8); + x1 |= (x1 >> 8); + x2 |= (x2 >> 8); + x3 |= (x3 >> 8); + x0 &= (uint64_t)0x0000FFFF0000FFFF; + x1 &= (uint64_t)0x0000FFFF0000FFFF; + x2 &= (uint64_t)0x0000FFFF0000FFFF; + x3 &= (uint64_t)0x0000FFFF0000FFFF; + w[0] = (uint32_t)x0 | (uint32_t)(x0 >> 16); + w[1] = (uint32_t)x1 | (uint32_t)(x1 >> 16); + w[2] = (uint32_t)x2 | (uint32_t)(x2 >> 16); + w[3] = (uint32_t)x3 | (uint32_t)(x3 >> 16); +} + +static const uint8_t Rcon[] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36 +}; + +static uint32_t sub_word(uint32_t x) +{ + uint64_t q[8]; + + memset(q, 0, sizeof q); + q[0] = x; + br_aes_ct64_ortho(q); + br_aes_ct64_bitslice_Sbox(q); + br_aes_ct64_ortho(q); + return (uint32_t)q[0]; +} + +static void br_aes_ct64_keysched(uint64_t *comp_skey, const uint8_t *key) +{ + int i, j, k, nk, nkf; + uint32_t tmp; + uint32_t skey[60]; + + int key_len = 32; + + nk = (int)(key_len >> 2); + nkf = (int)((14 + 1) << 2); + br_range_dec32le(skey, (key_len >> 2), key); + tmp = skey[(key_len >> 2) - 1]; + for (i = nk, j = 0, k = 0; i < nkf; i ++) { + if (j == 0) { + tmp = (tmp << 24) | (tmp >> 8); + tmp = sub_word(tmp) ^ Rcon[k]; + } else if (nk > 6 && j == 4) { + tmp = sub_word(tmp); + } + tmp ^= skey[i - nk]; + skey[i] = tmp; + if (++ j == nk) { + j = 0; + k ++; + } + } + + for (i = 0, j = 0; i < nkf; i += 4, j += 2) { + uint64_t q[8]; + + br_aes_ct64_interleave_in(&q[0], &q[4], skey + i); + q[1] = q[0]; + q[2] = q[0]; + q[3] = q[0]; + q[5] = q[4]; + q[6] = q[4]; + q[7] = q[4]; + br_aes_ct64_ortho(q); + comp_skey[j + 0] = + (q[0] & (uint64_t)0x1111111111111111) + | (q[1] & (uint64_t)0x2222222222222222) + | (q[2] & (uint64_t)0x4444444444444444) + | (q[3] & (uint64_t)0x8888888888888888); + comp_skey[j + 1] = + (q[4] & (uint64_t)0x1111111111111111) + | (q[5] & (uint64_t)0x2222222222222222) + | (q[6] & (uint64_t)0x4444444444444444) + | (q[7] & (uint64_t)0x8888888888888888); + } +} + +static void br_aes_ct64_skey_expand(uint64_t *skey, const uint64_t *comp_skey) +{ + unsigned u, v, n; + + n = (14 + 1) << 1; + for (u = 0, v = 0; u < n; u ++, v += 4) { + uint64_t x0, x1, x2, x3; + + x0 = x1 = x2 = x3 = comp_skey[u]; + x0 &= (uint64_t)0x1111111111111111; + x1 &= (uint64_t)0x2222222222222222; + x2 &= (uint64_t)0x4444444444444444; + x3 &= (uint64_t)0x8888888888888888; + x1 >>= 1; + x2 >>= 2; + x3 >>= 3; + skey[v + 0] = (x0 << 4) - x0; + skey[v + 1] = (x1 << 4) - x1; + skey[v + 2] = (x2 << 4) - x2; + skey[v + 3] = (x3 << 4) - x3; + } +} + +static inline void add_round_key(uint64_t *q, const uint64_t *sk) +{ + q[0] ^= sk[0]; + q[1] ^= sk[1]; + q[2] ^= sk[2]; + q[3] ^= sk[3]; + q[4] ^= sk[4]; + q[5] ^= sk[5]; + q[6] ^= sk[6]; + q[7] ^= sk[7]; +} + +static inline void shift_rows(uint64_t *q) +{ + int i; + + for (i = 0; i < 8; i ++) { + uint64_t x; + + x = q[i]; + q[i] = (x & (uint64_t)0x000000000000FFFF) + | ((x & (uint64_t)0x00000000FFF00000) >> 4) + | ((x & (uint64_t)0x00000000000F0000) << 12) + | ((x & (uint64_t)0x0000FF0000000000) >> 8) + | ((x & (uint64_t)0x000000FF00000000) << 8) + | ((x & (uint64_t)0xF000000000000000) >> 12) + | ((x & (uint64_t)0x0FFF000000000000) << 4); + } +} + +static inline uint64_t rotr32(uint64_t x) +{ + return (x << 32) | (x >> 32); +} + +static inline void mix_columns(uint64_t *q) +{ + uint64_t q0, q1, q2, q3, q4, q5, q6, q7; + uint64_t r0, r1, r2, r3, r4, r5, r6, r7; + + q0 = q[0]; + q1 = q[1]; + q2 = q[2]; + q3 = q[3]; + q4 = q[4]; + q5 = q[5]; + q6 = q[6]; + q7 = q[7]; + r0 = (q0 >> 16) | (q0 << 48); + r1 = (q1 >> 16) | (q1 << 48); + r2 = (q2 >> 16) | (q2 << 48); + r3 = (q3 >> 16) | (q3 << 48); + r4 = (q4 >> 16) | (q4 << 48); + r5 = (q5 >> 16) | (q5 << 48); + r6 = (q6 >> 16) | (q6 << 48); + r7 = (q7 >> 16) | (q7 << 48); + + q[0] = q7 ^ r7 ^ r0 ^ rotr32(q0 ^ r0); + q[1] = q0 ^ r0 ^ q7 ^ r7 ^ r1 ^ rotr32(q1 ^ r1); + q[2] = q1 ^ r1 ^ r2 ^ rotr32(q2 ^ r2); + q[3] = q2 ^ r2 ^ q7 ^ r7 ^ r3 ^ rotr32(q3 ^ r3); + q[4] = q3 ^ r3 ^ q7 ^ r7 ^ r4 ^ rotr32(q4 ^ r4); + q[5] = q4 ^ r4 ^ r5 ^ rotr32(q5 ^ r5); + q[6] = q5 ^ r5 ^ r6 ^ rotr32(q6 ^ r6); + q[7] = q6 ^ r6 ^ r7 ^ rotr32(q7 ^ r7); +} + +static void inc4_be(uint32_t *x) +{ + *x = br_swap32(*x)+4; + *x = br_swap32(*x); +} + +static void aes_ctr4x(uint8_t out[64], uint32_t ivw[16], uint64_t sk_exp[120]) +{ + uint32_t w[16]; + uint64_t q[8]; + int i; + + memcpy(w, ivw, sizeof(w)); + for (i = 0; i < 4; i++) { + br_aes_ct64_interleave_in(&q[i], &q[i + 4], w + (i << 2)); + } + br_aes_ct64_ortho(q); + + add_round_key(q, sk_exp); + for (i = 1; i < 14; i++) { + br_aes_ct64_bitslice_Sbox(q); + shift_rows(q); + mix_columns(q); + add_round_key(q, sk_exp + (i << 3)); + } + br_aes_ct64_bitslice_Sbox(q); + shift_rows(q); + add_round_key(q, sk_exp + 112); + + br_aes_ct64_ortho(q); + for (i = 0; i < 4; i ++) { + br_aes_ct64_interleave_out(w + (i << 2), q[i], q[i + 4]); + } + br_range_enc32le(out, w, 16); + + /* Increase counter for next 4 blocks */ + inc4_be(ivw+3); + inc4_be(ivw+7); + inc4_be(ivw+11); + inc4_be(ivw+15); +} + +static void br_aes_ct64_ctr_init(uint64_t sk_exp[120], const uint8_t *key) +{ + uint64_t skey[30]; + + br_aes_ct64_keysched(skey, key); + br_aes_ct64_skey_expand(sk_exp, skey); +} + +void aes256ctr_init(aes256ctr_ctx *s, const uint8_t key[32], const uint8_t nonce[12]) +{ + br_aes_ct64_ctr_init(s->sk_exp, key); + + br_range_dec32le(s->ivw, 3, nonce); + memcpy(s->ivw + 4, s->ivw, 3 * sizeof(uint32_t)); + memcpy(s->ivw + 8, s->ivw, 3 * sizeof(uint32_t)); + memcpy(s->ivw + 12, s->ivw, 3 * sizeof(uint32_t)); + s->ivw[ 3] = br_swap32(0); + s->ivw[ 7] = br_swap32(1); + s->ivw[11] = br_swap32(2); + s->ivw[15] = br_swap32(3); +} + +void aes256ctr_squeezeblocks(uint8_t *out, size_t nblocks, aes256ctr_ctx *s) +{ + while (nblocks > 0) { + aes_ctr4x(out, s->ivw, s->sk_exp); + out += 64; + nblocks--; + } +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/aes256ctr.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/aes256ctr.h new file mode 100644 index 0000000000000000000000000000000000000000..458213132158c9e8634ecd08f71d2f1852e11d56 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/aes256ctr.h @@ -0,0 +1,26 @@ +#ifndef AES256CTR_H +#define AES256CTR_H + +#include +#include + +#define AES256CTR_BLOCKBYTES 64 + +#define AES256CTR_NAMESPACE(s) pqcrystals_dilithium_aes256ctr_ref_##s + +typedef struct { + uint64_t sk_exp[120]; + uint32_t ivw[16]; +} aes256ctr_ctx; + +#define aes256ctr_init AES256CTR_NAMESPACE(init) +void aes256ctr_init(aes256ctr_ctx *state, + const uint8_t key[32], + const uint8_t nonce[12]); + +#define aes256ctr_squeezeblocks AES256CTR_NAMESPACE(squeezeblocks) +void aes256ctr_squeezeblocks(uint8_t *out, + size_t nblocks, + aes256ctr_ctx *state); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/api.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/api.h new file mode 100644 index 0000000000000000000000000000000000000000..ceeef106dcb7262db36908b430c914bff28c2183 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/api.h @@ -0,0 +1,152 @@ +#ifndef API_H +#define API_H + +#include +#include + +#define pqcrystals_dilithium2_PUBLICKEYBYTES 1312 +#define pqcrystals_dilithium2_SECRETKEYBYTES 2528 +#define pqcrystals_dilithium2_BYTES 2420 + +#define pqcrystals_dilithium2_ref_PUBLICKEYBYTES pqcrystals_dilithium2_PUBLICKEYBYTES +#define pqcrystals_dilithium2_ref_SECRETKEYBYTES pqcrystals_dilithium2_SECRETKEYBYTES +#define pqcrystals_dilithium2_ref_BYTES pqcrystals_dilithium2_BYTES + +int pqcrystals_dilithium2_ref_keypair(uint8_t *pk, uint8_t *sk); + +int pqcrystals_dilithium2_ref_signature(uint8_t *sig, size_t *siglen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium2_ref(uint8_t *sm, size_t *smlen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium2_ref_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +int pqcrystals_dilithium2_ref_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + +#define pqcrystals_dilithium2aes_ref_PUBLICKEYBYTES pqcrystals_dilithium2_ref_PUBLICKEYBYTES +#define pqcrystals_dilithium2aes_ref_SECRETKEYBYTES pqcrystals_dilithium2_ref_SECRETKEYBYTES +#define pqcrystals_dilithium2aes_ref_BYTES pqcrystals_dilithium2_ref_BYTES + +int pqcrystals_dilithium2aes_ref_keypair(uint8_t *pk, uint8_t *sk); + +int pqcrystals_dilithium2aes_ref_signature(uint8_t *sig, size_t *siglen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium2aes_ref(uint8_t *sm, size_t *smlen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium2aes_ref_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +int pqcrystals_dilithium2aes_ref_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + +#define pqcrystals_dilithium3_PUBLICKEYBYTES 1952 +#define pqcrystals_dilithium3_SECRETKEYBYTES 4000 +#define pqcrystals_dilithium3_BYTES 3293 + +#define pqcrystals_dilithium3_ref_PUBLICKEYBYTES pqcrystals_dilithium3_PUBLICKEYBYTES +#define pqcrystals_dilithium3_ref_SECRETKEYBYTES pqcrystals_dilithium3_SECRETKEYBYTES +#define pqcrystals_dilithium3_ref_BYTES pqcrystals_dilithium3_BYTES + +int pqcrystals_dilithium3_ref_keypair(uint8_t *pk, uint8_t *sk); + +int pqcrystals_dilithium3_ref_signature(uint8_t *sig, size_t *siglen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium3_ref(uint8_t *sm, size_t *smlen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium3_ref_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +int pqcrystals_dilithium3_ref_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + +#define pqcrystals_dilithium3aes_ref_PUBLICKEYBYTES pqcrystals_dilithium3_ref_PUBLICKEYBYTES +#define pqcrystals_dilithium3aes_ref_SECRETKEYBYTES pqcrystals_dilithium3_ref_SECRETKEYBYTES +#define pqcrystals_dilithium3aes_ref_BYTES pqcrystals_dilithium3_ref_BYTES + +int pqcrystals_dilithium3aes_ref_keypair(uint8_t *pk, uint8_t *sk); + +int pqcrystals_dilithium3aes_ref_signature(uint8_t *sig, size_t *siglen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium3aes_ref(uint8_t *sm, size_t *smlen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium3aes_ref_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +int pqcrystals_dilithium3aes_ref_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + +#define pqcrystals_dilithium5_PUBLICKEYBYTES 2592 +#define pqcrystals_dilithium5_SECRETKEYBYTES 4864 +#define pqcrystals_dilithium5_BYTES 4595 + +#define pqcrystals_dilithium5_ref_PUBLICKEYBYTES pqcrystals_dilithium5_PUBLICKEYBYTES +#define pqcrystals_dilithium5_ref_SECRETKEYBYTES pqcrystals_dilithium5_SECRETKEYBYTES +#define pqcrystals_dilithium5_ref_BYTES pqcrystals_dilithium5_BYTES + +int pqcrystals_dilithium5_ref_keypair(uint8_t *pk, uint8_t *sk); + +int pqcrystals_dilithium5_ref_signature(uint8_t *sig, size_t *siglen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium5_ref(uint8_t *sm, size_t *smlen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium5_ref_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +int pqcrystals_dilithium5_ref_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + +#define pqcrystals_dilithium5aes_ref_PUBLICKEYBYTES pqcrystals_dilithium5_ref_PUBLICKEYBYTES +#define pqcrystals_dilithium5aes_ref_SECRETKEYBYTES pqcrystals_dilithium5_ref_SECRETKEYBYTES +#define pqcrystals_dilithium5aes_ref_BYTES pqcrystals_dilithium5_ref_BYTES + +int pqcrystals_dilithium5aes_ref_keypair(uint8_t *pk, uint8_t *sk); + +int pqcrystals_dilithium5aes_ref_signature(uint8_t *sig, size_t *siglen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium5aes_ref(uint8_t *sm, size_t *smlen, + const uint8_t *m, size_t mlen, + const uint8_t *sk); + +int pqcrystals_dilithium5aes_ref_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +int pqcrystals_dilithium5aes_ref_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/config.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/config.h new file mode 100644 index 0000000000000000000000000000000000000000..47f92b39051a1c30873e78a697fa3438bf6aa992 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/config.h @@ -0,0 +1,44 @@ +#ifndef CONFIG_H +#define CONFIG_H + +//#define DILITHIUM_MODE 2 +//#define DILITHIUM_USE_AES +//#define DILITHIUM_RANDOMIZED_SIGNING +//#define USE_RDPMC +//#define DBENCH + +#ifndef DILITHIUM_MODE +#define DILITHIUM_MODE 5 +#endif + +#ifdef DILITHIUM_USE_AES +#if DILITHIUM_MODE == 2 +#define CRYPTO_ALGNAME "Dilithium2-AES" +#define DILITHIUM_NAMESPACETOP pqcrystals_dilithium2aes_ref +#define DILITHIUM_NAMESPACE(s) pqcrystals_dilithium2aes_ref_##s +#elif DILITHIUM_MODE == 3 +#define CRYPTO_ALGNAME "Dilithium3-AES" +#define DILITHIUM_NAMESPACETOP pqcrystals_dilithium3aes_ref +#define DILITHIUM_NAMESPACE(s) pqcrystals_dilithium3aes_ref_##s +#elif DILITHIUM_MODE == 5 +#define CRYPTO_ALGNAME "Dilithium5-AES" +#define DILITHIUM_NAMESPACETOP pqcrystals_dilithium5aes_ref +#define DILITHIUM_NAMESPACE(s) pqcrystals_dilithium5aes_ref_##s +#endif +#else +#if DILITHIUM_MODE == 2 +#define CRYPTO_ALGNAME "Dilithium2" +#define DILITHIUM_NAMESPACETOP pqcrystals_dilithium2_ref +#define DILITHIUM_NAMESPACE(s) pqcrystals_dilithium2_ref_##s +#elif DILITHIUM_MODE == 3 +#define CRYPTO_ALGNAME "Dilithium3" +#define DILITHIUM_NAMESPACETOP pqcrystals_dilithium3_ref +#define DILITHIUM_NAMESPACE(s) pqcrystals_dilithium3_ref_##s +#elif DILITHIUM_MODE == 5 +#define CRYPTO_ALGNAME "Dilithium5" +#define DILITHIUM_NAMESPACETOP pqcrystals_dilithium5_ref +#define DILITHIUM_NAMESPACE(s) pqcrystals_dilithium5_ref_##s +#endif +#endif + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/fips202.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/fips202.c new file mode 100644 index 0000000000000000000000000000000000000000..2afe799ea7caf4250b12ae47a361fb2177ebc4e4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/fips202.c @@ -0,0 +1,774 @@ +/* Based on the public domain implementation in crypto_hash/keccakc512/simple/ from + * http://bench.cr.yp.to/supercop.html by Ronny Van Keer and the public domain "TweetFips202" + * implementation from https://twitter.com/tweetfips202 by Gilles Van Assche, Daniel J. Bernstein, + * and Peter Schwabe */ + +#include +#include +#include "fips202.h" + +#define NROUNDS 24 +#define ROL(a, offset) ((a << offset) ^ (a >> (64-offset))) + +/************************************************* +* Name: load64 +* +* Description: Load 8 bytes into uint64_t in little-endian order +* +* Arguments: - const uint8_t *x: pointer to input byte array +* +* Returns the loaded 64-bit unsigned integer +**************************************************/ +static uint64_t load64(const uint8_t x[8]) { + unsigned int i; + uint64_t r = 0; + + for(i=0;i<8;i++) + r |= (uint64_t)x[i] << 8*i; + + return r; +} + +/************************************************* +* Name: store64 +* +* Description: Store a 64-bit integer to array of 8 bytes in little-endian order +* +* Arguments: - uint8_t *x: pointer to the output byte array (allocated) +* - uint64_t u: input 64-bit unsigned integer +**************************************************/ +static void store64(uint8_t x[8], uint64_t u) { + unsigned int i; + + for(i=0;i<8;i++) + x[i] = u >> 8*i; +} + +/* Keccak round constants */ +const uint64_t KeccakF_RoundConstants[NROUNDS] = { + (uint64_t)0x0000000000000001ULL, + (uint64_t)0x0000000000008082ULL, + (uint64_t)0x800000000000808aULL, + (uint64_t)0x8000000080008000ULL, + (uint64_t)0x000000000000808bULL, + (uint64_t)0x0000000080000001ULL, + (uint64_t)0x8000000080008081ULL, + (uint64_t)0x8000000000008009ULL, + (uint64_t)0x000000000000008aULL, + (uint64_t)0x0000000000000088ULL, + (uint64_t)0x0000000080008009ULL, + (uint64_t)0x000000008000000aULL, + (uint64_t)0x000000008000808bULL, + (uint64_t)0x800000000000008bULL, + (uint64_t)0x8000000000008089ULL, + (uint64_t)0x8000000000008003ULL, + (uint64_t)0x8000000000008002ULL, + (uint64_t)0x8000000000000080ULL, + (uint64_t)0x000000000000800aULL, + (uint64_t)0x800000008000000aULL, + (uint64_t)0x8000000080008081ULL, + (uint64_t)0x8000000000008080ULL, + (uint64_t)0x0000000080000001ULL, + (uint64_t)0x8000000080008008ULL +}; + +/************************************************* +* Name: KeccakF1600_StatePermute +* +* Description: The Keccak F1600 Permutation +* +* Arguments: - uint64_t *state: pointer to input/output Keccak state +**************************************************/ +static void KeccakF1600_StatePermute(uint64_t state[25]) +{ + int round; + + uint64_t Aba, Abe, Abi, Abo, Abu; + uint64_t Aga, Age, Agi, Ago, Agu; + uint64_t Aka, Ake, Aki, Ako, Aku; + uint64_t Ama, Ame, Ami, Amo, Amu; + uint64_t Asa, Ase, Asi, Aso, Asu; + uint64_t BCa, BCe, BCi, BCo, BCu; + uint64_t Da, De, Di, Do, Du; + uint64_t Eba, Ebe, Ebi, Ebo, Ebu; + uint64_t Ega, Ege, Egi, Ego, Egu; + uint64_t Eka, Eke, Eki, Eko, Eku; + uint64_t Ema, Eme, Emi, Emo, Emu; + uint64_t Esa, Ese, Esi, Eso, Esu; + + //copyFromState(A, state) + Aba = state[ 0]; + Abe = state[ 1]; + Abi = state[ 2]; + Abo = state[ 3]; + Abu = state[ 4]; + Aga = state[ 5]; + Age = state[ 6]; + Agi = state[ 7]; + Ago = state[ 8]; + Agu = state[ 9]; + Aka = state[10]; + Ake = state[11]; + Aki = state[12]; + Ako = state[13]; + Aku = state[14]; + Ama = state[15]; + Ame = state[16]; + Ami = state[17]; + Amo = state[18]; + Amu = state[19]; + Asa = state[20]; + Ase = state[21]; + Asi = state[22]; + Aso = state[23]; + Asu = state[24]; + + for(round = 0; round < NROUNDS; round += 2) { + // prepareTheta + BCa = Aba^Aga^Aka^Ama^Asa; + BCe = Abe^Age^Ake^Ame^Ase; + BCi = Abi^Agi^Aki^Ami^Asi; + BCo = Abo^Ago^Ako^Amo^Aso; + BCu = Abu^Agu^Aku^Amu^Asu; + + //thetaRhoPiChiIotaPrepareTheta(round, A, E) + Da = BCu^ROL(BCe, 1); + De = BCa^ROL(BCi, 1); + Di = BCe^ROL(BCo, 1); + Do = BCi^ROL(BCu, 1); + Du = BCo^ROL(BCa, 1); + + Aba ^= Da; + BCa = Aba; + Age ^= De; + BCe = ROL(Age, 44); + Aki ^= Di; + BCi = ROL(Aki, 43); + Amo ^= Do; + BCo = ROL(Amo, 21); + Asu ^= Du; + BCu = ROL(Asu, 14); + Eba = BCa ^((~BCe)& BCi ); + Eba ^= (uint64_t)KeccakF_RoundConstants[round]; + Ebe = BCe ^((~BCi)& BCo ); + Ebi = BCi ^((~BCo)& BCu ); + Ebo = BCo ^((~BCu)& BCa ); + Ebu = BCu ^((~BCa)& BCe ); + + Abo ^= Do; + BCa = ROL(Abo, 28); + Agu ^= Du; + BCe = ROL(Agu, 20); + Aka ^= Da; + BCi = ROL(Aka, 3); + Ame ^= De; + BCo = ROL(Ame, 45); + Asi ^= Di; + BCu = ROL(Asi, 61); + Ega = BCa ^((~BCe)& BCi ); + Ege = BCe ^((~BCi)& BCo ); + Egi = BCi ^((~BCo)& BCu ); + Ego = BCo ^((~BCu)& BCa ); + Egu = BCu ^((~BCa)& BCe ); + + Abe ^= De; + BCa = ROL(Abe, 1); + Agi ^= Di; + BCe = ROL(Agi, 6); + Ako ^= Do; + BCi = ROL(Ako, 25); + Amu ^= Du; + BCo = ROL(Amu, 8); + Asa ^= Da; + BCu = ROL(Asa, 18); + Eka = BCa ^((~BCe)& BCi ); + Eke = BCe ^((~BCi)& BCo ); + Eki = BCi ^((~BCo)& BCu ); + Eko = BCo ^((~BCu)& BCa ); + Eku = BCu ^((~BCa)& BCe ); + + Abu ^= Du; + BCa = ROL(Abu, 27); + Aga ^= Da; + BCe = ROL(Aga, 36); + Ake ^= De; + BCi = ROL(Ake, 10); + Ami ^= Di; + BCo = ROL(Ami, 15); + Aso ^= Do; + BCu = ROL(Aso, 56); + Ema = BCa ^((~BCe)& BCi ); + Eme = BCe ^((~BCi)& BCo ); + Emi = BCi ^((~BCo)& BCu ); + Emo = BCo ^((~BCu)& BCa ); + Emu = BCu ^((~BCa)& BCe ); + + Abi ^= Di; + BCa = ROL(Abi, 62); + Ago ^= Do; + BCe = ROL(Ago, 55); + Aku ^= Du; + BCi = ROL(Aku, 39); + Ama ^= Da; + BCo = ROL(Ama, 41); + Ase ^= De; + BCu = ROL(Ase, 2); + Esa = BCa ^((~BCe)& BCi ); + Ese = BCe ^((~BCi)& BCo ); + Esi = BCi ^((~BCo)& BCu ); + Eso = BCo ^((~BCu)& BCa ); + Esu = BCu ^((~BCa)& BCe ); + + // prepareTheta + BCa = Eba^Ega^Eka^Ema^Esa; + BCe = Ebe^Ege^Eke^Eme^Ese; + BCi = Ebi^Egi^Eki^Emi^Esi; + BCo = Ebo^Ego^Eko^Emo^Eso; + BCu = Ebu^Egu^Eku^Emu^Esu; + + //thetaRhoPiChiIotaPrepareTheta(round+1, E, A) + Da = BCu^ROL(BCe, 1); + De = BCa^ROL(BCi, 1); + Di = BCe^ROL(BCo, 1); + Do = BCi^ROL(BCu, 1); + Du = BCo^ROL(BCa, 1); + + Eba ^= Da; + BCa = Eba; + Ege ^= De; + BCe = ROL(Ege, 44); + Eki ^= Di; + BCi = ROL(Eki, 43); + Emo ^= Do; + BCo = ROL(Emo, 21); + Esu ^= Du; + BCu = ROL(Esu, 14); + Aba = BCa ^((~BCe)& BCi ); + Aba ^= (uint64_t)KeccakF_RoundConstants[round+1]; + Abe = BCe ^((~BCi)& BCo ); + Abi = BCi ^((~BCo)& BCu ); + Abo = BCo ^((~BCu)& BCa ); + Abu = BCu ^((~BCa)& BCe ); + + Ebo ^= Do; + BCa = ROL(Ebo, 28); + Egu ^= Du; + BCe = ROL(Egu, 20); + Eka ^= Da; + BCi = ROL(Eka, 3); + Eme ^= De; + BCo = ROL(Eme, 45); + Esi ^= Di; + BCu = ROL(Esi, 61); + Aga = BCa ^((~BCe)& BCi ); + Age = BCe ^((~BCi)& BCo ); + Agi = BCi ^((~BCo)& BCu ); + Ago = BCo ^((~BCu)& BCa ); + Agu = BCu ^((~BCa)& BCe ); + + Ebe ^= De; + BCa = ROL(Ebe, 1); + Egi ^= Di; + BCe = ROL(Egi, 6); + Eko ^= Do; + BCi = ROL(Eko, 25); + Emu ^= Du; + BCo = ROL(Emu, 8); + Esa ^= Da; + BCu = ROL(Esa, 18); + Aka = BCa ^((~BCe)& BCi ); + Ake = BCe ^((~BCi)& BCo ); + Aki = BCi ^((~BCo)& BCu ); + Ako = BCo ^((~BCu)& BCa ); + Aku = BCu ^((~BCa)& BCe ); + + Ebu ^= Du; + BCa = ROL(Ebu, 27); + Ega ^= Da; + BCe = ROL(Ega, 36); + Eke ^= De; + BCi = ROL(Eke, 10); + Emi ^= Di; + BCo = ROL(Emi, 15); + Eso ^= Do; + BCu = ROL(Eso, 56); + Ama = BCa ^((~BCe)& BCi ); + Ame = BCe ^((~BCi)& BCo ); + Ami = BCi ^((~BCo)& BCu ); + Amo = BCo ^((~BCu)& BCa ); + Amu = BCu ^((~BCa)& BCe ); + + Ebi ^= Di; + BCa = ROL(Ebi, 62); + Ego ^= Do; + BCe = ROL(Ego, 55); + Eku ^= Du; + BCi = ROL(Eku, 39); + Ema ^= Da; + BCo = ROL(Ema, 41); + Ese ^= De; + BCu = ROL(Ese, 2); + Asa = BCa ^((~BCe)& BCi ); + Ase = BCe ^((~BCi)& BCo ); + Asi = BCi ^((~BCo)& BCu ); + Aso = BCo ^((~BCu)& BCa ); + Asu = BCu ^((~BCa)& BCe ); + } + + //copyToState(state, A) + state[ 0] = Aba; + state[ 1] = Abe; + state[ 2] = Abi; + state[ 3] = Abo; + state[ 4] = Abu; + state[ 5] = Aga; + state[ 6] = Age; + state[ 7] = Agi; + state[ 8] = Ago; + state[ 9] = Agu; + state[10] = Aka; + state[11] = Ake; + state[12] = Aki; + state[13] = Ako; + state[14] = Aku; + state[15] = Ama; + state[16] = Ame; + state[17] = Ami; + state[18] = Amo; + state[19] = Amu; + state[20] = Asa; + state[21] = Ase; + state[22] = Asi; + state[23] = Aso; + state[24] = Asu; +} + +/************************************************* +* Name: keccak_init +* +* Description: Initializes the Keccak state. +* +* Arguments: - uint64_t *s: pointer to Keccak state +**************************************************/ +static void keccak_init(uint64_t s[25]) +{ + unsigned int i; + for(i=0;i<25;i++) + s[i] = 0; +} + +/************************************************* +* Name: keccak_absorb +* +* Description: Absorb step of Keccak; incremental. +* +* Arguments: - uint64_t *s: pointer to Keccak state +* - unsigned int pos: position in current block to be absorbed +* - unsigned int r: rate in bytes (e.g., 168 for SHAKE128) +* - const uint8_t *in: pointer to input to be absorbed into s +* - size_t inlen: length of input in bytes +* +* Returns new position pos in current block +**************************************************/ +static unsigned int keccak_absorb(uint64_t s[25], + unsigned int pos, + unsigned int r, + const uint8_t *in, + size_t inlen) +{ + unsigned int i; + + while(pos+inlen >= r) { + for(i=pos;i> 8*(i%8); + outlen -= i-pos; + pos = i; + } + + return pos; +} + + +/************************************************* +* Name: keccak_absorb_once +* +* Description: Absorb step of Keccak; +* non-incremental, starts by zeroeing the state. +* +* Arguments: - uint64_t *s: pointer to (uninitialized) output Keccak state +* - unsigned int r: rate in bytes (e.g., 168 for SHAKE128) +* - const uint8_t *in: pointer to input to be absorbed into s +* - size_t inlen: length of input in bytes +* - uint8_t p: domain-separation byte for different Keccak-derived functions +**************************************************/ +static void keccak_absorb_once(uint64_t s[25], + unsigned int r, + const uint8_t *in, + size_t inlen, + uint8_t p) +{ + unsigned int i; + + for(i=0;i<25;i++) + s[i] = 0; + + while(inlen >= r) { + for(i=0;is); + state->pos = 0; +} + +/************************************************* +* Name: shake128_absorb +* +* Description: Absorb step of the SHAKE128 XOF; incremental. +* +* Arguments: - keccak_state *state: pointer to (initialized) output Keccak state +* - const uint8_t *in: pointer to input to be absorbed into s +* - size_t inlen: length of input in bytes +**************************************************/ +void shake128_absorb(keccak_state *state, const uint8_t *in, size_t inlen) +{ + state->pos = keccak_absorb(state->s, state->pos, SHAKE128_RATE, in, inlen); +} + +/************************************************* +* Name: shake128_finalize +* +* Description: Finalize absorb step of the SHAKE128 XOF. +* +* Arguments: - keccak_state *state: pointer to Keccak state +**************************************************/ +void shake128_finalize(keccak_state *state) +{ + keccak_finalize(state->s, state->pos, SHAKE128_RATE, 0x1F); + state->pos = SHAKE128_RATE; +} + +/************************************************* +* Name: shake128_squeeze +* +* Description: Squeeze step of SHAKE128 XOF. Squeezes arbitraily many +* bytes. Can be called multiple times to keep squeezing. +* +* Arguments: - uint8_t *out: pointer to output blocks +* - size_t outlen : number of bytes to be squeezed (written to output) +* - keccak_state *s: pointer to input/output Keccak state +**************************************************/ +void shake128_squeeze(uint8_t *out, size_t outlen, keccak_state *state) +{ + state->pos = keccak_squeeze(out, outlen, state->s, state->pos, SHAKE128_RATE); +} + +/************************************************* +* Name: shake128_absorb_once +* +* Description: Initialize, absorb into and finalize SHAKE128 XOF; non-incremental. +* +* Arguments: - keccak_state *state: pointer to (uninitialized) output Keccak state +* - const uint8_t *in: pointer to input to be absorbed into s +* - size_t inlen: length of input in bytes +**************************************************/ +void shake128_absorb_once(keccak_state *state, const uint8_t *in, size_t inlen) +{ + keccak_absorb_once(state->s, SHAKE128_RATE, in, inlen, 0x1F); + state->pos = SHAKE128_RATE; +} + +/************************************************* +* Name: shake128_squeezeblocks +* +* Description: Squeeze step of SHAKE128 XOF. Squeezes full blocks of +* SHAKE128_RATE bytes each. Can be called multiple times +* to keep squeezing. Assumes new block has not yet been +* started (state->pos = SHAKE128_RATE). +* +* Arguments: - uint8_t *out: pointer to output blocks +* - size_t nblocks: number of blocks to be squeezed (written to output) +* - keccak_state *s: pointer to input/output Keccak state +**************************************************/ +void shake128_squeezeblocks(uint8_t *out, size_t nblocks, keccak_state *state) +{ + keccak_squeezeblocks(out, nblocks, state->s, SHAKE128_RATE); +} + +/************************************************* +* Name: shake256_init +* +* Description: Initilizes Keccak state for use as SHAKE256 XOF +* +* Arguments: - keccak_state *state: pointer to (uninitialized) Keccak state +**************************************************/ +void shake256_init(keccak_state *state) +{ + keccak_init(state->s); + state->pos = 0; +} + +/************************************************* +* Name: shake256_absorb +* +* Description: Absorb step of the SHAKE256 XOF; incremental. +* +* Arguments: - keccak_state *state: pointer to (initialized) output Keccak state +* - const uint8_t *in: pointer to input to be absorbed into s +* - size_t inlen: length of input in bytes +**************************************************/ +void shake256_absorb(keccak_state *state, const uint8_t *in, size_t inlen) +{ + state->pos = keccak_absorb(state->s, state->pos, SHAKE256_RATE, in, inlen); +} + +/************************************************* +* Name: shake256_finalize +* +* Description: Finalize absorb step of the SHAKE256 XOF. +* +* Arguments: - keccak_state *state: pointer to Keccak state +**************************************************/ +void shake256_finalize(keccak_state *state) +{ + keccak_finalize(state->s, state->pos, SHAKE256_RATE, 0x1F); + state->pos = SHAKE256_RATE; +} + +/************************************************* +* Name: shake256_squeeze +* +* Description: Squeeze step of SHAKE256 XOF. Squeezes arbitraily many +* bytes. Can be called multiple times to keep squeezing. +* +* Arguments: - uint8_t *out: pointer to output blocks +* - size_t outlen : number of bytes to be squeezed (written to output) +* - keccak_state *s: pointer to input/output Keccak state +**************************************************/ +void shake256_squeeze(uint8_t *out, size_t outlen, keccak_state *state) +{ + state->pos = keccak_squeeze(out, outlen, state->s, state->pos, SHAKE256_RATE); +} + +/************************************************* +* Name: shake256_absorb_once +* +* Description: Initialize, absorb into and finalize SHAKE256 XOF; non-incremental. +* +* Arguments: - keccak_state *state: pointer to (uninitialized) output Keccak state +* - const uint8_t *in: pointer to input to be absorbed into s +* - size_t inlen: length of input in bytes +**************************************************/ +void shake256_absorb_once(keccak_state *state, const uint8_t *in, size_t inlen) +{ + keccak_absorb_once(state->s, SHAKE256_RATE, in, inlen, 0x1F); + state->pos = SHAKE256_RATE; +} + +/************************************************* +* Name: shake256_squeezeblocks +* +* Description: Squeeze step of SHAKE256 XOF. Squeezes full blocks of +* SHAKE256_RATE bytes each. Can be called multiple times +* to keep squeezing. Assumes next block has not yet been +* started (state->pos = SHAKE256_RATE). +* +* Arguments: - uint8_t *out: pointer to output blocks +* - size_t nblocks: number of blocks to be squeezed (written to output) +* - keccak_state *s: pointer to input/output Keccak state +**************************************************/ +void shake256_squeezeblocks(uint8_t *out, size_t nblocks, keccak_state *state) +{ + keccak_squeezeblocks(out, nblocks, state->s, SHAKE256_RATE); +} + +/************************************************* +* Name: shake128 +* +* Description: SHAKE128 XOF with non-incremental API +* +* Arguments: - uint8_t *out: pointer to output +* - size_t outlen: requested output length in bytes +* - const uint8_t *in: pointer to input +* - size_t inlen: length of input in bytes +**************************************************/ +void shake128(uint8_t *out, size_t outlen, const uint8_t *in, size_t inlen) +{ + size_t nblocks; + keccak_state state; + + shake128_absorb_once(&state, in, inlen); + nblocks = outlen/SHAKE128_RATE; + shake128_squeezeblocks(out, nblocks, &state); + outlen -= nblocks*SHAKE128_RATE; + out += nblocks*SHAKE128_RATE; + shake128_squeeze(out, outlen, &state); +} + +/************************************************* +* Name: shake256 +* +* Description: SHAKE256 XOF with non-incremental API +* +* Arguments: - uint8_t *out: pointer to output +* - size_t outlen: requested output length in bytes +* - const uint8_t *in: pointer to input +* - size_t inlen: length of input in bytes +**************************************************/ +void shake256(uint8_t *out, size_t outlen, const uint8_t *in, size_t inlen) +{ + size_t nblocks; + keccak_state state; + + shake256_absorb_once(&state, in, inlen); + nblocks = outlen/SHAKE256_RATE; + shake256_squeezeblocks(out, nblocks, &state); + outlen -= nblocks*SHAKE256_RATE; + out += nblocks*SHAKE256_RATE; + shake256_squeeze(out, outlen, &state); +} + +/************************************************* +* Name: sha3_256 +* +* Description: SHA3-256 with non-incremental API +* +* Arguments: - uint8_t *h: pointer to output (32 bytes) +* - const uint8_t *in: pointer to input +* - size_t inlen: length of input in bytes +**************************************************/ +void sha3_256(uint8_t h[32], const uint8_t *in, size_t inlen) +{ + unsigned int i; + uint64_t s[25]; + + keccak_absorb_once(s, SHA3_256_RATE, in, inlen, 0x06); + KeccakF1600_StatePermute(s); + for(i=0;i<4;i++) + store64(h+8*i,s[i]); +} + +/************************************************* +* Name: sha3_512 +* +* Description: SHA3-512 with non-incremental API +* +* Arguments: - uint8_t *h: pointer to output (64 bytes) +* - const uint8_t *in: pointer to input +* - size_t inlen: length of input in bytes +**************************************************/ +void sha3_512(uint8_t h[64], const uint8_t *in, size_t inlen) +{ + unsigned int i; + uint64_t s[25]; + + keccak_absorb_once(s, SHA3_512_RATE, in, inlen, 0x06); + KeccakF1600_StatePermute(s); + for(i=0;i<8;i++) + store64(h+8*i,s[i]); +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/fips202.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/fips202.h new file mode 100644 index 0000000000000000000000000000000000000000..c37f5355de9f3dc531fd683924185fe1117e11c5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/fips202.h @@ -0,0 +1,57 @@ +#ifndef FIPS202_H +#define FIPS202_H + +#include +#include + +#define SHAKE128_RATE 168 +#define SHAKE256_RATE 136 +#define SHA3_256_RATE 136 +#define SHA3_512_RATE 72 + +#define FIPS202_NAMESPACE(s) pqcrystals_dilithium_fips202_ref_##s + +typedef struct { + uint64_t s[25]; + unsigned int pos; +} keccak_state; + +#define KeccakF_RoundConstants FIPS202_NAMESPACE(KeccakF_RoundConstants) +extern const uint64_t KeccakF_RoundConstants[]; + +#define shake128_init FIPS202_NAMESPACE(shake128_init) +void shake128_init(keccak_state *state); +#define shake128_absorb FIPS202_NAMESPACE(shake128_absorb) +void shake128_absorb(keccak_state *state, const uint8_t *in, size_t inlen); +#define shake128_finalize FIPS202_NAMESPACE(shake128_finalize) +void shake128_finalize(keccak_state *state); +#define shake128_squeeze FIPS202_NAMESPACE(shake128_squeeze) +void shake128_squeeze(uint8_t *out, size_t outlen, keccak_state *state); +#define shake128_absorb_once FIPS202_NAMESPACE(shake128_absorb_once) +void shake128_absorb_once(keccak_state *state, const uint8_t *in, size_t inlen); +#define shake128_squeezeblocks FIPS202_NAMESPACE(shake128_squeezeblocks) +void shake128_squeezeblocks(uint8_t *out, size_t nblocks, keccak_state *state); + +#define shake256_init FIPS202_NAMESPACE(shake256_init) +void shake256_init(keccak_state *state); +#define shake256_absorb FIPS202_NAMESPACE(shake256_absorb) +void shake256_absorb(keccak_state *state, const uint8_t *in, size_t inlen); +#define shake256_finalize FIPS202_NAMESPACE(shake256_finalize) +void shake256_finalize(keccak_state *state); +#define shake256_squeeze FIPS202_NAMESPACE(shake256_squeeze) +void shake256_squeeze(uint8_t *out, size_t outlen, keccak_state *state); +#define shake256_absorb_once FIPS202_NAMESPACE(shake256_absorb_once) +void shake256_absorb_once(keccak_state *state, const uint8_t *in, size_t inlen); +#define shake256_squeezeblocks FIPS202_NAMESPACE(shake256_squeezeblocks) +void shake256_squeezeblocks(uint8_t *out, size_t nblocks, keccak_state *state); + +#define shake128 FIPS202_NAMESPACE(shake128) +void shake128(uint8_t *out, size_t outlen, const uint8_t *in, size_t inlen); +#define shake256 FIPS202_NAMESPACE(shake256) +void shake256(uint8_t *out, size_t outlen, const uint8_t *in, size_t inlen); +#define sha3_256 FIPS202_NAMESPACE(sha3_256) +void sha3_256(uint8_t h[32], const uint8_t *in, size_t inlen); +#define sha3_512 FIPS202_NAMESPACE(sha3_512) +void sha3_512(uint8_t h[64], const uint8_t *in, size_t inlen); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/ntt.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/ntt.c new file mode 100644 index 0000000000000000000000000000000000000000..5ea8b530e11e2eb2f92b58c9f6cc21b7372c878e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/ntt.c @@ -0,0 +1,98 @@ +#include +#include "params.h" +#include "ntt.h" +#include "reduce.h" + +static const int32_t zetas[N] = { + 0, 25847, -2608894, -518909, 237124, -777960, -876248, 466468, + 1826347, 2353451, -359251, -2091905, 3119733, -2884855, 3111497, 2680103, + 2725464, 1024112, -1079900, 3585928, -549488, -1119584, 2619752, -2108549, + -2118186, -3859737, -1399561, -3277672, 1757237, -19422, 4010497, 280005, + 2706023, 95776, 3077325, 3530437, -1661693, -3592148, -2537516, 3915439, + -3861115, -3043716, 3574422, -2867647, 3539968, -300467, 2348700, -539299, + -1699267, -1643818, 3505694, -3821735, 3507263, -2140649, -1600420, 3699596, + 811944, 531354, 954230, 3881043, 3900724, -2556880, 2071892, -2797779, + -3930395, -1528703, -3677745, -3041255, -1452451, 3475950, 2176455, -1585221, + -1257611, 1939314, -4083598, -1000202, -3190144, -3157330, -3632928, 126922, + 3412210, -983419, 2147896, 2715295, -2967645, -3693493, -411027, -2477047, + -671102, -1228525, -22981, -1308169, -381987, 1349076, 1852771, -1430430, + -3343383, 264944, 508951, 3097992, 44288, -1100098, 904516, 3958618, + -3724342, -8578, 1653064, -3249728, 2389356, -210977, 759969, -1316856, + 189548, -3553272, 3159746, -1851402, -2409325, -177440, 1315589, 1341330, + 1285669, -1584928, -812732, -1439742, -3019102, -3881060, -3628969, 3839961, + 2091667, 3407706, 2316500, 3817976, -3342478, 2244091, -2446433, -3562462, + 266997, 2434439, -1235728, 3513181, -3520352, -3759364, -1197226, -3193378, + 900702, 1859098, 909542, 819034, 495491, -1613174, -43260, -522500, + -655327, -3122442, 2031748, 3207046, -3556995, -525098, -768622, -3595838, + 342297, 286988, -2437823, 4108315, 3437287, -3342277, 1735879, 203044, + 2842341, 2691481, -2590150, 1265009, 4055324, 1247620, 2486353, 1595974, + -3767016, 1250494, 2635921, -3548272, -2994039, 1869119, 1903435, -1050970, + -1333058, 1237275, -3318210, -1430225, -451100, 1312455, 3306115, -1962642, + -1279661, 1917081, -2546312, -1374803, 1500165, 777191, 2235880, 3406031, + -542412, -2831860, -1671176, -1846953, -2584293, -3724270, 594136, -3776993, + -2013608, 2432395, 2454455, -164721, 1957272, 3369112, 185531, -1207385, + -3183426, 162844, 1616392, 3014001, 810149, 1652634, -3694233, -1799107, + -3038916, 3523897, 3866901, 269760, 2213111, -975884, 1717735, 472078, + -426683, 1723600, -1803090, 1910376, -1667432, -1104333, -260646, -3833893, + -2939036, -2235985, -420899, -2286327, 183443, -976891, 1612842, -3545687, + -554416, 3919660, -48306, -1362209, 3937738, 1400424, -846154, 1976782 +}; + +/************************************************* +* Name: ntt +* +* Description: Forward NTT, in-place. No modular reduction is performed after +* additions or subtractions. Output vector is in bitreversed order. +* +* Arguments: - uint32_t p[N]: input/output coefficient array +**************************************************/ +void ntt(int32_t a[N]) { + unsigned int len, start, j, k; + int32_t zeta, t; + + k = 0; + for(len = 128; len > 0; len >>= 1) { + for(start = 0; start < N; start = j + len) { + zeta = zetas[++k]; + for(j = start; j < start + len; ++j) { + t = montgomery_reduce((int64_t)zeta * a[j + len]); + a[j + len] = a[j] - t; + a[j] = a[j] + t; + } + } + } +} + +/************************************************* +* Name: invntt_tomont +* +* Description: Inverse NTT and multiplication by Montgomery factor 2^32. +* In-place. No modular reductions after additions or +* subtractions; input coefficients need to be smaller than +* Q in absolute value. Output coefficient are smaller than Q in +* absolute value. +* +* Arguments: - uint32_t p[N]: input/output coefficient array +**************************************************/ +void invntt_tomont(int32_t a[N]) { + unsigned int start, len, j, k; + int32_t t, zeta; + const int32_t f = 41978; // mont^2/256 + + k = 256; + for(len = 1; len < N; len <<= 1) { + for(start = 0; start < N; start = j + len) { + zeta = -zetas[--k]; + for(j = start; j < start + len; ++j) { + t = a[j]; + a[j] = t + a[j + len]; + a[j + len] = t - a[j + len]; + a[j + len] = montgomery_reduce((int64_t)zeta * a[j + len]); + } + } + } + + for(j = 0; j < N; ++j) { + a[j] = montgomery_reduce((int64_t)f * a[j]); + } +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/ntt.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/ntt.h new file mode 100644 index 0000000000000000000000000000000000000000..731132d5cdfeabf454210e908cbd94097f1c5958 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/ntt.h @@ -0,0 +1,13 @@ +#ifndef NTT_H +#define NTT_H + +#include +#include "params.h" + +#define ntt DILITHIUM_NAMESPACE(ntt) +void ntt(int32_t a[N]); + +#define invntt_tomont DILITHIUM_NAMESPACE(invntt_tomont) +void invntt_tomont(int32_t a[N]); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/packing.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/packing.c new file mode 100644 index 0000000000000000000000000000000000000000..b53dcc02a1a223f362788e1c2f78cd204f61884c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/packing.c @@ -0,0 +1,323 @@ +#include "params.h" +#include "packing.h" +#include "polyvec.h" +#include "poly.h" + +/************************************************* +* Name: pack_pk +* +* Description: Bit-pack public key pk = (rho, t1). +* +* Arguments: - uint8_t pk[]: output byte array +* - const uint8_t rho[]: byte array containing rho +* - const polyveck *t1: pointer to vector t1 +**************************************************/ +void pack_pk(uint8_t pk[CRYPTO_PUBLICKEYBYTES], + const uint8_t rho[SEEDBYTES], + const polyveck *t1) +{ + unsigned int i; + + for(i = 0; i < SEEDBYTES; ++i) + pk[i] = rho[i]; + pk += SEEDBYTES; + + for(i = 0; i < K; ++i) + polyt1_pack(pk + i*POLYT1_PACKEDBYTES, &t1->vec[i]); +} + +/************************************************* +* Name: unpack_pk +* +* Description: Unpack public key pk = (rho, t1). +* +* Arguments: - const uint8_t rho[]: output byte array for rho +* - const polyveck *t1: pointer to output vector t1 +* - uint8_t pk[]: byte array containing bit-packed pk +**************************************************/ +void unpack_pk(uint8_t rho[SEEDBYTES], + polyveck *t1, + const uint8_t pk[CRYPTO_PUBLICKEYBYTES]) +{ + unsigned int i; + + for(i = 0; i < SEEDBYTES; ++i) + rho[i] = pk[i]; + pk += SEEDBYTES; + + for(i = 0; i < K; ++i) + polyt1_unpack(&t1->vec[i], pk + i*POLYT1_PACKEDBYTES); +} + +/************************************************* +* Name: pack_sk +* +* Description: Bit-pack secret key sk = (rho, tr, key, t0, s1, s2). +* +* Arguments: - uint8_t sk[]: output byte array +* - const uint8_t rho[]: byte array containing rho +* - const uint8_t tr[]: byte array containing tr +* - const uint8_t key[]: byte array containing key +* - const polyveck *t0: pointer to vector t0 +* - const polyvecl *s1: pointer to vector s1 +* - const polyveck *s2: pointer to vector s2 +**************************************************/ +// void pack_sk(uint8_t sk[CRYPTO_SECRETKEYBYTES], +// const uint8_t rho[SEEDBYTES], +// const uint8_t tr[SEEDBYTES], +// const uint8_t key[SEEDBYTES], +// const polyveck *t0, +// const polyvecl *s1, +// const polyveck *s2) +// { +// unsigned int i; + +// for(i = 0; i < SEEDBYTES; ++i) +// sk[i] = rho[i]; +// sk += SEEDBYTES; + +// for(i = 0; i < SEEDBYTES; ++i) +// sk[i] = key[i]; +// sk += SEEDBYTES; + +// for(i = 0; i < SEEDBYTES; ++i) +// sk[i] = tr[i]; +// sk += SEEDBYTES; + +// for(i = 0; i < L; ++i) +// polyeta_pack(sk + i*POLYETA_PACKEDBYTES, &s1->vec[i]); +// sk += L*POLYETA_PACKEDBYTES; + +// for(i = 0; i < K; ++i) +// polyeta_pack(sk + i*POLYETA_PACKEDBYTES, &s2->vec[i]); +// sk += K*POLYETA_PACKEDBYTES; + +// for(i = 0; i < K; ++i) +// polyt0_pack(sk + i*POLYT0_PACKEDBYTES, &t0->vec[i]); +// } + +// ===============UPDATED======================================== +// tr was 256-bit, and we fixed it: +void pack_sk(uint8_t sk[CRYPTO_SECRETKEYBYTES+SEEDBYTES], + const uint8_t rho[SEEDBYTES], + const uint8_t tr[SEEDBYTES*2], + const uint8_t key[SEEDBYTES], + const polyveck *t0, + const polyvecl *s1, + const polyveck *s2) +{ + unsigned int i; + + for(i = 0; i < SEEDBYTES; ++i) + sk[i] = rho[i]; + sk += SEEDBYTES; + + // for(i = 0; i < SEEDBYTES*2; ++i) + // sk[i] = tr[i]; + // sk += SEEDBYTES*2; + + // for(i = 0; i < SEEDBYTES; ++i) + // sk[i] = key[i]; + // sk += SEEDBYTES; + + for(i = 0; i < SEEDBYTES; ++i) + sk[i] = key[i]; + sk += SEEDBYTES; + + for(i = 0; i < SEEDBYTES*2; ++i) + sk[i] = tr[i]; + sk += SEEDBYTES*2; + + for(i = 0; i < L; ++i) + polyeta_pack(sk + i*POLYETA_PACKEDBYTES, &s1->vec[i]); + sk += L*POLYETA_PACKEDBYTES; + + for(i = 0; i < K; ++i) + polyeta_pack(sk + i*POLYETA_PACKEDBYTES, &s2->vec[i]); + sk += K*POLYETA_PACKEDBYTES; + + for(i = 0; i < K; ++i) + polyt0_pack(sk + i*POLYT0_PACKEDBYTES, &t0->vec[i]); +} + +/************************************************* +* Name: unpack_sk +* +* Description: Unpack secret key sk = (rho, tr, key, t0, s1, s2). +* +* Arguments: - const uint8_t rho[]: output byte array for rho +* - const uint8_t tr[]: output byte array for tr +* - const uint8_t key[]: output byte array for key +* - const polyveck *t0: pointer to output vector t0 +* - const polyvecl *s1: pointer to output vector s1 +* - const polyveck *s2: pointer to output vector s2 +* - uint8_t sk[]: byte array containing bit-packed sk +**************************************************/ +// void unpack_sk(uint8_t rho[SEEDBYTES], +// uint8_t tr[SEEDBYTES], +// uint8_t key[SEEDBYTES], +// polyveck *t0, +// polyvecl *s1, +// polyveck *s2, +// const uint8_t sk[CRYPTO_SECRETKEYBYTES]) +// { +// unsigned int i; + +// for(i = 0; i < SEEDBYTES; ++i) +// rho[i] = sk[i]; +// sk += SEEDBYTES; + +// for(i = 0; i < SEEDBYTES; ++i) +// key[i] = sk[i]; +// sk += SEEDBYTES; + +// for(i = 0; i < SEEDBYTES; ++i) +// tr[i] = sk[i]; +// sk += SEEDBYTES; + +// for(i=0; i < L; ++i) +// polyeta_unpack(&s1->vec[i], sk + i*POLYETA_PACKEDBYTES); +// sk += L*POLYETA_PACKEDBYTES; + +// for(i=0; i < K; ++i) +// polyeta_unpack(&s2->vec[i], sk + i*POLYETA_PACKEDBYTES); +// sk += K*POLYETA_PACKEDBYTES; + +// for(i=0; i < K; ++i) +// polyt0_unpack(&t0->vec[i], sk + i*POLYT0_PACKEDBYTES); +// } + +// ===============UPDATED======================================== +// tr was 256-bit, and we fixed it: +void unpack_sk(uint8_t rho[SEEDBYTES], + uint8_t tr[SEEDBYTES*2], + uint8_t key[SEEDBYTES], + polyveck *t0, + polyvecl *s1, + polyveck *s2, + const uint8_t sk[CRYPTO_SECRETKEYBYTES]) +{ + unsigned int i; + + for(i = 0; i < SEEDBYTES; ++i) + rho[i] = sk[i]; + sk += SEEDBYTES; + + for(i = 0; i < SEEDBYTES; ++i) + key[i] = sk[i]; + sk += SEEDBYTES; + + for(i = 0; i < SEEDBYTES*2; ++i) + tr[i] = sk[i]; + sk += SEEDBYTES*2; + + + for(i=0; i < L; ++i) + polyeta_unpack(&s1->vec[i], sk + i*POLYETA_PACKEDBYTES); + sk += L*POLYETA_PACKEDBYTES; + + for(i=0; i < K; ++i) + polyeta_unpack(&s2->vec[i], sk + i*POLYETA_PACKEDBYTES); + sk += K*POLYETA_PACKEDBYTES; + + for(i=0; i < K; ++i) + polyt0_unpack(&t0->vec[i], sk + i*POLYT0_PACKEDBYTES); +} + +/************************************************* +* Name: pack_sig +* +* Description: Bit-pack signature sig = (c, z, h). +* +* Arguments: - uint8_t sig[]: output byte array +* - const uint8_t *c: pointer to challenge hash length SEEDBYTES +* - const polyvecl *z: pointer to vector z +* - const polyveck *h: pointer to hint vector h +**************************************************/ +// Updated because the sig was gettting only 256-bit c +// Now, it gets 512-bit +void pack_sig(uint8_t sig[CRYPTO_BYTES+SEEDBYTES], + const uint8_t c[SEEDBYTES+SEEDBYTES], + const polyvecl *z, + const polyveck *h) +{ + unsigned int i, j, k; + + // for(i=0; i < SEEDBYTES; ++i) + // sig[i] = c[i]; + // sig += SEEDBYTES; + for(i=0; i < SEEDBYTES*2; ++i) + sig[i] = c[i]; + sig += SEEDBYTES*2; + + for(i = 0; i < L; ++i) + polyz_pack(sig + i*POLYZ_PACKEDBYTES, &z->vec[i]); + sig += L*POLYZ_PACKEDBYTES; + + /* Encode h */ + for(i = 0; i < OMEGA + K; ++i) + sig[i] = 0; + + k = 0; + for(i = 0; i < K; ++i) { + for(j = 0; j < N; ++j) + if(h->vec[i].coeffs[j] != 0) + sig[k++] = j; + + sig[OMEGA + i] = k; + } +} + +/************************************************* +* Name: unpack_sig +* +* Description: Unpack signature sig = (c, z, h). +* +* Arguments: - uint8_t *c: pointer to output challenge hash +* - polyvecl *z: pointer to output vector z +* - polyveck *h: pointer to output hint vector h +* - const uint8_t sig[]: byte array containing +* bit-packed signature +* +* Returns 1 in case of malformed signature; otherwise 0. +**************************************************/ +int unpack_sig(uint8_t c[SEEDBYTES*2], + polyvecl *z, + polyveck *h, + const uint8_t sig[CRYPTO_BYTES]) +{ + unsigned int i, j, k; + + for(i = 0; i < SEEDBYTES*2; ++i) + c[i] = sig[i]; + sig += SEEDBYTES*2; + + for(i = 0; i < L; ++i) + polyz_unpack(&z->vec[i], sig + i*POLYZ_PACKEDBYTES); + sig += L*POLYZ_PACKEDBYTES; + + /* Decode h */ + k = 0; + for(i = 0; i < K; ++i) { + for(j = 0; j < N; ++j) + h->vec[i].coeffs[j] = 0; + + if(sig[OMEGA + i] < k || sig[OMEGA + i] > OMEGA) + return 1; + + for(j = k; j < sig[OMEGA + i]; ++j) { + /* Coefficients are ordered for strong unforgeability */ + if(j > k && sig[j] <= sig[j-1]) return 1; + h->vec[i].coeffs[sig[j]] = 1; + } + + k = sig[OMEGA + i]; + } + + /* Extra indices are zero for strong unforgeability */ + for(j = k; j < OMEGA; ++j) + if(sig[j]) + return 1; + + return 0; +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/packing.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/packing.h new file mode 100644 index 0000000000000000000000000000000000000000..7c7cb6f4c2185589c54e8be935ded41e25a33709 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/packing.h @@ -0,0 +1,38 @@ +#ifndef PACKING_H +#define PACKING_H + +#include +#include "params.h" +#include "polyvec.h" + +#define pack_pk DILITHIUM_NAMESPACE(pack_pk) +void pack_pk(uint8_t pk[CRYPTO_PUBLICKEYBYTES], const uint8_t rho[SEEDBYTES], const polyveck *t1); + +#define pack_sk DILITHIUM_NAMESPACE(pack_sk) +void pack_sk(uint8_t sk[CRYPTO_SECRETKEYBYTES], + const uint8_t rho[SEEDBYTES], + const uint8_t tr[SEEDBYTES], + const uint8_t key[SEEDBYTES], + const polyveck *t0, + const polyvecl *s1, + const polyveck *s2); + +#define pack_sig DILITHIUM_NAMESPACE(pack_sig) +void pack_sig(uint8_t sig[CRYPTO_BYTES], const uint8_t c[SEEDBYTES], const polyvecl *z, const polyveck *h); + +#define unpack_pk DILITHIUM_NAMESPACE(unpack_pk) +void unpack_pk(uint8_t rho[SEEDBYTES], polyveck *t1, const uint8_t pk[CRYPTO_PUBLICKEYBYTES]); + +#define unpack_sk DILITHIUM_NAMESPACE(unpack_sk) +void unpack_sk(uint8_t rho[SEEDBYTES], + uint8_t tr[SEEDBYTES], + uint8_t key[SEEDBYTES], + polyveck *t0, + polyvecl *s1, + polyveck *s2, + const uint8_t sk[CRYPTO_SECRETKEYBYTES]); + +#define unpack_sig DILITHIUM_NAMESPACE(unpack_sig) +int unpack_sig(uint8_t c[SEEDBYTES], polyvecl *z, polyveck *h, const uint8_t sig[CRYPTO_BYTES]); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/params.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/params.h new file mode 100644 index 0000000000000000000000000000000000000000..ca40e50e29e555fb3daebf195e0c3bead9ceb9b3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/params.h @@ -0,0 +1,75 @@ +#ifndef PARAMS_H +#define PARAMS_H + +#include "config.h" + +#define SEEDBYTES 32 +#define CRHBYTES 64 +#define N 256 +#define Q 8380417 +#define D 13 +#define ROOT_OF_UNITY 1753 + +#if DILITHIUM_MODE == 2 +#define K 4 +#define L 4 +#define ETA 2 +#define TAU 39 +#define BETA 78 +#define GAMMA1 (1 << 17) +#define GAMMA2 ((Q-1)/88) +#define OMEGA 80 + +#elif DILITHIUM_MODE == 3 +#define K 6 +#define L 5 +#define ETA 4 +#define TAU 49 +#define BETA 196 +#define GAMMA1 (1 << 19) +#define GAMMA2 ((Q-1)/32) +#define OMEGA 55 + +#elif DILITHIUM_MODE == 5 +#define K 8 +#define L 7 +#define ETA 2 +#define TAU 60 +#define BETA 120 +#define GAMMA1 (1 << 19) +#define GAMMA2 ((Q-1)/32) +#define OMEGA 75 + +#endif + +#define POLYT1_PACKEDBYTES 320 +#define POLYT0_PACKEDBYTES 416 +#define POLYVECH_PACKEDBYTES (OMEGA + K) + +#if GAMMA1 == (1 << 17) +#define POLYZ_PACKEDBYTES 576 +#elif GAMMA1 == (1 << 19) +#define POLYZ_PACKEDBYTES 640 +#endif + +#if GAMMA2 == (Q-1)/88 +#define POLYW1_PACKEDBYTES 192 +#elif GAMMA2 == (Q-1)/32 +#define POLYW1_PACKEDBYTES 128 +#endif + +#if ETA == 2 +#define POLYETA_PACKEDBYTES 96 +#elif ETA == 4 +#define POLYETA_PACKEDBYTES 128 +#endif + +#define CRYPTO_PUBLICKEYBYTES (SEEDBYTES + K*POLYT1_PACKEDBYTES) +// It is updated 3 became 4 in order to add one more SEEDBYTES for tr +#define CRYPTO_SECRETKEYBYTES (4*SEEDBYTES \ + + L*POLYETA_PACKEDBYTES \ + + K*POLYETA_PACKEDBYTES \ + + K*POLYT0_PACKEDBYTES) +#define CRYPTO_BYTES (SEEDBYTES + L*POLYZ_PACKEDBYTES + POLYVECH_PACKEDBYTES) + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/poly.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/poly.c new file mode 100644 index 0000000000000000000000000000000000000000..4dbbb6b6de6ed69cb4506ab90de8c7536a43f286 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/poly.c @@ -0,0 +1,916 @@ +#include +#include "params.h" +#include "poly.h" +#include "ntt.h" +#include "reduce.h" +#include "rounding.h" +#include "symmetric.h" + +#ifdef DBENCH +#include "test/cpucycles.h" +extern const uint64_t timing_overhead; +extern uint64_t *tred, *tadd, *tmul, *tround, *tsample, *tpack; +#define DBENCH_START() uint64_t time = cpucycles() +#define DBENCH_STOP(t) t += cpucycles() - time - timing_overhead +#else +#define DBENCH_START() +#define DBENCH_STOP(t) +#endif + +/************************************************* +* Name: poly_reduce +* +* Description: Inplace reduction of all coefficients of polynomial to +* representative in [-6283009,6283007]. +* +* Arguments: - poly *a: pointer to input/output polynomial +**************************************************/ +void poly_reduce(poly *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + a->coeffs[i] = reduce32(a->coeffs[i]); + + DBENCH_STOP(*tred); +} + +/************************************************* +* Name: poly_caddq +* +* Description: For all coefficients of in/out polynomial add Q if +* coefficient is negative. +* +* Arguments: - poly *a: pointer to input/output polynomial +**************************************************/ +void poly_caddq(poly *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + a->coeffs[i] = caddq(a->coeffs[i]); + + DBENCH_STOP(*tred); +} + +/************************************************* +* Name: poly_add +* +* Description: Add polynomials. No modular reduction is performed. +* +* Arguments: - poly *c: pointer to output polynomial +* - const poly *a: pointer to first summand +* - const poly *b: pointer to second summand +**************************************************/ +void poly_add(poly *c, const poly *a, const poly *b) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + c->coeffs[i] = a->coeffs[i] + b->coeffs[i]; + + DBENCH_STOP(*tadd); +} + +/************************************************* +* Name: poly_sub +* +* Description: Subtract polynomials. No modular reduction is +* performed. +* +* Arguments: - poly *c: pointer to output polynomial +* - const poly *a: pointer to first input polynomial +* - const poly *b: pointer to second input polynomial to be +* subtraced from first input polynomial +**************************************************/ +void poly_sub(poly *c, const poly *a, const poly *b) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + c->coeffs[i] = a->coeffs[i] - b->coeffs[i]; + + DBENCH_STOP(*tadd); +} + +/************************************************* +* Name: poly_shiftl +* +* Description: Multiply polynomial by 2^D without modular reduction. Assumes +* input coefficients to be less than 2^{31-D} in absolute value. +* +* Arguments: - poly *a: pointer to input/output polynomial +**************************************************/ +void poly_shiftl(poly *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + a->coeffs[i] <<= D; + + DBENCH_STOP(*tmul); +} + +/************************************************* +* Name: poly_ntt +* +* Description: Inplace forward NTT. Coefficients can grow by +* 8*Q in absolute value. +* +* Arguments: - poly *a: pointer to input/output polynomial +**************************************************/ +void poly_ntt(poly *a) { + DBENCH_START(); + + ntt(a->coeffs); + + DBENCH_STOP(*tmul); +} + +/************************************************* +* Name: poly_invntt_tomont +* +* Description: Inplace inverse NTT and multiplication by 2^{32}. +* Input coefficients need to be less than Q in absolute +* value and output coefficients are again bounded by Q. +* +* Arguments: - poly *a: pointer to input/output polynomial +**************************************************/ +void poly_invntt_tomont(poly *a) { + DBENCH_START(); + + invntt_tomont(a->coeffs); + + DBENCH_STOP(*tmul); +} + +/************************************************* +* Name: poly_pointwise_montgomery +* +* Description: Pointwise multiplication of polynomials in NTT domain +* representation and multiplication of resulting polynomial +* by 2^{-32}. +* +* Arguments: - poly *c: pointer to output polynomial +* - const poly *a: pointer to first input polynomial +* - const poly *b: pointer to second input polynomial +**************************************************/ +void poly_pointwise_montgomery(poly *c, const poly *a, const poly *b) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + c->coeffs[i] = montgomery_reduce((int64_t)a->coeffs[i] * b->coeffs[i]); + + DBENCH_STOP(*tmul); +} + +/************************************************* +* Name: poly_power2round +* +* Description: For all coefficients c of the input polynomial, +* compute c0, c1 such that c mod Q = c1*2^D + c0 +* with -2^{D-1} < c0 <= 2^{D-1}. Assumes coefficients to be +* standard representatives. +* +* Arguments: - poly *a1: pointer to output polynomial with coefficients c1 +* - poly *a0: pointer to output polynomial with coefficients c0 +* - const poly *a: pointer to input polynomial +**************************************************/ +void poly_power2round(poly *a1, poly *a0, const poly *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + a1->coeffs[i] = power2round(&a0->coeffs[i], a->coeffs[i]); + + DBENCH_STOP(*tround); +} + +/************************************************* +* Name: poly_decompose +* +* Description: For all coefficients c of the input polynomial, +* compute high and low bits c0, c1 such c mod Q = c1*ALPHA + c0 +* with -ALPHA/2 < c0 <= ALPHA/2 except c1 = (Q-1)/ALPHA where we +* set c1 = 0 and -ALPHA/2 <= c0 = c mod Q - Q < 0. +* Assumes coefficients to be standard representatives. +* +* Arguments: - poly *a1: pointer to output polynomial with coefficients c1 +* - poly *a0: pointer to output polynomial with coefficients c0 +* - const poly *a: pointer to input polynomial +**************************************************/ +void poly_decompose(poly *a1, poly *a0, const poly *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + a1->coeffs[i] = decompose(&a0->coeffs[i], a->coeffs[i]); + + DBENCH_STOP(*tround); +} + +/************************************************* +* Name: poly_make_hint +* +* Description: Compute hint polynomial. The coefficients of which indicate +* whether the low bits of the corresponding coefficient of +* the input polynomial overflow into the high bits. +* +* Arguments: - poly *h: pointer to output hint polynomial +* - const poly *a0: pointer to low part of input polynomial +* - const poly *a1: pointer to high part of input polynomial +* +* Returns number of 1 bits. +**************************************************/ +unsigned int poly_make_hint(poly *h, const poly *a0, const poly *a1) { + unsigned int i, s = 0; + DBENCH_START(); + + for(i = 0; i < N; ++i) { + h->coeffs[i] = make_hint(a0->coeffs[i], a1->coeffs[i]); + s += h->coeffs[i]; + } + + DBENCH_STOP(*tround); + return s; +} + +/************************************************* +* Name: poly_use_hint +* +* Description: Use hint polynomial to correct the high bits of a polynomial. +* +* Arguments: - poly *b: pointer to output polynomial with corrected high bits +* - const poly *a: pointer to input polynomial +* - const poly *h: pointer to input hint polynomial +**************************************************/ +void poly_use_hint(poly *b, const poly *a, const poly *h) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N; ++i) + b->coeffs[i] = use_hint(a->coeffs[i], h->coeffs[i]); + + DBENCH_STOP(*tround); +} + +/************************************************* +* Name: poly_chknorm +* +* Description: Check infinity norm of polynomial against given bound. +* Assumes input coefficients were reduced by reduce32(). +* +* Arguments: - const poly *a: pointer to polynomial +* - int32_t B: norm bound +* +* Returns 0 if norm is strictly smaller than B <= (Q-1)/8 and 1 otherwise. +**************************************************/ +int poly_chknorm(const poly *a, int32_t B) { + unsigned int i; + int32_t t; + DBENCH_START(); + + if(B > (Q-1)/8) + return 1; + + /* It is ok to leak which coefficient violates the bound since + the probability for each coefficient is independent of secret + data but we must not leak the sign of the centralized representative. */ + for(i = 0; i < N; ++i) { + /* Absolute value */ + t = a->coeffs[i] >> 31; + t = a->coeffs[i] - (t & 2*a->coeffs[i]); + + if(t >= B) { + DBENCH_STOP(*tsample); + return 1; + } + } + + DBENCH_STOP(*tsample); + return 0; +} + +/************************************************* +* Name: rej_uniform +* +* Description: Sample uniformly random coefficients in [0, Q-1] by +* performing rejection sampling on array of random bytes. +* +* Arguments: - int32_t *a: pointer to output array (allocated) +* - unsigned int len: number of coefficients to be sampled +* - const uint8_t *buf: array of random bytes +* - unsigned int buflen: length of array of random bytes +* +* Returns number of sampled coefficients. Can be smaller than len if not enough +* random bytes were given. +**************************************************/ +static unsigned int rej_uniform(int32_t *a, + unsigned int len, + const uint8_t *buf, + unsigned int buflen) +{ + unsigned int ctr, pos; + uint32_t t; + DBENCH_START(); + + ctr = pos = 0; + while(ctr < len && pos + 3 <= buflen) { + t = buf[pos++]; + t |= (uint32_t)buf[pos++] << 8; + t |= (uint32_t)buf[pos++] << 16; + t &= 0x7FFFFF; + + if(t < Q) + a[ctr++] = t; + } + + DBENCH_STOP(*tsample); + return ctr; +} + +/************************************************* +* Name: poly_uniform +* +* Description: Sample polynomial with uniformly random coefficients +* in [0,Q-1] by performing rejection sampling on the +* output stream of SHAKE256(seed|nonce) or AES256CTR(seed,nonce). +* +* Arguments: - poly *a: pointer to output polynomial +* - const uint8_t seed[]: byte array with seed of length SEEDBYTES +* - uint16_t nonce: 2-byte nonce +**************************************************/ +#define POLY_UNIFORM_NBLOCKS ((768 + STREAM128_BLOCKBYTES - 1)/STREAM128_BLOCKBYTES) +void poly_uniform(poly *a, + const uint8_t seed[SEEDBYTES], + uint16_t nonce) +{ + unsigned int i, ctr, off; + unsigned int buflen = POLY_UNIFORM_NBLOCKS*STREAM128_BLOCKBYTES; + uint8_t buf[POLY_UNIFORM_NBLOCKS*STREAM128_BLOCKBYTES + 2]; + stream128_state state; + + stream128_init(&state, seed, nonce); + stream128_squeezeblocks(buf, POLY_UNIFORM_NBLOCKS, &state); + + ctr = rej_uniform(a->coeffs, N, buf, buflen); + + while(ctr < N) { + off = buflen % 3; + for(i = 0; i < off; ++i) + buf[i] = buf[buflen - off + i]; + + stream128_squeezeblocks(buf + off, 1, &state); + buflen = STREAM128_BLOCKBYTES + off; + ctr += rej_uniform(a->coeffs + ctr, N - ctr, buf, buflen); + } +} + +/************************************************* +* Name: rej_eta +* +* Description: Sample uniformly random coefficients in [-ETA, ETA] by +* performing rejection sampling on array of random bytes. +* +* Arguments: - int32_t *a: pointer to output array (allocated) +* - unsigned int len: number of coefficients to be sampled +* - const uint8_t *buf: array of random bytes +* - unsigned int buflen: length of array of random bytes +* +* Returns number of sampled coefficients. Can be smaller than len if not enough +* random bytes were given. +**************************************************/ +static unsigned int rej_eta(int32_t *a, + unsigned int len, + const uint8_t *buf, + unsigned int buflen) +{ + unsigned int ctr, pos; + uint32_t t0, t1; + DBENCH_START(); + + ctr = pos = 0; + while(ctr < len && pos < buflen) { + t0 = buf[pos] & 0x0F; + t1 = buf[pos++] >> 4; + +#if ETA == 2 + if(t0 < 15) { + t0 = t0 - (205*t0 >> 10)*5; + a[ctr++] = 2 - t0; + } + if(t1 < 15 && ctr < len) { + t1 = t1 - (205*t1 >> 10)*5; + a[ctr++] = 2 - t1; + } +#elif ETA == 4 + if(t0 < 9) + a[ctr++] = 4 - t0; + if(t1 < 9 && ctr < len) + a[ctr++] = 4 - t1; +#endif + } + + DBENCH_STOP(*tsample); + return ctr; +} + +/************************************************* +* Name: poly_uniform_eta +* +* Description: Sample polynomial with uniformly random coefficients +* in [-ETA,ETA] by performing rejection sampling on the +* output stream from SHAKE256(seed|nonce) or AES256CTR(seed,nonce). +* +* Arguments: - poly *a: pointer to output polynomial +* - const uint8_t seed[]: byte array with seed of length CRHBYTES +* - uint16_t nonce: 2-byte nonce +**************************************************/ +#if ETA == 2 +#define POLY_UNIFORM_ETA_NBLOCKS ((136 + STREAM256_BLOCKBYTES - 1)/STREAM256_BLOCKBYTES) +#elif ETA == 4 +#define POLY_UNIFORM_ETA_NBLOCKS ((227 + STREAM256_BLOCKBYTES - 1)/STREAM256_BLOCKBYTES) +#endif +void poly_uniform_eta(poly *a, + const uint8_t seed[CRHBYTES], + uint16_t nonce) +{ + unsigned int ctr; + unsigned int buflen = POLY_UNIFORM_ETA_NBLOCKS*STREAM256_BLOCKBYTES; + uint8_t buf[POLY_UNIFORM_ETA_NBLOCKS*STREAM256_BLOCKBYTES]; + stream256_state state; + + stream256_init(&state, seed, nonce); + stream256_squeezeblocks(buf, POLY_UNIFORM_ETA_NBLOCKS, &state); + + ctr = rej_eta(a->coeffs, N, buf, buflen); + + while(ctr < N) { + stream256_squeezeblocks(buf, 1, &state); + ctr += rej_eta(a->coeffs + ctr, N - ctr, buf, STREAM256_BLOCKBYTES); + } +} + +/************************************************* +* Name: poly_uniform_gamma1m1 +* +* Description: Sample polynomial with uniformly random coefficients +* in [-(GAMMA1 - 1), GAMMA1] by unpacking output stream +* of SHAKE256(seed|nonce) or AES256CTR(seed,nonce). +* +* Arguments: - poly *a: pointer to output polynomial +* - const uint8_t seed[]: byte array with seed of length CRHBYTES +* - uint16_t nonce: 16-bit nonce +**************************************************/ +#define POLY_UNIFORM_GAMMA1_NBLOCKS ((POLYZ_PACKEDBYTES + STREAM256_BLOCKBYTES - 1)/STREAM256_BLOCKBYTES) +void poly_uniform_gamma1(poly *a, + const uint8_t seed[CRHBYTES], + uint16_t nonce) +{ + uint8_t buf[POLY_UNIFORM_GAMMA1_NBLOCKS*STREAM256_BLOCKBYTES]; + stream256_state state; + + stream256_init(&state, seed, nonce); + stream256_squeezeblocks(buf, POLY_UNIFORM_GAMMA1_NBLOCKS, &state); + polyz_unpack(a, buf); +} + +/************************************************* +* Name: challenge +* +* Description: Implementation of H. Samples polynomial with TAU nonzero +* coefficients in {-1,1} using the output stream of +* SHAKE256(seed). +* +* Arguments: - poly *c: pointer to output polynomial +* - const uint8_t mu[]: byte array containing seed of length SEEDBYTES +**************************************************/ + +//=============================================================== +// ********************** FIPS Update *************************** +// void poly_challenge(poly *c, const uint8_t seed[SEEDBYTES]) { +void poly_challenge(poly *c, const uint8_t seed[SEEDBYTES*2]) { +//=============================================================== + unsigned int i, b, pos; + uint64_t signs; + uint8_t buf[SHAKE256_RATE]; + keccak_state state; + + shake256_init(&state); +//=============================================================== +// ********************** FIPS Update *************************** + // shake256_absorb(&state, seed, SEEDBYTES); + shake256_absorb(&state, seed, SEEDBYTES*2); +//=============================================================== + shake256_finalize(&state); + shake256_squeezeblocks(buf, 1, &state); + + signs = 0; + for(i = 0; i < 8; ++i) + signs |= (uint64_t)buf[i] << 8*i; + pos = 8; + + for(i = 0; i < N; ++i) + c->coeffs[i] = 0; + for(i = N-TAU; i < N; ++i) { + do { + if(pos >= SHAKE256_RATE) { + shake256_squeezeblocks(buf, 1, &state); + pos = 0; + } + + b = buf[pos++]; + } while(b > i); + + c->coeffs[i] = c->coeffs[b]; + c->coeffs[b] = 1 - 2*(signs & 1); + signs >>= 1; + } +} + +/************************************************* +* Name: polyeta_pack +* +* Description: Bit-pack polynomial with coefficients in [-ETA,ETA]. +* +* Arguments: - uint8_t *r: pointer to output byte array with at least +* POLYETA_PACKEDBYTES bytes +* - const poly *a: pointer to input polynomial +**************************************************/ +void polyeta_pack(uint8_t *r, const poly *a) { + unsigned int i; + uint8_t t[8]; + DBENCH_START(); + +#if ETA == 2 + for(i = 0; i < N/8; ++i) { + t[0] = ETA - a->coeffs[8*i+0]; + t[1] = ETA - a->coeffs[8*i+1]; + t[2] = ETA - a->coeffs[8*i+2]; + t[3] = ETA - a->coeffs[8*i+3]; + t[4] = ETA - a->coeffs[8*i+4]; + t[5] = ETA - a->coeffs[8*i+5]; + t[6] = ETA - a->coeffs[8*i+6]; + t[7] = ETA - a->coeffs[8*i+7]; + + r[3*i+0] = (t[0] >> 0) | (t[1] << 3) | (t[2] << 6); + r[3*i+1] = (t[2] >> 2) | (t[3] << 1) | (t[4] << 4) | (t[5] << 7); + r[3*i+2] = (t[5] >> 1) | (t[6] << 2) | (t[7] << 5); + } +#elif ETA == 4 + for(i = 0; i < N/2; ++i) { + t[0] = ETA - a->coeffs[2*i+0]; + t[1] = ETA - a->coeffs[2*i+1]; + r[i] = t[0] | (t[1] << 4); + } +#endif + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyeta_unpack +* +* Description: Unpack polynomial with coefficients in [-ETA,ETA]. +* +* Arguments: - poly *r: pointer to output polynomial +* - const uint8_t *a: byte array with bit-packed polynomial +**************************************************/ +void polyeta_unpack(poly *r, const uint8_t *a) { + unsigned int i; + DBENCH_START(); + +#if ETA == 2 + for(i = 0; i < N/8; ++i) { + r->coeffs[8*i+0] = (a[3*i+0] >> 0) & 7; + r->coeffs[8*i+1] = (a[3*i+0] >> 3) & 7; + r->coeffs[8*i+2] = ((a[3*i+0] >> 6) | (a[3*i+1] << 2)) & 7; + r->coeffs[8*i+3] = (a[3*i+1] >> 1) & 7; + r->coeffs[8*i+4] = (a[3*i+1] >> 4) & 7; + r->coeffs[8*i+5] = ((a[3*i+1] >> 7) | (a[3*i+2] << 1)) & 7; + r->coeffs[8*i+6] = (a[3*i+2] >> 2) & 7; + r->coeffs[8*i+7] = (a[3*i+2] >> 5) & 7; + + r->coeffs[8*i+0] = ETA - r->coeffs[8*i+0]; + r->coeffs[8*i+1] = ETA - r->coeffs[8*i+1]; + r->coeffs[8*i+2] = ETA - r->coeffs[8*i+2]; + r->coeffs[8*i+3] = ETA - r->coeffs[8*i+3]; + r->coeffs[8*i+4] = ETA - r->coeffs[8*i+4]; + r->coeffs[8*i+5] = ETA - r->coeffs[8*i+5]; + r->coeffs[8*i+6] = ETA - r->coeffs[8*i+6]; + r->coeffs[8*i+7] = ETA - r->coeffs[8*i+7]; + } +#elif ETA == 4 + for(i = 0; i < N/2; ++i) { + r->coeffs[2*i+0] = a[i] & 0x0F; + r->coeffs[2*i+1] = a[i] >> 4; + r->coeffs[2*i+0] = ETA - r->coeffs[2*i+0]; + r->coeffs[2*i+1] = ETA - r->coeffs[2*i+1]; + } +#endif + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyt1_pack +* +* Description: Bit-pack polynomial t1 with coefficients fitting in 10 bits. +* Input coefficients are assumed to be standard representatives. +* +* Arguments: - uint8_t *r: pointer to output byte array with at least +* POLYT1_PACKEDBYTES bytes +* - const poly *a: pointer to input polynomial +**************************************************/ +void polyt1_pack(uint8_t *r, const poly *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N/4; ++i) { + r[5*i+0] = (a->coeffs[4*i+0] >> 0); + r[5*i+1] = (a->coeffs[4*i+0] >> 8) | (a->coeffs[4*i+1] << 2); + r[5*i+2] = (a->coeffs[4*i+1] >> 6) | (a->coeffs[4*i+2] << 4); + r[5*i+3] = (a->coeffs[4*i+2] >> 4) | (a->coeffs[4*i+3] << 6); + r[5*i+4] = (a->coeffs[4*i+3] >> 2); + } + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyt1_unpack +* +* Description: Unpack polynomial t1 with 10-bit coefficients. +* Output coefficients are standard representatives. +* +* Arguments: - poly *r: pointer to output polynomial +* - const uint8_t *a: byte array with bit-packed polynomial +**************************************************/ +void polyt1_unpack(poly *r, const uint8_t *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N/4; ++i) { + r->coeffs[4*i+0] = ((a[5*i+0] >> 0) | ((uint32_t)a[5*i+1] << 8)) & 0x3FF; + r->coeffs[4*i+1] = ((a[5*i+1] >> 2) | ((uint32_t)a[5*i+2] << 6)) & 0x3FF; + r->coeffs[4*i+2] = ((a[5*i+2] >> 4) | ((uint32_t)a[5*i+3] << 4)) & 0x3FF; + r->coeffs[4*i+3] = ((a[5*i+3] >> 6) | ((uint32_t)a[5*i+4] << 2)) & 0x3FF; + } + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyt0_pack +* +* Description: Bit-pack polynomial t0 with coefficients in ]-2^{D-1}, 2^{D-1}]. +* +* Arguments: - uint8_t *r: pointer to output byte array with at least +* POLYT0_PACKEDBYTES bytes +* - const poly *a: pointer to input polynomial +**************************************************/ +void polyt0_pack(uint8_t *r, const poly *a) { + unsigned int i; + uint32_t t[8]; + DBENCH_START(); + + for(i = 0; i < N/8; ++i) { + t[0] = (1 << (D-1)) - a->coeffs[8*i+0]; + t[1] = (1 << (D-1)) - a->coeffs[8*i+1]; + t[2] = (1 << (D-1)) - a->coeffs[8*i+2]; + t[3] = (1 << (D-1)) - a->coeffs[8*i+3]; + t[4] = (1 << (D-1)) - a->coeffs[8*i+4]; + t[5] = (1 << (D-1)) - a->coeffs[8*i+5]; + t[6] = (1 << (D-1)) - a->coeffs[8*i+6]; + t[7] = (1 << (D-1)) - a->coeffs[8*i+7]; + + r[13*i+ 0] = t[0]; + r[13*i+ 1] = t[0] >> 8; + r[13*i+ 1] |= t[1] << 5; + r[13*i+ 2] = t[1] >> 3; + r[13*i+ 3] = t[1] >> 11; + r[13*i+ 3] |= t[2] << 2; + r[13*i+ 4] = t[2] >> 6; + r[13*i+ 4] |= t[3] << 7; + r[13*i+ 5] = t[3] >> 1; + r[13*i+ 6] = t[3] >> 9; + r[13*i+ 6] |= t[4] << 4; + r[13*i+ 7] = t[4] >> 4; + r[13*i+ 8] = t[4] >> 12; + r[13*i+ 8] |= t[5] << 1; + r[13*i+ 9] = t[5] >> 7; + r[13*i+ 9] |= t[6] << 6; + r[13*i+10] = t[6] >> 2; + r[13*i+11] = t[6] >> 10; + r[13*i+11] |= t[7] << 3; + r[13*i+12] = t[7] >> 5; + } + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyt0_unpack +* +* Description: Unpack polynomial t0 with coefficients in ]-2^{D-1}, 2^{D-1}]. +* +* Arguments: - poly *r: pointer to output polynomial +* - const uint8_t *a: byte array with bit-packed polynomial +**************************************************/ +void polyt0_unpack(poly *r, const uint8_t *a) { + unsigned int i; + DBENCH_START(); + + for(i = 0; i < N/8; ++i) { + r->coeffs[8*i+0] = a[13*i+0]; + r->coeffs[8*i+0] |= (uint32_t)a[13*i+1] << 8; + r->coeffs[8*i+0] &= 0x1FFF; + + r->coeffs[8*i+1] = a[13*i+1] >> 5; + r->coeffs[8*i+1] |= (uint32_t)a[13*i+2] << 3; + r->coeffs[8*i+1] |= (uint32_t)a[13*i+3] << 11; + r->coeffs[8*i+1] &= 0x1FFF; + + r->coeffs[8*i+2] = a[13*i+3] >> 2; + r->coeffs[8*i+2] |= (uint32_t)a[13*i+4] << 6; + r->coeffs[8*i+2] &= 0x1FFF; + + r->coeffs[8*i+3] = a[13*i+4] >> 7; + r->coeffs[8*i+3] |= (uint32_t)a[13*i+5] << 1; + r->coeffs[8*i+3] |= (uint32_t)a[13*i+6] << 9; + r->coeffs[8*i+3] &= 0x1FFF; + + r->coeffs[8*i+4] = a[13*i+6] >> 4; + r->coeffs[8*i+4] |= (uint32_t)a[13*i+7] << 4; + r->coeffs[8*i+4] |= (uint32_t)a[13*i+8] << 12; + r->coeffs[8*i+4] &= 0x1FFF; + + r->coeffs[8*i+5] = a[13*i+8] >> 1; + r->coeffs[8*i+5] |= (uint32_t)a[13*i+9] << 7; + r->coeffs[8*i+5] &= 0x1FFF; + + r->coeffs[8*i+6] = a[13*i+9] >> 6; + r->coeffs[8*i+6] |= (uint32_t)a[13*i+10] << 2; + r->coeffs[8*i+6] |= (uint32_t)a[13*i+11] << 10; + r->coeffs[8*i+6] &= 0x1FFF; + + r->coeffs[8*i+7] = a[13*i+11] >> 3; + r->coeffs[8*i+7] |= (uint32_t)a[13*i+12] << 5; + r->coeffs[8*i+7] &= 0x1FFF; + + r->coeffs[8*i+0] = (1 << (D-1)) - r->coeffs[8*i+0]; + r->coeffs[8*i+1] = (1 << (D-1)) - r->coeffs[8*i+1]; + r->coeffs[8*i+2] = (1 << (D-1)) - r->coeffs[8*i+2]; + r->coeffs[8*i+3] = (1 << (D-1)) - r->coeffs[8*i+3]; + r->coeffs[8*i+4] = (1 << (D-1)) - r->coeffs[8*i+4]; + r->coeffs[8*i+5] = (1 << (D-1)) - r->coeffs[8*i+5]; + r->coeffs[8*i+6] = (1 << (D-1)) - r->coeffs[8*i+6]; + r->coeffs[8*i+7] = (1 << (D-1)) - r->coeffs[8*i+7]; + } + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyz_pack +* +* Description: Bit-pack polynomial with coefficients +* in [-(GAMMA1 - 1), GAMMA1]. +* +* Arguments: - uint8_t *r: pointer to output byte array with at least +* POLYZ_PACKEDBYTES bytes +* - const poly *a: pointer to input polynomial +**************************************************/ +void polyz_pack(uint8_t *r, const poly *a) { + unsigned int i; + uint32_t t[4]; + DBENCH_START(); + +#if GAMMA1 == (1 << 17) + for(i = 0; i < N/4; ++i) { + t[0] = GAMMA1 - a->coeffs[4*i+0]; + t[1] = GAMMA1 - a->coeffs[4*i+1]; + t[2] = GAMMA1 - a->coeffs[4*i+2]; + t[3] = GAMMA1 - a->coeffs[4*i+3]; + + r[9*i+0] = t[0]; + r[9*i+1] = t[0] >> 8; + r[9*i+2] = t[0] >> 16; + r[9*i+2] |= t[1] << 2; + r[9*i+3] = t[1] >> 6; + r[9*i+4] = t[1] >> 14; + r[9*i+4] |= t[2] << 4; + r[9*i+5] = t[2] >> 4; + r[9*i+6] = t[2] >> 12; + r[9*i+6] |= t[3] << 6; + r[9*i+7] = t[3] >> 2; + r[9*i+8] = t[3] >> 10; + } +#elif GAMMA1 == (1 << 19) + for(i = 0; i < N/2; ++i) { + t[0] = GAMMA1 - a->coeffs[2*i+0]; + t[1] = GAMMA1 - a->coeffs[2*i+1]; + + r[5*i+0] = t[0]; + r[5*i+1] = t[0] >> 8; + r[5*i+2] = t[0] >> 16; + r[5*i+2] |= t[1] << 4; + r[5*i+3] = t[1] >> 4; + r[5*i+4] = t[1] >> 12; + } +#endif + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyz_unpack +* +* Description: Unpack polynomial z with coefficients +* in [-(GAMMA1 - 1), GAMMA1]. +* +* Arguments: - poly *r: pointer to output polynomial +* - const uint8_t *a: byte array with bit-packed polynomial +**************************************************/ +void polyz_unpack(poly *r, const uint8_t *a) { + unsigned int i; + DBENCH_START(); + +#if GAMMA1 == (1 << 17) + for(i = 0; i < N/4; ++i) { + r->coeffs[4*i+0] = a[9*i+0]; + r->coeffs[4*i+0] |= (uint32_t)a[9*i+1] << 8; + r->coeffs[4*i+0] |= (uint32_t)a[9*i+2] << 16; + r->coeffs[4*i+0] &= 0x3FFFF; + + r->coeffs[4*i+1] = a[9*i+2] >> 2; + r->coeffs[4*i+1] |= (uint32_t)a[9*i+3] << 6; + r->coeffs[4*i+1] |= (uint32_t)a[9*i+4] << 14; + r->coeffs[4*i+1] &= 0x3FFFF; + + r->coeffs[4*i+2] = a[9*i+4] >> 4; + r->coeffs[4*i+2] |= (uint32_t)a[9*i+5] << 4; + r->coeffs[4*i+2] |= (uint32_t)a[9*i+6] << 12; + r->coeffs[4*i+2] &= 0x3FFFF; + + r->coeffs[4*i+3] = a[9*i+6] >> 6; + r->coeffs[4*i+3] |= (uint32_t)a[9*i+7] << 2; + r->coeffs[4*i+3] |= (uint32_t)a[9*i+8] << 10; + r->coeffs[4*i+3] &= 0x3FFFF; + + r->coeffs[4*i+0] = GAMMA1 - r->coeffs[4*i+0]; + r->coeffs[4*i+1] = GAMMA1 - r->coeffs[4*i+1]; + r->coeffs[4*i+2] = GAMMA1 - r->coeffs[4*i+2]; + r->coeffs[4*i+3] = GAMMA1 - r->coeffs[4*i+3]; + } +#elif GAMMA1 == (1 << 19) + for(i = 0; i < N/2; ++i) { + r->coeffs[2*i+0] = a[5*i+0]; + r->coeffs[2*i+0] |= (uint32_t)a[5*i+1] << 8; + r->coeffs[2*i+0] |= (uint32_t)a[5*i+2] << 16; + r->coeffs[2*i+0] &= 0xFFFFF; + + r->coeffs[2*i+1] = a[5*i+2] >> 4; + r->coeffs[2*i+1] |= (uint32_t)a[5*i+3] << 4; + r->coeffs[2*i+1] |= (uint32_t)a[5*i+4] << 12; + r->coeffs[2*i+0] &= 0xFFFFF; + + r->coeffs[2*i+0] = GAMMA1 - r->coeffs[2*i+0]; + r->coeffs[2*i+1] = GAMMA1 - r->coeffs[2*i+1]; + } +#endif + + DBENCH_STOP(*tpack); +} + +/************************************************* +* Name: polyw1_pack +* +* Description: Bit-pack polynomial w1 with coefficients in [0,15] or [0,43]. +* Input coefficients are assumed to be standard representatives. +* +* Arguments: - uint8_t *r: pointer to output byte array with at least +* POLYW1_PACKEDBYTES bytes +* - const poly *a: pointer to input polynomial +**************************************************/ +void polyw1_pack(uint8_t *r, const poly *a) { + unsigned int i; + DBENCH_START(); + +#if GAMMA2 == (Q-1)/88 + for(i = 0; i < N/4; ++i) { + r[3*i+0] = a->coeffs[4*i+0]; + r[3*i+0] |= a->coeffs[4*i+1] << 6; + r[3*i+1] = a->coeffs[4*i+1] >> 2; + r[3*i+1] |= a->coeffs[4*i+2] << 4; + r[3*i+2] = a->coeffs[4*i+2] >> 4; + r[3*i+2] |= a->coeffs[4*i+3] << 2; + } +#elif GAMMA2 == (Q-1)/32 + for(i = 0; i < N/2; ++i) + r[i] = a->coeffs[2*i+0] | (a->coeffs[2*i+1] << 4); +#endif + + DBENCH_STOP(*tpack); +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/poly.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/poly.h new file mode 100644 index 0000000000000000000000000000000000000000..d2fd989b6a62c9f1bef50bac6c5415973b9c4798 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/poly.h @@ -0,0 +1,79 @@ +#ifndef POLY_H +#define POLY_H + +#include +#include "params.h" + +typedef struct { + int32_t coeffs[N]; +} poly; + +#define poly_reduce DILITHIUM_NAMESPACE(poly_reduce) +void poly_reduce(poly *a); +#define poly_caddq DILITHIUM_NAMESPACE(poly_caddq) +void poly_caddq(poly *a); + +#define poly_add DILITHIUM_NAMESPACE(poly_add) +void poly_add(poly *c, const poly *a, const poly *b); +#define poly_sub DILITHIUM_NAMESPACE(poly_sub) +void poly_sub(poly *c, const poly *a, const poly *b); +#define poly_shiftl DILITHIUM_NAMESPACE(poly_shiftl) +void poly_shiftl(poly *a); + +#define poly_ntt DILITHIUM_NAMESPACE(poly_ntt) +void poly_ntt(poly *a); +#define poly_invntt_tomont DILITHIUM_NAMESPACE(poly_invntt_tomont) +void poly_invntt_tomont(poly *a); +#define poly_pointwise_montgomery DILITHIUM_NAMESPACE(poly_pointwise_montgomery) +void poly_pointwise_montgomery(poly *c, const poly *a, const poly *b); + +#define poly_power2round DILITHIUM_NAMESPACE(poly_power2round) +void poly_power2round(poly *a1, poly *a0, const poly *a); +#define poly_decompose DILITHIUM_NAMESPACE(poly_decompose) +void poly_decompose(poly *a1, poly *a0, const poly *a); +#define poly_make_hint DILITHIUM_NAMESPACE(poly_make_hint) +unsigned int poly_make_hint(poly *h, const poly *a0, const poly *a1); +#define poly_use_hint DILITHIUM_NAMESPACE(poly_use_hint) +void poly_use_hint(poly *b, const poly *a, const poly *h); + +#define poly_chknorm DILITHIUM_NAMESPACE(poly_chknorm) +int poly_chknorm(const poly *a, int32_t B); +#define poly_uniform DILITHIUM_NAMESPACE(poly_uniform) +void poly_uniform(poly *a, + const uint8_t seed[SEEDBYTES], + uint16_t nonce); +#define poly_uniform_eta DILITHIUM_NAMESPACE(poly_uniform_eta) +void poly_uniform_eta(poly *a, + const uint8_t seed[CRHBYTES], + uint16_t nonce); +#define poly_uniform_gamma1 DILITHIUM_NAMESPACE(poly_uniform_gamma1) +void poly_uniform_gamma1(poly *a, + const uint8_t seed[CRHBYTES], + uint16_t nonce); +#define poly_challenge DILITHIUM_NAMESPACE(poly_challenge) +void poly_challenge(poly *c, const uint8_t seed[SEEDBYTES]); + +#define polyeta_pack DILITHIUM_NAMESPACE(polyeta_pack) +void polyeta_pack(uint8_t *r, const poly *a); +#define polyeta_unpack DILITHIUM_NAMESPACE(polyeta_unpack) +void polyeta_unpack(poly *r, const uint8_t *a); + +#define polyt1_pack DILITHIUM_NAMESPACE(polyt1_pack) +void polyt1_pack(uint8_t *r, const poly *a); +#define polyt1_unpack DILITHIUM_NAMESPACE(polyt1_unpack) +void polyt1_unpack(poly *r, const uint8_t *a); + +#define polyt0_pack DILITHIUM_NAMESPACE(polyt0_pack) +void polyt0_pack(uint8_t *r, const poly *a); +#define polyt0_unpack DILITHIUM_NAMESPACE(polyt0_unpack) +void polyt0_unpack(poly *r, const uint8_t *a); + +#define polyz_pack DILITHIUM_NAMESPACE(polyz_pack) +void polyz_pack(uint8_t *r, const poly *a); +#define polyz_unpack DILITHIUM_NAMESPACE(polyz_unpack) +void polyz_unpack(poly *r, const uint8_t *a); + +#define polyw1_pack DILITHIUM_NAMESPACE(polyw1_pack) +void polyw1_pack(uint8_t *r, const poly *a); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/polyvec.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/polyvec.c new file mode 100644 index 0000000000000000000000000000000000000000..c4e9037ab7d892552fba9d03a729762b6c5c4cb2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/polyvec.c @@ -0,0 +1,390 @@ +#include +#include "params.h" +#include "polyvec.h" +#include "poly.h" + +/************************************************* +* Name: expand_mat +* +* Description: Implementation of ExpandA. Generates matrix A with uniformly +* random coefficients a_{i,j} by performing rejection +* sampling on the output stream of SHAKE128(rho|j|i) +* or AES256CTR(rho,j|i). +* +* Arguments: - polyvecl mat[K]: output matrix +* - const uint8_t rho[]: byte array containing seed rho +**************************************************/ +void polyvec_matrix_expand(polyvecl mat[K], const uint8_t rho[SEEDBYTES]) { + unsigned int i, j; + + for(i = 0; i < K; ++i) + for(j = 0; j < L; ++j) + poly_uniform(&mat[i].vec[j], rho, (i << 8) + j); +} + +void polyvec_matrix_pointwise_montgomery(polyveck *t, const polyvecl mat[K], const polyvecl *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + polyvecl_pointwise_acc_montgomery(&t->vec[i], &mat[i], v); +} + +/**************************************************************/ +/************ Vectors of polynomials of length L **************/ +/**************************************************************/ + +void polyvecl_uniform_eta(polyvecl *v, const uint8_t seed[CRHBYTES], uint16_t nonce) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_uniform_eta(&v->vec[i], seed, nonce++); +} + +void polyvecl_uniform_gamma1(polyvecl *v, const uint8_t seed[CRHBYTES], uint16_t nonce) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_uniform_gamma1(&v->vec[i], seed, L*nonce + i); +} + +void polyvecl_reduce(polyvecl *v) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_reduce(&v->vec[i]); +} + +/************************************************* +* Name: polyvecl_add +* +* Description: Add vectors of polynomials of length L. +* No modular reduction is performed. +* +* Arguments: - polyvecl *w: pointer to output vector +* - const polyvecl *u: pointer to first summand +* - const polyvecl *v: pointer to second summand +**************************************************/ +void polyvecl_add(polyvecl *w, const polyvecl *u, const polyvecl *v) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_add(&w->vec[i], &u->vec[i], &v->vec[i]); +} + +/************************************************* +* Name: polyvecl_ntt +* +* Description: Forward NTT of all polynomials in vector of length L. Output +* coefficients can be up to 16*Q larger than input coefficients. +* +* Arguments: - polyvecl *v: pointer to input/output vector +**************************************************/ +void polyvecl_ntt(polyvecl *v) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_ntt(&v->vec[i]); +} + +void polyvecl_invntt_tomont(polyvecl *v) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_invntt_tomont(&v->vec[i]); +} + +void polyvecl_pointwise_poly_montgomery(polyvecl *r, const poly *a, const polyvecl *v) { + unsigned int i; + + for(i = 0; i < L; ++i) + poly_pointwise_montgomery(&r->vec[i], a, &v->vec[i]); +} + +/************************************************* +* Name: polyvecl_pointwise_acc_montgomery +* +* Description: Pointwise multiply vectors of polynomials of length L, multiply +* resulting vector by 2^{-32} and add (accumulate) polynomials +* in it. Input/output vectors are in NTT domain representation. +* +* Arguments: - poly *w: output polynomial +* - const polyvecl *u: pointer to first input vector +* - const polyvecl *v: pointer to second input vector +**************************************************/ +void polyvecl_pointwise_acc_montgomery(poly *w, + const polyvecl *u, + const polyvecl *v) +{ + unsigned int i; + poly t; + + poly_pointwise_montgomery(w, &u->vec[0], &v->vec[0]); + for(i = 1; i < L; ++i) { + poly_pointwise_montgomery(&t, &u->vec[i], &v->vec[i]); + poly_add(w, w, &t); + } +} + +/************************************************* +* Name: polyvecl_chknorm +* +* Description: Check infinity norm of polynomials in vector of length L. +* Assumes input polyvecl to be reduced by polyvecl_reduce(). +* +* Arguments: - const polyvecl *v: pointer to vector +* - int32_t B: norm bound +* +* Returns 0 if norm of all polynomials is strictly smaller than B <= (Q-1)/8 +* and 1 otherwise. +**************************************************/ +int polyvecl_chknorm(const polyvecl *v, int32_t bound) { + unsigned int i; + + for(i = 0; i < L; ++i) + if(poly_chknorm(&v->vec[i], bound)) + return 1; + + return 0; +} + +/**************************************************************/ +/************ Vectors of polynomials of length K **************/ +/**************************************************************/ + +void polyveck_uniform_eta(polyveck *v, const uint8_t seed[CRHBYTES], uint16_t nonce) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_uniform_eta(&v->vec[i], seed, nonce++); +} + +/************************************************* +* Name: polyveck_reduce +* +* Description: Reduce coefficients of polynomials in vector of length K +* to representatives in [-6283009,6283007]. +* +* Arguments: - polyveck *v: pointer to input/output vector +**************************************************/ +void polyveck_reduce(polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_reduce(&v->vec[i]); +} + +/************************************************* +* Name: polyveck_caddq +* +* Description: For all coefficients of polynomials in vector of length K +* add Q if coefficient is negative. +* +* Arguments: - polyveck *v: pointer to input/output vector +**************************************************/ +void polyveck_caddq(polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_caddq(&v->vec[i]); +} + +/************************************************* +* Name: polyveck_add +* +* Description: Add vectors of polynomials of length K. +* No modular reduction is performed. +* +* Arguments: - polyveck *w: pointer to output vector +* - const polyveck *u: pointer to first summand +* - const polyveck *v: pointer to second summand +**************************************************/ +void polyveck_add(polyveck *w, const polyveck *u, const polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_add(&w->vec[i], &u->vec[i], &v->vec[i]); +} + +/************************************************* +* Name: polyveck_sub +* +* Description: Subtract vectors of polynomials of length K. +* No modular reduction is performed. +* +* Arguments: - polyveck *w: pointer to output vector +* - const polyveck *u: pointer to first input vector +* - const polyveck *v: pointer to second input vector to be +* subtracted from first input vector +**************************************************/ +void polyveck_sub(polyveck *w, const polyveck *u, const polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_sub(&w->vec[i], &u->vec[i], &v->vec[i]); +} + +/************************************************* +* Name: polyveck_shiftl +* +* Description: Multiply vector of polynomials of Length K by 2^D without modular +* reduction. Assumes input coefficients to be less than 2^{31-D}. +* +* Arguments: - polyveck *v: pointer to input/output vector +**************************************************/ +void polyveck_shiftl(polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_shiftl(&v->vec[i]); +} + +/************************************************* +* Name: polyveck_ntt +* +* Description: Forward NTT of all polynomials in vector of length K. Output +* coefficients can be up to 16*Q larger than input coefficients. +* +* Arguments: - polyveck *v: pointer to input/output vector +**************************************************/ +void polyveck_ntt(polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_ntt(&v->vec[i]); +} + +/************************************************* +* Name: polyveck_invntt_tomont +* +* Description: Inverse NTT and multiplication by 2^{32} of polynomials +* in vector of length K. Input coefficients need to be less +* than 2*Q. +* +* Arguments: - polyveck *v: pointer to input/output vector +**************************************************/ +void polyveck_invntt_tomont(polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_invntt_tomont(&v->vec[i]); +} + +void polyveck_pointwise_poly_montgomery(polyveck *r, const poly *a, const polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_pointwise_montgomery(&r->vec[i], a, &v->vec[i]); +} + + +/************************************************* +* Name: polyveck_chknorm +* +* Description: Check infinity norm of polynomials in vector of length K. +* Assumes input polyveck to be reduced by polyveck_reduce(). +* +* Arguments: - const polyveck *v: pointer to vector +* - int32_t B: norm bound +* +* Returns 0 if norm of all polynomials are strictly smaller than B <= (Q-1)/8 +* and 1 otherwise. +**************************************************/ +int polyveck_chknorm(const polyveck *v, int32_t bound) { + unsigned int i; + + for(i = 0; i < K; ++i) + if(poly_chknorm(&v->vec[i], bound)) + return 1; + + return 0; +} + +/************************************************* +* Name: polyveck_power2round +* +* Description: For all coefficients a of polynomials in vector of length K, +* compute a0, a1 such that a mod^+ Q = a1*2^D + a0 +* with -2^{D-1} < a0 <= 2^{D-1}. Assumes coefficients to be +* standard representatives. +* +* Arguments: - polyveck *v1: pointer to output vector of polynomials with +* coefficients a1 +* - polyveck *v0: pointer to output vector of polynomials with +* coefficients a0 +* - const polyveck *v: pointer to input vector +**************************************************/ +void polyveck_power2round(polyveck *v1, polyveck *v0, const polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_power2round(&v1->vec[i], &v0->vec[i], &v->vec[i]); +} + +/************************************************* +* Name: polyveck_decompose +* +* Description: For all coefficients a of polynomials in vector of length K, +* compute high and low bits a0, a1 such a mod^+ Q = a1*ALPHA + a0 +* with -ALPHA/2 < a0 <= ALPHA/2 except a1 = (Q-1)/ALPHA where we +* set a1 = 0 and -ALPHA/2 <= a0 = a mod Q - Q < 0. +* Assumes coefficients to be standard representatives. +* +* Arguments: - polyveck *v1: pointer to output vector of polynomials with +* coefficients a1 +* - polyveck *v0: pointer to output vector of polynomials with +* coefficients a0 +* - const polyveck *v: pointer to input vector +**************************************************/ +void polyveck_decompose(polyveck *v1, polyveck *v0, const polyveck *v) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_decompose(&v1->vec[i], &v0->vec[i], &v->vec[i]); +} + +/************************************************* +* Name: polyveck_make_hint +* +* Description: Compute hint vector. +* +* Arguments: - polyveck *h: pointer to output vector +* - const polyveck *v0: pointer to low part of input vector +* - const polyveck *v1: pointer to high part of input vector +* +* Returns number of 1 bits. +**************************************************/ +unsigned int polyveck_make_hint(polyveck *h, + const polyveck *v0, + const polyveck *v1) +{ + unsigned int i, s = 0; + + for(i = 0; i < K; ++i) + s += poly_make_hint(&h->vec[i], &v0->vec[i], &v1->vec[i]); + + return s; +} + +/************************************************* +* Name: polyveck_use_hint +* +* Description: Use hint vector to correct the high bits of input vector. +* +* Arguments: - polyveck *w: pointer to output vector of polynomials with +* corrected high bits +* - const polyveck *u: pointer to input vector +* - const polyveck *h: pointer to input hint vector +**************************************************/ +void polyveck_use_hint(polyveck *w, const polyveck *u, const polyveck *h) { + unsigned int i; + + for(i = 0; i < K; ++i) + poly_use_hint(&w->vec[i], &u->vec[i], &h->vec[i]); +} + +void polyveck_pack_w1(uint8_t r[K*POLYW1_PACKEDBYTES], const polyveck *w1) { + unsigned int i; + + for(i = 0; i < K; ++i) + polyw1_pack(&r[i*POLYW1_PACKEDBYTES], &w1->vec[i]); +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/polyvec.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/polyvec.h new file mode 100644 index 0000000000000000000000000000000000000000..615ac52990add89062af3ee231c8dde0a547a1f6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/polyvec.h @@ -0,0 +1,93 @@ +#ifndef POLYVEC_H +#define POLYVEC_H + +#include +#include "params.h" +#include "poly.h" + +/* Vectors of polynomials of length L */ +typedef struct { + poly vec[L]; +} polyvecl; + +#define polyvecl_uniform_eta DILITHIUM_NAMESPACE(polyvecl_uniform_eta) +void polyvecl_uniform_eta(polyvecl *v, const uint8_t seed[CRHBYTES], uint16_t nonce); + +#define polyvecl_uniform_gamma1 DILITHIUM_NAMESPACE(polyvecl_uniform_gamma1) +void polyvecl_uniform_gamma1(polyvecl *v, const uint8_t seed[CRHBYTES], uint16_t nonce); + +#define polyvecl_reduce DILITHIUM_NAMESPACE(polyvecl_reduce) +void polyvecl_reduce(polyvecl *v); + +#define polyvecl_add DILITHIUM_NAMESPACE(polyvecl_add) +void polyvecl_add(polyvecl *w, const polyvecl *u, const polyvecl *v); + +#define polyvecl_ntt DILITHIUM_NAMESPACE(polyvecl_ntt) +void polyvecl_ntt(polyvecl *v); +#define polyvecl_invntt_tomont DILITHIUM_NAMESPACE(polyvecl_invntt_tomont) +void polyvecl_invntt_tomont(polyvecl *v); +#define polyvecl_pointwise_poly_montgomery DILITHIUM_NAMESPACE(polyvecl_pointwise_poly_montgomery) +void polyvecl_pointwise_poly_montgomery(polyvecl *r, const poly *a, const polyvecl *v); +#define polyvecl_pointwise_acc_montgomery \ + DILITHIUM_NAMESPACE(polyvecl_pointwise_acc_montgomery) +void polyvecl_pointwise_acc_montgomery(poly *w, + const polyvecl *u, + const polyvecl *v); + + +#define polyvecl_chknorm DILITHIUM_NAMESPACE(polyvecl_chknorm) +int polyvecl_chknorm(const polyvecl *v, int32_t B); + + + +/* Vectors of polynomials of length K */ +typedef struct { + poly vec[K]; +} polyveck; + +#define polyveck_uniform_eta DILITHIUM_NAMESPACE(polyveck_uniform_eta) +void polyveck_uniform_eta(polyveck *v, const uint8_t seed[CRHBYTES], uint16_t nonce); + +#define polyveck_reduce DILITHIUM_NAMESPACE(polyveck_reduce) +void polyveck_reduce(polyveck *v); +#define polyveck_caddq DILITHIUM_NAMESPACE(polyveck_caddq) +void polyveck_caddq(polyveck *v); + +#define polyveck_add DILITHIUM_NAMESPACE(polyveck_add) +void polyveck_add(polyveck *w, const polyveck *u, const polyveck *v); +#define polyveck_sub DILITHIUM_NAMESPACE(polyveck_sub) +void polyveck_sub(polyveck *w, const polyveck *u, const polyveck *v); +#define polyveck_shiftl DILITHIUM_NAMESPACE(polyveck_shiftl) +void polyveck_shiftl(polyveck *v); + +#define polyveck_ntt DILITHIUM_NAMESPACE(polyveck_ntt) +void polyveck_ntt(polyveck *v); +#define polyveck_invntt_tomont DILITHIUM_NAMESPACE(polyveck_invntt_tomont) +void polyveck_invntt_tomont(polyveck *v); +#define polyveck_pointwise_poly_montgomery DILITHIUM_NAMESPACE(polyveck_pointwise_poly_montgomery) +void polyveck_pointwise_poly_montgomery(polyveck *r, const poly *a, const polyveck *v); + +#define polyveck_chknorm DILITHIUM_NAMESPACE(polyveck_chknorm) +int polyveck_chknorm(const polyveck *v, int32_t B); + +#define polyveck_power2round DILITHIUM_NAMESPACE(polyveck_power2round) +void polyveck_power2round(polyveck *v1, polyveck *v0, const polyveck *v); +#define polyveck_decompose DILITHIUM_NAMESPACE(polyveck_decompose) +void polyveck_decompose(polyveck *v1, polyveck *v0, const polyveck *v); +#define polyveck_make_hint DILITHIUM_NAMESPACE(polyveck_make_hint) +unsigned int polyveck_make_hint(polyveck *h, + const polyveck *v0, + const polyveck *v1); +#define polyveck_use_hint DILITHIUM_NAMESPACE(polyveck_use_hint) +void polyveck_use_hint(polyveck *w, const polyveck *v, const polyveck *h); + +#define polyveck_pack_w1 DILITHIUM_NAMESPACE(polyveck_pack_w1) +void polyveck_pack_w1(uint8_t r[K*POLYW1_PACKEDBYTES], const polyveck *w1); + +#define polyvec_matrix_expand DILITHIUM_NAMESPACE(polyvec_matrix_expand) +void polyvec_matrix_expand(polyvecl mat[K], const uint8_t rho[SEEDBYTES]); + +#define polyvec_matrix_pointwise_montgomery DILITHIUM_NAMESPACE(polyvec_matrix_pointwise_montgomery) +void polyvec_matrix_pointwise_montgomery(polyveck *t, const polyvecl mat[K], const polyvecl *v); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/precomp.gp b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/precomp.gp new file mode 100644 index 0000000000000000000000000000000000000000..74dbdf836dee2884fe13e66f39b75818ea569a7f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/precomp.gp @@ -0,0 +1,12 @@ +precomp() = { + brv = [128, 64, 192, 32, 160, 96, 224, 16, 144, 80, 208, 48, 176, 112, 240, 8, 136, 72, 200, 40, 168, 104, 232, 24, 152, 88, 216, 56, 184, 120, 248, 4, 132, 68, 196, 36, 164, 100, 228, 20, 148, 84, 212, 52, 180, 116, 244, 12, 140, 76, 204, 44, 172, 108, 236, 28, 156, 92, 220, 60, 188, 124, 252, 2, 130, 66, 194, 34, 162, 98, 226, 18, 146, 82, 210, 50, 178, 114, 242, 10, 138, 74, 202, 42, 170, 106, 234, 26, 154, 90, 218, 58, 186, 122, 250, 6, 134, 70, 198, 38, 166, 102, 230, 22, 150, 86, 214, 54, 182, 118, 246, 14, 142, 78, 206, 46, 174, 110, 238, 30, 158, 94, 222, 62, 190, 126, 254, 1, 129, 65, 193, 33, 161, 97, 225, 17, 145, 81, 209, 49, 177, 113, 241, 9, 137, 73, 201, 41, 169, 105, 233, 25, 153, 89, 217, 57, 185, 121, 249, 5, 133, 69, 197, 37, 165, 101, 229, 21, 149, 85, 213, 53, 181, 117, 245, 13, 141, 77, 205, 45, 173, 109, 237, 29, 157, 93, 221, 61, 189, 125, 253, 3, 131, 67, 195, 35, 163, 99, 227, 19, 147, 83, 211, 51, 179, 115, 243, 11, 139, 75, 203, 43, 171, 107, 235, 27, 155, 91, 219, 59, 187, 123, 251, 7, 135, 71, 199, 39, 167, 103, 231, 23, 151, 87, 215, 55, 183, 119, 247, 15, 143, 79, 207, 47, 175, 111, 239, 31, 159, 95, 223, 63, 191, 127, 255]; + + q = 2^23 - 2^13 + 1; + qinv = Mod(1/q,2^32); + mont = Mod(2^32,q); + + z = 0; + for(i = 1, q-1, z = Mod(i,q); if(znorder(z) == 512, break)); + zetas = vector(255, i, centerlift(mont * z^(brv[i]))); + return(zetas); +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/public_key.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/public_key.hex new file mode 100644 index 0000000000000000000000000000000000000000..2c87571361c4bec7ae2be79a25bc39e7798fd34e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/public_key.hex @@ -0,0 +1 @@ +6d669b7275c97c1cdbaeb4ca9369c086afe01291cf241992b5e5e3efec9adeb14e01e30691daaf1c83f8570db58e0a22720e5ed831560af28d513626365a29ce7ee0d7246735f03f7530378e8c6babec312f2795f7fdab9b3f21e149490a427c266ee178db146851ea345f509c669e363baa4601341dfdb5a126a87e5410bb292319a26d32ad1275b79bf5c1c5ee72dad3ee30e3954af890de529678b165accf8006899993fcdce89edf3d3b1977f02b99dd033ba0e8a6f69196a538b1c85fb1fb77aaf6752c42864162706c832a6feba6c07fa9ca68ecfa3a38539b45dd4ef779ebbf5e38a0f04a4608eec6db26cc311dc23791ed6e4e248bb5027374a1cef4f8caeac350d502dc2b04f3cc54b51cef3948767dda18832a7bf5efcf2cc63b3126284034090b0ea21e344b93f75752ca91c68ab7084732212df48c326e6f2154636e306311f4f93421ed74e12a3c26c47cb56ed29fa9fa5c1fccf1cc40ce2c1d1a774766e2e97ea02094ce35f2c5a56073beb00d4229bb7077ed641e6864874bb4dcebc5c9992ce0682b3a83f4cab47c3a59d5309d7daa7747d0cdb47a667e613d33c42aef7efb29b18d924a265eaaa82dd83eaaa2a37d43f46842d2eaf9ea3d2ef009d5d027e0ba3a250438537c9be017356f2bb6e45472e6b298a66cf71ccf39c4a46845e3b09a60655f62c22630f17fa008b4809d8eb15ffdf1569b72a3c4e0ce196cb3a60bb9539851e65e21d5a069d14b95986063586a80ee75999f723a04eb31d3672068f8c79964abda0975ed558e3e44f6ad4961062d01f29108f08b0d8e87beb1b1ad6a866b7292c5a211dc6905c70cae38b8c7079e453145496b13129428d1a5d2ce0eef8295e7d47406900c3f662fb0baa1cdb2646a7e3b2e9aee4180cb89a2bc2dc6079b209d0bae6bd9fdd0d223d220ed91df2929b9c2fff003594263b41ac0aceeb85d509aa1094ca881b3669694edc7c7dfd85e44fe69787bc44144df053821b1cc6565c1d9336bff140292a8ee0057c2eb3d49f78ce7e196cb633bf10786f58d75524213b03b0d2b3a1951792b6f8e192da37cfbc6b69296b73cf8f28e04676db965faaf7bb36a05aa3ee97cb94367c492dc059c7089ac1aeccdc08a83faa3bedf476c3e9f5a8036ce659404300d3bbe17809f3c363a06fbd68083ac084910151f63fa3e445c29eec37043942977e4f94c82817951b4caf28a4fdb578f6f3fc2968e763f0707ede410770b169632a1aa8fd4e413355aa8e3a7b20eab8e7f4645564c2768cf1685b273b4ae39a921ff93193ad06a99451f6035558cdfd6db8a40a1d3b4668e568f90f1b00137c30b2fb77e89686116ff6d3b738ae69e7321f98ee5d4e3011f00175d623bb3958d82f50e9e900b5256a86eac5a1c5096fd0893d8b4b62dd76acee390ced46413e8254eae39a73b5ac2c50c56fea576ef29b86cc15ef9df4f508bb0734887ca998a806475720351ceefbfd80f45e8d1d437f05585f49d812b2f05f178c524a73da319c7e67e5f1f679b513ebc25be2b198bc4e9e3c9c13aa0d091a784317a14e5affa2c877e8284bffbac07f518921e9a6576cd5a951227c6c6fd5dd76a1b384c8e4c88fc31651f4df5868f26637600dd86a7ba32e72decea2a31f1431a6bf7fc16bb0ef5fb141c4e4c587aa602c28fd8eba0de52ac602e2a647024655c1ca3a5e66bfdd791956699efc7dde7bfc1436d2c30eb6156c252d47976ffb83bd711f4a4c2e5766110fa187584841a5cb04168ffe4cf79870d1e32f5631adff9c57021e3ff2748602ab47d95e847881df859fe2a03df82e10c7d43ca21cfc32fc80521168c140ec728d6bce1e8571a3ab413ae9a75c447cecb48acac480a3e5f5aa08142a9b4274e92397ad3c3062dc69e3d9413e9e8e36d83e313de41fabf6c3d293ea8d5107170ad2b65925fd393a8d089c907e23c884934b9f462396c8a310ce6fb8f863a1d3e42fe50f525f7ebe2a18ca5d2c207e2d7fab5172f94a61524cecdc683662beef1fedb577e7ebc162afe2fb2ba3d18d249648cce33cf7dd157247150c3ae787dc67f18cc91cd51c4671ca713225433f91cf9e8302b4636c4016cbfd55c6da913cf47ca01d5f595cf0fdb50e02c727a26962d99fc5c080e665a21e4361aa5566ad2b0f8945844f51182cf3dffb2323058cf3f498a19153e8ceb3ae328293c71a7e3951607c923f9b754768937c6546bce816694c38d187192e879706e93cf434f1c0742cc9ded3a96c51437ae1cbe36d75d6425a23cdf5d92dad35cf6e4dcaba812e8020745f6bc4c3ce9835f5a071e8c6588ad18587514a40fa916ff013dda3cfaea17e3141d5e6b4581ff9e1bfc296c1b25336d8229815d2301c51ab2315397f5f11b99e0824577c374d1bf6200b21c25127575abed09f80bb8bb1880ed201287984999ab0d922574c4d9ec50ef45eb53bbd952b606d37a5fff34875d301589157e8fdb861f99e937514032847202dab8bc31c33b7693738b621eb12c128998212e6ade07ddf0d9135ea91150f0d0b95ccc40b48a0e8936508c6f6fd200ab5cd8763027c3913d6df66cf8d7b7ab727f6362b580075e1ab7354e6d304a21d68fd1f2714a6d23de3cf87d729f83db30d5345fbf21ce7f2e94fd68f521d646dd38601320dde2bc030a89b7aa11d704daa1bb6b5ce05d44ee7dbd95ef35ccb330589ccc9e58917ef933c50f1db79a52ab1d84397a4c285849ba6ffa79005348db10c343a76a2297690cf75f4ab84cc17934cc24cd7b5da8ee093fb1b42d8ccc0ea58c72e33c4c32a805fd3cc961f0917cd0def13432b6c3bb706c133ec1522d612aba77b030957edb7b9bbf7e3931f29a906d80f263d3f61bb1ec8e4bece2def44021e9ad1214e6b88b13bba037d9fd2ccfb8eae4f6f907405848a5cfe19042984b9832b633cabec9020194d8b005511a708fd5d4cfc2201d7109a2247f9137ca20b5a6e2d74668fe3d8b90e719418e0a80914487bbffffefb177895aac8409acae615edf3773327a1a7f26697ff88cf75e52566d7d311fc4fc95a377b4f287609dbfd9c21116fc78898a02cb1fb48cc2903b1e32305e709f14e556681027c6c37cc2cd71e3087d99fab04803c1df6361040d70dafc206600f3318806b9b45ec08d21d217332a06b41247183b0d4b6ed8171bfef0dfda03986eac1e4972f7e848a5c024a2308883a4d7bfc1a3c8be1f8769bc1a49e974be208770821dd10c22c2d3c5418b63d8131fd8834bc0a58acd7334728c100e6ceca0b4bc29c51edad1f671e447568661225b82e8f8c31bba5885b9ed07743d110f0bea5062afb723fb93ff5c1729f5cd030fc633ab6558ae681bcff776cc10ba33599e7302198620d287ef478ecba556de05358f003d111ee556c3489172c90c0dace1850bad2782db4cd3841b930d1c12454f39e98b39904a83a9968f8e56d4515fdf07ff51bb9a456d442f69721e0142e1607034c17d97a0ee509e49d64809e5c6ce25df0f5dd646a559ae8e3fc20cf56718d10cd3713e5a901cf6dba9bdc3840e8a2eb600e22b19f237c691b2d1158af20b28fa36f10397d68f65e2368f99c6aba954caaf34dfd7299e8eb563229f79ae0d1352d4ff73a4c0791d7ed071e4a0c1ada3fd63041d03c8edc26efae03b2e2707 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/randombytes.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/randombytes.c new file mode 100644 index 0000000000000000000000000000000000000000..7f4b857158941708e1760c85419180b7e0b8f9d1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/randombytes.c @@ -0,0 +1,80 @@ +#include +#include +#include +#include "randombytes.h" + +#ifdef _WIN32 +#include +#include +#else +#include +#include +#ifdef __linux__ +#define _GNU_SOURCE +#include +#include +#else +#include +#endif +#endif + +#ifdef _WIN32 +void randombytes(uint8_t *out, size_t outlen) { + HCRYPTPROV ctx; + size_t len; + + if(!CryptAcquireContext(&ctx, NULL, NULL, PROV_RSA_FULL, CRYPT_VERIFYCONTEXT)) + abort(); + + while(outlen > 0) { + len = (outlen > 1048576) ? 1048576 : outlen; + if(!CryptGenRandom(ctx, len, (BYTE *)out)) + abort(); + + out += len; + outlen -= len; + } + + if(!CryptReleaseContext(ctx, 0)) + abort(); +} +#elif defined(__linux__) && defined(SYS_getrandom) +void randombytes(uint8_t *out, size_t outlen) { + ssize_t ret; + + while(outlen > 0) { + ret = syscall(SYS_getrandom, out, outlen, 0); + if(ret == -1 && errno == EINTR) + continue; + else if(ret == -1) + abort(); + + out += ret; + outlen -= ret; + } +} +#else +void randombytes(uint8_t *out, size_t outlen) { + static int fd = -1; + ssize_t ret; + + while(fd == -1) { + fd = open("/dev/urandom", O_RDONLY); + if(fd == -1 && errno == EINTR) + continue; + else if(fd == -1) + abort(); + } + + while(outlen > 0) { + ret = read(fd, out, outlen); + if(ret == -1 && errno == EINTR) + continue; + else if(ret == -1) + abort(); + + out += ret; + outlen -= ret; + } +} +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/randombytes.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/randombytes.h new file mode 100644 index 0000000000000000000000000000000000000000..619b7f9a93231573f421750bf855cdbecf64ec7e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/randombytes.h @@ -0,0 +1,9 @@ +#ifndef RANDOMBYTES_H +#define RANDOMBYTES_H + +#include +#include + +void randombytes(uint8_t *out, size_t outlen); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/reduce.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/reduce.c new file mode 100644 index 0000000000000000000000000000000000000000..75feff8bc5e35bce6feaa8c6eb84a04195773d99 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/reduce.c @@ -0,0 +1,69 @@ +#include +#include "params.h" +#include "reduce.h" + +/************************************************* +* Name: montgomery_reduce +* +* Description: For finite field element a with -2^{31}Q <= a <= Q*2^31, +* compute r \equiv a*2^{-32} (mod Q) such that -Q < r < Q. +* +* Arguments: - int64_t: finite field element a +* +* Returns r. +**************************************************/ +int32_t montgomery_reduce(int64_t a) { + int32_t t; + + t = (int64_t)(int32_t)a*QINV; + t = (a - (int64_t)t*Q) >> 32; + return t; +} + +/************************************************* +* Name: reduce32 +* +* Description: For finite field element a with a <= 2^{31} - 2^{22} - 1, +* compute r \equiv a (mod Q) such that -6283009 <= r <= 6283007. +* +* Arguments: - int32_t: finite field element a +* +* Returns r. +**************************************************/ +int32_t reduce32(int32_t a) { + int32_t t; + + t = (a + (1 << 22)) >> 23; + t = a - t*Q; + return t; +} + +/************************************************* +* Name: caddq +* +* Description: Add Q if input coefficient is negative. +* +* Arguments: - int32_t: finite field element a +* +* Returns r. +**************************************************/ +int32_t caddq(int32_t a) { + a += (a >> 31) & Q; + return a; +} + +/************************************************* +* Name: freeze +* +* Description: For finite field element a, compute standard +* representative r = a mod^+ Q. +* +* Arguments: - int32_t: finite field element a +* +* Returns r. +**************************************************/ +int32_t freeze(int32_t a) { + a = reduce32(a); + a = caddq(a); + return a; +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/reduce.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/reduce.h new file mode 100644 index 0000000000000000000000000000000000000000..26d9b4ee2ef786020bf0145770d8aa81b9eba1b8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/reduce.h @@ -0,0 +1,22 @@ +#ifndef REDUCE_H +#define REDUCE_H + +#include +#include "params.h" + +#define MONT -4186625 // 2^32 % Q +#define QINV 58728449 // q^(-1) mod 2^32 + +#define montgomery_reduce DILITHIUM_NAMESPACE(montgomery_reduce) +int32_t montgomery_reduce(int64_t a); + +#define reduce32 DILITHIUM_NAMESPACE(reduce32) +int32_t reduce32(int32_t a); + +#define caddq DILITHIUM_NAMESPACE(caddq) +int32_t caddq(int32_t a); + +#define freeze DILITHIUM_NAMESPACE(freeze) +int32_t freeze(int32_t a); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rng.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rng.c new file mode 100644 index 0000000000000000000000000000000000000000..43763dd16792c90b7210f2c82c66f13f785a0452 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rng.c @@ -0,0 +1,222 @@ +// +// rng.c +// +// Created by Bassham, Lawrence E (Fed) on 8/29/17. +// Copyright © 2017 Bassham, Lawrence E (Fed). All rights reserved. +// + +#include +#include "rng.h" +#include +#include +#include + +AES256_CTR_DRBG_struct DRBG_ctx; + +void AES256_ECB(unsigned char *key, unsigned char *ctr, unsigned char *buffer); + +/* + seedexpander_init() + ctx - stores the current state of an instance of the seed expander + seed - a 32 byte random value + diversifier - an 8 byte diversifier + maxlen - maximum number of bytes (less than 2**32) generated under this seed and diversifier + */ +int +seedexpander_init(AES_XOF_struct *ctx, + unsigned char *seed, + unsigned char *diversifier, + unsigned long maxlen) +{ + if ( maxlen >= 0x100000000 ) + return RNG_BAD_MAXLEN; + + ctx->length_remaining = maxlen; + + memcpy(ctx->key, seed, 32); + + memcpy(ctx->ctr, diversifier, 8); + ctx->ctr[11] = maxlen % 256; + maxlen >>= 8; + ctx->ctr[10] = maxlen % 256; + maxlen >>= 8; + ctx->ctr[9] = maxlen % 256; + maxlen >>= 8; + ctx->ctr[8] = maxlen % 256; + memset(ctx->ctr+12, 0x00, 4); + + ctx->buffer_pos = 16; + memset(ctx->buffer, 0x00, 16); + + return RNG_SUCCESS; +} + +/* + seedexpander() + ctx - stores the current state of an instance of the seed expander + x - returns the XOF data + xlen - number of bytes to return + */ +int +seedexpander(AES_XOF_struct *ctx, unsigned char *x, unsigned long xlen) +{ + unsigned long offset; + + if ( x == NULL ) + return RNG_BAD_OUTBUF; + if ( xlen >= ctx->length_remaining ) + return RNG_BAD_REQ_LEN; + + ctx->length_remaining -= xlen; + + offset = 0; + while ( xlen > 0 ) { + if ( xlen <= (16-ctx->buffer_pos) ) { // buffer has what we need + memcpy(x+offset, ctx->buffer+ctx->buffer_pos, xlen); + ctx->buffer_pos += xlen; + + return RNG_SUCCESS; + } + + // take what's in the buffer + memcpy(x+offset, ctx->buffer+ctx->buffer_pos, 16-ctx->buffer_pos); + xlen -= 16-ctx->buffer_pos; + offset += 16-ctx->buffer_pos; + + AES256_ECB(ctx->key, ctx->ctr, ctx->buffer); + ctx->buffer_pos = 0; + + //increment the counter + for (int i=15; i>=12; i--) { + if ( ctx->ctr[i] == 0xff ) + ctx->ctr[i] = 0x00; + else { + ctx->ctr[i]++; + break; + } + } + + } + + return RNG_SUCCESS; +} + + +void handleErrors(void) +{ + ERR_print_errors_fp(stderr); + abort(); +} + +// Use whatever AES implementation you have. This uses AES from openSSL library +// key - 256-bit AES key +// ctr - a 128-bit plaintext value +// buffer - a 128-bit ciphertext value +void +AES256_ECB(unsigned char *key, unsigned char *ctr, unsigned char *buffer) +{ + EVP_CIPHER_CTX *ctx; + + int len; + + int ciphertext_len; + + /* Create and initialise the context */ + if(!(ctx = EVP_CIPHER_CTX_new())) handleErrors(); + + if(1 != EVP_EncryptInit_ex(ctx, EVP_aes_256_ecb(), NULL, key, NULL)) + handleErrors(); + + if(1 != EVP_EncryptUpdate(ctx, buffer, &len, ctr, 16)) + handleErrors(); + ciphertext_len = len; + + /* Clean up */ + EVP_CIPHER_CTX_free(ctx); +} + +void +randombytes_init(unsigned char *entropy_input, + unsigned char *personalization_string, + int security_strength) +{ + unsigned char seed_material[48]; + + memcpy(seed_material, entropy_input, 48); + if (personalization_string) + for (int i=0; i<48; i++) + seed_material[i] ^= personalization_string[i]; + memset(DRBG_ctx.Key, 0x00, 32); + memset(DRBG_ctx.V, 0x00, 16); + AES256_CTR_DRBG_Update(seed_material, DRBG_ctx.Key, DRBG_ctx.V); + DRBG_ctx.reseed_counter = 1; +} + +int +randombytes(unsigned char *x, unsigned long long xlen) +{ + unsigned char block[16]; + int i = 0; + + while ( xlen > 0 ) { + //increment V + for (int j=15; j>=0; j--) { + if ( DRBG_ctx.V[j] == 0xff ) + DRBG_ctx.V[j] = 0x00; + else { + DRBG_ctx.V[j]++; + break; + } + } + AES256_ECB(DRBG_ctx.Key, DRBG_ctx.V, block); + if ( xlen > 15 ) { + memcpy(x+i, block, 16); + i += 16; + xlen -= 16; + } + else { + memcpy(x+i, block, xlen); + xlen = 0; + } + } + AES256_CTR_DRBG_Update(NULL, DRBG_ctx.Key, DRBG_ctx.V); + DRBG_ctx.reseed_counter++; + + return RNG_SUCCESS; +} + +void +AES256_CTR_DRBG_Update(unsigned char *provided_data, + unsigned char *Key, + unsigned char *V) +{ + unsigned char temp[48]; + + for (int i=0; i<3; i++) { + //increment V + for (int j=15; j>=0; j--) { + if ( V[j] == 0xff ) + V[j] = 0x00; + else { + V[j]++; + break; + } + } + + AES256_ECB(Key, V, temp+16*i); + } + if ( provided_data != NULL ) + for (int i=0; i<48; i++) + temp[i] ^= provided_data[i]; + memcpy(Key, temp, 32); + memcpy(V, temp+32, 16); +} + + + + + + + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rng.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rng.h new file mode 100644 index 0000000000000000000000000000000000000000..577e2639d6e5a40e7172f8960711dc2ba96b009a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rng.h @@ -0,0 +1,55 @@ +// +// rng.h +// +// Created by Bassham, Lawrence E (Fed) on 8/29/17. +// Copyright © 2017 Bassham, Lawrence E (Fed). All rights reserved. +// + +#ifndef rng_h +#define rng_h + +#include + +#define RNG_SUCCESS 0 +#define RNG_BAD_MAXLEN -1 +#define RNG_BAD_OUTBUF -2 +#define RNG_BAD_REQ_LEN -3 + +typedef struct { + unsigned char buffer[16]; + int buffer_pos; + unsigned long length_remaining; + unsigned char key[32]; + unsigned char ctr[16]; +} AES_XOF_struct; + +typedef struct { + unsigned char Key[32]; + unsigned char V[16]; + int reseed_counter; +} AES256_CTR_DRBG_struct; + + +void +AES256_CTR_DRBG_Update(unsigned char *provided_data, + unsigned char *Key, + unsigned char *V); + +int +seedexpander_init(AES_XOF_struct *ctx, + unsigned char *seed, + unsigned char *diversifier, + unsigned long maxlen); + +int +seedexpander(AES_XOF_struct *ctx, unsigned char *x, unsigned long xlen); + +void +randombytes_init(unsigned char *entropy_input, + unsigned char *personalization_string, + int security_strength); + +int +randombytes(unsigned char *x, unsigned long long xlen); + +#endif /* rng_h */ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rounding.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rounding.c new file mode 100644 index 0000000000000000000000000000000000000000..889f0a296b52d3f642591aabe1f88837b316ded3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rounding.c @@ -0,0 +1,102 @@ +#include +#include "params.h" +#include "rounding.h" + +/************************************************* +* Name: power2round +* +* Description: For finite field element a, compute a0, a1 such that +* a mod^+ Q = a1*2^D + a0 with -2^{D-1} < a0 <= 2^{D-1}. +* Assumes a to be standard representative. +* +* Arguments: - int32_t a: input element +* - int32_t *a0: pointer to output element a0 +* +* Returns a1. +**************************************************/ +int32_t power2round(int32_t *a0, int32_t a) { + int32_t a1; + + a1 = (a + (1 << (D-1)) - 1) >> D; + *a0 = a - (a1 << D); + return a1; +} + +/************************************************* +* Name: decompose +* +* Description: For finite field element a, compute high and low bits a0, a1 such +* that a mod^+ Q = a1*ALPHA + a0 with -ALPHA/2 < a0 <= ALPHA/2 except +* if a1 = (Q-1)/ALPHA where we set a1 = 0 and +* -ALPHA/2 <= a0 = a mod^+ Q - Q < 0. Assumes a to be standard +* representative. +* +* Arguments: - int32_t a: input element +* - int32_t *a0: pointer to output element a0 +* +* Returns a1. +**************************************************/ +int32_t decompose(int32_t *a0, int32_t a) { + int32_t a1; + + a1 = (a + 127) >> 7; +#if GAMMA2 == (Q-1)/32 + a1 = (a1*1025 + (1 << 21)) >> 22; + a1 &= 15; +#elif GAMMA2 == (Q-1)/88 + a1 = (a1*11275 + (1 << 23)) >> 24; + a1 ^= ((43 - a1) >> 31) & a1; +#endif + + *a0 = a - a1*2*GAMMA2; + *a0 -= (((Q-1)/2 - *a0) >> 31) & Q; + return a1; +} + +/************************************************* +* Name: make_hint +* +* Description: Compute hint bit indicating whether the low bits of the +* input element overflow into the high bits. +* +* Arguments: - int32_t a0: low bits of input element +* - int32_t a1: high bits of input element +* +* Returns 1 if overflow. +**************************************************/ +unsigned int make_hint(int32_t a0, int32_t a1) { + if(a0 > GAMMA2 || a0 < -GAMMA2 || (a0 == -GAMMA2 && a1 != 0)) + return 1; + + return 0; +} + +/************************************************* +* Name: use_hint +* +* Description: Correct high bits according to hint. +* +* Arguments: - int32_t a: input element +* - unsigned int hint: hint bit +* +* Returns corrected high bits. +**************************************************/ +int32_t use_hint(int32_t a, unsigned int hint) { + int32_t a0, a1; + + a1 = decompose(&a0, a); + if(hint == 0) + return a1; + +#if GAMMA2 == (Q-1)/32 + if(a0 > 0) + return (a1 + 1) & 15; + else + return (a1 - 1) & 15; +#elif GAMMA2 == (Q-1)/88 + if(a0 > 0) + return (a1 == 43) ? 0 : a1 + 1; + else + return (a1 == 0) ? 43 : a1 - 1; +#endif +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rounding.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rounding.h new file mode 100644 index 0000000000000000000000000000000000000000..b72e8e8d661b6839a3cbc145be5348e7177b9d3c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/rounding.h @@ -0,0 +1,19 @@ +#ifndef ROUNDING_H +#define ROUNDING_H + +#include +#include "params.h" + +#define power2round DILITHIUM_NAMESPACE(power2round) +int32_t power2round(int32_t *a0, int32_t a); + +#define decompose DILITHIUM_NAMESPACE(decompose) +int32_t decompose(int32_t *a0, int32_t a); + +#define make_hint DILITHIUM_NAMESPACE(make_hint) +unsigned int make_hint(int32_t a0, int32_t a1); + +#define use_hint DILITHIUM_NAMESPACE(use_hint) +int32_t use_hint(int32_t a, unsigned int hint); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/secret_key.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/secret_key.hex new file mode 100644 index 0000000000000000000000000000000000000000..871fba63d2515a3c48ac1b63a2e3a75058c59d0d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/secret_key.hex @@ -0,0 +1 @@ +6d669b7275c97c1cdbaeb4ca9369c086afe01291cf241992b5e5e3efec9adeb1822063a2b3e06d14de744466e734a9085360aeed612f3ea800add488122ef227ba03d38ac048fd5c2fc87ed019a42fbd4c682b07f74d1a1cb92dcc2164c0cd8d13b021c806042016650137212088658212660034321bb78109348622c12480006c629651d912040098019b046cdac8308c128c199201c928664b948424c96514958c1c433021c67052088a80847150c65148082984088019956cc2148d4a38064198681002910108601992801a280c63106e0c2968d8a608e09884200464c442445c463183920c18b12008a38d110309143564194745cb4408ca208161b871d0407119852523b62ce2180908b94d0a15705036490aa551cac00418b2011a814d10a471d436900c45121c930d11396618217052204dc92072d8060d1384045388259b944c5bc07122406ac2486e1b86094ca465e3a26dc8c09062b651d3484a091741d832809b44094c024503c825db04325b883002110c19c35151826102b648a1940ce3a84942128242968d61422a1347001b440a58346c0cc48d9a38484bb801c00264e34288d0480120400a508440013032a496808344301a0146004741e3826d59b008c0187244124104379213824c8a366d99c229c4c6101ba020c932621418628946898ac088621860c014228130109b146ac3b6250a393003b6710b994d21b14914c944e4b40d934245e338000a468444a0511939851c24828c2646a1c871a2a80cd0a645c2060c5246219c444a59260edc106ce3868419a38d09984519a70c60346619320c50c60893c011999269e10606242711000506c03064620488d14421138911224602598849c40052182086000364904430db14891303204c824d19234c1b924d1c0166c2200a9c20320b39481b0861189181d24229e02642613010c14472509665443411e02246488870e1308e8c3240193521c836010b34640c118d94168d51268443c82c8b164a18a2801c00285c3421d29468a20490d192040cb684cb4890a140465cb26010150e19097044464d24324d1bc9451a222584446a04364ec1b2648a3450ca28320ab38924056459426140266ecc38510ca50943088d11a45009a005a34041414200e3409218998011062690127218412502976591240c82302ddc3429c00268810452c2886c4942419316858b8404c1427121144c4406445a140288220920120cd3a805043124c1184d1c07641c825159c8280b416518986c193145e21828c394600b936c611885202385d9260ae2128e13850409928d01c10020802418870840280588324adb3292c1c401199245223226048345ca06310949890887704c9860d14465d8a8849830420344461380852295704b04419b0420028249d4b000d1348d13155012490a1ba5640cb5108b3811d042311a940463424164c20cdc080623992d1c28600c026d0c194901488d90366c11c60524418e9b222dcb146e1ac1884b183184444110a22583484d1ab149e2b04023872183922de31631c11442218701a0122c20028814994811c161032084cc32204aa629242472020869db0205e1829049b208a11691091422800642840621e2206c11468199426653446081404d043161019809204762143380d1888dd9348cc048025b308252b4110a082ae1c6310023515a36311ac98c89c28da4a62d0802098b94441aa44c443672e32224140404e0a8001989911aa460823212c02690c3b848d484450a370514408e2492219b3826610481429071014251801251d834650b88498296899a268459a065d3a4640b29468b4824d9184aa4887102b464db186640281151284192c24521142012b5411490110c078000a88522346e09488ae3840c9494241a17819c0052db44114a4670113581da840441468a0b482a0c224ad938528344460ba405d13885cb469093b84514a7200cb04c4b4072484862c242501a95011a4288dc361101458cdc380e1c12840aa6499a128d81261263223113472e1bc72ccaa070da922443803122032ad3b2291c2762e3308003090a00376a00118550345202495289a61108a140194062592821e3b2244996710c00109b30001483881a037002414c11068120498410158099908050c601a0142509b74dc0bc8f9c11686977238332d2427ba6786b4912773479c4a361d6a2c4c3b2acfb1504727ce692944337e267aa471e1f4cf9b9de2131d640a2511a81ce20d32671e5623e9685971f51577c130413cda9280fb7b1f8c19aa9316d37ec311a158b5c509ff2abeb1426fbabdf9527f0670f2b47273c9d3f4038cc293028712fe3d91ea1530acaf81858fbbaef00473c1fcaba2821e1f6b317127b6c67a8289f13c3790e88e3708f973e0ce684fca096f5ddfe33c19202f19720203566ec159a291c71b1d3d1463ffa03198abad3cee0e6f99f2f997bdaca5e659702f56886aa9707514a620798c255f039888fb8a4ec49616c54e749676c6d320c18230d0e8277bef360eeb4fe72a64379eb73be3edb4ac9a59f15076b5ff0cdce1e98e41e287956e6e8a3b937e34874139c8d80fa6321043c1e03451b87f06d08c80c745464c48521e0f4e9d964ec6f577e88e17ebec61ef98bb962ebec9b0a663bd31170e3ceb3ceaf6cfbf5a395e153d7750c3aff01596e23c2bc7b63fdb3aca6682c8609136e7db710b6a6988f74c18aae20b798aeaf82010b7b618fa4f6a8e9d661655b112dee4847656524f80e8f76c7b4c59f3898511a1df9d2fcc22cae741d2129ca63de51e7e3f6680699972a76705e61167b2c257d2ee2c703e7936648d7e24c2c0aa78a260972ec43fb1cbe3049d1659678723368598fcffc32523b884bd4e16883613d9514c1b846392a2f8dcf1b3f3b46c75b6472185c8c8d111c0a7b50a057689e96489ccab3dd275550b46b677319f04b0de74a18478a24f0827296eabd801c01bc3db782a592689ad44bd5d7fe4efc61eedac9640fb1779b2f6f717a17105968dee3f55f6edd8e8b1f11816082bd342f93ff3d5bafa724f0872c4f530fe854e6f686015e72f457f956909efb250bb3e3c174b538d5cdc96c1f93968ba55491b429233a323922b771d08419e8f16407c7944939ac8cdb264b6cfb748c9d8cbbf859ca922eb13581e396d6b5ad7d14f5a150da9be413c9afec3295d503b43656047370660d28929a3d1d36526d727601813de66630e5dc6b2d18485f0bc8f09a9e6e1cdb08b36b5bfb2a62528ccaa3412720f5e4b59862bb527884c45c7770a83da67d00cc756b3327b98310600c58da37648f9a9965226b49cbe75aafbc3ef49fcddb8ad78c0deb21920d7d7c07df38121ffba813d9ed53690a6fd49e31e9b5970d7b7040b3d5a01e956181181b340dfd0d15855e4aa9f2e7f538d5f4320dbc8f6ad424fdd5efbeb317b2b8d9d4b61222fc1cc9f645f92319ed0d5106f0299a49e5032c29da92bda915392e3010103de3e23c92cc31ba7d82d2c1e21349d543432098f1e31fca896af32825342f84ce5b9cafb657c35c8aba340617e91f22e4bd1fd60309a09e36f86b158372cec558d80daadbb66f7e40b4b14b868eea5933976ea962afa6c25a263ed5c2992761a18a3fd6efd4c7a4ab635dcbd8561a293ad3351e6d921da43e38a8cb9eefbe729baf427ea5a56da4e60f05ca9de4a7e4e333f6d2c49b05b48b8c1940fff4ad01ce9d205daed93a629dd4543a8a95c6e848c5bb3e3e8b0b8fd32c5fdd1f126922b1946f2d5189638c5ac68a012e38bed50945d77a80c71fc89b09d4dc8ac389bc539bb9bd047a0dd0a5021b162bc826629ee7bedcc93524f016f85e27d54f50f6cac9e3dbc9c321c97c31ee8752897ff3897672274955d85a622a02f65bd4499cf08f8777ac5ce3cd4330b95154e7f5d7190604b1647f836953c6e4eb96006c1b0abd6140840de7a873029d69c280bd8118c393099f3c92f066710e88139d8eeb4288c016925f32d8cc62d34906ff35ad0880cc0231814e7cb68f066b0b2fa1fcefbce5505b39ece7f5d095ea2c6908f25d13be6b9ceaa6220170c415e51eec7ffd9fc2e6047eb31059f50040ea7c9888e37bf2121208c0cf8ad153562e0af09e07ca9a0fa812ac6c94b8090b95164f3d1cf0dbe515e4256c82ad71b6a04e74d3852a4b3fd2cde2f3a49ef676ddd05dcb120bcff126f59c102a4cc71afc98ba9067a7c5b5d5b40b4c2d0ffa368219600c859b898af55d9a18a9b118ef0f085eefa53bf7223aeb47c5930bba4d289f72d99826939205ac4d175e0cc47f9b985497a7b6f5b78bf81ee5bfb600b639f762ccc127269ad6c3fe3ff3bbfd3b9ffeddce436e7da92990b4dea696908a8233547dc0104142e86ef7d8107f5b389a67d6af13d9c69f3c0316cd6d61a267e5b1866ea9e5ba7d53284f60a2de4201393fac7604241c3802ee702f041dc0b2f64ef4c281c301d31f52ec52dc93e110208fcbb73824a9bfe7571c85028b24594f8f3f4f1e1f97e870578928fff2209c67a13bb2f1717db5d780888c4aa932376895c77a8047f36e8f8a798d9f2dcfba3a44c9e85718f168a17197a165ea16af2c796660209142313e88fe0fb76c04558cf317e1d8efb54f2cd74d29f053ec29ab76250f231cffb9e7229a349f3aff807c00b316f59ed5b04ebbe6b7a209d84b95faa02d396698117d675c06b0acc657570d2c489fc1d036a537004bef039e1d6c28ed8184478265827fe691d0fa27ba5392d2c4bb9a41d8bdd590717fcb542dbbd79381f8721fc5cc5ef4ec3635453f21565c3f8f5e71851fcd0cd17667eee5629a3f40e76021909cce2655e1622f8492690e8d50b0772e6d5778bd391a3516f96ec4cc00fb7b7cd5c07ff96084e51e13089bfaae4206632105850ff549a88baa28b26a8325dc83597f3210e02f8ae54ff50d1277fa559fd9fa05f697260c09e6e209757eb747e4ce56d5f01ae38a0a11f2cbe95332ddda9021eacf58693d6358244507617e445b349c681508a16acca47c5d61679575856a82742abcd976fe3ef1aded89697e8415825aa05bbec0538ddbab808bce59d768c6cdbc6d51dbfe1f01f0fbc94103277660ee6dcd10fce9e33b520de752d173d4cfc2b5754a3c92e81438e5380cec83d734f2945ab5c62b92c96e0d3b5aaf63b1ee378e8127ce019605d747766ac4a3783fa2c213845a3d2ccd0a6580bef5a436b3453bdb2b77dcf59dfec63580e41109ed75f84dd80a21d0b40328000cd5f1bbd9c1927aab3a0892048f95011984bc3b7c467704638df57959547c7ca18da56b75b879bb9832046c1c12cf9e4de9e6570c77e3b7c7a33fdf9a031b1c9df2dca8013e52d61bfaf4c86c9f570a395cfc052a8929876a993ce784ff76277acd2742d7aebb0bb248269efe35ce8e3349fb49a05bc12b8688729295e48ed46d13cdad63bb44eeaba27da023290b570f032751cd6aec15b88eff5917eda47cc93f11c753fd137cff477df92311284483b740a02e0b19965b976efec12b86f68470bab1bdcf86ff839ffac70fe7893d3f73be46c9bec11b738c8ef7b08f2f42cd87e9e081102a0f266d7503f7e996593a46220f3db519c6809fa4d8f67210ee99ca1b4837e1f7d37f108a4751e1f35c7f4da1b585db25bb0dbc2c68d9e4a13b484a7143e64621c6e0b6c141021befad4e6d05a5994375e115548eb8888be42ece5de328ded5ff2d59ba962a453db66b80beef6a9a64d656e0208cc0c71e4b03b16e2d42f44def1c98e32c3dc3d01ccdfde69a64ef59d926dac518396c522438c8fc8aa76738696421c36b64984a11e9fb26ad06ac9ec1e5697970dca72fd6fa2028bead575543b539783b0cc92158196512c10fb449235cdc6347248a67db37ee1127f2666983d010f9a44ed9fc0e755b4e6a2c2abcd222544714184b8c9db72e6711e43beb631d3774d197a12a760b4025611346f500522ee173f40694d53aef5c079cb8b63e02e8a61b86e1b4490e72c3175bce78d37f9bb79a673ba58873e98154d62ee89e69675c407f0485bef1c42a2a57fc483c977a802117454296cc7b615fdbdc03b63d04a5f5f80733e9d837c4479e5bc0c3aa5f13c3532f94b55e481760d0c81822fbd237ff9338f8e833ca7469e6f93baeb2388d9730dcc96c38015ee52235cbd5c453d27d929b715726ad479f8c5312ed35d199b283e419aa88bfe663c4ed1e765beeb9cae86f1db9f39e14dd1df9020d9faa7399da3fc54c1c4c4c88bb4d171d08d7359e7443d680c6f8252d365caeec3d312a856f2333a76fa9242c756ebd0be184c767c7ae5a807420286017da9887230a0c44bb2a0986bd6a390f30e5ef1893bfda3c6abe716515277139a34dbe32a7a61e90d4b754180df21bd5378f4965fff6c73d79834e7ae0e3c1770ec4cf9928ab9bb10bf2fd0d0430afaa3e22bb43c04bbea1fa7b65a91baa9e92c9d2317d844e1196eb08f1a2bf6e93fd4818bb24744cc866962099eec2a93fb53168485af983fdb542660146895300146363433251905fe09458e70dfa339fd143bc57b152715ba3060fc12af3494d9623d11de42e7fdf7d2dc95bc8ef31c40497fafd47e87995b882ed8987d256690ea6329f8bde3c3c587e2f82c2886ba028e3616896ad3b7d89634c3437fa2d9a9259f2f4efa7356955175ad3e0a6f2ad8cf5cab2925b28f25ad29c1e7570ebd040462d04ed4ae33b0b4f65919e347d4c00f58f29cb2486369aa5ce58673f4803a090fea88da783896e7d704c471362b810e098762f6c42cf507d8775e7e1bd437c59a44feceee87f32e07adbfa2ffd1b3f01ae87a06cae0add428bb0d3eef19505eab1b17c1cfd6510d4145e3a64a006 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/sign.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/sign.c new file mode 100644 index 0000000000000000000000000000000000000000..b3104ab47591701cf47b3f2a7d09c638a5553247 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/sign.c @@ -0,0 +1,631 @@ +#include +#include "params.h" +#include "sign.h" +#include "packing.h" +#include "polyvec.h" +#include "poly.h" +#include "randombytes.h" +#include "symmetric.h" +#include "fips202.h" +#include "reduce.h" + +/************************************************* +* Name: crypto_sign_keypair_with_external_seed +* +* Description: Generates public and private key using an external seed. +* +* Arguments: - uint8_t *pk: pointer to output public key (allocated +* array of CRYPTO_PUBLICKEYBYTES bytes) +* - uint8_t *sk: pointer to output private key (allocated +* array of CRYPTO_SECRETKEYBYTES bytes) +* - const uint8_t *external_seed: pointer to an array of +* SEEDBYTES number of uint8_t values +* +* Returns 0 (success) +**************************************************/ + +// Function to print an array of bytes in hex format +void print_hex(const char *label, const uint8_t *data, size_t len) { + printf("%s: ", label); + for (size_t i = 0; i < len; ++i) { + printf("%02X", data[len-1-i]); + } + printf("\n"); +} + + +void print_polyk_from_hex(const char *label, uint8_t *data, size_t len) { + size_t cnt = len; + printf("%s: ", label); + for (size_t i = 0; i < K; ++i) { + printf("vec[%zu]: ", i); + for (size_t j = 0; j < N; ++j) { + cnt--; + printf("%02X ", data[cnt]); + } + printf("\n"); + } +} + +// Function to print a polyvecl structure in hex format +void print_polyvecl(const char *label, const polyvecl *v) { + printf("%s:\n", label); + for (size_t i = 0; i < L; ++i) { + printf("vec[%zu]: ", i); + for (size_t j = 0; j < N; ++j) { + // printf("%08X ", v->vec[i].coeffs[j]); + printf("%08X ", caddq(v->vec[i].coeffs[j])); + } + printf("\n"); + } +} + +// Function to print a polyvecl structure in hex format +void print_polyveck(const char *label, const polyveck *v) { + printf("%s:\n", label); + for (size_t i = 0; i < K; ++i) { + printf("vec[%zu]: ", i); + for (size_t j = 0; j < N; ++j) { + // printf("%08X ", v->vec[i].coeffs[j]); + printf("%08X ", caddq(v->vec[i].coeffs[j])); + } + printf("\n"); + } +} + +// Function to print a polyvecl structure in hex format +void print_poly(const char *label, const poly *v) { + printf("%s:\n", label); + printf("vec[0]: "); + for (size_t j = 0; j < N; ++j) { + // printf("%08X ", v->vec[i].coeffs[j]); + printf("%08X ", caddq(v->coeffs[j])); + } + printf("\n"); +} + +int crypto_sign_keypair_with_external_seed(uint8_t *pk, uint8_t *sk, const uint8_t *external_seed) { + uint8_t seedbuf[2*SEEDBYTES + CRHBYTES]; + // UPDATED because tr is 512-bit + uint8_t tr[SEEDBYTES*2]; + const uint8_t *rho, *rhoprime, *key; + polyvecl mat[K]; + polyvecl s1, s1hat; + polyveck s2, t1, t0; + + /* Copy external seed into seedbuf */ + memcpy(seedbuf, external_seed, SEEDBYTES); + //=============================================================== + // ********************** FIPS Update *************************** + // shake256(seedbuf, 2*SEEDBYTES + CRHBYTES, seedbuf, SEEDBYTES); + const uint8_t byte_K = K; // K = 8 + const uint8_t byte_L = L; // L = 7 + seedbuf[SEEDBYTES] = byte_K; + seedbuf[SEEDBYTES + 1] = byte_L; + shake256(seedbuf, 2*SEEDBYTES + CRHBYTES, seedbuf, SEEDBYTES+2); + //=============================================================== + rho = seedbuf; + rhoprime = rho + SEEDBYTES; + key = rhoprime + CRHBYTES; + + /* Expand matrix */ + polyvec_matrix_expand(mat, rho); + + /* Sample short vectors s1 and s2 */ + polyvecl_uniform_eta(&s1, rhoprime, 0); + polyveck_uniform_eta(&s2, rhoprime, L); + + /* Matrix-vector multiplication */ + s1hat = s1; + polyvecl_ntt(&s1hat); +#if DEBUG == 1 + print_polyvecl("s1", &s1); + print_polyvecl("s1hat", &s1hat); +#endif + + + polyvec_matrix_pointwise_montgomery(&t1, mat, &s1hat); + polyveck_reduce(&t1); + polyveck_invntt_tomont(&t1); + + /* Add error vector s2 */ + polyveck_add(&t1, &t1, &s2); +#if DEBUG == 1 + print_polyveck("t", &t1); +#endif + + /* Extract t1 and write public key */ + polyveck_caddq(&t1); + polyveck_power2round(&t1, &t0, &t1); + pack_pk(pk, rho, &t1); + + /* Compute H(rho, t1) and write secret key */ + // UPDATED because tr is 512-bit + // shake256(tr, SEEDBYTES, pk, CRYPTO_PUBLICKEYBYTES); + shake256(tr, 2*SEEDBYTES, pk, CRYPTO_PUBLICKEYBYTES); + pack_sk(sk, rho, tr, key, &t0, &s1, &s2); + +#if DEBUG == 1 + print_polyveck("s2", &s2); + print_polyveck("t0", &t0); + print_polyveck("t1", &t1); + print_hex("seedbuf", seedbuf, sizeof(seedbuf)); + print_hex("tr", tr, SEEDBYTES*2); + print_hex("rho", rho, SEEDBYTES); + print_hex("rhoprime", rhoprime, CRHBYTES); + print_hex("key", key, SEEDBYTES); +#endif + + return 0; +} + + +/************************************************* +* Name: crypto_sign_keypair +* +* Description: Generates public and private key. +* +* Arguments: - uint8_t *pk: pointer to output public key (allocated +* array of CRYPTO_PUBLICKEYBYTES bytes) +* - uint8_t *sk: pointer to output private key (allocated +* array of CRYPTO_SECRETKEYBYTES bytes) +* +* Returns 0 (success) +**************************************************/ +int crypto_sign_keypair(uint8_t *pk, uint8_t *sk) { + uint8_t seedbuf[2*SEEDBYTES + CRHBYTES]; + uint8_t tr[SEEDBYTES]; + const uint8_t *rho, *rhoprime, *key; + polyvecl mat[K]; + polyvecl s1, s1hat; + polyveck s2, t1, t0; + + /* Get randomness for rho, rhoprime and key */ + randombytes(seedbuf, SEEDBYTES); + shake256(seedbuf, 2*SEEDBYTES + CRHBYTES, seedbuf, SEEDBYTES); + rho = seedbuf; + rhoprime = rho + SEEDBYTES; + key = rhoprime + CRHBYTES; + + /* Expand matrix */ + polyvec_matrix_expand(mat, rho); + + /* Sample short vectors s1 and s2 */ + polyvecl_uniform_eta(&s1, rhoprime, 0); + polyveck_uniform_eta(&s2, rhoprime, L); + + /* Matrix-vector multiplication */ + s1hat = s1; + polyvecl_ntt(&s1hat); + polyvec_matrix_pointwise_montgomery(&t1, mat, &s1hat); + polyveck_reduce(&t1); + polyveck_invntt_tomont(&t1); + + /* Add error vector s2 */ + polyveck_add(&t1, &t1, &s2); + + /* Extract t1 and write public key */ + polyveck_caddq(&t1); + polyveck_power2round(&t1, &t0, &t1); + pack_pk(pk, rho, &t1); + + /* Compute H(rho, t1) and write secret key */ + shake256(tr, SEEDBYTES, pk, CRYPTO_PUBLICKEYBYTES); + pack_sk(sk, rho, tr, key, &t0, &s1, &s2); + + return 0; +} + +/************************************************* +* Name: crypto_sign_signature +* +* Description: Computes signature. +* +* Arguments: - uint8_t *sig: pointer to output signature (of length CRYPTO_BYTES) +* - size_t *siglen: pointer to output length of signature +* - uint8_t *m: pointer to message to be signed +* - size_t mlen: length of message +* - uint8_t *sk: pointer to bit-packed secret key +* +* Returns 0 (success) +**************************************************/ +/* +* I need to add rnd input as an argument, which is signature randomness. +* This rnd is 256-bit, meaning that it should be const uint8_t *rnd. +* As a result, seedbuf requires should be extended 256 bit more. +* Since the result is written to the memory following rhoprime pointer, +* it should not be problem. +* shake256(rhoprime, CRHBYTES, key, SEEDBYTES + CRHBYTES) requires update +* because lenght changed and the initial pointer cannot cover rnd. It covers +* key and mu. +*/ +int crypto_sign_signature(uint8_t *sig, + size_t *siglen, + const uint8_t *m, + const uint8_t *rnd, + size_t mlen, + const uint8_t *sk) +{ +#if DEBUG == 1 + printf("\n======================================\n"); + printf("\n========Signature Generation==========\n"); + printf("\n======================================\n"); + int i; +#endif + unsigned int n; + // I need to update this part because tr is 512 bit not, 256-bit + // uint8_t seedbuf[3*SEEDBYTES + 2*CRHBYTES]; + uint8_t seedbuf[3*SEEDBYTES + 2*CRHBYTES + SEEDBYTES*2]; + uint8_t *rho, *tr, *key, *mu, *rhoprime; + uint16_t nonce = 0; + polyvecl mat[K], s1, y, z; + polyveck t0, s2, w1, w0, h; + poly cp; + keccak_state state; + + rho = seedbuf; + tr = rho + SEEDBYTES; + key = tr + SEEDBYTES*2; + mu = key + SEEDBYTES; + rhoprime = mu + CRHBYTES; + unpack_sk(rho, tr, key, &t0, &s1, &s2, sk); +#if DEBUG == 1 + printf("\n========Unpacked secret key elements==========\n"); + print_hex("rho", rho, SEEDBYTES); + print_hex("tr", tr, SEEDBYTES*2); + print_hex("K", key, SEEDBYTES); + print_hex("M_prime", m, ((unsigned int)mlen)); + print_polyvecl("s1", &s1); + print_polyveck("s2", &s2); + print_polyveck("t0", &t0); +#endif + + /* Compute CRH(tr, msg) */ + shake256_init(&state); + shake256_absorb(&state, tr, SEEDBYTES*2); + shake256_absorb(&state, m, mlen); + shake256_finalize(&state); + shake256_squeeze(mu, CRHBYTES, &state); + + +#ifdef DILITHIUM_RANDOMIZED_SIGNING + randombytes(rhoprime, CRHBYTES); +#else + // shake256(rhoprime, CRHBYTES, key, SEEDBYTES + CRHBYTES); + // I updated this part because NIST hashes rnd with key and mu + /* Hash key || rnd || mu to generate rhoprime */ + shake256_init(&state); + shake256_absorb(&state, key, SEEDBYTES); // Absorb key (32 bytes) + shake256_absorb(&state, rnd, SEEDBYTES); // Absorb rnd (32 bytes) + shake256_absorb(&state, mu, CRHBYTES); // Absorb mu (64 bytes) + shake256_finalize(&state); + shake256_squeeze(rhoprime, CRHBYTES, &state); // Generate rhoprime +#endif + +#if DEBUG == 1 + print_hex("mu", mu, SEEDBYTES*2); + print_hex("rhoprime", rhoprime, 2*SEEDBYTES); +#endif + + /* Expand matrix and transform vectors */ + // TODO: I am not sure about this part, NIST spec and Dilithum spec uses + // rhoprime + polyvec_matrix_expand(mat, rho); +#if DEBUG == 1 + for(i = 0; i < K; ++i){ + printf(" A[%d] \n",i); + print_polyvecl("A", &mat[i]); + } +#endif + + polyvecl_ntt(&s1); + polyveck_ntt(&s2); + polyveck_ntt(&t0); + +rej: + /* Sample intermediate vector y */ + polyvecl_uniform_gamma1(&y, rhoprime, nonce++); +#if DEBUG == 1 + print_polyvecl("y", &y); +#endif + + /* Matrix-vector multiplication */ + z = y; + polyvecl_ntt(&z); + polyvec_matrix_pointwise_montgomery(&w1, mat, &z); + polyveck_reduce(&w1); + polyveck_invntt_tomont(&w1); +#if DEBUG == 1 + print_polyveck("Ay", &w1); +#endif + + /* Decompose w and call the random oracle */ + polyveck_caddq(&w1); + polyveck_decompose(&w1, &w0, &w1); +#if DEBUG == 1 + print_polyveck("w0", &w0); + print_polyveck("Decomposed w1", &w1); +#endif + polyveck_pack_w1(sig, &w1); +#if DEBUG == 1 + print_polyk_from_hex("w1Encode", sig, K*POLYW1_PACKEDBYTES); +#endif + + shake256_init(&state); + shake256_absorb(&state, mu, CRHBYTES); + shake256_absorb(&state, sig, K*POLYW1_PACKEDBYTES); + shake256_finalize(&state); + // shake256_squeeze(sig, SEEDBYTES, &state); + // Updated because we use 512-bit output + shake256_squeeze(sig, CRHBYTES, &state); +#if DEBUG == 1 + print_hex("~c1", sig, SEEDBYTES); + print_hex("~c2", sig+SEEDBYTES, SEEDBYTES); +#endif + poly_challenge(&cp, sig); +#if DEBUG == 1 + print_poly("c", &cp); +#endif + poly_ntt(&cp); +#if DEBUG == 1 + print_poly("c_hat", &cp); +#endif + + /* Compute z, reject if it reveals secret */ + polyvecl_pointwise_poly_montgomery(&z, &cp, &s1); + polyvecl_invntt_tomont(&z); + polyvecl_add(&z, &z, &y); + polyvecl_reduce(&z); +#if DEBUG == 1 + print_polyvecl("z", &z); +#endif + if(polyvecl_chknorm(&z, GAMMA1 - BETA)){ +#if DEBUG == 1 + printf("\n-----------------------------------\n"); + printf("Signature was Rejected due to z"); + printf("\n-----------------------------------\n"); +#endif + goto rej; + } + + /* Check that subtracting cs2 does not change high bits of w and low bits + * do not reveal secret information */ + polyveck_pointwise_poly_montgomery(&h, &cp, &s2); + polyveck_invntt_tomont(&h); + polyveck_sub(&w0, &w0, &h); + polyveck_reduce(&w0); +#if DEBUG == 1 + print_polyveck("r0", &w0); +#endif + if(polyveck_chknorm(&w0, GAMMA2 - BETA)){ +#if DEBUG == 1 + printf("\n-----------------------------------\n"); + printf("Signature was Rejected due to r0"); + printf("\n-----------------------------------\n"); +#endif + goto rej; + } + + /* Compute hints for w1 */ + polyveck_pointwise_poly_montgomery(&h, &cp, &t0); + polyveck_invntt_tomont(&h); + polyveck_reduce(&h); +#if DEBUG == 1 + print_polyveck("<>", &h); +#endif + if(polyveck_chknorm(&h, GAMMA2)) + goto rej; + + polyveck_add(&w0, &w0, &h); + n = polyveck_make_hint(&h, &w0, &w1); +#if DEBUG == 1 + print_polyveck("after makehint h", &h); +#endif + if(n > OMEGA) + goto rej; + + /* Write signature */ + pack_sig(sig, sig, &z, &h); + *siglen = CRYPTO_BYTES+SEEDBYTES; + return 0; +} + +/************************************************* +* Name: crypto_sign +* +* Description: Compute signed message. +* +* Arguments: - uint8_t *sm: pointer to output signed message (allocated +* array with CRYPTO_BYTES + mlen bytes), +* can be equal to m +* - size_t *smlen: pointer to output length of signed +* message +* - const uint8_t *m: pointer to message to be signed +* - size_t mlen: length of message +* - const uint8_t *sk: pointer to bit-packed secret key +* +* Returns 0 (success) +**************************************************/ +int crypto_sign(uint8_t *sm, + size_t *smlen, + const uint8_t *m, + const uint8_t *rnd, + size_t mlen, + const uint8_t *sk) +{ + size_t i; + + for(i = 0; i < mlen; ++i) + sm[CRYPTO_BYTES +SEEDBYTES + mlen - 1 - i] = m[mlen - 1 - i]; + crypto_sign_signature(sm, smlen, sm + CRYPTO_BYTES+SEEDBYTES, rnd, mlen, sk); + *smlen += mlen; + return 0; +} + +/************************************************* +* Name: crypto_sign_verify +* +* Description: Verifies signature. +* +* Arguments: - uint8_t *m: pointer to input signature +* - size_t siglen: length of signature +* - const uint8_t *m: pointer to message +* - size_t mlen: length of message +* - const uint8_t *pk: pointer to bit-packed public key +* +* Returns 0 if signature could be verified correctly and -1 otherwise +**************************************************/ +int crypto_sign_verify(const uint8_t *sig, + size_t siglen, + const uint8_t *m, + size_t mlen, + const uint8_t *pk) +{ + unsigned int i; + uint8_t buf[K*POLYW1_PACKEDBYTES]; + uint8_t rho[SEEDBYTES]; + uint8_t mu[CRHBYTES]; + // uint8_t c[SEEDBYTES]; + // uint8_t c2[SEEDBYTES]; + uint8_t c[SEEDBYTES*2]; + uint8_t c2[SEEDBYTES*2]; + poly cp; + polyvecl mat[K], z; + polyveck t1, w1, h; + keccak_state state; + + if(siglen != (CRYPTO_BYTES+SEEDBYTES)) + return -1; + + unpack_pk(rho, &t1, pk); + if(unpack_sig(c, &z, &h, sig)) + return -1; + if(polyvecl_chknorm(&z, GAMMA1 - BETA)) + return -1; + + /* Compute CRH(H(rho, t1), msg) */ + // shake256(mu, SEEDBYTES, pk, CRYPTO_PUBLICKEYBYTES); + // This one is tr + shake256(mu, SEEDBYTES*2, pk, CRYPTO_PUBLICKEYBYTES); +#if DEBUG == 1 + print_hex("tr", mu, SEEDBYTES*2); + print_hex("rho", rho, SEEDBYTES); + print_hex("M_prime", m, ((unsigned int)mlen)); +#endif + // This for mu + shake256_init(&state); + // shake256_absorb(&state, mu, SEEDBYTES); + shake256_absorb(&state, mu, SEEDBYTES*2); //tr + // printf("the message lenght is %d\n",mlen); + shake256_absorb(&state, m, mlen); + shake256_finalize(&state); + shake256_squeeze(mu, CRHBYTES, &state); +#if DEBUG == 1 + print_hex("mu", mu, SEEDBYTES*2); + print_polyveck("h", &h); + print_polyveck("t1", &t1); + print_polyvecl("z", &z); +#endif + + + /* Matrix-vector multiplication; compute Az - c2^dt1 */ + poly_challenge(&cp, c); + polyvec_matrix_expand(mat, rho); + +#if DEBUG == 1 + for(i = 0; i < K; ++i){ + printf(" A[%d] \n",i); + print_polyvecl("A", &mat[i]); + } +#endif + + polyvecl_ntt(&z); + polyvec_matrix_pointwise_montgomery(&w1, mat, &z); + + poly_ntt(&cp); + polyveck_shiftl(&t1); + polyveck_ntt(&t1); + polyveck_pointwise_poly_montgomery(&t1, &cp, &t1); + + polyveck_sub(&w1, &w1, &t1); + polyveck_reduce(&w1); + polyveck_invntt_tomont(&w1); + + /* Reconstruct w1 */ + polyveck_caddq(&w1); +#if DEBUG == 1 + print_polyveck("w1", &w1); +#endif + polyveck_use_hint(&w1, &w1, &h); + polyveck_pack_w1(buf, &w1); + +#if DEBUG == 1 + print_hex("Decomposed w1", buf, K*POLYW1_PACKEDBYTES); +#endif + + /* Call random oracle and verify challenge */ + shake256_init(&state); + shake256_absorb(&state, mu, CRHBYTES); + shake256_absorb(&state, buf, K*POLYW1_PACKEDBYTES); + shake256_finalize(&state); + // shake256_squeeze(c2, SEEDBYTES, &state); + shake256_squeeze(c2, SEEDBYTES*2, &state); + for(i = 0; i < SEEDBYTES*2; ++i) + if(c[i] != c2[i]) + { + printf("Mismatch c[%d] = %d, while c[%d] = %d\n", i,c[i], i, c2[i]); + return -1; + } + + return 0; +} + +/************************************************* +* Name: crypto_sign_open +* +* Description: Verify signed message. +* +* Arguments: - uint8_t *m: pointer to output message (allocated +* array with smlen bytes), can be equal to sm +* - size_t *mlen: pointer to output length of message +* - const uint8_t *sm: pointer to signed message +* - size_t smlen: length of signed message +* - const uint8_t *pk: pointer to bit-packed public key +* +* Returns 0 if signed message could be verified correctly and -1 otherwise +**************************************************/ +int crypto_sign_open(uint8_t *m, + size_t *mlen, + const uint8_t *sm, + size_t smlen, + const uint8_t *pk) +{ + size_t i; + + if(smlen < CRYPTO_BYTES+SEEDBYTES) + goto badsig; + + *mlen = smlen - (CRYPTO_BYTES+SEEDBYTES); + // printf("the message lenght is %d and smlen (%d) - CRYPTO_BYTES+SEEDBYTES(%d) \n",*mlen, smlen, (CRYPTO_BYTES+SEEDBYTES)); + // int crypto_sign_verify(const uint8_t *sig, + // size_t siglen, + // const uint8_t *m, + // size_t mlen, + // const uint8_t *pk) + if(crypto_sign_verify(sm, CRYPTO_BYTES+SEEDBYTES, sm + SEEDBYTES +CRYPTO_BYTES, *mlen, pk)) + goto badsig; + else { + /* All good, copy msg, return 0 */ + for(i = 0; i < *mlen; ++i) + m[i] = sm[CRYPTO_BYTES+SEEDBYTES + i]; + return 0; + } + +badsig: + /* Signature verification failed */ + *mlen = -1; + for(i = 0; i < smlen; ++i) + m[i] = 0; + + return -1; +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/sign.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/sign.h new file mode 100644 index 0000000000000000000000000000000000000000..2d843aa27e432a0098eecc394dd1001e1792b271 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/sign.h @@ -0,0 +1,64 @@ +#ifndef SIGN_H +#define SIGN_H + +#include +#include +#include "params.h" +#include "polyvec.h" +#include "poly.h" +#include +#include + +#define DEBUG 1 + +#define challenge DILITHIUM_NAMESPACE(challenge) +void challenge(poly *c, const uint8_t seed[SEEDBYTES]); + +#define crypto_sign_keypair DILITHIUM_NAMESPACE(keypair) +int crypto_sign_keypair(uint8_t *pk, uint8_t *sk); + +#define crypto_sign_signature DILITHIUM_NAMESPACE(signature) +int crypto_sign_signature(uint8_t *sig, + size_t *siglen, + const uint8_t *m, + const uint8_t *rnd, + size_t mlen, + const uint8_t *sk); + +#define crypto_sign DILITHIUM_NAMESPACETOP +int crypto_sign(uint8_t *sm, + size_t *smlen, + const uint8_t *m, + const uint8_t *rnd, + size_t mlen, + const uint8_t *sk); + +#define crypto_sign_verify DILITHIUM_NAMESPACE(verify) +int crypto_sign_verify(const uint8_t *sig, size_t siglen, + const uint8_t *m, size_t mlen, + const uint8_t *pk); + +#define crypto_sign_open DILITHIUM_NAMESPACE(open) +int crypto_sign_open(uint8_t *m, size_t *mlen, + const uint8_t *sm, size_t smlen, + const uint8_t *pk); + +// Function to print an array of bytes in hex format +void print_hex(const char *label, const uint8_t *data, size_t len); + + +void print_polyk_from_hex(const char *label, uint8_t *data, size_t len); + +// Function to print a polyvecl structure in hex format +void print_polyvecl(const char *label, const polyvecl *v); + +// Function to print a polyvecl structure in hex format +void print_polyveck(const char *label, const polyveck *v) ; + +// Function to print a polyvecl structure in hex format +void print_poly(const char *label, const poly *v); + +int crypto_sign_keypair_with_external_seed(uint8_t *pk, uint8_t *sk, const uint8_t *external_seed); + + +#endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/signature.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/signature.hex new file mode 100644 index 0000000000000000000000000000000000000000..34181844a87a35cbeaf4273ff30eb92ed7e59b6a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/signature.hex @@ -0,0 +1 @@ +bee2e96b8885c3510f228117a257cb36f3b15776aa1166a8a7dbf872e91c213254be80999d1b912c0a8c42c866d0b67189e67a7b31f142ce5ea2bf98f58fdda7bd6f08340f16448878785dc9656e4fb5fa7633dd9e3d53c90359f63574cf0c0149cc45a5d9a5b85be69d990d97f339322a51ba64d678f1846971f24166b3564f3d90941c861d282aacdaeef5618fe2052131f090f2379711420100ece503ec457634490961f361e9467deadaa80983fe168be6265d63e80e596687255a518ac7eca75c93b5c6493e21aa9afe8ada0899462c6b33ea93fa880fffca6edd4c2b3ba926eeafed43cdc2255cb47a998827b722c37ff474710f46e640090feb04a64efd8ce48384709267e110ab2698d4831c7e10cae3e305d11e864ef7267c5a632c3fb1cc77ce90e19c73b6215c7118744d3d13138beefbd93e8fc93c9044099966b864911cdc941fa2675be5b906d0f7baab06e565bf7a171bc8785e8570d0d9eea4cbd366da38f6d6ecc85d1ba8e750821e248d385243c6adc341b1ada0817c5016967ea8a3683857d3ab00a1ee1c04e24d011a88f4215a2416238d96b72a87387cae8414d4d0556c5cfc6796d485a6972cf53b1b8f28f86abd9ff45553f1fcfd62b68133232324401ad23d13683b5a9822484a05ee6fce2f38ec9b63c7884e2d02ec3343779dbed68550dfd7bf10aa5cfee6c43df9b8c9ce7b65a04117ea3bb4d9efd84e2c4110b86e5730008a9c8c0d73f5347ca7a828a6e29dbf4d47afa2bc891822346b979bc1dff8b7af61470f8d02d38ce5fb8e2e9b23bad00440379bbc2e1da49600e733dd339cd0ce70567ca00b385442ad02f9237af6cd27791f93db0d4ad27288f1907d6772c64123dffab0f795a410d387c8dd625a1e5d87ffc65cd3785bc137e156ebd44c252a669ee7281d4059987162cd9c1f5cd27f903849348e9affd7539c3df09d65c227891d3a5c545e784c83e92ece1ff0a8b132929825f40d35aa2474d40f1828153dc52278bc2a04e81f3917b795adac98f69106931218ace17906d8400e432d424560d4dd2ce4cba011dc8fde7e4a60f3b166fd56f5fd27d4da6ed677ae21bb7a188cc4bf2f818361908b0c29215d3ea26f7a8f691f8abe1ad077d8711123cff6a33c36d52ac13a39e0e3c083231ae689be4d5f9f9ebfa36ff530f3c50717ba0e0aeb9feddcacae3348e541c73ae54c39f5d3069ee636b7f2cd55f404bdbb1043121b8a19435c540d3b6cba87112ab1646f86ff17b23b30692747bded845a3930c0a499fc27f1c36aee75097243df6a8a56d27310f35a06dfac76fecd1752a1a5c83c8ce8742b50ec04caeb416f2d5ffbaacb2ffe551cf4820fb0b69e3d5e039b6157a36d0d633197f7c6bd04e1f9a08ea7e49e0f5a7784e8d03d7e8e61e93b267865a695cb16f405984f92d50731b1d3c5b9f009e71e3795ebb1c5e5d9dd5710323258e7901a59f3054c752a9bc64e99f7389207b57d7a7c6e087e88abeec8604f417ad9a2ca325a4d3a13d88eff125fb43caebe4fe45833afd2200f6fcce3f913c31cc5db9f955da0d5bf616a009f8cdfe6a728b8b63dab99dfadf3edf2ad94c6417d710aedb625c495bfcc8b8dbbc6d0e91c830864c3084510755cbf4a75fe093f0791c49f6c757e059100cac6ea7c893edba0f0bc6daa785e5c02d6ea3b9c6a2b4522cc5bace5c85cafa0a02ab547ed841b1be648fbf0c7c97a85c97330a3b15d0d0c637ccdd1e5066ad5d31f09fe5f52ffc0e1eb5b9d1c65d858bce7d77acdb087e5e35a02613af8df62dd55ae74edfa1cc792b6342fd77b096ac4ce86eb32131591e11ef4068692fa3086b498a147d0877270a7307fd76afb5a139997b1c715ca78979560ea46d65f7c00311f34276f1d647843d5c2c0f1bb058481220bb60f17e52ee499f4b79662d179d5f65fd4c6b54025e59dc7a3707586c617e0a9a7ebd8c71206ebc69ac3351951f21127a45c4076031dfbd1e19353689be5aa4cee3c02ffed13f685debfcaf38ebea1665d847d16bf80e04711795f8bd0320bac579665ef8924094924992b7aec45c6196615cff05f0c96c4e86cbde14e35ff1c6381a84ebc6dd9f30b37ba20385d7ecf56c920f6e1f5782b530e1374604b3bf379ea0bc55d68f4b69aa88603cf6919658522f866b1b224841f1db614e440eaa7b5916b96ec3a40bf66d35d0cd3b8f103743061b9941eb55eaf7fcbfb2a1fbb6086bdc2675073d84fedca1727df4bcd03b27f9a362946f9a6eb9147e0a103fc93b9bff93fb1588c72a1d95c1531c148aeefa27631bf75874dba9aa4a04e8c91ded0e3cf8d54c890d9f333e31b9fc1709424b10e1e5919a883c780f1397ac6d41e38f2a941f604200801e68af1b343254e6a902dcc3064caedc766f1c7342bf5801e787dca74239b344e44c647fac5069c529c4fbd8a96a27f9d21fbc5a87e44fb02286fcb9ec673d040ede00df6b78cc6ee37a72d222e3e278e15042bb74435e6a4b65907dd3c0f16b9e405a1a1766dad7b6617ec285d87eac518bcded1f77bc42a20623ca8a4418368e94b17132adcac243e7cd25f19c2de3feb66c3d9be2954bddd9fc3f3fd9eb00860b7cea2b67ddac1dbea2d81ddaab0f632deb8c13a47f2d2d6e90514b17af9c16fce21cc62ccdf780a0e89b9d5afc056779b11160fd13bb0ac3e34b6f279ebc91c35bc03dc8d016065208a99daabcd2aaa25aa0a1e4cf4680b56026cf92472b770029a3952198fda37d478a365e45c93bf254e23498c11e19917b672785b5d711336af3ec1f77e8ca6a77cac03e70285c8927b9da859a58b1293b39954f3050260f6ad042f2497410b709025993ca59f9708abfe6f785b74e467989fd63c543afec3db5caf48f67958449b70b6a425d2976df6efd2d6d6e1f82cee3cf1ef6ee7e613cb15f2c2ddd148f6c2644a1dfd92c7527382c34b54fdfab22a9411a5d47048b8e0fad4e2ae91ee51ba3c829204db084381e4408450df456ce6e3f94097fa3f3404e0e9bfd1006a34f0d29551559642b31f58ce8e15cc5cab1168d89a413719705e25c9a65a75117f7d3eb858017c81d2bbbd3723bd90cef092aefe082a3471798b617ee325438f7dde3fcad1f61b0d85facf2e68c0dbbdf43e778410b2c40f258e50dcd47ab8382cfe2be960eb162fc6fed7ae47ad1fcd3de27c94a0b0dd2ba2d602f59f68a2d4b37bd4cba284a884525e8c3c60b7030b36b3c3d103fbf0f41bdcd19a58072cb193fd15842bad40bca764465f780f752e090063e782d5586f9225553572b2a9a9f6b0adaf10c395568f195926c5a00dbb4a2395700fa3f7c109f09ee677a829eb07efb1913c9f16926916fac1c4a33bdc7ee223781435592613a0498435d3d6943b47b796c7e7b2102d6142f9501d66d5c9b01eaed95d8ad1af9d652f90c653bd7a61fe19cc4dea2b8924b76a9eb0132922e40e37714d89e78c8cde7a42194e2b49023de9b0f46bb7080ae0094771e5d13ae151d673297db33689a288cf1fa70852f7868fceca1c2813a36d0e36d0b6c60039e2acb24457b3308cbcafdbca72d86bbb7c0f40759e000896b5da79cff117483fc71db60623de4ef0bbd4849b947cbd467ef808d6152ec2dfc30b7c8ab277d15738f9a1e706f5f1836433cd8db11513cae93332e2acf5c8a4f17cdbaa78f329bacf117f565ca4d3951de57d3f0f53c7407d8c0d14d574092465f1d961e423c726b52e8521762d1501d2572231ff3b2b14bb22f6ffd8ce0e772367778339d3e41bdab75344778ceb3b4ad92db692242aa6f72499d8cca75cb91eea06124b0c9b43288ba355f4fbe056e835079d792d6432a5a61c5bc5162ce0a48b92c2061aaeb015ee2da22eea1be135b13ccab419d7297433371dd5fcfb629c4216c352b360ad1e5b8b49f7a242a1179fc5494c73cf780fe21371d4fbd6fe2dbdbd0c335f4aa32ac4e08486bc210ff3b008b5f3ad3cab4f545f3acaecde59ed6d87c485c6a117d782706a835c5d8f4c88a8db10a71e36e96913af1f8b41ddb156141a2eb77c60f8356e21e48ba3a87c47a891a8e3b739933faa48415083e847161ae4d442874daa9e170ab52789146c34bd01db39b2202320534c9b1374473e5e386ca7024272b5dd2e72bfa11042633285048dbe9cf074e1e5a7bbe428b7d2c922729dacb6a4a765c16e97b56e52750bb2b2ca29b01007ed49d4d9bc684b06a7a4b1f79c7c1ac30b4bd34324251c2a5791716b85b032f66721c3e766898835e5da1e2f7b0de78661e983ebdc64b21f1b9b56d4e8d2193fe0d14d314f74c69a6bf4edce4d5b2f0c9f12033aec9904ba32f442c367f5344d7d22fb708a98d215f91bcff3be38d0581f0e7cdf846e5086b59879b1b8f71a7cafebd05c74f2d65b37c82768536b704beaf0256624d38a8301d74000a40d8b65c3e1d63ce09a1b6405909ddd1896986b414dc0f07b94d5a85e1cb114e61a39f0fc49f1cc2ca582bd5f8bad24fcab115d0fecfb3422c24b94d7239fc8e523b3a304a15d6dbdf31234b2181e8ebe6d59273c2705ba9ad66c3153396b5d974bdb950948e9a21e1a9ed23549d3a620fc3676f4d5f28f8382d6e40c8c0b5070364791c4283579e549fba6cd55c3b21e830c6ae04971303c625971ac25244c5452c231edd5a7029cb8d2340eb14b655716959fb548c91062b699b4f6a62bfae9872d419b1093f727c23a8dd5aaaff7b10f04d3ec466d423f0214fd2fdeeab947f23198516a07af052d57e8b86713d377df6337068b1b53c5cabe0987a8cca0a076c473c8de92fbc75e43165d24e60c75fdbb35c2befcafbfb0ab4cee6bc2abdeb47e35978eff163cc9efddc0b5981bcbfb697857528d0e489de27a139d2e1590fffe579e467b9519315e57b810a913bcc99ea4f28a054cd2fd55a3c43108433ee0c823a5b262f2a7ab3f993f760b922de1b6e2cd1211cf20cccf492ef2fbb57239fe355c758ef13f9ec5e201e59833a5bfce7006d1423164988fcf8a7586524a6e41822eb8e7ad41e84f86ec5861fc5a62942d343c4fd0b163ea6b4ac138e2b1f60f99bb9593b539c523930c857b13a7c2452e8859735a0dc2dc3f9a6e32c794057e625469a4e8b3dedb3c30eed8b338915e1db98634ae56fb92f6c2c45c3fca2263b2c1a0b27ef7c32c3497dc1be7aa269d8b829783b724fb113a0ad6f478874e46eea4ce3205149adb479aab0b71e237ac48d475c9a9380af108e2175cfae7ca06055e0819477d8e7aec09e0911ba7f00ae6f2db203dc4c4d96cd1e587386e98546241f84fd2a17ca2f2831d432cabcd9c55b6fe8bd96d889156dfb06f25e5b3af5c9ebd7f361d280b849f308d3d0742daefdf79f17acf3565054e9d5251e6615a57cf1cebcfb954b7ae6cf93e6fe247c35961ff553a6c4847e6234ebf85d1de8a644c3b0a8f1fdb0047677029d02d59324c42acb3d182316bf4b95afc88ddcc79a83598712f2e10247b2ea9f326936911e433d1d394620c156d11f5d72de7d77f0c2082275b87ffc042a1a5c3da7ef28e806039a145a315bd9a3afd48f1d00f1857baa549d9096dc8702426a3bbb2dc0f1b61d419ed8aaa0de51cbd86ab99e3daabb6516a329bb68fe677a2501a2c5c8922b24263eb63432d00ea436331a332b40f2d17922e19ac808c88685ff1980b8a2d2b4604a7fef1cd246bc4f987596025327ec5fe0b4a2a697e1be3a530ba56cef1a98245ab65c2cf88868ab9ba0f8f835c835fbacd67a7f2842ec5d32455aaf2f40488ebfd7c352b83e5dd1377b8c238eaf7d97b552e90fa1789f3c5a21d7117568d61d4f48ad916f2dec31cd7f50306ca6c157deb43668c68a801e471f263dfc54748158dfc57d598d42b3c6d686b092facb1a5bc0f8994747779bc9144faded095f773c714a7a0bcdefbb7116e16dd73c97a42bf789381ee709186931c5688a8ffcbb5617880180343606dc6d2d1aff5f4a70610f33a3fa9040aaaf379cf594becb1f7872e3720b5f9cda4bf7d8f5fb999a41ad173a6dc394912ff0c58b8e07373e8df02a15846435f320260b30607e9c94ba90768dc5679b35f25ba28312afc159175073d89814cb0a1c6883ed0a2415f7758a9a338b7da6ebff9dbdc0e874527363867f713b9b98ec2db5c19e97dd423a9b8acc9ccd7fea887b3cae3fbc4dd608cce9a2ca4c5e8b0763a8421ec3763dd93f3c8508cc7c2f9839caec36398ea0c327e710ff5266f41de7200c7b321f950a595e71a9f078e1fce18cf64dfcc082159f07c77a357393b46b72f6a80c0a090f65cab1003d5a37db3ade771c0be7032743c79c9afb763d8060899379e96e3cd8f8f05cca5644991c9671e9247db96ffc6dd0ba16583a52e8f8adfcf87f3a8030e1d2f45b2d2d4daef1c3841738e959aa8b3cbf634619099b4b74762696e7a8898b6e2ee09162e5c676c74929606070e123d4086b7516567bef8445b646b7093b5dee1000000000000000a151b252e363b440000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric-aes.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric-aes.c new file mode 100644 index 0000000000000000000000000000000000000000..b01e9204e94bf5ff2df36877275f21d4855280ed --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric-aes.c @@ -0,0 +1,13 @@ +#include +#include "symmetric.h" +#include "aes256ctr.h" + +void dilithium_aes256ctr_init(aes256ctr_ctx *state, + const uint8_t key[32], + uint16_t nonce) +{ + uint8_t expnonce[12] = {0}; + expnonce[0] = nonce; + expnonce[1] = nonce >> 8; + aes256ctr_init(state, key, expnonce); +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric-shake.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric-shake.c new file mode 100644 index 0000000000000000000000000000000000000000..11ec09cce6150df3a602d5d2fb9e75d0777d65cc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric-shake.c @@ -0,0 +1,28 @@ +#include +#include "params.h" +#include "symmetric.h" +#include "fips202.h" + +void dilithium_shake128_stream_init(keccak_state *state, const uint8_t seed[SEEDBYTES], uint16_t nonce) +{ + uint8_t t[2]; + t[0] = nonce; + t[1] = nonce >> 8; + + shake128_init(state); + shake128_absorb(state, seed, SEEDBYTES); + shake128_absorb(state, t, 2); + shake128_finalize(state); +} + +void dilithium_shake256_stream_init(keccak_state *state, const uint8_t seed[CRHBYTES], uint16_t nonce) +{ + uint8_t t[2]; + t[0] = nonce; + t[1] = nonce >> 8; + + shake256_init(state); + shake256_absorb(state, seed, CRHBYTES); + shake256_absorb(state, t, 2); + shake256_finalize(state); +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric.h new file mode 100644 index 0000000000000000000000000000000000000000..0b34fb685c539729172d8cb2d578810fd95ee97a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/symmetric.h @@ -0,0 +1,63 @@ +#ifndef SYMMETRIC_H +#define SYMMETRIC_H + +#include +#include "params.h" + +#ifdef DILITHIUM_USE_AES + +#include "aes256ctr.h" +#include "fips202.h" + +typedef aes256ctr_ctx stream128_state; +typedef aes256ctr_ctx stream256_state; + +#define dilithium_aes256ctr_init DILITHIUM_NAMESPACE(dilithium_aes256ctr_init) +void dilithium_aes256ctr_init(aes256ctr_ctx *state, + const uint8_t key[32], + uint16_t nonce); + +#define STREAM128_BLOCKBYTES AES256CTR_BLOCKBYTES +#define STREAM256_BLOCKBYTES AES256CTR_BLOCKBYTES + +#define stream128_init(STATE, SEED, NONCE) \ + dilithium_aes256ctr_init(STATE, SEED, NONCE) +#define stream128_squeezeblocks(OUT, OUTBLOCKS, STATE) \ + aes256ctr_squeezeblocks(OUT, OUTBLOCKS, STATE) +#define stream256_init(STATE, SEED, NONCE) \ + dilithium_aes256ctr_init(STATE, SEED, NONCE) +#define stream256_squeezeblocks(OUT, OUTBLOCKS, STATE) \ + aes256ctr_squeezeblocks(OUT, OUTBLOCKS, STATE) + +#else + +#include "fips202.h" + +typedef keccak_state stream128_state; +typedef keccak_state stream256_state; + +#define dilithium_shake128_stream_init DILITHIUM_NAMESPACE(dilithium_shake128_stream_init) +void dilithium_shake128_stream_init(keccak_state *state, + const uint8_t seed[SEEDBYTES], + uint16_t nonce); + +#define dilithium_shake256_stream_init DILITHIUM_NAMESPACE(dilithium_shake256_stream_init) +void dilithium_shake256_stream_init(keccak_state *state, + const uint8_t seed[CRHBYTES], + uint16_t nonce); + +#define STREAM128_BLOCKBYTES SHAKE128_RATE +#define STREAM256_BLOCKBYTES SHAKE256_RATE + +#define stream128_init(STATE, SEED, NONCE) \ + dilithium_shake128_stream_init(STATE, SEED, NONCE) +#define stream128_squeezeblocks(OUT, OUTBLOCKS, STATE) \ + shake128_squeezeblocks(OUT, OUTBLOCKS, STATE) +#define stream256_init(STATE, SEED, NONCE) \ + dilithium_shake256_stream_init(STATE, SEED, NONCE) +#define stream256_squeezeblocks(OUT, OUTBLOCKS, STATE) \ + shake256_squeezeblocks(OUT, OUTBLOCKS, STATE) + +#endif + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/cpucycles.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/cpucycles.c new file mode 100644 index 0000000000000000000000000000000000000000..ccbf54dd7d6f7c5a44c2b9a9b297adf3f9dcbc8b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/cpucycles.c @@ -0,0 +1,17 @@ +#include +#include "cpucycles.h" + +uint64_t cpucycles_overhead(void) { + uint64_t t0, t1, overhead = -1LL; + unsigned int i; + + for(i=0;i<100000;i++) { + t0 = cpucycles(); + __asm__ volatile(""); + t1 = cpucycles(); + if(t1 - t0 < overhead) + overhead = t1 - t0; + } + + return overhead; +} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/cpucycles.h b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/cpucycles.h new file mode 100644 index 0000000000000000000000000000000000000000..7b7b9f797bf4d11731f336e4ca5de716be436162 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/cpucycles.h @@ -0,0 +1,33 @@ +#ifndef CPUCYCLES_H +#define CPUCYCLES_H + +#include + +#ifdef USE_RDPMC /* Needs echo 2 > /sys/devices/cpu/rdpmc */ + +static inline uint64_t cpucycles(void) { + const uint32_t ecx = (1U << 30) + 1; + uint64_t result; + + __asm__ volatile ("rdpmc; shlq $32,%%rdx; orq %%rdx,%%rax" + : "=a" (result) : "c" (ecx) : "rdx"); + + return result; +} + +#else + +static inline uint64_t cpucycles(void) { + uint64_t result; + + __asm__ volatile ("rdtsc; shlq $32,%%rdx; orq %%rdx,%%rax" + : "=a" (result) : : "%rdx"); + + return result; +} + +#endif + +uint64_t cpucycles_overhead(void); + +#endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT1_expected.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT1_expected.hex new file mode 100644 index 0000000000000000000000000000000000000000..e4b16ee9b8612b96f3cb52c182c43978e678a451 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT1_expected.hex @@ -0,0 +1,3 @@ +00 +6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE008301E666F59D3EC5044DE456788FDE19EB39677B5F9FE14150DA463A706F3BAF715B95336B2D685A7CD7880713E4587BF7D857BF7E315696B8D0D9D49E142918BF0974E7F43237D4BE3AD394599E3D39BB7649932553447E5D5ACC3499930176ECD3A844A425F50D0511C9226C4B9A24F2A011CD88D32308E0312A0C87CC34A995823C65F4F0F98E50C37788CE38DC28FB8B9BFAAFA904B541EE712F6A041E0611374F6BF17EAC0BD56F3B6BF336DA9242070C2469A20C4D1616149A6159252011D299F93F986D875DD30B38A22549174570138C2BB3AA9CBEA91974F3D89BF5AE32BE9E58B854A2F8E86FF76780C03490F467DB0651C20B1DF60EB97A3C99D9BD664BE6A5E4C8A8AD4CC36390D7004E4BB421DAED654C357DA4D68498933EC71777AD64C2AE013C73EB457C68EF9A745ADEEB4FDFC879E774D03FAF6B14AAB10752E24B52D0F2D94D540A1EBE10F597E514442D6C13C2E2498E8AF3017C52DB233A90717DF25B4D072B7D88EE8731D16824C95D1FB983C449DEB466276060FEE4C7EE381451F232C29C7C3220850C61D1C3C00DB1CD9726A02A56609F3A65D3D164604588CD9B431412F1ADD914C5C2DABBC90467C0C4EA5F76E24AA618765F8B0636D7B065E1F4E6F622EAE17152458C766586772D363FA99214F472B0DB8A1E49D82D0278F2958B0AAA1586DB134BDFD2438742495007E2FE5B60E246399226947A12EA17631CAA534687CB75C060B4797EAB8277CC4F8A7A20387606EFE2DBD3E736249277D90FCAB992A8C99E85AB03EB4CAC5D88553958528AF92974718135F1D0C793EB000EA0AEC3EC1858FDD18688D1DA27278DEBF2CA8110BA4A204F7930E1C8CEECAFB73F75DDB34C5C55968A7933058426B55D039F7292AC43F64584F6DF187A1D6B003F514CC13B26C2F348195AA321DE6A27EC11348DE50D825A2964C631992E4B0B425B1BEB4F9600E3ADC4431CF2E88B4223D2DB663C3CE70EF85DDD56A9BAF138A9D7EDD894131C3A8F41A04EF9F86752B72181FABB37C86B877E61D60EED95EEFFABE6376E14ACA817C5F41961AF8A7849BAC094917B2D132276B6B3486AFF950D23D4AADC24CE98A5269E1C69917960A31EE09A527C358175CAA0CB1B018E9526D93534EADBACB52B273D735E22DD0D5C28FA3E47CFE90B5215AE24F146C3464BFEAF01D28DAA553C1E94428A104A9D78AEC762591E8879F76851CFB4648566721B0CAC1F14FE16149A9D8210CC8F2F50DEF7B46C843BE93BD8D55602493350AB560EA5BA17716423BE0EB8360AB109D8FB18BFEA040847B7335145D4F200D19CF6FE7BAC917F426C9B3D39A9CA4329818F240E7DA382761072F4A6505EA8E76C1E446FEB6625E38DDBCD3CDA81E83BF768F3E01D9D263B367303AE156C0B7183364A1E7941A09298A3ADF7BD231E6114B9DCE7952B113F78163138B9266F843F1ED97D9C2B163A6E8BD4C1AB4E179367C5AC96CECF5050FE821FDFA44E9E680B61C6018932DF717811459AF2542E2CDE77178C2E9880F011E405EAFA59C8CBBED76E5A1941104B1B9D3A60491C954755E02E894103F1F4977475E9EA36609FD67C9DE318EDA2370DCCDBB9CEF7AE6360905EC220838C9769823441CDD0DA8EF0ABE5F2D1D76E2FE08FEF53DE1D6166AB1A92B1AC093E5ABF7658C4B57287F2D1FD7B82DEDAF8D5A4FBAC4B35D58231694E162497578ABD7AA7C8FE7B3541A7F18E54E8B7F08764C5E68449DF655901549832D628FA63D2B2C5A150933994A9863317AD40D778D9D2C05C7898850B90173223C7A0AF890FD7E66221B6F06318B2ED5E199CB424885AB841E7A4726FABA2F9BB53BC3236434C35FBBE4B1A0F93F50C37896C29F8E302AD31ED3331D620E3B629455101A1F1CC7BA5E46E68ED4A8CCC87B4DC75BC0162B6330F833FBA2575DFAF5B5F28BC54FF2BA81E7A47313C15482B605E66BB38C6198F1392104080FBE78B86B1BC9A6FB881F5C7820147E6BA14B81ACCF20CAE96641094C216902EA5C125F6C935A150D7C9ACC5D9E2E5D90E38C0503AA9426017C76AAFCD5261B506274EC13A9679FB09796027A4BB759D928279B94D841A097393BF7E5BD69A496CC3DECD2B0F07F83392AADE33DC51B2A84F6A07635DC0EF57A9AD5959B6A50B7BA509AD5B11FAD26B419F9F1E3F9C7329B5A953D7CC87B2DE210611CF52A639EF2B3908012CB88E1D6F57625079CB103D6C98101A11BD2233B65602CA3049BD320520419F76B061E3598DE38152C88767D1A24FBD02BB10C38EACAE317DE6BB287B4D2CAE5DA0214965D8773778626E9B972859D8482B8D0547E4F56DFF87681D5BC5120F613FBBD91E1F14E6DEFE672E2A7EABCBBB9B11082C5E700AA0B1F7C1785FCED19A93AFE7C59FA2519BCDEB494C3D13B2125F385323B816C68F8F5628C7C2ABFD0278A337073DA74D16099698C4B114E8A8CE344E0A15D0FC7ED497B001D53D4C96DC3954D3B4B956CB9D2A272C51F1559B22904B40CC8531E40CC412C68CB6EEA4A4090B38E2797329985467E818A524D3228EACAE7825D3DAD2EAA422FDC77AED71A205DA7838D945E7FEC37E4DCA67E504CE35E5B045F56F1E8D7529EBD6F1AF7B6E939E2B7AB4027D37A5135D172DA1AF9CA2F728A6F37DE60DD23D97D11E75AB1FD51F8E9A1397E5822159DB583802B32EEBB4567ECE3746D1AE33314785643DD2A0741E7F1BF2D261F22124E8DDD08C640A48B54717517C21CD325328BC239CA028B2630D063C8CC20BE9BDB48502DADDE73FFED5963816533E020AED1208536255B1CCE985433127FF4F04D5B1E2F2108704B8B966588C0156AFC2AE192986FBEC443BAEF6CB85A6F29C7792405A24114710AE1C746444FDF5FB659E5E346826207B8C54463A0617CE17FF33E40F931FE576715C932EF29FD76B04A69B58E0303D8EF25678C8B70AF12E9045591C04E8B77106940415177E868593A09C7E14619A4B332F9ADC3A658B86017F32656C5429C115E110037A8CC7E544677D2DD239A59D54D0F3C7460EC15208346BA56DF5086C5DBCC41E0C95FCB6861C2C0C32AAF3454EFEE2FFBA214B430EF248A59B32444D8D0D3DB87C9D4B1536D157728EE7585EF532776A003A023C0AB0E9FF557108C390684D565A665063266AE6670ED53B0FAF8FF67829BB737825B153A9338CBE3DF1A462849B93A81F84ED07BE6D6240003274737F618DCB26E48252CE4204DD3139FF6876F43B305D835620FEDF79AA67433DC25287320E9917967B70B2D866D17B698BFFF2B3AB9514949E58B57C68A45412C1FC421C768BF5EE8A10C8AEF56926F51EC62C11569F31AA517868E5CAD89E958066EB9EDD7271B31CB4B1D6CE211225AEB5B57F749719DA07ECBEFE03881DDE3D81E4135F2DC81AF779776C1B8057162A6C982FBB4DA6A9AD284AB10C70022044F46D400BF6AD7182D197789983BE99227979A1334BA149D869BA1C4088123435BF978541356DAF171F33ADB1C97907A0FB5845074A85D26F546135AED0F91BE4539C12BF9411E4B556F687D069DB6B21FE2B7F321887448CEA55DB19FBB8B0482A55AEC16738D74CD265093836BE99D4FB53E9B014B037CDBFE9 +6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE003B9AC2C1422A1AE802DDD7464D3F32729A3C7DE894D506ACAD25CEB372EA3149C98780DCD1314BAA29B9B807754C47DE5DCA954064F28528B815FE27B79AC506B3AD7629D2C971AB8F282E0C6E7E5548EE0E113242B7A0E064A6DBCE30C5619B19800889A04404B50013C088C1302962124CD3B4910A352C43123119996522185202C38523440D90244A1A30224428618106291897680A200908326A44A44C4490218A16689AA8511AA52C62468D04C340D3862860A46013187084948C63C04404A92820082043162A23292D1AB12948B60921883100C53000C48CD98268E1304C6332450C328618083191980D10B8709B302264040893A48C21C9700C35715B000D143122CC98102104809B28641C308021307118335024254408178CC00848844490489830CA440009195119230C52200E4906321C154E194885132549A3000408156D20410CDA4252C1348C00316943822464946D1C81110196214B0200CA2884CC466451186A181000A4982160B06803946C94485180404692222C23446998264D1C01085202208AA6080A316193400E9CC81181322E21158484C24100227254226258069248484411270404C011928245A1C68CE33266C138725A86010CC99084340858A86080C070D026629B302A04296904108D0BB904504628504824D04805A24802C3208CA014004138214B240104B5494200000C2428124084A220449B069063C0888C14214912105416242087445010850CB564DB2441D042299A168A21B44C13B77010C085190269CC40611C4846980625601446E4226224272262242944C62D08318420322104B4610A3812D92844A40820CCA8290B21310A3429032140C1A26C8A161252A664A3B251042951C4049163B02D1444308C40660C400C01A52C09942D62C61103985019104D19A828D38640C0306554A671E0B4859B8610043669D0462918A371402249004385CB4028893666412269A42851D98029140721DA80911B26505BA0609942715088491023095A902122278E43B2700CC94CA402709240100A397002360E113041D8402D1B246DC392614C868D21B800D3242212C82112998509160C5AA22409344210A22403428CC0B28D12B66963340DCCB065A112114A3869CC148158440954A6800CA805C4388A8406019B322D831290090260A1288858104124400219344818A04D001062132250E338219A962153088051260199C4281BB97104978404052CA0C210D3428181424D61846C5A30491BC224C02028CA922D4A90100427864C962109194514822C11A69113B80403187001A2515214495A0230CB302C94102C00498609A025C2124C1B026940A444411662022528DCA22D0016425830665B8624D42448DB260C4C088501904921244154068402434A244205401448CA4484C0420C9826049CA205D1C2511301861CA150D902500C39868C0031220548D31081124805D1086962382C0A23709B4472E3486E22967014336CD8902903004963208A039125088921C0820C994032C2344E4B9869098044E4046994200999246D09A96001292DC842288A3402E408700C236E0A054964442A82C800024831CB90501C056812122CD0800C594861CBA6099CC08142B80024418A94204042144D19466218050924336AD400611248328A047293B46962C27141A68944963162304683426C00192209464D8B0649E1B070424431C180659C002411A83113212C4B46281B180D884270D1B00D90C845DAC248591426224400C2944150C804180000CBA62419021010890C18222162A881C89248D3942082067209A8900C498A41862819C5809A184D14102E2212520008120C334563C63010934C60C631DC400E98825060022AD22240E4062DDB320ECA324ED4182408C3284AC268E28040A1C86451C265CB166023094C820468D9222E1C499242242100370EC812726408250A202A58240459164C08173000460512904003072152C0641C836D9C322E11158A1035885AA08DD9804803B64C0110651086401101420AC164DB224D64B25102360D93463114B668638429C8102494300819370214824588284054A8299014126136120B098CA49828C292454C006063C481C03625CA882D244030D3A82DC9C825D2844800329250A271D3440D223460121312868C5F8620794A050E20D0E1011786240EA664F2F69BB1B7E30EC66B1A4A0BE59B79F2198AD9804483E475E53B3C49CB0CE5EF92912AF440F23B995813D11B59F798E93C9D13539817C7AC68CAD1AA1AC27656BD0C4797E9C8EC17784C1A327A9DFEAF4D6191EECDAFE049B733FE39D5EB4000936FEEFCF82928E9F94CFD5CF4C1E3DEB1433A47F6D328B5E83DD156D0182DC692347591AA6F732CFBE982935FD1846CACF4CB8515C55AB85EE5AD44CB09D3269E2E6D11780961FD131D5E6FBF89849F47F2B71D8283FF25385E52B07DBB266C674CEE3D0B5DF5A56D8BDCDCFAAEE6A248E71DB1345AFC597CA830A1A35B4396EF4C1ADF9ED01BCE9B6EB637FA24AA160B9076BAE30559F8B29DEDB3D25B79064AB0CF8B8D70ADDDEB8B174248D5AEA4D18DE43B8938CDD2ACBA5477BD4AACC3CE595E5D269FE675210D23152B04710F368428794A75F49B683ED20DD647515777955A8CB38A36AFCD2CE0ACEC4F0DFE807702D1EB3BDE72E9E085AA4E09EB1B0947413852EC3C0AC52F06CB959C85394EB3748119EDBE6C80D2D8F792CE0D915E4F4B151EFB135E7F4DC97D858141C57F70417B43A6A126956978D78EFB9F037243B4CB41DF968B7EE5B52087F05AA9FE487BD16C0347CF1335760BD2398AD54DDA00A5AAC446D80B1C7998C602192ADAFCB809D14EE328641BA3AA00F8D29C3A848ACBDC1946BC0D35E0BE0F8F7E3DA3F68D9FA9768F5CF275534A0ECA9E60FCEA38F1E042C316143A767B33ACCAD8C8D66C70C75FD1F0B2586B653AD4AF54E56EF06933EAD31DE365D110B9C4A2A98BCBA165CAFE386F887C72156EB14FF0DAD665616CE3CE65C1904F2C1747B2EC2B5C9D6776BCD79E5AC64B7933BDDEDEDDBBC725BFDBCCDE2FB375AE2BE3537BDF89BF4C25F83A49D6A6A8D0761CF39D620C53ED837D198255CF5B910A6DB57877DF92D8BB6E9C526B8C4EC93100DEE0500A210C984583E1538160EDAC2C6F866E7F5D99D7B1B81582F5D0EBBF2786E3F556013BA9B6F656EB798838EA0579201A95D56BBC3BCDB9511AFBD4D81288896F87108C077F1A81A3BD297BB124A80086890242995E03CF42A0C21E272A9AFA1DC103463D2AB494F7D017686D31894DD2F6EBB0C3CB6223EC79C65D45C1B0D4EF1961F16D653FCF25977B651EC51A13AE8D4A3472EE71969A7A936F5DBBB9396A46D97642358CAF4894C9A6DF84A59C5962A6990A76F0614890169F001870D49CF2E75008CC4A5D85E72DE2D6CF3FA71852253522FE8B0E423CB417A38EB78C8763C3720C04E67FF88979EBA09E34538BB523B99B8E34167412F77AEA894D83ACF946FC054D0AF47295E51ED83F7486940A4D41C04AD7EBEE610BF1D03FA54071D51A1509E4F49163A25081BE8790D087F5F4F05C88550FCA9BF99C9BE5953D51DD0845C93E41EEEF62E0794B2927C4F5ED9BD3E34EA9200A79DDEB4B2D8F305FE05F827C7E2ED186341CB5D1152FC80104E0E13683D941294C778417164B684A976E56E78DA4D17C3C73229314870B85C455C23B830B9A28A3D8C0B566426DC169F326ABCE2EFFF39E9B199AE5C1292B6F2EF37AF1DEA9272C8D5423DF8A5632F991E14DCA2514788B62BE164828E9ACB893DDA602A5E2FB9EFCBEFD95ABFB82D2B02D49CC53084A49AB1BEC23E5B4C8E714CB03405F1BCF7E11BB59729DDC0B7BEFB291276DCEDACAAD39A2F01C7DC98B9E065EAFED1CC8CE3E848080A2FC5B98C9F6BF5040273342F0312F8B9844594A503DD3E6AF1C9E35C1032A4A8A5E7BF33A82F35E16EDF8C60C90021D8C0BA4C386245DFEF09448431D8C00D1E26EE4D8C77DAA1A705ED4792ACB4EA27C1566FB56683C43BF67842E67534CB3F9677C8AB9D0EEE7827CDEFC223AC948B880B5F1CE9537272932002C1A4DD218F527166EBFB2B2FA2BF37246ECDFDFA72B6DA11C30D1C7D248AD64818F691D59B755DAF71BED9AB5FB52E03622A900D66B4C6384169BDF9EB61C02DF45FB76B1A26F34E938B190861745C021FA876200C7FC8E222DDBFAD8BE781B185424AAAFC65862DB132BEC6D18837A1F58A876C99E63F51420B83F459675612F7ACF80B4EB1DD0721CAA1B4970DA608679C6383E817FE16B66B19181EDFC39270C7E917B1F10EB7A011997E967853B78E00CFD58D224D933CC5A995532DCD4E532E4030515F4A05B331D575DDAC29BAB069F09AF0D173373DB1EC2B6366BB371008A2386FD88BE77F5ED5E198CBE88DF24BC6E393FEBC10C470A72D47C0F834653C9AE800E893C6BA68EA28A838FCBB69C3E964A5FAFC2067DD406B257C98DD3979EC7C7ECBE96A33D85515DA2CB6AA5E1FFF204AF62DD4119A0E48C04A3F2B38660F52964D8D4AEE146A9C53C31906DAD0FD90B5D83B3E31B690A4C4935249981BE1F1A85EC6E0FEE4C88F2D89E2969AB8CBBEB501916558D29EA7C3ECF1C9EF1A04350633B4CDA737DFB151CB5E7361173F3AEDDDF527D73F2F9D5B6213AA68F883E9A2633785EC6BE642A9FD0F21A42F6B9DAABDCD1E6ADBEF64841B59686EAE3EC88EEF0A9CBC12BC012622DF2DD93A86229044AF2F260D2183F51E833EE92D98F0251E3F85FAB74CE367B8B7AA63D3CF8C8BF4D78358BAE0A0241E210AC69353087CC7331357EB4450F9509CFE595F54032EE057754A8EDD746CB9282E768DC6B830C5B4A219343AD124EDB3BBC42505566A7038C959BC35585B6055F1968DA243F778F4E46DB462ABEB93B81243C31EB59622EDF81F06CCC61D2A6EA73E109C387915F277BCF1FC11105BBA70293C0FAB5C065F23BAA19290A302F08091107A4B1D568852622098383427760EF8F2928625BDDA5F514C5ADE959891EF2959F248A3532BF9D30E714059EBDEC958708F8A83C268BEF2682D603CA886347E198FD68233999C77D30D7455DE6BCFD0144277062B304BEF0E34C5A9D8D780D29EC2321E07340771C46360483ADCAF12D5B79FDBFE2856ACE8859F6B12414B3F7E8BB5813498960F34FDC64FC848579CAF9DCCF19B4FB825ED5716DCCCD6872CBDE3831D67384942CD8A9EC4BBFEF5706B8F9F05FE1E8FE69D3EA6A8621C22144177B1C1259E1A79DFDF89728887BEF1A70482556831B672440E13FE3E3FC8204A02EA1EFF19D95253887285BFBEA16A0F219EFBCEC30A8AE86589A5703103A8A393FA6F6B657704AC677C14CD10D3D62D13FBD378C2DDA325B61B85952D51293871E1FCDC948C77BEAE9A6F0E87CE1A8051C8F8087685C12624BDF58380ED66F55B43DDD6D362173A5BD389859C17D95ECE3AB732639FFE451CD103EE4854DB2F39614F658BAA384BC9948D0714EB48A887143E7A1FA4B690C22B492A70C612B59FFD2D6B3B5E99C2003E2C359B1E62DCB620C7A246A7B9B3246131556F2F3D513A23C6A9FD2280ED686D767CCD01754EB4C99692F2B380C36081344C1D35EE1949736B6976F4852CFBE64FABCF11B9AFB828576B4F9787AA7D03E84598A7143EF7311FAF2970E23ED4C173F985D6450165AE3E241A18234E74FF3DDB921A5300B1C4FB6E432E698F53F66E38C07BCD6E77605DF4624D579076292DE1CE6FC6F0081A38BD92D39B24B73BAC1C52BD68E9181D3DCD0AC7534DB48901E5984F9902557BFA231B2EA28C3183262A1B2221F7426EA88A5816093A5CAE2CD5D59A9390FC93A2956944B064CF013BCDB67FB423D1328D2C6D7BA329013FA2D30EFD69FDCA1A95EA6D06C7363534B2F3F7DAAFA296EAA09B3668E9CF82D9BA959B32F3CAD3C10C6EA48611554539C37DF6BCA3385EAD3FCFF96D372B42393B73C8DAAAA31506EE0527B7FB3E593DCCCA57C8FBBD4A3C7F8A53899869132FBC3E4050607BBFE29C675E3945E74A31CD531BA7AEB2E2F0CD990B8F983A90DFEA0568F0677EA9563F7C479DE968940CF242992692865CFDA89FA078BBEF49CE4575BDFB380366011C8435F12B42D9AB99AB6A31912C4354149D723101D1365A65E7CC68D82E30517773902FB38DDA2B324E7208E987ED287D092E7662A430241BFCA552D314127E38C8597A89519D4F1E62A79465AD5F4EAA3FA77CD98326D2F92CE9852055CECCF62D63CB9D7F198AE085E4D45C8E48FCFFE593AD652D9154167BF3E6195810A445AE158F1F9A6793363AFC1F22CA882FEED3A5F5727CA76477C5F23F0FC8700CDC6A5BCB2B20B4F9266351D304A96A82BF5F314AF685C1C707C92E3E847B7047D689C70B25E5501CAEC9919626F4A0FC81586AF1EC88889B423387D5D95482618A650E80B53B07CACE3228940602E3DB47466CE9BCCB6E4D8AA61C8912583E810B3B2E7E9CB48BD403ECF08D28C70AE0B620859C1F09B61131404C3D5BFFCD860E0F42AB299006230B2876D77DDA91C8C62BD93A844E4B344E3255EEA531C6C458D04ABDB0FAEF2D1C0B4C55F570A5A51023F4D4EFFF59F9ABE17922FE732CA71BCD434AD7710B84CD4AC9F2507A06826562AD7F647826F9DBBE4EDD23F124369DB8526FC2B4D52F0741415F972BEF6A935BD812A56C8221B7DEF0F5106BC01E913E3D43DB86C2BB4C7E0762663C6DE788721C2AA07F8954887E2142F2E914A099EFC0AEE1339210D3E53DA3ECF88624B1119BE34010B886C80F51D1850838F2150E72B042AF32899C0D3D7B02A57F8CF263A369562E4E945A31282A502A95EE9BB0316C6861006DAC17F936F54C4C7 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT2_expected.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT2_expected.hex new file mode 100644 index 0000000000000000000000000000000000000000..c086d81e9f88d405a9ee3854feae9d0077e0131f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT2_expected.hex @@ -0,0 +1,3 @@ +00 +4E130489218BC6CD1A9DF06B2586365F4362D8A007563DD1BF7D77F29663CB459F1B080DCCA1E39FA04CC66B9DCD4A6CDD2FDC25B96E87D778C068A41D7D4AB8FFA0E156AEF370568021A0F56EC60853AA4579F7C7151A31A7A8E5257D791D06ED11CB264B658467E82EC5EFEEB6FA224577EEB84D4453C82D821B87771FE57B10526B6B003E94F9CC812731C08A4B9FFCE90A06AD3134BDA3CF4E7E46DA7BC775B95116E96B53817CDA3FD3BC4D6F612C52BC2EEEE4153159B6D223E7A7B20EAF926C822DD064375FD26CEE2DA8DBA4665409D5A4F38BA2464D393FA00258379038331E4FCE0115988C634A95656888EB26E95049435440F42006C3515C7BCF4EBD138792B163ED11ECB45719D9B7821D6F7768B631D67DC614CF595C42FD2255252152C38190A5E41BC5868839EFD2E12DD73AFB61E8719C0ABC10679249DA931B4BBA405A46C3C112A4004A8E3A273965DB3AEBD8CA5D2BD12584160CB21369B1C5163D111DDBFC040CECDAE8B580B038B0D476211B05414A04B72AEA2FF2BE302422CA22F77CC5E4B576BDB838FBCDE65606F841030C2EBEB821619EE7C3C60C82BCBC3D55B0150A72A95EB2363121B925414138674A0619E128EC73EE4A9868D257F79F27658657CB72D9987FD03826C38DE6509F97B25144E4D0FAB4F40A3C152CCEDD908C50F8EB12E775CF512337BE1DB1AE9B320541EFC0DBC70ADC7C50494295C11D5770D6AECEAE9EEDDA468AE90800474D80B5BAA4CFDFA0A56F3C120C8A2397F31C429F915D1E748539C2A60BF05FA043E93D503FFFFD538D5B22BC0FE8498DCF20EDEBFB9FB973CB00EFFB3B65DE718292D783A16BF01301AD2EE546D48C0F44A05323EB15137C0527CB1A55775A6BE5B0F3862BD8EDDB3CD54F9AFABC42916DB1473DCDF9FB115A64F8EE011F2CA6D11528384B3757711ACA40979C23E65DF41F8D4B2D593C1351B713AF8421970D9ACD3F7E7ABFC764B8CD985159A78205F20C7A478CD987A18325F20D30C33B172E94A7C8F3B097A0627EFB6DDF787973F4B410EBF38E3215B59A4C218FCB5973A378D9A2CEE29986A61B841069BAC816147D0D8DB1BFC8E7E0FE811B589484F19FFD03890861703A27A0C9D451048C925C40C888410044F7420FC25B6B79F99E1055BE964968C354C917F3F981F7B67D1AB451E127CB50E5A1B8C3F179C3FF2175DE548D1137297555BE12489E6F3CF2831DD0E45F2E4151011DBCFB8D55AB280C0F0B5A81B492A33C674BE15221A990B800D9CD5DA9048FDB938633A3BA965398D8FF1AB77F301ADF74FB7AF818E4ECF587416D1CF1BD0F50A65D5EE7EE34E1B6388A3FFF8063B12551BE96AD882EA8D4DEBD9E7DEB05990221114784E7D1092FC01F7BEE9EABD72D3F49E572BF79C771F3E912935C2C71F61BF53EEED86D4FE1D85D702E0CD0D322A92C39935C9ECDC838242C3C97B708A40CC8311F72127FA66F6B63F640C1499F1C70AF48179629E404ABDD56518268BDF1B55F3A6A61E4836B881CFE7B64A9663402FF2DDA2997BE6A557580477ADDC419D5932324306F4BBD3E014CDD8D8FC9102D1431BD895B0809F8BF9214932E915FA0CD1A67A00DFBAC207189D9DCC0A5E1842B92233B8336F19868F29EBD31064EA8227E157942ECBB4C05D40926B4497F277394A7625DE21518C1CF3880F6E23A0A18918BC441A8E7A2E63DE4A37EC35E559FC5FB0CC0E016CC7FE06752866DFB1117B07B635663F39974FD138700545F6B64B2AE401EF894DE97FBCCD34ACBD5CA3AB9A63864E2B0B5B12306065268BF0427478CA944BCF25B2AD50BA6D6481AD0D40EADF2977F12D028421AFF4556B7C450BD8BEEBC697005FC656051E8EBEB7F288361DA5F91AED8F578DF23BB964C68107E0FD6B4C022779F84D78B31F2D152B07D1DA564D425484A0A5F223C4EDE705CAA2652179FBC9A65BA065039E2D531B80645FF9F54FB131F697FA80277B743F33588636A771CD9DDBD0511FAB5F1642A02E043AAC57618887534FBE5EFD1441028BA58D68A390A3DF8EBCBAE896170BAF3E352DB8C2857DD5EFA25E2695C157234115D136631CA96CACF71D6DAD9138B86366FF62C30064EF467ED753D8560E47EBAB157E5EFE8115907092BFC06DA6F33FF14AD29573D61EFB73651AB2B515E67E9215DDF86BC52D2DBF2A4206AEFC55411784D8A44291AC7EE56E9D124E1E69B0C5DC4E418D88D3AEEC568DC2CAB4D812B124C7CD91FA8613AB0A5CFCD6F668075DC4069AAA37DC3C7EA67C184E02B5BB33D604C983CCB9ECEE5D4B6AF74E6F44932937425B18438F3D5F358BDCA002F8E0596EF63BB934A91B0DBB69D9B3830A5CF6E1DFEC05629AEBF50F31D2EBBD9ED0894617878F1B9ED88F0F718D765CEF17A06DC288484062533681506E440A3C0E84C90119859C0978D612F0C062BE8FC5FEF3A4759C9E6193C66B56FCCFFBB6D44C713B748BD4C4A4FABB9DA38468CB4300437E5258C383EF438323F23CFC1D6C77304EAB8629A8910CDBB91C3B5C6EB81DABD2240B62E0D3C60C25554150F33387461C514A258DD2FBC1EE8E39DA5BAA6AB3E26AAD009EB78906B488E41ED03EFEDE7D7F8E67605D3C3131F4FE41C79F9C146B6BF51C56734BBE8961421DED7C16A44730093AE312563B6D98305DF2EA0527E797DCB46330690ADACA60C4A240CC42F770375EC7A49800FC573D94E168B053DE9B5B485A530BE485EE5291301D8A70F1FAAE35B49274BF0739E0E5DE495FFD791B6A3C5DB7D81BD7EBA6DD2D9E326DF27F2DC957943B5BCCCF7A616B41B2DCF2269B9AAC96CC06337FECCAD0A870F0DF3F1F1E99E45869ABD22282EE80603DACADC28288B4D3BCD5FDB39C176EE3E92592310B3A7D42B58AA477D832E113D696BDC4E2A5946410803F24203EE93C13BF380F4C84E2C62722F75851E54B0718FF23DFFC937BD3D1D2D787673E60BD218C102B572C874EE3F5971EF7F24EA5EF2A093B6813718E526806F270F7712117AD6BA1A91D1A3CA817F66B0F354BE66DA05A2EF3B9D05685C107C74E09EA8BBFDD182A1C7A6AB9191224E4BA13AF29076652B79419E11060A0BCC68EF8F97598888C12BA214AB25FFE68298A959B0CC755F00D6FF2688E20451728C51AC2FC96F53115591845AC9E330AED88A7387B5F73A136E598041F7E81BA18321A0E620F088A8A882C691E9D8F99E4C00AC849B3057069F9A5A0024E3015D613B773AEA1E1581AA57FFC246E5EAC3DA2A84A4E48B60BCFA9EC42686ED217469CDEC1912ECD07A5BAB69FE67BE98515D200022B408ACB03E2E927E3A77E4DFF29AAAE0D1DE55779FBE73FFD37FDCE0A3FEACB64DF225FA31324C3E276BCD4753A2594032FCD27256ED4F34DD2BA992C3AAEFCC89F89D9B46635321368F2DB71A3F9612BEFDB641A6B33DC3D8AA317476BC805959261426F7331DEAA84B8C6BD2142B3077BA40A9284B6DBE7D6C92DE0A99D0C1BA619946BFE2537BC7AA29BA4347AD4FF2F5EBB554E740E49744E3200B7562CAEBB9FF565990B6C79E917884F162973DA858811C0A8D2799F65AA7B3CC8AFEAB97204EAEB83EBFBC6A688E48E7FCCDFF21987AD436DF23C16E27F9715F7660884E553421292862B5CDB5A246B13E75F5677DB14EB5802441A3F01F +4E130489218BC6CD1A9DF06B2586365F4362D8A007563DD1BF7D77F29663CB45F5A174EAF47F9C8BB723ECAE888081EF19773FD058691588480FE23247C9886F403733B8A4D5923E737E3EC5A5BC019D015672BF421BDB6A830CE2F9D229B6D2275C41BB2F14A0B5632D21945070EE1653E97CC251C8CDFCF4068211CB6A24D68A1290123730C4B87141040164442E24B4251B05251A248C94166EE33450844251234085591286DC08915CB870C2326A2497109186095CB2101BB2485C445261344C591012D9286023950DC0266220C70100108413A869C2322942C62520202182948908153153166CCBA0000944501AA90412318851427254B66002222A209130182344931629C80689E1B82101426D52242C1C13855322229B22916290909244308A2861E0A4518B222813111218098100076A1921419302908824621832280C898CD434000A800C22238CC8981181046D13899048024E0386204342699C44650CC2895A882559A06812316C1127680A394648B651DC384882102DC2364A02A12C5BC02C24A50118912160A64D20219100164620400150321011A2808A360E94124C1A1525C2C88C43248CD0266109076498B401C1484E04A010620201DCB0818C066624170222151251327291800024272E2009450AB9101400668410260CA25000828198348854060E9B36321C87040093444A300DDB84899A484A1B474513805053B840A38431412429CBC248CB3646A1340E18A269C9926D48128E04183049C8448C92800A46450CA05102184D19150108B8315A060813446A5B48655494411001689A448800305012070152442CD83080C0A22581226A194500489250CB82851394484A1051C3046D89124D02922C2313400AB14CA3B4241B228AA012204C0401A144898C4271641226C8028A884600E10445C808699A00804A3001DB102618B40D0C3204DC8665D898499B140964844161862D10808510016C22000DE0A830C418044CC049923485C03671A3022103A16DE0207112A7640815208AA4044C164EA12066D98001233730C3182220460410346890B42454424444B89042C888DCC29090106D13464C98C66443048582362D620009D0962812C02C88B00C5BA805A2C8619A84694008321B87644228011BA74D081761D4228E82006A5A420E5CB86101B6055B32668800318010901BA631C0401101443010450111A728843426DC90648C306481300A1289681CB92122472E21482A242705E312401B994114808C4B40104C1681584488A24672D3021121444552425108172C4A902188120221A02841822D58224420C500E00030129844E04231D31226CA960D0B4909CC480181262613248D98182C18448CD39200A3C46888102223136423238081A22C582009DC90445A148EC93291E1463122C981A02462181384DBC285E100905A10655B262982B09180C600E0986059306D18190614276D0C24851110200429894B2288C01080A2160A48B08C62304EC0446D4114211C3392A102891C23260B1209D8340422C224D4368D041451539021E1C2608A841114132920B90D984292C4361203909093C84493009221156523257092106E14C3701AA470E146209096280B342D18078D1A373110831083102DA20470822010430860501610D1447288906DDA94245226281025000C334143A04993386624A75182082844C2300BC47121356D0A300EC24240D4024A80302591B860A3042291A08113940C883800D4B670801268620648D848064806602423509A346222433183A6210C04484130844994805838049324286300020CA485C9C05162B28499166D98108183B681C0340961B28541348044064AD8320941022D0A352C983664C288695208850AA01000A22D1C137001A50081928509838891347111222D43862CDB24728CC4645A288A1C826854B04191024003486824346D24336C5C266A8104280BA4501347911122280C4301192124503840CA20315A488A04B8509BC26421450DA1340C634072DA288224C28404006620B729E2A6258094250C4265521040C32882DA1286022586884690D9288C02403123A861C930711828688C0866C90206582088A4A445201560521832C092600A09519404042302219B0620D1C02801122D2089600AB604642051CCA42C51164C21110563C23188C20544444563144A6130888B3860A118904C3852EBFE4A5235C8D8FDACBF1F0546D7E244B119225B648A9D6F84949F1097FF2A302FFD636B8ADCA5B833657227F6432C2409C7BB078696CBF666B7BFA550E7DD1EDF40119D51EBEFA2862A773F05427480464D6279581BC7E8829DEF05EDAFEDBA3894960E2F9C2700C52EC53BA72C8467097E08805A4C23106F3559C1CCE2AA70C23DF45DEAAFA26500E17E93C2A9FA71062E3DD628EC4065F78E192CEE47AF2C01FDC3A495EF01FAAB25C9AEFE9431154CEDBCABA4D2E9793291F52F8AB834129044E3C69DA4F726CB6909DF7FFFD4B7B48C1DE143CCB63E84276CC00595C1DFDA1FF6B134DA457C2B66E893EB6561DE33F96F8426E0E2791A278286A6C5B5155AC2E3B90821828C3546E451945863C0E9E2853F7B44C296C454F991D091B65221C1324809A8F683DA113DE0FF641C9141D68B888E816602F165B46777F1157C4D6C4656A5E99BD0EE46F89047B0C4A509AB2C3BED7A175E45815C16F9065F49C7261959FA0F9CF4B6A5A5742AD6C4D768F7B7AF02E453DABE24AE382DD50458A1D20E4D9F30E98404061F927F26A5B6A677B2957FE4C973B42F2A1A9F61A7C4DBFC4FA590130EBE23E0921760EF05F25D6C7A61E2B0D636FB21537298EEB279D38FD4B85744CEE35D168590C53AC9AF082A1B0C7A46EBE5828C6B98BD89F562C1145DC5A54B4ED8F7997D0E48CF90D56B9569D3A4C4847769BA3D1ED526724ADFAB7229E5CECAB2D08E7FA9B096669D063CA3FD42D2153FEA0E703E23178233435AB81E7588C9BAE343FBFDBE77AEF158DBDCE8E1A4C3A69CDC67F3EA1D4C923118310930CD2B83BF534EBA764635D12E5FC86EBF2560D12DB4B24E4434C9135E4CB7631E0B8AD570C54584BA92B27B54A502FDF57896EEF6054D55E2B15769B53784C8D024EF9B10CF583D99CB4155BB4E3E9B2C28D382952C062F6319D26D7DCB0E946767D13B11CB870265BF829A93DE55E17AE7AC5D706CD0484E62DDE8DC2B16CFE5063EB8327460C516921C312F2C47BE9E71AF239EDC87FB8EB3F2D712609B615FA634CF9991DD10C1897654D5534A537A193741AEE36EA98D768349BE367F63E21EEC6D6A5086C7490E6F6AB0D7776CBA761A28FB5C3FB1DCBB4A5A90F6A8147C80D5254C8870725FEC69C93285A5A974917A7F3E6C7EA58416B814FDFED39AE3AB71A62B0CBB0427EA697DF596784EFD9D650990DFBFD2B5AED08AE76A243497ABAEC5591150616BBA7D7DDAE4D522067062D98FCDDEB0360C2099F13CFC66D001B18C4D1A8CAF7AB4C8F12D9E931F641AECD1F894BBBD3A62E7EC18CDC02C2580625B5334E32E565D4FD9CB7EDC25E9ED12D0DEFFE81E94F62AD696BD3F2BD17585E9E3D87AF16C9EECF24CF61F53669918666F8585A4E2BC34F6205F5DE856BFC767C4D0E2B67622416CCF8CB89A619B65D9B0D002D457C5388314DA854C4CA94EC466B97C8A55DC08C73F7FF0DA6D898B7A77062F9150E322FBE3339C62AA192DEAB57816A27EEA7C9BCA609E79AB10C88B0137811BCE51E17298487C287074A0D1FDB59813BB535AC57FA6DE8178C6CEBA4E6130063DCA5D7E256D173C11E31BC072BA6A70582B3146113DF433F93D74A2A72CF55482A1030DFA0C2C6A0AFDF5E9837D22F7CE89C9A4D81FAF4EEAC6262701B011CAABAD823B5CED6918627F66B1A07C3E5944D53E161AF56478F7598530BFAC4317BB363D4B2B04BC3D0CD938527437C2F88DAE1D447033A315EA49B2ECF62EC6BF95711A57B7B6C0AB04FD6706FC3553A7B726F30C06347F4CF35D989F57AD779DB038280BE50125B9A8AC1A2C84F9B8C7A650A3EA1533F575CA029709E943DD9E1F2ACE7757143A8CB9FBA11025D49CA9CECE240D1B63140C30CE7D0EB2311E5BD9CD7EAA3FE81E93607D14D5D329FD28FDB0E62FB87D448C3C1F85B42FAEE0DC60993EBCFA8D848903E55E2E987D34467400B8F50741EB573BB9FD41A0A5BA61EC07EBDB2675912DE28FECB52A40494245EA078A754C1B9641F4F2B6D7512944A83E8D1A70B7F3E62A13E9C456152F163BA359752A91A8F833373D6CA24EE0901657636FB2DA1E9E0C16A789ED447036002098B7D9D66EF633047792E9CB8C8CD45DA05EB5ED49377F060CB67CC33AD0D609741D0B3DF408F584D83910FDBCED95724714F4334E8C6AAFF680D5AD60C5A1402A97641DC8FA7B1531DEAFD369EFEA623F475694B04E8E5F52FAC99D8BA2D928E60C4D8AF2A68683FE7EE6D82021E35B895D57BF7F4BED6E2DE8B0D1DD0D0662068D4A9674AA65121489ABF8DEF5F2A9F1E2D36A8AAFF54C56E2E6217C7C9DB4B750207C5AA367A25401C7A3C7ADA45E1BF4E3D777D1306755FC0D69830F3BF262B83E727E5415992D6BDECD7EBC6DCE31FCB1EE0B54DDFAF20B522608870C9A0B1C9DA746DAA1E13A451FDD6192EE7E4514B8B99BAE4FA2107CEE404A7BA585FA7E1F1529E66DFC6435A1C26D3CF0CA13836F0B44E8947833F8DCD0DC2FA60C9E6303BB78E1C6E72A3615F9B3719E9F6A0D2F043DBC9AD7BFA803DA6FF03BA5B366B50EA314E42AEFAB8D2861462982115C2C7D6248EC74F7289A3151EEBD3DA0F43B89E9B5C50FBD0955DD803A3109EE451F96F5DBF1F9B42CA04724779F0FBE9D1C672F6BC478E919A07A486732817EC3741F231E9ED25715FB86EA804DC1B23BBF148E20DA21E6301EDAFF8813F5A97BD9F196E40BCCC824281F7C7F0F4A5D396BD2D3AC94A99B0BF24BD7888276A52543B0435091B4E94328164576AE7A572D2C4693DEED54F583D85C783BCD540A1240C40B68AD8DEEAA7255387029653228EC60AF145C2ECDD26A1D0B267695ACDDD490495CCC87BC1013C065357569790FC44001EFCAC9DD18BDF6EF505BF5C4FC555DCFB2A098108A1C06A3400C10248480C8B3836B26CE19BA22EE4C087C687559B6B6EFCBDA275926CF10F151DA7B2A0EC4DC214EAAAB6F93043437B32E0CE139EA665E2CBAFEBE56D6F1B98BC82FB299C381076BD1E1B0564F39FF03795794374269B3321C8E2E9BC6EE8D03084C3BF949E26B759E5A71CCBCE856FD0CE5FE7F0531178B2C80E2F913D777CDF265CA351FD1EEAF2650A2C8A52ADEFE7EFDA688556AC442D9D4EF43AFB177987831AD7ECA98C3042581F2389EBB972BB11C8D6845C8159FFFF7B2B7AD2E77F6FD4FE21E00A528F1C243D84B4793ECD4BE3F94E59B2B0435518B9BE6BD0633E310F254B822A66EAA384D7AC066C4F273254F3A2C00CFCC43C3A52FEFFB2B51CE1564A0CE3682727BBE58D9455533269FCE603C7F6872A6C07BB290C0B8AA95134D55B8D551AD77F071985EDE813578564EADA5632B9AE931EEB24D6966DC6863DD2DEAB2E3D0F4CB3AE862AFEF5B6D4C9288B1B3079C395924C67B03C415E7A8070A6839996C5BAC53E427A61A7EA100CC10F3ABF7D311845DCA174FFD06C3F05B88CD2FF32E9E44659D7E80F40EC56172C68BC5293820886BC47E8339CBBAD03383D099888E668AD95A905373D30CDDF91756C9C7C89F6DCD6E0BC9E9C4ED9A876F1568B49B6CCE9C520110BB205E307ABF68A8FEA783D1FF4BDE01F57A6B1224E9C83FBEA507BF14F77BC27BA0806D48F8A0FA1CC1DC0EEED7FEE5FCBEA5FB609D76413329F54685CEE7E4FDD309114F71F864A26F05A672315150823110947291991437C60902AE0767BBD42C57D6C97F5CCEC62207C8123E750945BA0BB444C894A98DB610ACC5703121CF8A93C7CA9CCDA90EA0938304651EB84D2534F2E67960064F81A41ACFE3560066DEDC1D7F954C01CEC3A8083975829149FFD8A54E3EAB95A076361EB7561EFAA8E678987F381F662B59A49579D9A2453AE756C133EB4460E72218696DF703DCE965AC32CD144C83819076D6D82D8B5451E0FBC384EA3A2C5675F2042F48D1D1A914B384DD0727CCFDF0A07218B3BA7BD10A55A550679C12244059D2DE9F76A4B1855733725EDB2981CF956D22223833FD43B9669BA21B38FE2C6BF49484BB4FE9E5CCD5F883E856DF05525D9E3BC452B73E6CB6DB583E3641D215019D0C48EAAC8C03D646CE537800AE96457CF187D3CD456D13AE4B657FACC6D9F78581F209E94CBD19B6768FBE0F558AB7E2D4938A0D2D92C6C8BCA7A01D7500286756E87C9A55F10BF60E23F7D6039E17CC6340445E297FBB213730455D0A7B33B852E4829D31BFE5DC6AF3CB5916176E4D125863A49592A306B9ED9CDBA4E2F40A4C8F3C85943C10BA10B688DDF847FA2212E374C64148BF6D1D856768696C6C8F04D213065A453530CA6964377687CCB2AF180ECA47260A493C8427CD418E91D38C50FA9ABF904E419A612881CD595821657C95729FDF8D1D965E80D8F8F82C6009A8BFEBA81ACF69503B873F92E557DCA50F87187BFDAE231D0164CA86E58025F51B0BCC8051D9A88313A619B87BAAF7B16EC52808CA8CF9856CB09A58B71FD67FDB4B3A0B88536DC3EE689101CC39F7F0418E3CEA104C62E83DA5631998DE88562499C4D18A98A1DEAB254C74334C325C11EDA989F98548674C19CA942AA95CEBBAC2A593BE1A1595B702B701DD42E89C8E65DFF6E104053815FE2D7D0908CC2698D2B6C26FE981025691A1680727A0D65C37B0D87EAE23CDA4E6EE98F7A981B9CF44B6B2752AD2337E02CEE156BF8968174FBF7EB0574BB62434D69EDE82D49BE6DADB3510026559B7 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT3_expected.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT3_expected.hex new file mode 100644 index 0000000000000000000000000000000000000000..d6889f3df994b1a80887b7a854672593f6b7a92b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_KAT3_expected.hex @@ -0,0 +1,3 @@ +00 +9C17C88109B6927D423D887BC2FC24A5C4405C8E736C1C9D9A799C5CC09DAC3BE947BB391590EBCFB93BC00F569874F69780502C80C4EDC87DC9378294EC3D62F584E70AA18C0F1139DAE97590D0C89CF57803A26FD82F264F2CF2A184B2DA47F44E22306B95879CB3A036C918B6166E1408E59D35E2177F6CBD05EBE6F1230FED71A3CA9CA73F3333070A1DF3FFCBBFF32F82EE2ED47285D8F05809240ED1F91873D3D817AF74CAA85BF78EF02EE9B36FF3BEADFEFC436001A219770927C1756A8FCD265721CC8CCD367C7B19A40DBA1C9DEE9611863BED506F42203AEA72EF21026307AF0602437BD5A8E7B1B1F1DED44C4A009E785BD170BC98C839753F076BF7ACFCF3DB89FACDDBE5F5CDDFF76931C0966CD935102FA75A967C67222D5F8DDF2412F0CEDFA4C9FD94C6C58F26BA4954D872229BEA543107613C71994652F9268EBF81862CE4DA0D172233D358823229618803AE54608871866DCE80B988BC82F702A8C16C9A6E58B465C39197432152297524CCB00338067CC08DA6E2AAC288AA9B3AC40493A454ACC7786D6A2F261E86F4FC6A341896C2E1B7EB46AD1E4F35D970B5B4FF1AE8F514F6C78BF27A40EC941DEC16C95D9D91F869B578BF37E5164EE77DB6D38F7E65D9E703C6323750C24C6B41BCA787AD02208421D3DB8D7090FD3D154D9561B9638BC20BD55EABDFBD0F772D590EADA34FADD191F4FCD80C4B0A9EBE8A069270B89FDC2F0C54C5E9D835951E76E4255B9AD8DEA2092E806D7C62BCD7800E175C93420D7D8E3806F2B6F325171A80C34F0EC7AE7C48CF4664BF07675B8C617FB7944795070E7B47EA9BE7509BEC0514439E9DE57E4C6A2A64303176D1BC37632DE696CA7A3785943E299A1B152AC93D1FC8EBD3A451FE780098A13A72F4EFB4A41131549038C38815687150DA19FB3DD1CB611B9196135606169090D426B33C0B267CCB630172BBBAA67ED2817227DBE6FCDE76CFEA14A17A36B034977559C9E8AA525052CBCDCB66E3410DF8D321F3992B02C3CA8FEF477F2E22ACD2B31A89D194CCFCB4C41F8FAB34128EDFF327C80022CB9E15FD41ADEEE69F227CFFD706312AEE2C824FD281D62C31C98B2306D08A39DEE41BFD1CC702E55EA718A0C265E116BE6B87678927373592B6438B7FD490B2810132579BDDCA4FBBCC0764DD245F6D4DDB97943F52A0FCD190C71744C2E6352F4D0D2121ABAB3870994E21D617A96D77C195436B291ECD15E9CD29C6E05617526FCD8F853C8CEF29CEC0549073D4AFF72CB975D3B6F4EC0BB0CEBA04E35E69E702D5E1C671424EDD6A6835E0E9FC9FCD7FF16B90B039BC1B1295F88F724AFC6DF5F70C22A6E7CD16315F5B7DBABEE28B7651EB16293E2F4998A4F4640EA6EFB4C0E8F51B7DF809CD8F53A4C18F4F4EEBDB18F3CE2DD37F12E0931A46B296158A82D6F4980ED9FC9316BFD7C519688C0C4BD22DDE4EED750EA96898481D7790B95907F3D7E9323EC42B59342A52616E288717B8DE4D5550DE95560EF33FAEB2E2A4D9641FD0630F487DB670B9490D8F91F4E2E9DDB7B6B2ED9DABAE448622DC60A5F869C96E12F1B26A77B42FD6F513E9F8C0D53BCB5610EFBAE271B754C735787E9FFC5FE8778E967D713C2C3CFBBAF59B2262F1C4B8C0499EA77CD587A5296A819955781AC371C20E66471CAE28C6B098A6D25216F5CC3F52A258EFD3E22B010DFB5971B5EB004ADEB9D34375B157EBDFD3331B6A9D56D8DADA55AC152C3AE497A36269F44F3180C47EB8C315BC3F3A0C8AA1CC062C487BD917FC3988AA468C63856277620F576CD6B70BA66D3F9377CF20452DD3E7A8890FFCF309D7E5FDE1B2ADB2BB6E96ED3E8F2CD1F075D82599B92F74602A87FE5506E25E2307FA48D0C171E61BE15E10C3EE42398D078EB42049D44B0A343915F3A99547E2E27DA86B6D0B88F9529613412FF6D6AD459F30C1BBAD521E99869F1F01EE7540407D645A7B6ABF590DBF180A85076CF838D89F0BD53CA96759CCD3F11726257FF862A565217B82068BEA4BE94215F0DB4775558FC6D97B7D4F3254A4D733E6604A003C804BD380D6046469E310AB9B07CFBB605A32DF6E1B15734F8C2580D792AE5AD45C13C37D90D893218FB7BC6A449161C0B91B2FE8197C81929EC8823942A2EA8F7C04A307249CD3295B6B529CC87041B6866E9F358B5EF30486D7CE9BB297FE73B2A0BF7FE5D4F7C56281DFF8CA46B5F1DA6A14A15EBE6F6D7DFC4327834E655CE52C310B6DD6D72A9D948A930A11FAA6E57A08A6FB873341A3F1211D0396884C07F785BF4531839AA77EEE2D5BD8D1B767602C01F6CA35FDB0F6A3967C367F88762FFF45A67A4E75C16F744B6E6FBECEDB03B346EBB18B1A35D0F2CF387277CE01F8068DC250E19F0E37FE36783C0D4FF4A1292577DE8F3E81CD769B2D22EAE286E75756ECF31E56B00A57DB2C17750909ED9959946C86E25112ACFAC5F526A331B5E49DECEDAF38EEFD5D5368A8539E49A0766C22CF5F713E6EE058E9BE157805A521FECC934987809B9C5190EBD0E709D1B2EBDB06F925F3203131171ABFE76684849C0A82EC8D66ACD60A24794BD39C18782506BC7F9F7DC6B1BC7EB2D70A3FD7AEF3DB81568C5F6513161D8DCF0B9383DD97207C186572449F7B55806FB564723729394C85291E01C5EC803D8FD2D702BD9F84BAC47E6E659A3FD90D04B4F53A01DEF302898D4EC430BEB2936C70B976355DC2A68D798EDE02F534872E369582E8B4DF771AA3FB15C2602F2487A21EE9DCA0C2ABA12ECBAB2C8B49939180C3E305336EACFDC339F502EC730B55E0FE4227415EDD151811D018FB34839DCDB684C9C8453F681916316DADB8BBB025A6B66DB0C6315C73D0654113CE37FAE29DA59A893C4C7F001DE15F0AE4B59C211EE59808021DC7CCFC2BC8B2C15214B783FC55E8C50A19ABEEC8093D82C3E12058B7023AE561384D9B28307EC60D004BE81512B0D03F02388FCC2878832C1F881251BBD73D3245336E12653445B6CD704A796A284A7A7F1F7F37DD9D22C2B2BE0D3C497E2F25CB95933D154199A32D4971965BE442C914ED7C42F28D33BBB61684AC719EA5F4D7FF7202E3D476519B3CA236A143B1DD22B34F479C0519531BBFF5E1E1D8330B231D588AEFB2BABEE0A1BED4A1D775C5BD5177A8CFDAF83E5B4CE662418D4A13FE34D3875E9EA15BAA45033CFD746673AB16FDE39F31BEF02051CFF7DC335C6B9DD8CBD17CA9B652F01AF2E3044FC3B1F15378A967F023DAB2AFC2CFA577B82DA875E1FAB014728BD7A8948859EE9619EE02DFC85859D28DAD6B8B2AA72F7973D6709D1DCB0C625084771F3EAA12D4B6D091E6E5026845F0C30FEED6BBACD4A9B5D623CA247CD6622D1E18590E5EF3FE9A094263E886E567BD1AFE24D7E263C5B2CDCF03D1FFE2DE85D7C81A7634066B30E0FF49B71234DB9441017954CB05B8BB72C11710A55041C737AD29A58B9EC6E2CD871B56976C389133F45EA4A6C39545AD15BAFD9863A333637F7AAD613BB82E61652A00BF90DB3FA1B4205198A42151DE6A3500F0A770AF589AB63C01299A28F94B9395D652866BDE7505BAD85DBB2B9D56E43D02F679F94B4F0DCDCAEC1487E18B89F96BA1F1890BCEA47E60FB0165092BA684F8381625F83C86FA90F006 +9C17C88109B6927D423D887BC2FC24A5C4405C8E736C1C9D9A799C5CC09DAC3B0AC8866103C621D3464AF8A7E67C30C8FA7F66580CDABDB9E6848E611578D0E85F99D936F0B17CDDAD87C4107D0642F26EABDDE9732CE11AE78FACD7532C2868A1A29A6B5A0CDD35F4EA2F536DEB14A7146F4E94F723B69B976F4688FE8B5D22A0B281D1426D18144D1A066403A98808390E010241D32428233764A3C220190322C8C0405A9265C8B82813B789C9089211082AE4B464D018300031644A928812A52DC2280108C58559A86111270912080D4B384621B144994268C0062999228D01A511A2C46882928C24B70D81168ECA0465D920289442329CA00924356059348EC4C46D23C52123A425CA10921441240B424E02C94C6094318C082908260440046249304A21154002180DD282294CB051211406DB2480DA08012125661B96641819125B9649C9406C180004090380CA1210D0444EC2A271D822694B2091DB8251E0A00D0C9788D044091BB020C3C04024C7251849450AC84001164D1BA96960A691C2B2288284818BB44404B90C9C4206D8063198926098846589240800098209B349A0286CA3C428C1145198222919266109A208081152E082895CC06423A641C408721126321431122231700B15868A16426480311B156E023702DB4491A130804114200A119098142519A1519814264B422C0A878DD9386402B33080B25104B785D2120D11C44864A88DE2868D1C2090CA940D0C15500A188011870513988D94A265CB164D1486418B168C88002D14C680A39069989431514866C44286A304302449048C962C0312806124456312806182098B300699A65002942D08C44124C96C000546C2B6098C0025531872CC108C13A0458482080A972554C2886342859C3049CC18929AA82013220AC0282694367049A60850C850A0B22C60B220A4388D1A128008346190366C0094700A0912C8302C41B66859B669D4C2814226699A2404542442A3245203115123234801B2001AB24843B0615806890AB66811B5641230841AB88DDB280A2437645A262164340508075200B7689B988DCA164810B9440B8490E0A41011880494184013B500440060181469540050030864C40062512030C42200C9828900496CDC96404126051B87245036495006029116449A105213A62C528224214690D4364D24014044B628D8264AD0A26C82288AD4C66920A36C49A40440068E63B405141168E0264008884419158C19C62994966110868041C43108458949B030A102851990041A166A8AB631C33085DA1672E2028E119711E128810C8388D21200CA164419C52544468D1134615C946DC0485154808C9C045153040E09380D110248D814880B88719CC60C64142812854801938DD894890284258312698BA828C2A690D4264504B57120468D21462E410241A3C0082030028B442C02264849024D530065CA24465904460A290E11A460D0A020D1140D130185D4B829494684989081DB2290D9B011C4460209182C63484E4314001CA24450B20CE0C48C09C98C8AA28011B06058C20914B9208C384CA0A49124271223112C63807102B31048866DE0882D03488C61A4895C241143282541409118286D54261191B82CD82069A4A229E4304153A20D08C1400182694A440948222D6304066434212490648006418AA40DD094690043819216649408486094715CA24D61248018B8814194200AC650E1468A4CA65192822844140D4B2006CCC84D1C3460D04069208641C4C66DDA904880A2111BB44CC4926DA1B0080C11724C204C93406111494258948920388C89982504A68813412699B6458C148060288A032402A442658AA82C1AC5412288705C882114A78C0A447241402C88180012B48C4BA8640A934CE184400A984DE13070E08404230900CA326249846400378492B08141A629C20621DB162409B74DD9A28D1A8208A3388483B60C8A824D20B48C4BC82C8100640BC4850A054E84B04CC1204C503851131305CBA210040002CCB660DAA8084AA091121121612401D016920CC950849804DC803081A465C986301803321BA1681AC904D9062C042149CB480EA11088D00802E01086D9346C22850C9B420A122948DB0089CB3088D9940891343294C8051B940420226010849114A58CD9341101355020C361A31682630231CC3881DBA809149349038948134210A304094A2688956D861BEC7549AE8CB7B5AACD88780F7B1D1597FA1BE27973CE28C4C0E9F35194AD0E2DF62E622B75E06E7E21AF5FDF3E4908FBA7D0B657FCE0A512FBF13D3C83F16CD3BE385BA075CEE26E68A28502C3C097539430E8F19916B44E53AA7742910B719CF4969D5EE2D246F5CA207AEFEB037E7CCD592094DDB72621C5937813A5B324ED4544200460F4EA7744DECC6D182A604C142D6212EB6F9F90B1AEA0F89EC07D9C083EBE1FD78D3C4C2282E1D5BA47064E8DFE71ED9A7FD7C0F95481F3CF0610CEA3FAD5C4E73789C70AF963A1DFA6DA9DF610BB98630EB4419399AFD1412E0693E33BD24381050FF62883D65150AB1DD0C67F443E5FD247412DB729D2E58453C770F934C475B89B458111DC6268F1CA0E9D143E7F0570D22AB5B7BD9446BFC7DEA9F06383FE1A0BD9E644CAF2B91AC44BFD37DEDAB4237990A3AD448715940001EA30E7219172B64D86E85C1FCA8DFA922B61819BB4BB68FFD44970FFD9CBD6BD2F09FB12E5265A5B0F919F6D4D6D06534FFE792CDF6882DA5D4557B51AAAF3A80A8CEA69E8678E66D1F47592BFF128EAAEBF38C70E8FF7AD31035DA28AF239FE245D2FDD4F853029A65399D5E6B6F4F4CA2D862B62AAEC8EFCC4B05DDCB351DFAAF1F7E7ADD9AF9FF44D2E2A384368200217F48DA0DF5013BECD2462D4BED2359FE44D9612EC6505A76071E116AB5F0F1DE88288DBE97A8B0EA32B9A6FC53695972A8F6B33542457C30C553DE91B118B15A6DB2D3F56FB0CCA91DF79741AF737E88A88A69424F7192EAFB981DF8256989189D75E0C7183E3ADA99CED3913ED35DF5AB82C8FD07D7B67DAB7EF443DF51D82FE87F8CAE103713F88E9B73F649B1D3C8589B71F06517B18502CB230EC27150C072D985A98790DBE1F83BD59421D19CC9E23D845C50CEA8515690944950809CF95FA636AB3509AFA1A7ACD2F6C346CD76362D15907764749F3E16C8BC84186E1FC9FA120F49859F7E4E6C75F7CE19C9C129C72A7CA129D10AD8EB9650DDB304F5F02FD7257DD8D71B97BD9ED47B9111236E3B706AE4800401B77E1E5A541E44DC1D686234884A5F910AAF16C8D23E593A307DA8F1180095D7A707566E9CBB125751499D748A7E1A78108B93DCFC165D2906A1DD9AAE8C5BCFCFD1D5879A8E30B6FC3EE38F470428E8455162261E7FB6F8D5BE329C0FD494492C296DC8A78128478F88BD6E1B2CBBD731ADB947300A82DE410B27C87180032AFBADEFF276BFDC0072179E36053A3F4C031FC2F94116938EF7B2A02CDED2C4C101AC0CBF0F0404BF9246F1E4B71EE2EA0569BA6478C4929DE40C56B075432203D8CD2C0EFAE663001CCB0947CA073C0301A3896793F7FDD0248F7CB4CDB184408FFA24AC8016716A7C40572731CC95DF6954A94BD2E507FCF71A8E250124E29313ACD6AED2EBBCB36ED59F102F706D5E1B79DC3D956F46997B4172C7FE20F550CFA0F1508312CAD73AAE7AC30BADFDE7D2A8B2ACEEA2FC564354276AB61A8F2D6A3CE5D43A5E6496894B66E72DA30370692421D267F04430397C3B9293F7EB11C107C2D2BB007EAB932BF25CA65D050CD061D3653BC1B25B5AFDAD7A9EA9352718CB9584615D8670CC61D7C165D778EB2766930470AC115F488C3767A6B80D987EBEA29839642720275E20602ADD280FFEF51005BE2AFFA3F69BCDC69C7C40FBDB9F8AB2C57E8745A9CA2124FFC3E088B5564C088B71847A2AA574A4251C1F5ED3F02E22A85BFB1AD2B137477439D4BAA4DAB63644A44C0CB121478A2D91E2B7B9D6CD02968EEADCB51BC5450ACAAA81EF9C1A05B475DF46C4D6603C371D6AE3A1E777A789E7205EF7AC574753F60493B81F8E0AD527A6A561F5C1723EB7E9AC1D82658C00F1CC538DD8E5552366FC9A34D0EEE1EEB9C4228C58D2D7132E3599686930BE56B9A59097B2238AC49FF4F6A9F893FBA76F511C6A6126686C0BB6CB946B0D3CF7DAFAC886BEC911564332E773C10ADFFAD490B94EC6545DF90CD12695E79936A7CE77E66C3F2781F6606874BD2E1379A8610B0BEEEF465334A455DC2887D8B35066B496856A5500AE079178EDD320A7AD2F0D350B0B3E78EA658787AD5F4CDD224340E93A06996904F9D5EA21219B871E21DD3BF7BD3BAD750048702059C86584B0E8B4EFB144503609D021C1DBD98F04C84BCE4304C834BB502CBA56A6AAFEAE643F76FBE439033D13F5FC93D8D852710C3CCA4E2507CAE51BB8779C622AE8197CAB5E51C9D11BD38BE4145CE12BFDA8F8B9ADAD8D8033D38143C92ACA69D5F72ADACB8D6BD10D427726D0F51AB7114A174E5187B8F9D114C2F4FB768EA80F74A49CCC642F5DBB7CEF2DAC669E250451CB9AD8EB2A7631E6884934E2A25FD710F3E47726D7709BC89800C6376158917026C299CDF76976624AB877136A19ECEBBBC1C36DE60EBB3CCBD43508EE6CCA750960543C16A0EA3676CAD076DC3464517FBB3B2D929AB2FA80FC0B31BF2026E4FFDBD2C20D2DBB8FA09BD88CB4B3CC124CE260BEDA345EE0232B2034AAE1E1918365878D4A0BA98CD4D7011014FF7569CDE130389A7D59E860AEF59BEB4F4D3259C1B092E68FF8AF679327F4181F6476D54D933B7EA376B1D4C0564D204CBE631C4AD3DB45F3A7CB894AB139BDEEFBAFB6EDDEF0DF6F7FD5EF140882E21CE59AC45417686DF7CA38AC90A7B44DDBE0F085CC397B3B65E6D2524CB2A6D4AE4BC69911CFE84465C9D6B697D28D84C8C28EF60ED5BC34B0EABDAE529CFF3C00F0C706584C48B565CC060A80F6DDB0DAD0799B8907E94B0C29A4E7A8D6CF0C5750DA5EB717B30341352E6046420C7A226A1935BB7F0D25E4067E30B527A55BF410B4335063ABC9BC76A5D885882AF728AD934BC7E55553B9ECA69D97311EB3CFB1DBC28891D3DBD954084E911DCBEEC1056C502385C8EDA9B4ABB93E623132084C5950FCD44725BDB70C9B9187A30DF477E128F143D870A7F02E5D2F20A3F1B034FA05475F58D98A6D8C22FFC0ED3792A1A2DDF00F62CC03CA04060BCA60EBB9CC27C2BB6636BBA116CFD03BB196D85DEEFFE0C2D6359129FE1877F723EA225FEB1E995A34B9A3A75D1E6C0786590E159CDD62B39D084AA5BD2EBC4456E694054922D4FBCBD5335F7F8448ACA08E650D296D45F3511365B5304F1359EEC32E4616C166F938F2F36C790BD577402C4A605149A4B4F8E1A101E97E22AEACFA89273B3C1824B42B0019AFE8C4ED8B7F6A265573E11AF026464BFB2C78532C0AC303EB5D36D88CC33F528E56310300D52481BBB27B7F8C523DC036B2D1A36C002B98BF5F58B4254D097DF7912D4189287A14D7AC1A30691BCB53FB9E86056852075B7278E4A50F76EBABC11761BFC5D2A86B5995B1CAAFCCE5F5B3BA2C195B692743B637E424AD4072C4B5DC6BE4A3DE4E041E72C64FFB9AF9C66353C5BB2A3967830B9CFC9AE5C632A14BB32797BCEC4A595D8761524026F13D237B165CA4240D4972287ABE72AC7F419F37E99047F17D5D9DB57C508AA0730D6D9D2049E19B1EB3C7EFEF2EE719047A777FD281A0960C09BD79443C5891AD8BCB1ED643B9A9F1E66FB5C7EC6DB926CD73DDFF4D39B15E386AD92170C4F678A7BD7FD6EFD600FE082A64AD91E2EDC675DF911B531074660096E85C66005318A3B85CF7E1C5D269C5BAE4096C9E05145C01C9A6294A50B3D4707A93254B0CDAFAB7B0ED1CA6CCB3DDC1FAA5304055C41095C503DD79F86A499F292C473C3B975DBBE53216C85D42E3E5A819E1A947639131CA18CA7831091D64FECA2713B8BA5577BB6B7FFAB6D376856A4D38856651EBF90929784436EE1F09EC9C99A2BE601294AC1C7ADBBC0EB050BC3F728D5D0F3D4831BA4DEE0E4674EBA6C2D26944029B8BBF90891C37A69DE342EC829625544A82C3FD8F61DBC40ECCC6527E06C26868B33BA362FE4E85FD8F76132E9065F6FA1DE7FC0CBB92A3306534AE9FA01256B24ECC2C63854D3F46284D0EFFEE19CE5B7998DD8DCEB38FEFEF074EF35A3748A9E44AB4F75F656FD08866DDC4F58252B25A0232180E8DB2CE8D346A558B03DD71B19D81E5B23BA688099DDAE1D10BF52932FD2EBD360E653BD4C3A254FA4B71F2859757FB024B14356BC00DD2877AF29BB57ACD812C22119F8CB62BA81C946C36B0D4CBE3A1B4810FFB27A47096108AAD74A5A0413D2A1B85286569853AC230BE9E34C78C84FE0F6269685878AA1246A55F37842584EE302301941B9A6CFB8BB4ABFBF3DAE55AD8ABF6CD6CD7B2C881DF7D5DC264A5F61584A990A8D1CCCE1C0CC05881B4358494283964EEFA16E9A47586FB9ECE3B39777DC6C1DE6931C5448C0AE2D6C51924D7F6BFBCBAF485F0F22FA2228A162C13240EB64C050F2EC800E937FA97C77E2854693A4CC83E1773EBA74CAD800F4AC6CE461C9693005BE0B3C288EF1898900466318B96AD247139E5E8D8CCCAEDD20719275E102F50F1CA019692642092CBCB21210EAE0DB708D96E50FF249E6918A628B7834BE30349EDBA515A46B0229E6E7AB1A88C25A7F6A3BDFA84EAAFCB52AA1A143FB09DF7CBF6E39FE1B813AD64FA786155C298D9483C2F9B39CF46F936AF6B95E3BA82356D7C99EDEE47CA00C3DF9A80E8DE0F246C5DE4FEB6C55B457A59CD82AFF7A60E3100D409E3EEBF2E695DD3D047CE2B35D3820AA8D4D7692C299C00B78EE7BA40DE61560CDE3FA77BE3AE68E diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input.hex new file mode 100644 index 0000000000000000000000000000000000000000..6a5f8e77304a263fb4997d758a5f0a5666f859d4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input.hex @@ -0,0 +1,2 @@ +00 +38359FBCD79582CFFE609E137EE2EFE8A8DBCBAD18BA92BB433AB4F09B49299D \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT1.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT1.hex new file mode 100644 index 0000000000000000000000000000000000000000..6a5f8e77304a263fb4997d758a5f0a5666f859d4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT1.hex @@ -0,0 +1,2 @@ +00 +38359FBCD79582CFFE609E137EE2EFE8A8DBCBAD18BA92BB433AB4F09B49299D \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT2.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT2.hex new file mode 100644 index 0000000000000000000000000000000000000000..545512733d695cc7b52ed67e6e5c0b0aa0dd0aba --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT2.hex @@ -0,0 +1,2 @@ +00 +29B4987C62218C19C77D695EB904AFFAA1BFEF6A52F138604CDAB1534E66DC10 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT3.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT3.hex new file mode 100644 index 0000000000000000000000000000000000000000..b6d9338acbe3a3ecb8057dee3ee12c2c3f288931 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_input_KAT3.hex @@ -0,0 +1,2 @@ +00 +9B54B9C91E0201251489E07D1442A42D0BF32189D0C0CA8A2D4871DB25F531FF \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_output.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_output.hex new file mode 100644 index 0000000000000000000000000000000000000000..e4b16ee9b8612b96f3cb52c182c43978e678a451 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/keygen_output.hex @@ -0,0 +1,3 @@ +00 +6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE008301E666F59D3EC5044DE456788FDE19EB39677B5F9FE14150DA463A706F3BAF715B95336B2D685A7CD7880713E4587BF7D857BF7E315696B8D0D9D49E142918BF0974E7F43237D4BE3AD394599E3D39BB7649932553447E5D5ACC3499930176ECD3A844A425F50D0511C9226C4B9A24F2A011CD88D32308E0312A0C87CC34A995823C65F4F0F98E50C37788CE38DC28FB8B9BFAAFA904B541EE712F6A041E0611374F6BF17EAC0BD56F3B6BF336DA9242070C2469A20C4D1616149A6159252011D299F93F986D875DD30B38A22549174570138C2BB3AA9CBEA91974F3D89BF5AE32BE9E58B854A2F8E86FF76780C03490F467DB0651C20B1DF60EB97A3C99D9BD664BE6A5E4C8A8AD4CC36390D7004E4BB421DAED654C357DA4D68498933EC71777AD64C2AE013C73EB457C68EF9A745ADEEB4FDFC879E774D03FAF6B14AAB10752E24B52D0F2D94D540A1EBE10F597E514442D6C13C2E2498E8AF3017C52DB233A90717DF25B4D072B7D88EE8731D16824C95D1FB983C449DEB466276060FEE4C7EE381451F232C29C7C3220850C61D1C3C00DB1CD9726A02A56609F3A65D3D164604588CD9B431412F1ADD914C5C2DABBC90467C0C4EA5F76E24AA618765F8B0636D7B065E1F4E6F622EAE17152458C766586772D363FA99214F472B0DB8A1E49D82D0278F2958B0AAA1586DB134BDFD2438742495007E2FE5B60E246399226947A12EA17631CAA534687CB75C060B4797EAB8277CC4F8A7A20387606EFE2DBD3E736249277D90FCAB992A8C99E85AB03EB4CAC5D88553958528AF92974718135F1D0C793EB000EA0AEC3EC1858FDD18688D1DA27278DEBF2CA8110BA4A204F7930E1C8CEECAFB73F75DDB34C5C55968A7933058426B55D039F7292AC43F64584F6DF187A1D6B003F514CC13B26C2F348195AA321DE6A27EC11348DE50D825A2964C631992E4B0B425B1BEB4F9600E3ADC4431CF2E88B4223D2DB663C3CE70EF85DDD56A9BAF138A9D7EDD894131C3A8F41A04EF9F86752B72181FABB37C86B877E61D60EED95EEFFABE6376E14ACA817C5F41961AF8A7849BAC094917B2D132276B6B3486AFF950D23D4AADC24CE98A5269E1C69917960A31EE09A527C358175CAA0CB1B018E9526D93534EADBACB52B273D735E22DD0D5C28FA3E47CFE90B5215AE24F146C3464BFEAF01D28DAA553C1E94428A104A9D78AEC762591E8879F76851CFB4648566721B0CAC1F14FE16149A9D8210CC8F2F50DEF7B46C843BE93BD8D55602493350AB560EA5BA17716423BE0EB8360AB109D8FB18BFEA040847B7335145D4F200D19CF6FE7BAC917F426C9B3D39A9CA4329818F240E7DA382761072F4A6505EA8E76C1E446FEB6625E38DDBCD3CDA81E83BF768F3E01D9D263B367303AE156C0B7183364A1E7941A09298A3ADF7BD231E6114B9DCE7952B113F78163138B9266F843F1ED97D9C2B163A6E8BD4C1AB4E179367C5AC96CECF5050FE821FDFA44E9E680B61C6018932DF717811459AF2542E2CDE77178C2E9880F011E405EAFA59C8CBBED76E5A1941104B1B9D3A60491C954755E02E894103F1F4977475E9EA36609FD67C9DE318EDA2370DCCDBB9CEF7AE6360905EC220838C9769823441CDD0DA8EF0ABE5F2D1D76E2FE08FEF53DE1D6166AB1A92B1AC093E5ABF7658C4B57287F2D1FD7B82DEDAF8D5A4FBAC4B35D58231694E162497578ABD7AA7C8FE7B3541A7F18E54E8B7F08764C5E68449DF655901549832D628FA63D2B2C5A150933994A9863317AD40D778D9D2C05C7898850B90173223C7A0AF890FD7E66221B6F06318B2ED5E199CB424885AB841E7A4726FABA2F9BB53BC3236434C35FBBE4B1A0F93F50C37896C29F8E302AD31ED3331D620E3B629455101A1F1CC7BA5E46E68ED4A8CCC87B4DC75BC0162B6330F833FBA2575DFAF5B5F28BC54FF2BA81E7A47313C15482B605E66BB38C6198F1392104080FBE78B86B1BC9A6FB881F5C7820147E6BA14B81ACCF20CAE96641094C216902EA5C125F6C935A150D7C9ACC5D9E2E5D90E38C0503AA9426017C76AAFCD5261B506274EC13A9679FB09796027A4BB759D928279B94D841A097393BF7E5BD69A496CC3DECD2B0F07F83392AADE33DC51B2A84F6A07635DC0EF57A9AD5959B6A50B7BA509AD5B11FAD26B419F9F1E3F9C7329B5A953D7CC87B2DE210611CF52A639EF2B3908012CB88E1D6F57625079CB103D6C98101A11BD2233B65602CA3049BD320520419F76B061E3598DE38152C88767D1A24FBD02BB10C38EACAE317DE6BB287B4D2CAE5DA0214965D8773778626E9B972859D8482B8D0547E4F56DFF87681D5BC5120F613FBBD91E1F14E6DEFE672E2A7EABCBBB9B11082C5E700AA0B1F7C1785FCED19A93AFE7C59FA2519BCDEB494C3D13B2125F385323B816C68F8F5628C7C2ABFD0278A337073DA74D16099698C4B114E8A8CE344E0A15D0FC7ED497B001D53D4C96DC3954D3B4B956CB9D2A272C51F1559B22904B40CC8531E40CC412C68CB6EEA4A4090B38E2797329985467E818A524D3228EACAE7825D3DAD2EAA422FDC77AED71A205DA7838D945E7FEC37E4DCA67E504CE35E5B045F56F1E8D7529EBD6F1AF7B6E939E2B7AB4027D37A5135D172DA1AF9CA2F728A6F37DE60DD23D97D11E75AB1FD51F8E9A1397E5822159DB583802B32EEBB4567ECE3746D1AE33314785643DD2A0741E7F1BF2D261F22124E8DDD08C640A48B54717517C21CD325328BC239CA028B2630D063C8CC20BE9BDB48502DADDE73FFED5963816533E020AED1208536255B1CCE985433127FF4F04D5B1E2F2108704B8B966588C0156AFC2AE192986FBEC443BAEF6CB85A6F29C7792405A24114710AE1C746444FDF5FB659E5E346826207B8C54463A0617CE17FF33E40F931FE576715C932EF29FD76B04A69B58E0303D8EF25678C8B70AF12E9045591C04E8B77106940415177E868593A09C7E14619A4B332F9ADC3A658B86017F32656C5429C115E110037A8CC7E544677D2DD239A59D54D0F3C7460EC15208346BA56DF5086C5DBCC41E0C95FCB6861C2C0C32AAF3454EFEE2FFBA214B430EF248A59B32444D8D0D3DB87C9D4B1536D157728EE7585EF532776A003A023C0AB0E9FF557108C390684D565A665063266AE6670ED53B0FAF8FF67829BB737825B153A9338CBE3DF1A462849B93A81F84ED07BE6D6240003274737F618DCB26E48252CE4204DD3139FF6876F43B305D835620FEDF79AA67433DC25287320E9917967B70B2D866D17B698BFFF2B3AB9514949E58B57C68A45412C1FC421C768BF5EE8A10C8AEF56926F51EC62C11569F31AA517868E5CAD89E958066EB9EDD7271B31CB4B1D6CE211225AEB5B57F749719DA07ECBEFE03881DDE3D81E4135F2DC81AF779776C1B8057162A6C982FBB4DA6A9AD284AB10C70022044F46D400BF6AD7182D197789983BE99227979A1334BA149D869BA1C4088123435BF978541356DAF171F33ADB1C97907A0FB5845074A85D26F546135AED0F91BE4539C12BF9411E4B556F687D069DB6B21FE2B7F321887448CEA55DB19FBB8B0482A55AEC16738D74CD265093836BE99D4FB53E9B014B037CDBFE9 +6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE003B9AC2C1422A1AE802DDD7464D3F32729A3C7DE894D506ACAD25CEB372EA3149C98780DCD1314BAA29B9B807754C47DE5DCA954064F28528B815FE27B79AC506B3AD7629D2C971AB8F282E0C6E7E5548EE0E113242B7A0E064A6DBCE30C5619B19800889A04404B50013C088C1302962124CD3B4910A352C43123119996522185202C38523440D90244A1A30224428618106291897680A200908326A44A44C4490218A16689AA8511AA52C62468D04C340D3862860A46013187084948C63C04404A92820082043162A23292D1AB12948B60921883100C53000C48CD98268E1304C6332450C328618083191980D10B8709B302264040893A48C21C9700C35715B000D143122CC98102104809B28641C308021307118335024254408178CC00848844490489830CA440009195119230C52200E4906321C154E194885132549A3000408156D20410CDA4252C1348C00316943822464946D1C81110196214B0200CA2884CC466451186A181000A4982160B06803946C94485180404692222C23446998264D1C01085202208AA6080A316193400E9CC81181322E21158484C24100227254226258069248484411270404C011928245A1C68CE33266C138725A86010CC99084340858A86080C070D026629B302A04296904108D0BB904504628504824D04805A24802C3208CA014004138214B240104B5494200000C2428124084A220449B069063C0888C14214912105416242087445010850CB564DB2441D042299A168A21B44C13B77010C085190269CC40611C4846980625601446E4226224272262242944C62D08318420322104B4610A3812D92844A40820CCA8290B21310A3429032140C1A26C8A161252A664A3B251042951C4049163B02D1444308C40660C400C01A52C09942D62C61103985019104D19A828D38640C0306554A671E0B4859B8610043669D0462918A371402249004385CB4028893666412269A42851D98029140721DA80911B26505BA0609942715088491023095A902122278E43B2700CC94CA402709240100A397002360E113041D8402D1B246DC392614C868D21B800D3242212C82112998509160C5AA22409344210A22403428CC0B28D12B66963340DCCB065A112114A3869CC148158440954A6800CA805C4388A8406019B322D831290090260A1288858104124400219344818A04D001062132250E338219A962153088051260199C4281BB97104978404052CA0C210D3428181424D61846C5A30491BC224C02028CA922D4A90100427864C962109194514822C11A69113B80403187001A2515214495A0230CB302C94102C00498609A025C2124C1B026940A444411662022528DCA22D0016425830665B8624D42448DB260C4C088501904921244154068402434A244205401448CA4484C0420C9826049CA205D1C2511301861CA150D902500C39868C0031220548D31081124805D1086962382C0A23709B4472E3486E22967014336CD8902903004963208A039125088921C0820C994032C2344E4B9869098044E4046994200999246D09A96001292DC842288A3402E408700C236E0A054964442A82C800024831CB90501C056812122CD0800C594861CBA6099CC08142B80024418A94204042144D19466218050924336AD400611248328A047293B46962C27141A68944963162304683426C00192209464D8B0649E1B070424431C180659C002411A83113212C4B46281B180D884270D1B00D90C845DAC248591426224400C2944150C804180000CBA62419021010890C18222162A881C89248D3942082067209A8900C498A41862819C5809A184D14102E2212520008120C334563C63010934C60C631DC400E98825060022AD22240E4062DDB320ECA324ED4182408C3284AC268E28040A1C86451C265CB166023094C820468D9222E1C499242242100370EC812726408250A202A58240459164C08173000460512904003072152C0641C836D9C322E11158A1035885AA08DD9804803B64C0110651086401101420AC164DB224D64B25102360D93463114B668638429C8102494300819370214824588284054A8299014126136120B098CA49828C292454C006063C481C03625CA882D244030D3A82DC9C825D2844800329250A271D3440D223460121312868C5F8620794A050E20D0E1011786240EA664F2F69BB1B7E30EC66B1A4A0BE59B79F2198AD9804483E475E53B3C49CB0CE5EF92912AF440F23B995813D11B59F798E93C9D13539817C7AC68CAD1AA1AC27656BD0C4797E9C8EC17784C1A327A9DFEAF4D6191EECDAFE049B733FE39D5EB4000936FEEFCF82928E9F94CFD5CF4C1E3DEB1433A47F6D328B5E83DD156D0182DC692347591AA6F732CFBE982935FD1846CACF4CB8515C55AB85EE5AD44CB09D3269E2E6D11780961FD131D5E6FBF89849F47F2B71D8283FF25385E52B07DBB266C674CEE3D0B5DF5A56D8BDCDCFAAEE6A248E71DB1345AFC597CA830A1A35B4396EF4C1ADF9ED01BCE9B6EB637FA24AA160B9076BAE30559F8B29DEDB3D25B79064AB0CF8B8D70ADDDEB8B174248D5AEA4D18DE43B8938CDD2ACBA5477BD4AACC3CE595E5D269FE675210D23152B04710F368428794A75F49B683ED20DD647515777955A8CB38A36AFCD2CE0ACEC4F0DFE807702D1EB3BDE72E9E085AA4E09EB1B0947413852EC3C0AC52F06CB959C85394EB3748119EDBE6C80D2D8F792CE0D915E4F4B151EFB135E7F4DC97D858141C57F70417B43A6A126956978D78EFB9F037243B4CB41DF968B7EE5B52087F05AA9FE487BD16C0347CF1335760BD2398AD54DDA00A5AAC446D80B1C7998C602192ADAFCB809D14EE328641BA3AA00F8D29C3A848ACBDC1946BC0D35E0BE0F8F7E3DA3F68D9FA9768F5CF275534A0ECA9E60FCEA38F1E042C316143A767B33ACCAD8C8D66C70C75FD1F0B2586B653AD4AF54E56EF06933EAD31DE365D110B9C4A2A98BCBA165CAFE386F887C72156EB14FF0DAD665616CE3CE65C1904F2C1747B2EC2B5C9D6776BCD79E5AC64B7933BDDEDEDDBBC725BFDBCCDE2FB375AE2BE3537BDF89BF4C25F83A49D6A6A8D0761CF39D620C53ED837D198255CF5B910A6DB57877DF92D8BB6E9C526B8C4EC93100DEE0500A210C984583E1538160EDAC2C6F866E7F5D99D7B1B81582F5D0EBBF2786E3F556013BA9B6F656EB798838EA0579201A95D56BBC3BCDB9511AFBD4D81288896F87108C077F1A81A3BD297BB124A80086890242995E03CF42A0C21E272A9AFA1DC103463D2AB494F7D017686D31894DD2F6EBB0C3CB6223EC79C65D45C1B0D4EF1961F16D653FCF25977B651EC51A13AE8D4A3472EE71969A7A936F5DBBB9396A46D97642358CAF4894C9A6DF84A59C5962A6990A76F0614890169F001870D49CF2E75008CC4A5D85E72DE2D6CF3FA71852253522FE8B0E423CB417A38EB78C8763C3720C04E67FF88979EBA09E34538BB523B99B8E34167412F77AEA894D83ACF946FC054D0AF47295E51ED83F7486940A4D41C04AD7EBEE610BF1D03FA54071D51A1509E4F49163A25081BE8790D087F5F4F05C88550FCA9BF99C9BE5953D51DD0845C93E41EEEF62E0794B2927C4F5ED9BD3E34EA9200A79DDEB4B2D8F305FE05F827C7E2ED186341CB5D1152FC80104E0E13683D941294C778417164B684A976E56E78DA4D17C3C73229314870B85C455C23B830B9A28A3D8C0B566426DC169F326ABCE2EFFF39E9B199AE5C1292B6F2EF37AF1DEA9272C8D5423DF8A5632F991E14DCA2514788B62BE164828E9ACB893DDA602A5E2FB9EFCBEFD95ABFB82D2B02D49CC53084A49AB1BEC23E5B4C8E714CB03405F1BCF7E11BB59729DDC0B7BEFB291276DCEDACAAD39A2F01C7DC98B9E065EAFED1CC8CE3E848080A2FC5B98C9F6BF5040273342F0312F8B9844594A503DD3E6AF1C9E35C1032A4A8A5E7BF33A82F35E16EDF8C60C90021D8C0BA4C386245DFEF09448431D8C00D1E26EE4D8C77DAA1A705ED4792ACB4EA27C1566FB56683C43BF67842E67534CB3F9677C8AB9D0EEE7827CDEFC223AC948B880B5F1CE9537272932002C1A4DD218F527166EBFB2B2FA2BF37246ECDFDFA72B6DA11C30D1C7D248AD64818F691D59B755DAF71BED9AB5FB52E03622A900D66B4C6384169BDF9EB61C02DF45FB76B1A26F34E938B190861745C021FA876200C7FC8E222DDBFAD8BE781B185424AAAFC65862DB132BEC6D18837A1F58A876C99E63F51420B83F459675612F7ACF80B4EB1DD0721CAA1B4970DA608679C6383E817FE16B66B19181EDFC39270C7E917B1F10EB7A011997E967853B78E00CFD58D224D933CC5A995532DCD4E532E4030515F4A05B331D575DDAC29BAB069F09AF0D173373DB1EC2B6366BB371008A2386FD88BE77F5ED5E198CBE88DF24BC6E393FEBC10C470A72D47C0F834653C9AE800E893C6BA68EA28A838FCBB69C3E964A5FAFC2067DD406B257C98DD3979EC7C7ECBE96A33D85515DA2CB6AA5E1FFF204AF62DD4119A0E48C04A3F2B38660F52964D8D4AEE146A9C53C31906DAD0FD90B5D83B3E31B690A4C4935249981BE1F1A85EC6E0FEE4C88F2D89E2969AB8CBBEB501916558D29EA7C3ECF1C9EF1A04350633B4CDA737DFB151CB5E7361173F3AEDDDF527D73F2F9D5B6213AA68F883E9A2633785EC6BE642A9FD0F21A42F6B9DAABDCD1E6ADBEF64841B59686EAE3EC88EEF0A9CBC12BC012622DF2DD93A86229044AF2F260D2183F51E833EE92D98F0251E3F85FAB74CE367B8B7AA63D3CF8C8BF4D78358BAE0A0241E210AC69353087CC7331357EB4450F9509CFE595F54032EE057754A8EDD746CB9282E768DC6B830C5B4A219343AD124EDB3BBC42505566A7038C959BC35585B6055F1968DA243F778F4E46DB462ABEB93B81243C31EB59622EDF81F06CCC61D2A6EA73E109C387915F277BCF1FC11105BBA70293C0FAB5C065F23BAA19290A302F08091107A4B1D568852622098383427760EF8F2928625BDDA5F514C5ADE959891EF2959F248A3532BF9D30E714059EBDEC958708F8A83C268BEF2682D603CA886347E198FD68233999C77D30D7455DE6BCFD0144277062B304BEF0E34C5A9D8D780D29EC2321E07340771C46360483ADCAF12D5B79FDBFE2856ACE8859F6B12414B3F7E8BB5813498960F34FDC64FC848579CAF9DCCF19B4FB825ED5716DCCCD6872CBDE3831D67384942CD8A9EC4BBFEF5706B8F9F05FE1E8FE69D3EA6A8621C22144177B1C1259E1A79DFDF89728887BEF1A70482556831B672440E13FE3E3FC8204A02EA1EFF19D95253887285BFBEA16A0F219EFBCEC30A8AE86589A5703103A8A393FA6F6B657704AC677C14CD10D3D62D13FBD378C2DDA325B61B85952D51293871E1FCDC948C77BEAE9A6F0E87CE1A8051C8F8087685C12624BDF58380ED66F55B43DDD6D362173A5BD389859C17D95ECE3AB732639FFE451CD103EE4854DB2F39614F658BAA384BC9948D0714EB48A887143E7A1FA4B690C22B492A70C612B59FFD2D6B3B5E99C2003E2C359B1E62DCB620C7A246A7B9B3246131556F2F3D513A23C6A9FD2280ED686D767CCD01754EB4C99692F2B380C36081344C1D35EE1949736B6976F4852CFBE64FABCF11B9AFB828576B4F9787AA7D03E84598A7143EF7311FAF2970E23ED4C173F985D6450165AE3E241A18234E74FF3DDB921A5300B1C4FB6E432E698F53F66E38C07BCD6E77605DF4624D579076292DE1CE6FC6F0081A38BD92D39B24B73BAC1C52BD68E9181D3DCD0AC7534DB48901E5984F9902557BFA231B2EA28C3183262A1B2221F7426EA88A5816093A5CAE2CD5D59A9390FC93A2956944B064CF013BCDB67FB423D1328D2C6D7BA329013FA2D30EFD69FDCA1A95EA6D06C7363534B2F3F7DAAFA296EAA09B3668E9CF82D9BA959B32F3CAD3C10C6EA48611554539C37DF6BCA3385EAD3FCFF96D372B42393B73C8DAAAA31506EE0527B7FB3E593DCCCA57C8FBBD4A3C7F8A53899869132FBC3E4050607BBFE29C675E3945E74A31CD531BA7AEB2E2F0CD990B8F983A90DFEA0568F0677EA9563F7C479DE968940CF242992692865CFDA89FA078BBEF49CE4575BDFB380366011C8435F12B42D9AB99AB6A31912C4354149D723101D1365A65E7CC68D82E30517773902FB38DDA2B324E7208E987ED287D092E7662A430241BFCA552D314127E38C8597A89519D4F1E62A79465AD5F4EAA3FA77CD98326D2F92CE9852055CECCF62D63CB9D7F198AE085E4D45C8E48FCFFE593AD652D9154167BF3E6195810A445AE158F1F9A6793363AFC1F22CA882FEED3A5F5727CA76477C5F23F0FC8700CDC6A5BCB2B20B4F9266351D304A96A82BF5F314AF685C1C707C92E3E847B7047D689C70B25E5501CAEC9919626F4A0FC81586AF1EC88889B423387D5D95482618A650E80B53B07CACE3228940602E3DB47466CE9BCCB6E4D8AA61C8912583E810B3B2E7E9CB48BD403ECF08D28C70AE0B620859C1F09B61131404C3D5BFFCD860E0F42AB299006230B2876D77DDA91C8C62BD93A844E4B344E3255EEA531C6C458D04ABDB0FAEF2D1C0B4C55F570A5A51023F4D4EFFF59F9ABE17922FE732CA71BCD434AD7710B84CD4AC9F2507A06826562AD7F647826F9DBBE4EDD23F124369DB8526FC2B4D52F0741415F972BEF6A935BD812A56C8221B7DEF0F5106BC01E913E3D43DB86C2BB4C7E0762663C6DE788721C2AA07F8954887E2142F2E914A099EFC0AEE1339210D3E53DA3ECF88624B1119BE34010B886C80F51D1850838F2150E72B042AF32899C0D3D7B02A57F8CF263A369562E4E945A31282A502A95EE9BB0316C6861006DAC17F936F54C4C7 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT1_expected.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT1_expected.hex new file mode 100644 index 0000000000000000000000000000000000000000..ad88af0b917ae790bcbffc0d3c89f05c9e08a62f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT1_expected.hex @@ -0,0 +1,3 @@ +01 +00002FB9 +6AE10E0133138AE0D51C77B5667D4C9180E04D0935EB5F282E696BBE794C8B96EB6A21A232C9366518132BD8EDFA9AC38142BB9CDCBA77C729BC4D1127A13933DCD44630D3CC6D1CF0242355A0DE121D15D7D4618F501E509C4E0BA296BC956571AF19BA6C8C2A75110DB6ABC3E7C682E87EB280DC29066E5D45C5D318DC3F14396AD3EE29A772117429E28A7B423B54470508A48D67CB6395190855A0D92B30E71B34CF7F508658E7268A27E2545E6B79E48F7C69ACCB09DCABF5BC5CCDB8CA8CA8CAA2F2869773349C666583702F3BDF94C40204514DA2B43A91443B119EDB0B421100AA587CAF238A87F916281435AA6FBF00BF16AA7BAD080D60B35C53792C438CA39A4BDC72BD7CEFCCFD877F82AD557B176DD5C28E78563D1DE719EBEA1099718B0F4129A493C11CBB2378F989D18A97074A2E0F3338CCB9A8A36C1B3749E7A99E7A765C70E5D60386C71BD4CAB64BFDB815509166D5F55CB4A380C8CF24E6BBF61AF3FE7BA3529D84B11FCD6BA6E18B87121857B00A737B0F3D9665720C38BB54C09C8D3917C5AD646E3D01359724534BC1910AD174761D64AE6F796900655E0B13AA3EF2282DFDCFBFA5B0F6585D33455D7D86DC6BDD252B040B66EC6A03FDFB4C06E54C734145817A20C42E408E7571FFB9D6D258E585D5904BCD45D16CA6E44FDE9A25E06CD3645A302EF8F3589D897181450C178E4DA1663F2F5960B4755A0107CE43A265E6EB0C9C267929CFB1A93ED1881798E9B8A1D91CAC83E63537FE0182D022548B60CF0BA47B6A7F90CBE86E1E5D39101C0D2FB333A82E2E99E9E0C1AD46DF3FE876D144FCD3B1D78424C6C5CF0F6E0BCB447A6E9CC337481F5C14D4FB74D764FB38B8EAA511951A50F41A4CE248E13E4694704A0554853A0AAB9405E2C274A4FCF8B5928667DE041E668B17AC577173B0F4CE34363A7C2AC9C3E0A45A39A46F0248BF3D45DBA806A230DB1DC7B0BEE80EC18BA8F042BD6FEE173177FC0194124AEB21BB06FA079A1BC80758B347E4B129D69EC6E8416BD89062BACE16F2288076469237231B6FF4902FEAC3BA7D884DB747DA6371E792827017778E43708A421931115EAAD9E4CA316814904009F1CCD36763FC63038641BBC4F6F93235E16884F8A12F8D71621354B0AE4A9EED64DC5462917D4B35370AD9EC8057ECBE3A6221FE8C39B11444D4BFC380F1F4D5AD18091059AA5089E109181247DE78DFC231401A3D517E9DB655EBB914385BAC1B2888E3837FDB08A9E7AEC206406B848D045593BB837DFC41DC283CAA753D8CB64CEDA3041B2330BAEBA2F1450F646BE15E0B2A46578B1F54A73FA4DE57FA1D632F3FD410C0E8B17C11E197B7A17C522EAC6FBB78001DF9F96CC5F6116635D404AB454BF4450D536250B80E813C8F397E038590011C66C5164E05FBDE695482185F02C4B6B566BF3FA564E9232F40594AF96C96CAEF18CBEABB292BA546EED3A1AEC1476A8418B25DCE79F12D7B4F89303688539815E05F96BEB3B1818472C7E4DA7435652DEB5FA4277F2A810831F88098899FE2EEE35C1B0E6F74DF159D0631C5683C2D7B86390BCECC534CF69F3AF74FEE59EAB25B634333470A55CC49C28C7252B1CF4C293EF500589805FBE5CC056573A10F188A02D050AA34289A21D8B7D587C0A288114E47F346DA3772FCAC58CBAC669DA616C9976C56D87CC275AD463F2131DF95460A151123C964B01A2B908AEEEB7DB3E2FE12EBA46321D7A3FCAEBDEA0FE11B78605E3C8390486CA5D484E6C413847BCD8C6BA1B00BD2322BE537B173647BB63BEF929223C6AEA687F8ABCC4A8B81C44F0FE24588D2C40BF76590AF7157E2E4409804A28AFD25E36275C34A976D22213D457C162ED9274BF52E20842ABC94B2A1D6A4A3F9C2AC544060974DD687C2BB96AFDF8C27522C0C438E7E0DD4DAD7AD640A4B3ECF50CB6250C0A97FDDF15D8865421E490F84650144AC489AE7920C4941895D7B2F1911513E428127562F9446BB706FC06F07BC6C9922987A970D4FC21937BC09F072BEB132BDF8014281BE75BBE6F8C74E337EABAA16A064EBC956C188787CB34A83D5698438AD22CD4FC80781AA1B66E5A2AE0180B50B77FBC07EB6EA60246DAB074494CC9381F6011C2ECE64F97B2F5CDA92FE91B5533518A7DAC9828FB33ED428890A7FEBD0906095094576CFBA1048665782B07194839CB86719DC91EE8C2F64D4576605C2B55804299F314DE8571D0C58C78F071FE810B2FDCD3D7AF0C635303B6ED0774637B1E563855D54D2A1B0FEB5CBF84E693E512F59A13A20E5FBDB77510E3356CF211DB09CB471DD1043D9940DC1BB6A26CEFFCA03F48BABE03C15226EF29E0DEAB6108BDDEE6462884F8708E79709775AFFB39303D78BC51C8B9EAB5D91A56F8BD1518708EF243AED01A637F525E25F297E0FEDE03F3136EF23C4B33DC1D256CC92E3B6AE64C368542AAF553B1605C94C255012D605D1291098D1F0B855D137BE49D198CDD3EBA0A9D9E7519B8A5BFB4DC3F338219CEA7C97251166B5004CEEC23606421A8F9248359E5346594080FAD04EEC15C56FAC9D55EAF4C399B1FC8D68501B88002212FC0E36DCAF5016371696AEE5EBE4396C36137C535B13F09D490564D38D1E0FFDF13902F7678FD06EBF8E34E81BF712D918348728BE21965F5956EC8AB1F5A8D8276E6A72B4A69FB7C5AF658C5DEE4C8BE285ABAFFE0EF41529AD44B31EA310C3665F2EE61B5817C1191549DA070A2BD4BC790E283BF81C11EA05A6E4652823EB3FA05283E784C4143F4C029A6A7D485A1B892F7462CC26B1879B4668D133DCF6B9827D3A91E069B25DFC72EF00FBD6FBEE4970E26222D81874C748C746DC5564732CABCD0FD99983034E4F5523A43831ACC1E6F3989FDE186D4BD07E15CEECD8E68375A5EC130AD93C0837A27F5EC5810F6C87CFD8E37BE6117496F7C283AEA1DD30A5FE5AF6F8A94867A5A7B336B4070B1B5539608BE8D10BF765F6984FB2D0AF376A7DD4E5E25922078782B77C4E5D5E086669D265C6306CB40BA5755E6D83D93D33C89F548FABB20DABFE7086B9E658F4A8BC22C11C8A12A106C534EAEA38F46FFC84C2A4D96C5DFC31F6F21B3FA32F988FB86A38D7103ACBCE69C5D143C33D1186C1FCA80A13C642487D5B221DC76556249EC81E42AD4DFF51EF86F2ABC45274AACE72A79A7B985412A3E94C92CB824E3B54F328FD2F06B49DB12338284DCCB5E03D063CAB73B939FB59A569E4E693E53B446279281BEF3637B55FA1C77DB77A389F43CA7E00B8711B32F98C9FFB2FA30D66075DA836CB528CDAF3FCF65B6EE3C0355E05A46DD0DF6B3D71E8C705B6C14514A537627FFCAF805F8545A86865D9EC83B243BDD4A444D6E09A7F26F5C30D824C39C65E1596BD506F70E793CD5E703159736F7A7C1B1A08A88E348FE12D0D74A190EE4C8CF1E2FF44B9FF40A28DB611296835E251E8451068C1016A3EDA063242D1DF3DDADE57998C1FCBF7B9F988392916D4D405F82ED894AD693FEB4206E1131911E3617F5A5325701D01AACD591469026E10585C1A73ABDE7ECA706C97F48B125A8E101E55D0262334750AB98A8C4D33F98763684402C16BC7BEDF35AC349AB471E3EEFF92A79AE0F11F3CF17EA1406FB6DB669537CC0E46F0A7C42695C4595FA2F0E604F048357125EEB01AE824FFB63B70F10DA410EB93933398C13B485493E4DD5AC42744B00D2F81BDB3C7030C3DEA36BDA258AD26D4540D1FB83C7E651E31C0A2F7D06A328820D85321B24E4B798153885D80111D17811D5ABB97C69B24E3E82B44649CB8C5E828A3D532DC8EF2C317890BCDEB43571EEFD97780E68E03C1F751F5EB823D75965ED7714397112774934F465F61C25271F1AB2EE80BAAF7049D1E0C78EB59BBC3594202F002E883B7B579B98D0D4865ED783AA0ADC84A4A37E73C3CFDB5F464812AEFC6081EF899B5F4C9F903279E77D39B2DD0939329B3C5060990BF8E0BBA6CCFB6F7BECA77F48585F44F8CE7293D121335939E3AD785BC66AB2C9DC955941EE85DB9D2A4F404B3F45C7A68452E6AD108530A1FAB8E35C9EB0AC7F647DABE0E0D50358A007DB71B6D76B9922797F9CC377D675E70D9E166B750FF457A5D3D649153C81CC1B659ECF3656BD864FDDB3C430AD6FE44B21DF23D0827D56899D8F0544472298FF1E12FDA44466822409222063A8BC27A2C2DF44B1C4F56C47062E7D717705967F8C10E0F1A35B0C4F1EDB14B4E3A2ED44163651179FAADB643E602F2C92DC144FD96871AD3CD194BC83951F18C77B92518F8F3013BCBB49E57A4338FDCEE5000EFB89A3DC2177ABEB2DC34C094476A8844CF072A17FECC8E87F8C3D85B776972CDD5EA7F8ED6DF4A123197F78150A2E9CF2E3CF88617E82FBA29410168DC261EF9516AD01187ABA8E189D59DE5E243CB019E5B7C34F5BD158B5E11E9D7BC75BDFC71B040EBFAEEAEFB7639355AD3BDD27AB9DD799BEDFA24D2AC5566DE15F46CF601E08A702B133D391B0E236951AAB4BBA409C5B8C49EA0D1E2DD2EB9D6EC67F76D12571C002C1E3448FDFD0FD6D5C070E6B749E9C3E6A86DE347E34A72DD2B19C51F405B8A4F4DC04E7A7F3E0BFCB51EDD253EBCF47171E0F57E7DC04C0B1ED1054D06B7DD2E8E6FBEDBB16D086E1975676B0B3D34F3D290495051DD8EDB5C6FD727C8A460668FA7EDDBAA5AC776727EC2A155770B5C98297C45F192C5817C0942C62FD9FF9BBB5085F7B197AAF21173E1B2313FD94DAEFE9B76E068E8D6A46F25D6E81E09F34D0337F22086EB2F32D4917A6B5D685E3FB94D919BD8D513BAADC61643AFCFF3B1DDAE63FD0562C3F60228C951217142269183F4D9BF65F438D86739219161F9C6AEE0F65244E85758C0BF3B137B30536129FF7557E5C52F05AF64883FEDD419DF69DD8B9C9EA6D4A6B018CF676E91855B58B37120D84D3ED06C7173BC3BFC65FA01CA02A01E2893FEFC9E0E708506C84698BE652909F0F9793C443635A032CDEC61C5ABBC097997A62BF2894133BC991A19567C9F4549B30EF4C081FE2FC52724CEA974DC6CDCD4042D3118AFFA2A7EBAB82ACB14BE405FD6A764C8405CCCD0D1BE12410855BDF950747EB26E948C7FADFD2089D26824F7100FE574815B487865090CA8D8307D27276C8C5FE813A22636672026C72B81290AE9917FDD5A314029D02BC37EA1C39B592EECD57883952907C4A2A4203CFD6498C19328E55500BA395947B0CE523836ADD259F92C358026CA86169D73D17044AF5F4B7EB42348764488FFEB8D34237F17BA80D5AEE6F5DB8977898B2BEB745B065FC20DC567CB4090D65D82003B466C21921FCC13C6291CEF5B18E6F6F77B8E07FE9F803F40EB4A015A76E18C03B40CBB8C8095AAD7AE64B52D6A1AAA31EE00C5E4EBD04597377DFF1037A0B12D2585E8C2FF784659F3A57CEF7732CFE93DC4A7F11E5124273A656CA234AAA7503246EE53F430A79A0F9ADA4B6C0A5AD6DF6054883339C013FAA1B6BE863DADD11B5443B5E4686C5CA6CC2BC43415A116D2B908F8949FB594A470B2D6017FAD537F066B8F2BF20AD2F376B33633F90BCB9D262EB23B399E8CC8D7632E17B49C4792B2217BBC020635CE2ABE63B1039463C7D069B2B004D0CB650CB917311A049B97560768EC46A793F19FEC3ECBF9493AE80D16FE24F00953348E522E28B2668FE430454AAAD914C385490786CA7D98E6A1CB345ACD0A67A6B57A175D8A51C2B51F8763861B027D29181655D5548E2B15986DD3835404A9A282DE523A045E5DF42FF092144ED9392D589DE70678FBDCACCE10C956AE96987A266AD001EE70422549F7F27BD92748CC06E7D24483CE0B83C3F2067D522E789D849250E7F7588A2DB9BA9D5F439D9369F04CE59A12474CB5FDFB08C2AD9E0889CB0F2056A7170428778D3BEC8F9084072D6C0FAA922400D8239119E44BD7266A43C55A70CFE0984F60A482D08F9E77426AA875AB50748161B48390A43DFF04534054C2A2D5E4A84C804C03128A0D7134BD3AB8E0A2BC7753F458A38B9B244FB654F9DA3C2784CCE6958DE3DC806DDDD84A8D2AA24A8382AF4D11E52E1F47733FF61B79895A9AA426BD060B4761EE687F1134A23EEC3EA828134C4B8108A6C5B9E3AE6913E955299DFBCE6488FE32036662FFB0CD451A98D97A1538F5BC34D527ACB9CE6D1DFB5862FA889422FF32319E35AB53102E566C710D4884BC3357280112F2C694D957D26BD3372D99CDFD00CF55098238994610D18A247BBA60650EC3AD7FCDB208B15C4AFD35A25735844D66A929037EAE673D66159185E4B2B79B48746BD9F046BA5828595CC6820EB8A860EC9C458E7AB183489C3ADA179C40A386B1F33F2D41C8B1AA5D571D1E7088B0ED0372C95824E870D63A4B95D87222C121766B270A3F5523BB6B69284B676C81F20D0F37418FB0B40240414E95B7CCD6E110658CC41F343F4F56BAD2D31A495D6BB2E9141E374AA7B2B8EFFA3E41434B4C4E6385BD0000000000000000000000000000000000060D161A2228313A diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT2_expected.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT2_expected.hex new file mode 100644 index 0000000000000000000000000000000000000000..7bceb1bb3073efba2533852eb93f1bf59efd0410 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT2_expected.hex @@ -0,0 +1,3 @@ +01 +00002F89 +58BC36248443BED9F1FA12DD93EF6FE7D89828D96315A0FBEF047B5D57BE38BF2BBAE0DF7E983151E879479E00046AB12BA8354A6F51F9C286B83560DF391BB7B1B2A495FF27E582D3D09412950CE565F2A800D18454C0C17181153091B57657ADD3EF44C97FDD8DE557FA590474BF804E569EB7FBC36357710A307F3D540F3457FF382730910BC41C20402449A0CBC5A93B5FF47DDA2D39E59DD58A862079FD60B24E8FD43BF8750AF3A463FF810E43CC4E84D9B54B716C8EDC3B00BFC0A8FA7210E30DC6FA7B8668078782643404736A7FCE53A870491E3CF91C38A9E761426FFE7ACA6D1DE13BA213273E899DDEBD4E0BAB8CA084525DBEAC382D0155421B800A1AA921BC4EA1990E19CE090696E081AF1D4145B5C6DAC1277FBC483500B80F1CFCF40F49F48D2D86531E98EB3D14D1F54E435E976F0C123B14A4D8111927C2B425A43316FB10F9DE9BAEC23D49F7CF37D2369ED11FC3801E84C981472DED8DA4D1AACE2F6F4050EB94A483F79F2551CE179B31D753072D02642873DFBE5C7E61C9FD32701C10847C6AC35F41A2DBD695DACE401814743B88C579BA7B188CC878150C71CB5C8AC5763A805801FDFE267D812F65FF31D958B857C41B06A738646E93AD2D9D0AD0E1678697C494FBB76CBD41FA63719A3331A96A4840F0DC65F890F7F81BE3D22CE8500CDA8E3AE5A6482DDFD749F363882353D2EE9BE0784BDA8BB2AE75A011869108FC9736E6E6B08D9F6F42DD42F4C06A561C5E8B585ECAFAC49BE7B17299BBFB4B74398D8A300C6447108FAEF5DB463454010217F01AE45F0282D4A3B9EAF23FE092EB750EC081D6EC0329A9A537A5C270C31B1499983A7C293EF72F0A4FD91CDBEA3F029DFB35FEA766C475A07BB4EB7297A9592A20E3FB15119F5A7A9E658D18C4EEB3E35963C122A1397456DCAC9DE8EC08DF9873C751A10E189B9C8DB3F63721910E930397C4CDE3D475AA7E5C56FA2B139690C20418DC40F9AC14BC29B419A45ADAD66AE2790EE4CF0233EFEF06E75CDCAD7A594BD9D64F0A030EAB8FD2C77B3AFC4E4737FB5682FEA678FFD75A794DA8E2A0348088A48D1321C9828E0CBE6F15A746DF22248B360F51B501A9BEDA1F7263D5BEE948C72C9ED854EEB7DB56E5885F6892BDBE019B8FFA9CA30DB9D1C82D3E13AFF7D75B0D0A713FCD4934B559A80F4F32062BC4883CBFE4B4F905B8B8E639A203D69AB8CF33B61A3092B38F03683EC64605DB4585C1E30021294BCC7C98D8DFD80940E82E65DDE8621A38638D6EFFA26E19CC215FDD0A305E6BD731ABA1CD14BD397ECD52BBE7CE7D84F88323A4C2D709D28333BF97DF22D24BF792EDE7B5F5DD1FCBEB169B625E36D2DFA95539188CE7B7BAD539C2BE1BA1971648478468AA3413DD6076A213EDDD1AB0FA85076B6D91DBFC858F1F935EF31DA87A24E3171B30AF8F03E8DF50A1781FAB6E3775E5D14B3025492B4E0309228AD41B68B278ADAD656EF83B0F8B1ED030835255A4A07C94A35D27B256AEC0381C35E640C1565A80D55D8905C7DD3BB69801DD362AFA95EE532714BAA8FF701E8F8F30A6165DFDF4FF260C6DE1135E66DAAA7EA771FDB07E07F818E4B2F7334850789F8FD0E385B23641F0D8A7C754A60B35A76389F5920A4DBC0E890A7207827F2B6368CA95241DB5C6664397D5A294FE3CADE660D80F69F0458171684A997B68E6CAD05417DC192638F9275DC093FBD4A72925DF8FBFC7B6777CD28F13658B4D3745DBBC82C88E42A16C31766A9ACBD13DE946054131FBCFF70677F2FE91078D9593F12423A3ACCCA5761830297971F6AD925455B9313683F01541B53543808D1E8C6ACBFB93D3B4C715880545B77AD0E7F1CFD6A3426815BCCE1F3E7EC720BA259046B06803110F12508B33D7C04C567BCB2069DAD995C590A2560C766185D7F2A186AD1B336A1A5BE702F6691F90978F1EB6F3403E00A2464F19AC7C76D2490CCAE4C0D117DB7543BDC73E6DCCC6AEE86D74984FBE575C10E6AAAC0028D61BBDD001BBA9186065A7BD1E7A8C13CDABB33F6F2FD03BE5E950793212CEAF82829142E7BC7E97CCC4F774892456870B23A1D6CBC5E1D2B797219AA1D4AEB332F2B38DC3B230E0EEDD600935523D9C05D7C750B485F32DF4BDD932676E6FA4A7AF63E12AA149AFA49ACE37B03DBEDFD502B97B36238DCB412E5D9C6AD0E8209119DD9BC5C22ACFB7FF53827CD2CBF259DA76D48CDC11C452FFE69D73354BA70D9CF566872011AB6D06D027C9B1DD93B97963F964B33F8F4FE51EE4E1F4436E5B3AA240320BF3CC6FE63B219553F6923A134D843C9B49F913525B4FDBB87F5F3235461E8DEBE849449BBDED39DE58BABF6BC66DCEA2115AED2582504E5FE394B9C2C346C5251E9F058C6447526CB3786A8A66E86747129EEBEA89F6F27AADACC5A97D6D9EDAF5533218C46BE6C8A108F8723F78576133FEEF95920D3B92CFA38B2547CC48B97087EC163FF9C244343F51683E8B1B7D29968A81423EB1346DDF5C4E638D796C8FFFFF6C482E47227327FB87885F52EA0840B06252E5DE252577838D869B074E6D0FEF4811866467B82121967283C2E47FF209D9E3860FC43681E0AFF54E6418443D5B3F769ADE3EF026F7E96762E1018326A0CBBAEF233996322E495DCC06693729D7C744ED8B7780161EE1277AD7C9C4B40481869AC463653E1E7F7F60AA5C352BF1F1A9CE483446F13DC6A26239A6D784B9F44DE97299ADB3CDCE3896081A7C93445C45D9ADDA1ED9FDC49E63202FA99D02B240C46DB1DABFD69AA70822333264064184BD583FC949B5134902767D003E6ED1D05581C1D6AA5AFD9A119B15F745E835CFC832011829AD48530C7C51AD17785B06748230985E77E2A2C4AC40313EF394052AF472A74044B8542261BE57136759FFCB1F42F349A464066BB4FF963D9517D4D82181B1851654B73203B16E302E7F7875067D2198E33F819270183ABC0AACAD3ADF227AA20314979F296AAE763E9934F15A6544FC5CAEBE33B6D51897ED5DD4094B377C51C931E9E62E5C05F340507C82C4E2788DC84E6B719F0C1A729AAECB019946C9DA7920DD20A7E7DF89EBA8BDC8E8EC1B03FE6ACC18E855C02408FE1EBEDB17066DBCFFDD0B1948FA53A45AB7A892C071EE692454D94453E2D5E8DC33E7B6C304154D3843C6FFACDCE3358F8D845546E2DE5C1E9641646702E6CB83AE5CBB07B35E9CD28DEE1C6CC88D8A614F262681FE0AC38B86AA792CFD0509A76928FE196ECA25D9A8A231A1DC659CB37C2D7EB3B7702443D879D6725FC633D503841F43B4EA7AE7155074B4DE876E2918339CC2BECA755F757183748F1E9FAB045C3F22DD5DC2EB5752A4EAF055F64F9BA6B3AA65EABEA3F585B72D712E40FD2B9BBF5F62ED5E9343D613A59A81B8D4172ED8837137DD07FB77C3D1B2095B9686F9ECB15E37C6C1B19267A5C0D299A1DDF368559F615733F451532554D0250D52E4C56242FDDCF6DF7F4C5E0F372B04AD24248687BF21243FFE82ADBF602204E9281C2BB4F47D5E3233A6CB0FAC7854BF4B298EAADD9242C085856126A1806D7B063C38D2D6F13CC617D22626BCDA228ACA22B798C0BBAD8D3BE108DBCF6ACAA304EC51C78BF2D06CFEFCF9B279B7677F78AE5055F77E0C8BDB8DEC635290D154F59E13DD6E45CB81BAA882A54B26D2447C8DCE935FD0A9E5EE20136C3FC643ADCD342EB901DD8A0C9A652DE28E552A73182616FD7AD0F662A465EC1D947A0442F5583811B7A921FE210DB41614A01B880C0F811BD74325967CB5361235E92C6941B4E5EFEBD38DB1F22A084C2AB64308BA1E47AA7223962DD65E7152C840AEF3B0607827B6E99F6037FFF6749A9B871ACD998F719A222F8ECFF7B060F586CA9CDD6D9ACF769DB558352F7ACA2A2CD8BCBD91915835D96F0B1770A88097C234D5D46AB064D9AC7B3A387280C9C8A16FC561A7585F6FAC747FA4091BDEB5AF963E9AC134B948FBFB32805C80FC5DA7798061D0B26CC8675E2FAD9AE52DB944FDCBCA68870B29E270D9D51A113B064FC6273CD3F86AB72CF31B20F0B72E1B964A2B2E42CB71129481AE61536DCD409B431E2859BCFA5734A47A05F149FF91181F081846D376730E4D492250DF165A2B542B39781977E96802A4AC38F450AB89EB87BC19E5F8C323F29F13394228C985DFE60A185728ED95DD62D764EDEB4F46C6D5F24EC9B105075ABECFD0A27A24D52DD0826B18F89BBFB55C27A42496F5408D283376C20807922609616B07425B4E180CC6E33BAE22186AC37E3775A6786BB6E930B928CD682632D687A2915094F520D76CD439DD125B3DE7295C5C3D1D1367C49954CD0B2B944F5CAC8CF765F39BA61B89B007CDB7D46ED1AF4ABB6E219C67534DF7AD50C422A0A34B2204633E4763A386E7235DA77CF46CD2388062028FF8832FFC74A4612886B0AE4554BFE6D82E604978101B413B5AB9478FF79B39F49ECC91FBB639DAC7A72B97B7693DC8647FB472AAB87CC9B28C0CC91AD51C557ADDB3B6D864903B98793C0E80AFE5F02A2FAD2CEDB1486BE609832DFD285D92E67D46FE19AE445F4FFD7C166EDDEA185666FCF0B4B9F75D169B440056DEF1E376B0F6166FBE07BFFB1925B69A2E85C25C7737F9FB48B87E7F66D2E1432E12BBC585E3D4E6C5ABD5E65326A67D1C944C67DCFBCBB0A017666187E71D2B1CAEDE13DB5A4576F2F0606E892B7C57296B95B009CB92137729786672E11E66CDAF1081E167B0AA0BE018711C8CF7D285359B6961CD04F79F95559801D1DFFD3AD1E712AACB0C121BAD5604C9A5B95782BFDE6F1A2DFC110579197D1C6E6686AF1CF312B95621C6B72B4A57CF8B1FC47B773EAC6392B6CE10F6ED1D9A0C2827A0B12D058FE72F99EEEE750CD4D41BD4A3D95B1B7880535F78E4942A7D83D3E2FB8C1892DAA7971E4A0092CEFC9786D69D689AD31D7AAEAD2CEFEA23E0CE14305BC745A472AE0782DD31F8F5484EB129696950B2CD00A8F401C19441FCD6A16BB2AC5A9AB36DE2B75EDFB5BFFEC0AFB37886F415D79DAFA24350BD01FE8B0824FBE6FDBF6B34DF81F0A75B5F5F87D94011014AE543B1B7F5C1F7BA542BC3F4B134E1D9EA6345339F4606D132998969FDE118BB0F305F2753D1D63EA33465199C5D04D2ED4889C19E180B68D2C5CAE8511F9C69A6539B1BC24EE28DA9C9C87D7C46887D01740262F7F2E76447C5CED2C8E23A43CF9B5A9EF603C14BF4FBF4578A1A316029B0C036D085EA7AC855516CFBC6F658923D54AD182AA66F6FC62812C49E0A209F5FCD343B1BEED407C74BD4499024DC312918B45FDDB307A8DCACE261D070F84CD26458B62D7F3E9BDCDF3946384AC7AA1C32A34A218EF6C9FF835FAE4508485D2A3F4E9C94425A5B3FF0422EC098A34CFF4583C722389ECCDED9ACC397D53985F362DBD0DD401CF830E206BC956439BAA66981F2EF63C30F9426A389CF72F144DB8FC4F7A245A7DE66F1594629FCBDD6CBF44CCAA2C4E3D45C0137F99CC69E08FF6BA2E835DEA3D9DAE61DB48E684BBAC10562B6587193DEB0E6980EAC9877A5F954E1AF915D02C8C394483DF6C8AC9840DEF57D7885E0A38E14E9D3B85EAFC94BBEC68BDF2CFE33C08CB3CB7A8530E8759D27EFE663724FAD3F23F6CB10655C0AED09BFFA78FB3C671770A2A9B928C4DA2B0852836730C1874F7A027C861A805DDCE2CA765D091ECDB3CDA874165B5B0B87A6D6B64A73A47DAC6B255AE65BBF445E1633440FFC2882D487CD30D5BE629A4DC58DF086A4C62116A64AD799E34BBC46CDE85EB71E7A7B279B6E50A13EFFB00EE7E86FB19541596D7CE82F028A26DD5C9D0D807F686492E0DD3FCEA572A1D1E544EF62C282A904803CC2C7B2CC0FF7804FA14060A1B7D8E06A61F5DC2FA43179286B4DA6EEB8065C3D6397E6CE850562DA4E614A44BF81C3442D00AC3AEBF682D5B1A9625BA462556CBDBE75CE951C3FA91F83105887C24AE3EB3ECCD05B4BF4D6C910A718C6BAAF44BE750CD008C2591638CCBA780807D02BC462B9A16967D2A5A927FD75AE048591B5CB40B3DF6F092469BB30B2939CE425A190847B904B631E08323B88E11958BC5C6FE6F97DEC18B7EB94D14089F9EFDECA3D20958780998A7DE03881BD99B7315465BE6CEDABA61F0D3935694D1FB6610E00BAD93E96ABFFBE51F653FAFD2353F3ECA0A65FE4CF7D5583A19D99CCA53C11A5E8E5450A2383C7222880062C1315D81C705F85ACCFED53B9E46DD9CC544F588BB7C7594E4EA2B7720984C23347BAEE26C015C065F732ADB6B71C772FF539D9AB8458917BFCD3D8B8F6F9A495A942DD429A91DB1BBBAA2CBFF201086B14B8104D6CD77655510EC4EB8C995B95B1939BD0602A893F631499C81B0DCF7D02293A839483BB697E7AB5B364B8A386D481648557206AF32F4C96DD05232B37536793BBCAD81B515E6E7D92B8C0173A5D8186DB189BAEE053B0DD4B4F678FDAEEFF14295C719EEAF1FE00000000000000000000000000000000000000000000000000040E161C20232A32 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT3_expected.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT3_expected.hex new file mode 100644 index 0000000000000000000000000000000000000000..5f6ff8a07e96dd5da6454187d9b031017a031cec --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_KAT3_expected.hex @@ -0,0 +1,3 @@ +01 +00002ED0 +3F1A9B8C87C0A08481C482D90D252CBC687B25E613C6BDC311BED7FC59BCABBE5353E8094DF52017277C5EEF17A07D65A7DE47EC40E127A745EBCABE4E77AC5781ECE95BBEEDCAA01914F00B98F04A6147222843A4F9A4F4CA0DBB5C26B530DE04D304FEF6AA5F3EB1789858760CBCCD9AFECBC45E02EC93827149960F8EC0867CE9D2F2E46F6DD8AF4F959DDF9DF7177BFCD67C43CEBC559037CC88772567E6279CF261CDB891631CA68FC3B88F7A5EE03C964810E29943607F890FCD81F4AC0554EC8FD304741DAC4A0F156B66DDCDCC7D12BD563B2D54411891CA94CD44F6EB127A7BB3C0FC51A06597639C97FA4787D4C819817A8100D9463FE92ABC339426B7C57670962575B37934E890F6924F95CAF81E62D42821B1B4E669320B4DFDFD8D213C1CA405F9540D3AF7776A3265A717468685F0F3A08A22E60517C6DAADED6AD1365D90E7D91DFC8F0415810C7F98406CF0C24A583B13531B52F3F492969B198B4AFDDA5340F059D21E8F5A830E1DE4DA51E17BEBFE8BA1E3B9F6C5222BFE154516C1C1143B96A49E04DD99F56F047E781FE925171D83B3755DAD89C361CE5D4A11A7E9C37C245BC6B3315723EB2DD15DF385A108C719EBE636ECB6529D6B9D4817EB011FD6127270831A097ECDA206519842148B029A1505849118CA06FD01FCFE100B1644C44379AE47442DABC2BAE7F342ED79B26379D50C0E61A809EEF8B7EEED4B403407B44FDB7E683EE3F85881BB715266F87A96E6E3DC1FBAC1715D1581CC3691729979E97D577D8691A9AB21769AB550C258A15F4A432EDC1E18669999051A7594950EE013D95E269973762E66808BE560D9765A104D4351F118653BE7F425D0FA9D3581724604028FA8A4D35C6AE687DCC0B55C915D75E5C590366713AB78A2AEA5C1515F36651F85B2997D6027C8AD330D914F3DBDA26A1ECBD1A34125342A32B5F432ED6E8EAD0E1BC5796108F5784CAE34A3207973A13044699B496753D7CD4420A8F45D71017C2439B773771229633E08E076F1AE5092ABBE3461DE11AAFAF154587342D3CBF56939B19DEDBF0A612FD3880A5B6D2EC518BE04D81B9F183250D9EB3949EF4B7A7EEDC4021B1A4DE20AF1B5A1633A26F3D1789C1DB42F379E4E16F1C87922B095B5751F8FCD4E9415438AC7F546B1BC000927A06A4BDDD18AD62B2E829C5C2E464F178D1FD9CFFE82083FE84CD61F5AF373D10B0DD30B151BECDD8FAAB9E185EAAAD459EC55E905B56417F5AFA8024B6D5B971D3F070F5CD513E85712B171D7DAAD6A47351279D4D204E33D6479BF0747F7F895117DC9EEB22552CE829DB8AB67A44E035748BF41C5663A17A1AC141DEEA02C990858508C62BB05D8ABB8825713C954C509B67D7A56259172F25E3EDFF8EB356A818233DE470F543152FC9AB0C0F2530FAF9B1B0CE6BAFCE2FAA46DDC76FC90F6B658DAC93263CDDA34294269AFD2826B2BB6F71E1608A6232D3CDD09BD5201FC7589AF0059ECF3F0EE167289A6C7EF1F414532BC981AF7D44B1F8787C4446D9619505B11E6F60C0C861C66291952A054DFCCBCFBB0DD75C9A74B0CCB3C0AEDA3A6D1C1C1DE0E494FF26133CE52A64B397A7DCD547F88F4F327750039B2EC77AD56E4D1A793A539C0EECF501B8E8186CC5AE6DC5CCF0A14964D2CF1BB83A974780972B2AF75545B9266DB1B3E2F052E15758086BEDFC5CD42DFB3E1F2DF6DE49D9CDFCC990174F52C66993AB07E66B2658C9B430E92838E38ACDD02CB9302756EEC3CFD74D92B0D89C90281A93ED479B7A37AF9D37A47F8E04B5B261669083F97062DE23B6C52EDFEF09CCF65B8F32920E5586BDEC1634009D42EF43640C26CE938B2BB5A5E459B74ADCBACC76A2BF7712509553DBC30F9D73EFA20F95B225808F22101CF4A068D6E1C1C64EC656EE535C57785296755F757722E897A53264E63A0311A13C6E47120C3850992EC703E98AB8029B6E29EA7246882D9083989C093382551663C570012FD42DD97EB86FC434D359B85716D0084844D185A1FE8AF8C90F17510F0E1264EEF6709A2C0E9A840F49C6E7E2984241DE2A50DB152AA9D43CAC0E7C6707B55BA44D18F36E2F5F89BA46A5C1E195E0860CF5B3CFB1C4C71A0A53AA1A1A83DE888D8EB9CF7354B361EBC37DAD4F9D0F96CDD62D108DA793BBC84761C5F29F24910D736C8C9A70DD467DFCB46A53F880414CD2634C2E8AC379F2C29F52167894B6E9BB41636F93653FE4371555E061B711442BFF93D04E0AC20D7B4E92A23D1BC77387A7679C688436D34CF37132FE336FE29B57F8D792BCC76C9B4F2CF048A2C8F9B3AD2EBAD9DFEF954A55978078AD5DD59189C25411717BA0C59AD2C89C7D58C6758019B3A134EC32B8DD5A7C90DEF509DF31AC9DA19BF136DC49CC8518CBC0B193D2A8D7681A1A8A6E1B4FD96896CEB085374A81C082C3EA606C4113C85E78C7C72945EB436497E5DEF79340B64DF13AC56123980C2B4985AB0F3DC4F1AEC2CBCD47B4693AB4DBDBB270F5FA2B7BC4A69D77B96164DBD43055A930FE97296034718569D3DD151CE0440B94FE8A2656195AB1082BA64881CCB1B196BFFD86584BECC610F9751DD29B0985BAB0DDC4D0583C2A12BAADE088C6A021A437989BAC7B72709340B4BB12E6FB9BACEC05EBEADE26AEA86ABFC225121672F2687B08E8C6CD87C744C62F65AEAD52EF3063F8492CC7DB1FEF69CFA96532001430BF131064FE5B2EF71BD65FB69F2E1187B34EF659AC499FA178B969E49F494A9FE3D0B3DF5BBBEA9E852D4A9587815E199474DCD774F5A1A4922E9F403EF9A56D79BF8D20BFBD3D3296757A29EE30F3A8DAB3CD909E8A50A775EE2BF33D136DF4234E7D44A2F5A4B8EEC945C6BAE494D35D24BA70122CD9071F3F7B3B217BB4B0C1035301D4BDFA7FCABED5E223CFA7C5420376B53EB97FE945BAC67CE84DA6E9E3A6BF44DCF46B5FB35957A30E922793FC47FB59AEE2808BA559D422208180F437108128C741F181E3ED84742A122F30B420CE3063016D0B8B8EE07293DF269E5B4A427EBC108EC22FDC33BCD7F02230A49B6433BC4E981BA5C72027398085E36BF72C868D3FCCE0CB15C8AEDB801254ADDA850EE2AC97392E36084A8456626131441587F72CBFD1974C3780875EA246CE93FDBA8757591A30F00900B9B9E07A77469D03897DBB6F52F8D6ED02F77469A825BC1F1C276D75DAE5307C3A72F09825C761CF44A9F78A2085B7F339549F0905DD0413211BD3A82961C5AD4FE88B9CD776640E38434392DF1510FF9F416541502FF9C81D0B92E5F6A6265A982DDA7A457D943F05238F3EAF3EAF88A6C300F1E6F800BAD8FB08CA1EB1C5655A5ED869F3BB7DDCCE5EC591A2D19A043342D554EEDE81242A9A3F0FA55887EB621684235398C15C5AAA9962361E94C223BDAD1D69C87A684390771364A87FBB854371AD33E80AD569753A389D7496A1A7682F1265C77DF9AC5B629FB576A4C0FB7954EAC01F5A94E213D1ECA6389D8F4FF9C4B768812E675A38870729756A14A7A17EFBA62981F03BBFD55248E515BA5913B770576652CE2836471C0A831DB7ACB9CF451CAA0CBE56F6FE0C84EBC5A551FA3C68C9C444D19552697E65B7A5D9535E7A6E5B1D322CEEA4F7DBFEA175EA716E750FE8BBA057FAF26D03F83011E92672E4BF4F1336FB883CD21A2AC3AAE4D81731DB30D794B04A25CA4EF2E389C54C237B1B142987383AB6F6FD7C527E8D3886ADA4F3DA08A20F33E252BF946424F058BDD055338E9DE72068D5BE75A06A0371102C429E980233157BB1B0B5DD1DB65248A9AADB3DDEC4EC4563E6353CEB01B8991D7E9A6B8C80519CBD8B06380F61A920395E4D2AF2910184870619F5CCF4E8D4E05F81068D88834CA0C64D5B91147A876A569BA0E23D430DE76B1A0CFC70B22CF4110423328196D2083B03D5791D7D967A82FA7DCFDED446518CA4D29BFE3A9B0CDCAFBBD4C74A5AF9445721EA1798C0219E9041A2543F31D8CCE862454F0BD361FFE6BD0B95D51C777C430D78E226E124C7A0908895C78A55ED6B0E841DCB6B42C8093958699DFA5F0B82F0C94697BDF822B7A94E1607FE85A801DC9626117E3D2FA3D9D828706AD8FAF1FA130B65400A5256EF7A174953D2855BE3FF62633E0C3C533A322729D5327AA103EF255AA3FE75A173224085BF3984A9C0E1DE30D08B04FA841BB0CB0C2C3C63BB3B8BF8310673200F2881AC80A621AC51DBE999B8561164A3883F022DE646A95DF2EB6ADC8A773805A009FD8BC5F72A758A109E4C3A4841BA80F27789C29E23FDE6ECBF23DBBC3C12556BA32737A2D625045550536EDBBE859D02279DF1A8DDAB731E1B2AEBF3F84588B21D109D9351BAF83E1AC61F990C564E34768025FD6124B0D8007E5D4C0D00521684EDEB739DA51D3A793C6DB364CAD8AE59C8D479E66843204675C8A6A76193D5BD690E349A27E6E55FCE7D20BA1460DAF762A0033CC54D42F1F387DEFB6D5108A3153FB43E425471092E882A06D34A226EB259667D6C85AA63421048C17B2E4E0488F5E4038EAE9C5D4198ED477470E4E4C4D4734AA77DD93F7172009E4583857501511C9E40C6D22ACA8A16A968F3C037ABE0E31437A82150EFBBFD7251EABAD03D93B2DE6159CB2B432802054AD2615F96552AA978C8F8F5CCD0626DAE79BE0BEEC69BD34C6988F6056F4FFC5DC3989F14EA6A486BFB4ADD7DCB960D25F71EF515B024CC9898EAF414EF07744A98F0DC3C3CFC91C4BC381238DFD67A29BFC43593D3A38C245E5E2077034BA8A646202AE547115BB40A4B4CBFB7D47AA6CD628243768F2E2A4A3B47B96ACE2E8C3E23A646C129C9F8885215EF0F7D13AE8E64D613E84366653A5DF27A55D606F95B1A44C56F40BDCAA60405E1C02D42D72F391E7BED3C7455CB3A26519DB1AE24D99BE9DEC4AB2119A6F05405C026AE30FE263AE13623F9A81F746DF4A0563DB49C14BD19BFABF1FBBBCCD6B05B565D9BA16B86C1F61B24CFAAEF2EAEB52D92CBF130FF5E49D834244FB34D478BB20899FAAFDB97C8901B11E906263A3F353AA2F87D66BA6DD41337D2C1D05819BEE7D215CC2B3ECA5E0A3A3A71F7FC9845FA2751F25FD292C37EF96B0017101E3C250AF43DC4307C449069E9257BA1BDA5B823E2343A7B1AD61EEB1BE94EAC4E410D7782AE9E8A75BB54849C5764C45935C6E4B2948BC6F72C620574096D57C14508719C21B02F6F75291A669740283303DF20ADE6A5B3038E82DCB3EA9508BAA297D8E39C56E1E1F98A20D57AC893DE4C1B59DCB35F1B15D2B923CB2ECDD2D793DFD3254B4CA3F8878E04CD301A1AE8177103E2012D17314D9BA9DCE0A05FAB6A7E23740E713DDA18574C8BF8AF2D116A16BD17367D5FE9C0C6375260481AD70E31FFEC9F8B9F63E5BB0FE6A4CDEC6782A5C62779B0B1ED0956865D963F89541D0508EB31EE26ED55557687934D2DC9A1093A5ABD5D2357672578D1E914E9329BE8CC1C6ABB8F82F1A63044C3119AAB980C1659FC7CCD04041EB8749AF7222E4626A22DF729D0B878A9FC434F7AB431041EBF49963F7F283BB5CB3FD433BD75428AD445B281524CA08E5ABD1AF6DB75208F70B06036399AB66BA84A014377685275BA2672A5016CAFBEA373C6176987232967F81E97156E1057F45ECDD86FE18BC95C10B3EBC7665F879B100ACDC4989427835F9E1A778F3A1E39B4FF2BE81E9B30B4F605C4144FBD8312A879436C532A72E6308BB794A2D69B4A6ADE42EF39C484A494A624909AE942BBC0C36B0FA7EE3838459B3C829F8A636FDD8750793ECFA500D04F10E9075957EB063776CEB14048861912D60DF85E43FA2FEDA98BE9FAD55E1B5A177D82933AD17C5B5913816C90FEB8509C91BFE8199AC75D66AE907430CCAE09CB2BDFFDAF40FF4341EDD45F7EBB55DB6A8691632D06D1DF6AF6974110322BDE9ACBF7E07DA4FC7D6C6D300B4CDA1AF21CF5EF780053BC38C17D418411AB6574D4F3F5E9426014EDD74DBCE26C76A53A09C6666B399DF95307F82B98264E45A6C158C7DE95567E74D67E8AD591E296B67EA01AF48C01FF3A7141F817C9B12C2A73BAD5B36694DFBD15F7D98DB91848A373946D9A1CE2955BECC1AB0801FF4B2F00256E3F62AB684B7D5F251260454C97FF6979E8ECA36F2956876009F7FD24A4FFE9276544C40044CFFD26C7579734AEB496F4E10DB0C5664300684D5D8B84E7466A4F857560F0AA1ED6916EAAC996412B4CE27DF2D877CD899DB377276E500E89533A9B70934365850CCE9145811379B924846C45627521E34AB03366EE128EFAEC353C695A1D4F13255D1393722CC03252B814890F7281C5A4BEC52A39AE4AA2F07565BC810DB4C32606F6864618E549E496F8712D45BC2B289200776958040B6B47F8A93F341DCB375994474059F46767F34021E3F424768DDEE1D2C3F949ED5EF3D42568597E8F309171F2046B7CAF00D1F2C88B2B7BAC1EBF61B36484C71AAB9D6D94C4DE4F900000000000000000000000000000000000000000000080F10161E283135 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input.hex new file mode 100644 index 0000000000000000000000000000000000000000..781188b38710b2af9d213e55f2de237382d49935 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input.hex @@ -0,0 +1,4 @@ +01 +BCE59D1F83462B9578534D7A05DC3F21C34EA93ED78387B32DE09ED3CD2A51EE2B8F7387C8C2D426EAF3795E99B158D467D9A039234FDF207D65D2577D1688E1 +6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE003B9AC2C1422A1AE802DDD7464D3F32729A3C7DE894D506ACAD25CEB372EA3149C98780DCD1314BAA29B9B807754C47DE5DCA954064F28528B815FE27B79AC506B3AD7629D2C971AB8F282E0C6E7E5548EE0E113242B7A0E064A6DBCE30C5619B19800889A04404B50013C088C1302962124CD3B4910A352C43123119996522185202C38523440D90244A1A30224428618106291897680A200908326A44A44C4490218A16689AA8511AA52C62468D04C340D3862860A46013187084948C63C04404A92820082043162A23292D1AB12948B60921883100C53000C48CD98268E1304C6332450C328618083191980D10B8709B302264040893A48C21C9700C35715B000D143122CC98102104809B28641C308021307118335024254408178CC00848844490489830CA440009195119230C52200E4906321C154E194885132549A3000408156D20410CDA4252C1348C00316943822464946D1C81110196214B0200CA2884CC466451186A181000A4982160B06803946C94485180404692222C23446998264D1C01085202208AA6080A316193400E9CC81181322E21158484C24100227254226258069248484411270404C011928245A1C68CE33266C138725A86010CC99084340858A86080C070D026629B302A04296904108D0BB904504628504824D04805A24802C3208CA014004138214B240104B5494200000C2428124084A220449B069063C0888C14214912105416242087445010850CB564DB2441D042299A168A21B44C13B77010C085190269CC40611C4846980625601446E4226224272262242944C62D08318420322104B4610A3812D92844A40820CCA8290B21310A3429032140C1A26C8A161252A664A3B251042951C4049163B02D1444308C40660C400C01A52C09942D62C61103985019104D19A828D38640C0306554A671E0B4859B8610043669D0462918A371402249004385CB4028893666412269A42851D98029140721DA80911B26505BA0609942715088491023095A902122278E43B2700CC94CA402709240100A397002360E113041D8402D1B246DC392614C868D21B800D3242212C82112998509160C5AA22409344210A22403428CC0B28D12B66963340DCCB065A112114A3869CC148158440954A6800CA805C4388A8406019B322D831290090260A1288858104124400219344818A04D001062132250E338219A962153088051260199C4281BB97104978404052CA0C210D3428181424D61846C5A30491BC224C02028CA922D4A90100427864C962109194514822C11A69113B80403187001A2515214495A0230CB302C94102C00498609A025C2124C1B026940A444411662022528DCA22D0016425830665B8624D42448DB260C4C088501904921244154068402434A244205401448CA4484C0420C9826049CA205D1C2511301861CA150D902500C39868C0031220548D31081124805D1086962382C0A23709B4472E3486E22967014336CD8902903004963208A039125088921C0820C994032C2344E4B9869098044E4046994200999246D09A96001292DC842288A3402E408700C236E0A054964442A82C800024831CB90501C056812122CD0800C594861CBA6099CC08142B80024418A94204042144D19466218050924336AD400611248328A047293B46962C27141A68944963162304683426C00192209464D8B0649E1B070424431C180659C002411A83113212C4B46281B180D884270D1B00D90C845DAC248591426224400C2944150C804180000CBA62419021010890C18222162A881C89248D3942082067209A8900C498A41862819C5809A184D14102E2212520008120C334563C63010934C60C631DC400E98825060022AD22240E4062DDB320ECA324ED4182408C3284AC268E28040A1C86451C265CB166023094C820468D9222E1C499242242100370EC812726408250A202A58240459164C08173000460512904003072152C0641C836D9C322E11158A1035885AA08DD9804803B64C0110651086401101420AC164DB224D64B25102360D93463114B668638429C8102494300819370214824588284054A8299014126136120B098CA49828C292454C006063C481C03625CA882D244030D3A82DC9C825D2844800329250A271D3440D223460121312868C5F8620794A050E20D0E1011786240EA664F2F69BB1B7E30EC66B1A4A0BE59B79F2198AD9804483E475E53B3C49CB0CE5EF92912AF440F23B995813D11B59F798E93C9D13539817C7AC68CAD1AA1AC27656BD0C4797E9C8EC17784C1A327A9DFEAF4D6191EECDAFE049B733FE39D5EB4000936FEEFCF82928E9F94CFD5CF4C1E3DEB1433A47F6D328B5E83DD156D0182DC692347591AA6F732CFBE982935FD1846CACF4CB8515C55AB85EE5AD44CB09D3269E2E6D11780961FD131D5E6FBF89849F47F2B71D8283FF25385E52B07DBB266C674CEE3D0B5DF5A56D8BDCDCFAAEE6A248E71DB1345AFC597CA830A1A35B4396EF4C1ADF9ED01BCE9B6EB637FA24AA160B9076BAE30559F8B29DEDB3D25B79064AB0CF8B8D70ADDDEB8B174248D5AEA4D18DE43B8938CDD2ACBA5477BD4AACC3CE595E5D269FE675210D23152B04710F368428794A75F49B683ED20DD647515777955A8CB38A36AFCD2CE0ACEC4F0DFE807702D1EB3BDE72E9E085AA4E09EB1B0947413852EC3C0AC52F06CB959C85394EB3748119EDBE6C80D2D8F792CE0D915E4F4B151EFB135E7F4DC97D858141C57F70417B43A6A126956978D78EFB9F037243B4CB41DF968B7EE5B52087F05AA9FE487BD16C0347CF1335760BD2398AD54DDA00A5AAC446D80B1C7998C602192ADAFCB809D14EE328641BA3AA00F8D29C3A848ACBDC1946BC0D35E0BE0F8F7E3DA3F68D9FA9768F5CF275534A0ECA9E60FCEA38F1E042C316143A767B33ACCAD8C8D66C70C75FD1F0B2586B653AD4AF54E56EF06933EAD31DE365D110B9C4A2A98BCBA165CAFE386F887C72156EB14FF0DAD665616CE3CE65C1904F2C1747B2EC2B5C9D6776BCD79E5AC64B7933BDDEDEDDBBC725BFDBCCDE2FB375AE2BE3537BDF89BF4C25F83A49D6A6A8D0761CF39D620C53ED837D198255CF5B910A6DB57877DF92D8BB6E9C526B8C4EC93100DEE0500A210C984583E1538160EDAC2C6F866E7F5D99D7B1B81582F5D0EBBF2786E3F556013BA9B6F656EB798838EA0579201A95D56BBC3BCDB9511AFBD4D81288896F87108C077F1A81A3BD297BB124A80086890242995E03CF42A0C21E272A9AFA1DC103463D2AB494F7D017686D31894DD2F6EBB0C3CB6223EC79C65D45C1B0D4EF1961F16D653FCF25977B651EC51A13AE8D4A3472EE71969A7A936F5DBBB9396A46D97642358CAF4894C9A6DF84A59C5962A6990A76F0614890169F001870D49CF2E75008CC4A5D85E72DE2D6CF3FA71852253522FE8B0E423CB417A38EB78C8763C3720C04E67FF88979EBA09E34538BB523B99B8E34167412F77AEA894D83ACF946FC054D0AF47295E51ED83F7486940A4D41C04AD7EBEE610BF1D03FA54071D51A1509E4F49163A25081BE8790D087F5F4F05C88550FCA9BF99C9BE5953D51DD0845C93E41EEEF62E0794B2927C4F5ED9BD3E34EA9200A79DDEB4B2D8F305FE05F827C7E2ED186341CB5D1152FC80104E0E13683D941294C778417164B684A976E56E78DA4D17C3C73229314870B85C455C23B830B9A28A3D8C0B566426DC169F326ABCE2EFFF39E9B199AE5C1292B6F2EF37AF1DEA9272C8D5423DF8A5632F991E14DCA2514788B62BE164828E9ACB893DDA602A5E2FB9EFCBEFD95ABFB82D2B02D49CC53084A49AB1BEC23E5B4C8E714CB03405F1BCF7E11BB59729DDC0B7BEFB291276DCEDACAAD39A2F01C7DC98B9E065EAFED1CC8CE3E848080A2FC5B98C9F6BF5040273342F0312F8B9844594A503DD3E6AF1C9E35C1032A4A8A5E7BF33A82F35E16EDF8C60C90021D8C0BA4C386245DFEF09448431D8C00D1E26EE4D8C77DAA1A705ED4792ACB4EA27C1566FB56683C43BF67842E67534CB3F9677C8AB9D0EEE7827CDEFC223AC948B880B5F1CE9537272932002C1A4DD218F527166EBFB2B2FA2BF37246ECDFDFA72B6DA11C30D1C7D248AD64818F691D59B755DAF71BED9AB5FB52E03622A900D66B4C6384169BDF9EB61C02DF45FB76B1A26F34E938B190861745C021FA876200C7FC8E222DDBFAD8BE781B185424AAAFC65862DB132BEC6D18837A1F58A876C99E63F51420B83F459675612F7ACF80B4EB1DD0721CAA1B4970DA608679C6383E817FE16B66B19181EDFC39270C7E917B1F10EB7A011997E967853B78E00CFD58D224D933CC5A995532DCD4E532E4030515F4A05B331D575DDAC29BAB069F09AF0D173373DB1EC2B6366BB371008A2386FD88BE77F5ED5E198CBE88DF24BC6E393FEBC10C470A72D47C0F834653C9AE800E893C6BA68EA28A838FCBB69C3E964A5FAFC2067DD406B257C98DD3979EC7C7ECBE96A33D85515DA2CB6AA5E1FFF204AF62DD4119A0E48C04A3F2B38660F52964D8D4AEE146A9C53C31906DAD0FD90B5D83B3E31B690A4C4935249981BE1F1A85EC6E0FEE4C88F2D89E2969AB8CBBEB501916558D29EA7C3ECF1C9EF1A04350633B4CDA737DFB151CB5E7361173F3AEDDDF527D73F2F9D5B6213AA68F883E9A2633785EC6BE642A9FD0F21A42F6B9DAABDCD1E6ADBEF64841B59686EAE3EC88EEF0A9CBC12BC012622DF2DD93A86229044AF2F260D2183F51E833EE92D98F0251E3F85FAB74CE367B8B7AA63D3CF8C8BF4D78358BAE0A0241E210AC69353087CC7331357EB4450F9509CFE595F54032EE057754A8EDD746CB9282E768DC6B830C5B4A219343AD124EDB3BBC42505566A7038C959BC35585B6055F1968DA243F778F4E46DB462ABEB93B81243C31EB59622EDF81F06CCC61D2A6EA73E109C387915F277BCF1FC11105BBA70293C0FAB5C065F23BAA19290A302F08091107A4B1D568852622098383427760EF8F2928625BDDA5F514C5ADE959891EF2959F248A3532BF9D30E714059EBDEC958708F8A83C268BEF2682D603CA886347E198FD68233999C77D30D7455DE6BCFD0144277062B304BEF0E34C5A9D8D780D29EC2321E07340771C46360483ADCAF12D5B79FDBFE2856ACE8859F6B12414B3F7E8BB5813498960F34FDC64FC848579CAF9DCCF19B4FB825ED5716DCCCD6872CBDE3831D67384942CD8A9EC4BBFEF5706B8F9F05FE1E8FE69D3EA6A8621C22144177B1C1259E1A79DFDF89728887BEF1A70482556831B672440E13FE3E3FC8204A02EA1EFF19D95253887285BFBEA16A0F219EFBCEC30A8AE86589A5703103A8A393FA6F6B657704AC677C14CD10D3D62D13FBD378C2DDA325B61B85952D51293871E1FCDC948C77BEAE9A6F0E87CE1A8051C8F8087685C12624BDF58380ED66F55B43DDD6D362173A5BD389859C17D95ECE3AB732639FFE451CD103EE4854DB2F39614F658BAA384BC9948D0714EB48A887143E7A1FA4B690C22B492A70C612B59FFD2D6B3B5E99C2003E2C359B1E62DCB620C7A246A7B9B3246131556F2F3D513A23C6A9FD2280ED686D767CCD01754EB4C99692F2B380C36081344C1D35EE1949736B6976F4852CFBE64FABCF11B9AFB828576B4F9787AA7D03E84598A7143EF7311FAF2970E23ED4C173F985D6450165AE3E241A18234E74FF3DDB921A5300B1C4FB6E432E698F53F66E38C07BCD6E77605DF4624D579076292DE1CE6FC6F0081A38BD92D39B24B73BAC1C52BD68E9181D3DCD0AC7534DB48901E5984F9902557BFA231B2EA28C3183262A1B2221F7426EA88A5816093A5CAE2CD5D59A9390FC93A2956944B064CF013BCDB67FB423D1328D2C6D7BA329013FA2D30EFD69FDCA1A95EA6D06C7363534B2F3F7DAAFA296EAA09B3668E9CF82D9BA959B32F3CAD3C10C6EA48611554539C37DF6BCA3385EAD3FCFF96D372B42393B73C8DAAAA31506EE0527B7FB3E593DCCCA57C8FBBD4A3C7F8A53899869132FBC3E4050607BBFE29C675E3945E74A31CD531BA7AEB2E2F0CD990B8F983A90DFEA0568F0677EA9563F7C479DE968940CF242992692865CFDA89FA078BBEF49CE4575BDFB380366011C8435F12B42D9AB99AB6A31912C4354149D723101D1365A65E7CC68D82E30517773902FB38DDA2B324E7208E987ED287D092E7662A430241BFCA552D314127E38C8597A89519D4F1E62A79465AD5F4EAA3FA77CD98326D2F92CE9852055CECCF62D63CB9D7F198AE085E4D45C8E48FCFFE593AD652D9154167BF3E6195810A445AE158F1F9A6793363AFC1F22CA882FEED3A5F5727CA76477C5F23F0FC8700CDC6A5BCB2B20B4F9266351D304A96A82BF5F314AF685C1C707C92E3E847B7047D689C70B25E5501CAEC9919626F4A0FC81586AF1EC88889B423387D5D95482618A650E80B53B07CACE3228940602E3DB47466CE9BCCB6E4D8AA61C8912583E810B3B2E7E9CB48BD403ECF08D28C70AE0B620859C1F09B61131404C3D5BFFCD860E0F42AB299006230B2876D77DDA91C8C62BD93A844E4B344E3255EEA531C6C458D04ABDB0FAEF2D1C0B4C55F570A5A51023F4D4EFFF59F9ABE17922FE732CA71BCD434AD7710B84CD4AC9F2507A06826562AD7F647826F9DBBE4EDD23F124369DB8526FC2B4D52F0741415F972BEF6A935BD812A56C8221B7DEF0F5106BC01E913E3D43DB86C2BB4C7E0762663C6DE788721C2AA07F8954887E2142F2E914A099EFC0AEE1339210D3E53DA3ECF88624B1119BE34010B886C80F51D1850838F2150E72B042AF32899C0D3D7B02A57F8CF263A369562E4E945A31282A502A95EE9BB0316C6861006DAC17F936F54C4C7 + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT1.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT1.hex new file mode 100644 index 0000000000000000000000000000000000000000..7ad86c857bd0b94bb0b83701dfad3d718265688b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT1.hex @@ -0,0 +1,4 @@ +01 +00001DA6 +67D7F4FE3CC57FC8BE9A3D06BCA0FE4A39F39E3A6158D3E4ADA9CCBABEB542CA67CAC48167928336993C569AB5AE55BF95C8291AE1A1AB2B595C90C0FB19041435F3B411609412630D80DB0C832D413D69C8D3C3CA78BD1BDC24167AF590B67449DAC7F6ECBF87698BF3929FBC874F6FD68551B28E4EEEFDE9A0D0E7FE9E569F1F9893D39C17C3BA7A6211B875A7BCAD0C14194C30D60CDDAD640EAF7A02CC9DAC074779345B83F0D282899B2B9B61F8504BEACA3C02A76611C82F2007953D04FD3C54D7A00DF8F6DE554FD83D1EA5DC841645B706C9D900DEE7862D526245215AC6B9D178E60F9602F1931503864D97F582834DB797CAB60DCDBDAFA3FAE8726B525E8BB69B5E0763FC4ED17FE7CD9C9629273AD5B073B9516F6CD7EE729351C213FDD122E3C11DBC58FD2A501B267AA4AB21364BAA856823816E77B81B6061279FEDA6617247B86073E55B19973BC0E725F34ED4BAF0AFB95E436A9B2290A2B316C18CDC0D9F98F9F6F13C5A3FC767EC0A9A49BE1378E92BC9B3010B41AE52AF409AE0FE27CB816EB2614DA41C796D5F4FAC4A743FE34EF7C0B3A78E0E4A5B439659D4AC27B698550E89A1626FAADF71420F559DF2E808144707B5C02090F754C3BD4EFCEBAF6FA4493C5D48F895FE7674C81F069E1F00E455BF5C965BE2926BD19AF76E20533A6115F4BCF2CC5DD3A49E10A2B3FCC9EEBB2B6E4F25118599062F2AA6CC3A9D86167B1BD08DDB2C53A5E46E1BF4E8C1967866320BA66AB67CE581981F2003B812BA058B75924254EE3715BADB8E6B1B9E4F4AA9844D578CA2F0AD12E1C964685FBFFC87108711E022EA7F63330CA72AF86262838863780F4115138672643E6D9B48C782B8637E01D3D20CFD5C98A1B57720762037FFB12742B4EA8E89E4B32EE7DBFCD5C11E4A6E839A83398ABBC32BA39C6A25922649971D88A102D1019B560C96B820C44551E14509468196CEAFE3B7BC8F253ABFC59FFBC01A13008F77C91B19083A9E7BE733C1A5E558C64557389CA19249CAB77014D0569BAC7812862A610DC6EE074C844A055ADCAAD496F6976C932587BAD9D7E2080F8623C5ED8D9D4FB9EFBDDCC4CCC1284D22A2997824577A619905B0D6E451CAA3B2D30DAD9728FC7623F9ED71F80599D65D9F2AA285BAE393D05C15891472B2DD2ED5CA669785EC4D441F3308EB4BBDAE8FC449962EF9787C39A533847540965601D8BCB6B4299AA636589BFE371D3904E18BC9AAC9B3B6EB8B7E8F322C22A6E01E6B26244F9E39586F124AE4E504FBC9D860A61B20B4C127FD0C55EE810AB9803D810233E6126488A6E95F8ADBB3F8E06D113DE6A3E361209E0D36B326E042CE9D2698DEE469DA15464AFF82D5603434C07CCFC4D956A7D55FE79CC127AAD2A56B34EB10E8B85C3CD5163C4BB8C1083BCE5E5EF986AE028837809641A6AF2B8295B743DD9B03931E755673DBDEDE56F6294270532D685DAF1187137CD7D29248F21B290EB8317E3EB28B62E45E140F4AFC6D1438F81E9EBFC6FC0F1A4146AAD83AD1F0EE2952643E7B6872CB2823AB21A155C281ABCD19E20A52611C6FFAA724578A070935B1A0BFEFBF061101A81227187E14E96B016242DA269FC91253FD827A73743A4BC49FB63E2D830D0FF409AA1C73706D7C2297CBC552CED567DFED72CD15060A522F9B88EC910B03CD2794A9FC07A8FFC5CB97817DC769E64D8C474A305035A49D05B1C572363913A315932E391B62AF291DC203B9A40F04F40EBF26A4AE186056CEC45EB7D21D88CF50258DCB5EF40CB2ECF949B18C72626469978FBE0964C8A25E8C2D27149C2266748F2B06746E8C9E7E2F0977BBBFE3FBEC7353F583FD5F7C2B0139EA928AE1F67004706F6D4ED7BD8D13BC68E0F4A49877C0B2F692936BE5FF99544B2B19B23A97EA6B5F585ABC9E69E689EFE25E15804C650444C479E0DC63C9CA2AEC41A316039EC7F675F1FD7C0476707370CFAEC9C3418CCF30B5D85FE0E15056D6C015DA59F9BE9028D9C2D93434F99DD8C1BDB41FA1EB021BFD0FC12EF0D038CA32B0FE1449342D83CD6BAE43A8CC4077074FB1191A8887BF29238D27415D93880682017470A42872D6CFA729AA2B3F8B37038C83583E4C33256FB871A704527594596FE858777A93D3095767BCAD2FE295352C93D227E1766A59ECEB38FB7C2E3664D6DA0DD4C063975FAB3AB4B68D125AF16D233389D96A337DBC18DA11F37F430C1E49BF8AD30258601CAC9215F32771C6FC2B7BC03B55AE9664E0D719C3B40C3E4FA7DEFED8571CE8E46FDE8701975D94319DC5FFBE93B4FC4898E2EFEB3CCFFB3494AC50BBA364C22A3953F052F62E46D0C35692AF40D2FBF899A23C1A4721375F307E2FDE2E588830753F908FAD96EBD5FC360D742E2CB2C38A7E142C95376ACAE29DE8E1034207D1CBC1DBF2968677AECED152B1EC1AFC195F3320352953F2503227152444BAA74EE8F98F2B4512F7ABB43D7F87889CF1F8C12D9BAB91EFCA5AED21058E322CEB4E59DB4DDE13BE46FBDFB225F4AEDF7137B548503008002A36D7A3E98C0ED65ED9322D66FAD4A741125EA4ABBB26A2FDD7AD136590061E7BC0D5228555D1A59F8A6E4B97ABB61F4B1AD9564E84C000585DF8BB31AE61CD25C9D91D1A1FC21A69AD286CBC7E00F592DFC1C65E2BE755DDF041486F3B52C8F72ACA97A149FE0CE1378236D99EF099A668F6847659F7EF617B66192CA452ECE3010AAC18A65D8964381F561B48D044096DECC22736C902D7E23EFFD26245018D9D7EA9E2F907932A1EBB405BCFD29F7A397C71A5E08962ABEDA5203988A81F787B25EDE84A7D85DE92A2B19974EF7D0378877B82BD7CB28B67F45F7EE625CCD054B44B4CD51802B4FE2E219315CA9F4C24065F5578732DC671C3004D31830DB435C763143CA209D7DDF3F5EA42244E68429102F4D90297B7C987EEDFF0DFA7F31964B76432E1DE27FA38570F2BF64D5FA3F12DD9772618ED2B95F51AC90410350320E19084F1596F6B791AF1EFC24DBFA2B7E30015AB14FAF43B568C5149A1152A47D278B5F01786F242858C210D28812147646A1A3A7CD69996809B784BB2F0053CFE18446F060622FE3B9181AE9175D6CFD8033AA752296016E7BBF639842DD4073AB282FF50F94B9E116C63DDED805277D4FD7987F740EF8118946851A5336A9F6F6E2FE3ECABCC518B31E741AA79AB500D9C6DEFCC437569966EAB1D4BD6CFF8AD0E5698D15F1342ED46CB6DA986F0C4B2B427752C18ADC5070043FFEEBA98569E90C79A3D5E0434119A077A097D69DA6E9AD7E32C6E8875A893F6D69424DCF4C0D4EA12605E5E8A9853E4B58E5659FED6D724CBAF582A89A228F99BE89D88F55095D0627B40B29365863C57F82B9EA22FDE731D1A2D8A9037665213F2C410D4AADCE12CF888DD4AF53FF839E962F0F53BEC60F97133D131C2C8EB588AA7D25EC025B9E821DA8E8FD8E550EC5E4D5923BFDDBAC522D1FA64C503078618B52F452B57874285AFD3F6B182CA6C979734C94F040EBAEDFEB547683E98F4D13F12A252E8839317A827CD97A7C3D81962A25DF7D8C62B57812EAFEA9EEAAD7D6A9E755AE4CF3AF42CA2152F663C1BADA0E653EB165F6FB56D86212378C0B9BD5733D4C37178FFB58E7357487B98DEA35127AB58A804B13E61E6D3E385C96884EA91C744DF6CD44B3EFBEFC79ED19C406AA6ECE144A44F1E78B33046C33EB17E3BF61A17D849493D08F0FCF8232AF2922D96213647A47A05A9A08D28AADD3B3BF412F29063C9D78CDD3385BFA9F8BF06DCDA23FF79A5912D867EE1B0D526718EAFA6F0E231CE6C51959BDCD8D201838A50634F1C6BEBE2E4F5235FD01A6D27B90C58C12D8210692BF68FEA5B8A8651E64EFC1DFCE07EE670D473F29AFA63E080F7675F23E7D2866E5F2F9A525BB657E8BE5933FBED1E206C7BA9FF097EC95B91E14612E16F0F4082F70A1B01EB6219D47C716455F4C1C60948CF3228557E787A3186B4758AD35922AF28BDB328693BAED15487F7448D1796BB9DB5C931EFABB4BE436B2710EA280368A8E20C5782A7FE986417003236BE9CADC560B3D7C2CA92341536CF67D412E855B92D0229C45B1C518D8BFC82DFC9F413D3FB23D37EBD96AA0CD0B39EF88B23609AE0FC2BD16FA9E934329558759F05C8D4C8F3F8728335B659D3986E44508322E47121E592C9DBC6F49656B473EF7DA53FF8EF7BAE07D1BBC68EF4AC369D7F8BE60948F34444C0C443A100443EFC444E7FCF0BC4DB6A2C2C64662A538D1F68F4DB95B0B83DFD744ABCCBE5DA343621F0E182CB9E915B2097C186F1B98E7D8F297C347B60EC26D04B6D9C1FFC01EDB2551FB8D11D49E52956F69CDE0E49E2E7DCC8E7C8E78C41A9B2A01483BAB11733A0943A9B765A5811451C07A195D87060F157D114358E478FBA2F2B755A2A455E9831B77EA9D33FAEDC1C562E1CFBD8DE156FAEFF10AF655713E36FB508342D9B4A239D6DB786CF9F57E1C39AE65A7329E434AA88C68F82359E6F057873968F9FB63D898F24BC13C0F7748F92E404C6185CE24C98D4E4D8D4B3C129CB46C614E773A89EAD73CF0C30CD7E6C9F6435F7C83A4C3F877E034755EAFC5F30ECE03F6413F4C7DCCD01649B6ACA9C1C3AC3D112F216AB852A27DB3B846CAED86B76FB699AA7623548EADFE6D16AAF5A3ECCC298D5CAA7E84ADA0B75290FC6ACE736051924DAE8FC5BA6DC9AFEF65F369D054A4A18950E71901F4483A4BDDB2584DEDC31A04C5F8916DA2DE33B37078E5DAF3304344A8AC368A6668464FFD7898A18D10685BDE6D0097F95A3587717F6A3A8827B46653D56E461EF861D6908AB7D865B532DAB37E02A7A6A72A06F25572D83ED6DAA540FE56BFFB2BC9D104A74F135127ECE457991152DD0564BA955971E8C9767DDFAE190052A98A63C4C0DFBD1B51BF60643E4C5EBCA678CE5150F03A6EF09AB0B1C2A0D2C19C2B30A645C7DB9B56B5AACFB862837A38407070DA9C7DDA20B99CAC7B03D10C8F28D6B1C686FD26F9A8FDCEDA6B188D472BC593AD51EA62DCF73D32EED5444484853AD0EFCAA60DD42DD2C50F5AD15DEC7B71BF585581B9F9C68C7C94C154CC7E0D19ABC90508C8EB2DE93F0BE4295973C1F443A1B2419E20F3D5F883912BBD5CDEB938A4452FE0BF2361A9E3B2ADDFBF000DB07EA19B2735CDF0E8E5C7EC5CC7CCE1A9C3E869718272E54CD9875C21DCCBB06FEDE38A4E787D111DC6A253A4604B314FE47A9B6F6FEBA3F8F013A456DBB78B497C4CA7F90CC6145F47C96D266BE5507DEE27E968052CAC85EC87049CDC68D723D8CF89B0C91F67CDE2908C0C71808004A070CFA2EB6408F5FD6108749406FFD3D5DEB6FBEA00FEADDAC4CC0E22A9F6F50B9893CC4CAD028FBB73C1B7BD4292AEAEBEB668859BAD444D0C5FEDE3C469CF28C5C726B59E828C473C8787453BAA3AB2BFC29C691FCAC2CF496ADF3949CC42FB16F3677D456E614B1F88406E6C9DA7DB9937B00764D61C3D347C140FDDABDF8CE5E3E2D385C3FA6FD9F13F3BF8073B5D6AACD5294938DEF9C6ED414FDE4B3C5EC43865A7FB02787E50F94033CFE32A85BBE24B09FAA3B55B8BDDE60E325B691A350F2F128CF74FB5B6DFCD0E946AC7BCFB839B3765616DF35AF29F3AC82F4E2DF7D4AE87A016094719A07B5897105E2B08AE3D807960FED396CF38863E69662238541EE295C06B290404985444F4B28388DD942E51867216C734580B3F1D5BB204B05D4993D6F8ACDC8F16FB77B607FEDA67939A2B6AE285ADB2C98E7D37A81AF0101A5CE39CEB2C67CF99441C1FD980C2C542E7284BD21F1D30E68EF3606C65D3230B5146DAB41D4ECBD5FD89FFC68441BCFED9AD8B4E0B616127A7AA39E84DBD1343E2A41B4DB1AEE0627657438034E890C8EBAE19791705BF6C948C630DB1423D310A34BF151AA8ACF3269253BADDF5B40AB7EB3A7AFE2D7891B925F65EA206F4CA121175E8F348B4162917A68FA768928AEB0504A60C4F42802DA25DCECEC60ACD21FB236080AF1FCC9146BA30AD964416F4B524ACC416B5357206980305555CE3485425EB8F87401FB1D8CCC184C486B5B563242BA9531147D6A2E7C0BEC1A56E083F05344BF97A18D0CE0FE56E8BE869C746D4AAB365225D8871D4F99020DDB1CE2B5D7D2E5DFC8A0DE780CBA0A9B9ABAC87F19C73639965AC2382488387F06199A08F283794E1B8D3580E5CCADE811ABA6881908277624D5395021016DFE21C345B9A21B474043E187403E5B0ECFABE43991865A424BD33D233AC4BD30A3CE73DCF49B58CC4A3D2CE25C54FAB3480FFE0D51A43B71FDB7E1126E66856D263DDC3BF1A31DCDB935DECCF858FA2CE5AC89BF32E36D8009657F11691201290A243B5680E060D2CE30F1BF2444D67DC94A24708F8F9261945D1B5275ECFEAAF40311CED5C3770A1C194EC44501DD25B7F5FE67BCF62D1BF31119F8EA7DEC1CF536C1026A8E72C7B2E167BCAA8673AE5506CF6208F3E1B6057B5D488B29EB84D6F94AB8AF322B8657075B9EAD3297505AA521D601C21540EE71349614CACE0E7F14EF42D6CD5377DDD0241E34CF273A1171135A376B98C53B218503A908577C268F6DD46CA9C26DFF5942998851627474DE9E6B46F49DEDE85CEB993A52D01F6AAD6F96439C18B0DD5A4FD559812227BBC0567A28C1299626B171855AA0C74E2F9B1AAA781D34CA58C72C708AC49F5AE1453902A1FFBB8458E8B4786771780ACAD999F8DB036CF4C3F77AE345817EDA2AD8F7D2AA9228C994F6AEE512F7C2D2AB72F2099EC932D818E495CAC8507B06CDC6702944237DBCE338C20EDC84D958C14233C1884BA09A023BF5284F0B0157048B6AEB508415DF337A553F6435140D0CE5D5CAA77F9137B2C1AD5A02B13738772743F192E53E970DDB401983535CB096F7D98644797F487CFCD18F1B22BA7494D892C1E5AA05E66B1A4326C70E348350C97DBC26CB110AE8289C97CCAAB150020827B7D7AC7913B4FF515583677018949D39CD73BC7DBB90696D5EBDBAE6BD6FC78E3826C8218996F079A387A17456875952B268211891404E80F8360F042EA3D9F7F7BEF772E64FA1EE8B4EBE0A1162A46EC1E9899766BF4D3099AF712A847CC86291B3D6FBF51B3B3CFF87D7DE71E73069619480F6056AAACDB9ED8E228BA075622C2FF242CB050342DF8F02118D071D27D1FDCBFADFF49184F5A100F95E1BCB019864E58E0F02672C8F5FEB97EFA06FBAE6EC3D57A10EC712BE0144323292A2CB27F1B1FCC104140F556D09A6074F853AD4328B00E6F2F24A61A7932311BC999805F2E774DB44ED72ED244A945928B9512556EFCB2BA7BE0E668C41AE7601339F0162CEC0A1AA91C3FEB6A8A40158D7A3560924455B9AFBD4B3881F6C08EC2895C84CEC30CB0F5B499B4A66267C719785F94A9B9F96FCEBEE939AD0FCF42D0E65DC241698DED0EDF1A9BB4147898E6E83851499175105BADFE4CB00B9000404DC92EFB4EBF41D9A9262EDA550DBD0B99353D001F90AA05591100BB678634FDE4E0B1C174222C253870DA3B8A797CAEA9B446309DE5210F9A932D6AD48A4A7361A943C1BC66BFDF75CAF5409034A8768BD535B20996A728A26E28340191E03DB17A7032FFF883EF664FD7351DD37DC2D72F0CC4B80BEDD1DC33BA3046162F5D0003140DF78FA588A9FDBDF778836C6CAE7E5A20FEF030C57867B295712DED14474FB87A301C31214FFBB4F8D166498ED93B6E233A669CB88D441A38A0E5846EF68F5DB20245980CA184878BA8BE1992A0638B058CD3A3A501CACFC818D2B5D7876DB6EB08E9F26430FB06EE0B9E834D1C331B66CD0BCCAD7A66ABF4A9D8F7A872932A3C0B25C5BBCA480159711E0BADCF69A1107B286AB199B210CE95BCBC4244780C074C42B6BD43869F27BD666F9B2541B1561B4C207E9A667EB1E31942697FCEBFD0B920EF80CFBC5CABA6F528187403D7E8262C110458B5382BC376799032362CE57ED39F0D29D7822C408923C29242385CA9749FACA43EB4483E095851E89D24CAC7BA5AAC60815CB5C8C5331CFD66352BC8623D5700F49FD98FFF9E869D5AE173961138D76E00CED6DBA09144083437CC8FF5ACDA10BAEC0081C8BD2F5838666A093B412532C521753C4E11ED0521923D1EE6BEF3B4FABED7467B9C8F75FB24FD8D96759A6146B34EF951C4DF92228C2E58231A8D25E3F08ED5A27BF6041AD7011DB41F815FEA503973D4E7B5798489B261A0AA4D0C32A19D17C584B1702713D1174E542BE4EDCEF27016BFC78118445A63FC1D17FBEE5F71DFF46F1EDCD050239C68DDBDEEFDAE7EB8963B5BB4819186D45191C05AA049E50C4319936C8788AB72744912AF28BBF5CC77C835C35BB4F987DBA6657BC2A7E58B7CE69AF37AF680DC0EA7797B29528AC70D92F295C561E2EE0D0E530854AA19EDC43C01A383035F6A5DFB354E9306962EAECA25EC85B9B78E8A1DF6CA50EEC733F60C81BF812981337F784F8CE07D0C03D8B3E72BEE1FFA55FB92DD0446CEE29D8825CBAF1A6ED295E613FC700FA31167224D99338C4F59B1BB9C1E63CF77476BF84F2001D42E4161F7737B47C1A5F219F6AC8B8E3ADAECA827AFCD6BC0CA09615BCE15F1BD0803BDCBD41E68F781517907EF3DD8E8A33A1E30ED09D7EC1D3605DC72C9232EF9F92475743164E92D953177B98906DFE5E414E134EBB63C79220D4907869CB2D93280F60DBECCC81B532CA336510E2A7F1D631F7BFC517AFF223430F9804C4A4877D8B7A385ED48F390ED9666A56EBD62F6C943D0E52AB1EA247BFB07C05908E99358A51E6111486133F4A6BE3BAF6B2D4C01529925ED911CE728B4CE4E8CF8379BD216108BF964496269BE76379912E94A4984B890A4BBB9692107D56AAADAF27ADE475E98A566C0C9E33DD1970A3DFF0E2F79197F6315E320BEB5E2CA3E3C904B557075981118B363042BA687DC682F13D213974B1647FB43DF7FA168C9D4F599C5BDFF2941C111C6C43FC75E69C290601EBC9F23D665F944A9B75932DF7792CB8A005A7CC83DD071376DB11F9C950B38B270E06C907FAA102AC76722325934755F53F3650B42D0FF293FA37086241C00E99B9C03FCE21F8D7555CFA93D09A0EAEE3733A8A5E4C45E74DD5EBFFD2F75EA60942BE34412BC82FC9959CFA155DC87FFA0AFFC1E7CA5057EE016B9751C16DF25610F1981A08B8E3352254AFA433E9B86D3CC13FE9B5B7FBDAD83CFA0FFE511E44412DFF1636BCBB49E9769FC52B302AFC7A96A3DFB233831007CFD6C302CCABC119DAD45EE63303DFA1F11C39C702AAAE00FCDCA913371F158BE5493A9B5C3B06AF66C8D5DE2BF9563FB617D1490FF6510971203DD25B27E1AFB289DF894396B8C26548BD53B320203AAF053B19CFC815C5D37E3115FD6CF8231B88FE4C330545F131A01124BB2487A3363B3E534BFD38B1D5138F8887EA63776D78783AC45675ED598617077AEAD86206B9FF61E3669C93C3C3A3A8F39E7848A88C0F94878E5D359C22BAE891FC7478BC8227FF320B047D0DFFC8218C1110136FA803EF6395E52DB8326CE8E3AA928CE42FBA04B1E7F1AC7B73296CBC1567090B9E92238859A87686D8E623B780F0376B8537F41B1BB102CC8C480C0B6C069F562468D4E1FE111B24D51F63E9BD38C47F35D8C2B5BE2E737274229974CC4CA63BD0E1F0446F6C4448EDB2498F2376EE26BDD8581242703715AD434E425908D61EAF865FAC5E82578EEB0525F54320B6C264F37DA36B55C2308D4FC6C7FB2F4D12A88CAFD93953193B7CC46804A0C464740B4972A71B7EAB5F6098FF78BDD452540AC5BAA894C10CD69A992217B422C88CC7849B4D8357D86234449B452AB4D49EDB1D2769512CF8A797F5FFF4E1E0A3FBDE292D91722D71322F0BD48C68A3CC998D03F7581EA7B5F5150E7AF58A076D09D103E9F64E61A2D375461007210DB511EA89FC4EEA75FFC71F7BF31400E7783F12F69A1EB5B7228952E2CD1D6FD57109237BDC024780006C229EAD71EBF4B543647FDD9216D98DC78B43CFEAE12166CDEDDE09B52BDCBFF089B1F7427EAECC21CCAF3FD5A35EE72C3107DF0670891E1AE12C1FB81581F3A45480F1FE06BECE6A494074FF3C47F90C961E371E8014707AB0FD004D19166140AF7B1C9D6B7E4B6826601AE104CE18E17939CF77C2A31F711D5C7D5126F4CB642178CE542973466696FAC1A0858ED62E4F2741E47B83B97DCF4610B1E4E262E700A06FDBFC6709BB1D4AFA7C20EFB72E0D623389DCCB049054CBBB322E63B09176E2903DBCE49083B01EB07F140D498B793E149573D8CA91DD2BBF8DEABAD9CECA0F896A7B306C22F8A761A65CE2BC1358A6ED07327AA0FF4C0B6E2906882A12C50D61D021A1316646461013D8169C4B54C61614CC9EDB2CE0AB0BAC96B36908BA3ABDF92D11D96EBBB9A60DA780AA58B804DC6F91E54D82068FE2FB10EC1FED54B794836F54503135A7F91921E2BBC2A61C99B6A0BDC04FBD2D4E7E430F16B5D3C7F06243517452BB7D2D51340BAF550D260A26A2F3B5451AD7D4E3A70CAF63F92E25D137C9E9B1433CAA5502DA269211F58AF2720FE3F899282C2C02B78E66D3302C5B9DC04B98197D3685EC4E6D4603D79B357282932689C2928361022E79C197A470212A69AC2BFC7505366CBB2BAB8D2E31314FFD77A04E85076D76948E836CF2A87918D43208CD856FFA33740FCAFFF9F690B2E6B33F1D89F65C71 +13FAAC5CAA1C92AF31DE6C25B147014BD7FE589A649FA0089AF0D606E4B869EC1E4519E3AEB57924B329B085EE7C80501241FEE198F3F41A94AEED9BFFCFC9F7250182F2FB7F56C145635D81FD4981B541AAF62A572520FE29FCC0AD050545BCD377EDA950D1DF476FD2B85C8C9E749807ECA53A51D6D0F4F42A339AA7C48181C83851A0A830D080651C3741E1A805D4324624272D21366D403652024250188488CA24804C842892360462109258844503326E13390E02928CA038044C348A52A46054082DCC329204822D5C9869E2246918914462A86560080A0C372010B9890CB92D63126D13986C21B02D20C52560340918C641A20872048684824026DCC26418165219223158928940A8408A3646491061E396690A2690CC042D41302119C06510872141400C83120D831205109905A42844DA06201AA30502150C04282521A430E03601CB804C1AA2618AB621610410649450E3C630C4226880343210C09021944589248118C7458B904402126250B400E2866800A2041BA68558080ECB228E59803192847159262A04216D13A00C0C452D518845834402C42846199345630069E2060E084528CB1271239484E2386E93446D1CA26D21C60561B228DC1406D19870DA9211CAB48DE1A20503376262B6014A284259948D80225010108C18354D13982912474DD3B8209A40120A398A88026A8B2280D99460E0A80491246D5B060D02012D13272D04154240860520948D9182215890688084115C0248C12012D0B68DE438666306258A884C9B0801DC087083445222404109252AC988851AB7491B899114244A8A043103408ADB3680593488410690DC084AA04830C9441198142E1B038124B06464209223B484A49631CB82648A9669A1C230C9A484A18420D9226A99A26513C168234404CB224940926C61066E83C8418332254AB48002067102007213A57123842908326E54828101920D83344A5020251B84718A182C64B064E31049E4C090243592A196308CB89109C3109336812399415402101C196153A68000022C8B10011018914318705AC20C1801665B341109836811B78998C6618C40910A430683204421284E41368C94202ADAA66541141213B9605B442901102499904C41342E24C28DC9082E11382E00018A9334455810009090316348610C2860D4262981280DDA10519C140C1B2308D29208C8464E10322E44A848633490810022501845DA420E24097162A04908194453C06144482622C42188320A01C00952046A1B25511BB185243809C2A86C603689608684448065D1226223C98DE400468CA0504800804A283044084A220640D800724A0062810425E2A22804C04C0A408E891089E0868DC2B4850C274843167291220C498061640488D1B605121721D1C231D4C2811B8271A4422A414212D9982589069110220C99886002B7219A1262D2C0219BC28412496A4B089022824011106603A749C1448063A65160380D84460CA4A28C9B162A09A388522426C3A25119A6802410860BB3888BC66C20A028D2A664A416721B05119CA42113932C1C86491CA30953380C92A67020C7244216280492714332221440406492514C448C8AB40188308611346560100CD0302D24B460A03870A0968920842924A88D58002010286EE1204C14286DD3402DDB38251C1381E4B465CBA645E082015A022CA01612C3322A14A36480124A01042A0895250C8440809051A1282524B86D08318AE0220E210692DB966C83124ADCA0692127065B1828C1882D133209434411C9462049C48481146C18956948C4480C492603080D18942000130901436118A60120474819111018A50023019022882818054213069191062509480E11456E8A00449914010020122092480B8320E4321210B429C290512139049BC411129890DA14661245048322049B442A942291C9A845CC408203C77181429223B670D924218BB08422392C4B2860A012905A807113462992C068CBB68D1C8064840482D9B82152202A1B0565018545D4462DC8B620D3404003C42051380AE3228541086C04C62C8B20051B091008A420E0906851B685083825E4428C504866CC98281B1171D2208E4C324E13424E02044984B20513B9059AC86500472E9220710A300CC13620DB8808803840188810A1A84D043582E404320B048061345208C5201B92401032121C426A231904949090CB9810B0D16BC03B32C91F22E9DC32FD1369B126053CEB625567AEBEA42D32F861AE27857C24814177623EE402427442714970674EA84BD573741F3ED9C297758E0666F718D5E61117BF138734FB56E3348CA54F05492294F52FC90C243BD836DE2D5B9797A189C7D38E6E35AD95E1533A32B5B589AB56941904BDE66124FA6CDFAB90C80A05A4EE8E50A5DE061DA6E11D3B40F218664631444651497AC3AC3E9A9114C9BA1E92D2FCEEEC9168E27296AF943472C8B4E251F753EF79F80948F2ED5BF690E0C0A074E8E0E4503410E8FAC6D8B022BCE3FAAD1C29681FE2223125F43FCE56DE461BA8264DC83CA1E690BA638E49052D0D05EC5176D12458159F2FABCA6556F15914598E014A4582C678C0F6ADD2F2AEAA330E816B0AC0BD5457948FA49FC4C954020070451143D8B4B4602BF9616BBD1D9F76B0EDD63F186BACCA0C0F861822E6AB56F771C6742106314D54EA9D0F1BDE66F4A504C6902D86B815F46F47E6D69A9DC16F290A8A9EFB06695670196D17E096543CFBB6927E25191B9538BDF5858B54EE4F69D35CFD511FAA422B6955F0EA87EBE5506DB4E7871C7FC5A2F974C736FF12AD545CE507AF4E430270E47EAD8663361CEFC3FFA2E3CD85982ADF648DE6F899056672D6CDC6841B1F2668CCEE9CC630AE9A91CEE7648AAABAFB09E4AC7ED0D7ED8165D851627A01919AF56FAD39CDFE838B5CF60E8FF5A2A7C91EE43F1AA3F81CC853B178E3481C32C2D6FD40B0EC924CC1887FC6DA4039FA0BA82D0A57472C9D6003BB3D819A0533D3FDBDE2CB06BE052AD7E56B92B431652D6D5991BBA6B564C15C1BAE95360A07DD76F0ECE8532376D0B71EB865933D3520EE7B3B35B7656ED684FBE914D01502EC4BD7FF39FADF06F6BB002B882213C4D42E6CA651BEEBA228BA93D825D618084917ABD3130C31B3B935A253D8D28BD45C5FAC4B05A42BD815B9CBFB6198DA4FAAB4DA6E9E95194E8084D66CD6B52BE2DE2A86DFEB25C254F59C4CB168185E00074E9CBF060639CA6ADDB7DE514CAFD5D1D3C74777C11957416932E8745C2B01AB7DEBE2E20FBA37476C0626140FCA24D3EF4F53148C51CA78C935C6C89233A6D4C57C317A19712A8040C1C4D3AAD221C1D375DB372FE07250FC3C1BEA8ECBA24D781492425702F35CEDE709AB063EC0804E71B8669B87DAD1563606E89EE0DD2A0B11B8836F5A2D375AC4B7F85FC5F80268FE26121210A4E1CD24BE3FF9E6D92A5437BF9019002140A42C317906D61D862200117FF0F8B8EE8D4C289C3950D083B5E5670D4ED32DA5C691F20CB648DDB715977ED6AC69F64DF8D5C99B4177E8B98876E7A5D29ED0C0F972CAE6256528233E15B13C69AB592C3AA260C77BA41BC608A57CAAE46AD240DDD5C2232E2297ECC90CE628DE5B83A551B06BB68FFCB152785B5AA6D1702DEAA8E92F704B0D31498692C537249D71DC6B1247948CC07413726DFAA43F53058807B77C4C73874EAA526EFDDFDD9116C98B0E2C5B7CAF9A25278761E2EC3B34B766877319243E138DFE6A3A03038D357516D9BF64955EB8B0A4975E026D0915BCB8637C769530458F242F65A68DCC78157CB30C4632938AC32781259BAA48F11B3949616E06C4D4E63F15B96E203D4B4A8110307D5CB3552810B9E1F3F4DA4209CF1BA98359F40E7055C7538ADD0AFB326E5F865B3F69E3D6C9F9F18358C0F6A47777B455B8CCE6C514CEB2235A7B376EF92482E2E86F42331511FB94A9038FF41FCFACBF353F3A43F3A79997167306DDC94A6D0628FC346B06166EE9D857D4B0C63990259AF271CDD8479F4B08633139663A1155340109B5FDAE255D1E4E21539C07249AECFE8E6AAC44A772B39596946BC8080D84453DBABF1E62843D179C1C38F1AEA5CF15BEC4A61810299632A2F3B9422DA99CB13C852B1CC6933DD52EA336A5A09D7D9F568CEDEF14CE1AECA48D92996CDB2CDA36A3C8E95F62DEE742CFF293037273E51F77BC208D5B345331E72C26BDCD0F51C9711BD899EE82128F834BB0B2A3DE473358F47EB2F98FBCEB2624A5D2697B86C7559FF40D14744C93AA2DD6570CC799C4B5669ECA0463AB0B4E1228032DC19A42E4F6C64D9EFB26E1B4E622AC06FD0C47B5A39123FF8F1085E4EADF768FBE9D5E12CBC5F380DBB414775E2836AB19CDEB19A0F653E7CCA9DE567D18020D19D24364E03C762EB54701E1893FFECA6D23A2163AA5CA9FC2DB681DD6E8AE2F42985C2D7E477225AC2F9C5274A5584E0FD90579B32D2143B89F9AD9576DF10A8E82D91C4987AF05F3E720D8557093A1DEC1D2699C2305651CAA0FD621EB48190751D74478381A499A61732B917E84B749A0465408014D249DC7D5C247AC0BF404B4311A25A55B2EC1301350B76E3F953EA2E67C90F1D5B9FC29BAAD30D07946AE1C2976A4FD32BEF26A2E93818913B36B237BE40EB7A907595B27E7BC80039683B3D28323F53B5521D244E3C87798478A8F9ACB55EC09E97BC5220F955057A889E7003B9DE288ACD5594AE65777F36D6C73FF5A17C7A8FAF039F60BC9E3EC54284384429C62EBCABCAE2E78F5B58DC7132994DFB16602A54B444B9A9C0FBA6F7AC3E357308CE2570743B8D2B5DE5F9FEA05A46307623E579195D6B5C946C47C57A14D5A6177636025FA555F700BD61FAE9822ED336AB21DA9E67F9E81CD815F2EB79F25AB194E8AFC564C43CB4CD8D681CD8F1BE41D9376668E45EA7E707EFE2E58BAF0CBC091DD427009B0716B819B857FE9841EC48248AA49EBCFAE706E5F8FC65076E6E871D6958EB1C7A357019950146CA8AB3821317C289C744450C293D3DB4B3006EDD727B5BFE7541F6817CF5467AF94232BAFE06E5AFB845C0216491DCEC3D603B32EA59AE651739D0E26138408A5E37A6E0BEBEE2956269A722AC36D7A3D2732486EAE6F8100C9A278988554895424EC080E282EAC6401129F51148DA16ACD7BFF0C1CAD9516F189AE1D1F4EC79110B942C026C6995A0AF85445AB9DADB1B2FBCA7BFCAAFE884AB6BA0717D3D7BAEF75D9A4507FDBBBBDBEA858EA7975118B94AF78E250F494205715B0EBC31755A38C1AA944F0D80452AD54639B2701462B2D82E522F8752110F44BD381E23C1EA52C15BF9A7DDEC0AB0AFE725B5993A0351737C1DB72989F48FB41AC479C777FD2E7808FDA72790640F9F741D643CCD0C1ADFDE90B9ACC84345E0B0739768ED8265455AF008BC09970B18D52D188AC387CC1DB7E47EF83A0108D39F7057BBC02E611DC34F9DE364B7ED9664A9C5C9D691DEF8E8FDE6C61484A097CF8A937FA55F353D439C380357BBD108933B6CC49CC5C5042D6E5FDF8F85BE9E4315E094EE569C5E3F38CBBED68948FC95226CE06ACF6D0C88408F3AC265B6B10BE10EF0467E011A5EF8F10026C7C54F8466E9E574FBAFF13FE9988E783BDCCD4B02BE46EECD77443F4CFE8969BF3551F2829FF2C0F8630DCF7B088C5BF1FDEAE2E81143D1573854D0D6D6F70FBB5ECB7C6E60F91B241E5543BD4F316C66A7F3C91491320587DA5CAA6345FC0D2240530BFC19AF88B43773FBB4A6369F540486BF74E3DC4DCDC4CD265C7C0D37213037CCCC1FA81D21EB4081C254C4096E044EB6BE48D07CCE2F460718164AE3B68B7298BB1B267FCC0AC3D0365437ED45C742A3FDD746910C1610E6CFEA9A17225DF2B577E790EB870F5A2190ECC166EBA09C171BD825D5E8EFFB3703746817908D299426DE95D605B368AF04D27B01FF5CAB91515096DE2986A0C575D14CF4224AA9523B661128740F19DF8072C917483746547EA422F8A3B40CB67FA87A7989A13C49262089A80B1E4113BB1EB9B469275D8BD336DE344318EB3310B3ACF8201A6F5F613CE0F2290AF5A8B9DD9A5B64AC8BB94AB56C36157C8EC8DBA4125321F30F753D489FA42C4881A3450DB8720892A8D3F52431B960A2404A748220A7305109A2E80EAD78B8D5C1F79D265B00C771129A2117DAFF0D24BDCEC32D53DF76A56CA24B6CFA0775F67614186D7513528FCBF2F7CC47D60C52580BE1797A62C17778DEE9FDC0B6D32585BD35C86276B363915D3D2E5A4BF58AA483891025522B572F4B635CBE94FF014ED19A017EFE0088CA05C54BBB6953BFCCD8D6F867769CFB02280ADE6C39BEE714EBBE252AE5AD84027F8F9C2CFF3FD01ECA4F051591B7FD9164C3C64386D177A74E17181CDD3C55C98AE89CC2C1A26B88D6FBD16DFB76742B631DD8F8D78B308D606B486071C30E81C25AEB864A822402CDDE0CF27FAE8B6CA16500775AD44733FEC8F10AE6677114A330E59FD52747B992113C53EC9A09AAC1C3646FC3760CA6024BF39B7DA597F8902CD605599779509E3F8CD8B03AB66C1993AD4B3317949578351B74055C7BAED3D7555B315765F1065414F39A7848DBACEA596C51D10BB0081381F7D5601DCD07D719BB9CA9A294E092376F6D4CC32B26A9A8FB5297CBE32CF4356EA70225CB302693A6DBD36C816AAD475815E9543F7DC8064C34870A799C32A6BF76D472797F1DCF908FC994604407B59C824AA76BAB6334CDDFE8D0227A383B0CFA2158CBC79DEFA98BC93A38DC0A0420C99B920BBA64DA16819A78F8BAD42355EFB42B4BF17C68AF75F7428B687334746245F7C5145B5272B9C504A9A0A3A985A9738BB1B42FAEEBDCE7E7962CF0AC6EC80F77CC5C9733E49DD1552812957E1FE30C4129A702E23DDEC09FD \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT2.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT2.hex new file mode 100644 index 0000000000000000000000000000000000000000..67176ea019e441c8172ab49425049e6f84c3ef95 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT2.hex @@ -0,0 +1,4 @@ +01 +00001D76 +36DC7A310D995379B796EB8F9CA346EDF60DEC7F6C00AA311B3E09EF96A6795C4B077C1D371DD8D4A538AEB78B81927D08008E817A6FC6B3F9B14FE56EF9B2664E76112F214EEE848E67EF33B4A4E26A2378E9480CC7D25C369E6C25A2673B946B635B6EECB5F5F1499B484DCCFD5165D6F14CAA8E1EC9A9E4FDE417403720D7B4BB30060AB95C6F227767D671B75A1BB5AC5CC33EF0509C69652748251869B072B9042618071233B48A9BDEBA330F0C450A2FAAE79291B9E2480D1CED11FABE56210A80C39F25E5574356CFAA32E57782145920D6C0D27C3AC7C63DED6A770A5A45119FAA92209F2A066AB90FCB81A886FB87641C550368C1B412E43F4FECC2FD659B2BDA6B7309797575DA2893314DAB058DD92C7470F570EC0B1D9C9A149FE0934D40182CAD14D5B3D98C4B7454CDD2AE7E54EFCD554AA5B458888048BD5201C04E7D6004FC2A597DA781BF15AAC9748B6659EC16602F10AD44145607917C3599A1F53DC95839086A6A4FFD66F8EAC8AF8F11C4F2EBA3B58C46B93D0494C4CDA4E8B8FF7278049D2B4BD7BA16BC57678219EBCB5E211D51A168B5CDF66453412565B9BD606CE29A5A70E60F3D451D4214B0A258D6E9325EA5196C55125F0E115B14FF34FF6B172471C2B4917FC36B0DBDC82D0475AF56249AB9297790535C0F0265D2A853DB0B41B418072D0ECC17CF91FCA86F6E10762EBC520F0AADCC3C79EFC25E9692FC0A66389B15ECDD1377A9C3D744CCCC4BD160FC65A45D4144DDCA04E5408576DBA6D5C875BB4071729361B0514E8B96405E2F48D47138D2D2DCF4DC865F717428FA1262DB0D2B7B1A356E9E76301D38BA506456B4AD70ED09B0D5A1375AA6E132D7E06F8745E7A5B5E4F6455F4282A87D2B372C40A34C09699AA8C2B2E060107BCDE0F9D99B64F17DA5FA01B6DA87B1738882976B21AE12D1BA0AEB37644AAFE5AC20E7F3F631FFC2A24EEFB61DC37485DF27FD9045BD9BB5D3F00B9B2694CB94B01E7A4F0D909B8612DD28BD64E6C1C5A612CB30DF6004276FF58491B8129FCB0B539CDF891A97AB58DDF04AE40BAA5781C3AEC65FD7E84DFD0369A53CF36303270DC80E3E428854D82B08C7AD022BD99AC0851B16C7D8D462DA21126F70D661A59E4D0FE4441806DEC48E37AC4A271F15D916135408A2751CAD53564967196763B512D52240B2B0D3D924B83CF482B5316B7988D73A16B773705097F5ECE0027CCB2C2EFF598B8F61ED4D6BC015E56D4549432A6A95328FE3122EAED0149E2144E4CD2262C7FE7495E41E0AC9FAC9A11E21AC940D25E74AED8EF6FECD21747FF8166589B7038EF1DD504F51E01F1ED911FCCF44949638AA6E8526F0B9DBC5E536FE2AE7D4DA9DEE66402A45CF55D0137FAFDA9207AA7E22FE396455F2F43108961FA6B0339D89EB8ED7EF13B936E3D2DA18E5EAE45B05DCAF5D845DC62CC55553E37CB328AA2C649ABEED0D862E8083962B81B84A85EC12D3CE5B600123AA7CE4764139BA7AFE5CD02F70D06DD9AB0BBE868070A9AACB951D362E2606FD940A8F5BE632393E0A179C2A62151A094901F5625D952D39D7CAA87B77C4919A8633458AD9B6DAA16D1B1CAEAA8075741094FBC0C08D30D9956812C1D3A75926C546ABD78A2B9D44C1B6EF8D6EC2A2EA8B7C23D0EA57E1320ACFB576FB9C575DA98B714D6B01F03364E618A2C03BA84BDF0E5D2A0403B1379416D87B5E022BD958B0C9170E82F8E9A727D39C8F7549E34A14792776AF0D72A27FCF63EA985B3882A717091EF35F5835D4DA127554B6637AC313BA3BAE8170B9E70A6DDA2DBE813A49F045D8C3A65ECFB4D5F71FC75AADEDAA91A81A958273ECF0CDC4512F0D0ACCF9D9D001A30D0B6B2D50BD216D6086AC5C9DE7388A7B1319F2E9E6CE128B1F72F765804E060A8A92C93295A99C66D6D79BD7DD4F7F02317927D60B2E9FD59EC3F95A874337228339EC673BBBF53BF0FE1886A4B14F19CD7FA9B771894377F904EE8BE48D64EE5D40882C684C81DA3198604FA599DA8D4EDEE8EC3294620B6555B3BC9627D4514DBD1F7E3E9DF7B56BDB4CD395A8CCADC184B2B8DEB2AC7CBEC6C96001EDB67E6CF6F872469B110097C69EDE1121D22FB5B5AA4CA540474630651A4F9E8F7B0ABA5DF568D882626BD158F925F8DCE1D81668EF7CF770DC615ED0F5A807E25991EC97BBF2F9E997A532A1BD82A2A616250D2232F72067A17550EE516F28940D8EDA9CCC0E02EEFA496010E499E62C50B03F1D3C1571342DB8A5BDE1F432F7B6163BA3AEF35656434937A42C4E1F473331E38467DEAA483189902364463832ED8C5E04E0195D3435A6FCE75EA3BDBDDB0A0319262083141B1BBC0C278CFD40319647E90BFB51374B0AA5EBF3C564EE95B7AF618669C935756AFF3150A93EDA92F0ADC29253758A6C8A83EF55F97F1A4C0DB566668F30DE59D93D8185BDC1CFFAFAE472E0B0FC4B1E16F0B748220EB2EB85EF127838D576638E738E9F93A05D41CC1264AC6BA03B202D9E3B06946CCC68DC15261A029B0C5E91DD81EC1D79BC51F74BB5EF778F00AC091513443308410F60AC1850F2548C8101DB3B6B4D453541E36F0ED57C2C14F465196F8F1D0D3ACD49CE3252BAA0C10521311B8B8366C579A430526ED58BDE92FED3F0B359ADB31D67BFD212BEDA7236DEE4615ABF13C856CCC93DD02AA28D1CE1F12C2DD69FEA828BDB9F4CBC9242E1017D1063A7BF842B00C75243303EF9060C8EA501BC73B3EE470919443EC91D1F0D6D0F23A899AB86F2E8A0898D318BA520DD15D9B24F4F10A1B9FC52457714A151E075BBE419E4216857500B8354A8445B5FBB526A6E008229F33D8DBA14DD42F424DE3675E704DB308048B2D17904DE46B76622BA08C62F17EBA3E9F414A1B10921858832EEFBC282755B319E176ECCDC32A25CC5E76479AC112570AA86518BB1E6CA3F46E010E8132C0A1E8273403C5C4D7046A05398D461CB6843D70EEF8C94DEA5DF53CA1A4C7842AF5DBBC6451554FC7F9913E56957C51E0A602D882BC389C5E5C7899539DBE6832B0AAB5EF26B2C96CB03D1795179A62F748CA501CFA34D5ABBAE3271AC1F005112645F10863AABB062FD2C781E4573173935B5392CF9E88A1A31989E1B8E94F77CEFBEC591DF6529C6D2FAB72E678C534C4EFF40177C41D02AF0EFEB6371835CB55AE0AA99C0653876CCB56ECA127A0A1DFC0F9EEB49525C9A5786F618DBF57C41C5CAA971A9505BECEA8969D9DB28B0E707C659EDC42280035254E91C522300368F49F2C36211E455FD620DC956AFEE41A2493BDB2B0B8AB78E0B838DA6584FF753BF88CA6A523042A285F84ED90E0FD5E28F75A21B53F618145C16925486DBF6B1E7D76585D0D117EC562E22239E14A49ED714814F01DE2B250E9B3B6A1C99D1A71CEDEEB3ADADF611C4A4F97E1B26AF9780AFED5783129FD58B1232C7E2DB9050AD3D494EAC254DC46B0461A1B4B63840621D45ADE97EE5663C9BD8FB7261152545AE35536611B5C65DD6D66878DB71640EA429F801D6FFE291B06062EBAB9B416DDA7D261A46E58B154684E86176169CFDC4A60EA38300C3D44F9A4C9DCA0CE1BF37DF8F786F28B5B3CC7B0199D3322CFDFD2CF88C5B794C69F59543FB985890471DBC93A313992ABD33691CCF69B96A9396E5F55B54FF7BCA82A31199E5E81CE94B6B523EC5C3E2F2884D8BD744CF0C072E29E4B542DBB370FA5966F68CB20ABF40619E76C099BC7A9A373707707624E8999D4CF0A75D4AEAE113D7823D7D2ABF54FB4E68B8A6A57A198B128DC69584D2DBA473B6725FBB8EC9561D6614D606ADC4FD9CF449008C0D54BE4F62EC1441FF79EB59442AEFBDF1F0976844B4FA3969EEFEA10794FDBE35E89EA52F50AB26319BD1604D3FF5AC660431F1073575ABFAEEA00E1246DCD1D9399939D655C222E19E9DBA5FF42709FC11E7E365D7F7CE2274FBF1738DC5CF5631547549F2BD4DE896C8FE039720F5E0149BD81533022DAEE22B93A3AAB9AA9DA15180EA071D98E9FD176804A5B04D089E9C2D386271A8B13E7D668AA74BFFFFCDA3B4E528937C41D43A87DBB46C2B49B63BEEAAB978415536A87D845F6C2484F21D71D0F904438C46E7B0A3C6DE5ABC01C6F7CBCFF21D3E74AEE96C20C32884DE4EBA0F282C0FAD06BD9CD6B7B5031F149E4788F102D2AC2C99FD09B14A4AE3BD6859CAFE6F5A494EE8CEA29F49D871B79BB66AA6E6EC3718B97E83765E96D5603B209027BBBBCB09EE6FDE3AEB65AB1D73684820AB1FDEF88086B93B6338BEC7088E04F5F6E520E3D715C6C5E5B79E73B9E7AE1C5EDEEE4015860CDB9FA21FB434C3F28AD865042284A7FE9A5FF47E8C6158DD83EDF28BFB18DD5AFA07A48BD5AF25B9644400CC976A9B0FE9D9071E708113802A78CFDAED28378AA4FD6FBD9390D8A17D6500A0E1835652C7E0B332A382576AC4381CAD51A31E64E5E24FEDBC62EF9D0CABA0C8EBD8B94625207D0C8C1C6DF4EA2B20832EE44D1E2DEB799BC97B7245EC404F10764296E5BC4A919EC24B4F5F7D18692FA8DCDD5BBC170A81BE7590B7BF4058DC7BEA0C545BC85F0B3F0936386C37115A333285451CCAFB8397F1AE1B56D0A8F884BC968E729D622D21FA26B89BA2726C91E6886838DC9912797FF2BDF6800665C1D1DADFA4A240BB9BBE21B6DD750389AFA49C5C366ACA5E9C3B31B358FDEC42B0032D9E2C22112E43BED2023B364DAB334BBBE2C3B669EF700702B5D1837A6EC15CEC2B2036D56B8760129F593A669FF00237D26BAD9F9C2F4ED4018D998E555D2C3CA1D53EAD6A1E27906353983D4408904E5FD9D79AFEFEC26ACEA1F39218C36637977F6E2F3F6211AA06AB9D5F991C76F420B152BC95C4BC10047E107CC82E3B00B2325ABBFDB0FFB2966D5FBA0EC7E8DE1DBCC053C4186AF23A6BDF3F14A7186665AC2682FB94B0E10516D500B7F67BE4BD2523E194A1ADD8B5564FAD9105C86B6D16B08AABA604419D55F571F11F4989197144DD12867D1636D12800D54D36FA88C620008095560103366711B8E3AADD5624FBC7FF51318D17311F02A807770466AD559CFDA0AE1439442E4413944855D4D0074D529CA8DD621DA02FA98F46327A7BA600387EAE5E724D64A82E94ABB760C891EE39F27F0CAE8D1AACFE20629DEC5DD9BF4CA91E65BF413FD2A9566B7DCA9E500C2C328F533AF2A957E46D9FB11F0DFE99127656B1D4BE20C946BAFF58E5FE1A9ED282ABEBF6EB35A35AF324DF0A858CA8AF507CE43D228ED81D863F7096044A084DAA37ACB6AEE98E5A94D363963D4F852B955C2F076848092E6199E07990372E56BA1D590BB83D0C7F834C852CBC39B666B801CD32A0C36B034264F3BA6911A719001FD0F4B63D2D628FD0CAD34B4C9355534A8A38512E758B110F48E5A09B504D20D178508E09B1423A1E61164E7D138B4A9455B95EC8EA786F5FFE67806781F1E619505FD7DDE9A904E9003CA7E5EA1077C94C228D36667031502D78B3B52C3B5A09FC398D8B5497B6E3F0C5381BC99DD7B11DADA2DCFAE352DDEA2C749F8CF5AF39587083C2C19576EFFE871AB94D1C7CA2183FABDB74B27A80FC4F20CB86B46B0B7F86384540EFF1C888168F74634F2C0BF7FB54F7002EBF90B6C4B2B25DFF068DFC7D087A27749D6C36AB0A33423044AE027DCA8C42678987005FB9DE5C2774924AD2A5A8FD2E89C288975F89B5C0EF70A20EDAD1925060A12606A9B03626039635BFF332A0E6BDDC4F5DDDA209AF8DAA0FEF045FBEA9523D04458FBB0BD81F65396938436AFF5FA66E997AE58D64E7B5C1B589558B3DFF6D035E31008D2C76CA426B07F1644F609945909DBD16559B36461CE882A361D0415A9D93CB98A5370C56913A299B2DD1AA372CB75C7E590A9629CAA6C439CC5C7D94A21F36F998C6FDEC1C1721ECC500ECE1214EFFDE65E479D38C635EA223286DB326EF9B19B3CB862C96C162D3DE238C2948E7613A0FA4843E39EAC51EF293AD7EEAFF0F522934C982890F83E922B2BD52815136D0A758B33641C54E7D4E0F3B19AA85859B750E7A7FB80892C3DAC5048767132E2DAC5804709B8560A4B3828B1CD25DAF263A2466AF7FE328ABC84EBBA26902FFD92B0D765AACC0C0DCBEF962E1B35B1195676E8A67ED593B23B2B0305B611F9E16633E77E3F31794C58C5309BA07DB5CF9AA1CC108186318A3F16A7141854C2FC8B469BC0F54BCB22976A3CA05FC2C8E23F1B6A891E7527F204ECCA0A5400B68565906E795FE4DAF52ADA95A9883676F9110B14CEEA389CE9BFFBB5D040E60D3D03C4E6D6CBE9ED53EA44B1AB6ED7EDBACD0AE0613DBA5A5C673A534D48B539DC85F48175F13404016C5289348504141338FE958AC28331853AE80ADFEB49A6637936BF82FB26B95295B2E46F4F9534720A4E86FF18B31335877C9CBA96A9B450C1C8C9C9862E51CFEDBE3DE5C8B901D792A179AF9A782C330035A14CE6A710D398BD28416CD72373FE216744F6237B38B97351A77D5D0DEA1A26A0A9A24FE15503240933E1CB5AF458E6FCA8624669A0DF439CD7FC13F7A1F10A0CC7DB8C6AFAD9C99B5FC45A7C565B5DCB74FF0EF426FE7C260D3ACB1E9E83DD8E6E11A642145BFBB7566D582D0540D7931AA28B7F8F682E6E2D90B6E6812FF8B7F15FCD3DEE686DF06E8E6C456C99C6B4215C4E874BCEEE3B4F94BA825C6A45C2A2B4C6DC04F8FF5939C74E7DA37E02D8230340C6E2AB7CB82BD226DDC1A7C7BD0C0FB36F71F9C772233132B8871A0D76728C2A141741C2662438C5CC7B129A6C8FC587A0E475545D176818B51190F0F19E91E05C04477283A0A7D4D646EEDA3BE64459780BAC1862D83E6B99C5731DF91F0CAB454E70A0D94D934D0CD83C8B8301DE282F9A1FFE49E73EDCB520C016FDB4AD02C261DC1A1E73E38809E60F91A4E38C69EC70D2A621DF0D21588F24CCD59D331C69E16F0F6BCAA8F24031DD5718875BD9EDA5B420C116E4316137D4B77623C9D73D182900BD7A0F90A193CD16107E692D469AF09F74702492E22C796B6B4A960D47FDC571B4A264EE3528A0F5A9D66DDAA33FF20C3101D50299EDA3225834C9429976EC8E590C6D48A721A14972BE70955EC1A0348D2F84347C1E8E21EB0C1FE67223B42A6BCCAC43648F3BB5464121180F8E3E682B4B664D91584AF55FD1C7D2E6F79A93C680238D29CB7FF36D259CB703DE03B2EEF6DE0CB77AAA8F49C61EE482A8DAD30824E603411D5F09482DC84BE794BB6EB65A7BC1DA92C8BC8364AA88D4B8212561745BCF3CBA0D6AC8B8AF80373DE3F44EE39CA3CE4C5763F422CD4E8827B1E7BDFF79DB990A52530E4A1E21F6CCDF50A322A086AFDF24EB5FE4D99F1D1BB4D6DA965D168E9726FF7A4C82F327A748DDB1DA5A3D0E9C8E0B060872B009CC9F913D35D94FAA912B0D6FBF233DEA3AE3C2A4E35BBCACE21CA3E5F7A7B9A486AE9D7A7D2E0B79FDB11D87072F1B307402BDB22746B86A1A0E6B41433D5BAEB2048ECA53A1ECF895E9EB9BC5D6AB5D5DF72353566BB90578F12C6A16A163E95CD35DA27C79379756141DD05C315B466871E2B726B8821FB6FB439B49430CB3CA47CD211D03DF40AE4A0BE87B6000BC9C75AD23552E2129F47AB64BC9E5E1620C99405CEDF7BC059547D547E2868A6D470D813AA5095D0AA4BB18D91964988391EE6F05DD47CA1DA0423CA238C5E50D43CFB0527973506B9F1DA4A8055C47D1FA1E0DC783CE3CF75FFAADF574EC2849631E2551368291AFB5F2C40A4F1A184E37A19E511F482B7920F6D51B13065E6327F3C21DAA7F73986F2D1FBF375DFE2505C0FBD35F403D253BDFD0BA1B00CCC5A20B683D4F1E1F2374FD914C7D674901A0F01BDFDC007E8021013BB9A2F885F0699D16805F9F2511A0C7D3CDC06E36679983A2A0F12662C88BB7DC643FBFFB58CB51AAB3CED28553910D063ED8FA37FD756B79AE4151521450E552E4F2B62EB6F6BCC8086BBBD30331F3F2534AB3ADEEACCF2A6E66F205935A167FA1D5C747936050E276E8E4CCAFD9E0A056E4AC2AC08738BC3A598F07E933B0ED285BACE3D24AE6FF7574351758F983FD7EEB3944473EDB4EC9A9828A5FC656BBF04DC623C75F8B8038F3699BD5F255CCD3EEDE4FEFA12AFE8F64436DDB1FF2DF100B09BEC657DC5D2B18E5722D5AB30D075D9A52A576B6F9FC8C8BA3ACA6A92E6596F688FF5D2A7E3183B696AB277B0B17F004843E58760683F90BE0C61DD0D1BF9099A865CAFD1BD1D8AB1B7D4AF2F86D51C18D7868BEFF3F6C53EC68FC46EC9F23D1AE1FE85CD97D8CECFD57A562E7E574ED1D0A7005813EB980C2A46A98CEC602C0E022E87D4A6EDBFD7DE9FDA8C02EF85701BB1CEF6013F4869D32CBA56B0AD6EB007591D03C76A839F9D01985C546C39E49D59395B10346820324F3E298C5CD977FC2FF83BD422CA550DDF2A69607BB8125647B389246ADF0095F22692BF907EC86BF8D70D7E8F2C50E35DC6EF34FD1258E1FEBA0B254470D43C77CB0073AEB2D4CE5F6772D49A101052D8CE943E1C7760F2994071644D27D26BACA88EA07F29B2F2050BAC5E05F2226F1F584D17DB80E4056B7F9C60A5D9DA0CC577C6BC802FAB26E570BF017DCC7236A1173E273397E373640ED02B4F9863C40D2A2A7828C3875D8081AEBEF349143BAAECF9089EE736EFF0EF80078D2CA7942FB24A92071D229A1FDD0F6A87D362E5165D57F62D927757BC31964B5DA63B90EB3591552F2B9902E2269A163FF221863ADEADC9BC92CAC0087ABDA02004C0B9F34E5CA8599DC3C4261489F7527FD27AD2B6501E602FDE47DEEBF3F3EFC0166B1EED95116CF43C8AFC0EF89BDAA9ACFB6DAC613770DEA78960C99C9628C0D21FAF63A0FF7A3F2733EDC0FC07B83F107A811BB3C1DFC6CFBFEC105193272A4BF915B1DAEB232E16216E40FD3F9D9399B15CC4C073BAE8D08A4EC42D91609574EB009A9B52F06D3F428F6EA9B0511D8319A1B1299C154C94B103CB586370A58F18F04F5D21AD3B638660D6C04E99D356A7289E37EFAD643A5EBB488D54F4A0194FBC4283A8C4ABB8D9A1D70150AA50F991204C038AF54B5B74F722CD6515045D62276A9E936476F42B282C3B08D9328089AEA259510240B95BD5E81FB9D7E006DCE0DA832BD9A833799E05CAAFA6305D16DBA4461BE13D3CAA95773B98F09230F2DBE13936495C2DF5BE3A8F3EEB4FD211810F4B07D3E2BE1A11CC87079DF1B32D44B6FE7942DF2627AC19FD9F584E771D7ED98AA4C074A9DA5B7C156F83D90EBBDAE78D636D51EB0CB30C7C7CBC1A96273C0AE0ACAD8E15D1196BCB2EEBDA332896BABAEF76B4275F863732D646C24627AB014AB602A47594D6031795B17144E6E2C23F0341422886C1E2512222ECD530017DA02FC015EBD5BDFB319F3AE942D75A55C21BF347A44B300ACCED7A339007A2527EF4499E3BA5DE334BE58D59918DD0CB55B2F478837F71E9CEFCBBC90808E0BEF8CC7712A3B008B69476C61535FF0787B7833B70C69B1EF506EC4F445B72AA12FAC2589815874E9123BA13A17477D61E41163CB21ADB8151658C99F1422C71A8183B8D0B1D489EF436564C47ED8482A0DE9170CD1BC34D88CE76E1B47B84E770020125F718B4AFB1E4587668634FC7464114762A9D74A93E33A5C0CDFA824CACBEB097B5CAC3B554BC0D41C402812D8E43DB37C730A6219AB6F0BACD096BBF261C78E991DE0A2278DCA7D1BE0E5F2FED72CA38BAA86924A84275BFED3B91FC8DCC5024316EA0587C96E030544F631076DEF65F05F98C7641A958313686B8580CFC20221ED50DE4D2CF32461FAACD0174AC46A6949EF8ADEE6FFA3F537228AEDCFFDB2250D7BDBC848AFDFEA67AE53CE9ACA45F349557E81F70F9DB92926FD0CED8C104E6B7AD180C7B3BEB86171EE84A8DD2C243F6869E04C2DAFDF0C938C0768415C56330C9BB6EE756BB335BAAF96EEAA5CB52E554E39E2435B0731B0062376F4730108DD2F05824A798DA24C239724D19F12C6F2FBDB52652352021E0167F31E0F5941C4687DCD13A81A20A0AF05A55D2533280941865DB4D5715AEC293A64AA2E5151C8F44A14B72C0879499027E67E4E2B487612216F6122361E8D34E92C2163B0C88583E3887DA93A3AA0E77FFAE3FE8FD5455BC86AE6D6D5AC7CB7BDF156A960C98B0BE50E1370A43E7D183636DEB2C64B264FC5922D4BD46A8206F911E7A742E72E4EBDBA39B6151AEDF5A6CB4157B375D9A59899808F1838C61EB4388B923423D3879E8228AFE0CEE9561135849A89363F84B41BCB166EBCD0E65A2A74FE710F2B3B55CA9DE2FA9DC163BFFF4BE91F10493936FCA15F5F39422C75233DB22299456D1EA3BAC26F6671557B2A5FB0E9460997DCA797C67C49DF109CFD597BE34C8E0FA0353F28B815D0CEB31DA93E49EF29CEAF20FEB0A8F5924DCC62E830353463245899900304A8C8DB5830BC0E97AB83853D8EB05660D6A9303833D170E138FF6F1C30D9DD64574D5F875F974225DA81ADE3D97924A38F552276F46A5208403AEF82D1E92959675EA6B353E5C6091034A295D9C12C288241055A2334C30DF0A37D2590626A7D1787A4F591A6E494BF55ABC76842BBBD508FE54C5630D11C54386A487A756ECBFC0AE8957E7CA8678D5B9B044117365AEBE79AFF2E6678001D23624 +6639A514256A8CA2D510FCACD916BDEC6245D3AC11A035B7C7095BA4DBB92C62A8D0C518807AD496B31228F96E1A2A23096EEABA09D37E615E24E5965E1073DD0192B175684B4F326189549EE36FE38AB2CB29380675306AF7FEB99B2BB8A07D5BDAA761EB9409F46E70EAE199F0B3A72568BF6964E6A58DDC6CC223FC89E27C104004C328694148109306900C0085913042D4B211E2922D60A80C91008512101118C04492344863824C81C20DC8200819C051640444C10470E42286618424149040C2344292161009400ED0203012B10991A404A4B24011A848191800DA128D83803003182C03A5201B4066D9462102442484880C09A20C1047689B140914B70C84B068D4282823885081128222326CA24882024150A4B04C44264059320498926924496950C0841910840C136E1AA10954A2889006864222665C026122304A20A36D12486181306992368509304A1416210B064EA3320403014D918885012051023701101411D33840E4206CC8A888582484444486D8A06C03C6499AA67140804518216024850001896522483222932D18052922344954900DA49890233351C434852025420B230122044D9A26604B266E8430011A2889C120240819461AB76503B50554B2605AB429091591E2122E1A320EE43808C8880D4AA264D3960042C06C24C92959C024A220208C942152B06513286D11B440DAB20104B84804A50D088650A4386049988488A28108490A81328442388EE440021BC811A1B204A1482E13B2842007501B288A24A9092109629BB465002966C44682D140459BA8400381108BC8051B826820466C40301111C77140C89112394444B60020992901178D624202549405D1320502872D02164598104249A0114A182ACB3802D0944552A441C11641C986255AB864D1184EE4B44D821224E3086A0CA30C5A18100BB3900C022C194780DC126264248801B9880A265110272C142025C4328659124423262D0BB590E28090A2385010042103876D61284618C38D08A10D922684D906501A33611B8468098830E3844C0A4424222640CC388A1C05110B460A24004C02132408067224C4611AA62409358AA4C6112322629C464E20964D580430CB388603B44C64C42C0000095A220DD206655040415A2864102510C4300E24A46DCCB28D89180D1407714AB8451413409B323011396C5882005890911293081122850BB94012050018C905C3248520B34D08964003852D8C220D109270D8464ADC34301424840CA480522282D1346D8CC810D4000C22850491B224D84688C084450AC30C1987111803618CA6644A384D09C8012092040301121A4722C1844823A1858AB24DCAA841A4160E8B34889C249280208849A0851C46290B1260D804604B4451C1C2911C0729013381E2C44019962062C28CE39220031824234202C24006C82264483466D2B630DC90880199054C242804424A5B0628D3866C1200896424492025050AC680192921E088812413204988448A368C20A36519006C00410E23304A18A04C0CB96C8A46210194105B82251B05840A15840A185059420E93C289D04611CB0242118100004606A4C28D1145114C186A922260093921A4941154C669534625898208C0080E4848061197411AA36CDAA80C0890655A2284DC380823A44CD04680011370C2840C8092249B1648C134801401445888215B4620A1A84D0BA04D4006061CA769D9380C1AB78D0019669212911C020E91A0909232515C224D243662113242CA081104A950E4C02020C069E3242E0C3109E4188518427261B84C840422A036605B1486120022D29881A3900542480613A54914228D4CC44D1B112994403112C6894C06665A384411499083904864C82D8B002DA3142CA2320261303044342CA2322E83464A923885C424690CC60C0926528844300416600C0741D0126244980888228CC214704B9069C1C84CE484440093449A226108850102C2212342282234650046698938660B371160840D58120C09102110B4451847480C434D1B33111C990459480D90260C0B464259B82C9A200D4416062139310BC38188120508806113396604318D8A928509372698380E21C925000384CC4228933031D2982C5332461BC10D5894451A47118490691B386083482D0A8921D8B82941928120156AD212414A90250C248202310DE1346950807101106864808004A5604488712216244FCA3DC070EAFADBB8E253BE1E85890557BA06F6FE596C9EFA6CADB19A6FF51D64B2F169E1FCAAA7761B8E4E94A6DDA9B390A96D7C0BD5AB3282F4F4E310FF1A7745741B15A80D1DB35B18090B1C35467939147179082650854D3481AC46C4D5F372ECACF58B439D2C8E9BE32AF5F647C4D1C8C06C5FBF01D95D35E4D7EB2D0D0FBA5B152CF08525006714C6A1DCC41281FEA9C16F1950B66DF989AD4671296C9BA6E565227A47EE10536BCCE94ED83E57092ADA82578FF23FE0C01268FEEDCC0953EEBEE12BE828BE36415712733E973D6A984747296AD5D24CB48002483869BEC1AB4AD0487BC6AA09CE9138577A5CFFAFE08119E3142803CE2C88D83CC9A102560B8A2BD01684F0C7FA1480421F4372F88CE04C3BDEB9A09FD541C17C67BF4D06781B6B8AB45A7C1DAF153B5CA37C1736A12B7999E05D213A2501AA67ECE2B92710749BBC902E550C33FD2A265CED7D3A88A961503E8C4A586867A9A2AC605849FCA19DDB92ACF22D481FE8A16B6BEA0E916119A83B8826B7B64EBDB9A8D7F5517A8812B9369EF1AF29818940FF4C1A41A8193BEE2685866B887E48DADC162929938202BBDA46D7FE090A185883192E45464E88026AD24C12B37FADFFC15956F0A2BC1AB5E4917EDC664D3B35E3C9E2CE2A73E9CF319AAE5A1EA8161B747989D2269B80E82086B677D417FACA39B64DE63AF8DEC028ED2713E7EA645A9367DBD8A4BF6E52BD45082712BD30A12D639DFF1069EB150941EB3204FB5F7D12C655F22594A70AABC428131168179AFD776579865A2BF65988276B9337B553EF75BCDB793B67FB602583A879747CE0169B72E2181C6BC1569A7353BF0476F7DCC04F7410F1C94C6C1E164E2ED651E90A3288EF61DC18B89BD8746C0491F680EAABDC51B68139E8EA42ED4CEC08CD60093D18EF38E26B1615789EE6206F8996B34EEC3773C098D61C0B4E4ACD835C98C16B0F3DD0A8145E1A74889297FDAF7FF20519A6184013E9773BACDE0705496D3B4103E5240759EDB954C9E77A05B20E4833F446F4CC447CF862778E97A388312D7AD5E0D2626B298BEAB7D27F5CA67EB73F3CDB03ED0239912590C787F9C3F4B04B170C6582DF1FA489C7F8FF48E78C3AB63EEB5CA0CAD4BA17AD57EB6181FABCE3D00D31602FC3ABDB1231EA961A5F64558D2678F963E603343FE35B4B97B60E102B95BCE07BA525F4122692A28F891A77A87F07C6444AE92C621875CCB9A973961C55D920BACE5050C42938B6FB81663DEA18FAE1625B13FA3225CC80FE23D557C35619214E140A55CE2ABE8BE2D82122BDD702B5263498B9C2957CD3B2D933F3C62A0696A0CC96D99BC106872F0E2B6E70BF9429530ED9B97E68C4ED660456D7A79E37622C0C854187985C9928850A15FCAEAB8D8D9A3A7CCA7C13C400458DB650B0B37C858F52B04FF135B6BAF86E4D91DBDFFBFD6CA957B3E1CBB1381AF4118D9FA13B70692030AB19C8D068ED620D8E7E150236B8B988C38B6D4002A3B4FD078F58B96A3C4A996A13F0C6190F783C6E6AADB8D69BA275D7045E1646C56C8024F8D1CDA3EBCDC42877674E480A070BC26C118504525595F034B4485CBB9C4C48E5B5AC4A250EE8A98A8D0448B5581F9AA1F92BCC10199A0A63AE5AAF39D6C2F82D64E6165C9878B3FDF4F3403ADA84A57202B94F4B65B4EFB551477FAC6338DEA7281962698CC54110B8F15D4BEB4C091B845306024445EE008933A8FFBE63AE3580E098A18FE33681D926D46AA99F5DCD9E9C6AF4CB2737036BE094EF63C0310A42DE5CCBCFC75AE57EDF5DEF3304BFD6854405781FA983BA2B582B631E4773A62CF8E3B222F9FB0C484653E7DC89851C989F62596377E35BA2A05F544D6C2AA1FFB71365BE259FA6AFDBB797D70C2E40474C2697A510E9C277133B26C2ABC03786589859134F5719314F392093125F15EC2334A2833BA6F4E634DE374AE5EE93E7C6FF37D978117122A19F5522E63D637E6109BBB80C95AA807B205B78821DE56BFD0BA9949BBF0A58E2D3803B89AC37DF91955536C5381D81377AE430C261992EF2501AB8FD653D715C93F63A98C7A00667AD74DE5548B685BAA6D301D4C6BD9E40F7B50434D8E88AFA19F73986CF55E5F318BC5264F909F8DCE692637FC09F62E9CFF2AE21FBF37698736557ACADB9E782B6E60A214216FEA674815507A12933B0A9DF9165180579072283F7351FD9696B1C7EF7713845B3EA3F618A0E52ED23273484EF1307E7082818903C5AE7A5EF2F11E5D1E813B8B2796D2E134C43EA733DEA8EC94CA03E64B0C06D7A52C38FD63658F549E49872BADB78020B9DD64055EF006D5D92FC0642EBBB025C44F436B9586C9453FDD9DF65B94ED020A5F647717881470C0C27C266AB56C3115E4336633E492893DC34359732740E954B74606232D2F6E988CE1FE565527395CDBF66F1CA04F42B34DDA2937857589E3DB5FAAE2B0CC97A68408B2D73089AD0098CBC66F03BEB12FF72A00AD72C5150BEB7760D700D634A0823988D20BBE9237B9E1E60737CFC7A97CA65AE467026E3664D2D2242E73C3D43AF26D33828358670BFB69A3480CC4483114FF22D93B452578CDEC1B93C732910438B66E30CEB14EF03CD044EB6D51E5AE1242EC49F176A4D888DCDBC6036163160D404B5B17F194BEC4A1A8FFE396B6A1E3500D2C1B17CC8CCA3F105A397D62B4462D3C09638B01B6A60AE76D93A4D7A204F8CD381C7ABB9C06F9B4F835D89A69A5F0424052C19D5AB4FED48B4CE549976F68BE60C54BBD5CD80E8A0DBF80A75A961332ADC8377CF2A286068B8E4C7F9BF85B2FFBC9FF2B9307BFE33070764C49EE7B2DA597BAA459C4C0C1D5BDA7DA4EDF5DF2ADE76F44A2C64576CAC913BBA0059027E98666DC03610189BD709BFE88F0AC93224DEF65D86FEB422563A83BA823F9F312CD13A7707275E3701369CB009EDBF95E966DB3DB9645F493852DD1F71B025102D2B5CBE6DC315DB57D4E47C9FFC1B65E0CFDA0FAFE7937459DEDBB5983FF57ECF7E1D38E9B67A0CEB91FD7CE01DAB9FA9CFF2A4DCB19C8F74A4DE51DF1D466A44FABFADED4CDA52FBA424B312A873D29DC420F8FF3C94DA1C896E0D54F8C882BAB83573716DEADC439904093EFB720A1120A7CD9E18DEE7B6674466737C36948A4EA961AD122E3C461FE6D5A3843262A3845CBC97E37EF41BA9274D0EE4E77CAC71DE5AA39E860959E353AC28D1A545BCDF977BB4BB7BCDED646BEED12A6E03ECDBD2FC3C1D845D5C9299882D15A295AD1D39888EC943216CC0175AFCC605938A2F72EA01F1B7BA77A954FE1CDE49A7B7E224D1807E81BD09634346DE0ABA64C0F5B3D2E6A9C47C497D28CD231A70347DC9B9713E1FE77CF42DE2AFECDFE081395AE1E2198E2C8D5FC05606D648F18D3B5E0D96BA194C1D9E4985506F6A96C48F1CA647D478EEDAE301E86DA2D916A41832D28A6315A2B95381632A3CFCE232621C8477680D4DC096A57163E4B570DC6AA475577A60166AB550437AEBD5810B523E4053AAFCA5D5F702F26C6FEFB18637B23606568C43AD1047AAA51E84178814319C6FE2CDA8128B7156F84ABF9D11D201390283801BBB87FC2AB6B050539D1DF5511893F809CA261303C54A7C8BF4D433E330ADFD495E3D36D61D469BACAE8F1F8814777B3D20B4F98EE5727C1826CFBFBA2E5BC624C4ADBC32519B731A666EC67D082570B1739066312284C1F560A9CE45EE0E576F5269EC5C325667D13C3A62EFBF24236A0598F973CA99C53DA3E5D4130FF8F4791E5A900B0B2FC93364B234F85926BDA82286AA1B04A2EE280357CB6D2A464E8DFE9AD6780BB2A6937F008DCDB8B64A904E9CAF6B75A4A3341D068381D6C8646992A7AFFC4C2749940FC7A51D4C7195F291F8A1E3C4E0C7AC189669269036A2996B9A7A1D696C35CEB82DEF7B4C19151E1DD8AC8706E38FFB945907D2D825B06F65EB460A5F51CC9B17310FB878D73A436788DDB87978BADE32BDDA761EDB2CABBF9D44B9E7112BD8D158B502AA34F7326244E2FF83C778B5AB05C2A8CAFA7E218EA97045C658152A21D8015B4A62B27ECB39B72CCAD51F52D3F323EF61F35304BF52FF7940642C38A0643181A6DC6042F8E4D87BBF40D04770899AE2165B39C2ABE3D00E41311FB1B3DD865567F9C60F5FD03AFEEFAA9EC299B50C1F378EBBA3700DF56C4EE64548C29A6ED299B8392DA122204FCB5CB990E898379DC6CFE26B6C37FA4F25066BFF6E296D1EDBDF8578A5E939CFB07EF8D5040DD3F46AA3152D5CD76285F9F864664E465FA66E338CCA55557467D6E7B443478CA00900A6E14FB8C7FE7F27984153A3A1CF070E91C8E520D1F6DC0D627AC966D6AE8B3B10B61BA99F642C0945174E3D62A3448A0F90C3B1F7104409FEFC05286B4AEC3BC389698D500E199F70F8374AFA60D2B4F83A22813F8121FD99E37BF310733F61635E4690B0C6D0498563287FFA83F2D677906A4CB0630CE3A768FA827125B8E37A5F5C855192762B8ABDB0DE0C94538E441620CA1B3F24425B37F7C13A9A55EF08117B8E5D2624A670473741449647E2997BB4F7A1E08A2D58ADA29E80F453C271BE545F2939E2F95342131C2C9C3E4FCD52C24F25D3D3C6B040BDF0B8BB0FF47B0E4A6EA11A3F3B10B68E4F2225D5A5E4946E6033926EA55A21531F7C344B06E42B49908C8F3D43439E949FA1 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT3.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT3.hex new file mode 100644 index 0000000000000000000000000000000000000000..0888d6790d5e80989b01d7f1879ebe9c8be5a3f7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_input_KAT3.hex @@ -0,0 +1,4 @@ +01 +00001CBD +CA0104B9DF99E87474389167359968A307F63AA32F0C804A96B18FFBE00C748B1D6894CBE2B7BA06EF17B6947ECE31DDC9F614348F01995FCCE77099A0D88B2BCD1035667631991C2BCAA4C86B4D31074A2FD46C38429B52CF0BFD7CD3E5D194DF22E2B0D57C0C9D624C772B54686AC963447E716C6B4DAFC00AE383CFFC69A2F6F931D616954BC9A140D785F15C5DB28ECC793D88C78D11F8F8452046ADDD3AD26988B21BF895DC810739FA7C45A8062B2931AD363B0C7EAB4CCFAC71CDD0DA3B54CA9A6388DCBF79AF799446395DC7A5B7ED1788188E9D03EB3BF7B80F8CFB9B7F33DA0D4DBE1840B9C6C5D80F6AE64487BBFEC86C596E2ED8E721A11D783F7552A4B01FA24F60B5B683E287BD75EA0DDC15314E014D402F527C5DAD74CFC49B4D824EFA77C359B90AFF15AC89C1AA35959570E2148DF7A09E27E2FC096AB5CB306B4868AB80A24DF745DCF9EDDE57357866182A9AF50796EAF97A1A1051FFE6F9038BE1F6239CADBF0BD81B23E2991941F34D0851AFCEBC4D3F8B472D6259CF61FFDB87F79928C66E69D969B254D57541A87C692160E5D58A837A1FE90A1799758A70F958DBC1BE5D6E6836845940C75E745245FBCE59D1F83462B9578534D7A05DC3F21C34EA93ED78387B32DE09ED3CD2A51EE2B8F7387C8C2D426EAF3795E99B158D467D9A039234FDF207D65D2577D1688E1B1E72B5EB096FB6377DC8EB6B3F51900380BEA561C03D546EE242EB4264C0369AA2D53B2B190E0422FBC4CF896CD549C2A08A37070331F15A9ECFFA0E91B1FC4D5157418914308EB8C6A992B197F33DDD517DF4610E88F2E35E505BA7C7CACB8E76677CA9B39A4094EB4590F6154FAAFA76C1D95D4072B5CE01F42355C47AFE569FA80142EDB49E2ADB34D3C356F4D882A52021C5216B3678AA6A5D52C51CC8BF09E7EAEDD2501A9886FAC977EA5F385F46E8718D39073D8995D392074C2525A4ABBE228F531E6B16AD5BCD5EF5CC4C3C71AA77EAC1747E2B763D0B3D66C7F35458BE43369BAA0ABED23202B733B3C7A111F9CF407A7D62EFF5BE3A5DDC3E49AF130012BC6D5D3641EBF268236473EAB09BE87BAF7707546B7AB194D2ECF5B03A56662B1D6462898DA94747CEE9DDA08A9026538D799F163E1E771EF7EADF8833C0510104FE7AD7EE75F44F8D4572E299A87FB17429718C576B29983B50FF81F8D48D41CC764809429A7CFE05F68168B6B36FF66CD75DC0021D774D07BC716A74F9450EAD2995089FEB89D1EA73A9CEB83155ADBA737B3DE33B6B617EE7F5CB6C6672AFC439990B612A6AE71540FC6D7FF535FC88DED0E6A80A484735F63209D39F12E6E129C4ED2EDD8C8B5A24472B83A058B0F1C86B7F4C53D88927C7E9EDB5C40C5D6C7F0ED8A626C5F35E1D3981936F0F1FE4E8CEE0FC7F66F0016B14F3D1EAA993A5DB9B92C03D99C0A867FEB343D9F43BBBBBD85F58B2380811CF153FE66E5B5DD07D5A87ABCADBBD472692358777BF17AAFB622D487A100062465D9BFBE0E63B9D862A02F09E371EE820D969B29B4E6F6A1120CDA9F9E3FB804B26E2E9C3DE219044D1D6E62A28CBC90C262B76914B8929465FD901777F6F5C112D196A002A0F4C4FFAFD2578B5CAEA21452968400DAD6490E313D32A708A42F64E9CF412EC0E358F6B833EB0190C5933037202C266ABAD212B570E609FB7D338AD3F850EFDEE9347EBCFEBBBCE90E7F27372E244C3F035D4ABF1008055215E573F0C4001FFCDA5E6B6C5B29B7F59132CD86481FD0E1245EE4084DCA3D44A0C9E6B6B14E1BCBF56F470F15609DE76588795D5CB62BFC9C253EEFCC155C116D70CCF9112D8E0A801A3C640C7D16634EA02DA9DB9AC57DC2F7D43F48ABE631D3438C2BD3EC97832244E81223EEE47054878BB2472F64E9ACA0D5A8B0B04F783C5052E0ED6AFADA5274C94084621E989084EF9814128226346996CEB6FA07FB957C7432878505442FAFC4D945A953336F9C92B8ABE4E4A092DA65E2BF1A7A274E1EE9D7958E35334D9B7CF8B314F0AA5C45E93111460A8F5409C0BCB842DF9C9887FE4643BF8958CDB40EB66438BA53972E359EB712BF4C553D871ED702F74C41D1217D7887C891E49043C0826FCCEB2897BFAF9F217DC9F566DE1C416DE9118491162113E2EB56CDD4C024DCA4A33359D88CB0247BDD6802455063DE9666A4C52075359316B3B557D42B7C99700F55CABCB2B802AE4209C6B937C798433AF94159A4EC0A7DE00C809F6E6675A4213A1CE8A7099FB7FE6A0C7FB383233444B64AA120BABA1C4E61C6426001184E897A3C6B0BDCF9759A72146EF848EFA65EF09076A4FF2E6DA518C5A08F2A2A12D904C893297234E53CFFA04F285F350412456C9A13E153421D65DD30B236653AC13CCE3D5CF1EBCB8AB46808414BD3725987D6E464EB4F97321595153DBF9994F7E19AFBD19E9BE929D18563789567B28B1AF05BDB5D2C5C289FCBE8EB159D0017E09DA8FE5E9D49D3A231814778370DFE703ADABFB175859A895A6ED86F9B6B52CCDBBF936622C5E5A01D50E2B6D5730EA4588680EFCCF390211F211472F9E10314482CFB45A24706BBCA8CB515B6A9AA6EE1D2509E8F9AE9D6F545BD3971A02CC26699608FE1F076A925008AB6CA8576CC5A962326A369BDA8ACED3618F02BBC55337FAB2D66050514F904083D4386B43B6EAD553DF5603201C6D684F7156FBD2D3DDE3D7EB0D569AFD42886E57B747F21D44B88AD58FA2370FE6BF2DFA4D94D8FF983A1C2B89876E75AAE3828D1306DB9A639D052EFA6A0EFA0F61737CCC45E0C516815E92E256BA49E7853F9E9D4670593BF9402E59EE80F6CDFF8244D156FAEA8220D483601794A3CB5E1D7B60DCF991A545D2C72F62E5EA05BEAA77FA86A80400A07B97D8159F0EC170913ED885B578767CCA7A5BFB8BFDB7AC99002555145D9DF5011654700D6FBF2EC2BA609C969EBECFCC0EE346FA01B6CF07E6855F3C832BF1DB6E247448438BAEC055FD41CDBE921E5F62D93F4E7964258A9CB3991E8084BFFC2E5B29BD1E32A64E32BF5E27416CBA7FA3DFC143281F3797E1927AE9D9E07FB424833A7911C23F231D676EB0FB061C179C72FF0038E48068D43A805D56C3B6A16F5A2E5E8457F1A3E0F927A8880CD261F0D0AD8F82EF0E52E1BED003661F1D4510F7BCCE680CE84A0181F046366126A53EE67C7309C6982C28966B6CA1F324D03F5E09AEB111486C44B6551B1C36E84C2A72F78AEF5CA31AA66EDFB0792C00579C0C7C1FAE501735706CCFADE03E9A0847E498A24AC1DCBC7DB8FFC946B8D914633559B63E3031C214414BCC1921D2A53726695340648CF6C2BB4FDF132C77BC39E9CEB2E4D22EB138D807D7B79F78CD9713F5BE7512FD32E73E886DE16A9B1B19026B91EE6AB92DE4DE663D9774344B283149AF4890BFA57ABD1C9DFF128F9F169E4CECEBA0FEE1C33D4E34B877EF04DC887F7109B2BA65EF5732ED4B7C6B33131EB5867811D4A8A3536102F5AEFCACAA681A6A45A3BDCB24C4FDBF49A134244044E2B424996CF6F3C514C77EDF2AEC177B8F80A1AB77F6D3D920E508C76EB71ADFE2209A132839E9BB16BD9991A545AA0587B7594E0422647DC84CD355B20983AD582324D4F19E33E9CFA5CEDC739B26F43BBAD1F165720306F48CB15B23B961E5990C2DCC39E5BF58A9BFC10829590A7AA8F60E13EE1DBA85EF5EB9B1F6DDA891ADF7357E16CEEA4ACDC00E20F8F364AE3EA838CB4A0FDCCF8B439A242F8D18B8E0B9FB8E074922E0C25922CBEC46C98A82E93F0E95884BA9853CC738AFADA3F08BFB66C17DE7977EB7CE5495B8620B537B49D1D37EA4B3477B79759EC7D9AF17EFDB2EF89945D453BCBDB349CFC623FBDB8F125EC492CCBAF30006523B543B6A17245CDC5EE7E28EA895654A5EA74781CCB0F30343C73B4BB88CE07BD37DE9220712F11748EFACCE925626FFDD8447D37BD9CF2476437C093BA4CC0AB674E4CF9543CEA67BC25B9BD56946C0D077F0849796EFB74C7F66D5B86CD9A38B8138D816F677CE08DE6A6A911BA4DD1834751548578CEE4CFAC50C11D685E52DECB77A475FF5468C38DB23853BB2118C78AC3D52079042FB7F370B3D0406E402EFA6432D3055C572C81DD999876E8306021118BA87D5D430E4AB9C24670EAA1274ABF4BFB8149D9067C427DCC026A61C5B724CAE1858ADE366FB42CEE52C36F0F99AC02E8BDF784EBF311334B83B2B277982519DFFA3AC35D97F9F30635CC17BF8E017EC4E209EAD104B52C58E8762052CA62BA7A82FD011860E4F298D889A11F6A2BB1B4157CDA42AF9CCD0B5324329A92CB9FD6EB81DB3FC58431BC5C9A6DC1B07F7D2B00B32E5A39960C5E2CD69CA2914F23365B518ED746B27733D713E8ABEAF9D1FFC6D3D9B601FB386A6911F24CC818C0353658CB826F43FEEA792055720065601F1364BB6184699F16E3EE2B359CF0642C85E9115B18E55482356E2F91121C5884578F3D2C45462E47A3D477B3D63448A8C1679E68F9B7AE509100B7B2B142FB6BA20179E599259414520B02B745E592FD10D0D40D780A95C164D651E96A7052B69BBDA979216989A57506638F891336E2EA123303F997194B7AAB4F22CB192AB59A8BDA7CC88D0F43E4DD949146006CA3F91CF28535ED42662A61F630AD6E7319A7B98FF5C7200FECA768F14BFD43BD60DBEC814E22C26F1A8191ACC869A6BCE61991E4F36148908A5B1557A507C407D73A6FE75A548CBB8CACF13E57BA6B01FF0DF900051AE7C0C346D5DADE5F1C1BBFF967236BA5BAEF19A70FEB320BD76035F3A6B11383F13E6DCB8D1533A6529C98334A3F2A9105A5CF1C940659459C405C197130EBA44F0A2881B4614B7A0BBDAD5930DE5C3389A7349265629E29C0123CC89F3F540FE5C9019662A4383A38248F22201967D908EB48D530D17D50A08B35FCAB73AE8ADFDD72A8A7551EC28C7573E2B33EA4F61EE84C3DCA33DD5861B8FB7176C4AFBC174250D51F86B1452903191E39EF099C0CBCC15B3FB5DD30A2822F68AA37D59583BDC1CCDAB1B2E0337BF397647FEA9111A5B94C6A3369E90F3B86C266F4C11C9A7D9E24802B31B5F93B8EA9AEDC6C2944965D6B54601311D251E81C77AC1BB2159263D0A92F377F111DBC8D554C3AF747FE7E82A6E6BF0E4E3743B7AA42C3B5B8D3E5D9C3B427B3290452136E61592609826F4B61D4960B7C3784D0E2508363212AEEAE624489B739D0573CE23B35D30826182DB5F4D09772582E4D6B61938041344EA434614C21B01530327C08539A84F03275D0C4A77FDF230FBE6639CC7A12C34545C5CAD34AABF8E25D64AFCA8206948737DBA643867A146F17ABF81A926294E2368A5A2F0C381E2C244B21843E3ABBA680CC3F1F0509DFAFF4C70B68C82D3D7EF8EE053DBD154376FAAB5D561A19362314B037CFE18DD03BB817444FBF08D771A13B9D745DC066C89C10ACD53597B74916BA719F9EEEBA865252FE13EDDF97978092FDD1524CDD865FD6AE9C14329EB62B322F46905804AF1CFFC13B46B6AF4ABCB107D44DD27B460101F7A38DC786239E34CA9D1A444898673BB3DD92EE88478A3C539A563CEAF5CF499AE8E07BDAC0CD5419DEFE2977105B5E0138D84A8F9BFAD82F58884377B803C8B68164A3E678648C18127A832FA994EBEDCDE4FECE85DAFF8CD6F44F4CE57694522DC30BFC492BF62796D05A9B87BF13A7D538EE5C55E6898D50ED127E8C12F87D160AEEBD3CB126BC4144A51F685079E962DB6FDDE3BA6D0C8038BD6FD8377C4BEFC2EBF1A876833516D206C2E309C61E4CEAB5F86ED83FF20C8723BFE63D8E480798292E6EC6D418D3CEB623AC6983A3F8A3AD568F73E408F15AB88C8F56F3CCF5B32C76BDCEB1FA41357C42E1215CC503A316EA0A83FB341ED6ED20B1154E5001A754F92E97570F9DA7EA8AB7F2EFEE7B79A1DDA705645ABC5B1E04CE4F922BB03435D11FC83EB580CDFF7EDEB78F2CEBBB6053410E84477864C16D4CD7CD9D16B932372FDB99DBCCE2DC3B5CDCCF7DB86AEC9BDCB8E4F27B65ACA9A3FB985CF95C5BAE253797C8474D0C25F0FFBD151E6558E524C6E96267677EB7A3E128C918CD3B09F1DDE311401152C62B4C59EA1D408ACCC4A12A34664D7C0858D7E99A0327724AE9CA55A9322D865EFB4FBFD37FC79F8D7B2BF08B1824D44777153ED6604E05DB1FC9B1ACCE05F8C53C32594A84F32D97AE49E819029204AB7713AF2AF2C281448A34C69D5F3DC76345031D2CC05B6B26303198E182901FE65710EA95793DC8495F1995F0196DC9473B7AB922786BBC61A91868BB0BE05E2034EFFB288502DDFE2595887CCD144E98ECA4D1E0C044C642396F98473BFDEEE796530467F6B5EC0D5B79674EBDF5D1416F94A8EAC7F4833947F1DE610029779CD436729E55AE3D959F99D5438E0E4407D0A870A38AB31E08F16A06345B7BA730CCF55CF1FDA1E9D04833ADE5FD74A34E2629DCB75A3482312860404F7E75D94D7FD2C8215C6A21BD5FCAE81CF4467931A984AA24B927039526B95C2F5F39AB2040A23C76B64CD2D04E95DE6DD9B8EA849F9F7919A619EFAC498E7E3F4A70432E28B1C5DEDB08D122AE503E98D34D13A4E8A69FA267C3E20671077F977F71308D3EA1AAED5DC33B3F41E0ED981050B3B915EDA07AFD71CFD3AF13A2063813039BE85EF98706399299118D2427A7912A131DB7BA731D18DC2838A116E05C4CBC660895294A73D170C060CD83C9AA0884C5F3FE52F4891C2101997D688709F356A556CE202C571E1170BC339F3E2A75A5A13810E3A2F2133438C1705895523D03F00BBE4F4FA9BCE6D7A14517BD54E281F202BAB40DF35253961DC9E94DF5C2C5C3F0E420AC67A85BEC2ED70545B94202AACE5E58180104E42C5AA6F7F59915BEA69AC10F678D40506AD2B502D77EBE4D05CF8253B4795094F04BBDFCC8033EA131BE83F3F647D22D1212C16895F52FEA576EFB344A476D2A8EC74739BA62632C4B5B08076905BC0103CC9B2193EF6C4785685F2B3F79FC39B5ED09B258E5E9BD346557F24CB542B69A3ABE367123179879A02F941F9781935D44BCABCC563BB1F31C44BB77D5E7A4FC7EC2C11D597E7288C6088497DCC97910CFD8245A4F255CFBCB8FFF95905E8224B770E910A253356916EAF1B3277D831BEA5BD6681C6C7D57D363608EE78973B7BBBC156FE5536C963030B6BC8D306F3C1EE72F14163DE0DCD0CE741EF975A9DDA77EE386B991F3096FEC95FD394E26578269F491572B36AF42CEF1D86CDC82D63DF00AA397E1960378763F5CED239BD2A6D0EB7C5BD7CDA2228B684FA57B7FAF497310D510CD386DE6406924CD592ABB1E9753EC8BCC594ED52B70C04F7C53E19B0CB607DEBA79FABD6748A52692CDA34BB7CBF95D1ABBFF8AEF8F8AC7E5D52EF58FC79B0C7662DA90A0F737CBD42E64B648B624AB497162A7B27E41850A9BB4AF0489550773EBF1EC6742CE8D53A20921149563AA74337ED4CF1EE8685F41D36F748B6DED5F894BBC50A8DEC84621B6AAE690D6EE0B392A7266A480CF985295361B14AF0A5CEFC1EB737ED3AEA5E5894FDE80CAE477FE742395CACD1174CF2B345774BDDF71853BA1854EDC8F5CB03D33C5F58EC386ECBAC8E4209F8881473A4FFE306ED3194F455D4441D132B7685425435E58AF1F2964B657C71EB6E28FE3568183F7A0E570821EA49DECFBA3128002E77208749DCBD3F5E15453AB6DE9EB313D7445377B3BA74BD2F67AE31F560ABB628CA0DDB120CAC6CB62EC9CCC65051F70FC41BDCDF29F885FC9A558929F58CDE1200072F96C3D8F22032A0AB3F705884F0D827823FBDB62FFAA39EEBFECD9F57DA083D1ED541CF36465A999558F2299A865456C94D67E74F1EDC7166F91F4CBAC8F89E680BDED946A174E9260DD50C6B0A980A4B886850797149FCAF8871AB3080A76B645E333290A0DF319DE058981B8CFAD7A54FCD62345DFD9C3E6F7A26D212C97FA6F09866E23D5A19EB9CAE760E876B2AAF43BDF9004D5CFDC41570EABACACD4B57662087B6A91B6249CDAF905BC2B1AF5934F1A05D20E6C6784F0FFDA0A3E79A2C0939BF36C55EA0E31B1AE614D44CD413118EA165FA549026574D1549FF7D63B4C464A896C5C0E8D5569AB2B10D1DC56458FD1E069B5F91B1D084F7AE34F67ECDCBF33299B12C102F953CC48B0661AB4EFB493F7E4B2EA8F6FE59C3D5EF7D121B26B912B86BC0AE987B6A3543558F0B935AE62B4711A586DDAC9E5960C48B99CB80191B11F4053527905123D20C549457BA87608948933442CB06BEA0E73FE99E3C4198E9E7C51BBB7074DA46E752E46B3E419FAE2AD60D180303D710C0A59C6B980B24F0BFD39959368B5F56AB3845A2167F4683AA82A9613257BC801F5146CFCA857F2DF4FBEA85C54930D4373F70C083F661077567F1173819EBAA585EA3675F97951CF8C9997887BBEA9B99E17A1E0215DFC2B9A66760A277F68E747141AFE5CAB6B25D73D562B91BADDCC7938F2EA75F1C990E88311549F38FCE2C52933498B22E2810227D1EAFED4BEABCB153324622E107A6D96214F3C6D5DB91855005056A8D1BC5D5518867C373709D24DC1FCE21537C58999E26CDF4FE61ABE5E1225DE80F98D02253999F39A145FF3008F12880C173A7ADEE15025E3E186FF0C2090872A0A51505A09094FA2946AFA1840B0D6D526DEEEA95FD8E259E70B2E794C97F50E7833B165E7BEEAF5D3CAB7C3AA1CEF00003B94159F0F6DCBC74808E3FF237D5C3E94353FC0E700CAF48DA8BD94B991EFFF2DACC9E423A2AD63824CF879EF838C784C7D4C0CEE3DACF5884941BCC14E043082D382AFF598BBE0321DFE9406434DDF558EE2BDC272C2B04CBF8CEF92EF8180D0FEBD3D62E1F73F3B1E7FB0EDF9B50538D49C52CEE53F3000E581FCD7E6FEA1CEEC9DCB4876B3F1D1B1A301A2D395DEAC54D68181406D7ECA05A416D3D8E0EE10228483D8515A0F662D933C53F945B50C65C5B8D51EC45360661C92761A1F74EE06FAF8889244620DABA05593DDD4D6A82A30F34DCEF50B1B1D261CC357AB0673370A38DFEDEF3D591377CA29DF609682EFFA212092ABF84FCAD677DFAD758575CA35046467C6925B6185F9B734D5E194F5CA48DD10D0B84B7E9096703A9EEF0D3EFEFFC0F58C4D38D741F15AE766D06156B26E9C82B464C9F609F0A4FF699D52E0E11E054738476456CB81859ABE457F3595E9D7F1CFEE5D0437094CF093F468C79C093CD615F7409A505C610169010F46E148F3D264FEEA1DF42B3E78D1C4B33C92EE9BBD9C508E89BC4CE0BA0C412F75821EB54730FBB627C6C93694810CD741167D5288768165A68034CE2B16B0E73ABFBF75A905C9A9E577024EF2070EBE8A68076AE37BDF3507C7CB10EAE13D3A05BB3DA33F873F488150CE67AB892D61A11FAF5850B6A26862FF0CE85E4B0AB3EEBDC81F68BFDE39B0582185E4322404A0195BF5951BF7CDDAA6530DB0EFA0A2E6B2A9CF8DCD8B0D15447448847D1EB5FCCDC80EEDF166988D55DCF3BCE37E24A0A5F302F820C2782849E70BA47523A7AA1FF12F144148E9B5A1E05035A346FC4028BDA824B8D5FDECEC4036EB2C3A7DA612A703EFBE4D5E5E17CBCE1EBF546880C227EEE2D9CA4113D0ED61AFA70171700F0F9A1BC7CE7807A081EF09E9CEDA5DFFDDECADAA7CB5ACB2DBBE26550ED006C5B7DD89A2585EBED5995F8F76F3EF8F13B6AE77084727DC894C74268D4D91000155FDC94DEE049E54F4E4D2494EF926F23B73E60EE16CC3711B67B6F6B3A3BA6BA8CE602AE1BA87ACAD58650AA8F7F0F36AEA21080CA8DFC618AAF865B14BBD69FF7B413FFC81DC6C8BF2A7B122EC2C13DD7832610DB9E6EA0E5CACBE1703AF551997E6C51BCE7BAD4B3EB1F392EE12C5691F795090C6F1D6405D0E682F279B3DE64A9F45B1853346D8D337FF8037370CB4DBE5B241959FB8DD985A4F154470833E422AD9EAD7A14EC1CAF6308FCF7E9AAC13ACAFAAD98011148A2D52D40511CF13C7CF0ED1E320617B908BD1A6A442FAFB2E543703844B0D40FCBD1B392CDF5DAC9CE4C2CA69C8F04AA033F5D6D11DC1A5667FB352BE6BF88A9978AAD37B01BF8652A2C475E8516AE1A6E56F8CD596B9A780864ADC65A04F615ABB2BD4BA97301FB0CB7D9AB5423BB14C29030DCD5345C54D556ABB116051C04D79C81402B70AA9F32CD01B6C06FCFB416C4CB7709CEB12DF3E8BC541333C90E6D991B24D7D1D98D0839AA86614F3D91ABBEE5DF138A9DF2C0591204FEB3D9DD546305FD017B72FCA4DF01A7C1728606EDBA07EC101D7172971C9F4ACE7D6D09E06BF9E8552A4CB3ABF6FD84FD350F60A3E1826BBCBA484D4B5B284E2E1EF2A164FEDCD0D22AE77026C4A6596ABCCEBF6ACE68C11ED108BD3C +5B62D37A8591CFB588DA48B3B1AA1570C3491210EFCB877AE913F5C98D06C5853C78D526C61C387FC6E15BC8E612762899056F844B324E4829E5DCE6E2144804682D4F5D3CEBEFA61305B64386107BAC5022DE119038F94F656ABE41A61717532E374C1196780C888EF1F7455BF502420F61FE9EC389C1BB6B75397622374EE00AC0856130828C806CE14840D9322440B02923822D53126A0221108B988822A191D43231D82831E2C80CD4A8705B086D83B001A0A64183180681027040220D223269DB940802958C8AB6500C056E2222311C91491B9451833064D4280A112750232610CC088054222ECB344511B90063128119C04CCC942914C36114C1049B1290A414460893242316665B184262B211E330868A280CD9920504009162A4605A926C1B28100C002E1C4491C3A869C246860200050B1888588664520625A0102158409090022288A468484685C3844CD428919BA0300381300C372191B2001C086C13142ECB30710B3021840864E44465A4B061E2144184808118B70DA4161201398C0436810C2970DAA029D840600282411290898C106A19140A6394711C256D18C08DC488249A881123418DA33491CBC801D010680B865090104161B0511A15501C0104C01605D2B825E02226D1A0708B98248BA22040426A529220941080D34006D3C86458B4651C1440DB168DD1A66DA0B67108325109128A92C869833400CC842004064ED9340502132D1992800424309B260E2319105AC669481061994028C3A29163024C52462A5030221496846280250A300862B26523282922292410436C10B11001120D993884A34661830430D0100A00318589444C5C28802330884C22445148248A083223C02C442682E3C86C5A0088622224C2444C0A854554B26D18452214214898464A1886610B26205330310A9840443669C3208424380D94C62911C445528249DCA431DB4211C3824CDAB885D800655C462E238288221980D93468118441E42609601488204486623445CB02411A266DC392514C142D1AA8515CB60DCAA22819286522368D4A0630DC44491B036641C231E0064CC08430918460142670E0000CDC10624036852348819334308230458A38300095319B082D608268911868C2C2109C048D9C084120B16C82804C14C61120C071D1B850930245A48420D8142A4C302663B29103932521466023094A0A076C14012190180E901012C2B62458C809D0A004429885834010820629D0102462C624D844021C054CC43841D4082D0A498C2425600047621B90001AB78C63A228A1A229121126828820D224028344285448640A3104CC166411A52520B0205BB61052422509C62912474CCA226289261222812D4A28428888210CA9210A0965CB948518929002C56D59C04DE0C04C54360063426D62206420C8815C484511037209100C14122964008508A225C8068E80062A84C89198A411DB302613851023C6681BB54D49066041268501B970E3B005C424458C8425DBC469A2A45011914DD1064261080212C9010AB1240035658C164A10358621A38050284021196543000C03174800394108B448049571912481A4982D1CA669511090928845194642094226D4B42842800021028423294A51284DDAC690D0262401B26161C0250C8265199290A136680B0689C9B84D02948002227053386A0C08885B962899988419060490964DD8C86119370C21986D8848515CA6294C042A2208441AA93111C2905218220C454EDA1404C42488C8280C20433259C668803891DA8000249301C094089A008C53321220C468CB928D623881E30426011505C2145181488D008244A4468011C38499A090E0A425133510D14088E394000A271108C44822362D8C004D4A86512430242405818C4624C9348598882CE0B841091612204968A1C830A096108348106332068022610CC491803062082301D88045DBC82510C18C6486601909910BB3480A244A8A9870813031532881C494111A88605B828C0315022017901383641046890103668BA451223840C002458A8011A032101C35514A481091488021990CD8949148B29112282A224440C3127281920C12B889524024C3B0655C8209D104712143710A326112389213042C9B00820431000CB344DC1010E2B82859982C032602CAB00CCB843113C6200331280AC061D2848C1A4110911430D3388CDC005262C0858AC660B6B814546CB4270B543A708AC86BC1CE481601287A65C59BE8D90379B0CAA51F6D98723C5BA4787DFF8F095CE307869084EB4783EDE6ECCF369F923E9F435FBC1E5AD11B5E20159EB53B41A0596BE86945FA60133274AF288DEC348188C166BEF153321723169E4BBB7CC6CC2DBD6158374E10891EB82EC47383F1BF3A103B912FC2A929461137DC00FFBFB8D5A8884B1702D329CE3EB967FC0B1847DBBD06C3CEF44CF4EDFDD34E9671A3B51572A7510174D26968B869F044919AC6CF766250953DC9F4F3D0B28FB6D7D0F973BD3944B6ADA312044A09EC59E008EE8F92329776708916B1301D2CA52F9F571EE458AB13D13EDB882305351E3A1B41FF9BDB54D1BD5B768B7AE758EC8CAC4668582073FEA7BAE86D6ADDA4A4F582E7C4C298178DB1A5038D9D337B1AC18BE442865444D24B0D2443D6200A6C938963A812F1600D3689D8EAE1D668A7A0C2A3745CFF5484D0E1AD2B25A9A70CA3FB16D423DB83318BDA289478A5C44C5F81253AF25A7EDC4B35BD73CBDF3C621B0DF2ACB9B1D9C5A87CFF528D0C04F77A31818BB36492F3445E250712BCD2A0C2D3CC3B1BEF6AE9D1F4653EEC35E2C34F14CD872172FA46ECAA5824507EDBC63A5D5E8222308044C6A0647924F9D1B8AD7584EF56467A4531004AB4AE1D48203E032A1B83CB53C8BABC556AA6163E7DB321E71E55DE72EA992BF47E0F70C2180325559C33F6A0F9677BB801D99525CCCD1738C19DE9AA91A85146761FE773255D8B6BD41DB2515C23444463616F14459536703096F595E841B93AE455B9F37AD2E1A5710C83042689944C5C4A39F944E98C07D898C59F4BBB9DC8A4AC6F3789286D8B61382994EEE1C7581B3F2D12309FAC0A1F5B5F02D0C4978231D52D57D3D56D8F12075F4145270A3DCAA543A008F8A39D95FB555E1EE9D2C9F1FF557FB6C38BF4050B6F59C51C02203046ABFFD51745EDEE1B5BBFCF7A9BE1017839CC6A4638F4316DC6CD63009360ABB2B6B02818C542124B280E18A74BAEB9273B3F2DB8111CDA487DB87A18DFD16D380B037DDC8E60B5F1874D37F704E1A8743D51259D9A778DE571EB1962ED8A07B641B21C274BA9D1385B6406CC3D8ED00B697FEA1BD10967FE481EDD332EA30619655E0A454D58E59672293694DED52C791ED09E2BB3126EF1FF977931C0116B67C91E038FC70C382B28DFD692B1ED75A3B3753D5859A46AB0159C7F9FCB7E6CE9CB91C13A0A3D243D53956E444E7EA734724D45EDA455ECC7C3C74B2A2C4214C7D2B6B66B1BE97C7D6057EE64794EE0130001CFB597BC8B5C0C3E4D159E76F6409CD2C8D6ADA7F8BE816992B191B80FBE9835BD3EDD60CE62A79141DDEE46673B189A0F1CD0B103A66A6B42A3D9319B92761BC8A54F416AA8942E780BE5B70262426B11E3AE9EF12B3FB3BB884E3E230471C020DE7FCB92091396817AB83B9A7C40D53F580AED146CAD8C64BE7E0B5F84F0CB35A2731B710A10D784874B5CA4FAA3FFF38536890F3E48C5B6BA96BDFD22A8C02FBB2668D16AB52BF742D79ACAA94893C81C108622AF5B4B0D1DDAA009A2B1205B02D1B8F754134AC4A92E0669278A0FA2119C62F9F75763FD76CD4712D04B00042C00BD8E4DF2176918F97D83C03DAEA19FA30FDD16E1F9FE534B444C7C4A3E01C2779135D773AF35ECE0A3CA8CD3F3530760059580980DCA09DEEE0740F5D83D69DAF36A5A92D9F4096CBEECAED0816CE1326EC1804C54584E8C28355E5D00795838907B20CDCFCA4FE18C0D3D6E0DE96EC0A6C502057AF96C61A265DDD8D874E4D42289FD04F9DCDA6C270E7C53C3A2B23B20AB13AA8E3FB8B0DC77C0CD0F00B6C2FB8A36D935356E10D51A20E53739A5BDE93F96B49ADC09AEEC0B35EBFEC815880A56DF5B1D110839A9BF7946576E33C226964F6075987489DF3A7C0B574E21A219B670E074713ADCE8E401969B6D1A5D2EDE0F725C0FD829AA435EB3F4B9E689061C92008547F4AE3430B259F557E1A2DA041643FE2FDBC8E03286B50EF73D6DCEF0B9C6C75AB40F1D2F8D4CCB6725AF56A37044A3933923FC2F32378855CC0FBBC0327F25C16C59285BD19627CEDA13CE715E35A689B67DBF61C3B45C48FE507B02C4C2689ED5CA3D76418E3C2FC5269E3525A7C122A0FDD0E00CF4F960D45513C049223084BC5519B028F17F94A3B7CC1C407618935F248C3FBF0678F2A7A05E8A1911059264409A8801BBB80A3AAF8E0B6D86CFB3775F7F9AE87152371C6216947E89BA04EF44E8AC304B876028DAAFB54C3FF067029F15AE768235BAB8F854009110645AA801B2904F6939014BD76E5AA510BAB9D5AC17BBD536FC32CB2B4505A47D8679AE67DA0304E4982F03E22E77068A23B32192A24569D40356FAD23B1D79E40F17F5D2B0DF23EA437EB2371CE2C7278653A884FE38AE0CE9D9C60F97CC88E3CFE5AF1AC3A1D22079BF9FC2B42435231F110DB596581B44FA7E31265BEC9FF7C86EFAE208B898F36302B66E409184EEF82DF40FD60D6A4796C071C088BCD95E8F8AE857047BF83CA41EC4A845B48E5631F85192FB998067B0B7172E575D6671917363064C08CDFF23CA8499F240738D730DED8A79CF015FD9FF34D53A0B6BD0D1DD38B32AD0B3585FB99AEEB5C11547B8AD365269FE96CC855E3E7E5508930A639D82BD105867396D6074A6C2330A35967B1914FB52AB94F44E3DE354D8349DBC86E444B5165ED20376B11DFC9FA5F51F6069FD743804BD04222E22A79B54603AB0983530E1101227F8BFFA3A24E084D452E1DBA5B5FEFFB23B9842395658C38C7970405E17E0E8451AA188BC920887B35917159F83D7B187227B26B659D168EA4A2C8FA6330D372DEAFACD8854852F313618DC847C56832CB2A3C8029C5770F7D7D63CD3109EFD2725F24016232028CB1666DC9F407040806AE63115BFE51D2BD2D74286B205557C7F58F7EFD4755C53E2BF24F3D9F97E48ED86E2B7689B385BE82849DE6CA634963F2782436ECBD35F58EA3CEAF50A452EFB16F6072FA1E9A10B3E948E5F2959C4DDDD89921D4CB0214AF3149B7FE5E2DACBD9632720CD06B4B210350435F663C4562424927197703D7ABCF4F278C4335C623C55D8021B7A5766854DA7AC210F25A326F84E0BBDA83495D44BB923FD32AF32528A68F11C7557F4DE631DCFD8C233F473ABD54C6ACF3B3E935CD6942495FA61211CC158B7C2FEC84F923D6C4F902A8A19B46A931C68F420260A477A6C3A28B3B4133634EB5751E3A7CC46022B706BFBE01A3E062284C2D4A8758ACE690514B137FA480676B09EDDDD309D6F52F94B2D0287270CFEB1A6E663B762080ED4C4769BAE6C168CBA07AD79B1A1690C5FBE0D9A05656D4E52466C906271CB7C023A72A2F015BF869446FF35E9BC1A59E23D9928CBD1285512AECD6C904CA47F63A8747FE79AC8438D6C26F13FC4549453349441D959B66DB25037127C036AB356C8CF79F99F10BE8502734CD91CA6ED2F543F2C2D5412CB6D16DF798204510CF5A17E6E33397B38BCF4BC57546AF7824C0B4DC7D107392B97730CDC0F1528648FED45BCE3443A44BDF1B28B31FC8FD17A1B4A737CD28F927559FE2564A3018DBE808D3AB4A4440527825D2013D487293AA875E5E911510CB8B56B04099F96CA23C62E72C2156EA08B6C7CF5E45C869BD2468AFA718C7E3B73C6D02C7FEAB0AE69C233F0E46E57945C4D4EFF7796285E8988B51280323A8E89CE7BD8C068B0828CC0BEB77C0F44E28C5E75A21853AB9D8159B0E2255C5DD8F5746F924E237A4A8FA3745F5CA39814EE64E7EB1C94DC7B4A2889CFE7A01690A89285DAE12AA6CEF45805714F05BF0FFF97ED82E51842B099FAFF2F0C0F2C608FB3CB6E069D276714A21D1AEF73A870159CF5C56CEB3403D96F4AD1D413D03583985068349F73524D66760A17AAAD749931870581BA8C576FF6549661A43529A2145739AFCB3BADA0EA472AEA14986670A97FEF749F520054CDF4820C191E5D94599D95A9050CB45B6E8E5FCD28816D331F21FF06EBA6C0DDC495AB8F1BC645386AD1EC65EAC1FB4C4AA5FB8A301BCF5A04A7D61A8310804475CA128824C767426E55EED148C766181E2F2573149C2AA36496563A4497DD9244F9B17791AF92489B0BE38BB5A778E679B93BE4BEDE0C06B60A048955A0F598FB16256799ACA1CFA818863EB852A7329FD13BB9177B8653E3EB32D6C40601AC61F69FC91468737480C6C8D422755D2AC35E410D7504E07DE414A7FAD9A00CE495C84452ED9EEE7817066DF613156995D4132CBE14F1607FF63BDCE71849C7E3A20B5F728EEE14DF98C950706E97F6C2E340300431EF2A6E0FDD9B2EE45139C2DC66FC4FCF8231A86B9F498FEBCCC3E87F19DA17D09FBC476C8CDF0870775891CDF0C94411FC686FBB54C9EBB8AC22BC43AB8A72528DBED5AEDFE87CC534E3127CFB22784BDB2811B39D20C29A0FE79061A0CD54787EE228013EFA979413F8BE983F7D9EEF5508DDCFBAD3F4AF8526291A1840BBBE247969C8EA5218778571891783F16D84E517B7CC7F1A50999A23085AEA463EDFA3AC16AAE8ACF4670C69437821C57349A12F561A87218BA746065666A7B76EF92EA8ADA926BEDC8F25F809F4E747F92B7F16FAE68EA88BE10542DB5ADD7042E8B26115E2A587C5BE310684AF723C6BA4BAE47725FA641BF4C0218F5315E5B2EA0D89F0EF \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_output.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_output.hex new file mode 100644 index 0000000000000000000000000000000000000000..4766438f565c36484ee7bbc3c0a8642fde8f8aa8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/signing_output.hex @@ -0,0 +1,3 @@ +01 +00001255 +38796E20B090704AA24C32C0C124A7DEF5F130609930B6E1AED360E513B596E661776CF8976D08F52605680DEF3C4EBDB95740C59650522ACB3CD56303D4D823E0C4BD7493B3B27047885BA8CFD93B4D71C0B9B300F56557C665ED9C953E894B02FE79219D32DBAF5AE4DBBADA3CBF2861EF00C40075142DE7552DFD76C76F18997884A8F00B9B6DCDB234C162000C37AFFD2D346128F84204DD5AF3612D45C0EBDCCF49C5F02ABF5E984AAF164A08E150F75A19C1BF0F64A70903B07254161BEE6742DF447DF312E408B7F00E6CA547280866574F050E0F8CA05E16F1001BDF6C5877D088B919D5754F2B4DC7BACCEA22431065A58F221F616CFB33289129C8891FB590D76E15DD76A94163B20B9D8DF203A1A6FF451E95E7B06936704DEB768F6A4FC95A333665064DB55D0CD5B28FD844C249D1DA5423F3F31665F42676BE1BF123C9A8BB26C76ADDFC6E8B66A940FF88283129BAB039EF285F1CEFA91C11178CCF37599D3857AEFA3D6D8B8F1C806D3154FC1D8995AFCCBC73EA0AE540726411A18CD0297201139A7F182D84FACA6DCE99D48C7A84BF5BFB3352E0B16943D96C5F758FA8AA111D8F3CD25CEA8D0B232BAF70FB8547728BA0E19BCB9A75509F4892B7826B3AEEABC56F3A45EF2B7A4F6BBDFA052EB1A7204BB59C9D4A3777E4D5EBEB1F7AF263E3614794A0E66250884BF9CFB777522398DA1B9C709C33F06E8C5E108D30218C199C5B097C823837A99AC786074052668C8A4B5AF0152AE4D92FE4E98C91F7D318AE67F482CBD19BB70AFC290B90ED5B630387410596BFC754764C81AFFB5931AE0A85E41E1DC950E65CA22D272B58CEEDBC6DE6635ED6C85B05A699DE77B6B921B6DC281A914159E26C77F84F7636D0A3D9B90E8965949CF1A04EA6D36838CD54530D1E9953442BEF130B25CBB733B43A324ED5898B0C8F8EF5C71FF164D5F37B2219E2CC3618DF2CEA8449C95BB3261C350E6BA81E7B72E6D46740DFC331CDB78D3074F79DCEED70BEF2B0467A73137058795AA933ED60E00AB9105ECE16193839EC4534012A2DB5910970E0BCECF04085D622EB92BBAAFE2A888E1B2F4E381E58518F7AD10445E21E40829ED18D61DE3856812D5AAF963F058C1203BD6D73B933518BB4A44DB2154E10C0B07830FA07E20001857D46D3CB541061EC6CBBDABA1731574B3A140E1CC1F3EF88AE1D78FE7E80A6565FAC737FA1E0A70BE706250C93DC1BAFD46BA50CFE07A3DDB8CAC3943BEC70044D9D374EA8D8C3634FA270A6701DD69C251A7229A0F37F49649195252E9B74D03B6256565E26BF484FAF02181D6457BE6F615FF54E21356B36E119DFAB1673984A31A47365F766C9C4229EEA10B483B219AEE164162A54F3A9D7A474D8C8AD1A2D82B95F42E88E6EE7B67C2D103A1E939D4377A59FA56673DC1F0EF642B3B7541ACA2D21AAE4044E53B29C04C16D510575C2D5F104BDBA6D3102DD46589E690C34DB73245D0A299DF65974BF462FC35B58A6465518988F5E2D3C2B5C60C728C0F21E311228A7AE2F7481C9EC12183FFBD2314BC065BE9E5A7ABCA9627E9360EC13AA078953FFE49C981E29D9FC0117929BC51056CE6F9E3CD6D65877C95A6C7B6E4BD0B2BAD131DF0477645FCEDA0E5328638D094F618FF61932B7B2ECC280D26C9BB72AAEF2B34E55A2527A34E76406AD6917C95085A228CD7EF3DC63FEF65CE8A33B1B4BF784D008686B6471D0E9E699CA6E589DBB666D6C11B608B3F4030FCDD476F381CE03FE12DCBA93E2AF7BEF259BB86BC39AE969BEACCED93FACFD3707C5DCBE449245F6E2E0D0E689CF5B534C9EAAC4F083A38B5F869E025290C07DA6AB972158A1A07F2A1BE774848D05A1B7DB112CFEFD66CC91911DB54906557DC52036685F76B2BE5557D14E1B58C7A962F7A8706787F726076FFAB03997E438DBAFDC5FC38E1BBACA4533694069371FBEFA4E271AE66B876020C3C7543FB2BAFA40FBB08125EFB057FF3E14E253F3949745AD6AC708B87B598B9A28020FFD44A243661D0DF1B2F26E047B55BF1E502B5DDC5EFBFED7E18084D0E9DB9AE1E55B40212C4001D5B19BC93BC74CEE4BE3DDFC54E58BD56B40EC4A1E8DB3AE7C2CB982A47E147334868BD5AB4FCFF96389D90B0CA78A23C6CDF71CD155D2E2D20B7A7F21544475A4C10A90F304A174CABFF35450DC5185D505C45BBB034CC010AD2306909473C51ECC4F87019CF66959D07C83B4E6C29F946D8399E5E2BC4BD5B959BD29B87B82872514B0C8F86997C2BF78DA0E9BD6AC12F7109D2F05339FCE83C0A528A6894574D99EC76CA5F38C4E1A1E7FEF0110EA2B86F29BA2463448502BD725A90780F8F20C4DEAC5FBFD93BC48B4ADE4C814012BAF6C3EE604462F5B710D07D3FF86884D7BBFD755CBF136F2E51E693D205F1CA1FAE7C69932CBE89AA2706842B23271AB38A2639871B025D234B498EE34C04436670B2640471A3ADC444DD3ED165CD0DBCD0A22F5B34461E2BD6F0D13AA7408FDFFD5CE7F28DF3DC4CC44C5A5A33076125F78CBF5390C0829A83FCD10A7A73A56D94689BBDF3269E7F82085087B86E6F4AC449903C4CE7FC0948EF0EA57AE339F1A60EE0A299DF503561677C00F49ED61EBDC96670290DBC8C8EEE3D8B71C1EB0E49B95913739C8EE2049900610EE8FED70EE6B5D99FA11C5DA2B7336FA095B98BBD1E8545D1B4F35C73F4B5B501AFD2970BFC33078F66F4E86837BBEE43D3831065BFC889BE93CDCE21709DCD0A833D8C9A97E068EB4C7727499A7883C7A961555E64C6F6E2E2A577593C28A7D2F80F5C1230A74F3B1EBBB8380A8A185E7FD44F760C387C2BEA509A9E86C308F115F422D02A456E5261E3163745E3D22367ABC9F9BF1E6C75C1C7D271F568F06A344DF1BD84551FADCDBDE55DFE14743FFD36C8E071E0B85B6514A1F7780EF562D0DCE25AF095F7AA867A1B73CA9F6BEB2097DDD696D44CF4E645DEE67D159960C3AE7B8A587866C71F304E06451CCC62DA4C389B041369D6F58CB4C47E4E887475A6D84711A034C6D7EFA988C7A11E2E919CABF01AA2FA9D6216CD4A7F22FE692FFE1DB53E4CE1B5A7AEA2525E8F88B05D1297B5D435352D92A66035DB97FC06D1C74540A487DD48AF1BB462312A0EFBCE06B7317CC201EF86D48387421575294EA33282E65DD8D1BC87F575AB0E8FB92ED251D3D559A7ABAABD7D83F6E97189AC79D031449725B1F887070C02F9882073AFA471DA18DD15B4773A915AE3E23C8E70FAC216217928625D47D35EBE7C487432AD36DB44A1283D75616AB65E18CC3C4724882062FD50D8FA09DF41280304323330473322DC97233ED27461FFA436B6D194BC2F531454B3B80BBC4DC768F77FDEEB7D4E5D8AE6D97FAD09556799996D820990FAE21C3F2A91C2FD35D71BF0BC8AA26F00107EA708606D973C649C50AA0E09F082051C0AD5926567C512DF7971745E1CBB78CF8EE3EC075EFDDF9E53A060FF4CC4CE2A961630E46C8414074A2A5F92CE1BF236D0FEA264EA495DA9B925A62CA1E876D76E03B522B118F021BA817C2B624AF63EDED7AD7A48D30F9AD785AB30016AC34AF8F0D5FA057CA341E3D2A9B94F2C3CAACE30AE3A856DCF17BB43F8634915F3A2CCFEADEF07EB9B719D4509DB18CC10868EB4DDC7AFCC5536E009C1EE6EBF2BA8B1F60E3190E2F881C4DDC271E2E993246941B36C548092BCA953EA9CB946AAD1DE5A27B912DF856C09F2B4F4F658743C2629B1684B68A465E318A896A6E8FE4395058A26C95AFA6C46990A6B577FB41DF7ED8ED433663BD792B65308C921C5BD450C6253ECB33F4397DB7419BEADEB409D1D5FD9AE1AEAEC6AE31221002209076BBFE67F915F78B939133715493B32B97D5CA6D8C7C944346FD0F89058B35873EC808CA75C100A51C38010B6062B44C48EECFE49EA82943B94A812E9532753BE035F138ED92226D82F77CD18D945CB13F266198F511799865FE92D8B7BAA4D9CD6EABDC5E97B14962B86603F455E7EF457EAF9EA41323B4B0A7A93BC29520FC908C034AE3D660ED914F383C2F8F98534E536FA4ACA7C2B1A719D581D9C269837893C130FF3EAD5C98BA7B12D0BEECFC02FE6A8213FAEEBCB3B0376667B313FC62C831BAE913DE0BCE877881BB8060601700BE7853DDE98C121780F37D8C0C4A647F667A0E107E0DD6623D0B6533F1ED50450A9669D24F0A47FF3D532F846D7B2034E214B3B37C6EE1F36E9389837E0CB8CCB84970FC2A01AA189944E2DB2620E92B39DF0F2006F8F379C60CE38B88ADB3F14F6F6B216444FB0C63160EC03B397F552BDD3CA971066A6974E08F4BD4B60D219AE64EE1340752B5525E7133FF8F21803E77FA78C291FABF65D0ED54BBAEE1F0EFE6760C10BE545C405CBC597456FFCE829E0066AE53052CE56A7379E8B838A4A837A791A9798AE7F331F8E5C80B5EEAAA1127046D32A64AC23685EBA4F11335E1AB41AEE81B39A7B2A6741BD66CC40826F08ABC5EB5138E64D42F76BD641DCC5A46ED65D50AF5D7021DEFE796D71A8A7FFC01F889FC595734E0E07D6A24B2F36C28B70A08FFD9269A56ACF1B88F0C12ED0BC26733D9F78267D6AC77BD5A57F4D631DA8B9D73374230A8A9237A532F617EDE49AA4D00393B4D6874DD2D8B92D42C032B0ECB2326A77CEA9C02C0DABEB6C78242701561F5415674E6CD96C2EDD0E96EBA22A12EAD6502BE87B902A9988015EE0E675412600C7E4571A5C745E024295DE17427D9A69A355F176DCDE2C5BFDB1B548EAE6DFD8FA2E2A50CBFA90DFB69E0C939FC969DF9A501BBF7AB51017E7CC2B2752A3913451FE2CC061B0C9A95464A281E21976AC7287A431DAD74E287A3FEFD21978A75D9ACB35A9D10F54DAD84BEBF5A7A65F7F9419FD7E9101A04080D448701CDAA0D04413D1095CE33D39435C14A9798CEFF5C9FB8A9FB460C14157A28FA0F2BCE96E08A194CB27B656251AE24531DF2CF182B9009E104663DEF45AA9B3060922210FB531FCCE4137020CEB7C6E469DEECCC55FC04C822A7151F3B054F2CF33B052A1856FC31B6B90C4865D0CCC40806B2E8DC70334E86F285049F9836B414C406800DFF77B239C1F9DB0595639777E2581A5246158A50654F0C62911220A88C212F02EDE91161FD1DBC5269F6E6169BB57E5790EC1C4CDB21DA2D2F2C0BCB8EEC8BD349F128969E11B840D1947BAA65C79D8FBACB0D6FAA59FAF094DEF2F751F4F3E519A7D2AC8E5A3FE25E684648B3F6376C655EE912F19700AC3A0BE51A93D56EA67AC21D0BF6424DC2BE720AC23003A503BBE1FB5A0CEABADF7B26B71988A1403F3858247CBA9979ED4852EE31A156939ADD80574A1A230FD8812489D93D890DA7BA16900FD4DD51DC223AC82BCEBB52841A58E389608CFD01202132D35B846581BAF761DE5BE422FC6CE265FEAB725172D9D9E0545EBBBDF4C724F73217954EA64B522E08680EBE34F8B5AB163B798F5FFFD23C3F73F2B18F0D766084E6F4D830658867A7CB6909E055EFA391BA69B163246DCCBC96C38AB830E18D54CB1F54998082AA6A46C88AC43277DE95035BAE901A81AEB4DCCB41F93CDB9DC080396E9EF8A3A36A8ECD57CE8415972ECA84FA3715B9C0F5046F91C486B81ACB1544E7365AA7A248125A0B3A06E24EE55643F9FB9F6F9E99868E862E8810A6F5A6C25F7AEBA8EA1C1C8BEFD723ADE25D8C51E48912F05122FB54D91A196D41CADD54CFF5C41E9125CF3EEE2702D914C39449E6CB50138513F86A69B5D8FA6977F16AD026A1101BDBBA2A4D07ED50B2EC16CB12AD0544A4C09336637DA9DCF36C292850D229943ACE2FFC65C415C595CFE261335016C5F8B4F6FE11B9A8A396C7D352555353A3ACE365EDC9902D5D192267401FBE41FFC75912DE0B295BC49641BB96E92C10B451733893DE9C79F1B64810734B473631DA5649A90F4B878803AAD72D2A83C49E8A5B0815369F06F077A9F946EBF74918EE0D0433F3D0EBEAA987A1C97260BB7F35495501E62A5EF664E9D745C1804E5961542599EA43389203C539DD77F93909A3C7DE272A0F9D325B99E59B505F5DC8E409712E928A6F7962E728D466E5D42375891DEB0741298F1ED874B853E9FCA68F5562F9C5399BA5F59F43DC628D1C90FB7ECD60EB771FAD4A81A464A552CE62F1D8D05D990E9A9FCF787DDFB13010466A1B42ABED02E2F81DD66013C43744EB670BC6EC0740AA75925F2BC3C24B9F8A28FBD8AA5A8B5FFF106E0DD2B9BEAE5E01C4B725F1EB22ECDE0163B28E7CDF3B6CAA75B7772EF74D02603AC2BA16971EC69F96ECDC811BF0E7D4AF47ED133EAEB24FE1B93EC6C6FF85CD0E4CCC4332182260B8399997096A061748FEDA6C4B74C77DD74FE329A9547335D0F61264C8E2AF163296645C5F31851597CD034DC431DC0AAC0C3558E941ADA82A70CA246FD1191D989DC9CBD1DCEF334B82A0AEDCE2FD45475EC4F50E5F628CBABEDDF6102B809BD6ED242D3241C6CBDEE43157879CB6BC00000000000000000000000000000000000000000000030C141921272F35 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium.c b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium.c new file mode 100644 index 0000000000000000000000000000000000000000..f4b45a53ec623da9b14e8962ccb9901dac52e7e5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium.c @@ -0,0 +1,304 @@ +#include +#include +#include +#include +#include +#include +#include "../randombytes.h" +#include "../sign.h" + +// #define MLEN 64 +#define MLEN 65536 +#define M_PRIME 1 + +#ifndef PREHASH + #define PREHASH 0 +#endif + +#define PHM_SIZE 64 // 512 bits = 64 bytes + +#if PREHASH == 1 + #define OID_SIZE 11 // Size of OID (in bytes) + #define M_SIZE (2 + OID_SIZE + PHM_SIZE) // Size of final message M' +#else + #define M_SIZE (2 + PHM_SIZE) // Size of final message M' +#endif + +// Function prototypes +uint8_t hexCharToInt(char c); +uint8_t hexStringToByte(const char* str); +void writeFile(FILE* filename, uint8_t* data, size_t len); +void readFile(FILE* filename, uint8_t* data, size_t len); +void byteArrayToHexString(uint8_t* bytes, size_t len, char* str) ; +void byteToHexString(uint8_t byte, char* str); +void sizeTToByteArray(size_t value, uint8_t* array); +size_t byteArrayToSizeT(uint8_t* array); +void create_message_prime(uint8_t *PHM, uint8_t *M_prime); + + +const uint8_t rnd[32] = {0}; + +void create_message_prime(uint8_t *PHM, uint8_t *M_prime) { + #if PREHASH == 1 + // pre-hash MLDSA + // Step 1: Initialize M_prime with required sizes + M_prime[0] = 0x01; + M_prime[1] = 0x00; + + // Step 2: Add OID (0x0609608648016503040203) + uint8_t OID[OID_SIZE] = {0x06, 0x09, 0x60, 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03}; + memcpy(M_prime + 2, OID, OID_SIZE); + + // Step 3: Add 512-bit (64-byte) PHM + memcpy(M_prime + 2 + OID_SIZE, PHM, PHM_SIZE); + + #else + // pure MLDSA + // Step 1: Initialize M_prime with required sizes + M_prime[0] = 0x00; + M_prime[1] = 0x00; + + // Step 2: Add 512-bit (64-byte) PHM + memcpy(M_prime + 2, PHM, PHM_SIZE); + #endif +} + + +// Function to convert a hex character to its integer value +uint8_t hexCharToInt(char c) { + if (c >= '0' && c <= '9') return c - '0'; + if (c >= 'a' && c <= 'f') return c - 'a' + 10; + if (c >= 'A' && c <= 'F') return c - 'A' + 10; + return 0; // Invalid character +} + +// Function to convert a hex string to uint8_t +uint8_t hexStringToByte(const char* str) { + return (hexCharToInt(str[0]) << 4) | hexCharToInt(str[1]); +} +// Function to convert a byte array to a hex string +void byteArrayToHexString(uint8_t* bytes, size_t len, char* str) { + static const char hexDigits[] = "0123456789ABCDEF"; + for (size_t i = 0; i < len; i++) { + str[i * 2] = hexDigits[bytes[i] >> 4]; + str[i * 2 + 1] = hexDigits[bytes[i] & 0x0F]; + } + str[len * 2] = '\0'; // Null-terminate the string +} + +// Function to convert a byte to a two-character hex string +void byteToHexString(uint8_t byte, char* str) { + static const char hexDigits[] = "0123456789ABCDEF"; + str[0] = hexDigits[byte >> 4]; + str[1] = hexDigits[byte & 0x0F]; + str[2] = '\0'; // Null-terminate the string +} + +void writeFile(FILE *file, uint8_t* data, size_t len) { + + if (file == NULL) { + perror("Failed to open file for writing"); + exit(EXIT_FAILURE); + } + for (size_t i = 0; i < len; i++) { + fprintf(file, "%02X", data[i]); + } + fprintf(file, "\n"); +} + +// 0xABCD_10EF value[31:0] +// {AB, CD, 10, EF} +void readFile(FILE *file , uint8_t* data, size_t len) { + + if (file == NULL) { + perror("Failed to open file for reading"); + exit(EXIT_FAILURE); + } + + char *line = NULL; + size_t line_len = 0; + size_t i = 0; + + while (i < len && getline(&line, &line_len, file) != -1) { + size_t line_len_hex = strlen(line) / 2; + for (size_t j = 0; j < line_len_hex && i < len; j++) { + char buffer[3]; + buffer[0] = line[j * 2]; + buffer[1] = line[j * 2 + 1]; + buffer[2] = '\0'; + data[i++] = hexStringToByte(buffer); + } + } + + free(line); +} + +// Function to convert size_t to a byte array (Little Endian) +void sizeTToByteArray(size_t value, uint8_t* array) { + for (int i = 0; i < 4; i++) { + array[3-i] = (value >> (i * 8)) & 0xFF; + } +} + +// Function to convert a byte array to size_t (Little Endian) +size_t byteArrayToSizeT(uint8_t* array) { + size_t value = 0; + for (int i = 0; i < 4; i++) { + value = value<<8; + value |= (size_t)array[i]; + } + return value; +} + +int main(int argc, char *argv[]) { + if (argc != 3) { + fprintf(stderr, "Usage: %s \n", argv[0]); + return -1; + } + + uint8_t pk[CRYPTO_PUBLICKEYBYTES]; + uint8_t sk[CRYPTO_SECRETKEYBYTES]; + uint8_t external_seed[SEEDBYTES]; + uint8_t m[MLEN + CRYPTO_BYTES] = {0}; + uint8_t m2[MLEN + CRYPTO_BYTES]; + uint8_t sm[MLEN + CRYPTO_BYTES+SEEDBYTES]; + size_t mlen; + size_t smlen; + int ret; + + FILE *input_file; + FILE *output_file; + + input_file = fopen(argv[1], "r"); + if (!input_file) { + perror("Error opening input file"); + return -1; + } + + output_file = fopen(argv[2], "w"); + if (!output_file) { + perror("Error opening output file"); + fclose(input_file); + return -1; + } + + uint8_t cmd; + readFile(input_file, &cmd, 1); + + switch (cmd) { + case 0: // keygen + { + readFile(input_file, external_seed, SEEDBYTES); + char seed_hex[2 * SEEDBYTES + 1]; + byteArrayToHexString(external_seed, SEEDBYTES, seed_hex); + printf("seed_hex is %s\n", seed_hex); + + crypto_sign_keypair_with_external_seed(pk, sk, external_seed); + writeFile(output_file, &cmd, 1); + writeFile(output_file, pk, CRYPTO_PUBLICKEYBYTES); + writeFile(output_file, sk, CRYPTO_SECRETKEYBYTES); + + char command_hex[2+1]; + byteToHexString(cmd, command_hex); + printf("comand is %s\n", command_hex); + char pk_hex[2 * CRYPTO_PUBLICKEYBYTES + 1]; + byteArrayToHexString(pk, CRYPTO_PUBLICKEYBYTES, pk_hex); + printf("public key is %s\n", pk_hex); + char sk_hex[2 * (CRYPTO_SECRETKEYBYTES) + 1]; + byteArrayToHexString(sk, CRYPTO_SECRETKEYBYTES, sk_hex); + printf("secret key is %s\n", sk_hex); + } + break; + + case 1: // signing + { +#if M_PRIME == 1 + uint8_t PHM[PHM_SIZE]; // This should contain the SHA-512 hash of the message + readFile(input_file, PHM, PHM_SIZE); + create_message_prime(PHM, m); + mlen = M_SIZE; + printf("message lenght is %04X\n", (unsigned int)mlen); +#else + uint8_t mlen_array[4]; + readFile(input_file, mlen_array, 4); + mlen = byteArrayToSizeT(mlen_array); + printf("message lenght is %04X\n", (unsigned int)mlen); + readFile(input_file, m, mlen); +#endif + readFile(input_file, sk, CRYPTO_SECRETKEYBYTES); + + crypto_sign(sm, &smlen, m, rnd, mlen, sk); + + writeFile(output_file, &cmd, 1); + fprintf(output_file, "%08X\n", (unsigned int)smlen); + writeFile(output_file, sm, (smlen-mlen)); + + char command_hex[2+1]; + byteToHexString(cmd, command_hex); + printf("comand is %s\n", command_hex); + printf("signature lenght is %X\n", (unsigned int)smlen); + char sm_hex[2*(CRYPTO_BYTES+SEEDBYTES)]; + byteArrayToHexString(sm, (smlen-mlen), sm_hex); + printf("signature is %s\n", sm_hex); + } + break; + + case 2: // verification + { +#if M_PRIME == 1 + smlen = SEEDBYTES + CRYPTO_BYTES + M_SIZE; + printf("signature lenght is %04X\n", (unsigned int)smlen); + + + readFile(input_file, sm, SEEDBYTES +CRYPTO_BYTES+PHM_SIZE); + readFile(input_file, pk, CRYPTO_PUBLICKEYBYTES); + + uint8_t PHM[PHM_SIZE]; // This should contain the SHA-512 hash of the message + memcpy(PHM, sm + SEEDBYTES +CRYPTO_BYTES, PHM_SIZE); + create_message_prime(PHM, sm + SEEDBYTES +CRYPTO_BYTES); + mlen = M_SIZE; + printf("message lenght is %04X\n", (unsigned int)mlen); +#else + uint8_t smlen_array[4]; + readFile(input_file, smlen_array, 4); + smlen = byteArrayToSizeT(smlen_array); + printf("signature lenght is %04X\n", (unsigned int)smlen); + + + readFile(input_file, sm, smlen); + readFile(input_file, pk, CRYPTO_PUBLICKEYBYTES); +#endif + + ret = crypto_sign_open(m2, &mlen, sm, smlen, pk); + + writeFile(output_file, &cmd, 1); + fprintf(output_file, "%d\n", ret); + if (!ret) + writeFile(output_file, sm, SEEDBYTES*2); + else + fprintf(output_file, "0\n"); + + char command_hex[2+1]; + byteToHexString(cmd, command_hex); + printf("comand is %s\n", command_hex); + printf("message lenght is %X\n", (unsigned int)mlen); + printf("result is %d\n", ret); + + } + break; + + default: + fprintf(stderr, "Invalid command\n"); + fclose(input_file); + fclose(output_file); + return -1; + } + + fclose(input_file); + fclose(output_file); + + + + return 0; +} + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5 b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5 new file mode 100644 index 0000000000000000000000000000000000000000..ae8ed652210766b81c0e4f8201270c9b9ad7a157 Binary files /dev/null and b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5 differ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5_debug b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5_debug new file mode 100644 index 0000000000000000000000000000000000000000..6d11d40ce593c259d2c18ea0499fb28dde8b4bba Binary files /dev/null and b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/test_dilithium5_debug differ diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_input.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_input.hex new file mode 100644 index 0000000000000000000000000000000000000000..e9ab93d499c56bfccc4e8e41a53fd114d0bbe729 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_input.hex @@ -0,0 +1,3 @@ +02 +38796E20B090704AA24C32C0C124A7DEF5F130609930B6E1AED360E513B596E661776CF8976D08F52605680DEF3C4EBDB95740C59650522ACB3CD56303D4D823E0C4BD7493B3B27047885BA8CFD93B4D71C0B9B300F56557C665ED9C953E894B02FE79219D32DBAF5AE4DBBADA3CBF2861EF00C40075142DE7552DFD76C76F18997884A8F00B9B6DCDB234C162000C37AFFD2D346128F84204DD5AF3612D45C0EBDCCF49C5F02ABF5E984AAF164A08E150F75A19C1BF0F64A70903B07254161BEE6742DF447DF312E408B7F00E6CA547280866574F050E0F8CA05E16F1001BDF6C5877D088B919D5754F2B4DC7BACCEA22431065A58F221F616CFB33289129C8891FB590D76E15DD76A94163B20B9D8DF203A1A6FF451E95E7B06936704DEB768F6A4FC95A333665064DB55D0CD5B28FD844C249D1DA5423F3F31665F42676BE1BF123C9A8BB26C76ADDFC6E8B66A940FF88283129BAB039EF285F1CEFA91C11178CCF37599D3857AEFA3D6D8B8F1C806D3154FC1D8995AFCCBC73EA0AE540726411A18CD0297201139A7F182D84FACA6DCE99D48C7A84BF5BFB3352E0B16943D96C5F758FA8AA111D8F3CD25CEA8D0B232BAF70FB8547728BA0E19BCB9A75509F4892B7826B3AEEABC56F3A45EF2B7A4F6BBDFA052EB1A7204BB59C9D4A3777E4D5EBEB1F7AF263E3614794A0E66250884BF9CFB777522398DA1B9C709C33F06E8C5E108D30218C199C5B097C823837A99AC786074052668C8A4B5AF0152AE4D92FE4E98C91F7D318AE67F482CBD19BB70AFC290B90ED5B630387410596BFC754764C81AFFB5931AE0A85E41E1DC950E65CA22D272B58CEEDBC6DE6635ED6C85B05A699DE77B6B921B6DC281A914159E26C77F84F7636D0A3D9B90E8965949CF1A04EA6D36838CD54530D1E9953442BEF130B25CBB733B43A324ED5898B0C8F8EF5C71FF164D5F37B2219E2CC3618DF2CEA8449C95BB3261C350E6BA81E7B72E6D46740DFC331CDB78D3074F79DCEED70BEF2B0467A73137058795AA933ED60E00AB9105ECE16193839EC4534012A2DB5910970E0BCECF04085D622EB92BBAAFE2A888E1B2F4E381E58518F7AD10445E21E40829ED18D61DE3856812D5AAF963F058C1203BD6D73B933518BB4A44DB2154E10C0B07830FA07E20001857D46D3CB541061EC6CBBDABA1731574B3A140E1CC1F3EF88AE1D78FE7E80A6565FAC737FA1E0A70BE706250C93DC1BAFD46BA50CFE07A3DDB8CAC3943BEC70044D9D374EA8D8C3634FA270A6701DD69C251A7229A0F37F49649195252E9B74D03B6256565E26BF484FAF02181D6457BE6F615FF54E21356B36E119DFAB1673984A31A47365F766C9C4229EEA10B483B219AEE164162A54F3A9D7A474D8C8AD1A2D82B95F42E88E6EE7B67C2D103A1E939D4377A59FA56673DC1F0EF642B3B7541ACA2D21AAE4044E53B29C04C16D510575C2D5F104BDBA6D3102DD46589E690C34DB73245D0A299DF65974BF462FC35B58A6465518988F5E2D3C2B5C60C728C0F21E311228A7AE2F7481C9EC12183FFBD2314BC065BE9E5A7ABCA9627E9360EC13AA078953FFE49C981E29D9FC0117929BC51056CE6F9E3CD6D65877C95A6C7B6E4BD0B2BAD131DF0477645FCEDA0E5328638D094F618FF61932B7B2ECC280D26C9BB72AAEF2B34E55A2527A34E76406AD6917C95085A228CD7EF3DC63FEF65CE8A33B1B4BF784D008686B6471D0E9E699CA6E589DBB666D6C11B608B3F4030FCDD476F381CE03FE12DCBA93E2AF7BEF259BB86BC39AE969BEACCED93FACFD3707C5DCBE449245F6E2E0D0E689CF5B534C9EAAC4F083A38B5F869E025290C07DA6AB972158A1A07F2A1BE774848D05A1B7DB112CFEFD66CC91911DB54906557DC52036685F76B2BE5557D14E1B58C7A962F7A8706787F726076FFAB03997E438DBAFDC5FC38E1BBACA4533694069371FBEFA4E271AE66B876020C3C7543FB2BAFA40FBB08125EFB057FF3E14E253F3949745AD6AC708B87B598B9A28020FFD44A243661D0DF1B2F26E047B55BF1E502B5DDC5EFBFED7E18084D0E9DB9AE1E55B40212C4001D5B19BC93BC74CEE4BE3DDFC54E58BD56B40EC4A1E8DB3AE7C2CB982A47E147334868BD5AB4FCFF96389D90B0CA78A23C6CDF71CD155D2E2D20B7A7F21544475A4C10A90F304A174CABFF35450DC5185D505C45BBB034CC010AD2306909473C51ECC4F87019CF66959D07C83B4E6C29F946D8399E5E2BC4BD5B959BD29B87B82872514B0C8F86997C2BF78DA0E9BD6AC12F7109D2F05339FCE83C0A528A6894574D99EC76CA5F38C4E1A1E7FEF0110EA2B86F29BA2463448502BD725A90780F8F20C4DEAC5FBFD93BC48B4ADE4C814012BAF6C3EE604462F5B710D07D3FF86884D7BBFD755CBF136F2E51E693D205F1CA1FAE7C69932CBE89AA2706842B23271AB38A2639871B025D234B498EE34C04436670B2640471A3ADC444DD3ED165CD0DBCD0A22F5B34461E2BD6F0D13AA7408FDFFD5CE7F28DF3DC4CC44C5A5A33076125F78CBF5390C0829A83FCD10A7A73A56D94689BBDF3269E7F82085087B86E6F4AC449903C4CE7FC0948EF0EA57AE339F1A60EE0A299DF503561677C00F49ED61EBDC96670290DBC8C8EEE3D8B71C1EB0E49B95913739C8EE2049900610EE8FED70EE6B5D99FA11C5DA2B7336FA095B98BBD1E8545D1B4F35C73F4B5B501AFD2970BFC33078F66F4E86837BBEE43D3831065BFC889BE93CDCE21709DCD0A833D8C9A97E068EB4C7727499A7883C7A961555E64C6F6E2E2A577593C28A7D2F80F5C1230A74F3B1EBBB8380A8A185E7FD44F760C387C2BEA509A9E86C308F115F422D02A456E5261E3163745E3D22367ABC9F9BF1E6C75C1C7D271F568F06A344DF1BD84551FADCDBDE55DFE14743FFD36C8E071E0B85B6514A1F7780EF562D0DCE25AF095F7AA867A1B73CA9F6BEB2097DDD696D44CF4E645DEE67D159960C3AE7B8A587866C71F304E06451CCC62DA4C389B041369D6F58CB4C47E4E887475A6D84711A034C6D7EFA988C7A11E2E919CABF01AA2FA9D6216CD4A7F22FE692FFE1DB53E4CE1B5A7AEA2525E8F88B05D1297B5D435352D92A66035DB97FC06D1C74540A487DD48AF1BB462312A0EFBCE06B7317CC201EF86D48387421575294EA33282E65DD8D1BC87F575AB0E8FB92ED251D3D559A7ABAABD7D83F6E97189AC79D031449725B1F887070C02F9882073AFA471DA18DD15B4773A915AE3E23C8E70FAC216217928625D47D35EBE7C487432AD36DB44A1283D75616AB65E18CC3C4724882062FD50D8FA09DF41280304323330473322DC97233ED27461FFA436B6D194BC2F531454B3B80BBC4DC768F77FDEEB7D4E5D8AE6D97FAD09556799996D820990FAE21C3F2A91C2FD35D71BF0BC8AA26F00107EA708606D973C649C50AA0E09F082051C0AD5926567C512DF7971745E1CBB78CF8EE3EC075EFDDF9E53A060FF4CC4CE2A961630E46C8414074A2A5F92CE1BF236D0FEA264EA495DA9B925A62CA1E876D76E03B522B118F021BA817C2B624AF63EDED7AD7A48D30F9AD785AB30016AC34AF8F0D5FA057CA341E3D2A9B94F2C3CAACE30AE3A856DCF17BB43F8634915F3A2CCFEADEF07EB9B719D4509DB18CC10868EB4DDC7AFCC5536E009C1EE6EBF2BA8B1F60E3190E2F881C4DDC271E2E993246941B36C548092BCA953EA9CB946AAD1DE5A27B912DF856C09F2B4F4F658743C2629B1684B68A465E318A896A6E8FE4395058A26C95AFA6C46990A6B577FB41DF7ED8ED433663BD792B65308C921C5BD450C6253ECB33F4397DB7419BEADEB409D1D5FD9AE1AEAEC6AE31221002209076BBFE67F915F78B939133715493B32B97D5CA6D8C7C944346FD0F89058B35873EC808CA75C100A51C38010B6062B44C48EECFE49EA82943B94A812E9532753BE035F138ED92226D82F77CD18D945CB13F266198F511799865FE92D8B7BAA4D9CD6EABDC5E97B14962B86603F455E7EF457EAF9EA41323B4B0A7A93BC29520FC908C034AE3D660ED914F383C2F8F98534E536FA4ACA7C2B1A719D581D9C269837893C130FF3EAD5C98BA7B12D0BEECFC02FE6A8213FAEEBCB3B0376667B313FC62C831BAE913DE0BCE877881BB8060601700BE7853DDE98C121780F37D8C0C4A647F667A0E107E0DD6623D0B6533F1ED50450A9669D24F0A47FF3D532F846D7B2034E214B3B37C6EE1F36E9389837E0CB8CCB84970FC2A01AA189944E2DB2620E92B39DF0F2006F8F379C60CE38B88ADB3F14F6F6B216444FB0C63160EC03B397F552BDD3CA971066A6974E08F4BD4B60D219AE64EE1340752B5525E7133FF8F21803E77FA78C291FABF65D0ED54BBAEE1F0EFE6760C10BE545C405CBC597456FFCE829E0066AE53052CE56A7379E8B838A4A837A791A9798AE7F331F8E5C80B5EEAAA1127046D32A64AC23685EBA4F11335E1AB41AEE81B39A7B2A6741BD66CC40826F08ABC5EB5138E64D42F76BD641DCC5A46ED65D50AF5D7021DEFE796D71A8A7FFC01F889FC595734E0E07D6A24B2F36C28B70A08FFD9269A56ACF1B88F0C12ED0BC26733D9F78267D6AC77BD5A57F4D631DA8B9D73374230A8A9237A532F617EDE49AA4D00393B4D6874DD2D8B92D42C032B0ECB2326A77CEA9C02C0DABEB6C78242701561F5415674E6CD96C2EDD0E96EBA22A12EAD6502BE87B902A9988015EE0E675412600C7E4571A5C745E024295DE17427D9A69A355F176DCDE2C5BFDB1B548EAE6DFD8FA2E2A50CBFA90DFB69E0C939FC969DF9A501BBF7AB51017E7CC2B2752A3913451FE2CC061B0C9A95464A281E21976AC7287A431DAD74E287A3FEFD21978A75D9ACB35A9D10F54DAD84BEBF5A7A65F7F9419FD7E9101A04080D448701CDAA0D04413D1095CE33D39435C14A9798CEFF5C9FB8A9FB460C14157A28FA0F2BCE96E08A194CB27B656251AE24531DF2CF182B9009E104663DEF45AA9B3060922210FB531FCCE4137020CEB7C6E469DEECCC55FC04C822A7151F3B054F2CF33B052A1856FC31B6B90C4865D0CCC40806B2E8DC70334E86F285049F9836B414C406800DFF77B239C1F9DB0595639777E2581A5246158A50654F0C62911220A88C212F02EDE91161FD1DBC5269F6E6169BB57E5790EC1C4CDB21DA2D2F2C0BCB8EEC8BD349F128969E11B840D1947BAA65C79D8FBACB0D6FAA59FAF094DEF2F751F4F3E519A7D2AC8E5A3FE25E684648B3F6376C655EE912F19700AC3A0BE51A93D56EA67AC21D0BF6424DC2BE720AC23003A503BBE1FB5A0CEABADF7B26B71988A1403F3858247CBA9979ED4852EE31A156939ADD80574A1A230FD8812489D93D890DA7BA16900FD4DD51DC223AC82BCEBB52841A58E389608CFD01202132D35B846581BAF761DE5BE422FC6CE265FEAB725172D9D9E0545EBBBDF4C724F73217954EA64B522E08680EBE34F8B5AB163B798F5FFFD23C3F73F2B18F0D766084E6F4D830658867A7CB6909E055EFA391BA69B163246DCCBC96C38AB830E18D54CB1F54998082AA6A46C88AC43277DE95035BAE901A81AEB4DCCB41F93CDB9DC080396E9EF8A3A36A8ECD57CE8415972ECA84FA3715B9C0F5046F91C486B81ACB1544E7365AA7A248125A0B3A06E24EE55643F9FB9F6F9E99868E862E8810A6F5A6C25F7AEBA8EA1C1C8BEFD723ADE25D8C51E48912F05122FB54D91A196D41CADD54CFF5C41E9125CF3EEE2702D914C39449E6CB50138513F86A69B5D8FA6977F16AD026A1101BDBBA2A4D07ED50B2EC16CB12AD0544A4C09336637DA9DCF36C292850D229943ACE2FFC65C415C595CFE261335016C5F8B4F6FE11B9A8A396C7D352555353A3ACE365EDC9902D5D192267401FBE41FFC75912DE0B295BC49641BB96E92C10B451733893DE9C79F1B64810734B473631DA5649A90F4B878803AAD72D2A83C49E8A5B0815369F06F077A9F946EBF74918EE0D0433F3D0EBEAA987A1C97260BB7F35495501E62A5EF664E9D745C1804E5961542599EA43389203C539DD77F93909A3C7DE272A0F9D325B99E59B505F5DC8E409712E928A6F7962E728D466E5D42375891DEB0741298F1ED874B853E9FCA68F5562F9C5399BA5F59F43DC628D1C90FB7ECD60EB771FAD4A81A464A552CE62F1D8D05D990E9A9FCF787DDFB13010466A1B42ABED02E2F81DD66013C43744EB670BC6EC0740AA75925F2BC3C24B9F8A28FBD8AA5A8B5FFF106E0DD2B9BEAE5E01C4B725F1EB22ECDE0163B28E7CDF3B6CAA75B7772EF74D02603AC2BA16971EC69F96ECDC811BF0E7D4AF47ED133EAEB24FE1B93EC6C6FF85CD0E4CCC4332182260B8399997096A061748FEDA6C4B74C77DD74FE329A9547335D0F61264C8E2AF163296645C5F31851597CD034DC431DC0AAC0C3558E941ADA82A70CA246FD1191D989DC9CBD1DCEF334B82A0AEDCE2FD45475EC4F50E5F628CBABEDDF6102B809BD6ED242D3241C6CBDEE43157879CB6BC00000000000000000000000000000000000000000000030C141921272F35 +6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE008301E666F59D3EC5044DE456788FDE19EB39677B5F9FE14150DA463A706F3BAF715B95336B2D685A7CD7880713E4587BF7D857BF7E315696B8D0D9D49E142918BF0974E7F43237D4BE3AD394599E3D39BB7649932553447E5D5ACC3499930176ECD3A844A425F50D0511C9226C4B9A24F2A011CD88D32308E0312A0C87CC34A995823C65F4F0F98E50C37788CE38DC28FB8B9BFAAFA904B541EE712F6A041E0611374F6BF17EAC0BD56F3B6BF336DA9242070C2469A20C4D1616149A6159252011D299F93F986D875DD30B38A22549174570138C2BB3AA9CBEA91974F3D89BF5AE32BE9E58B854A2F8E86FF76780C03490F467DB0651C20B1DF60EB97A3C99D9BD664BE6A5E4C8A8AD4CC36390D7004E4BB421DAED654C357DA4D68498933EC71777AD64C2AE013C73EB457C68EF9A745ADEEB4FDFC879E774D03FAF6B14AAB10752E24B52D0F2D94D540A1EBE10F597E514442D6C13C2E2498E8AF3017C52DB233A90717DF25B4D072B7D88EE8731D16824C95D1FB983C449DEB466276060FEE4C7EE381451F232C29C7C3220850C61D1C3C00DB1CD9726A02A56609F3A65D3D164604588CD9B431412F1ADD914C5C2DABBC90467C0C4EA5F76E24AA618765F8B0636D7B065E1F4E6F622EAE17152458C766586772D363FA99214F472B0DB8A1E49D82D0278F2958B0AAA1586DB134BDFD2438742495007E2FE5B60E246399226947A12EA17631CAA534687CB75C060B4797EAB8277CC4F8A7A20387606EFE2DBD3E736249277D90FCAB992A8C99E85AB03EB4CAC5D88553958528AF92974718135F1D0C793EB000EA0AEC3EC1858FDD18688D1DA27278DEBF2CA8110BA4A204F7930E1C8CEECAFB73F75DDB34C5C55968A7933058426B55D039F7292AC43F64584F6DF187A1D6B003F514CC13B26C2F348195AA321DE6A27EC11348DE50D825A2964C631992E4B0B425B1BEB4F9600E3ADC4431CF2E88B4223D2DB663C3CE70EF85DDD56A9BAF138A9D7EDD894131C3A8F41A04EF9F86752B72181FABB37C86B877E61D60EED95EEFFABE6376E14ACA817C5F41961AF8A7849BAC094917B2D132276B6B3486AFF950D23D4AADC24CE98A5269E1C69917960A31EE09A527C358175CAA0CB1B018E9526D93534EADBACB52B273D735E22DD0D5C28FA3E47CFE90B5215AE24F146C3464BFEAF01D28DAA553C1E94428A104A9D78AEC762591E8879F76851CFB4648566721B0CAC1F14FE16149A9D8210CC8F2F50DEF7B46C843BE93BD8D55602493350AB560EA5BA17716423BE0EB8360AB109D8FB18BFEA040847B7335145D4F200D19CF6FE7BAC917F426C9B3D39A9CA4329818F240E7DA382761072F4A6505EA8E76C1E446FEB6625E38DDBCD3CDA81E83BF768F3E01D9D263B367303AE156C0B7183364A1E7941A09298A3ADF7BD231E6114B9DCE7952B113F78163138B9266F843F1ED97D9C2B163A6E8BD4C1AB4E179367C5AC96CECF5050FE821FDFA44E9E680B61C6018932DF717811459AF2542E2CDE77178C2E9880F011E405EAFA59C8CBBED76E5A1941104B1B9D3A60491C954755E02E894103F1F4977475E9EA36609FD67C9DE318EDA2370DCCDBB9CEF7AE6360905EC220838C9769823441CDD0DA8EF0ABE5F2D1D76E2FE08FEF53DE1D6166AB1A92B1AC093E5ABF7658C4B57287F2D1FD7B82DEDAF8D5A4FBAC4B35D58231694E162497578ABD7AA7C8FE7B3541A7F18E54E8B7F08764C5E68449DF655901549832D628FA63D2B2C5A150933994A9863317AD40D778D9D2C05C7898850B90173223C7A0AF890FD7E66221B6F06318B2ED5E199CB424885AB841E7A4726FABA2F9BB53BC3236434C35FBBE4B1A0F93F50C37896C29F8E302AD31ED3331D620E3B629455101A1F1CC7BA5E46E68ED4A8CCC87B4DC75BC0162B6330F833FBA2575DFAF5B5F28BC54FF2BA81E7A47313C15482B605E66BB38C6198F1392104080FBE78B86B1BC9A6FB881F5C7820147E6BA14B81ACCF20CAE96641094C216902EA5C125F6C935A150D7C9ACC5D9E2E5D90E38C0503AA9426017C76AAFCD5261B506274EC13A9679FB09796027A4BB759D928279B94D841A097393BF7E5BD69A496CC3DECD2B0F07F83392AADE33DC51B2A84F6A07635DC0EF57A9AD5959B6A50B7BA509AD5B11FAD26B419F9F1E3F9C7329B5A953D7CC87B2DE210611CF52A639EF2B3908012CB88E1D6F57625079CB103D6C98101A11BD2233B65602CA3049BD320520419F76B061E3598DE38152C88767D1A24FBD02BB10C38EACAE317DE6BB287B4D2CAE5DA0214965D8773778626E9B972859D8482B8D0547E4F56DFF87681D5BC5120F613FBBD91E1F14E6DEFE672E2A7EABCBBB9B11082C5E700AA0B1F7C1785FCED19A93AFE7C59FA2519BCDEB494C3D13B2125F385323B816C68F8F5628C7C2ABFD0278A337073DA74D16099698C4B114E8A8CE344E0A15D0FC7ED497B001D53D4C96DC3954D3B4B956CB9D2A272C51F1559B22904B40CC8531E40CC412C68CB6EEA4A4090B38E2797329985467E818A524D3228EACAE7825D3DAD2EAA422FDC77AED71A205DA7838D945E7FEC37E4DCA67E504CE35E5B045F56F1E8D7529EBD6F1AF7B6E939E2B7AB4027D37A5135D172DA1AF9CA2F728A6F37DE60DD23D97D11E75AB1FD51F8E9A1397E5822159DB583802B32EEBB4567ECE3746D1AE33314785643DD2A0741E7F1BF2D261F22124E8DDD08C640A48B54717517C21CD325328BC239CA028B2630D063C8CC20BE9BDB48502DADDE73FFED5963816533E020AED1208536255B1CCE985433127FF4F04D5B1E2F2108704B8B966588C0156AFC2AE192986FBEC443BAEF6CB85A6F29C7792405A24114710AE1C746444FDF5FB659E5E346826207B8C54463A0617CE17FF33E40F931FE576715C932EF29FD76B04A69B58E0303D8EF25678C8B70AF12E9045591C04E8B77106940415177E868593A09C7E14619A4B332F9ADC3A658B86017F32656C5429C115E110037A8CC7E544677D2DD239A59D54D0F3C7460EC15208346BA56DF5086C5DBCC41E0C95FCB6861C2C0C32AAF3454EFEE2FFBA214B430EF248A59B32444D8D0D3DB87C9D4B1536D157728EE7585EF532776A003A023C0AB0E9FF557108C390684D565A665063266AE6670ED53B0FAF8FF67829BB737825B153A9338CBE3DF1A462849B93A81F84ED07BE6D6240003274737F618DCB26E48252CE4204DD3139FF6876F43B305D835620FEDF79AA67433DC25287320E9917967B70B2D866D17B698BFFF2B3AB9514949E58B57C68A45412C1FC421C768BF5EE8A10C8AEF56926F51EC62C11569F31AA517868E5CAD89E958066EB9EDD7271B31CB4B1D6CE211225AEB5B57F749719DA07ECBEFE03881DDE3D81E4135F2DC81AF779776C1B8057162A6C982FBB4DA6A9AD284AB10C70022044F46D400BF6AD7182D197789983BE99227979A1334BA149D869BA1C4088123435BF978541356DAF171F33ADB1C97907A0FB5845074A85D26F546135AED0F91BE4539C12BF9411E4B556F687D069DB6B21FE2B7F321887448CEA55DB19FBB8B0482A55AEC16738D74CD265093836BE99D4FB53E9B014B037CDBFE9 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_output.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_output.hex new file mode 100644 index 0000000000000000000000000000000000000000..58e84009a3dd0e57ad3cafbec8d8c44ae33bfb41 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_output.hex @@ -0,0 +1,3 @@ +02 +0 +01000609608648016503040203BCE59D1F83462B9578534D7A05DC3F21C34EA93ED78387B32DE09ED3CD2A51EE2B8F7387C8C2D426EAF3795E99B158D467D9A039234FDF207D65D2577D1688E1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_output_KAT.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_output_KAT.hex new file mode 100644 index 0000000000000000000000000000000000000000..e09698fb95067730f2b5f73e1ed4a47b02814ad4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/Dilithium_ref/dilithium/ref/test/verif_output_KAT.hex @@ -0,0 +1,3 @@ +02 +0 +4AC4675C96D9117D1EDEB80D7CD284A3E1E1FE038E301205B4C408EB965235AD1C85F8BE3F77CA486FD207F7C75F4121CD3CA2B23D6BCE4382A6D36121815025D5806CBEF452E083933C6E5C7394AC88262A6DE7770B2D8843EC101FFB5E84DE2F7A8B74E7674B3B2319BD6BF4112F92C5CFC0A55F7FA061F45325408D039D51 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..6b52bedaf26e126ed08eecad93227c91450f22d9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/config/compile.yml @@ -0,0 +1,62 @@ +--- +provides: [uvmf_mldsa] +schema_version: 2.4.0 +requires: + - mldsa_uvmf_lib + - mldsa_top + - mldsa_coverage +targets: + tb: + directories: + - ${COMPILE_ROOT} + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/parameters + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/sequences + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/tests + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/testbench + files: + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_uvm.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.sv + - ${COMPILE_ROOT}/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.sv + tops: + - hdl_top + - hvl_top + sim: + pre_exec: 'echo "[PRE-EXEC] Copying C executable vector generator to $PWD" && cp $COMPILE_ROOT/Dilithium_ref/dilithium/ref/test/test_dilithium5 . && cp $COMPILE_ROOT/Dilithium_ref/dilithium/ref/test/test_dilithium5_debug .' +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+ABR_ASSERT_ON + #- '-v2k_generate' + #- '-timescale=1ns/1ps' + - '-noinherit_timescale=1ns/1ps' + #- '-ucli -i dump.ucli' + #sim: + #- '-ucli -i dump.ucli' + # Suppress a warning due to calling $fgets as task instead of function + # i.e. discarding the return value. This is in auto-generated code. + - '+warn=noRVOSFD' + # Suppress NOTE about repeated package imports within the same + # package (each .svh file included in the auto-generated UVM _pkg.sv + # files imports the same dependencies) + - '-suppress=SV-LCM-PPWI' + elab: + # Suppress warnings about too few port connections - auto-generated interfaces + # declare all signals as inout, but are driven at a lower layer than the + # instantiation, so they will always flag this + - '-suppress=TFIPC' + sim: + - '-sv_root $QUESTA_MVC_HOME/questa_mvc_core/linux_x86_64_gcc-6.2.0_vcs' + - '-sv_lib libahb_IN_SystemVerilog_VCS_full' + - '-sv_lib libapb3_IN_SystemVerilog_VCS_full' + # Report "MVC_ERROR" as "UVM_ERROR" + - '+QVIP_UVM_REPORTING' + - '+UVM_VERBOSITY=UVM_LOW' # Adding UVM verbosity level here diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/config/uvmf_mldsa.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/config/uvmf_mldsa.vf new file mode 100644 index 0000000000000000000000000000000000000000..141b1b69887b89764d09aad9302b75a533ba0a24 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/config/uvmf_mldsa.vf @@ -0,0 +1,250 @@ ++define+MAP_PROT_ATTR ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3 ++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules ++incdir+${UVMF_HOME}/common/mgc_vip/ahb ++incdir+${UVMF_HOME}/common/mgc_vip/apb ++incdir+${UVMF_HOME}/common/modules ++incdir+${UVMF_HOME}/common/utility_packages/qvip_utils_pkg ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload ++incdir+${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset ++incdir+${UVMF_HOME}/uvmf_base_pkg ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/coverage ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/decompose/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/makehint/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/rtl +${UVM_HOME}/src/uvm_pkg.sv +${QUESTA_MVC_HOME}/include/questa_mvc_svapi.svh +${QUESTA_MVC_HOME}/questa_mvc_src/sv/mvc_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/mgc_apb3_v1_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_master.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb_monitor.sv +${QUESTA_MVC_HOME}/questa_mvc_src/sv/apb3/modules/apb5_monitor.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg_hdl.sv +${UVMF_HOME}/uvmf_base_pkg/uvmf_base_pkg.sv +${UVMF_HOME}/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_master_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_module_hvl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_signal_if.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hdl.sv +${UVMF_HOME}/common/mgc_vip/ahb/mgc_ahb_slave_hvl.sv +${UVMF_HOME}/common/modules/ahb_master.v +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hdl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module_hvl.sv +${UVMF_HOME}/common/modules/ahb_memory_slave_module.sv +${UVMF_HOME}/common/modules/ahb_slave.v +${UVMF_HOME}/common/modules/apb3_memory_slave_module.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_master_hvl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hdl_wrapper.sv +${UVMF_HOME}/common/mgc_vip/apb/apb_monitor_hvl_wrapper.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/clock/clock_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/memload/memload_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/reset_pkg.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/async_reset_bfm.sv +${UVMF_HOME}/common/uvm_co_emulation_utilities/uvm_co-emulation_utilities/utils/reset/sync_reset_bfm.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/config_policies/qvip_ahb_lite_slave_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_util_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/coverage/mldsa_top_cov_if.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/coverage/mldsa_top_cov_bind.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_uvm.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded2.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/exp_mask/rtl/exp_mask.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_en.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cdc_rand_delay.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop_2sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_lfsr.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi4_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_diff_decode.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_slicer.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_count.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_dom_and_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sec_anchor_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_reg_we_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_packer_fifo.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_max_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_arb.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_intr_hw.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_onehot_check.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi8_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync_cnt.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_buf.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_receiver.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_flop.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_alert_sender.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv +${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv +${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_r1_lut.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_mem.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_mod_2gamma2.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_w1_encode.sv +${ADAMSBRIDGE_ROOT}/src/decompose/rtl/decompose_usehint.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_top.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_s1s2_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_t0_unpack.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/hintgen.sv +${ADAMSBRIDGE_ROOT}/src/makehint/rtl/makehint.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl/pkdecode.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_top.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_core.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_skencode.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_ctrl_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_mem_if.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_mem_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_seq_prim.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_seq_sec.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_top.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/coverage/config/uvmf_mldsa_cm_hier.cfg b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/coverage/config/uvmf_mldsa_cm_hier.cfg new file mode 100644 index 0000000000000000000000000000000000000000..f8b1e528fbd4ff86ae27a65d221a5f964bb5070d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/coverage/config/uvmf_mldsa_cm_hier.cfg @@ -0,0 +1,4 @@ +begin line+tgl+fsm+cond+branch + +tree hdl_top.dut 0 +end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_bench.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_bench.yaml new file mode 100644 index 0000000000000000000000000000000000000000..87a2a1b37fde849e30da51794006e95bf68f2eb6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_bench.yaml @@ -0,0 +1,14 @@ +uvmf: + benches: + mldsa: + + clock_half_period: 5ns + clock_phase_offset: 0ns + + interface_params: [] + + reset_assertion_level: 'False' + reset_duration: 200ns + + top_env: mldsa + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_environment.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_environment.yaml new file mode 100644 index 0000000000000000000000000000000000000000..e6ef08450750ed3172110091bf68ac945550a8e1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_environment.yaml @@ -0,0 +1,51 @@ +uvmf: + environments: + mldsa: + imports: + - name: "rw_txn_pkg" + + analysis_components: + - name: mldsa_pred + type: mldsa_predictor + - name: mldsa_sb + type: mldsa_scoreboard + + analysis_ports: [] + + config_constraints: [] + config_vars: [] + + parameters: [] + + scoreboards: [] + + subenvs: [] + + qvip_subenvs: + - name: "qvip_ahb_lite_slave_subenv" + type: "qvip_ahb_lite_slave" + + qvip_connections: + - driver: "qvip_ahb_lite_slave_subenv.ahb_lite_slave_0" + ap_key: "burst_transfer" + receiver: "mldsa_pred.ahb_slave_0_ae" + validate: "false" + - driver: "qvip_ahb_lite_slave_subenv.ahb_lite_slave_0" + ap_key: "trans_ap" # Assuming a placeholder key + receiver: "mldsa_sb.actual_ahb_analysis_export" + validate: "false" + + tlm_connections: + - driver: "mldsa_pred.mldsa_sb_ahb_ap" + receiver: "mldsa_sb.expected_ahb_analysis_export" + validate: "false" + + register_model: + use_adapter: "True" + use_explicit_prediction: "True" + reg_block_class: mldsa_reg_model_top + reg_model_package: mldsa_reg_model_top_pkg + maps: + - name: "fixme_map" + interface: "qvip_ahb_lite_slave_subenv.ahb_lite_slave_0" + qvip_agent: "True" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_global.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_global.yaml new file mode 100644 index 0000000000000000000000000000000000000000..562413a78821862157808557cd6d9e7710951f84 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_global.yaml @@ -0,0 +1,16 @@ +uvmf : + global: + header: | + // SPDX-License-Identifier: Apache-2.0 + // + // Licensed under the Apache License, Version 2.0 (the "License"); + // you may not use this file except in compliance with the License. + // You may obtain a copy of the License at + // + // http://www.apache.org/licenses/LICENSE-2.0 + // + // Unless required by applicable law or agreed to in writing, software + // distributed under the License is distributed on an "AS IS" BASIS, + // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + // See the License for the specific language governing permissions and + // limitations under the License. diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_predictor.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_predictor.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b2b56e84c00b3de057dba48116f35f0a288bd8b1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_predictor.yaml @@ -0,0 +1,10 @@ +uvmf: + util_components: + mldsa_predictor: + type: predictor + qvip_analysis_exports: + - name: ahb_slave_0_ae + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + analysis_ports: + - name: mldsa_sb_ahb_ap + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_scoreboard.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_scoreboard.yaml new file mode 100644 index 0000000000000000000000000000000000000000..359357aba97a37babfe1e036d2c39e9552e89387 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/mldsa_scoreboard.yaml @@ -0,0 +1,22 @@ +uvmf: + util_components: + mldsa_scoreboard: + type: scoreboard + qvip_analysis_exports: + - name: expected_ahb_analysis_export +# type: 'mvc_sequence_item_base' + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + analysis_exports: + - name: actual_ahb_analysis_export +# type: 'mvc_sequence_item_base' + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/run_yaml_uvmf_scripts.sh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/run_yaml_uvmf_scripts.sh new file mode 100644 index 0000000000000000000000000000000000000000..943280d1668ba90ea618c2340afc656e8082cbbf --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/run_yaml_uvmf_scripts.sh @@ -0,0 +1,8 @@ +export UVMF_HOME='/home/cad/tools/mentor/uvmf/UVMF_2022.3' +python ${UVMF_HOME}/scripts/yaml2uvmf.py mldsa_predictor.yaml \ + mldsa_scoreboard.yaml \ + ../../../../caliptra-rtl/src/libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_subenv_config.yaml \ + mldsa_environment.yaml \ + mldsa_bench.yaml \ + -d uvmf_template_output + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/.project b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/.project new file mode 100644 index 0000000000000000000000000000000000000000..af422d448e0f496219c73c90b72e6f423d176ae8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/.project @@ -0,0 +1,37 @@ + + + mldsa + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + verification_ip + 2 + UVMF_VIP_LIBRARY_HOME + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D/verification_ip + + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/.svproject b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/.svproject new file mode 100644 index 0000000000000000000000000000000000000000..7c05f487fabe9085fc7759718a7036e8470d1c03 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/docs/interfaces.csv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/docs/interfaces.csv new file mode 100644 index 0000000000000000000000000000000000000000..04f547ec08880b2f141f9ef512cac9b4175a1da7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/docs/interfaces.csv @@ -0,0 +1,12 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +, +Interface Description, Interface Type, Interface Transaction, Interface Name, + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/mldsa_sve.F b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/mldsa_sve.F new file mode 100644 index 0000000000000000000000000000000000000000..3394daa7bdaec2be8c0df5c3e7634bbbde226772 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/mldsa_sve.F @@ -0,0 +1,26 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// BFM Files + +// Environment Files +-F ${UVMF_VIP_LIBRARY_HOME}/environment_packages/mldsa_env_pkg/mldsa_env_pkg_sve.F + +// Bench Files ++incdir+./tb/tests +./tb/tests/mldsa_tests_pkg.sv + ++incdir+./tb/sequences +./tb/sequences/mldsa_sequences_pkg.sv + ++incdir+./tb/parameters +./tb/parameters/mldsa_parameters_pkg.sv + +./tb/testbench/hdl_top.sv +./tb/testbench/hvl_top.sv + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/dut.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/dut.compile new file mode 100644 index 0000000000000000000000000000000000000000..9b0008fc5d14c70eee9209d6fd817f7583a4b426 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/dut.compile @@ -0,0 +1,6 @@ + +# pragma uvmf custom dut_compile_info begin +src: + - ./vhdl/vhdl_dut.vhd + - ./verilog/verilog_dut.v +# pragma uvmf custom dut_compile_info end diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/verilog/verilog_dut.v b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/verilog/verilog_dut.v new file mode 100644 index 0000000000000000000000000000000000000000..96198441c694b55003c2a82a69e6cba58ae9a48c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/verilog/verilog_dut.v @@ -0,0 +1,21 @@ +module verilog_dut(clk, rst, in_signal, out_signal); + +input clk; +input rst; +input in_signal; +output out_signal; + +reg out_signal_o; + +always @(posedge clk) begin + if (rst) begin + out_signal_o <= 0; + end + else begin + out_signal_o <= ~in_signal; + end + end + +assign out_signal = out_signal_o; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/verilog/verilog_dut.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/verilog/verilog_dut.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..87e95f36f1bb04ad7bff0f159fb10c41157c6951 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/verilog/verilog_dut.vinfo @@ -0,0 +1 @@ +verilog_dut.v diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/vhdl/vhdl_dut.vhd b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/vhdl/vhdl_dut.vhd new file mode 100644 index 0000000000000000000000000000000000000000..904aa37d13a1de64524f687ce8664b6361ed48bc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/rtl/vhdl/vhdl_dut.vhd @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all ; + +entity vhdl_dut is + port ( clk : in std_logic ; + rst : in std_logic ; + in_signal : in std_logic ; + out_signal :out std_logic + ); +end vhdl_dut; + +architecture rtl of vhdl_dut is + begin + P1: process + variable out_signal_o : std_logic; + begin + wait until clk'event and clk = '1'; + out_signal_o := in_signal; + out_signal <= out_signal_o; + end process; + end rtl; diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/Makefile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..4b6751abe0a6f945c6b7068a7f51a7bec2252389 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/Makefile @@ -0,0 +1,208 @@ + +# +#---------------------------------------------------------------------- +# +# DESCRIPTION: This makefile includes the shared makefile and contains +# bench level make targets. +# +#---------------------------------------------------------------------- + + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# ********************************************************************************************* +# UVMF library directory: +# This variable points to the UVMF release where uvmf_base_pkg directory resides. +# This variable points to release code that is not user modified. +# This variable allows for UVMF release directories to reside independent of project related verification IP and project bench directories. +# This code below looks "upward" for directory starting with UVMF_* and returns first match for use with the release examples. +UVMF_HOME ?= ___PLEASE_SET_AN_ENVIRONMENT_VARIABLE_NAMED_UVMF_HOME_TO_POINT_TO_THE_UVMF_INSTALLATION___ + +# pragma uvmf custom exports begin +# +# Project(s) specific verification IP library: +# Directory where reusable verification packages for interfaces, environments, utilities, etc. reside. +# This variable allows for your verification IP to reside independent of project bench and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//verification_ip +export UVMF_VIP_LIBRARY_HOME ?= $(PWD)/../../../verification_ip +# +# Project specific bench: +# Directory where bench specific code is located. +# This variable allows for project_benches to reside independent of verification IP and UVMF release directories. +# For examples deployed with UVMF this will be $(UVMF_HOME)//project_benches/ +export UVMF_PROJECT_DIR ?= $(PWD)/.. +# +# ********************************************************************************************* +# QVIP specific code generated by QVIP Configurator: +# These variables identify where code generated by the QVIP configurator is located. +# The default values for these variables are to indicate to the user that the value needs to be set. +# This variable should point down to and including the uvmf directory in the QVIP confiurator generated code. +export QVIP_AHB_LITE_SLAVE_DIR_NAME ?= the_environment_variable_named_QVIP_AHB_LITE_SLAVE_DIR_NAME_needs_to_point_to_the_QVIP_configurator_generated_code_for_this_sub_environment +# +# pragma uvmf custom exports end +# ********************************************************************************************* + +## Check PATH for required vinfo scripts +PVAL := $(shell command -v make_filelist.py 2> /dev/null) +ifndef PVAL + MFLIST = $(UVMF_HOME)/scripts/make_filelist.py +else + MFLIST = make_filelist.py +endif + + +# Set test case specific Variables +TEST_NAME ?= test_top + +TEST_SEED ?= random +UVM_CLI_ARGS = + +# Usage of Veloce, etc. to be input by the user (subject to defaults) +USE_VELOCE ?= 0 + +# Usage of vinfo flow for generating file list +USE_VINFO ?= 0 + +# Usage of Veloce and Questa profilers +USE_VELOCE_PROFILER ?= 0 +USE_QUESTA_PROFILER ?= 0 + + +# Set project Variables +TEST_PLAN_NAME = mldsa_TestPlan +REPORTING_DO_FILE = mldsa_reports_script + + +# Include makefile that includes targets for UVM_VIP_Library packages +include $(UVMF_HOME)/scripts/Makefile + +include $(UVMF_HOME)/common/utility_packages/qvip_utils_pkg/Makefile + + + +# Include all requisite interface package targets for this bench + +# Include all requisite environment package targets for this bench +include $(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg/Makefile + + + +# Add to default compile/load/run arguments +VCOM_ARGS += + +# Note: vsim-3009 error can be eliminated by adding -timescale 1ps/1ps to VLOG_ARGS +VLOG_ARGS += -timescale 1ps/1ps + +VLOG_ARGS += $(UVM_DISABLE_FILE_LINE_CMD) + +VELANALYZE_ARGS += +VELANALYZE_HVL_ARGS += + +BATCH_VOPT_ARGS += +DEBUG_VOPT_ARGS += +EXTRA_VOPT_TOPS += +COMMON_VSIM_ARGS += -mvchome $(QUESTA_MVC_HOME) +COMMON_VSIM_ARGS += + + +BATCH_VSIM_ARGS += #-uvmcontrol=none +DEBUG_VSIM_ARGS += +EXTRA_VSIM_TOPS += + +# pragma uvmf custom additional_args begin +# pragma uvmf custom additional_args end + + +# Project bench package source +mldsa_PARAMETERS_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/parameters/mldsa_parameters_pkg.sv + + +mldsa_SEQUENCES_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/sequences/mldsa_sequences_pkg.sv + + +mldsa_TEST_PKG ?=\ +$(UVMF_PROJECT_DIR)/tb/tests/mldsa_tests_pkg.sv + +# pragma uvmf custom dut_files begin +# UVMF_CHANGE_ME : Reference Verilog DUT source. +mldsa_VERILOG_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v + +# UVMF_CHANGE_ME : Reference VHDL DUT source. +mldsa_VHDL_DUT ?=\ +$(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_files end + + +# Project bench package targets +COMP_mldsa_PARAMETERS_PKG_TGT_0 = q_comp_mldsa_parameters_pkg +COMP_mldsa_PARAMETERS_PKG_TGT_1 = v_comp_mldsa_parameters_pkg +COMP_mldsa_PARAMETERS_PKG_TGT = $(COMP_mldsa_PARAMETERS_PKG_TGT_$(USE_VELOCE)) + +comp_mldsa_parameters_pkg: $(COMP_mldsa_PARAMETERS_PKG_TGT) + +q_comp_mldsa_parameters_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(mldsa_PARAMETERS_PKG) + +v_comp_mldsa_parameters_pkg: q_comp_mldsa_parameters_pkg + $(HDL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/parameters $(mldsa_PARAMETERS_PKG) + + +comp_mldsa_sequence_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/sequences $(mldsa_SEQUENCES_PKG) + +comp_mldsa_tests_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_PROJECT_DIR)/tb/tests $(mldsa_TEST_PKG) + +# pragma uvmf custom dut_compile_make_target begin +# UVMF_CHANGE_ME : Add make target to compile your verilog dut here +comp_mldsa_verilog_dut: + echo "Compile your verilog DUT here" + $(HDL_COMP_CMD) $(mldsa_VERILOG_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your vhdl dut here +comp_mldsa_vhdl_dut: + echo "Compile your vhdl DUT here" + $(HDL_COMP_CMD_VHDL) $(mldsa_VHDL_DUT) + +# UVMF_CHANGE_ME : Add make target to compile your dut here +comp_mldsa_dut: comp_mldsa_vhdl_dut comp_mldsa_verilog_dut +# pragma uvmf custom dut_compile_make_target end + +comp_qvip: + $(HVL_COMP_CMD) +define+MAP_PROT_ATTR +incdir+$(QUESTA_MVC_HOME)/questa_mvc_src/sv/ -f $(QVIP_AHB_LITE_SLAVE_DIR_NAME)/qvip_ahb_lite_slave_filelist.f + $(HVL_COMP_CMD) +define+MAP_PROT_ATTR +incdir+$(QVIP_AHB_LITE_SLAVE_DIR_NAME) $(QVIP_AHB_LITE_SLAVE_DIR_NAME)/hdl_qvip_ahb_lite_slave.sv + +BUILD_TGT_0 = make_build +BUILD_TGT_1 = vinfo_build +BUILD_TGT = $(BUILD_TGT_$(USE_VINFO)) + + +comp_hvl : comp_hvl_core + + +comp_hvl_core : comp_qvip comp_qvip_utils_pkg \ + \ + comp_mldsa_env_pkg \ + comp_mldsa_parameters_pkg comp_mldsa_sequence_pkg comp_mldsa_tests_pkg + +comp_uvmf_core : comp_uvm_pkg comp_uvmf_base_pkg + +make_build: comp_mldsa_dut comp_uvmf_core comp_hvl comp_test_bench + +hvl_build: comp_mldsa_env_pkg comp_mldsa_sequence_pkg comp_mldsa_tests_pkg hvl_comp_testbench link optimize + + +vinfo_build: comp_qvip comp_mldsa_vhdl_dut build_hdl_vinfo build_hvl_vinfo $(VINFO_TGT) + + $(HDL_COMP_CMD) -F hdl.vf + $(VEL_COMP) + +build: $(BUILD_TGT) + +# pragma uvmf custom additional_targets begin +# pragma uvmf custom additional_targets end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_overlay.flow b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_overlay.flow new file mode 100644 index 0000000000000000000000000000000000000000..ad338f9724f741529693d381ab67d939fda21ba1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_overlay.flow @@ -0,0 +1,14 @@ +options: + # Use the following data structure and set the environment variable name and 'value' entry + # appropriately to point to the requisite QVIP subenvironments for this bench. This allows users + # to avoid having to set environment variables directly in their shell + env_vars: +# pragma uvmf custom QVIP_AHB_LITE_SLAVE_info begin + QVIP_AHB_LITE_SLAVE_DIR_NAME: + value: the_environment_variable_named_QVIP_AHB_LITE_SLAVE_DIR_NAME_needs_to_point_to_the_QVIP_configurator_generated_code_for_this_sub_environment + resolve_path: False # Set this to True if the value above is changed to something containing variable references +# pragma uvmf custom QVIP_AHB_LITE_SLAVE_info end +flows: + base: + variables: + using_qvip: True diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_testlist b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_testlist new file mode 100644 index 0000000000000000000000000000000000000000..996b9f99dec624b83d718a54c8a0c45ad5d5cf8c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_testlist @@ -0,0 +1,19 @@ + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO mldsa { } { } +# pragma uvmf custom tb_info end +TB mldsa +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_testlist.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_testlist.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9ea4f2935445032b653be667ad9ef7d7cf900158 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/bcr_testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: mldsa + extra_build_options: "" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: mldsa +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/compile.do b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/compile.do new file mode 100644 index 0000000000000000000000000000000000000000..226d1671d028f57da7929280dae03cb309b64e17 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/compile.do @@ -0,0 +1,75 @@ + + +################################################################## +## ENVIRONMENT VARIABLES +################################################################## +quietly set ::env(UVMF_VIP_LIBRARY_HOME) ../../../verification_ip +quietly set ::env(UVMF_PROJECT_DIR) .. + +## Using VRM means that the build is occuring several more directories deeper underneath +## the sim directory, need to prepend some more '..' +if {[info exists ::env(VRM_BUILD)]} { + quietly set ::env(UVMF_VIP_LIBRARY_HOME) "../../../../../$::env(UVMF_VIP_LIBRARY_HOME)" + quietly set ::env(UVMF_PROJECT_DIR) "../../../../../$::env(UVMF_PROJECT_DIR)" +} +quietly set ::env(UVMF_VIP_LIBRARY_HOME) [file normalize $::env(UVMF_VIP_LIBRARY_HOME)] +quietly set ::env(UVMF_PROJECT_DIR) [file normalize $::env(UVMF_PROJECT_DIR)] +quietly echo "UVMF_VIP_LIBRARY_HOME = $::env(UVMF_VIP_LIBRARY_HOME)" +quietly echo "UVMF_PROJECT_DIR = $::env(UVMF_PROJECT_DIR)" + + +################################################################### +## HOUSEKEEPING : DELETE FILES THAT WILL BE REGENERATED +################################################################### +file delete -force *~ *.ucdb vsim.dbg *.vstf *.log work *.mem *.transcript.txt certe_dump.xml *.wlf covhtmlreport VRMDATA +file delete -force design.bin qwave.db dpiheader.h visualizer*.ses +file delete -force veloce.med veloce.wave veloce.map tbxbindings.h edsenv velrunopts.ini +file delete -force sv_connect.* + +################################################################### +## COMPILE DUT SOURCE CODE +################################################################### +vlib work +# pragma uvmf custom dut_compile_dofile_target begin +# UVMF_CHANGE_ME : Add commands to compile your dut here, replacing the default examples +vlog -sv -timescale 1ps/1ps -suppress 2223,2286 $env(UVMF_PROJECT_DIR)/rtl/verilog/verilog_dut.v +vcom $env(UVMF_PROJECT_DIR)/rtl/vhdl/vhdl_dut.vhd +# pragma uvmf custom dut_compile_dofile_target end + +################################################################### +## COMPILE UVMF BASE/COMMON SOURCE CODE +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_HOME)/uvmf_base_pkg -F $env(UVMF_HOME)/uvmf_base_pkg/uvmf_base_pkg_filelist_hvl.f + +################################################################### +## QVIP COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(QUESTA_MVC_HOME)/questa_mvc_src/sv/ -f $env(QVIP_AHB_LITE_SLAVE_DIR_NAME)/qvip_ahb_lite_slave_filelist.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(QVIP_AHB_LITE_SLAVE_DIR_NAME) $env(QVIP_AHB_LITE_SLAVE_DIR_NAME)/hdl_qvip_ahb_lite_slave.sv +vlog -sv -timescale 1ps/1ps +incdir+$env(UVMF_HOME)/common/utility_packages/qvip_utils_pkg $env(UVMF_HOME)/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.sv + +################################################################### +## UVMF INTERFACE COMPILATION +################################################################### + +################################################################### +## UVMF ENVIRONMENT COMPILATION +################################################################### +do $env(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg/compile.do + +################################################################### +## UVMF BENCHES COMPILATION +################################################################### +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/parameters $env(UVMF_PROJECT_DIR)/tb/parameters/mldsa_parameters_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/sequences $env(UVMF_PROJECT_DIR)/tb/sequences/mldsa_sequences_pkg.sv +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/tests $env(UVMF_PROJECT_DIR)/tb/tests/mldsa_tests_pkg.sv + +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hdl.f +vlog -sv -timescale 1ps/1ps -suppress 2223 -suppress 2286 +incdir+$env(QUESTA_MVC_HOME)/questa_mvc_src/sv +incdir+$env(UVMF_PROJECT_DIR)/tb/testbench -F $env(UVMF_PROJECT_DIR)/tb/testbench/top_filelist_hvl.f + +################################################################### +## OPTIMIZATION +################################################################### +vopt hvl_top hdl_top -o optimized_batch_top_tb +vopt +acc hvl_top hdl_top -o optimized_debug_top_tb diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hdl.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hdl.compile new file mode 100644 index 0000000000000000000000000000000000000000..8e7bd41ac006d2a24f98a2fdc1f088d99b22d4c2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hdl.compile @@ -0,0 +1,5 @@ +needs: +# pragma uvmf custom dut_compile_info begin + - ../rtl/dut.compile +# pragma uvmf custom dut_compile_info end + - ../tb/testbench/hdl_top.compile diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hdl.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hdl.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..da27ec7737aafee5bfa929bb8f9e89fa9f8d11e4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hdl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hdl_top.vinfo diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hvl.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hvl.compile new file mode 100644 index 0000000000000000000000000000000000000000..ce95254966a11ccb8087ac0f7f4e7adff7da44f7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hvl.compile @@ -0,0 +1,2 @@ +needs: + - ../tb/testbench/hvl_top.compile diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hvl.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hvl.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..d22eff338360bd923bdd6611a5fd943938cbe239 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/hvl.vinfo @@ -0,0 +1 @@ +@use $UVMF_PROJECT_DIR/tb/testbench/hvl_top.vinfo diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/qvip.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/qvip.compile new file mode 100644 index 0000000000000000000000000000000000000000..a580d3f8f20d476d2d68c0269295e20221225d7f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/qvip.compile @@ -0,0 +1,9 @@ + +incdir: + - $QUESTA_MVC_HOME/questa_mvc_src/sv + - $QVIP_AHB_LITE_SLAVE_DIR_NAME +src: + - $QUESTA_MVC_HOME/include/questa_mvc_svapi.svh + - $QUESTA_MVC_HOME/questa_mvc_src/sv/mvc_pkg.sv + - -f $QVIP_AHB_LITE_SLAVE_DIR_NAME/qvip_ahb_lite_slave_filelist.f + - $QVIP_AHB_LITE_SLAVE_DIR_NAME/hdl_qvip_ahb_lite_slave.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/run.do b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/run.do new file mode 100644 index 0000000000000000000000000000000000000000..f13d0190bfbbb444fdf5c7e135ca737b638e5474 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/run.do @@ -0,0 +1,21 @@ + + +quietly set svLibs "" +quietly set extra_vsim_args "" + +################################################################### +## Check for additional vsim arguments passed using env var $UVMF_EXTRA_VSIM_ARGS +################################################################### +if {[info exists ::env(UVMF_EXTRA_VSIM_ARGS)]} { + echo "Adding more args to vsim command" + quietly set extra_vsim_args $::env(UVMF_EXTRA_VSIM_ARGS) +} + +################################################################## +## Launch Questa : generate vsim command line and execute +################################################################## +# pragma uvmf custom dut_run_dofile_target begin +# UVMF_CHANGE_ME : Change the UVM_TESTNAME plusarg to run a different test +quietly set cmd [format "vsim -i -sv_seed random +UVM_TESTNAME=test_top +UVM_VERBOSITY=UVM_HIGH -permit_unmatched_virtual_intf +notimingchecks -suppress 8887 %s %s -uvmcontrol=all -msgmode both -classdebug -assertdebug -mvchome $env(QUESTA_MVC_HOME) +uvm_set_config_int=*,enable_transaction_viewing,1 -do { set NoQuitOnFinish 1; onbreak {resume}; run 0; do wave.do; set PrefSource(OpenOnBreak) 0; radix hex showbase; } optimized_debug_top_tb" $svLibs $extra_vsim_args] +# pragma uvmf custom dut_run_dofile_target end +eval $cmd diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/tbx.config b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/tbx.config new file mode 100644 index 0000000000000000000000000000000000000000..eec58168c850bca0513bdb78f9c4219c12c7fa9e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/tbx.config @@ -0,0 +1,10 @@ + + + + + +comp -questa +velsyn -D1S +rtlc -allow_4ST + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/testlist b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/testlist new file mode 100644 index 0000000000000000000000000000000000000000..397a4e013b2556f9ff8f1cc2db248570d240922d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/testlist @@ -0,0 +1,20 @@ + + + + +# Test list for use by RMDB file +# File syntax is +# TB_INFO { } { } +# TB ## All subsequent tests will run on this bench until a different "TB" line is seen +# TEST <1st_seed> ... +# If not enough seeds are provided then random seeds are used to pad +# If no repeat count is given, default is 1 +# pragma uvmf custom tb_info begin +TB_INFO mldsa { UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../mldsa } { } +# pragma uvmf custom tb_info end +TB mldsa +# pragma uvmf custom regression_suite begin +TEST test_top 3 +# pragma uvmf custom regression_suite end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/testlist.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/testlist.yaml new file mode 100644 index 0000000000000000000000000000000000000000..dd0c179019d00de14b1c9166256ef278a006c8c5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/testlist.yaml @@ -0,0 +1,44 @@ + + + +# YAML test list for use by RMDB file +# File syntax is +# uvmf_testlist: +# testbenches: +# - name: +# extra_build_options: +# extra_run_options: +# - name: +# ... +# - name: +# tests: +# - name: +# uvm_testname: (defaults to test_name) +# testbench: (defaults to last tb name seen) +# repeat: (defaults to 1) +# seeds: [,,...,] (defaults to all random) +# extra_test_options: +# - name: +# ... +# - name: +# include: +# - (relative path reference is to the including YAML file) +# - +# ... +# - + +uvmf_testlist: + testbenches: +# pragma uvmf custom tb_info begin + - name: mldsa + extra_build_options: "UVMF_VIP_LIBRARY_HOME=../../../../../../../../verification_ip UVMF_PROJECT_DIR=../../../../../../../mldsa" + extra_run_options: "" +# pragma uvmf custom tb_info end + tests: + - testbench: mldsa +# pragma uvmf custom regression_suite begin + - name: test_top + repeat: 3 +# pragma uvmf custom regression_suite end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/top.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/top.compile new file mode 100644 index 0000000000000000000000000000000000000000..61a187f3df039bc60217aeceb4866a8451585af0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/top.compile @@ -0,0 +1,4 @@ +needs: + - qvip.compile + - hvl.compile + - hdl.compile diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/veloce.config b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/veloce.config new file mode 100644 index 0000000000000000000000000000000000000000..d097515557acf6f1b239cfac12cbcb50178b838b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/veloce.config @@ -0,0 +1,26 @@ + + + + + +# pragma uvmf custom additional begin +comp -num_boards 1 +comp -hvl questa +# Please choose the correct emulator type code for +# comp -platform command or else velcomp will fail +# Available types are: +# - Veloce2 Quattro: D2 +# - Veloce2 Maximus: D2M +# - Veloce Strato TiL, Ti, and Mi: Strato +# - Veloce Strato M and Strato T: StratoM +# - comp -platform +comp -platform Strato + +rtlc -enable_tbx_pragma_checks +rtlc -allow_4ST +rtlc -allow_MDR +rtlc -compile_display +rtlc -xwave_siglist xwaves.sigs +# pragma uvmf custom additional end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/viswave.do b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/viswave.do new file mode 100644 index 0000000000000000000000000000000000000000..78ef8e0a33cdef5a7cacf1ee8de8ee9cf74496c0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/viswave.do @@ -0,0 +1,10 @@ + + +onerror resume +wave tags F0 +wave update off + + +wave update on +WaveSetStreamView + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/wave.do b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/wave.do new file mode 100644 index 0000000000000000000000000000000000000000..58e82d95058c3f3bd6463564970ece236330f562 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/wave.do @@ -0,0 +1,24 @@ + + +onerror {resume} +quietly WaveActivateNextPane {} 0 + + +TreeUpdate [SetDefaultTree] +quietly wave cursor active 0 +configure wave -namecolwidth 472 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {27 ns} {168 ns} + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/xwaves.sigs b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/xwaves.sigs new file mode 100644 index 0000000000000000000000000000000000000000..d75f0a575b5b794226427e927e22f01a9fac3a01 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/sim/xwaves.sigs @@ -0,0 +1,17 @@ + + + + + +# pragma uvmf custom additional begin + +Group All + +#Top level signals +hdl_top.* +#Add additional levels or individual signals as needed +hdl_top.*.* + +# pragma uvmf custom additional end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.compile new file mode 100644 index 0000000000000000000000000000000000000000..382b4f451d329b9834ee90786ae738ca50841291 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.compile @@ -0,0 +1,4 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile +src: + - mldsa_parameters_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..b8d7b90c206fa8e206add630bb2b2bde0528a2e8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.sv @@ -0,0 +1,38 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains test level parameters +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +package mldsa_parameters_pkg; + + import uvmf_base_pkg_hdl::*; + + // pragma uvmf custom package_imports_additional begin + string dilithium_command = "test_dilithium5"; // default value + // pragma uvmf custom package_imports_additional end + + + // These parameters are used to uniquely identify each interface. The monitor_bfm and + // driver_bfm are placed into and retrieved from the uvm_config_db using these string + // names as the field_name. The parameter is also used to enable transaction viewing + // from the command line for selected interfaces using the UVM command line processing. + parameter string uvm_test_top_environment_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0 = "uvm_test_top.environment.qvip_ahb_lite_slave_subenv.ahb_lite_slave_0"; /* [0] */ + + // pragma uvmf custom package_item_additional begin + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..be0b779e229b277c2442bc9ac8c5a19b85bb3e33 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/parameters/mldsa_parameters_pkg.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +mldsa_parameters_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.compile new file mode 100644 index 0000000000000000000000000000000000000000..f6aa3e4f3059feb5b900ebb8ecc079d03ff1a69f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.compile @@ -0,0 +1,6 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.compile + - ../parameters/mldsa_parameters_pkg.compile +src: + - mldsa_sequences_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..9a593d3a00daa944e235c32a5b2401dd7f07b9f6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.sv @@ -0,0 +1,63 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package includes all high level sequence classes used +// in the environment. These include utility sequences and top +// level sequences. +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + +package mldsa_sequences_pkg; + import uvm_pkg::*; + import uvmf_base_pkg::*; + import mvc_pkg::*; + import mgc_ahb_v2_0_pkg::*; + import mldsa_parameters_pkg::*; + import mldsa_env_pkg::*; + import qvip_ahb_lite_slave_params_pkg::*; + import mldsa_reg_model_top_pkg::*; + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/mldsa_bench_sequence_base.svh" + `include "src/register_test_sequence.svh" + `include "src/example_derived_test_sequence.svh" + `include "src/ML_DSA_randomized_key_gen_sequence.svh" + `include "src/ML_DSA_randomized_key_gen_and_sign_sequence.svh" + `include "src/ML_DSA_randomized_early_run_sequence.svh" + `include "src/ML_DSA_randomized_zeroize_sequence.svh" + `include "src/ML_DSA_randomized_sign_gen_sequence.svh" + `include "src/ML_DSA_randomized_verif_sequence.svh" + `include "src/ML_DSA_randomized_verif_fail_sequence.svh" + `include "src/ML_DSA_randomized_reset_sequence.svh" + `include "src/ML_DSA_randomized_all_sequence.svh" + `include "src/ML_DSA_keygen_KATs_sequence.svh" + `include "src/ML_DSA_keygen_signing_KATs_sequence.svh" + `include "src/ML_DSA_verif_KATs_sequence.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the sequence package. Be sure to place + // the new sequence after any base sequences of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..38d90a728e53746cff03b171cd2beffa6959e76a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/mldsa_sequences_pkg.vinfo @@ -0,0 +1,5 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/mldsa_env_pkg/mldsa_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/mldsa_parameters_pkg.vinfo ++incdir+@vinfodir +mldsa_sequences_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_keygen_KATs_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_keygen_KATs_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..b11815703456ebd9f381914564fe9238eb47ca3d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_keygen_KATs_sequence.svh @@ -0,0 +1,165 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef struct { + string SEED; // Input SEED + string expected_PK; // Expected Public Key + string expected_SK; // Expected Secret Key +} keygen_kat_t; + +class ML_DSA_keygen_KATs_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_keygen_KATs_sequence); + + + // KAT arrays + keygen_kat_t keygen_kats[]; + bit [31:0] kat_SEED []; + bit ready; + bit valid; + int value; + + + function new(string name = ""); + super.new(name); + keygen_kats = new[3]; + kat_SEED = new[8]; + endfunction + + virtual task body(); + reg_model.reset(); + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + + // KeyGen KATs + keygen_kats[0].SEED = "38359FBCD79582CFFE609E137EE2EFE8A8DBCBAD18BA92BB433AB4F09B49299D"; + keygen_kats[0].expected_PK = "6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE008301E666F59D3EC5044DE456788FDE19EB39677B5F9FE14150DA463A706F3BAF715B95336B2D685A7CD7880713E4587BF7D857BF7E315696B8D0D9D49E142918BF0974E7F43237D4BE3AD394599E3D39BB7649932553447E5D5ACC3499930176ECD3A844A425F50D0511C9226C4B9A24F2A011CD88D32308E0312A0C87CC34A995823C65F4F0F98E50C37788CE38DC28FB8B9BFAAFA904B541EE712F6A041E0611374F6BF17EAC0BD56F3B6BF336DA9242070C2469A20C4D1616149A6159252011D299F93F986D875DD30B38A22549174570138C2BB3AA9CBEA91974F3D89BF5AE32BE9E58B854A2F8E86FF76780C03490F467DB0651C20B1DF60EB97A3C99D9BD664BE6A5E4C8A8AD4CC36390D7004E4BB421DAED654C357DA4D68498933EC71777AD64C2AE013C73EB457C68EF9A745ADEEB4FDFC879E774D03FAF6B14AAB10752E24B52D0F2D94D540A1EBE10F597E514442D6C13C2E2498E8AF3017C52DB233A90717DF25B4D072B7D88EE8731D16824C95D1FB983C449DEB466276060FEE4C7EE381451F232C29C7C3220850C61D1C3C00DB1CD9726A02A56609F3A65D3D164604588CD9B431412F1ADD914C5C2DABBC90467C0C4EA5F76E24AA618765F8B0636D7B065E1F4E6F622EAE17152458C766586772D363FA99214F472B0DB8A1E49D82D0278F2958B0AAA1586DB134BDFD2438742495007E2FE5B60E246399226947A12EA17631CAA534687CB75C060B4797EAB8277CC4F8A7A20387606EFE2DBD3E736249277D90FCAB992A8C99E85AB03EB4CAC5D88553958528AF92974718135F1D0C793EB000EA0AEC3EC1858FDD18688D1DA27278DEBF2CA8110BA4A204F7930E1C8CEECAFB73F75DDB34C5C55968A7933058426B55D039F7292AC43F64584F6DF187A1D6B003F514CC13B26C2F348195AA321DE6A27EC11348DE50D825A2964C631992E4B0B425B1BEB4F9600E3ADC4431CF2E88B4223D2DB663C3CE70EF85DDD56A9BAF138A9D7EDD894131C3A8F41A04EF9F86752B72181FABB37C86B877E61D60EED95EEFFABE6376E14ACA817C5F41961AF8A7849BAC094917B2D132276B6B3486AFF950D23D4AADC24CE98A5269E1C69917960A31EE09A527C358175CAA0CB1B018E9526D93534EADBACB52B273D735E22DD0D5C28FA3E47CFE90B5215AE24F146C3464BFEAF01D28DAA553C1E94428A104A9D78AEC762591E8879F76851CFB4648566721B0CAC1F14FE16149A9D8210CC8F2F50DEF7B46C843BE93BD8D55602493350AB560EA5BA17716423BE0EB8360AB109D8FB18BFEA040847B7335145D4F200D19CF6FE7BAC917F426C9B3D39A9CA4329818F240E7DA382761072F4A6505EA8E76C1E446FEB6625E38DDBCD3CDA81E83BF768F3E01D9D263B367303AE156C0B7183364A1E7941A09298A3ADF7BD231E6114B9DCE7952B113F78163138B9266F843F1ED97D9C2B163A6E8BD4C1AB4E179367C5AC96CECF5050FE821FDFA44E9E680B61C6018932DF717811459AF2542E2CDE77178C2E9880F011E405EAFA59C8CBBED76E5A1941104B1B9D3A60491C954755E02E894103F1F4977475E9EA36609FD67C9DE318EDA2370DCCDBB9CEF7AE6360905EC220838C9769823441CDD0DA8EF0ABE5F2D1D76E2FE08FEF53DE1D6166AB1A92B1AC093E5ABF7658C4B57287F2D1FD7B82DEDAF8D5A4FBAC4B35D58231694E162497578ABD7AA7C8FE7B3541A7F18E54E8B7F08764C5E68449DF655901549832D628FA63D2B2C5A150933994A9863317AD40D778D9D2C05C7898850B90173223C7A0AF890FD7E66221B6F06318B2ED5E199CB424885AB841E7A4726FABA2F9BB53BC3236434C35FBBE4B1A0F93F50C37896C29F8E302AD31ED3331D620E3B629455101A1F1CC7BA5E46E68ED4A8CCC87B4DC75BC0162B6330F833FBA2575DFAF5B5F28BC54FF2BA81E7A47313C15482B605E66BB38C6198F1392104080FBE78B86B1BC9A6FB881F5C7820147E6BA14B81ACCF20CAE96641094C216902EA5C125F6C935A150D7C9ACC5D9E2E5D90E38C0503AA9426017C76AAFCD5261B506274EC13A9679FB09796027A4BB759D928279B94D841A097393BF7E5BD69A496CC3DECD2B0F07F83392AADE33DC51B2A84F6A07635DC0EF57A9AD5959B6A50B7BA509AD5B11FAD26B419F9F1E3F9C7329B5A953D7CC87B2DE210611CF52A639EF2B3908012CB88E1D6F57625079CB103D6C98101A11BD2233B65602CA3049BD320520419F76B061E3598DE38152C88767D1A24FBD02BB10C38EACAE317DE6BB287B4D2CAE5DA0214965D8773778626E9B972859D8482B8D0547E4F56DFF87681D5BC5120F613FBBD91E1F14E6DEFE672E2A7EABCBBB9B11082C5E700AA0B1F7C1785FCED19A93AFE7C59FA2519BCDEB494C3D13B2125F385323B816C68F8F5628C7C2ABFD0278A337073DA74D16099698C4B114E8A8CE344E0A15D0FC7ED497B001D53D4C96DC3954D3B4B956CB9D2A272C51F1559B22904B40CC8531E40CC412C68CB6EEA4A4090B38E2797329985467E818A524D3228EACAE7825D3DAD2EAA422FDC77AED71A205DA7838D945E7FEC37E4DCA67E504CE35E5B045F56F1E8D7529EBD6F1AF7B6E939E2B7AB4027D37A5135D172DA1AF9CA2F728A6F37DE60DD23D97D11E75AB1FD51F8E9A1397E5822159DB583802B32EEBB4567ECE3746D1AE33314785643DD2A0741E7F1BF2D261F22124E8DDD08C640A48B54717517C21CD325328BC239CA028B2630D063C8CC20BE9BDB48502DADDE73FFED5963816533E020AED1208536255B1CCE985433127FF4F04D5B1E2F2108704B8B966588C0156AFC2AE192986FBEC443BAEF6CB85A6F29C7792405A24114710AE1C746444FDF5FB659E5E346826207B8C54463A0617CE17FF33E40F931FE576715C932EF29FD76B04A69B58E0303D8EF25678C8B70AF12E9045591C04E8B77106940415177E868593A09C7E14619A4B332F9ADC3A658B86017F32656C5429C115E110037A8CC7E544677D2DD239A59D54D0F3C7460EC15208346BA56DF5086C5DBCC41E0C95FCB6861C2C0C32AAF3454EFEE2FFBA214B430EF248A59B32444D8D0D3DB87C9D4B1536D157728EE7585EF532776A003A023C0AB0E9FF557108C390684D565A665063266AE6670ED53B0FAF8FF67829BB737825B153A9338CBE3DF1A462849B93A81F84ED07BE6D6240003274737F618DCB26E48252CE4204DD3139FF6876F43B305D835620FEDF79AA67433DC25287320E9917967B70B2D866D17B698BFFF2B3AB9514949E58B57C68A45412C1FC421C768BF5EE8A10C8AEF56926F51EC62C11569F31AA517868E5CAD89E958066EB9EDD7271B31CB4B1D6CE211225AEB5B57F749719DA07ECBEFE03881DDE3D81E4135F2DC81AF779776C1B8057162A6C982FBB4DA6A9AD284AB10C70022044F46D400BF6AD7182D197789983BE99227979A1334BA149D869BA1C4088123435BF978541356DAF171F33ADB1C97907A0FB5845074A85D26F546135AED0F91BE4539C12BF9411E4B556F687D069DB6B21FE2B7F321887448CEA55DB19FBB8B0482A55AEC16738D74CD265093836BE99D4FB53E9B014B037CDBFE9"; + keygen_kats[0].expected_SK = "6924BB4257A7B9AFF095C30BB35C6AE4198263120F8039AA4E78E174A786CE003B9AC2C1422A1AE802DDD7464D3F32729A3C7DE894D506ACAD25CEB372EA3149C98780DCD1314BAA29B9B807754C47DE5DCA954064F28528B815FE27B79AC506B3AD7629D2C971AB8F282E0C6E7E5548EE0E113242B7A0E064A6DBCE30C5619B19800889A04404B50013C088C1302962124CD3B4910A352C43123119996522185202C38523440D90244A1A30224428618106291897680A200908326A44A44C4490218A16689AA8511AA52C62468D04C340D3862860A46013187084948C63C04404A92820082043162A23292D1AB12948B60921883100C53000C48CD98268E1304C6332450C328618083191980D10B8709B302264040893A48C21C9700C35715B000D143122CC98102104809B28641C308021307118335024254408178CC00848844490489830CA440009195119230C52200E4906321C154E194885132549A3000408156D20410CDA4252C1348C00316943822464946D1C81110196214B0200CA2884CC466451186A181000A4982160B06803946C94485180404692222C23446998264D1C01085202208AA6080A316193400E9CC81181322E21158484C24100227254226258069248484411270404C011928245A1C68CE33266C138725A86010CC99084340858A86080C070D026629B302A04296904108D0BB904504628504824D04805A24802C3208CA014004138214B240104B5494200000C2428124084A220449B069063C0888C14214912105416242087445010850CB564DB2441D042299A168A21B44C13B77010C085190269CC40611C4846980625601446E4226224272262242944C62D08318420322104B4610A3812D92844A40820CCA8290B21310A3429032140C1A26C8A161252A664A3B251042951C4049163B02D1444308C40660C400C01A52C09942D62C61103985019104D19A828D38640C0306554A671E0B4859B8610043669D0462918A371402249004385CB4028893666412269A42851D98029140721DA80911B26505BA0609942715088491023095A902122278E43B2700CC94CA402709240100A397002360E113041D8402D1B246DC392614C868D21B800D3242212C82112998509160C5AA22409344210A22403428CC0B28D12B66963340DCCB065A112114A3869CC148158440954A6800CA805C4388A8406019B322D831290090260A1288858104124400219344818A04D001062132250E338219A962153088051260199C4281BB97104978404052CA0C210D3428181424D61846C5A30491BC224C02028CA922D4A90100427864C962109194514822C11A69113B80403187001A2515214495A0230CB302C94102C00498609A025C2124C1B026940A444411662022528DCA22D0016425830665B8624D42448DB260C4C088501904921244154068402434A244205401448CA4484C0420C9826049CA205D1C2511301861CA150D902500C39868C0031220548D31081124805D1086962382C0A23709B4472E3486E22967014336CD8902903004963208A039125088921C0820C994032C2344E4B9869098044E4046994200999246D09A96001292DC842288A3402E408700C236E0A054964442A82C800024831CB90501C056812122CD0800C594861CBA6099CC08142B80024418A94204042144D19466218050924336AD400611248328A047293B46962C27141A68944963162304683426C00192209464D8B0649E1B070424431C180659C002411A83113212C4B46281B180D884270D1B00D90C845DAC248591426224400C2944150C804180000CBA62419021010890C18222162A881C89248D3942082067209A8900C498A41862819C5809A184D14102E2212520008120C334563C63010934C60C631DC400E98825060022AD22240E4062DDB320ECA324ED4182408C3284AC268E28040A1C86451C265CB166023094C820468D9222E1C499242242100370EC812726408250A202A58240459164C08173000460512904003072152C0641C836D9C322E11158A1035885AA08DD9804803B64C0110651086401101420AC164DB224D64B25102360D93463114B668638429C8102494300819370214824588284054A8299014126136120B098CA49828C292454C006063C481C03625CA882D244030D3A82DC9C825D2844800329250A271D3440D223460121312868C5F8620794A050E20D0E1011786240EA664F2F69BB1B7E30EC66B1A4A0BE59B79F2198AD9804483E475E53B3C49CB0CE5EF92912AF440F23B995813D11B59F798E93C9D13539817C7AC68CAD1AA1AC27656BD0C4797E9C8EC17784C1A327A9DFEAF4D6191EECDAFE049B733FE39D5EB4000936FEEFCF82928E9F94CFD5CF4C1E3DEB1433A47F6D328B5E83DD156D0182DC692347591AA6F732CFBE982935FD1846CACF4CB8515C55AB85EE5AD44CB09D3269E2E6D11780961FD131D5E6FBF89849F47F2B71D8283FF25385E52B07DBB266C674CEE3D0B5DF5A56D8BDCDCFAAEE6A248E71DB1345AFC597CA830A1A35B4396EF4C1ADF9ED01BCE9B6EB637FA24AA160B9076BAE30559F8B29DEDB3D25B79064AB0CF8B8D70ADDDEB8B174248D5AEA4D18DE43B8938CDD2ACBA5477BD4AACC3CE595E5D269FE675210D23152B04710F368428794A75F49B683ED20DD647515777955A8CB38A36AFCD2CE0ACEC4F0DFE807702D1EB3BDE72E9E085AA4E09EB1B0947413852EC3C0AC52F06CB959C85394EB3748119EDBE6C80D2D8F792CE0D915E4F4B151EFB135E7F4DC97D858141C57F70417B43A6A126956978D78EFB9F037243B4CB41DF968B7EE5B52087F05AA9FE487BD16C0347CF1335760BD2398AD54DDA00A5AAC446D80B1C7998C602192ADAFCB809D14EE328641BA3AA00F8D29C3A848ACBDC1946BC0D35E0BE0F8F7E3DA3F68D9FA9768F5CF275534A0ECA9E60FCEA38F1E042C316143A767B33ACCAD8C8D66C70C75FD1F0B2586B653AD4AF54E56EF06933EAD31DE365D110B9C4A2A98BCBA165CAFE386F887C72156EB14FF0DAD665616CE3CE65C1904F2C1747B2EC2B5C9D6776BCD79E5AC64B7933BDDEDEDDBBC725BFDBCCDE2FB375AE2BE3537BDF89BF4C25F83A49D6A6A8D0761CF39D620C53ED837D198255CF5B910A6DB57877DF92D8BB6E9C526B8C4EC93100DEE0500A210C984583E1538160EDAC2C6F866E7F5D99D7B1B81582F5D0EBBF2786E3F556013BA9B6F656EB798838EA0579201A95D56BBC3BCDB9511AFBD4D81288896F87108C077F1A81A3BD297BB124A80086890242995E03CF42A0C21E272A9AFA1DC103463D2AB494F7D017686D31894DD2F6EBB0C3CB6223EC79C65D45C1B0D4EF1961F16D653FCF25977B651EC51A13AE8D4A3472EE71969A7A936F5DBBB9396A46D97642358CAF4894C9A6DF84A59C5962A6990A76F0614890169F001870D49CF2E75008CC4A5D85E72DE2D6CF3FA71852253522FE8B0E423CB417A38EB78C8763C3720C04E67FF88979EBA09E34538BB523B99B8E34167412F77AEA894D83ACF946FC054D0AF47295E51ED83F7486940A4D41C04AD7EBEE610BF1D03FA54071D51A1509E4F49163A25081BE8790D087F5F4F05C88550FCA9BF99C9BE5953D51DD0845C93E41EEEF62E0794B2927C4F5ED9BD3E34EA9200A79DDEB4B2D8F305FE05F827C7E2ED186341CB5D1152FC80104E0E13683D941294C778417164B684A976E56E78DA4D17C3C73229314870B85C455C23B830B9A28A3D8C0B566426DC169F326ABCE2EFFF39E9B199AE5C1292B6F2EF37AF1DEA9272C8D5423DF8A5632F991E14DCA2514788B62BE164828E9ACB893DDA602A5E2FB9EFCBEFD95ABFB82D2B02D49CC53084A49AB1BEC23E5B4C8E714CB03405F1BCF7E11BB59729DDC0B7BEFB291276DCEDACAAD39A2F01C7DC98B9E065EAFED1CC8CE3E848080A2FC5B98C9F6BF5040273342F0312F8B9844594A503DD3E6AF1C9E35C1032A4A8A5E7BF33A82F35E16EDF8C60C90021D8C0BA4C386245DFEF09448431D8C00D1E26EE4D8C77DAA1A705ED4792ACB4EA27C1566FB56683C43BF67842E67534CB3F9677C8AB9D0EEE7827CDEFC223AC948B880B5F1CE9537272932002C1A4DD218F527166EBFB2B2FA2BF37246ECDFDFA72B6DA11C30D1C7D248AD64818F691D59B755DAF71BED9AB5FB52E03622A900D66B4C6384169BDF9EB61C02DF45FB76B1A26F34E938B190861745C021FA876200C7FC8E222DDBFAD8BE781B185424AAAFC65862DB132BEC6D18837A1F58A876C99E63F51420B83F459675612F7ACF80B4EB1DD0721CAA1B4970DA608679C6383E817FE16B66B19181EDFC39270C7E917B1F10EB7A011997E967853B78E00CFD58D224D933CC5A995532DCD4E532E4030515F4A05B331D575DDAC29BAB069F09AF0D173373DB1EC2B6366BB371008A2386FD88BE77F5ED5E198CBE88DF24BC6E393FEBC10C470A72D47C0F834653C9AE800E893C6BA68EA28A838FCBB69C3E964A5FAFC2067DD406B257C98DD3979EC7C7ECBE96A33D85515DA2CB6AA5E1FFF204AF62DD4119A0E48C04A3F2B38660F52964D8D4AEE146A9C53C31906DAD0FD90B5D83B3E31B690A4C4935249981BE1F1A85EC6E0FEE4C88F2D89E2969AB8CBBEB501916558D29EA7C3ECF1C9EF1A04350633B4CDA737DFB151CB5E7361173F3AEDDDF527D73F2F9D5B6213AA68F883E9A2633785EC6BE642A9FD0F21A42F6B9DAABDCD1E6ADBEF64841B59686EAE3EC88EEF0A9CBC12BC012622DF2DD93A86229044AF2F260D2183F51E833EE92D98F0251E3F85FAB74CE367B8B7AA63D3CF8C8BF4D78358BAE0A0241E210AC69353087CC7331357EB4450F9509CFE595F54032EE057754A8EDD746CB9282E768DC6B830C5B4A219343AD124EDB3BBC42505566A7038C959BC35585B6055F1968DA243F778F4E46DB462ABEB93B81243C31EB59622EDF81F06CCC61D2A6EA73E109C387915F277BCF1FC11105BBA70293C0FAB5C065F23BAA19290A302F08091107A4B1D568852622098383427760EF8F2928625BDDA5F514C5ADE959891EF2959F248A3532BF9D30E714059EBDEC958708F8A83C268BEF2682D603CA886347E198FD68233999C77D30D7455DE6BCFD0144277062B304BEF0E34C5A9D8D780D29EC2321E07340771C46360483ADCAF12D5B79FDBFE2856ACE8859F6B12414B3F7E8BB5813498960F34FDC64FC848579CAF9DCCF19B4FB825ED5716DCCCD6872CBDE3831D67384942CD8A9EC4BBFEF5706B8F9F05FE1E8FE69D3EA6A8621C22144177B1C1259E1A79DFDF89728887BEF1A70482556831B672440E13FE3E3FC8204A02EA1EFF19D95253887285BFBEA16A0F219EFBCEC30A8AE86589A5703103A8A393FA6F6B657704AC677C14CD10D3D62D13FBD378C2DDA325B61B85952D51293871E1FCDC948C77BEAE9A6F0E87CE1A8051C8F8087685C12624BDF58380ED66F55B43DDD6D362173A5BD389859C17D95ECE3AB732639FFE451CD103EE4854DB2F39614F658BAA384BC9948D0714EB48A887143E7A1FA4B690C22B492A70C612B59FFD2D6B3B5E99C2003E2C359B1E62DCB620C7A246A7B9B3246131556F2F3D513A23C6A9FD2280ED686D767CCD01754EB4C99692F2B380C36081344C1D35EE1949736B6976F4852CFBE64FABCF11B9AFB828576B4F9787AA7D03E84598A7143EF7311FAF2970E23ED4C173F985D6450165AE3E241A18234E74FF3DDB921A5300B1C4FB6E432E698F53F66E38C07BCD6E77605DF4624D579076292DE1CE6FC6F0081A38BD92D39B24B73BAC1C52BD68E9181D3DCD0AC7534DB48901E5984F9902557BFA231B2EA28C3183262A1B2221F7426EA88A5816093A5CAE2CD5D59A9390FC93A2956944B064CF013BCDB67FB423D1328D2C6D7BA329013FA2D30EFD69FDCA1A95EA6D06C7363534B2F3F7DAAFA296EAA09B3668E9CF82D9BA959B32F3CAD3C10C6EA48611554539C37DF6BCA3385EAD3FCFF96D372B42393B73C8DAAAA31506EE0527B7FB3E593DCCCA57C8FBBD4A3C7F8A53899869132FBC3E4050607BBFE29C675E3945E74A31CD531BA7AEB2E2F0CD990B8F983A90DFEA0568F0677EA9563F7C479DE968940CF242992692865CFDA89FA078BBEF49CE4575BDFB380366011C8435F12B42D9AB99AB6A31912C4354149D723101D1365A65E7CC68D82E30517773902FB38DDA2B324E7208E987ED287D092E7662A430241BFCA552D314127E38C8597A89519D4F1E62A79465AD5F4EAA3FA77CD98326D2F92CE9852055CECCF62D63CB9D7F198AE085E4D45C8E48FCFFE593AD652D9154167BF3E6195810A445AE158F1F9A6793363AFC1F22CA882FEED3A5F5727CA76477C5F23F0FC8700CDC6A5BCB2B20B4F9266351D304A96A82BF5F314AF685C1C707C92E3E847B7047D689C70B25E5501CAEC9919626F4A0FC81586AF1EC88889B423387D5D95482618A650E80B53B07CACE3228940602E3DB47466CE9BCCB6E4D8AA61C8912583E810B3B2E7E9CB48BD403ECF08D28C70AE0B620859C1F09B61131404C3D5BFFCD860E0F42AB299006230B2876D77DDA91C8C62BD93A844E4B344E3255EEA531C6C458D04ABDB0FAEF2D1C0B4C55F570A5A51023F4D4EFFF59F9ABE17922FE732CA71BCD434AD7710B84CD4AC9F2507A06826562AD7F647826F9DBBE4EDD23F124369DB8526FC2B4D52F0741415F972BEF6A935BD812A56C8221B7DEF0F5106BC01E913E3D43DB86C2BB4C7E0762663C6DE788721C2AA07F8954887E2142F2E914A099EFC0AEE1339210D3E53DA3ECF88624B1119BE34010B886C80F51D1850838F2150E72B042AF32899C0D3D7B02A57F8CF263A369562E4E945A31282A502A95EE9BB0316C6861006DAC17F936F54C4C7"; + + keygen_kats[1].SEED = "29B4987C62218C19C77D695EB904AFFAA1BFEF6A52F138604CDAB1534E66DC10"; + keygen_kats[1].expected_PK = "4E130489218BC6CD1A9DF06B2586365F4362D8A007563DD1BF7D77F29663CB459F1B080DCCA1E39FA04CC66B9DCD4A6CDD2FDC25B96E87D778C068A41D7D4AB8FFA0E156AEF370568021A0F56EC60853AA4579F7C7151A31A7A8E5257D791D06ED11CB264B658467E82EC5EFEEB6FA224577EEB84D4453C82D821B87771FE57B10526B6B003E94F9CC812731C08A4B9FFCE90A06AD3134BDA3CF4E7E46DA7BC775B95116E96B53817CDA3FD3BC4D6F612C52BC2EEEE4153159B6D223E7A7B20EAF926C822DD064375FD26CEE2DA8DBA4665409D5A4F38BA2464D393FA00258379038331E4FCE0115988C634A95656888EB26E95049435440F42006C3515C7BCF4EBD138792B163ED11ECB45719D9B7821D6F7768B631D67DC614CF595C42FD2255252152C38190A5E41BC5868839EFD2E12DD73AFB61E8719C0ABC10679249DA931B4BBA405A46C3C112A4004A8E3A273965DB3AEBD8CA5D2BD12584160CB21369B1C5163D111DDBFC040CECDAE8B580B038B0D476211B05414A04B72AEA2FF2BE302422CA22F77CC5E4B576BDB838FBCDE65606F841030C2EBEB821619EE7C3C60C82BCBC3D55B0150A72A95EB2363121B925414138674A0619E128EC73EE4A9868D257F79F27658657CB72D9987FD03826C38DE6509F97B25144E4D0FAB4F40A3C152CCEDD908C50F8EB12E775CF512337BE1DB1AE9B320541EFC0DBC70ADC7C50494295C11D5770D6AECEAE9EEDDA468AE90800474D80B5BAA4CFDFA0A56F3C120C8A2397F31C429F915D1E748539C2A60BF05FA043E93D503FFFFD538D5B22BC0FE8498DCF20EDEBFB9FB973CB00EFFB3B65DE718292D783A16BF01301AD2EE546D48C0F44A05323EB15137C0527CB1A55775A6BE5B0F3862BD8EDDB3CD54F9AFABC42916DB1473DCDF9FB115A64F8EE011F2CA6D11528384B3757711ACA40979C23E65DF41F8D4B2D593C1351B713AF8421970D9ACD3F7E7ABFC764B8CD985159A78205F20C7A478CD987A18325F20D30C33B172E94A7C8F3B097A0627EFB6DDF787973F4B410EBF38E3215B59A4C218FCB5973A378D9A2CEE29986A61B841069BAC816147D0D8DB1BFC8E7E0FE811B589484F19FFD03890861703A27A0C9D451048C925C40C888410044F7420FC25B6B79F99E1055BE964968C354C917F3F981F7B67D1AB451E127CB50E5A1B8C3F179C3FF2175DE548D1137297555BE12489E6F3CF2831DD0E45F2E4151011DBCFB8D55AB280C0F0B5A81B492A33C674BE15221A990B800D9CD5DA9048FDB938633A3BA965398D8FF1AB77F301ADF74FB7AF818E4ECF587416D1CF1BD0F50A65D5EE7EE34E1B6388A3FFF8063B12551BE96AD882EA8D4DEBD9E7DEB05990221114784E7D1092FC01F7BEE9EABD72D3F49E572BF79C771F3E912935C2C71F61BF53EEED86D4FE1D85D702E0CD0D322A92C39935C9ECDC838242C3C97B708A40CC8311F72127FA66F6B63F640C1499F1C70AF48179629E404ABDD56518268BDF1B55F3A6A61E4836B881CFE7B64A9663402FF2DDA2997BE6A557580477ADDC419D5932324306F4BBD3E014CDD8D8FC9102D1431BD895B0809F8BF9214932E915FA0CD1A67A00DFBAC207189D9DCC0A5E1842B92233B8336F19868F29EBD31064EA8227E157942ECBB4C05D40926B4497F277394A7625DE21518C1CF3880F6E23A0A18918BC441A8E7A2E63DE4A37EC35E559FC5FB0CC0E016CC7FE06752866DFB1117B07B635663F39974FD138700545F6B64B2AE401EF894DE97FBCCD34ACBD5CA3AB9A63864E2B0B5B12306065268BF0427478CA944BCF25B2AD50BA6D6481AD0D40EADF2977F12D028421AFF4556B7C450BD8BEEBC697005FC656051E8EBEB7F288361DA5F91AED8F578DF23BB964C68107E0FD6B4C022779F84D78B31F2D152B07D1DA564D425484A0A5F223C4EDE705CAA2652179FBC9A65BA065039E2D531B80645FF9F54FB131F697FA80277B743F33588636A771CD9DDBD0511FAB5F1642A02E043AAC57618887534FBE5EFD1441028BA58D68A390A3DF8EBCBAE896170BAF3E352DB8C2857DD5EFA25E2695C157234115D136631CA96CACF71D6DAD9138B86366FF62C30064EF467ED753D8560E47EBAB157E5EFE8115907092BFC06DA6F33FF14AD29573D61EFB73651AB2B515E67E9215DDF86BC52D2DBF2A4206AEFC55411784D8A44291AC7EE56E9D124E1E69B0C5DC4E418D88D3AEEC568DC2CAB4D812B124C7CD91FA8613AB0A5CFCD6F668075DC4069AAA37DC3C7EA67C184E02B5BB33D604C983CCB9ECEE5D4B6AF74E6F44932937425B18438F3D5F358BDCA002F8E0596EF63BB934A91B0DBB69D9B3830A5CF6E1DFEC05629AEBF50F31D2EBBD9ED0894617878F1B9ED88F0F718D765CEF17A06DC288484062533681506E440A3C0E84C90119859C0978D612F0C062BE8FC5FEF3A4759C9E6193C66B56FCCFFBB6D44C713B748BD4C4A4FABB9DA38468CB4300437E5258C383EF438323F23CFC1D6C77304EAB8629A8910CDBB91C3B5C6EB81DABD2240B62E0D3C60C25554150F33387461C514A258DD2FBC1EE8E39DA5BAA6AB3E26AAD009EB78906B488E41ED03EFEDE7D7F8E67605D3C3131F4FE41C79F9C146B6BF51C56734BBE8961421DED7C16A44730093AE312563B6D98305DF2EA0527E797DCB46330690ADACA60C4A240CC42F770375EC7A49800FC573D94E168B053DE9B5B485A530BE485EE5291301D8A70F1FAAE35B49274BF0739E0E5DE495FFD791B6A3C5DB7D81BD7EBA6DD2D9E326DF27F2DC957943B5BCCCF7A616B41B2DCF2269B9AAC96CC06337FECCAD0A870F0DF3F1F1E99E45869ABD22282EE80603DACADC28288B4D3BCD5FDB39C176EE3E92592310B3A7D42B58AA477D832E113D696BDC4E2A5946410803F24203EE93C13BF380F4C84E2C62722F75851E54B0718FF23DFFC937BD3D1D2D787673E60BD218C102B572C874EE3F5971EF7F24EA5EF2A093B6813718E526806F270F7712117AD6BA1A91D1A3CA817F66B0F354BE66DA05A2EF3B9D05685C107C74E09EA8BBFDD182A1C7A6AB9191224E4BA13AF29076652B79419E11060A0BCC68EF8F97598888C12BA214AB25FFE68298A959B0CC755F00D6FF2688E20451728C51AC2FC96F53115591845AC9E330AED88A7387B5F73A136E598041F7E81BA18321A0E620F088A8A882C691E9D8F99E4C00AC849B3057069F9A5A0024E3015D613B773AEA1E1581AA57FFC246E5EAC3DA2A84A4E48B60BCFA9EC42686ED217469CDEC1912ECD07A5BAB69FE67BE98515D200022B408ACB03E2E927E3A77E4DFF29AAAE0D1DE55779FBE73FFD37FDCE0A3FEACB64DF225FA31324C3E276BCD4753A2594032FCD27256ED4F34DD2BA992C3AAEFCC89F89D9B46635321368F2DB71A3F9612BEFDB641A6B33DC3D8AA317476BC805959261426F7331DEAA84B8C6BD2142B3077BA40A9284B6DBE7D6C92DE0A99D0C1BA619946BFE2537BC7AA29BA4347AD4FF2F5EBB554E740E49744E3200B7562CAEBB9FF565990B6C79E917884F162973DA858811C0A8D2799F65AA7B3CC8AFEAB97204EAEB83EBFBC6A688E48E7FCCDFF21987AD436DF23C16E27F9715F7660884E553421292862B5CDB5A246B13E75F5677DB14EB5802441A3F01F"; + keygen_kats[1].expected_SK = "4E130489218BC6CD1A9DF06B2586365F4362D8A007563DD1BF7D77F29663CB45F5A174EAF47F9C8BB723ECAE888081EF19773FD058691588480FE23247C9886F403733B8A4D5923E737E3EC5A5BC019D015672BF421BDB6A830CE2F9D229B6D2275C41BB2F14A0B5632D21945070EE1653E97CC251C8CDFCF4068211CB6A24D68A1290123730C4B87141040164442E24B4251B05251A248C94166EE33450844251234085591286DC08915CB870C2326A2497109186095CB2101BB2485C445261344C591012D9286023950DC0266220C70100108413A869C2322942C62520202182948908153153166CCBA0000944501AA90412318851427254B66002222A209130182344931629C80689E1B82101426D52242C1C13855322229B22916290909244308A2861E0A4518B222813111218098100076A1921419302908824621832280C898CD434000A800C22238CC8981181046D13899048024E0386204342699C44650CC2895A882559A06812316C1127680A394648B651DC384882102DC2364A02A12C5BC02C24A50118912160A64D20219100164620400150321011A2808A360E94124C1A1525C2C88C43248CD0266109076498B401C1484E04A010620201DCB0818C066624170222151251327291800024272E2009450AB9101400668410260CA25000828198348854060E9B36321C87040093444A300DDB84899A484A1B474513805053B840A38431412429CBC248CB3646A1340E18A269C9926D48128E04183049C8448C92800A46450CA05102184D19150108B8315A060813446A5B48655494411001689A448800305012070152442CD83080C0A22581226A194500489250CB82851394484A1051C3046D89124D02922C2313400AB14CA3B4241B228AA012204C0401A144898C4271641226C8028A884600E10445C808699A00804A3001DB102618B40D0C3204DC8665D898499B140964844161862D10808510016C22000DE0A830C418044CC049923485C03671A3022103A16DE0207112A7640815208AA4044C164EA12066D98001233730C3182220460410346890B42454424444B89042C888DCC29090106D13464C98C66443048582362D620009D0962812C02C88B00C5BA805A2C8619A84694008321B87644228011BA74D081761D4228E82006A5A420E5CB86101B6055B32668800318010901BA631C0401101443010450111A728843426DC90648C306481300A1289681CB92122472E21482A242705E312401B994114808C4B40104C1681584488A24672D3021121444552425108172C4A902188120221A02841822D58224420C500E00030129844E04231D31226CA960D0B4909CC480181262613248D98182C18448CD39200A3C46888102223136423238081A22C582009DC90445A148EC93291E1463122C981A02462181384DBC285E100905A10655B262982B09180C600E0986059306D18190614276D0C24851110200429894B2288C01080A2160A48B08C62304EC0446D4114211C3392A102891C23260B1209D8340422C224D4368D041451539021E1C2608A841114132920B90D984292C4361203909093C84493009221156523257092106E14C3701AA470E146209096280B342D18078D1A373110831083102DA20470822010430860501610D1447288906DDA94245226281025000C334143A04993386624A75182082844C2300BC47121356D0A300EC24240D4024A80302591B860A3042291A08113940C883800D4B670801268620648D848064806602423509A346222433183A6210C04484130844994805838049324286300020CA485C9C05162B28499166D98108183B681C0340961B28541348044064AD8320941022D0A352C983664C288695208850AA01000A22D1C137001A50081928509838891347111222D43862CDB24728CC4645A288A1C826854B04191024003486824346D24336C5C266A8104280BA4501347911122280C4301192124503840CA20315A488A04B8509BC26421450DA1340C634072DA288224C28404006620B729E2A6258094250C4265521040C32882DA1286022586884690D9288C02403123A861C930711828688C0866C90206582088A4A445201560521832C092600A09519404042302219B0620D1C02801122D2089600AB604642051CCA42C51164C21110563C23188C20544444563144A6130888B3860A118904C3852EBFE4A5235C8D8FDACBF1F0546D7E244B119225B648A9D6F84949F1097FF2A302FFD636B8ADCA5B833657227F6432C2409C7BB078696CBF666B7BFA550E7DD1EDF40119D51EBEFA2862A773F05427480464D6279581BC7E8829DEF05EDAFEDBA3894960E2F9C2700C52EC53BA72C8467097E08805A4C23106F3559C1CCE2AA70C23DF45DEAAFA26500E17E93C2A9FA71062E3DD628EC4065F78E192CEE47AF2C01FDC3A495EF01FAAB25C9AEFE9431154CEDBCABA4D2E9793291F52F8AB834129044E3C69DA4F726CB6909DF7FFFD4B7B48C1DE143CCB63E84276CC00595C1DFDA1FF6B134DA457C2B66E893EB6561DE33F96F8426E0E2791A278286A6C5B5155AC2E3B90821828C3546E451945863C0E9E2853F7B44C296C454F991D091B65221C1324809A8F683DA113DE0FF641C9141D68B888E816602F165B46777F1157C4D6C4656A5E99BD0EE46F89047B0C4A509AB2C3BED7A175E45815C16F9065F49C7261959FA0F9CF4B6A5A5742AD6C4D768F7B7AF02E453DABE24AE382DD50458A1D20E4D9F30E98404061F927F26A5B6A677B2957FE4C973B42F2A1A9F61A7C4DBFC4FA590130EBE23E0921760EF05F25D6C7A61E2B0D636FB21537298EEB279D38FD4B85744CEE35D168590C53AC9AF082A1B0C7A46EBE5828C6B98BD89F562C1145DC5A54B4ED8F7997D0E48CF90D56B9569D3A4C4847769BA3D1ED526724ADFAB7229E5CECAB2D08E7FA9B096669D063CA3FD42D2153FEA0E703E23178233435AB81E7588C9BAE343FBFDBE77AEF158DBDCE8E1A4C3A69CDC67F3EA1D4C923118310930CD2B83BF534EBA764635D12E5FC86EBF2560D12DB4B24E4434C9135E4CB7631E0B8AD570C54584BA92B27B54A502FDF57896EEF6054D55E2B15769B53784C8D024EF9B10CF583D99CB4155BB4E3E9B2C28D382952C062F6319D26D7DCB0E946767D13B11CB870265BF829A93DE55E17AE7AC5D706CD0484E62DDE8DC2B16CFE5063EB8327460C516921C312F2C47BE9E71AF239EDC87FB8EB3F2D712609B615FA634CF9991DD10C1897654D5534A537A193741AEE36EA98D768349BE367F63E21EEC6D6A5086C7490E6F6AB0D7776CBA761A28FB5C3FB1DCBB4A5A90F6A8147C80D5254C8870725FEC69C93285A5A974917A7F3E6C7EA58416B814FDFED39AE3AB71A62B0CBB0427EA697DF596784EFD9D650990DFBFD2B5AED08AE76A243497ABAEC5591150616BBA7D7DDAE4D522067062D98FCDDEB0360C2099F13CFC66D001B18C4D1A8CAF7AB4C8F12D9E931F641AECD1F894BBBD3A62E7EC18CDC02C2580625B5334E32E565D4FD9CB7EDC25E9ED12D0DEFFE81E94F62AD696BD3F2BD17585E9E3D87AF16C9EECF24CF61F53669918666F8585A4E2BC34F6205F5DE856BFC767C4D0E2B67622416CCF8CB89A619B65D9B0D002D457C5388314DA854C4CA94EC466B97C8A55DC08C73F7FF0DA6D898B7A77062F9150E322FBE3339C62AA192DEAB57816A27EEA7C9BCA609E79AB10C88B0137811BCE51E17298487C287074A0D1FDB59813BB535AC57FA6DE8178C6CEBA4E6130063DCA5D7E256D173C11E31BC072BA6A70582B3146113DF433F93D74A2A72CF55482A1030DFA0C2C6A0AFDF5E9837D22F7CE89C9A4D81FAF4EEAC6262701B011CAABAD823B5CED6918627F66B1A07C3E5944D53E161AF56478F7598530BFAC4317BB363D4B2B04BC3D0CD938527437C2F88DAE1D447033A315EA49B2ECF62EC6BF95711A57B7B6C0AB04FD6706FC3553A7B726F30C06347F4CF35D989F57AD779DB038280BE50125B9A8AC1A2C84F9B8C7A650A3EA1533F575CA029709E943DD9E1F2ACE7757143A8CB9FBA11025D49CA9CECE240D1B63140C30CE7D0EB2311E5BD9CD7EAA3FE81E93607D14D5D329FD28FDB0E62FB87D448C3C1F85B42FAEE0DC60993EBCFA8D848903E55E2E987D34467400B8F50741EB573BB9FD41A0A5BA61EC07EBDB2675912DE28FECB52A40494245EA078A754C1B9641F4F2B6D7512944A83E8D1A70B7F3E62A13E9C456152F163BA359752A91A8F833373D6CA24EE0901657636FB2DA1E9E0C16A789ED447036002098B7D9D66EF633047792E9CB8C8CD45DA05EB5ED49377F060CB67CC33AD0D609741D0B3DF408F584D83910FDBCED95724714F4334E8C6AAFF680D5AD60C5A1402A97641DC8FA7B1531DEAFD369EFEA623F475694B04E8E5F52FAC99D8BA2D928E60C4D8AF2A68683FE7EE6D82021E35B895D57BF7F4BED6E2DE8B0D1DD0D0662068D4A9674AA65121489ABF8DEF5F2A9F1E2D36A8AAFF54C56E2E6217C7C9DB4B750207C5AA367A25401C7A3C7ADA45E1BF4E3D777D1306755FC0D69830F3BF262B83E727E5415992D6BDECD7EBC6DCE31FCB1EE0B54DDFAF20B522608870C9A0B1C9DA746DAA1E13A451FDD6192EE7E4514B8B99BAE4FA2107CEE404A7BA585FA7E1F1529E66DFC6435A1C26D3CF0CA13836F0B44E8947833F8DCD0DC2FA60C9E6303BB78E1C6E72A3615F9B3719E9F6A0D2F043DBC9AD7BFA803DA6FF03BA5B366B50EA314E42AEFAB8D2861462982115C2C7D6248EC74F7289A3151EEBD3DA0F43B89E9B5C50FBD0955DD803A3109EE451F96F5DBF1F9B42CA04724779F0FBE9D1C672F6BC478E919A07A486732817EC3741F231E9ED25715FB86EA804DC1B23BBF148E20DA21E6301EDAFF8813F5A97BD9F196E40BCCC824281F7C7F0F4A5D396BD2D3AC94A99B0BF24BD7888276A52543B0435091B4E94328164576AE7A572D2C4693DEED54F583D85C783BCD540A1240C40B68AD8DEEAA7255387029653228EC60AF145C2ECDD26A1D0B267695ACDDD490495CCC87BC1013C065357569790FC44001EFCAC9DD18BDF6EF505BF5C4FC555DCFB2A098108A1C06A3400C10248480C8B3836B26CE19BA22EE4C087C687559B6B6EFCBDA275926CF10F151DA7B2A0EC4DC214EAAAB6F93043437B32E0CE139EA665E2CBAFEBE56D6F1B98BC82FB299C381076BD1E1B0564F39FF03795794374269B3321C8E2E9BC6EE8D03084C3BF949E26B759E5A71CCBCE856FD0CE5FE7F0531178B2C80E2F913D777CDF265CA351FD1EEAF2650A2C8A52ADEFE7EFDA688556AC442D9D4EF43AFB177987831AD7ECA98C3042581F2389EBB972BB11C8D6845C8159FFFF7B2B7AD2E77F6FD4FE21E00A528F1C243D84B4793ECD4BE3F94E59B2B0435518B9BE6BD0633E310F254B822A66EAA384D7AC066C4F273254F3A2C00CFCC43C3A52FEFFB2B51CE1564A0CE3682727BBE58D9455533269FCE603C7F6872A6C07BB290C0B8AA95134D55B8D551AD77F071985EDE813578564EADA5632B9AE931EEB24D6966DC6863DD2DEAB2E3D0F4CB3AE862AFEF5B6D4C9288B1B3079C395924C67B03C415E7A8070A6839996C5BAC53E427A61A7EA100CC10F3ABF7D311845DCA174FFD06C3F05B88CD2FF32E9E44659D7E80F40EC56172C68BC5293820886BC47E8339CBBAD03383D099888E668AD95A905373D30CDDF91756C9C7C89F6DCD6E0BC9E9C4ED9A876F1568B49B6CCE9C520110BB205E307ABF68A8FEA783D1FF4BDE01F57A6B1224E9C83FBEA507BF14F77BC27BA0806D48F8A0FA1CC1DC0EEED7FEE5FCBEA5FB609D76413329F54685CEE7E4FDD309114F71F864A26F05A672315150823110947291991437C60902AE0767BBD42C57D6C97F5CCEC62207C8123E750945BA0BB444C894A98DB610ACC5703121CF8A93C7CA9CCDA90EA0938304651EB84D2534F2E67960064F81A41ACFE3560066DEDC1D7F954C01CEC3A8083975829149FFD8A54E3EAB95A076361EB7561EFAA8E678987F381F662B59A49579D9A2453AE756C133EB4460E72218696DF703DCE965AC32CD144C83819076D6D82D8B5451E0FBC384EA3A2C5675F2042F48D1D1A914B384DD0727CCFDF0A07218B3BA7BD10A55A550679C12244059D2DE9F76A4B1855733725EDB2981CF956D22223833FD43B9669BA21B38FE2C6BF49484BB4FE9E5CCD5F883E856DF05525D9E3BC452B73E6CB6DB583E3641D215019D0C48EAAC8C03D646CE537800AE96457CF187D3CD456D13AE4B657FACC6D9F78581F209E94CBD19B6768FBE0F558AB7E2D4938A0D2D92C6C8BCA7A01D7500286756E87C9A55F10BF60E23F7D6039E17CC6340445E297FBB213730455D0A7B33B852E4829D31BFE5DC6AF3CB5916176E4D125863A49592A306B9ED9CDBA4E2F40A4C8F3C85943C10BA10B688DDF847FA2212E374C64148BF6D1D856768696C6C8F04D213065A453530CA6964377687CCB2AF180ECA47260A493C8427CD418E91D38C50FA9ABF904E419A612881CD595821657C95729FDF8D1D965E80D8F8F82C6009A8BFEBA81ACF69503B873F92E557DCA50F87187BFDAE231D0164CA86E58025F51B0BCC8051D9A88313A619B87BAAF7B16EC52808CA8CF9856CB09A58B71FD67FDB4B3A0B88536DC3EE689101CC39F7F0418E3CEA104C62E83DA5631998DE88562499C4D18A98A1DEAB254C74334C325C11EDA989F98548674C19CA942AA95CEBBAC2A593BE1A1595B702B701DD42E89C8E65DFF6E104053815FE2D7D0908CC2698D2B6C26FE981025691A1680727A0D65C37B0D87EAE23CDA4E6EE98F7A981B9CF44B6B2752AD2337E02CEE156BF8968174FBF7EB0574BB62434D69EDE82D49BE6DADB3510026559B7"; + + keygen_kats[2].SEED = "9B54B9C91E0201251489E07D1442A42D0BF32189D0C0CA8A2D4871DB25F531FF"; + keygen_kats[2].expected_PK = "9C17C88109B6927D423D887BC2FC24A5C4405C8E736C1C9D9A799C5CC09DAC3BE947BB391590EBCFB93BC00F569874F69780502C80C4EDC87DC9378294EC3D62F584E70AA18C0F1139DAE97590D0C89CF57803A26FD82F264F2CF2A184B2DA47F44E22306B95879CB3A036C918B6166E1408E59D35E2177F6CBD05EBE6F1230FED71A3CA9CA73F3333070A1DF3FFCBBFF32F82EE2ED47285D8F05809240ED1F91873D3D817AF74CAA85BF78EF02EE9B36FF3BEADFEFC436001A219770927C1756A8FCD265721CC8CCD367C7B19A40DBA1C9DEE9611863BED506F42203AEA72EF21026307AF0602437BD5A8E7B1B1F1DED44C4A009E785BD170BC98C839753F076BF7ACFCF3DB89FACDDBE5F5CDDFF76931C0966CD935102FA75A967C67222D5F8DDF2412F0CEDFA4C9FD94C6C58F26BA4954D872229BEA543107613C71994652F9268EBF81862CE4DA0D172233D358823229618803AE54608871866DCE80B988BC82F702A8C16C9A6E58B465C39197432152297524CCB00338067CC08DA6E2AAC288AA9B3AC40493A454ACC7786D6A2F261E86F4FC6A341896C2E1B7EB46AD1E4F35D970B5B4FF1AE8F514F6C78BF27A40EC941DEC16C95D9D91F869B578BF37E5164EE77DB6D38F7E65D9E703C6323750C24C6B41BCA787AD02208421D3DB8D7090FD3D154D9561B9638BC20BD55EABDFBD0F772D590EADA34FADD191F4FCD80C4B0A9EBE8A069270B89FDC2F0C54C5E9D835951E76E4255B9AD8DEA2092E806D7C62BCD7800E175C93420D7D8E3806F2B6F325171A80C34F0EC7AE7C48CF4664BF07675B8C617FB7944795070E7B47EA9BE7509BEC0514439E9DE57E4C6A2A64303176D1BC37632DE696CA7A3785943E299A1B152AC93D1FC8EBD3A451FE780098A13A72F4EFB4A41131549038C38815687150DA19FB3DD1CB611B9196135606169090D426B33C0B267CCB630172BBBAA67ED2817227DBE6FCDE76CFEA14A17A36B034977559C9E8AA525052CBCDCB66E3410DF8D321F3992B02C3CA8FEF477F2E22ACD2B31A89D194CCFCB4C41F8FAB34128EDFF327C80022CB9E15FD41ADEEE69F227CFFD706312AEE2C824FD281D62C31C98B2306D08A39DEE41BFD1CC702E55EA718A0C265E116BE6B87678927373592B6438B7FD490B2810132579BDDCA4FBBCC0764DD245F6D4DDB97943F52A0FCD190C71744C2E6352F4D0D2121ABAB3870994E21D617A96D77C195436B291ECD15E9CD29C6E05617526FCD8F853C8CEF29CEC0549073D4AFF72CB975D3B6F4EC0BB0CEBA04E35E69E702D5E1C671424EDD6A6835E0E9FC9FCD7FF16B90B039BC1B1295F88F724AFC6DF5F70C22A6E7CD16315F5B7DBABEE28B7651EB16293E2F4998A4F4640EA6EFB4C0E8F51B7DF809CD8F53A4C18F4F4EEBDB18F3CE2DD37F12E0931A46B296158A82D6F4980ED9FC9316BFD7C519688C0C4BD22DDE4EED750EA96898481D7790B95907F3D7E9323EC42B59342A52616E288717B8DE4D5550DE95560EF33FAEB2E2A4D9641FD0630F487DB670B9490D8F91F4E2E9DDB7B6B2ED9DABAE448622DC60A5F869C96E12F1B26A77B42FD6F513E9F8C0D53BCB5610EFBAE271B754C735787E9FFC5FE8778E967D713C2C3CFBBAF59B2262F1C4B8C0499EA77CD587A5296A819955781AC371C20E66471CAE28C6B098A6D25216F5CC3F52A258EFD3E22B010DFB5971B5EB004ADEB9D34375B157EBDFD3331B6A9D56D8DADA55AC152C3AE497A36269F44F3180C47EB8C315BC3F3A0C8AA1CC062C487BD917FC3988AA468C63856277620F576CD6B70BA66D3F9377CF20452DD3E7A8890FFCF309D7E5FDE1B2ADB2BB6E96ED3E8F2CD1F075D82599B92F74602A87FE5506E25E2307FA48D0C171E61BE15E10C3EE42398D078EB42049D44B0A343915F3A99547E2E27DA86B6D0B88F9529613412FF6D6AD459F30C1BBAD521E99869F1F01EE7540407D645A7B6ABF590DBF180A85076CF838D89F0BD53CA96759CCD3F11726257FF862A565217B82068BEA4BE94215F0DB4775558FC6D97B7D4F3254A4D733E6604A003C804BD380D6046469E310AB9B07CFBB605A32DF6E1B15734F8C2580D792AE5AD45C13C37D90D893218FB7BC6A449161C0B91B2FE8197C81929EC8823942A2EA8F7C04A307249CD3295B6B529CC87041B6866E9F358B5EF30486D7CE9BB297FE73B2A0BF7FE5D4F7C56281DFF8CA46B5F1DA6A14A15EBE6F6D7DFC4327834E655CE52C310B6DD6D72A9D948A930A11FAA6E57A08A6FB873341A3F1211D0396884C07F785BF4531839AA77EEE2D5BD8D1B767602C01F6CA35FDB0F6A3967C367F88762FFF45A67A4E75C16F744B6E6FBECEDB03B346EBB18B1A35D0F2CF387277CE01F8068DC250E19F0E37FE36783C0D4FF4A1292577DE8F3E81CD769B2D22EAE286E75756ECF31E56B00A57DB2C17750909ED9959946C86E25112ACFAC5F526A331B5E49DECEDAF38EEFD5D5368A8539E49A0766C22CF5F713E6EE058E9BE157805A521FECC934987809B9C5190EBD0E709D1B2EBDB06F925F3203131171ABFE76684849C0A82EC8D66ACD60A24794BD39C18782506BC7F9F7DC6B1BC7EB2D70A3FD7AEF3DB81568C5F6513161D8DCF0B9383DD97207C186572449F7B55806FB564723729394C85291E01C5EC803D8FD2D702BD9F84BAC47E6E659A3FD90D04B4F53A01DEF302898D4EC430BEB2936C70B976355DC2A68D798EDE02F534872E369582E8B4DF771AA3FB15C2602F2487A21EE9DCA0C2ABA12ECBAB2C8B49939180C3E305336EACFDC339F502EC730B55E0FE4227415EDD151811D018FB34839DCDB684C9C8453F681916316DADB8BBB025A6B66DB0C6315C73D0654113CE37FAE29DA59A893C4C7F001DE15F0AE4B59C211EE59808021DC7CCFC2BC8B2C15214B783FC55E8C50A19ABEEC8093D82C3E12058B7023AE561384D9B28307EC60D004BE81512B0D03F02388FCC2878832C1F881251BBD73D3245336E12653445B6CD704A796A284A7A7F1F7F37DD9D22C2B2BE0D3C497E2F25CB95933D154199A32D4971965BE442C914ED7C42F28D33BBB61684AC719EA5F4D7FF7202E3D476519B3CA236A143B1DD22B34F479C0519531BBFF5E1E1D8330B231D588AEFB2BABEE0A1BED4A1D775C5BD5177A8CFDAF83E5B4CE662418D4A13FE34D3875E9EA15BAA45033CFD746673AB16FDE39F31BEF02051CFF7DC335C6B9DD8CBD17CA9B652F01AF2E3044FC3B1F15378A967F023DAB2AFC2CFA577B82DA875E1FAB014728BD7A8948859EE9619EE02DFC85859D28DAD6B8B2AA72F7973D6709D1DCB0C625084771F3EAA12D4B6D091E6E5026845F0C30FEED6BBACD4A9B5D623CA247CD6622D1E18590E5EF3FE9A094263E886E567BD1AFE24D7E263C5B2CDCF03D1FFE2DE85D7C81A7634066B30E0FF49B71234DB9441017954CB05B8BB72C11710A55041C737AD29A58B9EC6E2CD871B56976C389133F45EA4A6C39545AD15BAFD9863A333637F7AAD613BB82E61652A00BF90DB3FA1B4205198A42151DE6A3500F0A770AF589AB63C01299A28F94B9395D652866BDE7505BAD85DBB2B9D56E43D02F679F94B4F0DCDCAEC1487E18B89F96BA1F1890BCEA47E60FB0165092BA684F8381625F83C86FA90F006"; + keygen_kats[2].expected_SK = "9C17C88109B6927D423D887BC2FC24A5C4405C8E736C1C9D9A799C5CC09DAC3B0AC8866103C621D3464AF8A7E67C30C8FA7F66580CDABDB9E6848E611578D0E85F99D936F0B17CDDAD87C4107D0642F26EABDDE9732CE11AE78FACD7532C2868A1A29A6B5A0CDD35F4EA2F536DEB14A7146F4E94F723B69B976F4688FE8B5D22A0B281D1426D18144D1A066403A98808390E010241D32428233764A3C220190322C8C0405A9265C8B82813B789C9089211082AE4B464D018300031644A928812A52DC2280108C58559A86111270912080D4B384621B144994268C0062999228D01A511A2C46882928C24B70D81168ECA0465D920289442329CA00924356059348EC4C46D23C52123A425CA10921441240B424E02C94C6094318C082908260440046249304A21154002180DD282294CB051211406DB2480DA08012125661B96641819125B9649C9406C180004090380CA1210D0444EC2A271D822694B2091DB8251E0A00D0C9788D044091BB020C3C04024C7251849450AC84001164D1BA96960A691C2B2288284818BB44404B90C9C4206D8063198926098846589240800098209B349A0286CA3C428C1145198222919266109A208081152E082895CC06423A641C408721126321431122231700B15868A16426480311B156E023702DB4491A130804114200A119098142519A1519814264B422C0A878DD9386402B33080B25104B785D2120D11C44864A88DE2868D1C2090CA940D0C15500A188011870513988D94A265CB164D1486418B168C88002D14C680A39069989431514866C44286A304302449048C962C0312806124456312806182098B300699A65002942D08C44124C96C000546C2B6098C0025531872CC108C13A0458482080A972554C2886342859C3049CC18929AA82013220AC0282694367049A60850C850A0B22C60B220A4388D1A128008346190366C0094700A0912C8302C41B66859B669D4C2814226699A2404542442A3245203115123234801B2001AB24843B0615806890AB66811B5641230841AB88DDB280A2437645A262164340508075200B7689B988DCA164810B9440B8490E0A41011880494184013B500440060181469540050030864C40062512030C42200C9828900496CDC96404126051B87245036495006029116449A105213A62C528224214690D4364D24014044B628D8264AD0A26C82288AD4C66920A36C49A40440068E63B405141168E0264008884419158C19C62994966110868041C43108458949B030A102851990041A166A8AB631C33085DA1672E2028E119711E128810C8388D21200CA164419C52544468D1134615C946DC0485154808C9C045153040E09380D110248D814880B88719CC60C64142812854801938DD894890284258312698BA828C2A690D4264504B57120468D21462E410241A3C0082030028B442C02264849024D530065CA24465904460A290E11A460D0A020D1140D130185D4B829494684989081DB2290D9B011C4460209182C63484E4314001CA24450B20CE0C48C09C98C8AA28011B06058C20914B9208C384CA0A49124271223112C63807102B31048866DE0882D03488C61A4895C241143282541409118286D54261191B82CD82069A4A229E4304153A20D08C1400182694A440948222D6304066434212490648006418AA40DD094690043819216649408486094715CA24D61248018B8814194200AC650E1468A4CA65192822844140D4B2006CCC84D1C3460D04069208641C4C66DDA904880A2111BB44CC4926DA1B0080C11724C204C93406111494258948920388C89982504A68813412699B6458C148060288A032402A442658AA82C1AC5412288705C882114A78C0A447241402C88180012B48C4BA8640A934CE184400A984DE13070E08404230900CA326249846400378492B08141A629C20621DB162409B74DD9A28D1A8208A3388483B60C8A824D20B48C4BC82C8100640BC4850A054E84B04CC1204C503851131305CBA210040002CCB660DAA8084AA091121121612401D016920CC950849804DC803081A465C986301803321BA1681AC904D9062C042149CB480EA11088D00802E01086D9346C22850C9B420A122948DB0089CB3088D9940891343294C8051B940420226010849114A58CD9341101355020C361A31682630231CC3881DBA809149349038948134210A304094A2688956D861BEC7549AE8CB7B5AACD88780F7B1D1597FA1BE27973CE28C4C0E9F35194AD0E2DF62E622B75E06E7E21AF5FDF3E4908FBA7D0B657FCE0A512FBF13D3C83F16CD3BE385BA075CEE26E68A28502C3C097539430E8F19916B44E53AA7742910B719CF4969D5EE2D246F5CA207AEFEB037E7CCD592094DDB72621C5937813A5B324ED4544200460F4EA7744DECC6D182A604C142D6212EB6F9F90B1AEA0F89EC07D9C083EBE1FD78D3C4C2282E1D5BA47064E8DFE71ED9A7FD7C0F95481F3CF0610CEA3FAD5C4E73789C70AF963A1DFA6DA9DF610BB98630EB4419399AFD1412E0693E33BD24381050FF62883D65150AB1DD0C67F443E5FD247412DB729D2E58453C770F934C475B89B458111DC6268F1CA0E9D143E7F0570D22AB5B7BD9446BFC7DEA9F06383FE1A0BD9E644CAF2B91AC44BFD37DEDAB4237990A3AD448715940001EA30E7219172B64D86E85C1FCA8DFA922B61819BB4BB68FFD44970FFD9CBD6BD2F09FB12E5265A5B0F919F6D4D6D06534FFE792CDF6882DA5D4557B51AAAF3A80A8CEA69E8678E66D1F47592BFF128EAAEBF38C70E8FF7AD31035DA28AF239FE245D2FDD4F853029A65399D5E6B6F4F4CA2D862B62AAEC8EFCC4B05DDCB351DFAAF1F7E7ADD9AF9FF44D2E2A384368200217F48DA0DF5013BECD2462D4BED2359FE44D9612EC6505A76071E116AB5F0F1DE88288DBE97A8B0EA32B9A6FC53695972A8F6B33542457C30C553DE91B118B15A6DB2D3F56FB0CCA91DF79741AF737E88A88A69424F7192EAFB981DF8256989189D75E0C7183E3ADA99CED3913ED35DF5AB82C8FD07D7B67DAB7EF443DF51D82FE87F8CAE103713F88E9B73F649B1D3C8589B71F06517B18502CB230EC27150C072D985A98790DBE1F83BD59421D19CC9E23D845C50CEA8515690944950809CF95FA636AB3509AFA1A7ACD2F6C346CD76362D15907764749F3E16C8BC84186E1FC9FA120F49859F7E4E6C75F7CE19C9C129C72A7CA129D10AD8EB9650DDB304F5F02FD7257DD8D71B97BD9ED47B9111236E3B706AE4800401B77E1E5A541E44DC1D686234884A5F910AAF16C8D23E593A307DA8F1180095D7A707566E9CBB125751499D748A7E1A78108B93DCFC165D2906A1DD9AAE8C5BCFCFD1D5879A8E30B6FC3EE38F470428E8455162261E7FB6F8D5BE329C0FD494492C296DC8A78128478F88BD6E1B2CBBD731ADB947300A82DE410B27C87180032AFBADEFF276BFDC0072179E36053A3F4C031FC2F94116938EF7B2A02CDED2C4C101AC0CBF0F0404BF9246F1E4B71EE2EA0569BA6478C4929DE40C56B075432203D8CD2C0EFAE663001CCB0947CA073C0301A3896793F7FDD0248F7CB4CDB184408FFA24AC8016716A7C40572731CC95DF6954A94BD2E507FCF71A8E250124E29313ACD6AED2EBBCB36ED59F102F706D5E1B79DC3D956F46997B4172C7FE20F550CFA0F1508312CAD73AAE7AC30BADFDE7D2A8B2ACEEA2FC564354276AB61A8F2D6A3CE5D43A5E6496894B66E72DA30370692421D267F04430397C3B9293F7EB11C107C2D2BB007EAB932BF25CA65D050CD061D3653BC1B25B5AFDAD7A9EA9352718CB9584615D8670CC61D7C165D778EB2766930470AC115F488C3767A6B80D987EBEA29839642720275E20602ADD280FFEF51005BE2AFFA3F69BCDC69C7C40FBDB9F8AB2C57E8745A9CA2124FFC3E088B5564C088B71847A2AA574A4251C1F5ED3F02E22A85BFB1AD2B137477439D4BAA4DAB63644A44C0CB121478A2D91E2B7B9D6CD02968EEADCB51BC5450ACAAA81EF9C1A05B475DF46C4D6603C371D6AE3A1E777A789E7205EF7AC574753F60493B81F8E0AD527A6A561F5C1723EB7E9AC1D82658C00F1CC538DD8E5552366FC9A34D0EEE1EEB9C4228C58D2D7132E3599686930BE56B9A59097B2238AC49FF4F6A9F893FBA76F511C6A6126686C0BB6CB946B0D3CF7DAFAC886BEC911564332E773C10ADFFAD490B94EC6545DF90CD12695E79936A7CE77E66C3F2781F6606874BD2E1379A8610B0BEEEF465334A455DC2887D8B35066B496856A5500AE079178EDD320A7AD2F0D350B0B3E78EA658787AD5F4CDD224340E93A06996904F9D5EA21219B871E21DD3BF7BD3BAD750048702059C86584B0E8B4EFB144503609D021C1DBD98F04C84BCE4304C834BB502CBA56A6AAFEAE643F76FBE439033D13F5FC93D8D852710C3CCA4E2507CAE51BB8779C622AE8197CAB5E51C9D11BD38BE4145CE12BFDA8F8B9ADAD8D8033D38143C92ACA69D5F72ADACB8D6BD10D427726D0F51AB7114A174E5187B8F9D114C2F4FB768EA80F74A49CCC642F5DBB7CEF2DAC669E250451CB9AD8EB2A7631E6884934E2A25FD710F3E47726D7709BC89800C6376158917026C299CDF76976624AB877136A19ECEBBBC1C36DE60EBB3CCBD43508EE6CCA750960543C16A0EA3676CAD076DC3464517FBB3B2D929AB2FA80FC0B31BF2026E4FFDBD2C20D2DBB8FA09BD88CB4B3CC124CE260BEDA345EE0232B2034AAE1E1918365878D4A0BA98CD4D7011014FF7569CDE130389A7D59E860AEF59BEB4F4D3259C1B092E68FF8AF679327F4181F6476D54D933B7EA376B1D4C0564D204CBE631C4AD3DB45F3A7CB894AB139BDEEFBAFB6EDDEF0DF6F7FD5EF140882E21CE59AC45417686DF7CA38AC90A7B44DDBE0F085CC397B3B65E6D2524CB2A6D4AE4BC69911CFE84465C9D6B697D28D84C8C28EF60ED5BC34B0EABDAE529CFF3C00F0C706584C48B565CC060A80F6DDB0DAD0799B8907E94B0C29A4E7A8D6CF0C5750DA5EB717B30341352E6046420C7A226A1935BB7F0D25E4067E30B527A55BF410B4335063ABC9BC76A5D885882AF728AD934BC7E55553B9ECA69D97311EB3CFB1DBC28891D3DBD954084E911DCBEEC1056C502385C8EDA9B4ABB93E623132084C5950FCD44725BDB70C9B9187A30DF477E128F143D870A7F02E5D2F20A3F1B034FA05475F58D98A6D8C22FFC0ED3792A1A2DDF00F62CC03CA04060BCA60EBB9CC27C2BB6636BBA116CFD03BB196D85DEEFFE0C2D6359129FE1877F723EA225FEB1E995A34B9A3A75D1E6C0786590E159CDD62B39D084AA5BD2EBC4456E694054922D4FBCBD5335F7F8448ACA08E650D296D45F3511365B5304F1359EEC32E4616C166F938F2F36C790BD577402C4A605149A4B4F8E1A101E97E22AEACFA89273B3C1824B42B0019AFE8C4ED8B7F6A265573E11AF026464BFB2C78532C0AC303EB5D36D88CC33F528E56310300D52481BBB27B7F8C523DC036B2D1A36C002B98BF5F58B4254D097DF7912D4189287A14D7AC1A30691BCB53FB9E86056852075B7278E4A50F76EBABC11761BFC5D2A86B5995B1CAAFCCE5F5B3BA2C195B692743B637E424AD4072C4B5DC6BE4A3DE4E041E72C64FFB9AF9C66353C5BB2A3967830B9CFC9AE5C632A14BB32797BCEC4A595D8761524026F13D237B165CA4240D4972287ABE72AC7F419F37E99047F17D5D9DB57C508AA0730D6D9D2049E19B1EB3C7EFEF2EE719047A777FD281A0960C09BD79443C5891AD8BCB1ED643B9A9F1E66FB5C7EC6DB926CD73DDFF4D39B15E386AD92170C4F678A7BD7FD6EFD600FE082A64AD91E2EDC675DF911B531074660096E85C66005318A3B85CF7E1C5D269C5BAE4096C9E05145C01C9A6294A50B3D4707A93254B0CDAFAB7B0ED1CA6CCB3DDC1FAA5304055C41095C503DD79F86A499F292C473C3B975DBBE53216C85D42E3E5A819E1A947639131CA18CA7831091D64FECA2713B8BA5577BB6B7FFAB6D376856A4D38856651EBF90929784436EE1F09EC9C99A2BE601294AC1C7ADBBC0EB050BC3F728D5D0F3D4831BA4DEE0E4674EBA6C2D26944029B8BBF90891C37A69DE342EC829625544A82C3FD8F61DBC40ECCC6527E06C26868B33BA362FE4E85FD8F76132E9065F6FA1DE7FC0CBB92A3306534AE9FA01256B24ECC2C63854D3F46284D0EFFEE19CE5B7998DD8DCEB38FEFEF074EF35A3748A9E44AB4F75F656FD08866DDC4F58252B25A0232180E8DB2CE8D346A558B03DD71B19D81E5B23BA688099DDAE1D10BF52932FD2EBD360E653BD4C3A254FA4B71F2859757FB024B14356BC00DD2877AF29BB57ACD812C22119F8CB62BA81C946C36B0D4CBE3A1B4810FFB27A47096108AAD74A5A0413D2A1B85286569853AC230BE9E34C78C84FE0F6269685878AA1246A55F37842584EE302301941B9A6CFB8BB4ABFBF3DAE55AD8ABF6CD6CD7B2C881DF7D5DC264A5F61584A990A8D1CCCE1C0CC05881B4358494283964EEFA16E9A47586FB9ECE3B39777DC6C1DE6931C5448C0AE2D6C51924D7F6BFBCBAF485F0F22FA2228A162C13240EB64C050F2EC800E937FA97C77E2854693A4CC83E1773EBA74CAD800F4AC6CE461C9693005BE0B3C288EF1898900466318B96AD247139E5E8D8CCCAEDD20719275E102F50F1CA019692642092CBCB21210EAE0DB708D96E50FF249E6918A628B7834BE30349EDBA515A46B0229E6E7AB1A88C25A7F6A3BDFA84EAAFCB52AA1A143FB09DF7CBF6E39FE1B813AD64FA786155C298D9483C2F9B39CF46F936AF6B95E3BA82356D7C99EDEE47CA00C3DF9A80E8DE0F246C5DE4FEB6C55B457A59CD82AFF7A60E3100D409E3EEBF2E695DD3D047CE2B35D3820AA8D4D7692C299C00B78EE7BA40DE61560CDE3FA77BE3AE68E"; + + // Iterate through KATs and validate + foreach (keygen_kats[i]) begin + parse_hex_to_array(keygen_kats[i].SEED, kat_SEED); + parse_hex_to_array(keygen_kats[i].expected_PK, PK); + parse_hex_to_array(keygen_kats[i].expected_SK, SK); + + `uvm_info("KAT", $sformatf("Running KeyGen KAT %0d", i), UVM_LOW); + + // Write SEED to MLDSA_SEED registers + foreach (reg_model.MLDSA_SEED[j]) begin + reg_model.MLDSA_SEED[j].write(status, kat_SEED[j], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE_FAIL", $sformatf("Failed to write MLDSA_SEED[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_WRITE_PASS", $sformatf("Successfully wrote MLDSA_SEED[%0d]: %h", j, kat_SEED[j]), UVM_LOW); + end + end + + // Trigger KeyGen operation + data = 'h00000001; // KeyGen command + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE_FAIL", "Failed to write MLDSA_CTRL to trigger KeyGen"); + end else begin + `uvm_info("REG_WRITE_PASS", "Successfully wrote MLDSA_CTRL to trigger KeyGen", UVM_LOW); + end + + // Wait for ready flag in MLDSA_STATUS + ready = 0; + while (!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ_FAIL", "Failed to read MLDSA_STATUS"); + end else begin + `uvm_info("REG_READ_PASS", $sformatf("MLDSA_STATUS: %h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Read and validate PK + for (int j = 0; j < reg_model.MLDSA_PUBKEY.m_mem.get_size(); j++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, j, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ_FAIL", $sformatf("Failed to read MLDSA_PUBKEY[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_READ_PASS", $sformatf("Successfully read MLDSA_PUBKEY[%0d]: %h", j, data), UVM_LOW); + end + + if (data !== PK[j]) begin + `uvm_error("VALIDATION_FAIL", $sformatf("PK mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, PK[j], data)); + end else begin + `uvm_info("VALIDATION_PASS", $sformatf("PK match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW); + end + end + + // Read and validate SK + for (int j = 0; j < reg_model.MLDSA_PRIVKEY_OUT.m_mem.get_size(); j++) begin + reg_model.MLDSA_PRIVKEY_OUT.m_mem.read(status, j, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ_FAIL", $sformatf("Failed to read MLDSA_PRIVKEY_OUT[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_READ_PASS", $sformatf("Successfully read MLDSA_PRIVKEY_OUT[%0d]: %h", j, data), UVM_LOW); + end + + if (data !== SK[j]) begin + `uvm_error("VALIDATION_FAIL", $sformatf("SK mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, SK[j], data)); + end else begin + `uvm_info("VALIDATION_PASS", $sformatf("SK match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW); + end + end + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + end + + + `uvm_info("KAT", $sformatf("KeyGen KAT validation completed"), UVM_LOW); + + + endtask + + + + + endclass + + + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_keygen_signing_KATs_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_keygen_signing_KATs_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..2d88a4428b0aaf3306a8fabad1ba7ecda97375b1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_keygen_signing_KATs_sequence.svh @@ -0,0 +1,195 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef struct { + string SEED; // Input SEED + string MSG; // Input MSG + string expected_SIG; // Expected Signature + string expected_PK; // Expected Signature +} keygen_signing_kat_t; + +class ML_DSA_keygen_signing_KATs_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_keygen_signing_KATs_sequence); + + + // KAT arrays + keygen_signing_kat_t keygen_signing_kats[]; + bit [31:0] kat_MSG []; + bit [31:0] kat_SEED []; + bit ready; + bit valid; + int value; + + + function new(string name = ""); + super.new(name); + keygen_signing_kats = new[3]; + kat_SEED = new[8]; + kat_MSG = new[16]; + endfunction + + virtual task body(); + reg_model.reset(); + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + + // signing KATs + keygen_signing_kats[1].MSG = "fc2925c28f99410b1f0185546e7219797299369d27c6ab2d00adc627ba5564816fd47ef3175a769ae51fd160d23e458403e27cd6d16678ca6367a098d62e6610"; + keygen_signing_kats[1].SEED = "1beb2f2b7967afcf76cbfdead98ccf7637b4aef67aeaf2b263a324bb0885ed3e"; + keygen_signing_kats[1].expected_SIG = "85BC06C0229185010B1E23D65F9F974FFA0E86E6DED4CCEA6965313028757A7C4B10CE05BE1A3C317BE542D87EDDB3FEB57B785F28071772E2FFC49D151F5E5506C0B21FC934B6ECDE9026E344F18B21945DF950464725B94F5A8833B6185CAD50814B5CD16A9CBF44297426FBDAB19A9254E78D0944B479E7FE6FBAC48DFACD8A15DE627A60BA177A5A0445F84200B28330DAE2BDC30A67CCEC75A53BB2724BA2F3CC0CAE65FD48FD90E02524D3657441D376EF59346E64C2B26556C782A12E9ABE697BF58A70C3DA3C3C79FFCDC6B290F5D1CC660989CBEBDAD2094E96508EB9DAAB000F136BC370CF64CA556583082C9C953495C1FBCCCF6A209D546CE998425E0E17D81018153FEBFDD73D870D632D1CAEF5415B8B00E1B752432069139F514586E1ED7E55E695AC725B770854FA78AC27D75809D7B85D615D7092B2E609A9C8A9347623E3DE0CDB4AA9E782A4367EC1799B02106707A44C60535ECC6A7C4F59D1406900C3C566174D647F249C4FC2C4358EC5D0824030808F77CBBA8743B4410432BF93B9771BF5C92B522AC368C58734C0ACE50C3295E8F338CB92E9BDA9D4976BA2C60F3975DD074A9E8885A0069E92F839A26BCD38E639A79369F6FEE8E1A9CB0B2BEF03E196EEC6BA0838336AC40BA11917AABCD71CE8F00437343483FF27D9BBF2328449EAC9EB1672E750A79E3CB8C4BFEAEB1B106167FA56A8EC9F506ADF953D1E2221487F190FF6121541C3C6D3867B18DB63FCFDC279F2983030DEA61FCE0DC8F9BD0F8E2888ABA0E84AC27975B637B1B5DE12FD8CA9EA1E64CA16D845CAB2280BB94BFA0BB4F39586CA303565104BBE46A7F6CD3AC14865F5CC06894B2D11D26B7EFB845E9B9E98D3A6C7EABBFB03A66D7F5E7C7B210B8F240ECB1B62CFD4949C5352099FEFD45076B9636B89027F5596884C2F09A0851060146F575F4841701507F6660A4209263B0AEF5F8255E98E34BD7687D5D554CF68C6C267B1B1F10AF6ED940FBC5993B924FE925A3C43E2972BC9D00A4F13716B6822B34E165814C1C98FE7B34ADE716B21B326C2C0BC13CB86B9551D228E1A7BC9AC95BDE1FE822805C9FDF6332AAA10838972F87CAB9D160DF4C1E7EEA533C33646BDC5EB46234837CC5D46D6957E1F8BEDF493DBBA305B96E46D3FF39CE38FC2C013C5D5C4946A8A414F4C68BED207524673DF40C449D087A1DCA3D1A4BF0F2F0FD139528A95E2BD33072D125E31A99A17A1977B8BD58B652AE870D6CF743A52DC343F9D4EEAA10EBE2FE1EC57A8AE33A2050A40697B6D41E881471A8E720E9E39E71DD72335A6AFBE743437061A522B9B129DA4B74033356D0E1A9591EE5EB09E11FDCCD4E422CC6759B8DDF118A82FDDC975C7AAD69238255B1713D6B6901FA5E6411956038D831A077A8D90556C9F6CF48098F9BDB838AC7216DEAC2A84453B12D26B68C20B8EBC8C09EE4FAA40DA772D67FA8B474F9F3873DB8CE4EA74B72800128D94B5DC91AECF35EE24DA495459E2844AACAD6EA69015B7DEB23F06368260329CAC40AB498217BBBDD89115057EE95CC6BE72AED4D7456D897C7DFA55609FC4EAA162873E307FF1E9D202373D8AEB16CCDD45CD6BCD3D97E433B5912B2CBDA5D3DB0B2CC103FE7013128CC798B97141EFE1F888149C9F007FD02EF6F8999FB1C1F404793FEB582E94ACCEF2A642528A66A1DFF389E2360035EF98553A2F09B19911200B05DD8D781D9BE9D8191493678383C52519A5F98BF63A9E834690729BB9EB61834AC611A64771C8373AA27B3804B0A561CDC64D9B986AFB50C99B1F1CA07783F06CB8C2CCC88490F6C5862DB10B9D61752B0B03D2D93B0692D5ADB9B3347607FDEF6D2311117D28FEFED7738FEBEAA589C821CB2420DB361AFC5537131BE739DC9B7DA2099AA3DBDF9F04AD245AEE3E065D21848BE6E1E5F87D81D4322BC570264BD477F91FF0599F4219677CD228F87183C5249AEA2FC7FD1239170810CD839E4B8158B6595A73A96EF8B9E065FF5362ACF2AB0DDA13B0B9AD43D88986C664E76849F98C478E1D52A1FE4541075CD4229CB68A4385618DDC67FF635E477F409811790FEB183806FCF63216F36B79AB140FD39764E15B5C22B7D22C34D6440F4EB10BCD72E4F1BCB0AC98BF060FF857AD1CAB1539E51443B214E6C6BE287A5651C6A33A7CF8BC3E5CC6C09C240762EB2F0B25C80E6BA866F6B93696113C9F43ED4709BD7221628090D19BD575BA654F291A83053B94B47DF9497719F91296D5E08BFA63212ABD24E85556663A35890D21A97CB8A1A8E0DC45653093A058B2DAD1A0D1EDAE2F43CED4B84AE0206A77B6B35150F544E166CB30E47BD594C452349CCE2F71327849E334146CC5662F5D057E689F7AEA1FD2B1BB0F45BC04CEB801514F3C930E44EE4EE93ACED39917695546EFD5D78C090EF1C2C1272A87ADC3646881EAE493CABE4E364053AFCB22A621BAB938F1B2FE8393E84B5D2E113B51FDF720084E4E82EBDFB894D52C264D85AF5365237FDF20A9B4DD13A384AEB1AFE877781FC1B62D99878CCAF5F4B797C96056AAA11613719F60E56BF3AF4C0735A3E1B5F691129959A0ED13D627298EB461F7EC70AE9B191F2B507415119BBCC4DAA8024985A7D7AE424DA992A2587D109281B183DA90813F287406521565E26B2645009870DE574A8D0AD0DC73DA19F26AA85DFECB4792254E3EF5BD65ED32B8A81C152589F61A3E63E2B7BD46B490CCBBF17216697D5D6D87EE32545F900F5983CF3226DD997216897D556DAAD0D1FDF61D78378B5E4420E10F4D5CDD83B2FDE4BB24C8D8119F48A912E8BAC57D628B0ECA5F7C86A06925777834141D2F7B5B317C9907947166963B77059B7AEA5680FAB0F0DEB76AEF53489019614B7293AF592FD485D61DF6C99F5F7320D56554060053BDAAA982E89FB39DB5FA03C1BCBF93C2BE56FA310A15D85DEE86613DD5936D9020435D81795FBB811FE88D85D369B2083D24933443C0CB710CE29F50FD52A7E1209AEC6CB42EA18298DFF910A216BE1741AB1E985304CD63F1C2F3B3EB578C34BE5A5845AB38E91C83B68F9DE9A5D644652D60821A77076EC17A0A1AA776498DD51B95811CE82B2963D379890909E39E4C1925696449BF1365A8DBBCA21D791DD64C45633A596D8B6B926C4015F114D646C3304337560440611F7B0F87BCC4EB659F3667C9D3258EAF4EE3096EDAC3BDE0A2DF61624A318FBBBF1FC42E2E70017E83CFB812E374F1156B10F4FB6CCCB2E8BA6AA0B7BCC268F3044014C1EC56CF3EE0C8641298112F9004723E5847A4545FD34B9FFCB4124029140D352DB3A1E537A93E70C9E93A47B80979E1B8FA48CF44EB6ED479DF6ABE93BFA0B7D3B47E129AA9890302FFD5955395DD1D9483A627F530E8EC59E1CBE0542A3BB93DBEB737392FA9444C760CAE232C35D16AC8AEF4DE3DC5E55B7633DDFE1C0978E8E5D2515518EC5630F0A9F671F13790283B6159549622E1766D641E609CA26C593999A7ADFA8214D2351E059450094C54DE934A28E0D51F59FFA18CFAAACA94B5A1B9DE5539F49F9F0A790ABF8C3146A1B87038045C7F4A81694B7442420D9F6456E820FE081594071831367F58C1879E57B44F31E74982D66282876AA3C9693BAC0B81406A24E6DD94F3076D89F78407B7666A7509A06F89152D0B781AB6654BE96908E3B667B88A8F138BC5DB62C86E287215D0F5D8E9D4CE3FF8637F86EC85E3C73A9BEC26069B5B769CC446F87110BBE0BCB1B53BDB7DC605666AD9B23B23BA3F77FEF401AA108DCD298C751C6D901B96ED34178CE181E3A09BD1E98F97BC8EB21818D790E851C2CD9602A45AD63CDE41354DD9AC3BAFC5ADD87919E7CBC82D589D26DC0381334C104CB9B9983B6C2E10378AC1310F5C412414D5A8435E2C7DAF6C27DEFFBB1AED3CF135429DCDC0F0F5A9623EFF31F7EE4FE790CC46F9716DA34A15AD2162AC69C216F0F3715EBFF25A6C71839E54E14263CE2C7D8F6AFD1C6B7EC772E0C0EC395DB3C905D5BB5D8E1D3566C7B2410247DF8E730530EB9B9E924599D70A3E9A6C973BB2861355822EA7CA328468EF097A5A3C068390E17B8078A4DA364980DDB80A12C2FB973375333E2CBA83FFB331614410CD8B9554AB90EA4598FBBC71122FD7563C5CD69C3511F20579EE772671CAF34298F6369D8F2B5DE0711F4E145BFEB75E8767D48D43643695D36336C5276A9A5F629B7D6568FADF26327A69E95FF267278043DD9CA0A4206BF9E844ABA3AEB36AE12233FD8CEF1D24CC3B96AD5EF046F1975D7298D99A76BD949B4534B93C59CA7B9E5589EACD6173EA46A9F7FA0DC6588EC4D4073734D0816C6CE1260F04A67206A997F9CF4EF23848CF247DD9C2908FE15B1CF1904A4007B765DBB81F2FB1022AFE5C93A612DD70A7490BFC7470109AE1AA63CA69D1CCDE9086E9032A71A4AE9A3A8574B67029D830FD641392CF60E650515D2AF8DEF25D3F0C070BBBC7C16F94B214F32A7668951CE5BB795FB66C3E65053BBDE5CA90FA17FC02EE42DA713E94085AF9C742FB72041B1710C91B570A7060EA322C6A39CFEE0850E00F019945F41A290E3697CC8CD8C9C85A7E3ABA7563625BBBC2B3A8D344AE187701BE4D38AA5BA1A5B7011C250EADE01E2A12E4E75246D2459C06377C1427DB30563B47102393625729C3E12788683483962E8E6C6B4F5923D360F67BA39689DB6FE52D4E7CFEB286D6145C3700573F62470436F5A75B20D0641EF8456B670DBF8BF0C022E76C78664304C2589DD8F158A32B57B9122C60D0680AB386B3732F430B1C9D18641232FB322C4676EECD203790099E2A78640276C37476A32F72AC89D9CEFA40D438BAFA9C960491DF1CA4C0574B28EEBD15DE1076DAE402BE4C5AD88F480923618065C6B00781B79C149BB7CAC9263016F8B8502F6305581C94C693D655E84C9BADC91E7EAB1D1E987AA9C4781CD1E2D2DB1FEF265180B322CB21E62B915C05CBAB0AA876F3AB2F44B93DBAF59DEE23338224F1F62A0397EA6034AE04F0C6D5D6BE4465B8FA0683695B5F2DC76080F9A8F91BB8B4D4F739A5615DEBB33593750877AF3F52D80FC24C9D79957AA868291C91E77660EE41F3E7045AA53BCF5275BC5D9C821FA35B8B05CC8FED3212514338E56B07A476E4683810F7D5A35FFCA3A706EA218A40241C395966F99A8C1DDE202CA97E11698A0971401576264A5836D2ECC827FD4495F5667318FB73BFFCFA330A9524FCD20478B0B494CD9C18C6CA5C8EE9E5AF9DC90E25C3304F543E6DF69FE3FC3F19B3F520D19EC2A9FE49FD405244763C8F94E6DB9E6BF9C2A614A219A9362AD2DA32A998C2C9A2FB0B6BD1C0FF892E0EE163C33C9F4B7E6ED91940068571678D714BFEB48388AE29C66BEE27D633B50D26C571FE969A25BB755CA44EEBE68E01BD1FA9A175A5D2C1E0838719C2A7468AC9051DCA0569F193549443D77E57DD83C66BC5753E71E4E49853CB6BBFEDB61F7F0645B4E0A71F16DDECC2C371CAB4C2DA3A61BF27FF547FFC512B65E7F7F0285C9EC7806D615C8E0C3ACA1B762DA6D04AD99726A80213E0B3185C0FD09697B457CC1C673E87ED68FD9F94B58AD1DBF680BADC2C4ACFD970DE2C72FCD45E2CC92ED398E43724F55AF0F88334E849F8B0070AA4410A00A511F114C3AF05EEE66C6CC6282CB6C631236C1BF429175F632972AECCCAF29DA563610C8EF04CAB5463F32A8FAFBBF5FD81F399F684EA46A0451B16CDE4D101040D36C891723EAD87C8A9B1245459A4311BBBA2464F823ED60FE42EEE23481A565E15D5DBAC132808500AF67FF7A93998EFD772D231098AF4AEF6E9FAC876EB89CDA56071B1DFA5FB3EB16C97358997FE22597A35931DDC4C3604668A7A3333B24B7CE50BC3B2A073B3AB537D0A749260998263477A1B94014FABD8EC14B55589038AAC001C1A4C395EC4725CEA619A95D93C4DCCF61FE9FDC8714B112C31592A8A226E364B13FBABDED4C2952D93DA4A50F7FB3747829F613F3C31262F0DBCDCF14F8B9A5E82D989C20AB3590E88B4B6D6AA6758D736336C6C1C9AB627EA2E97250708ABCED1D2ECA7E16B8AB1D159363EB0091E1C4779F6580AD7FE78AB31CA96A822ED0E5F3469261C96391A99BFAF36CF725F24F815405EC1BC1C2DC7CAE945DF5C4F54EE523307DFC57E89B700383B3164A1582BD61F954182E09BE4ED83123346E0CC969A90E7F76B9CFB9C9FE55D6D0B639F5948DC98C389DD3E00C68FEC356D2BADDFAB03BC85181293467EF674FE919A8C788B1AAE1A71FCAF47198186692FE848C77FA47944B33BEEDE85A9D2C51CD9621A49EFE79660277F207EDAABE36D068D7BE36A0E06999D2F764E891D27010108D64FED39B3D8306AD16A62CF45D8AC7BD02E9EB1A05E0869ADB8E3C69CE295CD1642959AA9B2C2D72024263045676A77949FCACBFE031B2BC8CACBF80BBCF70F5E7B8E9CACB3F52058595A5F858DC2F8FF05137D9FBAE9FD11263150607A9BC8F0F50000000000000000000007141B1E2630374100"; + keygen_signing_kats[1].expected_PK = "3406C20EA187919F41CDDBF27F9C50A52B7EEED2870011EFF9EE10E8F69E0A39C794F3F7066E3CD63130D93950D0161F14CBA67DAE6D13A7DC8D9F439A6C626AD4005F3A48BA2E531C42E444E0C076496BC07DD0644D7096082258AA0D37F3D3D0D587E0064CDB9A505965691E27D295802D856B3295D4EA6562FB3247E343B1AE264E88A02B2777F92B64686F3F10C833A87FB693BA1F4DBE1812BEF2028BD37625D70CA9667320B8FBFB8C390BDD887A318E7AE9326BE4B457A612932C934E118ABC31A9C79D585AA4128E3559FF8790B96952C372697E96FAFF01E55168EC199E92A1360C3AC2196236561DC697A0599C072AEFD6A2683ABDC3C11557EB44B936465E15994D14C9B3F0E84EE72949CCFB9531F8CB75D79C9C2E68A1ACDB92C58A9C19241388C054345CE46CFC8AC2F1FF328639D09C071EB9E920F697943145B8FF45EDFBD8F5135929ED18091055CEE48E4776E87BBD62595E21990E72E5C09F48EB6F311773E523D395374AB1E0CC3D5B55F7EE22D2B189A882939CFE85694682685368E272DA8EAD2CFB972E4616FCD8143782C5C3A97F51CEFAC81387700C74D5D2E5B92CF762A1F327841AA117694ABA918FA29300C27DF3029EECC775EB2EA2E9EFA882A0EBA9E82C588DDF09FD4620E084756F5069BE893CFA1D8E0EC69962774E70D41F46F25F291C091BBAA447ACD24BDF5E7F0D6C50BCE69B79F51A4CA8FDD8343C49DE55EB3441E042404CB992803C2494D5512AA67A4BBBBBE765AD543C709A07EA71083EC4007E4828C58187C5FDCE680B34C902BD902A85E38C674B07D13E5BFC15CBD547867A3CC9A00D0DFC5219CBF4E82E7010B009493EE5672BE249DEBF2F4E91B5469F7CAAA5D5C69A080C8EF8394F06B8AC95FC8489A0A7BB21CAD3548BA524B609EEF7CE7C20DAB6C5B54B58307B416C3DB4D653A1446F25A8874A7B8B0AC6C2DBD175726849265103D455B1895213BA6C3D177CCD788145EAC23A65AFEF9CD75B0C2F0297420CDA46AAFCAAB92EE9955948A741BC3F60AD609A53BE44624520252957B2BA03113F6FEEFB690D0A7F5952FBB470F3F9075CF9EF0541A9B6BAA9DA6795BEDD8F41A27DF7F6C5855030354138E2077B4B2DDC570FDF0186DF23F077E1CF6EEF833D0E4CDA82709B69F9AC52E4D9254A7D0DDED46D64EF083C3585FA3A5B25D0323FDF17EABCBEEB64BA8513010494DF411045DCD48B1565697B0DD507450866E582BAE23C15010B6088806C254E6D81DFA7922F189F3A7559792F198A96916F96F78DB378541D02621D0EBB78C72D2A360E47EF09DDFBE1B2EC24C99C692E087D84C0BBBD8FF02275B51813624E97448C5FD294A2740D0775060A8F785630402DE3CE4357A655CB6DF2C534FEB3DAED1E1FF7C6161A0B0718DF0C2B3C228BB69D0D8828B876114B95621EDA905766E877DCE20756525A4C31FD84963974D984043B5A4CABFAF21297390A09FB6EC15867734065C7EF6B18AF9FB3596919820D21B766F5F2154E8BD3C74FD711C2F80F90431A44AE34997A9085765636D27CA3C3A7CABA01902D7554B0FC97180BF6547E97CBDD5E094CFF25206BAB14BF30C41EA76268996D4F011946387657B61E8715DC097DCDADE05A72712179F0A110E4203086C409090371BD175CCEC01DC33A7F4F20EF3448A1757E0C560BCD7747E6177346A8B8BB8F9FA7D04BE2D897BD3D5B5FE1231059BA5BFE40180A7F3ECECE7885B09970B692548C3D065BA17522151E0EEB32F3664C67D5164F92B48F3E167D71E11F3A822A2585BBE6395A9DD827933C31B7E43188830E5CF60381D6CC58DAB278AA0A5192F7CA4497704BF951000E3E786AD4AA651CD9E1650D0BBEE5B163287B44C1A918F6AE43C14E97A10E92F3F5F8596A97CC54094BFD618D72C433E4A7BC1ABBEA4406E5C5C8EF3FEC6F750CAF9654295FD26AFD89BE26B000B33C1F70DB955628AC16C0A25216942460A61A6807131EA5396ADE6716993F6D4D178B1E604DD078F2B488F784921467C3F93A4FFD2B9936F1C913F48B51EA64B64371EBC7B0F8A0ECA57FD0CCD614A130CBE5B9B2736CE5EA9652523AA2033DFF532F9FB94685456DB9C044C9DBFAED8B74CC7DED328737ED6D7CA13E55397699C8E0DE5DD7CA508EA4659C21A07968697BA3CCC7C9330CB7F8B95E7353D2B3374771709F364D82F3190134A27CD2A34D61869962F2403CE1F3218D9DA220B540F907E3AA578DFB60777A3109339CDB7304360E2754B3D07E132946C9DD795688A0704C75B10BFA36BC1306706353A1FD0BE5AE1560B7903FD411E49620D54DCC194D6E240FC87712C005D928B7A07C4F3337050D6060BA51EEC1D6FE0D7D73B39547E5F9331A6ADB3202EB2EF327F69C4A4AF35ABDE056475F4A4DF8728999D4D4BAA1650967269063285456D4CC8CE8C1F5B9E29E5305E387D34FB7259521E620D68DAB8532CFBF1021BBC8179F9225F38A0F04F19316F388DA2C4F6BF1C8F9A6343D890E4E4C71BA1EDB0B6D0B2FCCC559CC20AE06352C75E09A19A109BA1F1DC8D5CECA5D46EADA1AD47BD4F67FFCC40AC66DAF5B4DD15658B618631861EB6564BF13E9CEEB38225715E484983A706020875295D9BB289024EF61D116BFB84D72DD2D0F3C0373CF0605FE838B18E4A5D8DA5BD23D9E6E2B06E7044DB3D0774975FAFA8BFB6DCFDBE95EB5262FF93663A0A6F8A7B53BA1057E611FA1B3A3AF42741F291189CE1E2F628EDC1738767B0FEE93E66BD29FEB1C7CD9CE2D516CD9488FF33E9CE52198B05E2CD25020B37BA092F962B911864AEB5EE5E0037D9A5FB521EF99A1120B9A9F68A513C02E72794250333B68CC3A0AB9E473653D015CCAEA2B102B332B3B4BB95898440D6D290E73FF8F80EB40C2DCFCE9EBF64C574EFB9A1C3BBBC5AFA4D9F05F36BA6B44E66AF4959B79D706612CA98E689C56DB11AF684A004034FCFBD106BA1CA09D97D51BF20E2058FEE0E1A69B4A60B9834539AA94BA63EE1402CCF0D19B280109DC296CC2C40CF8441BE76C7DD2D17F3DE72B11C4AB7883FF352AC5EE4630D37BCD8D92291913F4B81021A094FE3DEF52824068C5FDCDE8EF26976B29DFAF51612837768A69CB3D06ACB1FFAA0B6F5FA0C5AE618D2156AB91F72697323A9D8BD3FE24A2B884B635CF933D2F80EB0DD48580ED87A30934AB5E7A5899299D366C09E7E3215935492E9356E3673E4DE1B29625FAD193BB53C0BC88BA55788A9970CC007288852661DCC161580FFFE307BF549F2721090C5B6424E9FE7852B8A76C6B06E9319B41720979D685669E95479467336CD68C06B48A6CB6916BE4D882D0C6371380F97F9AAE546AE520D843514E315146C7599DB5DF4D4BAA79EEF3EAF8C38EEA0DA201DDC5A954387C372FA1686F52C8F5CEBB9D54FF879D7339B5DE8BED40889DB44FBD9302BE8F0C20CB945389FE9B56770EE176D2999A9035DB69D9D13EA4E6F9CDCDFF55A5B6945604562915EC7C81D5D2B49E5B1750B01051E7532B8D644CADD714512948AA7F2D88CC5F154989A7D4221C67DB0852C02F6EC9A1EFC7CEAD302D871600C57CDD3EF134DF2EC0070EC7F8D1A80919045D1E630B426A941E15A0E1D6E258F47E2ABDCB9CA791F99885867CE36B6A49DA864A85A0C82B97959B"; + + keygen_signing_kats[0].MSG = "ca393154ce0e065793750cbb96156c74eb704ed0f2ac97c1131f250f550e1efab980c2cb146960dd7c0b562a1f412c6b2cbd203e1f048c73376590bd39d7a969"; + keygen_signing_kats[0].SEED = "2e693a2372d55bf2e3793a2d54a7c9dd70b92c0c2f78bc56450ce98816c5f730"; + keygen_signing_kats[0].expected_SIG = "8A659F891085C42893C7523700527092698C1C191B0F187A493139A48BAF373B92B6E6D9D507A0BC0F9CA86226FE5589EA760E99F2D4E22378E4CA968A3E945F1D7F36F97F7C11CFA5CD67D63EFDFAE7DF68DCB8A3D6975673EBCED7D8ADBEE342F7B8E6F32E6420B520FD284F72DF044D322B15079150E6BC6FCBDD3EB6FB175238E3306069B4EB7EE239FFBAEDA41C704BC3F38280DFBC2EC22DC806357E4282F41D3C63FC9F6B3B0A02AA0BA960A45066424A59DE99D43934B48BBC28C8E30066214A1E13A967D5A5CFA25811C013D85BE5BD1490C44F2ED16D7594011AD2BBB4339914E650A604B907D8EAF80FF24A42B0DB618D53C14857344951A653170621A225A06F70D0329C3EA15798A28C1111C2E4902DE9C04C54525254792C5C0DF0668F2DE6F3D77CDA05605A7741A4BDAF5650A76E68BB8BE505CF1B4C18EB3C3820A7A90E69E5D170C87DF46C29F1E024987681A1D36D69ADC6879C0BF785A8139E2A857DD4A76B29963DD28ABFB9415D7010B54A496133E5BCEFBD9504C0A541A3AF30A97337B249F585F604580333D83FD453E109442E1E0E4E37105781F4FDB9590B05890538BB61414C3094E0E110116FBC25088F6E32131FFDF3E9AF8312D603E25B695D8F6D9918DB442BF60F2C4C8F395A7089208D4CC82A99AF093EE32C216BCCC4E799A0FC9A9BBA09FD372FDE10F0C448B4B9DB4631D03D9EBD8BFEF09D686DCA17D1B14459C0190C4CF9EB53F47F4E95768364CEB2A9A36CAB718BC483CBDDA9BF1AF881EA346EEF7BF245E09E08D3F355AFBB0B3F6420C725368E5DB7F6182CAB20C82D1363374FF9E18F444111923E94BCFCD236293F4E47C391184CE4EBCBE1716B1638B879F7D526A12C4990B552344570552E0647602D0BE13F4DFBC87C104D73760EC31EEB9C52AF2BE770D73CC4794A88B61F2619EA0AD19E90BA1BBA75F8892977F3935EB3273AE04038B94AE7C3932E10B4D45E24B5EA4E7F767ECB2E929CD0C48DD5BDEF58646A17A15961FE57E008DC1B5E5331C8D2E3CB3A3EBEDF405476D33A53D707A38E9CF5D9066B84DEB8AE8A75CD776877B5C44A90694A970614E7CA109BCA9B76DA126C402F814B8A2D22CE7C2F5CBDB70C8A0595F922341CF32307E5E69030072F91B32C29D1205F0D585ECD2862389A16ED461E0482F65B3063B093ECF46B603863FFC85800041650143D5871660DBA750F1102BAD4EFEB3DDEA86AC29D0510E00B5A811586102A667B76F997FD6F0A918782327CB374AAE591ABB6175AA15506141E54E622325DD65E4F4C8F69370C6D82F3BD06F80B04DFDEA8D547B1A2AFDE90DF654B37AED1F1DF080B24BAB6C3D337A25720AA73DC3E5CCA88F71078B5D3F2BA1812A593537171691DC313E21E9012ED9DECC6D20416F840E14712D6AFA552022C7B5EC578F42BAB2F77661B2C4754541252251B179FC765DD52A9556C650E795CB153B2BE5BC8AFA721F87BDD996F7A82BCE1955F163B6B951F837E5FFC758FA92AB83D472199DDC8942902713D15F5D1B57EED176AF6366FE11932507221963D8D332911407F04AB610DCF434688976EC347B2B6748515C82329A3A5D31BB3D5A73B0959184B1BA8799ECBBEC94B5B5DE2A794810AAC46D94E2210094ADE4807E9DA3F26327A32E019C52044D80CD2502E67FAAEF5087ABBAF93543BF9DC3D3544163C469952AF12670BB21CD946210E059DE868A52B34BE30BE951DC81092ECD0CC261803E25B7B56F963D58EC92399EC96E095721E2A4B1AE553C37C90CA8EEDB76FFD1CF7F0B7223E6BD68700D2B04626D12EFA1053C65BB14892C623C8872B006F8F654009AF571A6F91D83AC8E6A3260FF78F946A197035BB4AE04DDC9BF783D315EE35ACAD9BEA041E5C631D2C860D4402A865CD3D13E82A0158114B5F51D403A769277C0056C4C645B29177B79394B639074E85918E4D9244EE4C2FA2E1DA05903A516C5054B348FAAD38696DCA8214914241F658A0A659D36A96D96515D055C87B2E628F4FDE39E18C2D0F164DD1893F3E595F11B5463117BE1EB276328DB1073AE17EFF6419652840CF7F99B93703C1FDFD41102B02AA6BEDCFFBEABA28AA3BED6FA8EC790243679E629397E64384493598C433E5A34F1A96EDBB9697094D16F33F1344608E3122361B25EDB34AC763049F5EB9D21028553893659049AC318F6FB55B6FFB13D245F09A413D06C6D9ECE959C2FBA470EDB17A00B9432665A7AA223193075D7CA97B2298437F77F21775F8867270B9829CF8BD7CB76BE6C6E8F1036BDEE6E2DBED599836A43432876B44BE2930741CD934E5D0291A8457BF0A612B99D51D6CF4C412F5A156222AA1548AF136CCE6A57D3BD730D0B0A3410F4303187CC23E6032DDDEF14CC65B45671A8C0EE608881CDCD7F558ABEE9714F25D5C491068E3E278CA01209D96EB6EC8C679B21DA34AA9B494B4A67F2C742AEC06653FC66D4013557AD388E8EF21071FDF117102786D4F2DE16A68BD4380BD18558BB29FCE4FF761DC3D5DCF48289198B1DC586EFFF23FC9A89478217B37FB6F69CEB89EFF9DD0E045CDDC05A6582E277052E51C65C6DC5521E2F59B854694FA985D05E923D14BB7EF6AFE34E63F25DAB21F669AE6C6A9CC70BD8FD72D30C9224D6ADB2F5428193C6190BCF1C073B409B0C35B658ECA358C2B9D24D02E5F5926AD2329829926C3F39B0FD49BBA44A9D3C5966F07B4A06243AF5CA160DEB492E1EA4847FF4FD14CA75B40D125B48ABBFC3E5B764A19A1D491AF110D876FBA529D3B5D3A3E48686AA9AB26947F1FA93D9D40C3DBB36FF652C7A30A3ECC728E94583DFF9AF8A275886214B6AC055F3323B9AB25B3822DD0C2ED64B95E3DFD9E4F50D547BFC790694F38CFEC4146DBD8DFBAA2D78B2B3E11F340ADB8BEDDEDDCED867D584F67B9F3601A62F2660932901393486156B0D61FD6E6B459F5C01A485979797F1635687EF246C960D64C1A248145F5D1658C27D42F0169E71825EF9AD8893673A5D323A05D28E444660ABC4030BEF6C66EFCB057A9EA0684B1B64735728DE008A65E2FA43B84CE5FC39649AD06C92119DDA9C70DBA340FC4C27DACD809637D4FDB0634684C5936B009B5FC3FC7D9B09B29C70ECFF695D885A35C21EBFF236BCDBFED085F7B4E609626221571C8112F03748DD010FC97FADFCADCF825B0472254C026A0C5E83610E870F75988A7148F2BA399E5891164E59740BB41D6E6277C73B1412993F91C3E2DAB02A4F12C427ACAA14B21973C1D442C79D2F038AF9AC48A0D5E12EB82E234615BB8692DFEA8A98D83CA3DD9033D7C48B00A0731EB2DC01377184BE6F2D7DD697D44787C6A6053E6E628437FFA0419A0BEA50FBE52D6089A71B2E82D002EE1FBE6BB3108CE863A08E26890DBB769A417E8926950419D2A952E20AEA560EFD64A525B63E46D2604DBD2CA4EF862BD3096392D5455A21095CA663F886460F592BC75555FE9B13A00A8CFC9D6991488AC59CA87B8A33C472866F821D20F99BD228509F561458CEA2D7EC30048BB547E53DC48F1F976BBB304FBCD3F1DA708941A3B3EC3B7E9992ADF216FE127CD16E5E23B08A7E364704184F659DFBA2719E3C78CBE2F19CD4A84F12D5F60ACDB839DE814C52D30CB8B216A443B2F98225C4E18653CB36CFF848C0E07FD925570040E60B9810BBFA1FF2FC92A0F9EA3E3C74DC443D5363DBC576684182B13D573BEC531151F32F94C1CB54533ACCCDFE86DF79572044054713F3A83275D47B552CC7EEA9501DA6982CB81EDD982CDAE683C10EF122BAD67AA2B69E1BEA2F628880688ACC773ACC727B0B33B190EE05F3BF5523C610CAF7A838A7B9C3F185D44696649D354E1DB65D76832EE32BA1749716BC509AB60688164A030E06B5866968B3CD64E26950B0BC99517219AF04AF5B79EB593B0FE4EB497293A688741027F0725565677ACC6E9432901ECAFA14DD2611144AA5F4F0278DA0F9D7502ACCD271DEA06D6A89C42D473EBB50AB9087202E8ED9E4C1476B48445E3A7A3E022F32A220BF29B5442E41E0106D560EDB47BE768D620B13767EE72E0527D07270D2178608FCDF80284668CE9B74CF63DA78350CE9BC7CCF87B38FDD5C4EEA3CDA098282285D14B74072F07524B0E68EB7E780EC225D6EAECC1DB7610A757508D752E3AD82C5D838B72677FB78EC5D5C0A6010BFACC9AB90CD159280F440E886435FB8A525B8AF97469A8985211A83FEDBA6A06D713868D544F104994EE93EE0A3C42D5106B6765210583AB868BE1A5B9A0269757CAF882A4B3C2D4FCF8DC4F3BDD409684D17235763013D3939FB4BB9197175D6B25A966399FA0BD6486A63E4A20B91B987E955CDE99DED263A9EC0796BF3D14B2DFA3BEBCE7CED3E0953C02A44596B4623FB73F60C6BE64F0DECF9D555CEA95CE07C60AC56CC0C20D9E39AAD4B51D94682C0B09010E9BD1A8D24E1BBCE8FBDDD30980F03D67A6413B95C22EF21B4E889ED43F55D787E2CA0CE1B3E237B46BE54B65CCF93E05CB4D63141BFA54F90CCC5B239417A8AAD7A88FA7CCDE45B26D12A664F49A8154A3965FA8E3CAF276E35B6AF06D8F271CBC18C17253C0A7E21373E7CAE61F6088CDFA4FBB434B206D45A3B937DABC331342D39CEA1FB4C52FEBBA4F89136AEFEF338F021E4AA3E0E028539A5F126EA37A1456655311493CF992ECD7602E150A290EAD12C9041ABC57C13EFB1A3ADC7F3ADC7690C8217B85D2D9D92AF969EEE20960A74759FC0B91503A391A7CD57FFC822CCEB8CD555F27C463F486BA2AA96FB2776EB88714B3225C3690A108D14406D6BD6241EC15CCDDCE4FDEA4032A667641144716BE03D02B52BC002840882B9C377B2BE19CE16A49867CF236ADF14E3401DF348A642548D36E9FA1FE56CD02DDA2CC05A50E4BAB45174A8BBAF0DFD8A2662E96DCE4F823509B2FD9172C85C46F281EB9785D4C9810B7DDBDF984AAF2838D7C854CA47439D4D359A7CCFAD80D3BB18D843818A0F6476162AE74766C55F217E2F62230EF763A34B360C7AA6B3C531D6869800AA8D933B7BB0E63FC942DA2E9B194BC55FA64ADCA4DCA0A58E898C437CA9D1239F50D9CCC834D9DF1E6BCDF8EEA63609AFA46852324B31B96FE4A535083423D59560D1AFD42F3F3C57E98DB0629AAF087283DE6754276173D3BF388702E263022A30A224466433239E6F0FD13570C6B96C491151EF1916EDC7865E2ECDFA2CD5F32332E224757E27C6ECDCA51E34C498D42BF07C3A7A36B24EA3D0BE1D668BF5D011577068C05A8EF206660B3460B252B39F0BE21122CC46541C4F79148D6099F78B2F7D79A2C8E0477DC2D19E0DF277E2504ED60808553640BA21E2427D84CCEDACC2390901D4D263BFA2BFBE18596AD80DC44AF44E7B2D0F41FB9EA0890D718DE8F34201C1D018DD89616884291C14DCB0A3C985865DCEEEF58EB8593E1F7A7904E704653E74371F9C691BFA337A63C60CC1EC7F3FB0EB21BF8AD4E1029EFEFE5541A3447708D8268C70345620AFB46C5004D2C49996215EBC2D14302ECFEA6727A5D6BFD625FF858B8B0992F5B5DDADECD788777DCFFD17126BAF4109A74ED7A0E24E1F339DEF1E19C237D3CBBF070694E067C95FB08DF8C6F43B545DC4466C05E0B3748B3FF01742270F1CB619570E6EB8959E3E99D05A66BF2C37BEBE515AB6D3F495C397E636B9CBB9C111BF778508C73F190EA4CED77B8015E97F2F78EE087ED453ED48C6BE372452C22FADFA50A30BBF441FABF7D87698C6DE497F13723E3A5B6BE71783205AB2868CA3FA35AED4D3C73A0C34DD21972F693F0C47BA839F27FB406215DA997C65B4DDCE96C37EC416BCD378884831651D7CE60701B034C629D33C10B2F000134F1E84180AF6AD365B0AEC2D2E0A1B080DB26E9102CA17F82D7073523BA7CD0A8ADAA49ADD73F42A0B21CC6C70089AD15937F21B0935D77AF65BEA0CC5010874EB966BF29196100FFC274E359AD514ABF01B5FC21649B360BEF9B2A39034B9AE50DB4456B4C43DA6FDA72994A184D93C7134114BDA317B6AAC8F53D75D905F6EE49D6E7F5C48C6135B1BD9A88DA1FA35994EB775EAF760306B4915181BC51F61DF9361B6ED38FFFF4F0E66CB15EFDA30FF1DFA41AB8CC4515EBC7C2B47729261C1D08412D791354BB2431CC9296C2DDAF8982036E0B3A609651C53A2AA6E505CEA9AE27F02155EC21A0BF635BD63D9B145A655D48CF6E527698987FE67E76855D710DAA8BF19885DEE24448B8AEECF685FA241ECFCFEE3CF75E54E762085AC0228FBB8C87A2ACB57B3DFD585E8C8CDCD8EC03E34C290A521EBA4CE37B9E1F446B9F4A1B70666DC9705D6ADD69FC206B817BB73A87F4DAC204D1151E24B8FCF7F6EA0DD84D57B85FCFBDFAFF66C0CA32A0251D5CDF19252B2D685BBD746DD2A5E8263B5154838586B5CFD146587BB3CDD9F30F141B38575E95A7EC9EC0E4E6F412475863B9DCE3375B6677828690FB6699C1CC0C4D8290B5BCC0F500000000000000000000000000000000000A111A1F262E323A00"; + keygen_signing_kats[0].expected_PK = "D7B1AE0B7AC9DEBF3236824CA48B49A5FF417C11FE65C667716FBAA44D3DD620F5EBDF9D49AF3B711F815E9BB80488C8F3106EC723E7CEE24F1408D73787A54AD9185B8A7E331F6085371C71C5A94A64B11AB9C2C05D1AB0AB8E2F6DE7A10E3562C28D10C563C57517688ECFCD7D2C5103511CEEB38C17DB88D256DFB1282A2A8D668543C2A5D44E01419F2FE79A9CF7708EEBADAE74956B0715E9FEC122CD98163DE1B961A79C343655957EB046E13CDF26C3E24D625F751D28E8B08BAAAAA2FD10D8071CFE63C875E129B290B2FD263D306D502AEDF01423A182DC1608B392283D0C5A11EA510048EC026E3D53A8F6124BA59929C7DB8AD898A6277218738C1FA2E51B338E7F2B7BBC45F5AB90A911C62608B663FD5DBD157BDF4C62CDDC3A82D8C07D70C896B37B56CC307905BE965B17EE996A1420044941F3FFBDCC6398E3AC716C78DC558DB07EC6AB6B2BAE75F2C8EE5A27BA0109E1993017D98B42933D19D9E0DE56D743E6CC681E2179A6972DB9EDC51902E6527A3A9D7C53B66AF3BA37D62684C0CE046798EC4CCE74224A1161E8F61AD01D44814E34ED69A77413414CCD597588964CD1D9824E50BB818928CDCE1FA35D470101EFD1664AB86A4C1FFCB2E51CDF2072BD8BDFBA7440BD9CB8643D5D8B1833B1771FF48DC532BE02D57181CBF38BCAAC0302E0B499DB4176B967973201E21B6E0E4D5ACCB65F1DF56E3D855F7AD2DB23CD0F838DAC241455A085BFE125FFB2526C3A71DB0EA64E756E0A5BCEB7992B10518AD366DBA6031AE43F4AC033129BA2A206ED17FECCA6747E5F350E0791DD0656125E682CFF2C0176F6A6BADFDAAEA474702BB1A60B4169F506977C693CB34DBA3010A0D26A5E6C287907E5CA1714A93890D9913D86EBC5900682CFAA0CF01573369AF40708F3CC83DF996CA12530B54958A288F58CF0D95C61D5E689ED2208E4A1AE20828D1098F894578E2C6FD1841A583954B037B7DB54DAFB11E6D8F38A7A091D777B36A29F90744C11D4DE7DFDD37E9E494E73C2920DCA5D8A377DA84148F0836C88D472FFD371402DE5A990D3E374F9478B834FCA975D261E79F9024DCD70DBDA745C776678C17B62353CD93A6380B849BE5680B679ACB0113C004A616D8E3208F89A52264319F973BA345E16AA40825D14D30FB179E8EDAF525AF8BAF56FBD44C97E0A3191C4D9A3DB9D4F9291BEC065988D82D39A5284F435CC2BBFE76367AC78E9768A12AC88F268157ACEFCC0FEA6BEF6E520A3603AFC090DC7D922D779B805AA38FB31FD95D656EF5DF3620122CA83DF5E83051CBCC2E6767A9005DF0D65DCD0863A3B6DDAA9357BF31D9E370A027458E687F6FB159935101ED576CC1A1965B51F1B46856C070F3EECA68D55DE610111BD831D34CAB4BBA7CBEA57065E27C2E2A075D2F301BF6B795CDD8C91A8610DC72E495A90419E58BACDAB419DE6CA5A06498E6EA382EC2CC284DEBF0AC7D52417CA1310484EE64C0C8385839D66A48821BC099BE9C267E0BDEBAAEDF2FED4C8D5C8FA38ADBD77B153991516C444B5D9F7FB01EA442B3F603F7285896C612B9332DDBA545B8342D9E553E7AB2C88A320F9206F9C72FE3CBFA15EC12541EED585484D9E7E0A97B44BFBFB66C48518BC31543C680A7D320424BB0A22697FE255E4787498F998812C712CF20DBE71750472C51D4AC501ABDDE8B90CA21476383E861721554A9E667360E030B02563E51973AE326BD3F8B9BED05272845B9CAED94188989624D70FFE5C6758A6BF6E225C641A3B71AED6F2844778C4BA844940544D8C8AB1D6556737E995EC517F66A60B616BA243E1739CB63443011A91E704210637807B72A993EECCB0C9719CD2FD3480FE45A4B329E7FDF51CC8FE9D136381A2DA3691AAABC604AF98465EF36FAB8C2C71CB9BD1C6D48BFFB072206903C6A41516212ABDD40206583ED0F66AED210023B19DAD522ADFE6E31586188566B7C64FDA5BC850691C75112FD5392CB18E5B1C2A0BC79A5FA757C5463F134980F2A203A93F759F3FD3AC4A17C71C5C6E428AB13DA82F3A52F45FEF60C7277EE256424542309C371B33CA9D1865E9F52D839FA9E578187B6D0C7390DB1715596ED24250AEB7968BBC9C5B77A73BC9B2C777E49B73F918D13BACF546942FF5070B760C1E624DB603DE558787F6BDB326B3C93165AEBE0B818A943FEB8B2DD72D8180917B739789B533FE057D3154159B0ABD67B60FF681E011E152BE6749F296E778461277F5AFE8BDF28AC56DAC78745545E3C20C8639BB76AAA76500E799078E59650FC82A0CB2B28A05DBF574CD9A50AB041D494A389D4DD779814A2B24ADF580880E95BC21DCCA392CA6CF7E9A50A3D80B5E6855A0426182489090BB82F1EA2150016B4B3EDD9FA3A2F8D85AD61AC2807BD814E5462545B82388A2CD33F310E316D4815F8812AC924FABDABE7E696E0FAFF17546F359430461053031D31BF20FBEF05A6EDFE9720E9BF2DCFE15D83A597B3BDC52714778176C3823364B383B61F5ADEEB770C3D1FE161407D697B6201D5F5B1121D034A6157E46F81342ABEE5D7BBB8977F6209219BA4B8DE936EC87054132CAC3FC65666199F48C20E2FD56B08D04CCD4CFECECE2BD1C65ADC9D0B8F26E5DD582845B761350A3A8E6179105B7906EA2DF4CC3C21402F0FD5ED1854A11CB59262819DF514CEC51C026A2AB9481AB229FE42B3A0494FCEC6C2F6AC160742254DAE4E4CEB4BCBD288108A71805EE27B994BC919BBCBFAE1E3436EBD6AAC2A56ACC37DA6D39B52266FD3A6B1331BFE9BDEDE19B6227575662CBD6DDC5049E205F30272C151BC0CC00E3A2EC4A0E012FCDDE6C51FC33A18C297F86AE61803B21346040099BE7B5F1527E9D648426F1A06D8F8F74DB968D439C04660B8B14EA5BFF205E273283FB1B40B47012E718C50C7E899533E591B54F8D0631181962EF810298B0C29414882E51B073B19BF1C49A893E6B541D61AA48E2EC909102C954FF63E81C40B61BEA01D642B869002D6D8BB1DD28090DB3CBCF1AF7FD0A17108C3842C12B4B55B741C28E303863F74B6A1998D18A7952CA6F1A6F83751A5550EB32A0F9218ACF9945CCB1181AEC15D750B74E6A6B170A6DFBFC7A09EA13089B6906CDDD285835D841C2F27F380FDA69A0679FF94715861146C9EA97A728E1FC7A7AC23FFCF8150F94DBD64F47BE44207903C64F2645DC7D4963CA94D0B97E395341C8EE2D52D015446F972415A5B651289274F57D55705B8152ED2948F8BFC84D7DBB127F30ACF4AE91C05C8D5C964992A4E6E8DE6B569F4E36C5B846A85544916DBBDFF6C9250C91B9523D5EDAC17505D6BEBBBC8111E89AB795298CBA5A0E25450EB73DCDEB643C051133408DA8F3D6B47C1AE23F1B010473AD0A2F62E63D05800BF9FB05DDB1040268A0D4F0EEA7AD172EF547A9685C4BA4AC0D719E607E96D4D20314153A366029A81AB826BD5235228AA2230C6C0DE15232F7DF8330536A5A156801ACC2F20BAD0DA972A9FB2B4566B48F648A9F870DE8181484DFE57530A8EB0E5C214C418224699824CAE98FBAFFADC7C9DDAF635ACB7C92B2113480FC110E1D43B6DDE1A755C4E11F197E7C8CFA38195774B65DB88FE7EFE0839C22617E0FE33139EFCE9342D2CE72616CDD58D0316C1694"; + + keygen_signing_kats[2].MSG = "9433ddf6e491cbf5cb03720b542e432f868bc7b5a0bbafd914f210c3a9d145953c6532b8212660ff219cb0bd283c6c25501aee58ef4201916e7671f92b759f21"; + keygen_signing_kats[2].SEED = "56594cac60a6f972e4317759f5dce7da43cbaa18717f89de21b83dcd3dcea9a5"; + keygen_signing_kats[2].expected_SIG = "9C5EFBD8FC4BC59259C5528538F9546FC47C6ADA017628AD039E841F3EEB41078CFEAFE6BCA288F8A1DBC40A0A8DD61D7CA0C5DCD435267B4352CA2E2F3BD346CC790FE55DF82A25C3F23D2D64B4A8970C1277A2522744027C90F0FA18BF22E49C1AE5E589129337505AB9ED4318F756911ECAB97C5E0343EAD34BA7B6B89DCC130903E9E0902941B58213C94C19CCB36033D514A628B3E99D819452A9298A76DF24407CCB332C55FAEC61CAB4C99D63586DEEF80323B8DC05EE160177046D298EBE7C7E07EE5570F6E4C95EA9F5FA6A72EE55FA7ADDBB09BFC096F6D544BEDD75DD1702203396E149C846D66B846CEA8A7718A627122ED3DA6E25A47887958A97A28F5A84A7B9E608A0D929CC0B48329ED824B2B39EAE56F20192F9BAC700C2DADB42BAD7210A76034CAB87576698AD61FC4FDE9A29193ECF2BD6FA5741143FF6D5DA8C125FA336BDB627C8ECFB327065C027408561685836107CFC2DD755E7933A2560B8CA5A13A5972C0F3CD1FABE9D1D31ED52E63EAB7C6F30D49911EE8435E1D58F42D24983484F62C6324CCA3AEF6279752CC429657C80E59D2CA789D82070CA167143B407290B373D5AE0F32715DA5040FDB844BB8B1B388E5131D5ED474004FCB10EEFA799CDD494397EB43DA9B69CE5468C13DB7E70E56A974B8EBB8636E62301161EE9CD92A61B9C00C389C784DC48EB29C3E3C03C13FDD841B6D5776583FFF2E143BA8279ACABD9B33B598CAED53EEF93333AD2076C5D4AC55625EE6888D67838B3FAE33068EE735F65BFFB8ED36A75071143D0DCDAECB0EA4BC1997778A6E919847B2127EFC49860DF42DB656681B115E7CA402D7395A3356957C9F63F6B53D7DD9AD681AFAD26A95B3844B042966B29961F2CAD3AE1B392C0F6E444F5F28F9D80302BE5AF3A450FF674ADEA63B72EA1D5E7C864BAAF1B1B2F6C65DC25073073AFBDE65BBD82C4EDFDA5FAB7C5639A5E79F4CA17143C4767A13AC4CD1942A1FDCE95F832577457FDEDA9FA8BD6CD91BEC05EA2AF3E77DDA26C233341147513E2E1E66079F6FBEDFB82B9C426516DE1AB27BC99C52EA86D16311AB303489693BAE687CA4FAF7FE5FF3E66D1B4509947C6A3AC8D2706C016BE4A75C64D0CB9F619B0E9310052D3A7DAA467698F54C043123316FB07CB095D389FAA0D643D9C68BEBDA18D3F26BDCF50C58271297F556C5F69E0F900C47E40BD22B9EC8F5762BDA9B6351817A93523B8C5AC863B8CA50E16798578F19DD85C80DD97ECF158944ED3874EAE1E4401B44FDB28053E4458B06B6A51C44635414CE5255C038FDD00B1777A12D52738298647E10B2C24A56932676305370B7FF2290D3907E1501CE17B67149CC83C19DC90BE28CD2BAFBB6FF08293FC2F0CA70B9083517F5BEA55BAC22BF1ABBB940E522916ADDACCF9B0BC1B2ADA06B3399F5908B6B517454FD84207A83C0813F1AC6802096DED339A162892FD2DA66B64C0E756360EA2A6D0DB794D5EBD44AE81263229F78F90543172758228F563CAE50C02B0E8918871D6F213A262B5C44D0EA31CABC478770B408A91FC7DB8E4A842E1C631951263BF836A338DA967582F4086D4A3BF47EDC57DBD6879D675322548705462912173BC8278FCAD7B546F9B9F73852724382A29F3904A06C8BC2E24BC0C6D3897A811A78EDEED0B8F8DEEE869542F936C7FF3AC0D67E55C95AB1C7A5F23AA1B989FCF97CCD2AE097A6E8548D97B0A76CBB2DFCCAB0C7D1AC9EBD3A8EB8F411A5712DCEFC79E9CFD3D69AF856E93925239FC666C7FF02518BABC50E8298766E953F95C2557637546DC7FA1B80E994F4EF93336122BBE707CEE4B7C2E875D2D1E14065A8636645A374D543E42586E4BBBA52D94E3EC1687C0488379A53C8DB5F409630586319033A06F7B21E382148906D16144FF8990B94FD90D4E85A729302410B89F121258033A7DA98883B50DB5E89CC9655CDFF8E9F041A075B7C742BEA13E36A83C5CDE0120BE9C59D50A0496A862432A82FC645D33C174DE11510873FE541DEA335E8054A0B193574CDE4E20CAB6E7731A1A28DED03844B3C76B9362565B332140F91AE84016758A0C4AA7ED931A509047A5F1F2E71DACC724808E8B30C96C5C1984FF406B3667937E7E9DA309B6A374DEE6E2C91CF7FD8F4459D4AE9D6C27310EDBB99390F897CC98D5A2051E848E8DD0BCCCC382FDB2DC8E4A4C1B5E6A582DA10C31B219E9670CFC53BB36EBCA29C6DF49E42B1AA34644FF5AA6C290EAC68938236913B8A8F970AF0A9A4FE56B2B441026ADAAA67E1BDB81D9FF9761D76E44CA7AC39B127048EBEDD8A2D41ACD9F559F2D0F575DBA0CAB52F8FE5E6031625DDEA9F363EE4CAEA36F4B6FB71CD079039867D22D089F4502A53B718A504F5CE1D0D16BDCA8860CD20D4F55A3D29EA7F7DB73AED014861A8C8E41EB39E3DAC98757EE6C3235673DEF318675D9E686FE85DEF0A3F38689751195460FF9BC8357191FB7CEB7A3F17C2FB1716301C5AA9550209CF8EFEF4A54E92FB41B1F962751EFE7A0C94B387F1DCD09DFFB76DCBE9B10D9436157C7B6755BD34321C99AB84335792EEC3730ACBD54E88AE9C0BF78072DF12ECD51175D4EC80EA45B2723BA6B9D4F5F7786A6F278078BC9D0FE09B4144FDFAEB86ED68A67609CE4CF3CE14B83D984007DA1986CB8488C0981C1D796B874DD70810601328E3CB1A72AFAC867022CDF07469CDFC1014899FE9BCE106FAFE9F909D4A25A886CF7EBCE107F52B2048A5D0A6ECA24532CBFAB0712B92EF7A2CB50EB15B2F9FD3FB0541A25E2DE4198202E9DB4B36012B2035F4F0FBC15CC6F121ACC19359A49381FDBCF74F46D80661996DBBE0D530B369BE69E0CA180D3CB9543AB8E7BA2C7BAB67C7B02DDA2BC9D070A60655A9FB0F90E6468F7502EFE170871FC0E27D43C3945A292BCF9BC01A3FDDEFD87E4BA46D915D918622998EAF3F64C3434E39B201921811D67F99F964DA3A831D6407F1C8C5311557E6D9FB83D55A03F19E6ADB056A1E965D90D1AD03F9B8588DBDD78FCEF81DC190944AD7FF4B9D1ADCBA06666649E5D8276D513FB7E148F3EBD555E0361A9D204202BE359BF4E5FB7A088C472EB0268323CADC8D5CF4E74BD9DADEF65A0395C26D57CCAD179257BBAA1C4D39B755CD3552C2A5A0C53ABC114AF180781F11AC83E7A5FCF7FD5A977A6223F6D779D2982B1E82CD6936CE4E29A6C5BF88D474F6FB163C6BF54F8C19FD556E368E71776048FDB3BF51E54FA2814DEDDA42FFC48A00516CF304CD8C6171922BAECDCC8779B43B73D8BA39E3C04C22745C61B7D92EEB8BF28C202375BF9B8801408F036685D0F04A11E50969BD235412443C4503560922750CB2BE179E4C9BDA51FC290ECBB5F51BA7CD060F6EDD70CCAC48AAE5E05E070A01874605CFAA6A5844B3C20AB989F6AA03DC0E9C5D046EBE0A819DD770849BB0039A1600AB455F46A0A6E11FBFF35CC06B4A87099B07F7C62997F0FC4BBD46F9A0001F031B58D2C1AC8C1B91ACD3BA2E3970B1AF0D11DB275C898A7A340BF0820F81370E957590F0E513A0D128325BE86C84BC61815BA37136BAEE6F94E0D0350758DF89B25CEC22D36515723C90B697333359AC830D4CA418859A42255163761642B84704DFA6E0C835560BDCE67E1D5424876053BF05B7B8310E0BB46299F3CCD677F8C67596FA268368463870DDD7F06347E8BB28BC7E3EA10ED6BF20A6939225DAEA03BF52D957990EB0A8DFCF403E67D1EA6EE6C48CAD03580883D0086546A8ABA936BD6C837E07EBD971245FAD5213EB5CC73AC6632051F5CBD5FC35F143BD8A30E4CCE9CCD9514626B986F2AA0787CDB0CF797623C41C6786A4D8F39C6749EFC1F06E968692C8B67ED4032200DA35A1C2CF393CF1851A184891F15EBA55560D12EDE777CBF5F95AAA638BE56977A0611E004C82ADB6F95906A3949BDC01683988348D3F5A47BC0BBCE22F7F147C429EB8B9E2FEB013AB6D20562B3E2856D4767AF8F8DEA16FC75815D9D25AC13795BF976E41FF3EC1599F36BD913E7E2D9AB5ABE7FB6FCF2CBA652CA00C3D84DB05C4BCCE42735822825E3DB5580075CEDA00F0F06500413EE11733C8C1B7B14680FA368EED79F118BE06E8373168B83821A2EE66349473CB0C36B16C4A00EBF9247B9E187E8CB4CC2429F3509D91875CEF69AA95552299EC7EB7947D6F1AA41A87B8DFD40F4F3D2465D7D1B26F0C4568448897115C4C3D007EB35270AA60CF47740F193A920291ED247FE5C67780F510FDC23A16DB4D1F56E4DA799EF2245BC2EBACC2D6B5564758F33A81E1BEB3075235AA6B132BDB0EECC4F98604138700D3D36C5B952F84CB50820805E8DD2D46E7ECE54B2EEE4025E158743C0D9422715ABDB76934237BD743ADA2795F5881B1A4139A371156C05830BB656A0D5571B419894D52CAD68E03C64CC33EE70F90819CE89A91CCA0F5ACF1594659DD195C8140E02D0249EE10BAF3C8068B765188627DAC302ABFC5A0B30AAD53F476C8E8A201CB5FBF85055D727894EFB3EF70C991A2D9D6C411923E456F4F8417705F042E890AD69AEFBE5E9EF5C0307FB1A99CE9E99C7830A383AD703503D5D847D703150920C423BC0A2CAE2A8E16F1FF30C932240F5B9239A4A3D4E56AFCCDC3A06E74FD5930B336052F9BB6029AAF9C9718AC62FF8352088CC6833D5F97352B4176463D58CE514D458CC5EE2B99E84CDB24F760EF7C737FA0F762FF4544BFAC078D4494C0BE2769EBB872802590E21E94599257E9452161968B6C2F8FCCB8241A861CBED00D2C38C3438A8A5BBC44C533B9B8BBF6E4F9DF7180BEF52062A465BA266B97021D16BF0FF8E29044F1D13798F47FA12791232E969484F729C699F7DDEFBE97E5ACA8FB900943E2EF04CEF3923DB07B9AD1D2880656BFBB365CFF326834F651A9A72181AE1AF6D9DC7FDBDE84F7D271984F948B8B963567F548E6E00C1648EFA7514E072C603450FACDA79B6827ECCDF9E607E9B2229F4976D5E7A3F3E1415854F2BE29A585B23FEAB97EF227BADC65206F8325FCC362A00AAD7B8187B61BE1AD29970EED3D6434D34AA81D6AFD4AAEA7CC5E74B43433FACE7E078ED44F84008D7CA3BFC44DCFD87E27F728FC2C7CCED887DC03D875305E266FFD83CDC31FBD75D17D94192BF7CE72259C37F83B2F47AD244A77E26B07B014A5F45003A433E1703E850D6BF96129079BDC684EB34081E43BB2020A52FBCEC34C9F035DCA3A66B152849D34B8E5BD492E06FB3F96145C52C56413F68101E609C93DD58362D24F4C849DB5209487FB47CC05A104C6E55E4F275A66ADFF772C84BD9B5651789982205367085DF95EE12B8CCC0CC6E442F98215A5C37952A732DA0E779333E1D35F75DA0F56162400BE8ECDC67F554AFF2A791C7B67859F1BC913F934A62CBFEC106841AAE74E88737E9C2C26305A32F5D7289BF25787C3C43909C175F40B895F3D8E34BACAC56F6406AF5F3F1AC28707099F68D72C841417AFE98F6450A46FDF89DA5909A3F1AD6CD16D6530396D991B6502D137A13BD91ED9A9461BDAA264746619FB4FA93B843580C68AAF80AED82577D16CC4E354F9D90EFE35F0A45ACA7D39831443448091B7308164D49255BC12FAA901E7BB0B98664C58B5DEE3820BC3497F0086B8346885403502886329442C71E51F7BC2759DB3E93F2193F74B5D923C5278D1CB41B6943E7F09FC36937A7E9DFEE6D5F20AA67C416123B66E7BA8E370DBC11755F912B65D16E29E4F3EC01ABAB2CC40BEF9286C7565806815824C3A4BA8BB3430D4DAE5EA46EEFFDE0BEC592EB00776E06D29D76A7A8ED633429574C9F9515C149181B9BE8489840B486C29213964FD8058497424832A4D221964C344AD9731849B654D395C18F2117CC3DF86B8BB37CA65BE7504A3FC27C9EA0EA49893BEA01028751C51826163AA95224ED6FD7152FB0ACB25C38017EA5FB6267CEF654BDABC122319D439B6173DE4538DC5118269CFFDD446351E74811FDEB87D3632C4D2EEF56AC06AD5B6C339F15BCC6898E36DDAF4B6A5ED83C37ED5C0B9E67372C1422302F9089452EEF0AE1D53A81200A44C6856ACADB838015B18932E682A6F7B2FA6CC9943F63469AFC460DAF780A472F31ED748AEB194CDEC5768B1B343AE64AD65985F84B5FDB0C98BB231B86D99DDD9C1668AE4F333450A713AA35FD96614EBA5EB3400681653327698445866C05347C84AC8A265930D486F08727633CE13FA0C844D3821F5727FBB3200AFCD51302E199B80F4447868E425961B19C8D649057B4FEFCF10EFB016670503848A1909868460E6429C6DC725E2FB5A73006F929D8F71DEA23B527AAAD638180E4339E82C9AADA5D06B8ADD5BFB077184FA270854B613A639084E6CBFC6253011D07F8F045CC391DB45CAE21DA014B3D67B9F55E6B04212243577086949CB71C1D7A818B8DBCE818254E7E85899BB1133235518B97D4DFEBEC036BACCDE0F6FD010F687F929EBBCCD7DBDFEB03579397A0C3C4D1E60B103D8EB7EA00000000000A121A242B37404600"; + keygen_signing_kats[2].expected_PK = "58E3563D36F5D0492030B6E5AA317FD727165ED2F494FF5EE45F7E395045C87E4B5709DFA6E7688B11B81F70BA940DFE52729C62AC9C8D56B0A93D2D2EBF4347144EFBFCAE4BF801CFB1BB6570A8A58C27602F44DE8399E1EF6281B84DB2614F4DE383BCF4573F411FF97CA729BD3503FB2F91F5F778581E89A8A44E3C3C3A86893E78F991B7A7FDADBA06C938A8FFB66F58CE9B584FC5DA89190BA94E896784834914A4240BD8143E1A12BB78036168B09D1E4BD274FEB8084EAF2913617D2A1C6BE16B54224C552B7D410A831941EB25AB9ADEF774A1F73FCF1436D428E051C23B2C7B08CA788B5A70768FE2B6B202139177A153867A236A9FC9CEA37F47FB7E2FF30972DE89C0850DD7B38AC0F855BBE607FDCEC0E4A32E7928450EB1A571357AB0E137830379F9BC7AB2D8D25C3C59E56229A4DFB1B28BD9B7D8A0B5FFECFBADF3D24EE4E15CBF34D6E771AEE04CB3EF866083FAE94A7BA0853AF896B1438FFA79079DBA05ED1326479B79EF1B770057907CE068B3A62170936F42DEA21E596710A0975BEBB86D605A8A1A4612E47F9E60678602080C57D07451D6F207DAC1D55444892DFC4783FD0ED05DC61054D1E5E234D11AE559C35EAA3A5F6F2EAC9F908600FF2229F188B3C7C3488C88C891A0016198F6DDC951DEC5BA79D217A7779D18938536B8A049A8E418E1A73B77490A8A11A7FC28F100D3F706EB490AC59E38D39F30BF632B458F4CEF494D5132D6C74864737D05AB0AC85C34C91A19E4BC065EFE5BB4F27718D9FFA0431E5619F447CB8C92111EA5AD8104C57C47E5BA02985D0DFDEB9BC9A6FACAAF57F4BE0BA680BF83308306BA43838F7EB9A8ED5F1384134902DE002705100E6785B2DA943ED591CAD0A085A850838E10AE9889FFC1CD2941E1899E1A26CA56CB7480D260B217798056D35EA62BD55F159CF0FC363A4F325235ACC231BCAE18E89EB70A6970B2EC08DB004961FE951F8ED294D7D68CA6DB402325D054A47D17FF5B38734298B99278273021F165817E7805D581A0B9E40D507CC89D543F7A1B718820B1F8414AD6946B1AF7BC3AC1A520312240C0B499CF6B2742508356F9C366980BB1894D343E1BB24F06EB81CCCF5CAD59158FFD2C0D5E0019A839EF8AAF32292C33E32F6454BC03F7CE05D157BD875210A4276EE7C828291BD5AD5D545AE4711FF0C1332AFC7D716D104344E88BE87124ABD94216405A370AD8097D80879DDE60CB1F70B8F2230CD81D719EBF1C5C1D6EE965A85CB8C9982CF1625BC69B0C89D5D4207AD037DB73A929F024DDCC2306CAFBA0FF819CA596EA988A366901172C153D7D2A467FA1AC7E738F3335C1A2008181A8EF3064227FE7E72DACF26BB28816BBECFB8224167224BD37C5B55BCBA256C9CBE8B18FF4C36EE6A1EF091A714416E91DB1D638592D0FAD1DA51085D36D12B1255884B849B2B6C661A9FACBBBD67EEE7BF27CEF998FEC1CBA2E5EBD5361B429D509EBFC6CB2DDEC67B6DC69884A342D4A6C6D8001E9652A1486B5360A17BBF3A47DE94D1A32A5E2602FAF1A41B5908F67E9832382E87C9D432A3B8B6E230A58EA733F980488491E7043F327160FCB6D34383FEE41FE7DB76D5BA72B3DF23034E648E8ADAF8D53E1F63403A62CAF6AB88CDBDDEC39E9AA4233E3D335DC890DB9454CDFDED997B292562B5B001451729C833627E9FAC08097FDBB64464CE6B4C0D33FE64987373951F2E3E19E7CE119A82C2529C244BA56C7BA3C703CD7C940759403829A505A635B4401AAC9A8A9C76EB375F6069D6C3FB6511E20F1E9F1B40EC3CD47CB90B638329F17E1A3D9CC45769AE2E6CFD9284C11F4B0892BEA676F9B09CAA8E83CE7B7648546FBA7E7A8B9580ECCEA43FE330A0F1520F5933164F524CA22EBA3889A51D184885E515CEF8B35E65DB4DFD90D8D4FA1FBD0F7F0936E55643905AC144175A27F189865C011D8570E2A57392A521C6C38DD7CE0D3FB5FB4C34FDA41645E5BB32DF8100507B8C0B33846D12C5878D5AA05B86E4D83718B5158E67B4D8CEAFEAAD3760599C63A0594B64E21DE4C1734AFC875005B798550F02D1203D94202AF189F140D3729733C276DBD47DBCC0B427CC113A38382E4044B74333D6EFE559FA327F9EB5DA8CFAA99B882EE97280E7A909E4B23A0D35CA8164440B71699D82623BD542ACF364C6D74E4D8D79A0C293629474B5D8A05D3408423A17B9045E9A3A6245D4F123DA541FB8FC8C5BFDC3E6BC508B823DB3EA81D1529558416E720346DEC470E5A7FDF7720893EC139DF5B8A7664ABA3FDE76AEEC0EED445850B5FE0F81FB3D0CB9BFC1432EF66FB8960E4601B50FCF176AAB7AE4C0E9328CBD5ADB4D8DD89DB72B0221382D96C04A8F511659D62FB268D781EB68962D2167806C73916CD66DF16E9CB7A1C25C794953FC3C87326AC3195E6285FE5076C35A56F24E7583E985D51F8EE8CF24AB0E78F2873E426C20B94D15A1E178F22D96C4EC22E90EB07EC066CE4A19BDCD66D03CAC9DD906D9D85C630A7E10F118D83DC7618AFECF90F3CD32D265253A05FEACD7DA610FC868BCF54F0053BB7625CE2E2C35C8A24BC8F3DC294F60DF8F345ACF03B2D8BE69B36E51B49492E8891FC09787527B3BEB02E6B2B69158448AE4507FBED5C3FEB923854656B642CBE0176DEE52B92EAF411B5E1480738476037D52D7AC9C04D909EB7AF11D98BFC66DFFE81F19CE1AAF2E3C646679B834CE0030A6E3AC7BE93027D2D7347B9165F9DEB26CD54F33A90A3AD5FFC88044202208C3D1C97B9668542D6F1DC4E1FD2DB6489392E9ED43FA989E5CCD6CC63E357D516167691AF5558541513B38D8DA32D19133EDF12E1D161C5873BB423B4E52D6B34E97875186D0DF7BB4EF4D05023B19274FB1DF47631F6282A45FDA95A07F8D5B0B0F814AE31CF30947FFA65D940C88CC191B3DD031897F8647D0F8D68C2FB79050F90EDA905673B206E6BDC844875101AED46513041695E9EF151B06AF764BBCCA82B0C93B9D26AB96877B49C9368C972E5D42E2CD41B3F7AB17F8F0B3EB1D0C284C699D9F5523D6C5E2F1E33747E49EB675CCF1B68D2CCDF4C7CAFBD6B1254C141001BDA1E8A9FF6F05C8B914182BC4348655D69D7DE203ABB70242AD8851369AF610CAC22E62A9B300F53ED948BF17D811B6C6B65F2E858E645F95A7F2DD7A9A6D6C2D627BDDA4C852C2AF523F9D03109335639009697FF25A1C67E3100083BD6A741A5B4C8D5567A85820E3D9CC6A7F03A1B7C902C75EF1DC49566A0E3A12671097F086CA024E61DE92F15303B0D6613EDF5FF80A5AF17FE2613437263899D8F66DD19B34A7887B72F416B8DFF7498EE37590DE4B1AA099E9AFE8B78D139238AB3473B60BCC70616F6ADEA0CE912C640D4672C4D68F2DB405ADB6643D7C82EF4F4C95DCE932DC8C96C870B1B7C0B91CF5150EEEBE6973068A3E60C5DE142C96A2DF5495E1CC3B3823608116D0838A5DA3A8AEB40887C08E58A62EA753FA3DDD0BB615646CC2A5B185C7B55A7DDFA9704C4FA0A74A2B1BD579C24AD9110B103A6042DC329CBFC728152533A41C3DD19C7F07F5DE5C863C97DA162E01FAB8E70DC91996897C68A173610B61558F298EF0A540BD762754DABD89B89334A2F95A9861879E0D23DFCA4DB8F04DB6A7E6A3D67"; + + // Iterate through KATs and validate + foreach (keygen_signing_kats[i]) begin + parse_hex_to_array(keygen_signing_kats[i].MSG, kat_MSG); + parse_hex_to_array(keygen_signing_kats[i].SEED, kat_SEED); + parse_hex_to_array(keygen_signing_kats[i].expected_SIG, SIG); + parse_hex_to_array(keygen_signing_kats[i].expected_PK, PK); + + `uvm_info("KAT", $sformatf("Running keygen and signing KAT %0d", i), UVM_LOW); + + // Write SEED to MLDSA_SEED registers + foreach (reg_model.MLDSA_SEED[j]) begin + reg_model.MLDSA_SEED[j].write(status, kat_SEED[j], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE_FAIL", $sformatf("Failed to write MLDSA_SEED[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_WRITE_PASS", $sformatf("Successfully wrote MLDSA_SEED[%0d]: %h", j, kat_SEED[j]), UVM_LOW); + end + end + + // Write MSG to MLDSA_MSG registers + foreach (reg_model.MLDSA_MSG[j]) begin + reg_model.MLDSA_MSG[j].write(status, kat_MSG[j], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE_FAIL", $sformatf("Failed to write MLDSA_MSG[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_WRITE_PASS", $sformatf("Successfully wrote MLDSA_MSG[%0d]: %h", j, kat_MSG[j]), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + valid = 0; + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Read and validate SIG + for (int j = 0; j < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); j++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, j, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ_FAIL", $sformatf("Failed to read MLDSA_SIGNATURE[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_READ_PASS", $sformatf("Successfully read MLDSA_SIGNATURE[%0d]: %h", j, data), UVM_LOW); + end + + if (data !== SIG[j]) begin + `uvm_error("VALIDATION_FAIL", $sformatf("SIG mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, SIG[j], data)); + end else begin + `uvm_info("VALIDATION_PASS", $sformatf("SIG match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW); + end + end + + + + // Read and validate PK + for (int j = 0; j < reg_model.MLDSA_PUBKEY.m_mem.get_size(); j++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, j, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ_FAIL", $sformatf("Failed to read MLDSA_PUBKEY[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_READ_PASS", $sformatf("Successfully read MLDSA_PUBKEY[%0d]: %h", j, data), UVM_LOW); + end + + if (data !== PK[j]) begin + `uvm_error("VALIDATION_FAIL", $sformatf("PK mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, PK[j], data)); + end else begin + `uvm_info("VALIDATION_PASS", $sformatf("PK match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW); + end + end + + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + end + + + `uvm_info("KAT", $sformatf("signing KAT validation completed"), UVM_LOW); + + + endtask + + + + + endclass + + + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_all_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_all_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..de1550e18a6bd44052c90e8f1cd73a4e17600db2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_all_sequence.svh @@ -0,0 +1,492 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_all_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_all_sequence); + + + bit ready; + bit valid; + string output_file; + string input_file; + int fd; + string line; + int value; + // Create a queue to hold the tasks in a randomized order + int order_array[3] = '{0, 1, 2}; // 0: keygen_sequence, 1: keygen_and_signing_sequence, 2: verification_sequence + + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + reg_model.reset(); + + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + + // Shuffle the array to randomize the order + order_array.shuffle(); + `uvm_info("ALL_SEQ", $sformatf("shuffled order is = %p", order_array), UVM_LOW); + + + // Execute tasks in the randomized order + foreach (order_array[i]) begin + case (order_array[i]) + 0: keygen_sequence(); + 1: keygen_and_signing_sequence(); + 2: verification_sequence(); + endcase + end + + endtask + + task verification_sequence(); + output_file = "./keygen_input_for_test.hex"; + input_file = "./keygen_output_for_test.hex"; + data =0; + ready =0; + valid = 0; + + + // --------------------------------------------------------- + // VERIFICATION TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + //========================================================= + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // Writing the SK into the MLDSA_PUBKEY register array + for (int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.write(status, i, PK[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", i, SK[i]), UVM_LOW); + end + end + + //========================================================= + output_file = "./signing_input_for_test.hex"; + input_file = "./signing_ouput_for_test.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 1); // Signature generation cmd + // Generate a random SEED array + foreach (MSG[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MSG data"); + end + MSG[i] = data; + end + write_file(fd, 16, MSG); // Write 64-byte Message to the file + write_file(fd, 1224, SK); // Write 4864-byte Secret Key to the file + $fclose(fd); + $system("./test_dilithium5 signing_input_for_test.hex signing_ouput_for_test.hex"); + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%08x\n", value)); + read_line(fd, 1157, SIG);// Read 4864-byte Signature to the file + SIG[0] = SIG[0] >> 8; + $fclose(fd); + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + reg_model.MLDSA_MSG[i].write(status, MSG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, MSG[i]), UVM_LOW); + end + end + + // Writing the SIGNATURE into the MLDSA_SIGNATURE register array + for (int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.write(status, i, SIG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGNATURE[%0d] written with %0h", i, SIG[i]), UVM_LOW); + end + end + + //========================================================= + + + + data = 'h0000_0003; // verify singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_VERIFY_RES register + foreach (reg_model.MLDSA_VERIFY_RES[i]) begin + reg_model.MLDSA_VERIFY_RES[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_VERIFY_RES[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_VERIFY_RES[%0d]: %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + endtask + + task keygen_sequence(); + data =0; + ready =0; + valid = 0; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + // --------------------------------------------------------- + // KEYGEN TEST + // --------------------------------------------------------- + + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_SEED data"); + end + + reg_model.MLDSA_SEED[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0001; // generate keys + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_PRIVKEY_OUT register + for(int i = 0; i < reg_model.MLDSA_PRIVKEY_OUT.m_mem.get_size(); i++) begin + reg_model.MLDSA_PRIVKEY_OUT.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PRIVKEY_OUT[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PRIVKEY_OUT[%0d]: %0h", i, data), UVM_LOW); + end + end + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + // --------------------------------------------------------- + // KEYGEN TEST IS DONE + // --------------------------------------------------------- + endtask + + task keygen_and_signing_sequence(); + + output_file = "./keygen_input_for_test.hex"; + input_file = "./keygen_output_for_test.hex"; + data =0; + ready =0; + valid = 0; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + //PRE test set up + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + // $system("pwd"); + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // --------------------------------------------------------- + // KEYGEN + SIGNING TEST + // --------------------------------------------------------- + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + + // --------------------------------------------------------- + // KEYGEN and SIGNING TEST IS DONE + // --------------------------------------------------------- + + + endtask + + + + endclass + + + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_early_run_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_early_run_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..5ea4ee37de0cc7986f0c8d269710c0e2e78396b2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_early_run_sequence.svh @@ -0,0 +1,241 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_early_run_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_early_run_sequence); + // Generate a random delay value between 0 and 100 + int unsigned random_delay; + + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + + bit ready; + bit valid; + string output_file = "./keygen_input_for_test.hex"; + string input_file = "./keygen_output_for_test.hex"; + int fd; + string line; + int value; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + //PRE test set up + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + // $system("pwd"); + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // --------------------------------------------------------- + // KEYGEN + SIGNING TEST + // --------------------------------------------------------- + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + //======================================================= + // This is another run before waiting for the completion + // Change the seed and message before it proceeds + //======================================================= + data = 'h0000_0000; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + // Randomize the delay + if (!randomize(random_delay) with { random_delay inside {[0:100]}; }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize delay"); + end else begin + `uvm_info("RANDOM_DELAY", $sformatf("Random delay: %0d cycles", random_delay), UVM_LOW); + end + // Introduce the random delay + #random_delay; // Delay for the random number of clock cycles + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + //================================================ + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + // --------------------------------------------------------- + // KEYGEN TEST IS DONE + // --------------------------------------------------------- + + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_key_gen_and_sign_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_key_gen_and_sign_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..2f97b8b36e87b50ca54c07eaaa4e104b106d9b64 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_key_gen_and_sign_sequence.svh @@ -0,0 +1,186 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_key_gen_and_sign_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_key_gen_and_sign_sequence); + + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + + bit ready; + bit valid; + string output_file = "./keygen_input_for_test.hex"; + string input_file = "./keygen_output_for_test.hex"; + int fd; + string line; + int value; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + //PRE test set up + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + // $system("pwd"); + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // --------------------------------------------------------- + // KEYGEN + SIGNING TEST + // --------------------------------------------------------- + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + // --------------------------------------------------------- + // KEYGEN TEST IS DONE + // --------------------------------------------------------- + + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_key_gen_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_key_gen_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..f3b3e7c8131188db8d8c53cc3b05dcd35e2b38f6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_key_gen_sequence.svh @@ -0,0 +1,125 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_key_gen_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_key_gen_sequence); + + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + + bit ready; + bit valid; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + // --------------------------------------------------------- + // KEYGEN TEST + // --------------------------------------------------------- + + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_SEED data"); + end + + reg_model.MLDSA_SEED[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0001; // generate keys + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_PRIVKEY_OUT register + for(int i = 0; i < reg_model.MLDSA_PRIVKEY_OUT.m_mem.get_size(); i++) begin + reg_model.MLDSA_PRIVKEY_OUT.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PRIVKEY_OUT[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PRIVKEY_OUT[%0d]: %0h", i, data), UVM_LOW); + end + end + // --------------------------------------------------------- + // KEYGEN TEST IS DONE + // --------------------------------------------------------- + + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_reset_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_reset_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..7df92cb0b59b546df4a8eb4dd281ba91c41e6464 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_reset_sequence.svh @@ -0,0 +1,514 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_reset_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_reset_sequence); + + + bit ready; + bit valid; + string output_file; + string input_file; + int fd; + string line; + int value; + // Create a queue to hold the tasks in a randomized order + int order_array[3] = '{0, 1, 2}; // 0: keygen_sequence, 1: keygen_and_signing_sequence, 2: verification_sequence + + static uvm_event ev; + int unsigned random_delay; + + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + + ev = uvm_event_pool::get_global("ev_rst"); + reg_model.reset(); + + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + + // Shuffle the array to randomize the order + order_array.shuffle(); + `uvm_info("ALL_RST_SEQ", $sformatf("shuffled order is = %p", order_array), UVM_LOW); + + + // Execute tasks in the randomized order and assert reset with a random delay + fork + begin + foreach (order_array[i]) begin + case (order_array[i]) + 0: keygen_sequence(); + 1: keygen_and_signing_sequence(); + 2: verification_sequence(); + endcase + end + end + begin + if (!randomize(random_delay) with { random_delay inside {[10:10000]}; }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize delay"); + end else begin + `uvm_info("RANDOM_DELAY", $sformatf("Random delay: %0d cycles", random_delay), UVM_LOW); + end + // Introduce the random delay + #random_delay; // Delay for the random number of clock cycles + ev.trigger(); + `uvm_info("ALL_RST_SEQ", $sformatf("The reset is triggered"), UVM_LOW); + end + join_any + disable fork; + #40000; + + endtask + + task verification_sequence(); + output_file = "./keygen_input_for_test.hex"; + input_file = "./keygen_output_for_test.hex"; + data =0; + ready =0; + valid = 0; + + + // --------------------------------------------------------- + // VERIFICATION TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + //========================================================= + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // Writing the SK into the MLDSA_PUBKEY register array + for (int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.write(status, i, PK[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", i, SK[i]), UVM_LOW); + end + end + + //========================================================= + output_file = "./signing_input_for_test.hex"; + input_file = "./signing_ouput_for_test.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 1); // Signature generation cmd + // Generate a random SEED array + foreach (MSG[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MSG data"); + end + MSG[i] = data; + end + write_file(fd, 16, MSG); // Write 64-byte Message to the file + write_file(fd, 1224, SK); // Write 4864-byte Secret Key to the file + $fclose(fd); + $system("./test_dilithium5 signing_input_for_test.hex signing_ouput_for_test.hex"); + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%08x\n", value)); + read_line(fd, 1157, SIG);// Read 4864-byte Signature to the file + SIG[0] = SIG[0] >> 8; + $fclose(fd); + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + reg_model.MLDSA_MSG[i].write(status, MSG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, MSG[i]), UVM_LOW); + end + end + + // Writing the SIGNATURE into the MLDSA_SIGNATURE register array + for (int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.write(status, i, SIG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGNATURE[%0d] written with %0h", i, SIG[i]), UVM_LOW); + end + end + + //========================================================= + + + + data = 'h0000_0003; // verify singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_VERIFY_RES register + foreach (reg_model.MLDSA_VERIFY_RES[i]) begin + reg_model.MLDSA_VERIFY_RES[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_VERIFY_RES[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_VERIFY_RES[%0d]: %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + endtask + + task keygen_sequence(); + data =0; + ready =0; + valid = 0; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + // --------------------------------------------------------- + // KEYGEN TEST + // --------------------------------------------------------- + + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_SEED data"); + end + + reg_model.MLDSA_SEED[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0001; // generate keys + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_PRIVKEY_OUT register + for(int i = 0; i < reg_model.MLDSA_PRIVKEY_OUT.m_mem.get_size(); i++) begin + reg_model.MLDSA_PRIVKEY_OUT.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PRIVKEY_OUT[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PRIVKEY_OUT[%0d]: %0h", i, data), UVM_LOW); + end + end + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + // --------------------------------------------------------- + // KEYGEN TEST IS DONE + // --------------------------------------------------------- + endtask + + task keygen_and_signing_sequence(); + + output_file = "./keygen_input_for_test.hex"; + input_file = "./keygen_output_for_test.hex"; + data =0; + ready =0; + valid = 0; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + //PRE test set up + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + // $system("pwd"); + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // --------------------------------------------------------- + // KEYGEN + SIGNING TEST + // --------------------------------------------------------- + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + + // --------------------------------------------------------- + // KEYGEN and SIGNING TEST IS DONE + // --------------------------------------------------------- + + + endtask + + + + endclass + + + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_sign_gen_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_sign_gen_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..a318edd3692f58a01a305b1c4e173d1b416ea659 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_sign_gen_sequence.svh @@ -0,0 +1,173 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_sign_gen_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_sign_gen_sequence); + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + bit ready; + bit valid; + string output_file = "./keygen_input_for_test.hex"; + string input_file = "./keygen_output_for_test.hex"; + int fd; + string line; + int value; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + // --------------------------------------------------------- + // SIGNING TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end +//========================================================= + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // Writing the SK into the MLDSA_PRIVKEY_IN register array + for (int i = 0; i < reg_model.MLDSA_PRIVKEY_IN.m_mem.get_size(); i++) begin + reg_model.MLDSA_PRIVKEY_IN.m_mem.write(status, i, SK[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PRIVKEY_IN[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PRIVKEY_IN[%0d] written with %0h", i, SK[i]), UVM_LOW); + end + end + +//========================================================= + + + data = 'h0000_0002; // generate singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + // --------------------------------------------------------- + // SIGNING TEST IS DONE + // --------------------------------------------------------- + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_verif_fail_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_verif_fail_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..b4bef5a4c6301517d318aedf8fb57f9abea54a03 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_verif_fail_sequence.svh @@ -0,0 +1,270 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_verif_fail_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_verif_fail_sequence); + + // Members to control randomized failure + int fail_register; // 0: PUBKEY, 1: MSG, 2: SIGNATURE + int fail_index; // Index of the word to modify + int fail_bit; // Bit position to modify + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + bit ready; + bit valid; + string output_file = "./keygen_input_for_test.hex"; + string input_file = "./keygen_output_for_test.hex"; + int fd; + string line; + int value; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + // Randomize the failure parameters + if (!randomize(fail_register, fail_bit) with { + fail_register inside {[0:2]}; // Randomly select PUBKEY, MSG, or SIGNATURE + fail_bit inside {[0:31]}; // Bit position (0 to 31) + }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize failure parameters"); + end else begin + `uvm_info("FAIL_TEST_SEQ", $sformatf("Failing register: %0d, bit: %0d", fail_register, fail_bit), UVM_LOW); + if (fail_register == 0 && !randomize(fail_index) with { + fail_index inside {[0:647]}; // Assuming max index is 647 for PUBKEY + }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize failure fail_index parameter for PK"); + end + else if (fail_register == 1 && !randomize(fail_index) with { + fail_index inside {[0:15]}; // Assuming max index is 15 for PUBKEY + }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize failure fail_index parameter for MSG"); + end + else if (fail_register == 2 && !randomize(fail_index) with { + fail_index inside {[0:1156]}; // Assuming max index is 1156 for PUBKEY + }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize failure fail_index parameter for MSG"); + end + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + // --------------------------------------------------------- + // SIGNING TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + +//========================================================= + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // Writing the SK into the MLDSA_PUBKEY register array + for (int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.write(status, i, PK[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", i, PK[i]), UVM_LOW); + end + end + +//========================================================= + output_file = "./signing_input_for_test.hex"; + input_file = "./signing_ouput_for_test.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 1); // Signature generation cmd + // Generate a random SEED array + foreach (MSG[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MSG data"); + end + MSG[i] = data; + end + write_file(fd, 16, MSG); // Write 64-byte Message to the file + write_file(fd, 1224, SK); // Write 4864-byte Secret Key to the file + $fclose(fd); + $system("./test_dilithium5 signing_input_for_test.hex signing_ouput_for_test.hex"); + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%08x\n", value)); + read_line(fd, 1157, SIG);// Read 4864-byte Signature to the file + SIG[0] = SIG[0] >> 8; + $fclose(fd); + + // This is a new file writes with the correct input sets for the predictor + + output_file = "./verif_failure_input_test.hex"; + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 2); // Signature generation cmd + write_file_without_newline(fd, 1157, SIG); + $fwrite(fd, "%02X%02X%02X", SIG[0][7:0],SIG[0][15:8],SIG[0][23:16]); + write_file(fd, 16, MSG); // Write 64-byte message to the file + write_file(fd, 648, PK); // Write 2592-byte Public Key to the file + $fclose(fd); + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + if (fail_register == 1 && i == fail_index) begin + MSG[i] ^= (1 << fail_bit); // Flip the selected bit + end + reg_model.MLDSA_MSG[i].write(status, MSG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, MSG[i]), UVM_LOW); + end + end + + // Writing the SIGNATURE into the MLDSA_SIGNATURE register array + for (int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + if (fail_register == 2 && i == fail_index) begin + SIG[i] ^= (1 << fail_bit); // Flip the selected bit + end + reg_model.MLDSA_SIGNATURE.m_mem.write(status, i, SIG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGNATURE[%0d] written with %0h", i, SIG[i]), UVM_LOW); + end + end + + if (fail_register == 0) begin + PK[fail_index] ^= (1 << fail_bit); // Flip the selected bit + reg_model.MLDSA_PUBKEY.m_mem.write(status, fail_index, PK[fail_index], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", fail_index)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", fail_index, PK[fail_index]), UVM_LOW); + end + end + +//========================================================= + + + + data = 'h0000_0003; // verify singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_VERIFY_RES register + foreach (reg_model.MLDSA_VERIFY_RES[i]) begin + reg_model.MLDSA_VERIFY_RES[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_VERIFY_RES[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_VERIFY_RES[%0d]: %0h", i, data), UVM_LOW); + end + end + // --------------------------------------------------------- + // VERIFIACTION FAILURE TEST IS DONE + // --------------------------------------------------------- + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_verif_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_verif_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..93178cef155724301e20b381f1f4155e473af134 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_verif_sequence.svh @@ -0,0 +1,208 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_verif_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_verif_sequence); + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + bit ready; + bit valid; + string output_file = "./keygen_input_for_test.hex"; + string input_file = "./keygen_output_for_test.hex"; + int fd; + string line; + int value; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + // --------------------------------------------------------- + // SIGNING TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + +//========================================================= + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // Writing the SK into the MLDSA_PUBKEY register array + for (int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.write(status, i, PK[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", i, SK[i]), UVM_LOW); + end + end + +//========================================================= + output_file = "./signing_input_for_test.hex"; + input_file = "./signing_ouput_for_test.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 1); // Signature generation cmd + // Generate a random SEED array + foreach (MSG[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MSG data"); + end + MSG[i] = data; + end + write_file(fd, 16, MSG); // Write 64-byte Message to the file + write_file(fd, 1224, SK); // Write 4864-byte Secret Key to the file + $fclose(fd); + $system("./test_dilithium5 signing_input_for_test.hex signing_ouput_for_test.hex"); + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%08x\n", value)); + read_line(fd, 1157, SIG);// Read 4864-byte Signature to the file + SIG[0] = SIG[0] >> 8; + $fclose(fd); + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + reg_model.MLDSA_MSG[i].write(status, MSG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, MSG[i]), UVM_LOW); + end + end + + // Writing the SIGNATURE into the MLDSA_SIGNATURE register array + for (int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.write(status, i, SIG[i], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGNATURE[%0d] written with %0h", i, SIG[i]), UVM_LOW); + end + end + +//========================================================= + + + + data = 'h0000_0003; // verify singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_VERIFY_RES register + foreach (reg_model.MLDSA_VERIFY_RES[i]) begin + reg_model.MLDSA_VERIFY_RES[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_VERIFY_RES[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_VERIFY_RES[%0d]: %0h", i, data), UVM_LOW); + end + end + // --------------------------------------------------------- + // VERIFIACTION TEST IS DONE + // --------------------------------------------------------- + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_zeroize_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_zeroize_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..777eee53f2084ec5c78c7ca0b5566743cffa47d0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_randomized_zeroize_sequence.svh @@ -0,0 +1,381 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_zeroize_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_randomized_zeroize_sequence); + // Generate a random delay value between 0 and 100 + int unsigned random_delay; + + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + + bit ready; + bit valid; + string output_file = "./keygen_input_for_test.hex"; + string input_file = "./keygen_output_for_test.hex"; + int fd; + string line; + int value; + reg_model.reset(); + data =0; + ready =0; + valid = 0; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + //PRE test set up + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + // $system("pwd"); + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + // --------------------------------------------------------- + // KEYGEN + SIGNING but Zeroization activated TEST + // --------------------------------------------------------- + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + //======================================================= + // This is the zeroization before waiting for the completion + //======================================================= + data = 'h0000_0000; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + // Randomize the delay + if (!randomize(random_delay) with { random_delay inside {[0:100]}; }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize delay"); + end else begin + `uvm_info("RANDOM_DELAY", $sformatf("Random delay: %0d cycles", random_delay), UVM_LOW); + end + // Introduce the random delay + #random_delay; // Delay for the random number of clock cycles + data = 'h0000_0008; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + //================================================ + + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + //======================================================= + // The zeroization is done + //======================================================= + + // Run keygen plus signing now and get the results + + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + // Generate a random SEED array + foreach (SEED[i]) begin + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize SEED data"); + end + SEED[i] = data; + end + // Write the KeyGen command and the SEED array to the file + $fwrite(fd, "%02X\n", 0); // KeyGen command + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // Execute the key generation process + // $system("pwd"); + $system("./test_dilithium5 keygen_input_for_test.hex keygen_output_for_test.hex"); + + // Open the generated file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + // Skip the two lines (KeyGen command and PK in output) + void'($fgets(line, fd)); + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + // Read the secret key (SK) from the file into the SK array + read_line(fd, 1224, SK); + $fclose(fd); + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + reg_model.MLDSA_SEED[i].write(status, SEED[i], UVM_FRONTDOOR, reg_model.default_map, this); + + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, SEED[i]), UVM_LOW); + end + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + // Randomize the data before writing + if (!this.randomize(data)) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize MLDSA_MSG data"); + end + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0004; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + + //======================================================= + // The keygen and signing operation is done + //======================================================= + + + + //======================================================= + // Zeroize again with a random delay + //======================================================= + + // Randomize the delay + if (!randomize(random_delay) with { random_delay inside {[0:100]}; }) begin + `uvm_error("RANDOMIZE_FAIL", "Failed to randomize delay"); + end else begin + `uvm_info("RANDOM_DELAY", $sformatf("Random delay: %0d cycles", random_delay), UVM_LOW); + end + // Introduce the random delay + #random_delay; // Delay for the random number of clock cycles + data = 'h0000_0008; // Perform signing operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + //================================================ + + + // Reading MLDSA_PUBKEY register + for(int i = 0; i < reg_model.MLDSA_PUBKEY.m_mem.get_size(); i++) begin + reg_model.MLDSA_PUBKEY.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + end + end + + // Reading MLDSA_SIGNATURE register + for(int i = 0; i < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); i++) begin + reg_model.MLDSA_SIGNATURE.m_mem.read(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + + // --------------------------------------------------------- + // ZEROIZE TEST IS DONE + // --------------------------------------------------------- + + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_verif_KATs_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_verif_KATs_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..d01d3ba72530707c911f4f6a73022059d6114531 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/ML_DSA_verif_KATs_sequence.svh @@ -0,0 +1,180 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef struct { + string MSG; // Input MSG + string SIG; // Input SIG + string PK; // Input PK + string expected_RES; // Expected Signature +} verif_kat_t; + +class ML_DSA_verif_KATs_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(ML_DSA_verif_KATs_sequence); + + + // KAT arrays + verif_kat_t verif_kats[]; + bit [31:0] kat_MSG []; + bit [31:0] kat_SIG []; + bit [31:0] kat_PK []; + bit [31:0] VERIFY_RES []; + bit ready; + bit valid; + int value; + + + function new(string name = ""); + super.new(name); + verif_kats = new[3]; + kat_MSG = new[16]; + kat_SIG = new[1157]; + kat_PK = new[648]; + VERIFY_RES = new[16]; + endfunction + + virtual task body(); + reg_model.reset(); + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + + // signing KATs + verif_kats[0].MSG = "afbdf91c942b5eb73b7cc474e53c05213fa41e7a2a826c58812f3065e7a289a6bee9169d145d9c81fbab6bbf7cb65e26d31d734e755d7abab5db81ed9290fb80"; + verif_kats[0].SIG = "89E8DA09EDD3600C15A06D5B5CBCA92CADF08F4313D0C0E2B23E24B329EEBD1D81DE6DEAE3F36797A494BA2121E0A274C3988770902E2CB325B79FD1C6ED2197A6386D50174548C5EAC449A1166F864DCC6A72C69CE883B783496A8FB7D7CAC3114996337082E3D45913F54151184FAF4CC4A45E71055E82E1F07279006278D00F427C1385800609418D46A6AC9EFC88E65C6532F2951B4C54A3EBAC4ABD047E9DBAD4ACBF9F1B67F53CDAE7C95D59CDE964C7F1644B2F2A2F2F3E1F8AEAEFE0FE7F6BF620E04ECFD0C6409FABFC71055B31BFC124441C388DF7B277DFF16EAAAD5985807DA361007E3163646F44541A623271B24ADB351CF68BAC7EBECF63B6C0ADDCF80EE0440BD7946E95F188C2DEC36D329524DC1B46738FB3FF0DA06FD3944248422394569D3CFA33E65CAB3E8C61DA6256DD396995BDEB151A5B7CDF429914F35FFA6B796807D70426715AF96B379DAE930D51A0717817CBDA0EF43F0EA2BEDE04D9FD2C72870F2B812818333C5EA491C344F4D359EFFC91984809A74E431DFEB05EFA1BA66924E4DEBA91E970A3ACBB2B34E272092E18C4FF4CCB7302C0067CE923C68C233AAE99B7090B7038CEFA82AB19A34B94D21FC70A8AEDBF26C8F2A4A4B74126E3A5E488579D639ED3881308E25143C2DA100395CC9F34CBFBE6770AE3D48C52AA2B9E1E1FAE2F6518E1BA8FEE95A029F72385FCBF1E1FE3E3AC96EDAF345104480F4CB407241B52AD07D896F73A12DD5123402E7F7D3E1B6363003B2388A351707836936A99FC26E5616583C101AB886C4A4B519145509DEDFD6C0BB3764B0BB3DF86DBF87437232C63881A74111058A5A415CB0708A20DC180391813D77D9F9F6E4ECB51771C101B2BE44701676D492E5318E995E6A8904657958A8AD1B11D6DEBA66DBD20D2884E23818609571EE5908698123B2043D813F1C61C6C758CBF58EEA1D3D3C7A01FEDE5E782BCF5DDB9A1CDA755EC0606D4493903E6DF27AA32791BE881276FE47A562A4FAC5335CC2BD21EBD488DBED137DFD288C87D4B56EED30B9A34AB295061EEEB0EE5E87112B615E010EA04DD29A3A0EE4FFD083E4A67DD320269D7EFE2AFB71E008279D28ECE96FC8274666925A0D3B42E58E4EFB621F3FDF1EF9987FD3A344FC496D0AFF92EE7216901559685E128B229A9D1561179DBAA0E08C086AB81120966875901295419E93FF5A73ABBCA65BBADB38AA627FE34CA63F8A0EE33DBDF7D2601FBD47A703786DF040D84EE16A3C78304EC38E4C9970129FF249353BE188CCC35F68D7BAB001A57734AC93CFBB85E48F6068AFA5F5C3897B3D219470283856416E1E256D526859DF5F440C6EAB7A86152429CD9719C132D6FD9926B3C69C55A0153B938ABCD31112C82A75BEF9A8B74B8316D61EF73D357B1F541B79B1A7E13FBDC019317A5FB76C8DC68BAFA3B8CCA73832178D01A298AFF65CABAAF18147507942EC8D9A15F2559A31872BC900D4685D2A6E279ED7B1220ED9DB5E3297CA4CA50179D93F07691B13B25C687942C1E2B50D78A4BD26D1912789247F1BAA82835852530E9A7CCAD49C1706C37A2E5262A1056C694AEB20D37AE7672051A6D1896D8E73C50F50F2A8675CFB6D35A7D68BE91E932CC51D85CA78560D135ABFB8EB36F980AE48826B932CC2AC2C8C1F3C1820ACEB3BB3E3084F19527D3A201C01683389E71ACC79AC5843AB2028B56897B90577BB31BDE84E6EBC26B88B151CC778A6B32EE9A2F6FE05842D632E709D409DD2B2D44FFDBCA91370A8E256920E71F8DF25B802766BEC7D614F035CA16045ED88E3FEC2D8DFB463F9FB0CBD7198F369306D352014777D2552651416FE35ACDA5622057CEC2787BAE8803ED784D71D661E2FEC67ED0963BC98FD5207C8640FCB132C63E89E648D01CDDBE942698A0B43E104D326608A021B0DD8F032FD915C34E0233CB673162B657D1FA00B25FEE1B2F14A3BB00E401A3CEAAD6F73D754CF4E1B6F890E82BD5C696A235ACF5FCFF26361B44151144DB231EDC51E46612AE8E4C6FA0C65C5113360E0F4C0E160A4960014D4785FE5ACCB1A4BFC20B966CD291F1E67B46CE04D4E41FC1AC2E13CABB8980114546825D2D4E7386CB7E6766911D23CE07A448921E7F6C79E3E7BA565D3977D46ED87C3A9FD3AB0C77ECBE8446819A498A146674B8670B1FFAFEBBD81AAFA6CDA9458129E3AF92D33EE0A591985828B3D1740C21FDE5E08DFCDD5CF0CFD5919EDF512FFAFC4E3EB85529DC38189600F3FA518710F0EDA7A0589FD72C77C7326F50C0F21995DA9862A7D2B9205B8701A0ED6E92E8057913AA9090433A08789912003BB950863C4CC9078978BD390C2B5DD3D54A3BB6F03CC3E2D8F218D0FD439DA10BB3524EA3948D095FFD3A8CA08AAE309C751BC2C1BB8C5C706C01AC1A9302CCD5AA9C43FA387AA7C23EF1E07E416E8C8670C81FFF314E554EBA6041D55DEB1B43D6A9180EE59CD68BE664AAA1EB13882D23FAF98191DFF594B661DBFE1CE59DE1AAE0448CE62A6E2848C05224ABBBFC78C7BEAB750DD012E16F3123B8BCE1889E1CFFA43829095774BC312C8C7704797531D020BE29E9B4A4637147E3C5B9A3A6D67B141B4CE0375BFC3E1A26B84F60100330600B10596843A4F17A861E4623C83A75C89259C1AFAE640D829CAAE9A0EE7D82E98503534C41155C12033F98510DE87086C0DBE69AD58DD635DAAFCDBB4C0AE4C915838AFEEF4F24367AD1B7D0973C30283ACD3E80BF236B56AAACB4DA8CA9CC812F62AEDF7E5EE1FE6A50D5AF849B8EAF90CDCD9623DE474B248EC1F3A3E3230EED1484A38CE390C9838D1FF542D7F34BA3A94073121D6913349F38A7BA4129A2620455D9EA4426C7B97A1550F14FB00066A5E05C7B7E8A6D5FAF7411FEB18EF65E85226FBA332EEA7148AB4076C2D53CD231EF6EE8FC5A79C36F8C8D1BE1AB4DFACE179A544AD4C8ABF375D797A82BC99414ED072A3B361DBADFE0E4E93D2E9EC8D0C21E4B7AB04D332608552D30474ED438E6A7F0DB05D4A649606DE526AE30FD5A1E76B909463852D9D4C1071AD6D1A1D5E1E7F5248D5A291E55A9C68E38F5D19138C874633D03B02A3C1BD4B46CF42F75884ECD7D7104F8894B22A80E5C3EBB8853818440F2604F810A17498DC11BEA29061EDF458A9EC1C5CAC28418758A11C3C0587B42F4ED2B4E43B9A1531F9FF2C02B8B2F65F49DD5D7EBEC992F2F6D78100FB74FFC6A58A9CE70136BF13127ECE08E3B732EAECEFA0868A26418B7E44ADE984D67FBC096DF8373D26DB165280F862AFCF8F51AD65722D911C8BC0155BF699418470423453EDACCCD53C586A916BE3C82A41D7350221680D6BD5F7D44F1DF59D2363902D427C0D4B45E0905AE48877B0D97E67B6004F0A9121914B8412B820D909BC25FDB7008B0A4853F16890E7D3E877056D37B356E44B0FF209E937D0F6A1D6C8568F659DE335328CC8C6C8B20C4525445E05966F06B92BEBA05CA68E7A0EF59F2B4F02EF2FEF7F5D07401CD0DE879597D12430F14E1BBA4E18EF55400085FCA175B4C02AADB6E5FE8E184439F68D7AC734DC7A97D68242C2068B1D34C617C98A2D8667CD34F8818494130582C57A4D97B75C552D6D2B29762BADABF9E775E1D55BE2FDA872F5CDE3C8EBC560B7DCA032DF15D56E300E5CDC823E8AEB3C35CA51A14A2F59A4A566AD1272BD0A766595721606282F29C7B06416B0AB096C4C591F9A2D495F3E3337D108C7AD2794F4051B41919249CDE0E0761F0CCCFF6BE5DD5FCA46C37A604B02E64F92D5AC2BC00BA6F1AD15C1FE1FF07FD6444947F3C944ED1200188C3228254EFA276A58D7F7165F494A89341015CA8D9F03F19BC6DFF099310009531E1ABE16F21C0F9C8CEE5491F8FEE37669D6953967C6889B8E02E0C3B8BF8BDBC755C9B0964F736AD2F5C2F5377324AB4656ECA8A8541C24F81BE146C72F717A9A841C7480C1A7BEDFD05D98576E121AE3C5C9C4AE092C688D75178170037ACADB2F44CA33E7975B63A096CC059361D4CBB5FED8501DFFBCC6B7F1ACEE4024A76109022A71B09DF6DB8EC31DDC84AF9120125A3CE044E514D28C653068CD4E6BBCE5A059A36263EFD7E70B56BC5D4D14142545062CC0FBB391EB8792F4AE0FB9B01CD7C73AB3CCE203FDCBF0D76C7AF2FFABC0B44184D7360D84CA9D29CB6459603809B09D73D009B898015F707E83D56F53C31F4F7CC1B160E874C2144432844911341B34BC16730D76F918B025308CA11A05389E2266E007777EA67A71A61471CAD0F7F0155C12BD01E1428280B0707664B2DCFFF2D782F3E82FE689FAFE91784B835C892BB28D0642B6824654E4B3A6B85D732B701C7939A75CE8E96D696E39F52AF214D1935DA31FC30E84290433101AD901EBF38FB6D59E6C992F517DBD91BA6E3BCFB01F7D04D7BBCE40A0A87363860FF616E4DCE34AB497D02199C5156BE5A44D4657B9143E1E11EE3DFD9E5526E4371AAED852F036EBD96F8B51BF87894017CDB0A4A706B2C5BF8F639D5CEC4706006B0DE3A1F10C39D953950D22821DCFCA96BB02D421F3B92CEA8815C4A7A6715918223DAB401936FE545EE94DE85B656B225532736DEC004E552696ECC8923E17A9A80B136C2B8A47890EE06FCB11DBAE067C93CADF37F3CB5BEDD0A0BCAEA0FCDF6868B6E83656D8C2DDAAC8C575630ED4F3456566951EE6DE25B487B6422EC2BA8EFB2738D6BF537B669DC132C8827FC3590CDD36C4B3ED0F1FEFF09C08191B1E553422560A502C21470050BEB5826165403B94D5F19B01B17723B75607403796B1E194E879D255BE6A34104D8AEBCD85AA23E7A644EE704C7C1436701A49364D04A88A6366B3206946E914DB711DEB99A764CC59A679F1D4DFA556925353C15DD0ACF91D66625944DF48F5071B3BA586803B61C2E5A01EA56683A88937A4C08A8CF57142A3C4A699CC07F489532761BE4CF2E7488DB1FC66CB84BA52A4CDCD4BD6187D947371DB2DCB11828F4ED76CC053DA3FC3E9CD50FB71970CE942881AC884F92BF9F23A18161FCD34E2F088752E93A1AFFC8D512B808287A0AF1691F7B1A7CD5C141172B2433FCE9B5EA44D73A5E5C2FA9C01F1FB3853CA6949D4171C8A073C0B8985475D41DD332A5FC476D9F1BBA2FA67D5604C3ED57246F53B0A778DE46AD8E83053A68B97BDF78581E2397C2FEB6E9CF241651C4E309E17D56F69F30530FA3A033E9391DDC2285AF27C438147B6241E34F4597D32411626E712909AB595234730B37A31FEC01FE0C21F5940EEE603BA081B7C01236393FD3B1B1B4C1690B0A1372BD1996F66EC65A23F33979438F70C9AD5BC51713FCC77CF4DE1304644860A70F7A44EEA171721BB681A9F5DE3B178C5F1B0EE934E28D6E0A4013C97DE45ECF41FE23D2FCE83E457A5ED12FC5DA034CC4615D06934D37F58257CDC9999F3AA3DA4AA45F8F61D5BD818788FEF8D04C26BCBFF07B865C000D7A56B8105F721CF12E2183FF0FC0857D5EEEEF0AB141A3089FBA9E9E4886B2C7FFDFC4D95A44FB3541527F7165F14E0B09DC9BF51254E06D157ED41E4D9CAADDE0D02F0A5A659939AF3140EC87D79872BB91ADBADF321C005E40B7AA96D9CF8C2E78546F04F590F648C1E93FF8092BC71CE26D6ACA4BC1293781B36AB7DBF5A65B133FDDA471D3C784E31A775349FAE7C0F4286D14AC942DDAE0AE894B940187F34D9C95FC014EA5920FE4D3C797D0E92D3187992A1493544139D87497FC3B08F7D86B7D60D66C4E6FAC5C88816A2EEF0B6724D6E46BE1743DF6AD564BCFD763F46271185195CF3847161DD0F806507F6E2673FDF2A3ED3DCD3FF60C4DD2320229EC396886D6653A39166C4C53A2D7E494855F3026C9536E95452C2DA77C5932A8991CE2B749DF5EA39A72FD3619013550E68D0378A666F03D36959C7A811328A3A266F415AD0529613DA43882BD0BC1D8EFCB566AFCBE32E0F0182653A15A3201DBC23BAA4947D033EA45E01FB77BAAF710F0A0417261A9DC1076FD8E5CC6D03FFDBA8229B978E89228409FC103BC9D87FF0351FD31C573B5663C9870132EA0555F233FF95F5C6FEDD9462A4245EF0F2578E294BF608EEC39BB275C192988C732776EFA6A240B63EEAB94D308D25BB2493B199F8E62868AF1493BF8513EC7F3C01F9A8ACE1F6D3187695DE3277A0B43957961D601B5DEC84647ADEA7FB37C1A009A8ECD29C745D2CEA2FF0839B544D5E9FB20541A7E54F9CD6735083EB029373CE44A911A818156EEB8C83F5C722E217E06E664A36DE2D7667A4C5E402AB487608075B851840C712EB6E281F2DF2F74C783FFA29301899BC7F8ABA0E99E1BF8825D5AAAE02180A79E43B96D40738ED2FA281250168151F9CF73EF2B56A2B3B33D0B7B62B439F603F254F6C4C96E1F96CB10224F18EAEF81FB08D870352375B9F94E6A9E060C282B475D617F96A4E9545676192538516279CDD8DCFE0558B1C2F1144D5E616D9DA9BEEE97A0A1A40000000000000000000000000000000000000000000000000000040712151F242D3100"; + verif_kats[0].PK = "75a8f4c956c0d7da6c7fe78fb03e722ed1fc4f2a5e2449600e616f61995a4a88babd92571c6802539c86367bac5d6c33ee7ad2f47331681daa2ecd3272a07c9888ef4fb3d7d7b5534d62d48db4e7aab9a3dcb6732cf5959d5acd4b258fd9aad057598db1a8503dd8f788f9b551423a93dec204c8a67890b533bdad3544e65dd2da8876e6803e5d77c6fa1f1c232ac0328c69650c63e23fd724496b95236b585f76fd7c949b0204ddf23e55c883c88b34a55b2d3b377de4122f9cbe78143efc7ab9d23b9867f5f939df336a025653b525d7f23586f82c3aad578883eddab3868a08115bd0c313ad31ff44f4f6b855025e5ff68b72c9d353ce54194914b266ef4d3f1f8740142a53d1c27bf5ef2d7e88402c565079247080ae0d07d6d7568fb887fe18bcfd8261ed2ef494c18a8e6b8a209781a4cd2cd32cf61ea4474e74aa20a22da5fd0b4955db1e2b9a6c3c38072c9042d2744a5810f3c3e9645b84dbfa7891f5bc4e41fddd2df1bacd84ae80bee0502cacac547fd6521aefcb4b95b58bcc194c6b5a4e5214018b6f2ba80f21122004ed559a86776826f3d777c25a283eada7bd2004b88e19d7b15fea24a153c08f0936e896ea2ed175c07a2cd40081d147087f8e7e8b56bd438f7dac54ba3a2d72556bacab5c6a6c8d632acf6e411e1e9299f2a2fd4c6519ac2262abe3874871039d177bffe6d167821f05e46393b1fcd5a2ce192183ff741b185280a379840c75b9ec706c1617db9224958572bef0158b000f6c5bce5066c4e311509efb92437c865ef4f6c2e8493a26ed8b2fd99adfc161a9059dff794ed52af6c83b7894fb2c79265468c230cddf36bfe6ebaf11463f0ef4ccc789ef23eecf3933638ac5ed3bfdc0122b791efd23d7c239bf969b886ec3626cf86b9d012c2809ea6ba63a4f8e77cbadb40f1a8b7c2b7ac21c00d3ac87d98e61ce6691a7f5b2351d80d8ed30b5a9006153a4878e517569f192f94f84bb9a4f35a45bb41ee126d93c19db43a981c57377dc9bce867a76f2c49d0d9e8801a1726c8eeb70f7ebdfac83e46a9cc2718502e590a9d70e82a9ccf56d33526c8e2575172c72e4259aa639999175827b93803c5b43e50c8833a80cc52a11b2c959b5572dea35924e12337bed0e92a4efda31e1e161b2b57b4828e9d95685e7db7ac795186a8b966f90caf876f405f1ee9d6459fbb2740783870fe6a5c3fe8036ed647bf544b88958c4f263409f56a61588d7d8bbb4073e7fd7c3c9e25006c97bc180435054414cefef80d77dd7dc81099f4bf565d4e891bd86368669faecd31f1f1a246c969838432715309aa45e8ed861517c13ac94602933a2cd3bfa06735e62c4beb652cb122579488ba8530bb5878787495cad696d7c5e1de65a66e4fbeeafaa259768ea2608ed25b5586ee1c06ceacd5510e4167f7aa4dbac15c68a2a71066096eb8f0fe6ae7345c2434a87d28bec35e506be01af27edf60752de9c9014b22de55778ac5010c780e79fcc357aa29326ec748bcc593e62e6dbc51ffb3f282033e8935d8ef7efff37ed6d1cdf5a204558773a1b8c7ecb87949013bdffd6e8e05c817e86dfb7b6298619870fe73e2b60992209207d94b856fd56f4c39ad937def57aeea0c832f54bf408755f3988a39ef871335bdc2169f675c95ea2658266e29e39fe97c0c2093e8a2eaa9db75a6a4fee8f6889be3a606c79956c24f3b560cce1c37161453868d9bbab0a87d85375126b6dc3e0d1f67b32a0006a8d3c705df2c6b03ba0fa2b9634c3b0869552a0dac3b21ecc8ba17b341c2210d0a23b5fd68bb1335ac96c3ef3701e0a2acd3890a4aebc908bc063bbf2ef3d50cf0f8da48f7ddeb86f9d773e544c70447041076e99c93db9d39780df774da35a0163da3ea50f17a69a214410736015a4abf71f43083324951fad485ebaf55de945f8c6efc3e8be26917e5a296050405a97fecbfd2625fc676ad1a9145bb8a9c1f1b3a46519f77da83c44d2861cad6a56ab01bf84f7709f0f5270ec550f6691c47e6b18f4b5b884118fd4af03d30460119322eaef583a15f00a561afc4985393ad53b681d41d469790a24bdc6056eb92dce833ab33581e08267cefbbc20676192a7608fb7e3422801d9351843b476263c0d1d5442613d6eb9924662b20bc213ca335a52a5f3cbcb8fca9d9164170c8928dd5d2eaf9290d82ea8ff7299e772de20567c79d6ebae9bf5834cad8d55acca5e9b22e9cd0942dd262f06d2b21c248838d8b76cac91e98fa4d5369fe26a609c2e6547c29137d45e4f4b08724df786511fbd75eb72dc72db2ff0b8d90461eead262feb1908f0605cf60b5f48733e3ee31b12eda1c220eecfca7160eae73da742aaa3408149ee255985ed681d733ab49771bbd77e344976ac45556a83cf5ea3a557d6f2d854af1396fe62bf2a582f3a252b9cbb00aff5e7a5daa0b44d3355374c70bc6117dbcf67cde2c025275a49105bf0d464b554761c8e0340fccfb2993728381f0a015dcc10d7a26970671ff41c6c12cff6e71e16a3763964042ab8ee7a1d9dd7dc8c73229061da4cf614d2f5336628ff9dc92a1a5fd33240ef00575d5008a2f1a632b7bb843ab18113b1f0975b6eca7abb6c18c2d17c9542b8ff6e99c186fcdaf6f0ab62dd37646277ad482d7f066c3c7678d5a9acc3c162c8ad3ea326ebcdd518240a6040b717dbe698f6e0e49f35741289a61f143bd0c2f33584733ea05c0f60321ace1874f0c2ff2730f729b9b20fcf64994719b95c0126af36e379afb8940ea28f69a43602a1009181547aa7f1c6b59bdfb5f010fba702e193d67af6a2d0277f474e504280eb8c565afe7696d8fed00cdd560536ea3959d2d7d1dbd702cd325ccde51cdf0c1af06b62089ceb523ab942a50a36e67c786b83f93c29b515cb56af23c5412c1b2ff1be9e01b53b6325c54f3e7fa5fb3f2d167bfe6f7aae10cd499486c74f26e76e8fc18e7fe42b09757222dddbaa0d97f88aa1f9fc0cf1c9f781b28abd0a7eb9334646829fddfc9f505ecd9bc8eddac160366bbc04aa2e62a7a209594a87f9e121dfe961da3adc7764dd63844b4fce43478d151fcda95ff1770b3d87a6727fc274d7ed11a1f0e286992e87dab4763cdc33027fb60d42a3065017214496e54c3d0ef5953254c02408d3ce807cdd58ffdce15af94762c4890f47f6215fbc28382f72c9346b4d74dd7c768a067ff6aa96e495dfa9d13470b6adc362bd8c442d77941438944521f67e85673c5ff373512909b8371dcde344cc8a602c33279033003c4b7bb51354b2e66c415e7cf3cd013004cc968be01a21d9104f92e9307d9d9581c2c125581739cf740dde7d530e22a3e08117559843a0edf0b6d576b4b528c8e21d00fe8814f357d63d0f4b091f4a9b4b3de3de2f3ddba9528f7c6e95433aea0ddc9077472572bc7f015542cbccac3db5ea7269cd97e060e3bfa854db263906946e6e5a973f355dd585da0d39603f52918804240f4c8a2640de27cf9cc53003201b6dc58a2ed125a52f46444938a93fecdfdbe504898fd127e70f9f1ae29eef61e6ac0d3b7c6a84561bff144eb78dfe9783f717be8381bf9458250424b61f095c1001be264376f4ba325ceff9bb4752cd3d8806870b5cfbfd252637364818ec11bff699cc10f3102fdd62a5b527ed7a"; + verif_kats[0].expected_RES = "89E8DA09EDD3600C15A06D5B5CBCA92CADF08F4313D0C0E2B23E24B329EEBD1D81DE6DEAE3F36797A494BA2121E0A274C3988770902E2CB325B79FD1C6ED2197"; + + verif_kats[1].MSG = "ca393154ce0e065793750cbb96156c74eb704ed0f2ac97c1131f250f550e1efab980c2cb146960dd7c0b562a1f412c6b2cbd203e1f048c73376590bd39d7a969"; + verif_kats[1].SIG = "8A659F891085C42893C7523700527092698C1C191B0F187A493139A48BAF373B92B6E6D9D507A0BC0F9CA86226FE5589EA760E99F2D4E22378E4CA968A3E945F1D7F36F97F7C11CFA5CD67D63EFDFAE7DF68DCB8A3D6975673EBCED7D8ADBEE342F7B8E6F32E6420B520FD284F72DF044D322B15079150E6BC6FCBDD3EB6FB175238E3306069B4EB7EE239FFBAEDA41C704BC3F38280DFBC2EC22DC806357E4282F41D3C63FC9F6B3B0A02AA0BA960A45066424A59DE99D43934B48BBC28C8E30066214A1E13A967D5A5CFA25811C013D85BE5BD1490C44F2ED16D7594011AD2BBB4339914E650A604B907D8EAF80FF24A42B0DB618D53C14857344951A653170621A225A06F70D0329C3EA15798A28C1111C2E4902DE9C04C54525254792C5C0DF0668F2DE6F3D77CDA05605A7741A4BDAF5650A76E68BB8BE505CF1B4C18EB3C3820A7A90E69E5D170C87DF46C29F1E024987681A1D36D69ADC6879C0BF785A8139E2A857DD4A76B29963DD28ABFB9415D7010B54A496133E5BCEFBD9504C0A541A3AF30A97337B249F585F604580333D83FD453E109442E1E0E4E37105781F4FDB9590B05890538BB61414C3094E0E110116FBC25088F6E32131FFDF3E9AF8312D603E25B695D8F6D9918DB442BF60F2C4C8F395A7089208D4CC82A99AF093EE32C216BCCC4E799A0FC9A9BBA09FD372FDE10F0C448B4B9DB4631D03D9EBD8BFEF09D686DCA17D1B14459C0190C4CF9EB53F47F4E95768364CEB2A9A36CAB718BC483CBDDA9BF1AF881EA346EEF7BF245E09E08D3F355AFBB0B3F6420C725368E5DB7F6182CAB20C82D1363374FF9E18F444111923E94BCFCD236293F4E47C391184CE4EBCBE1716B1638B879F7D526A12C4990B552344570552E0647602D0BE13F4DFBC87C104D73760EC31EEB9C52AF2BE770D73CC4794A88B61F2619EA0AD19E90BA1BBA75F8892977F3935EB3273AE04038B94AE7C3932E10B4D45E24B5EA4E7F767ECB2E929CD0C48DD5BDEF58646A17A15961FE57E008DC1B5E5331C8D2E3CB3A3EBEDF405476D33A53D707A38E9CF5D9066B84DEB8AE8A75CD776877B5C44A90694A970614E7CA109BCA9B76DA126C402F814B8A2D22CE7C2F5CBDB70C8A0595F922341CF32307E5E69030072F91B32C29D1205F0D585ECD2862389A16ED461E0482F65B3063B093ECF46B603863FFC85800041650143D5871660DBA750F1102BAD4EFEB3DDEA86AC29D0510E00B5A811586102A667B76F997FD6F0A918782327CB374AAE591ABB6175AA15506141E54E622325DD65E4F4C8F69370C6D82F3BD06F80B04DFDEA8D547B1A2AFDE90DF654B37AED1F1DF080B24BAB6C3D337A25720AA73DC3E5CCA88F71078B5D3F2BA1812A593537171691DC313E21E9012ED9DECC6D20416F840E14712D6AFA552022C7B5EC578F42BAB2F77661B2C4754541252251B179FC765DD52A9556C650E795CB153B2BE5BC8AFA721F87BDD996F7A82BCE1955F163B6B951F837E5FFC758FA92AB83D472199DDC8942902713D15F5D1B57EED176AF6366FE11932507221963D8D332911407F04AB610DCF434688976EC347B2B6748515C82329A3A5D31BB3D5A73B0959184B1BA8799ECBBEC94B5B5DE2A794810AAC46D94E2210094ADE4807E9DA3F26327A32E019C52044D80CD2502E67FAAEF5087ABBAF93543BF9DC3D3544163C469952AF12670BB21CD946210E059DE868A52B34BE30BE951DC81092ECD0CC261803E25B7B56F963D58EC92399EC96E095721E2A4B1AE553C37C90CA8EEDB76FFD1CF7F0B7223E6BD68700D2B04626D12EFA1053C65BB14892C623C8872B006F8F654009AF571A6F91D83AC8E6A3260FF78F946A197035BB4AE04DDC9BF783D315EE35ACAD9BEA041E5C631D2C860D4402A865CD3D13E82A0158114B5F51D403A769277C0056C4C645B29177B79394B639074E85918E4D9244EE4C2FA2E1DA05903A516C5054B348FAAD38696DCA8214914241F658A0A659D36A96D96515D055C87B2E628F4FDE39E18C2D0F164DD1893F3E595F11B5463117BE1EB276328DB1073AE17EFF6419652840CF7F99B93703C1FDFD41102B02AA6BEDCFFBEABA28AA3BED6FA8EC790243679E629397E64384493598C433E5A34F1A96EDBB9697094D16F33F1344608E3122361B25EDB34AC763049F5EB9D21028553893659049AC318F6FB55B6FFB13D245F09A413D06C6D9ECE959C2FBA470EDB17A00B9432665A7AA223193075D7CA97B2298437F77F21775F8867270B9829CF8BD7CB76BE6C6E8F1036BDEE6E2DBED599836A43432876B44BE2930741CD934E5D0291A8457BF0A612B99D51D6CF4C412F5A156222AA1548AF136CCE6A57D3BD730D0B0A3410F4303187CC23E6032DDDEF14CC65B45671A8C0EE608881CDCD7F558ABEE9714F25D5C491068E3E278CA01209D96EB6EC8C679B21DA34AA9B494B4A67F2C742AEC06653FC66D4013557AD388E8EF21071FDF117102786D4F2DE16A68BD4380BD18558BB29FCE4FF761DC3D5DCF48289198B1DC586EFFF23FC9A89478217B37FB6F69CEB89EFF9DD0E045CDDC05A6582E277052E51C65C6DC5521E2F59B854694FA985D05E923D14BB7EF6AFE34E63F25DAB21F669AE6C6A9CC70BD8FD72D30C9224D6ADB2F5428193C6190BCF1C073B409B0C35B658ECA358C2B9D24D02E5F5926AD2329829926C3F39B0FD49BBA44A9D3C5966F07B4A06243AF5CA160DEB492E1EA4847FF4FD14CA75B40D125B48ABBFC3E5B764A19A1D491AF110D876FBA529D3B5D3A3E48686AA9AB26947F1FA93D9D40C3DBB36FF652C7A30A3ECC728E94583DFF9AF8A275886214B6AC055F3323B9AB25B3822DD0C2ED64B95E3DFD9E4F50D547BFC790694F38CFEC4146DBD8DFBAA2D78B2B3E11F340ADB8BEDDEDDCED867D584F67B9F3601A62F2660932901393486156B0D61FD6E6B459F5C01A485979797F1635687EF246C960D64C1A248145F5D1658C27D42F0169E71825EF9AD8893673A5D323A05D28E444660ABC4030BEF6C66EFCB057A9EA0684B1B64735728DE008A65E2FA43B84CE5FC39649AD06C92119DDA9C70DBA340FC4C27DACD809637D4FDB0634684C5936B009B5FC3FC7D9B09B29C70ECFF695D885A35C21EBFF236BCDBFED085F7B4E609626221571C8112F03748DD010FC97FADFCADCF825B0472254C026A0C5E83610E870F75988A7148F2BA399E5891164E59740BB41D6E6277C73B1412993F91C3E2DAB02A4F12C427ACAA14B21973C1D442C79D2F038AF9AC48A0D5E12EB82E234615BB8692DFEA8A98D83CA3DD9033D7C48B00A0731EB2DC01377184BE6F2D7DD697D44787C6A6053E6E628437FFA0419A0BEA50FBE52D6089A71B2E82D002EE1FBE6BB3108CE863A08E26890DBB769A417E8926950419D2A952E20AEA560EFD64A525B63E46D2604DBD2CA4EF862BD3096392D5455A21095CA663F886460F592BC75555FE9B13A00A8CFC9D6991488AC59CA87B8A33C472866F821D20F99BD228509F561458CEA2D7EC30048BB547E53DC48F1F976BBB304FBCD3F1DA708941A3B3EC3B7E9992ADF216FE127CD16E5E23B08A7E364704184F659DFBA2719E3C78CBE2F19CD4A84F12D5F60ACDB839DE814C52D30CB8B216A443B2F98225C4E18653CB36CFF848C0E07FD925570040E60B9810BBFA1FF2FC92A0F9EA3E3C74DC443D5363DBC576684182B13D573BEC531151F32F94C1CB54533ACCCDFE86DF79572044054713F3A83275D47B552CC7EEA9501DA6982CB81EDD982CDAE683C10EF122BAD67AA2B69E1BEA2F628880688ACC773ACC727B0B33B190EE05F3BF5523C610CAF7A838A7B9C3F185D44696649D354E1DB65D76832EE32BA1749716BC509AB60688164A030E06B5866968B3CD64E26950B0BC99517219AF04AF5B79EB593B0FE4EB497293A688741027F0725565677ACC6E9432901ECAFA14DD2611144AA5F4F0278DA0F9D7502ACCD271DEA06D6A89C42D473EBB50AB9087202E8ED9E4C1476B48445E3A7A3E022F32A220BF29B5442E41E0106D560EDB47BE768D620B13767EE72E0527D07270D2178608FCDF80284668CE9B74CF63DA78350CE9BC7CCF87B38FDD5C4EEA3CDA098282285D14B74072F07524B0E68EB7E780EC225D6EAECC1DB7610A757508D752E3AD82C5D838B72677FB78EC5D5C0A6010BFACC9AB90CD159280F440E886435FB8A525B8AF97469A8985211A83FEDBA6A06D713868D544F104994EE93EE0A3C42D5106B6765210583AB868BE1A5B9A0269757CAF882A4B3C2D4FCF8DC4F3BDD409684D17235763013D3939FB4BB9197175D6B25A966399FA0BD6486A63E4A20B91B987E955CDE99DED263A9EC0796BF3D14B2DFA3BEBCE7CED3E0953C02A44596B4623FB73F60C6BE64F0DECF9D555CEA95CE07C60AC56CC0C20D9E39AAD4B51D94682C0B09010E9BD1A8D24E1BBCE8FBDDD30980F03D67A6413B95C22EF21B4E889ED43F55D787E2CA0CE1B3E237B46BE54B65CCF93E05CB4D63141BFA54F90CCC5B239417A8AAD7A88FA7CCDE45B26D12A664F49A8154A3965FA8E3CAF276E35B6AF06D8F271CBC18C17253C0A7E21373E7CAE61F6088CDFA4FBB434B206D45A3B937DABC331342D39CEA1FB4C52FEBBA4F89136AEFEF338F021E4AA3E0E028539A5F126EA37A1456655311493CF992ECD7602E150A290EAD12C9041ABC57C13EFB1A3ADC7F3ADC7690C8217B85D2D9D92AF969EEE20960A74759FC0B91503A391A7CD57FFC822CCEB8CD555F27C463F486BA2AA96FB2776EB88714B3225C3690A108D14406D6BD6241EC15CCDDCE4FDEA4032A667641144716BE03D02B52BC002840882B9C377B2BE19CE16A49867CF236ADF14E3401DF348A642548D36E9FA1FE56CD02DDA2CC05A50E4BAB45174A8BBAF0DFD8A2662E96DCE4F823509B2FD9172C85C46F281EB9785D4C9810B7DDBDF984AAF2838D7C854CA47439D4D359A7CCFAD80D3BB18D843818A0F6476162AE74766C55F217E2F62230EF763A34B360C7AA6B3C531D6869800AA8D933B7BB0E63FC942DA2E9B194BC55FA64ADCA4DCA0A58E898C437CA9D1239F50D9CCC834D9DF1E6BCDF8EEA63609AFA46852324B31B96FE4A535083423D59560D1AFD42F3F3C57E98DB0629AAF087283DE6754276173D3BF388702E263022A30A224466433239E6F0FD13570C6B96C491151EF1916EDC7865E2ECDFA2CD5F32332E224757E27C6ECDCA51E34C498D42BF07C3A7A36B24EA3D0BE1D668BF5D011577068C05A8EF206660B3460B252B39F0BE21122CC46541C4F79148D6099F78B2F7D79A2C8E0477DC2D19E0DF277E2504ED60808553640BA21E2427D84CCEDACC2390901D4D263BFA2BFBE18596AD80DC44AF44E7B2D0F41FB9EA0890D718DE8F34201C1D018DD89616884291C14DCB0A3C985865DCEEEF58EB8593E1F7A7904E704653E74371F9C691BFA337A63C60CC1EC7F3FB0EB21BF8AD4E1029EFEFE5541A3447708D8268C70345620AFB46C5004D2C49996215EBC2D14302ECFEA6727A5D6BFD625FF858B8B0992F5B5DDADECD788777DCFFD17126BAF4109A74ED7A0E24E1F339DEF1E19C237D3CBBF070694E067C95FB08DF8C6F43B545DC4466C05E0B3748B3FF01742270F1CB619570E6EB8959E3E99D05A66BF2C37BEBE515AB6D3F495C397E636B9CBB9C111BF778508C73F190EA4CED77B8015E97F2F78EE087ED453ED48C6BE372452C22FADFA50A30BBF441FABF7D87698C6DE497F13723E3A5B6BE71783205AB2868CA3FA35AED4D3C73A0C34DD21972F693F0C47BA839F27FB406215DA997C65B4DDCE96C37EC416BCD378884831651D7CE60701B034C629D33C10B2F000134F1E84180AF6AD365B0AEC2D2E0A1B080DB26E9102CA17F82D7073523BA7CD0A8ADAA49ADD73F42A0B21CC6C70089AD15937F21B0935D77AF65BEA0CC5010874EB966BF29196100FFC274E359AD514ABF01B5FC21649B360BEF9B2A39034B9AE50DB4456B4C43DA6FDA72994A184D93C7134114BDA317B6AAC8F53D75D905F6EE49D6E7F5C48C6135B1BD9A88DA1FA35994EB775EAF760306B4915181BC51F61DF9361B6ED38FFFF4F0E66CB15EFDA30FF1DFA41AB8CC4515EBC7C2B47729261C1D08412D791354BB2431CC9296C2DDAF8982036E0B3A609651C53A2AA6E505CEA9AE27F02155EC21A0BF635BD63D9B145A655D48CF6E527698987FE67E76855D710DAA8BF19885DEE24448B8AEECF685FA241ECFCFEE3CF75E54E762085AC0228FBB8C87A2ACB57B3DFD585E8C8CDCD8EC03E34C290A521EBA4CE37B9E1F446B9F4A1B70666DC9705D6ADD69FC206B817BB73A87F4DAC204D1151E24B8FCF7F6EA0DD84D57B85FCFBDFAFF66C0CA32A0251D5CDF19252B2D685BBD746DD2A5E8263B5154838586B5CFD146587BB3CDD9F30F141B38575E95A7EC9EC0E4E6F412475863B9DCE3375B6677828690FB6699C1CC0C4D8290B5BCC0F500000000000000000000000000000000000A111A1F262E323A00"; + verif_kats[1].PK = "D7B1AE0B7AC9DEBF3236824CA48B49A5FF417C11FE65C667716FBAA44D3DD620F5EBDF9D49AF3B711F815E9BB80488C8F3106EC723E7CEE24F1408D73787A54AD9185B8A7E331F6085371C71C5A94A64B11AB9C2C05D1AB0AB8E2F6DE7A10E3562C28D10C563C57517688ECFCD7D2C5103511CEEB38C17DB88D256DFB1282A2A8D668543C2A5D44E01419F2FE79A9CF7708EEBADAE74956B0715E9FEC122CD98163DE1B961A79C343655957EB046E13CDF26C3E24D625F751D28E8B08BAAAAA2FD10D8071CFE63C875E129B290B2FD263D306D502AEDF01423A182DC1608B392283D0C5A11EA510048EC026E3D53A8F6124BA59929C7DB8AD898A6277218738C1FA2E51B338E7F2B7BBC45F5AB90A911C62608B663FD5DBD157BDF4C62CDDC3A82D8C07D70C896B37B56CC307905BE965B17EE996A1420044941F3FFBDCC6398E3AC716C78DC558DB07EC6AB6B2BAE75F2C8EE5A27BA0109E1993017D98B42933D19D9E0DE56D743E6CC681E2179A6972DB9EDC51902E6527A3A9D7C53B66AF3BA37D62684C0CE046798EC4CCE74224A1161E8F61AD01D44814E34ED69A77413414CCD597588964CD1D9824E50BB818928CDCE1FA35D470101EFD1664AB86A4C1FFCB2E51CDF2072BD8BDFBA7440BD9CB8643D5D8B1833B1771FF48DC532BE02D57181CBF38BCAAC0302E0B499DB4176B967973201E21B6E0E4D5ACCB65F1DF56E3D855F7AD2DB23CD0F838DAC241455A085BFE125FFB2526C3A71DB0EA64E756E0A5BCEB7992B10518AD366DBA6031AE43F4AC033129BA2A206ED17FECCA6747E5F350E0791DD0656125E682CFF2C0176F6A6BADFDAAEA474702BB1A60B4169F506977C693CB34DBA3010A0D26A5E6C287907E5CA1714A93890D9913D86EBC5900682CFAA0CF01573369AF40708F3CC83DF996CA12530B54958A288F58CF0D95C61D5E689ED2208E4A1AE20828D1098F894578E2C6FD1841A583954B037B7DB54DAFB11E6D8F38A7A091D777B36A29F90744C11D4DE7DFDD37E9E494E73C2920DCA5D8A377DA84148F0836C88D472FFD371402DE5A990D3E374F9478B834FCA975D261E79F9024DCD70DBDA745C776678C17B62353CD93A6380B849BE5680B679ACB0113C004A616D8E3208F89A52264319F973BA345E16AA40825D14D30FB179E8EDAF525AF8BAF56FBD44C97E0A3191C4D9A3DB9D4F9291BEC065988D82D39A5284F435CC2BBFE76367AC78E9768A12AC88F268157ACEFCC0FEA6BEF6E520A3603AFC090DC7D922D779B805AA38FB31FD95D656EF5DF3620122CA83DF5E83051CBCC2E6767A9005DF0D65DCD0863A3B6DDAA9357BF31D9E370A027458E687F6FB159935101ED576CC1A1965B51F1B46856C070F3EECA68D55DE610111BD831D34CAB4BBA7CBEA57065E27C2E2A075D2F301BF6B795CDD8C91A8610DC72E495A90419E58BACDAB419DE6CA5A06498E6EA382EC2CC284DEBF0AC7D52417CA1310484EE64C0C8385839D66A48821BC099BE9C267E0BDEBAAEDF2FED4C8D5C8FA38ADBD77B153991516C444B5D9F7FB01EA442B3F603F7285896C612B9332DDBA545B8342D9E553E7AB2C88A320F9206F9C72FE3CBFA15EC12541EED585484D9E7E0A97B44BFBFB66C48518BC31543C680A7D320424BB0A22697FE255E4787498F998812C712CF20DBE71750472C51D4AC501ABDDE8B90CA21476383E861721554A9E667360E030B02563E51973AE326BD3F8B9BED05272845B9CAED94188989624D70FFE5C6758A6BF6E225C641A3B71AED6F2844778C4BA844940544D8C8AB1D6556737E995EC517F66A60B616BA243E1739CB63443011A91E704210637807B72A993EECCB0C9719CD2FD3480FE45A4B329E7FDF51CC8FE9D136381A2DA3691AAABC604AF98465EF36FAB8C2C71CB9BD1C6D48BFFB072206903C6A41516212ABDD40206583ED0F66AED210023B19DAD522ADFE6E31586188566B7C64FDA5BC850691C75112FD5392CB18E5B1C2A0BC79A5FA757C5463F134980F2A203A93F759F3FD3AC4A17C71C5C6E428AB13DA82F3A52F45FEF60C7277EE256424542309C371B33CA9D1865E9F52D839FA9E578187B6D0C7390DB1715596ED24250AEB7968BBC9C5B77A73BC9B2C777E49B73F918D13BACF546942FF5070B760C1E624DB603DE558787F6BDB326B3C93165AEBE0B818A943FEB8B2DD72D8180917B739789B533FE057D3154159B0ABD67B60FF681E011E152BE6749F296E778461277F5AFE8BDF28AC56DAC78745545E3C20C8639BB76AAA76500E799078E59650FC82A0CB2B28A05DBF574CD9A50AB041D494A389D4DD779814A2B24ADF580880E95BC21DCCA392CA6CF7E9A50A3D80B5E6855A0426182489090BB82F1EA2150016B4B3EDD9FA3A2F8D85AD61AC2807BD814E5462545B82388A2CD33F310E316D4815F8812AC924FABDABE7E696E0FAFF17546F359430461053031D31BF20FBEF05A6EDFE9720E9BF2DCFE15D83A597B3BDC52714778176C3823364B383B61F5ADEEB770C3D1FE161407D697B6201D5F5B1121D034A6157E46F81342ABEE5D7BBB8977F6209219BA4B8DE936EC87054132CAC3FC65666199F48C20E2FD56B08D04CCD4CFECECE2BD1C65ADC9D0B8F26E5DD582845B761350A3A8E6179105B7906EA2DF4CC3C21402F0FD5ED1854A11CB59262819DF514CEC51C026A2AB9481AB229FE42B3A0494FCEC6C2F6AC160742254DAE4E4CEB4BCBD288108A71805EE27B994BC919BBCBFAE1E3436EBD6AAC2A56ACC37DA6D39B52266FD3A6B1331BFE9BDEDE19B6227575662CBD6DDC5049E205F30272C151BC0CC00E3A2EC4A0E012FCDDE6C51FC33A18C297F86AE61803B21346040099BE7B5F1527E9D648426F1A06D8F8F74DB968D439C04660B8B14EA5BFF205E273283FB1B40B47012E718C50C7E899533E591B54F8D0631181962EF810298B0C29414882E51B073B19BF1C49A893E6B541D61AA48E2EC909102C954FF63E81C40B61BEA01D642B869002D6D8BB1DD28090DB3CBCF1AF7FD0A17108C3842C12B4B55B741C28E303863F74B6A1998D18A7952CA6F1A6F83751A5550EB32A0F9218ACF9945CCB1181AEC15D750B74E6A6B170A6DFBFC7A09EA13089B6906CDDD285835D841C2F27F380FDA69A0679FF94715861146C9EA97A728E1FC7A7AC23FFCF8150F94DBD64F47BE44207903C64F2645DC7D4963CA94D0B97E395341C8EE2D52D015446F972415A5B651289274F57D55705B8152ED2948F8BFC84D7DBB127F30ACF4AE91C05C8D5C964992A4E6E8DE6B569F4E36C5B846A85544916DBBDFF6C9250C91B9523D5EDAC17505D6BEBBBC8111E89AB795298CBA5A0E25450EB73DCDEB643C051133408DA8F3D6B47C1AE23F1B010473AD0A2F62E63D05800BF9FB05DDB1040268A0D4F0EEA7AD172EF547A9685C4BA4AC0D719E607E96D4D20314153A366029A81AB826BD5235228AA2230C6C0DE15232F7DF8330536A5A156801ACC2F20BAD0DA972A9FB2B4566B48F648A9F870DE8181484DFE57530A8EB0E5C214C418224699824CAE98FBAFFADC7C9DDAF635ACB7C92B2113480FC110E1D43B6DDE1A755C4E11F197E7C8CFA38195774B65DB88FE7EFE0839C22617E0FE33139EFCE9342D2CE72616CDD58D0316C1694"; + verif_kats[1].expected_RES = "8A659F891085C42893C7523700527092698C1C191B0F187A493139A48BAF373B92B6E6D9D507A0BC0F9CA86226FE5589EA760E99F2D4E22378E4CA968A3E945F"; + + verif_kats[2].MSG = "9433ddf6e491cbf5cb03720b542e432f868bc7b5a0bbafd914f210c3a9d145953c6532b8212660ff219cb0bd283c6c25501aee58ef4201916e7671f92b759f21"; + verif_kats[2].SIG = "9C5EFBD8FC4BC59259C5528538F9546FC47C6ADA017628AD039E841F3EEB41078CFEAFE6BCA288F8A1DBC40A0A8DD61D7CA0C5DCD435267B4352CA2E2F3BD346CC790FE55DF82A25C3F23D2D64B4A8970C1277A2522744027C90F0FA18BF22E49C1AE5E589129337505AB9ED4318F756911ECAB97C5E0343EAD34BA7B6B89DCC130903E9E0902941B58213C94C19CCB36033D514A628B3E99D819452A9298A76DF24407CCB332C55FAEC61CAB4C99D63586DEEF80323B8DC05EE160177046D298EBE7C7E07EE5570F6E4C95EA9F5FA6A72EE55FA7ADDBB09BFC096F6D544BEDD75DD1702203396E149C846D66B846CEA8A7718A627122ED3DA6E25A47887958A97A28F5A84A7B9E608A0D929CC0B48329ED824B2B39EAE56F20192F9BAC700C2DADB42BAD7210A76034CAB87576698AD61FC4FDE9A29193ECF2BD6FA5741143FF6D5DA8C125FA336BDB627C8ECFB327065C027408561685836107CFC2DD755E7933A2560B8CA5A13A5972C0F3CD1FABE9D1D31ED52E63EAB7C6F30D49911EE8435E1D58F42D24983484F62C6324CCA3AEF6279752CC429657C80E59D2CA789D82070CA167143B407290B373D5AE0F32715DA5040FDB844BB8B1B388E5131D5ED474004FCB10EEFA799CDD494397EB43DA9B69CE5468C13DB7E70E56A974B8EBB8636E62301161EE9CD92A61B9C00C389C784DC48EB29C3E3C03C13FDD841B6D5776583FFF2E143BA8279ACABD9B33B598CAED53EEF93333AD2076C5D4AC55625EE6888D67838B3FAE33068EE735F65BFFB8ED36A75071143D0DCDAECB0EA4BC1997778A6E919847B2127EFC49860DF42DB656681B115E7CA402D7395A3356957C9F63F6B53D7DD9AD681AFAD26A95B3844B042966B29961F2CAD3AE1B392C0F6E444F5F28F9D80302BE5AF3A450FF674ADEA63B72EA1D5E7C864BAAF1B1B2F6C65DC25073073AFBDE65BBD82C4EDFDA5FAB7C5639A5E79F4CA17143C4767A13AC4CD1942A1FDCE95F832577457FDEDA9FA8BD6CD91BEC05EA2AF3E77DDA26C233341147513E2E1E66079F6FBEDFB82B9C426516DE1AB27BC99C52EA86D16311AB303489693BAE687CA4FAF7FE5FF3E66D1B4509947C6A3AC8D2706C016BE4A75C64D0CB9F619B0E9310052D3A7DAA467698F54C043123316FB07CB095D389FAA0D643D9C68BEBDA18D3F26BDCF50C58271297F556C5F69E0F900C47E40BD22B9EC8F5762BDA9B6351817A93523B8C5AC863B8CA50E16798578F19DD85C80DD97ECF158944ED3874EAE1E4401B44FDB28053E4458B06B6A51C44635414CE5255C038FDD00B1777A12D52738298647E10B2C24A56932676305370B7FF2290D3907E1501CE17B67149CC83C19DC90BE28CD2BAFBB6FF08293FC2F0CA70B9083517F5BEA55BAC22BF1ABBB940E522916ADDACCF9B0BC1B2ADA06B3399F5908B6B517454FD84207A83C0813F1AC6802096DED339A162892FD2DA66B64C0E756360EA2A6D0DB794D5EBD44AE81263229F78F90543172758228F563CAE50C02B0E8918871D6F213A262B5C44D0EA31CABC478770B408A91FC7DB8E4A842E1C631951263BF836A338DA967582F4086D4A3BF47EDC57DBD6879D675322548705462912173BC8278FCAD7B546F9B9F73852724382A29F3904A06C8BC2E24BC0C6D3897A811A78EDEED0B8F8DEEE869542F936C7FF3AC0D67E55C95AB1C7A5F23AA1B989FCF97CCD2AE097A6E8548D97B0A76CBB2DFCCAB0C7D1AC9EBD3A8EB8F411A5712DCEFC79E9CFD3D69AF856E93925239FC666C7FF02518BABC50E8298766E953F95C2557637546DC7FA1B80E994F4EF93336122BBE707CEE4B7C2E875D2D1E14065A8636645A374D543E42586E4BBBA52D94E3EC1687C0488379A53C8DB5F409630586319033A06F7B21E382148906D16144FF8990B94FD90D4E85A729302410B89F121258033A7DA98883B50DB5E89CC9655CDFF8E9F041A075B7C742BEA13E36A83C5CDE0120BE9C59D50A0496A862432A82FC645D33C174DE11510873FE541DEA335E8054A0B193574CDE4E20CAB6E7731A1A28DED03844B3C76B9362565B332140F91AE84016758A0C4AA7ED931A509047A5F1F2E71DACC724808E8B30C96C5C1984FF406B3667937E7E9DA309B6A374DEE6E2C91CF7FD8F4459D4AE9D6C27310EDBB99390F897CC98D5A2051E848E8DD0BCCCC382FDB2DC8E4A4C1B5E6A582DA10C31B219E9670CFC53BB36EBCA29C6DF49E42B1AA34644FF5AA6C290EAC68938236913B8A8F970AF0A9A4FE56B2B441026ADAAA67E1BDB81D9FF9761D76E44CA7AC39B127048EBEDD8A2D41ACD9F559F2D0F575DBA0CAB52F8FE5E6031625DDEA9F363EE4CAEA36F4B6FB71CD079039867D22D089F4502A53B718A504F5CE1D0D16BDCA8860CD20D4F55A3D29EA7F7DB73AED014861A8C8E41EB39E3DAC98757EE6C3235673DEF318675D9E686FE85DEF0A3F38689751195460FF9BC8357191FB7CEB7A3F17C2FB1716301C5AA9550209CF8EFEF4A54E92FB41B1F962751EFE7A0C94B387F1DCD09DFFB76DCBE9B10D9436157C7B6755BD34321C99AB84335792EEC3730ACBD54E88AE9C0BF78072DF12ECD51175D4EC80EA45B2723BA6B9D4F5F7786A6F278078BC9D0FE09B4144FDFAEB86ED68A67609CE4CF3CE14B83D984007DA1986CB8488C0981C1D796B874DD70810601328E3CB1A72AFAC867022CDF07469CDFC1014899FE9BCE106FAFE9F909D4A25A886CF7EBCE107F52B2048A5D0A6ECA24532CBFAB0712B92EF7A2CB50EB15B2F9FD3FB0541A25E2DE4198202E9DB4B36012B2035F4F0FBC15CC6F121ACC19359A49381FDBCF74F46D80661996DBBE0D530B369BE69E0CA180D3CB9543AB8E7BA2C7BAB67C7B02DDA2BC9D070A60655A9FB0F90E6468F7502EFE170871FC0E27D43C3945A292BCF9BC01A3FDDEFD87E4BA46D915D918622998EAF3F64C3434E39B201921811D67F99F964DA3A831D6407F1C8C5311557E6D9FB83D55A03F19E6ADB056A1E965D90D1AD03F9B8588DBDD78FCEF81DC190944AD7FF4B9D1ADCBA06666649E5D8276D513FB7E148F3EBD555E0361A9D204202BE359BF4E5FB7A088C472EB0268323CADC8D5CF4E74BD9DADEF65A0395C26D57CCAD179257BBAA1C4D39B755CD3552C2A5A0C53ABC114AF180781F11AC83E7A5FCF7FD5A977A6223F6D779D2982B1E82CD6936CE4E29A6C5BF88D474F6FB163C6BF54F8C19FD556E368E71776048FDB3BF51E54FA2814DEDDA42FFC48A00516CF304CD8C6171922BAECDCC8779B43B73D8BA39E3C04C22745C61B7D92EEB8BF28C202375BF9B8801408F036685D0F04A11E50969BD235412443C4503560922750CB2BE179E4C9BDA51FC290ECBB5F51BA7CD060F6EDD70CCAC48AAE5E05E070A01874605CFAA6A5844B3C20AB989F6AA03DC0E9C5D046EBE0A819DD770849BB0039A1600AB455F46A0A6E11FBFF35CC06B4A87099B07F7C62997F0FC4BBD46F9A0001F031B58D2C1AC8C1B91ACD3BA2E3970B1AF0D11DB275C898A7A340BF0820F81370E957590F0E513A0D128325BE86C84BC61815BA37136BAEE6F94E0D0350758DF89B25CEC22D36515723C90B697333359AC830D4CA418859A42255163761642B84704DFA6E0C835560BDCE67E1D5424876053BF05B7B8310E0BB46299F3CCD677F8C67596FA268368463870DDD7F06347E8BB28BC7E3EA10ED6BF20A6939225DAEA03BF52D957990EB0A8DFCF403E67D1EA6EE6C48CAD03580883D0086546A8ABA936BD6C837E07EBD971245FAD5213EB5CC73AC6632051F5CBD5FC35F143BD8A30E4CCE9CCD9514626B986F2AA0787CDB0CF797623C41C6786A4D8F39C6749EFC1F06E968692C8B67ED4032200DA35A1C2CF393CF1851A184891F15EBA55560D12EDE777CBF5F95AAA638BE56977A0611E004C82ADB6F95906A3949BDC01683988348D3F5A47BC0BBCE22F7F147C429EB8B9E2FEB013AB6D20562B3E2856D4767AF8F8DEA16FC75815D9D25AC13795BF976E41FF3EC1599F36BD913E7E2D9AB5ABE7FB6FCF2CBA652CA00C3D84DB05C4BCCE42735822825E3DB5580075CEDA00F0F06500413EE11733C8C1B7B14680FA368EED79F118BE06E8373168B83821A2EE66349473CB0C36B16C4A00EBF9247B9E187E8CB4CC2429F3509D91875CEF69AA95552299EC7EB7947D6F1AA41A87B8DFD40F4F3D2465D7D1B26F0C4568448897115C4C3D007EB35270AA60CF47740F193A920291ED247FE5C67780F510FDC23A16DB4D1F56E4DA799EF2245BC2EBACC2D6B5564758F33A81E1BEB3075235AA6B132BDB0EECC4F98604138700D3D36C5B952F84CB50820805E8DD2D46E7ECE54B2EEE4025E158743C0D9422715ABDB76934237BD743ADA2795F5881B1A4139A371156C05830BB656A0D5571B419894D52CAD68E03C64CC33EE70F90819CE89A91CCA0F5ACF1594659DD195C8140E02D0249EE10BAF3C8068B765188627DAC302ABFC5A0B30AAD53F476C8E8A201CB5FBF85055D727894EFB3EF70C991A2D9D6C411923E456F4F8417705F042E890AD69AEFBE5E9EF5C0307FB1A99CE9E99C7830A383AD703503D5D847D703150920C423BC0A2CAE2A8E16F1FF30C932240F5B9239A4A3D4E56AFCCDC3A06E74FD5930B336052F9BB6029AAF9C9718AC62FF8352088CC6833D5F97352B4176463D58CE514D458CC5EE2B99E84CDB24F760EF7C737FA0F762FF4544BFAC078D4494C0BE2769EBB872802590E21E94599257E9452161968B6C2F8FCCB8241A861CBED00D2C38C3438A8A5BBC44C533B9B8BBF6E4F9DF7180BEF52062A465BA266B97021D16BF0FF8E29044F1D13798F47FA12791232E969484F729C699F7DDEFBE97E5ACA8FB900943E2EF04CEF3923DB07B9AD1D2880656BFBB365CFF326834F651A9A72181AE1AF6D9DC7FDBDE84F7D271984F948B8B963567F548E6E00C1648EFA7514E072C603450FACDA79B6827ECCDF9E607E9B2229F4976D5E7A3F3E1415854F2BE29A585B23FEAB97EF227BADC65206F8325FCC362A00AAD7B8187B61BE1AD29970EED3D6434D34AA81D6AFD4AAEA7CC5E74B43433FACE7E078ED44F84008D7CA3BFC44DCFD87E27F728FC2C7CCED887DC03D875305E266FFD83CDC31FBD75D17D94192BF7CE72259C37F83B2F47AD244A77E26B07B014A5F45003A433E1703E850D6BF96129079BDC684EB34081E43BB2020A52FBCEC34C9F035DCA3A66B152849D34B8E5BD492E06FB3F96145C52C56413F68101E609C93DD58362D24F4C849DB5209487FB47CC05A104C6E55E4F275A66ADFF772C84BD9B5651789982205367085DF95EE12B8CCC0CC6E442F98215A5C37952A732DA0E779333E1D35F75DA0F56162400BE8ECDC67F554AFF2A791C7B67859F1BC913F934A62CBFEC106841AAE74E88737E9C2C26305A32F5D7289BF25787C3C43909C175F40B895F3D8E34BACAC56F6406AF5F3F1AC28707099F68D72C841417AFE98F6450A46FDF89DA5909A3F1AD6CD16D6530396D991B6502D137A13BD91ED9A9461BDAA264746619FB4FA93B843580C68AAF80AED82577D16CC4E354F9D90EFE35F0A45ACA7D39831443448091B7308164D49255BC12FAA901E7BB0B98664C58B5DEE3820BC3497F0086B8346885403502886329442C71E51F7BC2759DB3E93F2193F74B5D923C5278D1CB41B6943E7F09FC36937A7E9DFEE6D5F20AA67C416123B66E7BA8E370DBC11755F912B65D16E29E4F3EC01ABAB2CC40BEF9286C7565806815824C3A4BA8BB3430D4DAE5EA46EEFFDE0BEC592EB00776E06D29D76A7A8ED633429574C9F9515C149181B9BE8489840B486C29213964FD8058497424832A4D221964C344AD9731849B654D395C18F2117CC3DF86B8BB37CA65BE7504A3FC27C9EA0EA49893BEA01028751C51826163AA95224ED6FD7152FB0ACB25C38017EA5FB6267CEF654BDABC122319D439B6173DE4538DC5118269CFFDD446351E74811FDEB87D3632C4D2EEF56AC06AD5B6C339F15BCC6898E36DDAF4B6A5ED83C37ED5C0B9E67372C1422302F9089452EEF0AE1D53A81200A44C6856ACADB838015B18932E682A6F7B2FA6CC9943F63469AFC460DAF780A472F31ED748AEB194CDEC5768B1B343AE64AD65985F84B5FDB0C98BB231B86D99DDD9C1668AE4F333450A713AA35FD96614EBA5EB3400681653327698445866C05347C84AC8A265930D486F08727633CE13FA0C844D3821F5727FBB3200AFCD51302E199B80F4447868E425961B19C8D649057B4FEFCF10EFB016670503848A1909868460E6429C6DC725E2FB5A73006F929D8F71DEA23B527AAAD638180E4339E82C9AADA5D06B8ADD5BFB077184FA270854B613A639084E6CBFC6253011D07F8F045CC391DB45CAE21DA014B3D67B9F55E6B04212243577086949CB71C1D7A818B8DBCE818254E7E85899BB1133235518B97D4DFEBEC036BACCDE0F6FD010F687F929EBBCCD7DBDFEB03579397A0C3C4D1E60B103D8EB7EA00000000000A121A242B37404600"; + verif_kats[2].PK = "58E3563D36F5D0492030B6E5AA317FD727165ED2F494FF5EE45F7E395045C87E4B5709DFA6E7688B11B81F70BA940DFE52729C62AC9C8D56B0A93D2D2EBF4347144EFBFCAE4BF801CFB1BB6570A8A58C27602F44DE8399E1EF6281B84DB2614F4DE383BCF4573F411FF97CA729BD3503FB2F91F5F778581E89A8A44E3C3C3A86893E78F991B7A7FDADBA06C938A8FFB66F58CE9B584FC5DA89190BA94E896784834914A4240BD8143E1A12BB78036168B09D1E4BD274FEB8084EAF2913617D2A1C6BE16B54224C552B7D410A831941EB25AB9ADEF774A1F73FCF1436D428E051C23B2C7B08CA788B5A70768FE2B6B202139177A153867A236A9FC9CEA37F47FB7E2FF30972DE89C0850DD7B38AC0F855BBE607FDCEC0E4A32E7928450EB1A571357AB0E137830379F9BC7AB2D8D25C3C59E56229A4DFB1B28BD9B7D8A0B5FFECFBADF3D24EE4E15CBF34D6E771AEE04CB3EF866083FAE94A7BA0853AF896B1438FFA79079DBA05ED1326479B79EF1B770057907CE068B3A62170936F42DEA21E596710A0975BEBB86D605A8A1A4612E47F9E60678602080C57D07451D6F207DAC1D55444892DFC4783FD0ED05DC61054D1E5E234D11AE559C35EAA3A5F6F2EAC9F908600FF2229F188B3C7C3488C88C891A0016198F6DDC951DEC5BA79D217A7779D18938536B8A049A8E418E1A73B77490A8A11A7FC28F100D3F706EB490AC59E38D39F30BF632B458F4CEF494D5132D6C74864737D05AB0AC85C34C91A19E4BC065EFE5BB4F27718D9FFA0431E5619F447CB8C92111EA5AD8104C57C47E5BA02985D0DFDEB9BC9A6FACAAF57F4BE0BA680BF83308306BA43838F7EB9A8ED5F1384134902DE002705100E6785B2DA943ED591CAD0A085A850838E10AE9889FFC1CD2941E1899E1A26CA56CB7480D260B217798056D35EA62BD55F159CF0FC363A4F325235ACC231BCAE18E89EB70A6970B2EC08DB004961FE951F8ED294D7D68CA6DB402325D054A47D17FF5B38734298B99278273021F165817E7805D581A0B9E40D507CC89D543F7A1B718820B1F8414AD6946B1AF7BC3AC1A520312240C0B499CF6B2742508356F9C366980BB1894D343E1BB24F06EB81CCCF5CAD59158FFD2C0D5E0019A839EF8AAF32292C33E32F6454BC03F7CE05D157BD875210A4276EE7C828291BD5AD5D545AE4711FF0C1332AFC7D716D104344E88BE87124ABD94216405A370AD8097D80879DDE60CB1F70B8F2230CD81D719EBF1C5C1D6EE965A85CB8C9982CF1625BC69B0C89D5D4207AD037DB73A929F024DDCC2306CAFBA0FF819CA596EA988A366901172C153D7D2A467FA1AC7E738F3335C1A2008181A8EF3064227FE7E72DACF26BB28816BBECFB8224167224BD37C5B55BCBA256C9CBE8B18FF4C36EE6A1EF091A714416E91DB1D638592D0FAD1DA51085D36D12B1255884B849B2B6C661A9FACBBBD67EEE7BF27CEF998FEC1CBA2E5EBD5361B429D509EBFC6CB2DDEC67B6DC69884A342D4A6C6D8001E9652A1486B5360A17BBF3A47DE94D1A32A5E2602FAF1A41B5908F67E9832382E87C9D432A3B8B6E230A58EA733F980488491E7043F327160FCB6D34383FEE41FE7DB76D5BA72B3DF23034E648E8ADAF8D53E1F63403A62CAF6AB88CDBDDEC39E9AA4233E3D335DC890DB9454CDFDED997B292562B5B001451729C833627E9FAC08097FDBB64464CE6B4C0D33FE64987373951F2E3E19E7CE119A82C2529C244BA56C7BA3C703CD7C940759403829A505A635B4401AAC9A8A9C76EB375F6069D6C3FB6511E20F1E9F1B40EC3CD47CB90B638329F17E1A3D9CC45769AE2E6CFD9284C11F4B0892BEA676F9B09CAA8E83CE7B7648546FBA7E7A8B9580ECCEA43FE330A0F1520F5933164F524CA22EBA3889A51D184885E515CEF8B35E65DB4DFD90D8D4FA1FBD0F7F0936E55643905AC144175A27F189865C011D8570E2A57392A521C6C38DD7CE0D3FB5FB4C34FDA41645E5BB32DF8100507B8C0B33846D12C5878D5AA05B86E4D83718B5158E67B4D8CEAFEAAD3760599C63A0594B64E21DE4C1734AFC875005B798550F02D1203D94202AF189F140D3729733C276DBD47DBCC0B427CC113A38382E4044B74333D6EFE559FA327F9EB5DA8CFAA99B882EE97280E7A909E4B23A0D35CA8164440B71699D82623BD542ACF364C6D74E4D8D79A0C293629474B5D8A05D3408423A17B9045E9A3A6245D4F123DA541FB8FC8C5BFDC3E6BC508B823DB3EA81D1529558416E720346DEC470E5A7FDF7720893EC139DF5B8A7664ABA3FDE76AEEC0EED445850B5FE0F81FB3D0CB9BFC1432EF66FB8960E4601B50FCF176AAB7AE4C0E9328CBD5ADB4D8DD89DB72B0221382D96C04A8F511659D62FB268D781EB68962D2167806C73916CD66DF16E9CB7A1C25C794953FC3C87326AC3195E6285FE5076C35A56F24E7583E985D51F8EE8CF24AB0E78F2873E426C20B94D15A1E178F22D96C4EC22E90EB07EC066CE4A19BDCD66D03CAC9DD906D9D85C630A7E10F118D83DC7618AFECF90F3CD32D265253A05FEACD7DA610FC868BCF54F0053BB7625CE2E2C35C8A24BC8F3DC294F60DF8F345ACF03B2D8BE69B36E51B49492E8891FC09787527B3BEB02E6B2B69158448AE4507FBED5C3FEB923854656B642CBE0176DEE52B92EAF411B5E1480738476037D52D7AC9C04D909EB7AF11D98BFC66DFFE81F19CE1AAF2E3C646679B834CE0030A6E3AC7BE93027D2D7347B9165F9DEB26CD54F33A90A3AD5FFC88044202208C3D1C97B9668542D6F1DC4E1FD2DB6489392E9ED43FA989E5CCD6CC63E357D516167691AF5558541513B38D8DA32D19133EDF12E1D161C5873BB423B4E52D6B34E97875186D0DF7BB4EF4D05023B19274FB1DF47631F6282A45FDA95A07F8D5B0B0F814AE31CF30947FFA65D940C88CC191B3DD031897F8647D0F8D68C2FB79050F90EDA905673B206E6BDC844875101AED46513041695E9EF151B06AF764BBCCA82B0C93B9D26AB96877B49C9368C972E5D42E2CD41B3F7AB17F8F0B3EB1D0C284C699D9F5523D6C5E2F1E33747E49EB675CCF1B68D2CCDF4C7CAFBD6B1254C141001BDA1E8A9FF6F05C8B914182BC4348655D69D7DE203ABB70242AD8851369AF610CAC22E62A9B300F53ED948BF17D811B6C6B65F2E858E645F95A7F2DD7A9A6D6C2D627BDDA4C852C2AF523F9D03109335639009697FF25A1C67E3100083BD6A741A5B4C8D5567A85820E3D9CC6A7F03A1B7C902C75EF1DC49566A0E3A12671097F086CA024E61DE92F15303B0D6613EDF5FF80A5AF17FE2613437263899D8F66DD19B34A7887B72F416B8DFF7498EE37590DE4B1AA099E9AFE8B78D139238AB3473B60BCC70616F6ADEA0CE912C640D4672C4D68F2DB405ADB6643D7C82EF4F4C95DCE932DC8C96C870B1B7C0B91CF5150EEEBE6973068A3E60C5DE142C96A2DF5495E1CC3B3823608116D0838A5DA3A8AEB40887C08E58A62EA753FA3DDD0BB615646CC2A5B185C7B55A7DDFA9704C4FA0A74A2B1BD579C24AD9110B103A6042DC329CBFC728152533A41C3DD19C7F07F5DE5C863C97DA162E01FAB8E70DC91996897C68A173610B61558F298EF0A540BD762754DABD89B89334A2F95A9861879E0D23DFCA4DB8F04DB6A7E6A3D67"; + verif_kats[2].expected_RES = "9C5EFBD8FC4BC59259C5528538F9546FC47C6ADA017628AD039E841F3EEB41078CFEAFE6BCA288F8A1DBC40A0A8DD61D7CA0C5DCD435267B4352CA2E2F3BD346"; + + // Iterate through KATs and validate + foreach (verif_kats[i]) begin + parse_hex_to_array(verif_kats[i].MSG, kat_MSG); + parse_hex_to_array(verif_kats[i].SIG, kat_SIG); + parse_hex_to_array(verif_kats[i].PK, kat_PK); + parse_hex_to_array(verif_kats[i].expected_RES, VERIFY_RES); + + `uvm_info("KAT", $sformatf("Running verification KAT %0d", i), UVM_LOW); + + // Writing the PK into the MLDSA_PUBKEY register array + for (int j = 0; j < reg_model.MLDSA_PUBKEY.m_mem.get_size(); j++) begin + reg_model.MLDSA_PUBKEY.m_mem.write(status, j, kat_PK[j], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", j)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", j, kat_PK[j]), UVM_LOW); + end + end + + // Write MSG to MLDSA_MSG registers + foreach (reg_model.MLDSA_MSG[j]) begin + reg_model.MLDSA_MSG[j].write(status, kat_MSG[j], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE_FAIL", $sformatf("Failed to write MLDSA_MSG[%0d] for KAT %0d", j, i)); + end else begin + `uvm_info("REG_WRITE_PASS", $sformatf("Successfully wrote MLDSA_MSG[%0d]: %h", j, kat_MSG[j]), UVM_LOW); + end + end + + // Writing the SIGNATURE into the MLDSA_SIGNATURE register array + for (int j = 0; j < reg_model.MLDSA_SIGNATURE.m_mem.get_size(); j++) begin + reg_model.MLDSA_SIGNATURE.m_mem.write(status, j, kat_SIG[j], UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGNATURE[%0d]", j)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGNATURE[%0d] written with %0h", j, kat_SIG[j]), UVM_LOW); + end + end + + data = 'h0000_0003; // Perform verification operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + valid = 0; + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_HIGH); + end + valid = data[1]; + end + + // Reading MLDSA_VERIFY_RES register + foreach (reg_model.MLDSA_VERIFY_RES[j]) begin + reg_model.MLDSA_VERIFY_RES[j].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_VERIFY_RES[%0d]", j)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_VERIFY_RES[%0d]: %0h", j, data), UVM_LOW); + end + + if (data !== VERIFY_RES[j]) begin + `uvm_error("VALIDATION_FAIL", $sformatf("SIG mismatch for KAT %0d at index %0d: Expected %h, Got %h", i, j, SIG[j], data)); + end else begin + `uvm_info("VALIDATION_PASS", $sformatf("SIG match for KAT %0d at index %0d: %h", i, j, data), UVM_LOW); + end + end + + + data = 'h0000_0008; // Perform zeorization operation + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h and zeroized", data), UVM_LOW); + end + end + + + `uvm_info("KAT", $sformatf("signing KAT validation completed"), UVM_LOW); + + + endtask + + + + + endclass + + + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/example_derived_test_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/example_derived_test_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..32b1733ebd57a332ea3a8dd3e498f996e49bb1d6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/example_derived_test_sequence.svh @@ -0,0 +1,253 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in example_derived_test. +// It is an example of a sequence that is extended from %(benchName)_bench_sequence_base +// and can override %(benchName)_bench_sequence_base. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils(example_derived_test_sequence); + + function new(string name = ""); + super.new(name); + endfunction + + virtual task body(); + bit [31:0] data; + bit ready; + bit valid; + bit [7:0][31:0] seed; + reg_model.reset(); + data =0; + ready =0; + valid =0; + seed[0] = 32'h38359FBC; + seed[1] = 32'hD79582CF; + seed[2] = 32'hFE609E13; + seed[3] = 32'h7EE2EFE8; + seed[4] = 32'hA8DBCBAD; + seed[5] = 32'h18BA92BB; + seed[6] = 32'h433AB4F0; + seed[7] = 32'h9B49299D; + #400; + + + if (reg_model.default_map == null) begin + `uvm_fatal("MAP_ERROR", "mldsa_uvm_rm.default_map map is not initialized"); + end else begin + `uvm_info("MAP_INIT", "mldsa_uvm_rm.default_map is initialized", UVM_LOW); + end + + // --------------------------------------------------------- + // KEYGEN TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_LOW); + end + ready = data[0]; + end + + // Writing MLDSA_SEED register + foreach (reg_model.MLDSA_SEED[i]) begin + data = seed[i]; // example data + reg_model.MLDSA_SEED[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SEED[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SEED[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0001; // generate keys + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_LOW); + end + valid = data[1]; + end + + // Reading MLDSA_PUBKEY register + //foreach (reg_model.MLDSA_PUBKEY[i]) begin + // reg_model.MLDSA_PUBKEY[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + // if (status != UVM_IS_OK) begin + // `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PUBKEY[%0d]", i)); + // end else begin + // `uvm_info("REG_READ", $sformatf("MLDSA_PUBKEY[%0d]: %0h", i, data), UVM_LOW); + // end + //end + + // Reading MLDSA_PRIVKEY_OUT register + //foreach (reg_model.MLDSA_PRIVKEY_OUT[i]) begin + // reg_model.MLDSA_PRIVKEY_OUT[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + // if (status != UVM_IS_OK) begin + // `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_PRIVKEY_OUT[%0d]", i)); + // end else begin + // `uvm_info("REG_READ", $sformatf("MLDSA_PRIVKEY_OUT[%0d]: %0h", i, data), UVM_LOW); + // end + //end + // --------------------------------------------------------- + // KEYGEN TEST IS DONE + // --------------------------------------------------------- +/* + // --------------------------------------------------------- + // SIGNING TEST + // --------------------------------------------------------- + + while(!ready) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_LOW); + end + ready = data[0]; + end + + // Writing MLDSA_MSG register + foreach (reg_model.MLDSA_MSG[i]) begin + data = 'h1122_3344; // example data + reg_model.MLDSA_MSG[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_MSG[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_MSG[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_SIGN_RND register + foreach (reg_model.MLDSA_SIGN_RND[i]) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_SIGN_RND[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGN_RND[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGN_RND[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_PRIVKEY_IN register + for(int i = 0; i < reg_model.MLDSA_PRIVKEY_IN.m_mem.get_size(); i++) begin + data = 'h0000_0000; // example data + reg_model.MLDSA_PRIVKEY_IN.m_mem.write(status, i, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PRIVKEY_IN[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PRIVKEY_IN[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0002; // generate singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + while(!valid) begin + reg_model.MLDSA_STATUS.read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_STATUS")); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_STATUS: %0h", data), UVM_LOW); + end + valid = data[1]; + end + + // Reading MLDSA_SIGNATURE register + foreach (reg_model.MLDSA_SIGNATURE[i]) begin + reg_model.MLDSA_SIGNATURE[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_SIGNATURE[%0d]: %0h", i, data), UVM_LOW); + end + end + + // --------------------------------------------------------- + // SIGNING TEST IS DONE + // --------------------------------------------------------- +*/ + // --------------------------------------------------------- + // VERIFIACTION TEST + // --------------------------------------------------------- +/* + // Writing MLDSA_SIGNATURE register + foreach (reg_model.MLDSA_SIGNATURE[i]) begin + data = 'h1122_3344; // example data + reg_model.MLDSA_SIGNATURE[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_SIGNATURE[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_SIGNATURE[%0d] written with %0h", i, data), UVM_LOW); + end + end + + // Writing MLDSA_PRIVKEY_IN register + foreach (reg_model.MLDSA_PUBKEY[i]) begin + data = 'h1122_3344; // example data + reg_model.MLDSA_PUBKEY[i].write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_PUBKEY[%0d]", i)); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_PUBKEY[%0d] written with %0h", i, data), UVM_LOW); + end + end + + data = 'h0000_0003; // generate singature + reg_model.MLDSA_CTRL.write(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_WRITE", $sformatf("Failed to write MLDSA_CTRL")); + end else begin + `uvm_info("REG_WRITE", $sformatf("MLDSA_CTRL written with %0h", data), UVM_LOW); + end + + // Reading MLDSA_VERIFY_RES register + foreach (reg_model.MLDSA_VERIFY_RES[i]) begin + reg_model.MLDSA_VERIFY_RES[i].read(status, data, UVM_FRONTDOOR, reg_model.default_map, this); + if (status != UVM_IS_OK) begin + `uvm_error("REG_READ", $sformatf("Failed to read MLDSA_VERIFY_RES[%0d]", i)); + end else begin + `uvm_info("REG_READ", $sformatf("MLDSA_VERIFY_RES[%0d]: %0h", i, data), UVM_LOW); + end + end + // --------------------------------------------------------- + // VERIFIACTION TEST IS DONE + // --------------------------------------------------------- +*/ + + endtask +endclass + + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/mldsa_bench_sequence_base.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/mldsa_bench_sequence_base.svh new file mode 100644 index 0000000000000000000000000000000000000000..05bb56fafb83f628d437e860a8e490fdff3ae21c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/mldsa_bench_sequence_base.svh @@ -0,0 +1,197 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This file contains the top level and utility sequences +// used by test_top. It can be extended to create derivative top +// level sequences. +// +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// + + +typedef mldsa_env_configuration mldsa_env_configuration_t; + +class mldsa_bench_sequence_base extends uvmf_sequence_base #(uvm_sequence_item); + + `uvm_object_utils( mldsa_bench_sequence_base ); + + // pragma uvmf custom sequences begin + +typedef mldsa_env_sequence_base #( + .CONFIG_T(mldsa_env_configuration_t) + ) + mldsa_env_sequence_base_t; +rand mldsa_env_sequence_base_t mldsa_env_seq; + + + + // UVMF_CHANGE_ME : Instantiate, construct, and start sequences as needed to create stimulus scenarios. + // Instantiate sequences here + // pragma uvmf custom sequences end + + // Sequencer handles for each active interface in the environment + + // Sequencer handles for each QVIP interface + mvc_sequencer uvm_test_top_environment_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_sqr; + + // Top level environment configuration handle + mldsa_env_configuration_t top_configuration; + + // Configuration handles to access interface BFM's + // Local handle to register model for convenience + mldsa_reg_model_top reg_model; + uvm_status_e status; + + // pragma uvmf custom class_item_additional begin + bit [31:0] data; + bit [31:0] SEED [0:7]; //32 Bytes + bit [31:0] SK []; //4896 Bytes + bit [31:0] PK []; //2592 Bytes + bit [31:0] MSG [0:15]; //64 Bytes + bit [31:0] SIG []; //4628 Bytes + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + function new( string name = "" ); + super.new( name ); + // Retrieve the configuration handles from the uvm_config_db + + // Retrieve top level configuration handle + if ( !uvm_config_db#(mldsa_env_configuration_t)::get(null,UVMF_CONFIGURATIONS, "TOP_ENV_CONFIG",top_configuration) ) begin + `uvm_info("CFG", "*** FATAL *** uvm_config_db::get can not find TOP_ENV_CONFIG. Are you using an older UVMF release than what was used to generate this bench?",UVM_NONE); + `uvm_fatal("CFG", "uvm_config_db#(mldsa_env_configuration_t)::get cannot find resource TOP_ENV_CONFIG"); + end + + // Retrieve config handles for all agents + + // Assign the sequencer handles from the handles within agent configurations + + // Retrieve QVIP sequencer handles from the uvm_config_db + if( !uvm_config_db #(mvc_sequencer)::get( null,UVMF_SEQUENCERS,"uvm_test_top.environment.qvip_ahb_lite_slave_subenv.ahb_lite_slave_0", uvm_test_top_environment_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_sqr) ) + `uvm_warning("CFG" , "uvm_config_db #( mvc_sequencer )::get cannot find resource ahb_lite_slave_0" ) + reg_model = top_configuration.mldsa_rm; + if (reg_model == null) begin + `uvm_fatal("CFG", "reg_model is null. Ensure that the register model is properly initialized."); + end + + + // pragma uvmf custom new begin + // Construct arrays + SK = new[1224]; + PK = new[648]; + SIG = new[1157]; + // pragma uvmf custom new end + + endfunction + + // **************************************************************************** + virtual task body(); + // pragma uvmf custom body begin + + // Construct sequences here + + mldsa_env_seq = mldsa_env_sequence_base_t::type_id::create("mldsa_env_seq"); + + fork + join + reg_model.reset(); + // Start RESPONDER sequences here + fork + join_none + // Start INITIATOR sequences here + fork + join + +mldsa_env_seq.start(top_configuration.vsqr); + + // UVMF_CHANGE_ME : Extend the simulation XXX number of clocks after + // the last sequence to allow for the last sequence item to flow + // through the design. + fork + join + + // pragma uvmf custom body end + endtask + + function void read_line(int fd, int bit_length_words, ref bit [31:0] array []); + string line; + int words_read; + bit [31:0] word; + bit [31:0] reversed_word; + + // Read the data from the file line by line + words_read = 0; + while (!$feof(fd) && words_read < bit_length_words) begin + line = ""; + void'($fgets(line, fd)); // Read a line from the file + while ($sscanf(line, "%08x", word) == 1) begin + reversed_word = {word[7:0], word[15:8], word[23:16], word[31:24]}; + array[(bit_length_words-1)-words_read] = reversed_word; + words_read++; + // Remove the parsed part from the line + line = line.substr(8); + end + end + endfunction + + function void write_file(int fd, int bit_length_words, bit [31:0] array []); + int i; + int words_to_write; + + // Write the data from the array to the file + words_to_write = bit_length_words; + for (i = 0; i < words_to_write; i++) begin + $fwrite(fd, "%02X%02X%02X%02X", array[(words_to_write-1)-i][7:0], array[(words_to_write-1)-i][15:8], + array[(words_to_write-1)-i][23:16],array[(words_to_write-1)-i][31:24]); + end + $fwrite(fd, "\n"); + + endfunction + + function void write_file_without_newline(int fd, int bit_length_words, bit [31:0] array []); + int i; + int words_to_write; + + // Write the data from the array to the file + words_to_write = bit_length_words; + for (i = 0; i < words_to_write-1; i++) begin + $fwrite(fd, "%02X%02X%02X%02X", array[(words_to_write-1)-i][7:0], array[(words_to_write-1)-i][15:8], + array[(words_to_write-1)-i][23:16],array[(words_to_write-1)-i][31:24]); + end + + endfunction + + function void parse_hex_to_array(string hex_data, ref bit [31:0] array []); + int hex_len; + int bit_length_words; + bit [31:0] word; + bit [31:0] reversed_word; + string chunk; + + // Calculate the number of words from the length of the hexadecimal string + hex_len = hex_data.len(); + bit_length_words = hex_len / 8; + array = new[bit_length_words]; + + // Parse the hexadecimal string into the array + for (int i = 0; i < bit_length_words; i++) begin + chunk = hex_data.substr((hex_len - 8 * (i + 1)), (hex_len - 8 * i - 1)); + void'($sscanf(chunk, "%08x", word)); + reversed_word = {word[7:0], word[15:8], word[23:16], word[31:24]}; + // Reverse the order of the words as well as their bytes + array[i] = reversed_word; + end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/register_test_sequence.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/register_test_sequence.svh new file mode 100644 index 0000000000000000000000000000000000000000..c839963ccd81d19441385dd6a096ce2d5747817b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/sequences/src/register_test_sequence.svh @@ -0,0 +1,73 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains the top level sequence used in register_test. +// It uses the UVM built in register test. Specific UVM built-in tests can be +// selected in the body task. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test_sequence extends mldsa_bench_sequence_base; + + `uvm_object_utils( register_test_sequence ); + + uvm_reg_mem_built_in_seq uvm_register_test_seq; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + // **************************************************************************** + virtual task body(); + uvm_register_test_seq = new("uvm_register_test_seq"); + + // Reset the DUT + fork + // pragma uvmf custom register_test_reset begin + // UVMF_CHANGE_ME + // Select the desired wait_for_reset or provide custom mechanism. + // fork-join for this code block may be unnecessary based on your situation. + // pragma uvmf custom register_test_reset end + join + + // pragma uvmf custom register_test_setup begin + // UVMF_CHANGE_ME perform potentially necessary operations before running the sequence. + // pragma uvmf custom register_test_setup end + + // Reset the register model + reg_model.reset(); + // Identify the register model to test + uvm_register_test_seq.model = reg_model; + // Perform the register test + // Disable particular tests in sequence by commenting options below + uvm_register_test_seq.tests = { + // pragma uvmf custom register_test_operation begin + UVM_DO_REG_HW_RESET | + UVM_DO_REG_BIT_BASH | + UVM_DO_REG_ACCESS | + UVM_DO_MEM_ACCESS | + UVM_DO_SHARED_ACCESS | + UVM_DO_MEM_WALK | + UVM_DO_ALL_REG_MEM_TESTS + // pragma uvmf custom register_test_operation end + }; + + uvm_register_test_seq.start(null); + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.compile new file mode 100644 index 0000000000000000000000000000000000000000..6871463254afb442a96b9864d53489734aced82a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.compile @@ -0,0 +1,8 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.compile + - ../parameters/mldsa_parameters_pkg.compile +src: + - hdl_top.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..ca023b7df877e08c0b11eaebe7ede19cdbeacc10 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.sv @@ -0,0 +1,164 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// Description: This top level module instantiates all synthesizable +// static content. This and tb_top.sv are the two top level modules +// of the simulation. +// +// This module instantiates the following: +// DUT: The Design Under Test +// Interfaces: Signal bundles that contain signals connected to DUT +// Driver BFM's: BFM's that actively drive interface signals +// Monitor BFM's: BFM's that passively monitor interface signals +// +//---------------------------------------------------------------------- + +//---------------------------------------------------------------------- +// + +module hdl_top; + +import mldsa_parameters_pkg::*; +import qvip_ahb_lite_slave_params_pkg::*; +import uvmf_base_pkg_hdl::*; +import uvm_pkg::*; +`ifdef CALIPTRA +import kv_defines_pkg::*; +`endif + + // pragma attribute hdl_top partition_module_xrtl + hdl_qvip_ahb_lite_slave + #( + .AHB_LITE_SLAVE_0_ACTIVE(1), + .UNIQUE_ID("uvm_test_top.environment.qvip_ahb_lite_slave_subenv."), + .EXT_CLK_RESET(1) + ) uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl(); + +// pragma uvmf custom clock_generator begin + bit clk; + // Instantiate a clk driver + // tbx clkgen + initial begin + clk = 0; + #0ns; + forever begin + clk = ~clk; + #5ns; + end + end +// pragma uvmf custom clock_generator end + +// pragma uvmf custom reset_generator begin + bit rst; + uvm_event ev; + initial begin + ev = uvm_event_pool::get_global("ev_rst"); + rst = 0; + #200ns; + rst = 1; + while(1) begin // On the fly reset + `uvm_info("HDL_TOP_TB",$sformatf(" waiting for the reset event trigger"),UVM_LOW) + // waiting for event trigger + ev.wait_trigger; + `uvm_info("HDL_TOP",$sformatf(" the reset event got triggered"),UVM_LOW) + rst = 0; + #200ns; + rst = 1; + end + end + +`ifdef CALIPTRA + var kv_rd_resp_t kv_rd_resp; + initial begin + kv_rd_resp = '{default:0}; + end +`endif + + // pragma uvmf custom dut_instantiation begin + // AHB Clock/reset + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.default_clk_gen_CLK = clk; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.default_reset_gen_RESET = rst; + + mldsa_mem_if mldsa_memory_export(); + + // SRAM module + mldsa_mem_top + mldsa_mem_top_inst + ( + .clk_i(clk), + .mldsa_memory_export + ); + + // DUT + mldsa_top #( + .AHB_ADDR_WIDTH(18), + .AHB_DATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH), + .CLIENT_DATA_WIDTH(32) + ) + dut + ( + .clk (clk), + .rst_b (rst), + + .haddr_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HADDR[17:0]), + .hwdata_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HWDATA ), + .hsel_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HSEL ), + .hwrite_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HWRITE ), + .hready_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HREADYOUT ), + .htrans_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HTRANS ), + .hsize_i (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HSIZE ), + .hresp_o (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HRESP ), + .hreadyout_o(uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HREADY ), + .hrdata_o (uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HRDATA ), + .mldsa_memory_export, +`ifdef CALIPTRA + .kv_read(), + .kv_rd_resp(kv_rd_resp), +`endif + .debugUnlock_or_scan_mode_switch('0), + .busy_o(), + .error_intr(), + .notif_intr() + ); + + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HBURST = 3'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HPROT = 7'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HMASTLOCK = 1'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HNONSEC = 1'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HAUSER = 64'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HWUSER = 64'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HRUSER = 64'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_mult_HSEL = 16'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HEXCL = 1'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HMASTER = 16'b0; + assign uvm_test_top_environment_qvip_ahb_lite_slave_subenv_qvip_hdl.ahb_lite_slave_0_HEXOKAY = 1'b0; + + + initial begin + import uvm_pkg::uvm_config_db; + end + +endmodule + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..1b7c8112ef8eb97c4fdb6854a0656bf8a96f2328 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hdl_top.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_PROJECT_DIR/rtl/verilog/verilog_dut.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/mldsa_parameters_pkg.vinfo +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.vinfo +hdl_top.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.compile new file mode 100644 index 0000000000000000000000000000000000000000..5bb8b70d66ce6fa5083d37d77f6130a682ccb055 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.compile @@ -0,0 +1,8 @@ +incdir: + - ${uvm_path}/src + - . +needs: + - $UVMF_HOME/common/utility_packages/qvip_utils_pkg/qvip_utils_pkg.compile + - ../tests/mldsa_tests_pkg.compile +src: + - hvl_top.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..62dd0e9dc17b1791363e87e37387c1e6ef60dd4e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.sv @@ -0,0 +1,33 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This module loads the test package and starts the UVM phases. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +module hvl_top; + +import uvm_pkg::*; +import mldsa_tests_pkg::*; + + // pragma uvmf custom module_item_additional begin + // pragma uvmf custom module_item_additional end + + initial begin + $timeformat(-9,3,"ns",5); + run_test(); + end + +endmodule + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..09b95f0ebd4e1d4feed51dc06ea1b9aac4985f11 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/hvl_top.vinfo @@ -0,0 +1,2 @@ +@use $UVMF_PROJECT_DIR/tb/tests/mldsa_tests_pkg.vinfo +hvl_top.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/top_filelist_hdl.f b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/top_filelist_hdl.f new file mode 100644 index 0000000000000000000000000000000000000000..1e9dab6534f1419cd2c2c4b9ec5b9d71fc217c64 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/top_filelist_hdl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hdl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/top_filelist_hvl.f b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/top_filelist_hvl.f new file mode 100644 index 0000000000000000000000000000000000000000..42383ab2dce9ebb4c807b5c1bb9c2cfb1a2b4fee --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/testbench/top_filelist_hvl.f @@ -0,0 +1,3 @@ +$UVMF_PROJECT_DIR/tb/testbench/hvl_top.sv +// pragma uvmf custom additional begin +// pragma uvmf custom additional end diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.compile new file mode 100644 index 0000000000000000000000000000000000000000..a70865970ae24ac94976b10d5e43e02ad39f008f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + - ../../../../verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.compile + - ../parameters/mldsa_parameters_pkg.compile + - ../sequences/mldsa_sequences_pkg.compile +src: + - mldsa_tests_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..1926d7502d773be52ae21ee1926cbb3f029e24ac --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.sv @@ -0,0 +1,67 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This package contains all tests currently written for +// the simulation project. Once compiled, any test can be selected +// from the vsim command line using +UVM_TESTNAME=yourTestNameHere +// +// CONTAINS: +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package mldsa_tests_pkg; + + import uvm_pkg::*; + import uvmf_base_pkg::*; + import mldsa_parameters_pkg::*; + import mldsa_env_pkg::*; + import mldsa_sequences_pkg::*; + import qvip_ahb_lite_slave_pkg::*; + import QUESTA_MVC::*; + import qvip_utils_pkg::*; + import mvc_pkg::*; + import mgc_ahb_v2_0_pkg::*; + + + `include "uvm_macros.svh" + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + `include "src/test_top.svh" + `include "src/register_test.svh" + `include "src/example_derived_test.svh" + `include "src/ML_DSA_randomized_key_gen_test.svh" + `include "src/ML_DSA_randomized_zeroize_test.svh" + `include "src/ML_DSA_randomized_early_run_test.svh" + `include "src/ML_DSA_randomized_key_gen_and_sign_test.svh" + `include "src/ML_DSA_randomized_sign_gen_test.svh" + `include "src/ML_DSA_randomized_reset_test.svh" + `include "src/ML_DSA_keygen_KATs_test.svh" + `include "src/ML_DSA_keygen_signing_KATs_test.svh" + `include "src/ML_DSA_verif_KATs_test.svh" + `include "src/ML_DSA_randomized_verif_test.svh" + `include "src/ML_DSA_randomized_verif_fail_test.svh" + `include "src/ML_DSA_randomized_all_test.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new tests to the src directory + // be sure to add the test file here so that it will be + // compiled as part of the test package. Be sure to place + // the new test after any base tests of the new test. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..2311092d2665891d15425bb9f1b3dbdfc704794a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/mldsa_tests_pkg.vinfo @@ -0,0 +1,6 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +@use $UVMF_VIP_LIBRARY_HOME/environment_packages/mldsa_env_pkg/mldsa_env_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/parameters/mldsa_parameters_pkg.vinfo +@use $UVMF_PROJECT_DIR/tb/sequences/mldsa_sequences_pkg.vinfo ++incdir+@vinfodir +mldsa_tests_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_KATs_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_KATs_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..5fdcb3a894ba41a2b81ede97380e8be76886d522 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_KATs_test.svh @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// Test uses a random seed to generate a public and private key pair +// Next it signs a random message with the private key +// Next it verifies that signature using the public key +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_keygen_KATs_test extends test_top; + + `uvm_component_utils(ML_DSA_keygen_KATs_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_keygen_KATs_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_keygen_KATs_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_keygen_KATs_sequence + ML_DSA_keygen_KATs_sequence seq; + seq = ML_DSA_keygen_KATs_sequence::type_id::create("ML_DSA_keygen_KATs_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_KATs_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_KATs_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..5b479ed1e30f17d1d25b95af2ba83ec4888ddc04 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_KATs_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_keygen_KATs_test' +testname: ML_DSA_keygen_KATs_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_signing_KATs_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_signing_KATs_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..ed8c209ce53cfc368b6c76f5dfa596868cb87235 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_signing_KATs_test.svh @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// Test uses a random seed to generate a public and private key pair +// Next it signs a random message with the private key +// Next it verifies that signature using the public key +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_keygen_signing_KATs_test extends test_top; + + `uvm_component_utils(ML_DSA_keygen_signing_KATs_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_keygen_signing_KATs_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_keygen_signing_KATs_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_keygen_signing_KATs_sequence + ML_DSA_keygen_signing_KATs_sequence seq; + seq = ML_DSA_keygen_signing_KATs_sequence::type_id::create("ML_DSA_keygen_signing_KATs_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_signing_KATs_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_signing_KATs_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..33c7f10646dbea7d5b20635fc22ae145251fe85f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_keygen_signing_KATs_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_keygen_signing_KATs_test' +testname: ML_DSA_keygen_signing_KATs_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_all_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_all_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..34fdf33ec1004e69af8a4e1e9b53f94fb15eeb18 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_all_test.svh @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// Test uses a random seed to generate a public and private key pair +// Next it signs a random message with the private key +// Next it verifies that signature using the public key +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_all_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_all_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_all_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_all_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_all_sequence + ML_DSA_randomized_all_sequence seq; + seq = ML_DSA_randomized_all_sequence::type_id::create("ML_DSA_randomized_all_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_all_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_all_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..b612043c189a4f7433dba45223dea417e393a88e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_all_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_all_test' +testname: ML_DSA_randomized_all_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_early_run_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_early_run_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..9c1b06eaef44be92ea7f78023ef49755939aaf48 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_early_run_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_early_run_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_early_run_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_early_run_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_early_run_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_early_run_sequence + ML_DSA_randomized_early_run_sequence seq; + seq = ML_DSA_randomized_early_run_sequence::type_id::create("ML_DSA_randomized_early_run_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_early_run_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_early_run_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..70e99678f87edb67dc564343025c364044a8455d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_early_run_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_early_run_test' +testname: ML_DSA_randomized_early_run_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..8b912a167c7db4d4f0675f8aa829402c55dc701c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_key_gen_and_sign_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_key_gen_and_sign_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_key_gen_and_sign_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_key_gen_and_sign_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_key_gen_and_sign_sequence + ML_DSA_randomized_key_gen_and_sign_sequence seq; + seq = ML_DSA_randomized_key_gen_and_sign_sequence::type_id::create("ML_DSA_randomized_key_gen_and_sign_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..0654476aa0e2fc363bf67364cf2a5d9472667256 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_and_sign_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_key_gen_and_sign_test' +testname: ML_DSA_randomized_key_gen_and_sign_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..5ca1f34d498ad42c42f8b4db7866f5447268f9ba --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_key_gen_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_key_gen_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_key_gen_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_key_gen_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_key_gen_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_key_gen_sequence + ML_DSA_randomized_key_gen_sequence seq; + seq = ML_DSA_randomized_key_gen_sequence::type_id::create("ML_DSA_randomized_key_gen_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_reset_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_reset_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..e162c3b46c7acbdfde7825449102a19468c80fd6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_reset_test.svh @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// Test uses a random seed to generate a public and private key pair +// Next it signs a random message with the private key +// Next it verifies that signature using the public key +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_reset_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_reset_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_reset_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_reset_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_reset_sequence + ML_DSA_randomized_reset_sequence seq; + seq = ML_DSA_randomized_reset_sequence::type_id::create("ML_DSA_randomized_reset_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_reset_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_reset_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..e124ff60b570905bb1d80a8f186863b02ae160f1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_reset_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_reset_test' +testname: ML_DSA_randomized_reset_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_sign_gen_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_sign_gen_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..a65e7bc16ee53385100b465971e883733c587e58 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_sign_gen_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_sign_gen_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_sign_gen_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_sign_gen_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_sign_gen_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_sign_gen_sequence + ML_DSA_randomized_sign_gen_sequence seq; + seq = ML_DSA_randomized_sign_gen_sequence::type_id::create("ML_DSA_randomized_sign_gen_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_fail_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_fail_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..53587ed6b837a5d9bcff577c328824a26a36faa2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_fail_test.svh @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_verif_fail_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_verif_fail_test); + + + bit expect_verif_failure; + bit expect_predictor_verif_failure; + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_verif_fail_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_verif_fail_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + + expect_verif_failure = 1; + expect_predictor_verif_failure = 1; + + uvm_config_db#(bit)::set(null, "*", "expect_verif_failure", expect_verif_failure); + uvm_config_db#(bit)::set(null, "*", "expect_predictor_verif_failure", expect_predictor_verif_failure); + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_verif_fail_sequence + ML_DSA_randomized_verif_fail_sequence seq; + seq = ML_DSA_randomized_verif_fail_sequence::type_id::create("ML_DSA_randomized_verif_fail_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_fail_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_fail_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..86053a0989d09508f41289df61a76f632686b638 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_fail_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +# seed: 4098270334 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_verif_fail_test' +testname: ML_DSA_randomized_verif_fail_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..9eeb6b6ec48f06fd27a511ce829e697de18e94a8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_verif_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_verif_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_verif_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_verif_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_verif_sequence + ML_DSA_randomized_verif_sequence seq; + seq = ML_DSA_randomized_verif_sequence::type_id::create("ML_DSA_randomized_verif_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..5dcb0ac7edd725d6b63b8fa92bbeb6772d895bc6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_verif_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +# seed: 4098270334 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_verif_test' +testname: ML_DSA_randomized_verif_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_zeroize_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_zeroize_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..b58c38e7ee2b904007f60216b0590af9ba05f8d4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_zeroize_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_randomized_zeroize_test extends test_top; + + `uvm_component_utils(ML_DSA_randomized_zeroize_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_randomized_zeroize_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_randomized_zeroize_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_randomized_zeroize_sequence + ML_DSA_randomized_zeroize_sequence seq; + seq = ML_DSA_randomized_zeroize_sequence::type_id::create("ML_DSA_randomized_zeroize_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_zeroize_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_zeroize_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..faa2c5b21af0fd08c7bfd38d04ca57bdb11e22e9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_randomized_zeroize_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_zeroize_test' +testname: ML_DSA_randomized_zeroize_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..dc2882309da4465f70e7a4610c48380213f39399 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_test.svh @@ -0,0 +1,52 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// Test uses a random seed to generate a public and private key pair +// Next it signs a random message with the private key +// Next it verifies that signature using the public key +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class ML_DSA_verif_KATs_test extends test_top; + + `uvm_component_utils(ML_DSA_verif_KATs_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the ML_DSA_verif_KATs_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(ML_DSA_verif_KATs_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the ML_DSA_verif_KATs_sequence + ML_DSA_verif_KATs_sequence seq; + seq = ML_DSA_verif_KATs_sequence::type_id::create("ML_DSA_verif_KATs_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..a919f54ec114480778eecbbdf6df9aee408841d9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/ML_DSA_verif_KATs_test.yml @@ -0,0 +1,8 @@ +--- +# Random seed desired... +#seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_verif_KATs_test' +testname: ML_DSA_verif_KATs_test +parameters: + dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/abr_example_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/abr_example_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..d3145f6f5b08f0b0ac98ae87e0888078caff53cd --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/abr_example_test.yml @@ -0,0 +1,18 @@ +--- +# Random seed desired... +seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_key_gen_test' +testname: ML_DSA_randomized_key_gen_test +parameters: + dilithium_command: "test_dilithium5" +#plusargs: +# - '+UVM_TESTNAME=ML_DSA_randomized_sign_gen_test' +#testname: ML_DSA_randomized_sign_gen_test +#parameters: +# dilithium_command: "test_dilithium5" +#plusargs: +# - '+UVM_TESTNAME=ML_DSA_randomized_verif_test' +#testname: ML_DSA_randomized_verif_test +#parameters: +# dilithium_command: "test_dilithium5" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/abr_example_test.yml.orig b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/abr_example_test.yml.orig new file mode 100644 index 0000000000000000000000000000000000000000..2dc26612b8dab530d9da71c67b43d783164a7fa2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/abr_example_test.yml.orig @@ -0,0 +1,32 @@ +--- +# Random seed desired... +<<<<<<< HEAD +#seed: 1 +#plusargs: +# - '+UVM_TESTNAME=ML_DSA_randomized_key_gen_test' +#testname: ML_DSA_randomized_key_gen_test +#parameters: +# dilithium_command: "test_dilithium5" +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_sign_gen_test' +testname: ML_DSA_randomized_sign_gen_test +parameters: + dilithium_command: "test_dilithium5" +======= +seed: 1 +plusargs: + - '+UVM_TESTNAME=ML_DSA_randomized_key_gen_test' +testname: ML_DSA_randomized_key_gen_test +parameters: + dilithium_command: "test_dilithium5" +#plusargs: +# - '+UVM_TESTNAME=ML_DSA_randomized_sign_gen_test' +#testname: ML_DSA_randomized_sign_gen_test +#parameters: +# dilithium_command: "test_dilithium5" +>>>>>>> main +#plusargs: +# - '+UVM_TESTNAME=ML_DSA_randomized_verif_test' +#testname: ML_DSA_randomized_verif_test +#parameters: +# dilithium_command: "test_dilithium5" \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/example_derived_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/example_derived_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..461c6a5ae22a6d03d7675581ad7741d796ab5862 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/example_derived_test.svh @@ -0,0 +1,51 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class example_derived_test extends test_top; + + `uvm_component_utils(example_derived_test); + + function new(string name = "", uvm_component parent = null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below is an example of how to replace the mldsa_bench_sequence_base + // sequence with the example_derived_test_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(example_derived_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + // UVMF_CHANGE_ME Test specific configuration values can be set here. + // The configuration structure has already been randomized. + // pragma uvmf custom configuration_settings_post_randomize end + endfunction + + virtual task main_phase(uvm_phase phase); + // Start the example_derived_test_sequence + example_derived_test_sequence seq; + seq = example_derived_test_sequence::type_id::create("example_derived_test_sequence"); + seq.start(null); // You may need to specify a sequencer if your environment requires it + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/register_test.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/register_test.svh new file mode 100644 index 0000000000000000000000000000000000000000..d05180a5ac813ba2727393bacbe3f048a798fd77 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/register_test.svh @@ -0,0 +1,40 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This test extends test_top and makes +// changes to test_top using the UVM factory type_override: +// +// Test scenario: +// This is a template test that can be used to create future tests. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class register_test extends test_top; + + `uvm_component_utils( register_test ); + + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + + virtual function void build_phase(uvm_phase phase); + // The factory override below replaces the mldsa_bench_sequence_base + // sequence with the register_test_sequence. + mldsa_bench_sequence_base::type_id::set_type_override(register_test_sequence::get_type()); + // Execute the build_phase of test_top AFTER all factory overrides have been created. + super.build_phase(phase); + endfunction + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/test_top.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/test_top.svh new file mode 100644 index 0000000000000000000000000000000000000000..1dc72f28e3d5f24bad2f14b4b9042f7b2cfe81d9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/tb/tests/src/test_top.svh @@ -0,0 +1,99 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// Description: This top level UVM test is the base class for all +// future tests created for this project. +// +// This test class contains: +// Configuration: The top level configuration for the project. +// Environment: The top level environment for the project. +// Top_level_sequence: The top level sequence for the project. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +typedef mldsa_env_configuration mldsa_env_configuration_t; +typedef mldsa_environment mldsa_environment_t; + +class test_top extends uvmf_test_base #(.CONFIG_T(mldsa_env_configuration_t), + .ENV_T(mldsa_environment_t), + .TOP_LEVEL_SEQ_T(mldsa_bench_sequence_base)); + + `uvm_component_utils( test_top ); + +// This message handler can be used to redirect QVIP Memeory Model messages through +// the UVM messaging mecahanism. How to enable and use it is described in +// $UVMF_HOME/common/utility_packages/qvip_utils_pkg/src/qvip_report_catcher.svh +qvip_memory_message_handler message_handler; + + + string interface_names[] = { + uvm_test_top_environment_qvip_ahb_lite_slave_subenv_ahb_lite_slave_0 /* ahb_lite_slave_0 [0] */ +}; + +uvmf_active_passive_t interface_activities[] = { + ACTIVE /* ahb_lite_slave_0 [0] */ }; + + // pragma uvmf custom class_item_additional begin + string command; + // pragma uvmf custom class_item_additional end + + // **************************************************************************** + // FUNCTION: new() + // This is the standard systemVerilog constructor. All components are + // constructed in the build_phase to allow factory overriding. + // + function new( string name = "", uvm_component parent = null ); + super.new( name ,parent ); + endfunction + + + + // **************************************************************************** + // FUNCTION: build_phase() + // The construction of the configuration and environment classes is done in + // the build_phase of uvmf_test_base. Once the configuraton and environment + // classes are built then the initialize call is made to perform the + // following: + // Monitor and driver BFM virtual interface handle passing into agents + // Set the active/passive state for each agent + // Once this build_phase completes, the build_phase of the environment is + // executed which builds the agents. + // + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + // pragma uvmf custom configuration_settings_post_randomize begin + + // Initialize the command with a default value + command = "test_dilithium5"; + + // Check for the command line argument and update the command string + if ($test$plusargs("DILITHIUM_COMMAND")) begin + string arg_value; + if ($value$plusargs("DILITHIUM_COMMAND=%s", arg_value)) begin + command = arg_value; + end + end + + `uvm_info("TEST_TOP", $sformatf("DILITHIUM_COMMAND set to: %s", command), UVM_LOW) + + // Set the configuration parameter for the environment using wildcard + uvm_config_db#(string)::set(null, "*", "dilithium_command", command); + + // pragma uvmf custom configuration_settings_post_randomize end + configuration.initialize(NA, "uvm_test_top.environment", interface_names, null, interface_activities); + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/yaml/mldsa_bench.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/yaml/mldsa_bench.yaml new file mode 100644 index 0000000000000000000000000000000000000000..53dc1bad9a92949866ed0c26e23ad78f2e771e77 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/project_benches/mldsa/yaml/mldsa_bench.yaml @@ -0,0 +1,16 @@ +uvmf: + benches: + mldsa: + active_passive: [] + active_passive_default: ACTIVE + clock_half_period: 5ns + clock_phase_offset: 0ns + existing_library_component: 'True' + imports: + - name: mvc_pkg + - name: mgc_ahb_v2_0_pkg + interface_params: [] + reset_assertion_level: 'False' + reset_duration: 200ns + top_env: mldsa + use_dpi_link: 'False' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/.project b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/.project new file mode 100644 index 0000000000000000000000000000000000000000..ce825b44cf077f4bab8ee94013d14ec768e492c8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/.project @@ -0,0 +1,32 @@ + + + mldsa_env_pkg + + + + + + org.python.pydev.PyDevBuilder + + + + + net.sf.sveditor.core.SVProjectBuilder + + + + + + net.sf.sveditor.core.SVNature + org.python.pydev.pythonNature + + + + + + UVMF_VIP_LIBRARY_HOME + $%7BPARENT-2-PROJECT_LOC%7D + + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/.svproject b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/.svproject new file mode 100644 index 0000000000000000000000000000000000000000..fd93a143b08eea928ffa6ba69b8656e0ef7c67bf --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/.svproject @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/Makefile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..3a792ceed139aa1963bc7ef13fe642dac9bfb8ab --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/Makefile @@ -0,0 +1,57 @@ +# mldsa environment packages source and make target + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + +# Include all requisite sub-environment package targets for this bench + +mldsa_ENV_PKG =\ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv \ + $(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv + +COMP_mldsa_PKG_TGT_0 = q_comp_mldsa_env_pkg +COMP_mldsa_PKG_TGT_1 = v_comp_mldsa_env_pkg +COMP_mldsa_PKG_TGT = $(COMP_mldsa_PKG_TGT_$(USE_VELOCE)) + +comp_mldsa_env_pkg: $(COMP_mldsa_PKG_TGT) + +q_comp_mldsa_env_pkg: + $(HVL_COMP_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg $(mldsa_ENV_PKG) + +v_comp_mldsa_env_pkg: q_comp_mldsa_env_pkg + $(VELANALYZE_HVL_CMD) +incdir+$(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg $(mldsa_ENV_PKG) + + + +ifeq ($(MTI_VCO_MODE),64) + GCC_COMP_ARCH = -m64 +else + GCC_COMP_ARCH = -m32 +endif + +export mldsa_ENV_DPI_SRC ?= $(UVMF_VIP_LIBRARY_HOME)/environment_packages/mldsa_env_pkg/dpi + +C_FILE_COMPILE_LIST_mldsa_env_pkg = \ + +O_FILE_COMPILE_LIST_mldsa_env_pkg = $(notdir $(C_FILE_COMPILE_LIST_mldsa_env_pkg:.c=.o)) + +GCC_COMP_ARGS_mldsa_env_pkg += -I$(mldsa_ENV_DPI_SRC) \ + -fPIC + +GCC_COMP_ARGS_mldsa_env_pkg += $(mldsa_ENV_GCC_COMP_ARGUMENTS) + +GCC_LINK_ARGS_mldsa_env_pkg += \ + \ + -o .so + +comp_mldsa_env_pkg_c_files: + @echo "--------------------------------" + @echo "Compiling Environment C source" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_COMP_ARGS_mldsa_env_pkg) $(C_FILE_COMPILE_LIST_mldsa_env_pkg) + @echo "--------------------------------" + @echo "Linking Environment C objects into a shared object" + @echo "--------------------------------" + gcc $(GCC_COMP_ARCH) $(GCC_LINK_ARGS_mldsa_env_pkg) $(O_FILE_COMPILE_LIST_mldsa_env_pkg) + @echo "--------------------------------" + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/compile.do b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/compile.do new file mode 100644 index 0000000000000000000000000000000000000000..6806c1f52077852e6f323c5b61773bb7e041179f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/compile.do @@ -0,0 +1,13 @@ +# Tcl do file for compile of mldsa interface + +# pragma uvmf custom additional begin +# pragma uvmf custom additional end + + + +quietly set cmd [format "vlog -timescale 1ps/1ps +incdir+%s/environment_packages/mldsa_env_pkg" $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +quietly set cmd [format "%s %s/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv" $cmd $env(UVMF_VIP_LIBRARY_HOME)] +eval $cmd + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.compile b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.compile new file mode 100644 index 0000000000000000000000000000000000000000..52b65f2c137144d3ae7aa4e9bdae0511ec663d9a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.compile @@ -0,0 +1,7 @@ +needs: + - $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.compile + +src: + - registers/mldsa_reg_model_top_pkg.sv + - mldsa_env_pkg.sv + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..c807ae7fb328e4399fefc451a03c900e89e296e1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.sv @@ -0,0 +1,61 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// PACKAGE: This file defines all of the files contained in the +// environment package that will run on the host simulator. +// +// CONTAINS: +// - +// - +// - +// - +// - +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +package mldsa_env_pkg; + + import uvm_pkg::*; + `include "uvm_macros.svh" + import uvmf_base_pkg::*; + import mvc_pkg::*; + import mgc_ahb_v2_0_pkg::*; + import rw_txn_pkg::*; + import mldsa_reg_model_top_pkg::*; + import qvip_ahb_lite_slave_pkg::*; + import qvip_ahb_lite_slave_params_pkg::*; + + `uvm_analysis_imp_decl(_ahb_slave_0_ae) + `uvm_analysis_imp_decl(_actual_ahb_analysis_export) + `uvm_analysis_imp_decl(_expected_ahb_analysis_export) + + // pragma uvmf custom package_imports_additional begin + // pragma uvmf custom package_imports_additional end + + // Parameters defined as HVL parameters + + `include "src/mldsa_env_typedefs.svh" + `include "src/mldsa_env_configuration.svh" + `include "src/mldsa_predictor.svh" + `include "src/mldsa_scoreboard.svh" + `include "src/mldsa_environment.svh" + `include "src/mldsa_env_sequence_base.svh" + + // pragma uvmf custom package_item_additional begin + // UVMF_CHANGE_ME : When adding new environment level sequences to the src directory + // be sure to add the sequence file here so that it will be + // compiled as part of the environment package. Be sure to place + // the new sequence after any base sequence of the new sequence. + // pragma uvmf custom package_item_additional end + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.vinfo b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.vinfo new file mode 100644 index 0000000000000000000000000000000000000000..c9778b6163ea56059b48806ab2cf0da93a177dce --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg.vinfo @@ -0,0 +1,4 @@ +@use $UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.vinfo +registers/mldsa_reg_model_top_pkg.sv ++incdir+@vinfodir +mldsa_env_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg_sve.F b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg_sve.F new file mode 100644 index 0000000000000000000000000000000000000000..dcbaafffa1e91e81a796fc658f38ac2b5e18ef5e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/mldsa_env_pkg_sve.F @@ -0,0 +1,12 @@ + +// UVM ++incdir+${UVM_HOME}/src +${UVM_HOME}/src/uvm_pkg.sv + +// Common UVMF files +-f ${UVMF_HOME}/common/common_sve.f + +// Sub-Environments + ++incdir+. +./mldsa_env_pkg.sv diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_covergroups.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_covergroups.svh new file mode 100644 index 0000000000000000000000000000000000000000..52c42454b7cbe6d36513ce51f236f1f319b752a1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_covergroups.svh @@ -0,0 +1,464 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef MLDSA_REG_COVERGROUPS + `define MLDSA_REG_COVERGROUPS + + /*----------------------- MLDSA_REG__MLDSA_NAME COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_NAME_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_NAME_fld_cg with function sample( + input bit [32-1:0] NAME + ); + option.per_instance = 1; + NAME_cp : coverpoint NAME; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_VERSION COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_VERSION_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_VERSION_fld_cg with function sample( + input bit [32-1:0] VERSION + ); + option.per_instance = 1; + VERSION_cp : coverpoint VERSION; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_CTRL COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_CTRL_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_CTRL_fld_cg with function sample( + input bit [3-1:0] CTRL, + input bit [1-1:0] ZEROIZE + ); + option.per_instance = 1; + CTRL_cp : coverpoint CTRL; + ZEROIZE_cp : coverpoint ZEROIZE; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_STATUS COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_STATUS_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_STATUS_fld_cg with function sample( + input bit [1-1:0] READY, + input bit [1-1:0] VALID + ); + option.per_instance = 1; + READY_cp : coverpoint READY; + VALID_cp : coverpoint VALID; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_ENTROPY COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_ENTROPY_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_ENTROPY_fld_cg with function sample( + input bit [32-1:0] ENTROPY + ); + option.per_instance = 1; + ENTROPY_cp : coverpoint ENTROPY; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_SEED COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_SEED_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_SEED_fld_cg with function sample( + input bit [32-1:0] SEED + ); + option.per_instance = 1; + SEED_cp : coverpoint SEED; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_SIGN_RND COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_SIGN_RND_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_SIGN_RND_fld_cg with function sample( + input bit [32-1:0] SIGN_RND + ); + option.per_instance = 1; + SIGN_RND_cp : coverpoint SIGN_RND; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_MSG COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_MSG_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_MSG_fld_cg with function sample( + input bit [32-1:0] MSG + ); + option.per_instance = 1; + MSG_cp : coverpoint MSG; + + endgroup + + /*----------------------- MLDSA_REG__MLDSA_VERIFY_RES COVERGROUPS -----------------------*/ + covergroup mldsa_reg__MLDSA_VERIFY_RES_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__MLDSA_VERIFY_RES_fld_cg with function sample( + input bit [32-1:0] VERIFY_RES + ); + option.per_instance = 1; + VERIFY_RES_cp : coverpoint VERIFY_RES; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__GLOBAL_INTR_EN_T COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__global_intr_en_t_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__global_intr_en_t_fld_cg with function sample( + input bit [1-1:0] error_en, + input bit [1-1:0] notif_en + ); + option.per_instance = 1; + error_en_cp : coverpoint error_en; + notif_en_cp : coverpoint notif_en; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__ERROR_INTR_EN_T COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__error_intr_en_t_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__error_intr_en_t_fld_cg with function sample( + input bit [1-1:0] error_internal_en + ); + option.per_instance = 1; + error_internal_en_cp : coverpoint error_internal_en; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__NOTIF_INTR_EN_T COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__notif_intr_en_t_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__notif_intr_en_t_fld_cg with function sample( + input bit [1-1:0] notif_cmd_done_en + ); + option.per_instance = 1; + notif_cmd_done_en_cp : coverpoint notif_cmd_done_en; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_DD3DCF0A COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_fld_cg with function sample( + input bit [1-1:0] agg_sts + ); + option.per_instance = 1; + agg_sts_cp : coverpoint agg_sts; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_E6399B4A COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_fld_cg with function sample( + input bit [1-1:0] agg_sts + ); + option.per_instance = 1; + agg_sts_cp : coverpoint agg_sts; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__ERROR_INTR_T_ERROR_INTERNAL_STS_83ADAB02 COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_fld_cg with function sample( + input bit [1-1:0] error_internal_sts + ); + option.per_instance = 1; + error_internal_sts_cp : coverpoint error_internal_sts; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_DONE_STS_1C68637E COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg with function sample( + input bit [1-1:0] notif_cmd_done_sts + ); + option.per_instance = 1; + notif_cmd_done_sts_cp : coverpoint notif_cmd_done_sts; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__ERROR_INTR_TRIG_T COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__error_intr_trig_t_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__error_intr_trig_t_fld_cg with function sample( + input bit [1-1:0] error_internal_trig + ); + option.per_instance = 1; + error_internal_trig_cp : coverpoint error_internal_trig; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__NOTIF_INTR_TRIG_T COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__notif_intr_trig_t_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__notif_intr_trig_t_fld_cg with function sample( + input bit [1-1:0] notif_cmd_done_trig + ); + option.per_instance = 1; + notif_cmd_done_trig_cp : coverpoint notif_cmd_done_trig; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_60DDFF93 COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93_fld_cg with function sample( + input bit [32-1:0] cnt + ); + option.per_instance = 1; + cnt_cp : coverpoint cnt; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_BE67D6D5 COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5_fld_cg with function sample( + input bit [32-1:0] cnt + ); + option.per_instance = 1; + cnt_cp : coverpoint cnt; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_15E6ED7E COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_fld_cg with function sample( + input bit [1-1:0] pulse + ); + option.per_instance = 1; + pulse_cp : coverpoint pulse; + + endgroup + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_6173128E COVERGROUPS -----------------------*/ + covergroup mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_bit_cg with function sample(input bit reg_bit); + option.per_instance = 1; + reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; + } + reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); + } + + endgroup + covergroup mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_fld_cg with function sample( + input bit [1-1:0] pulse + ); + option.per_instance = 1; + pulse_cp : coverpoint pulse; + + endgroup + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..7b1d13d0361a39e30f496cdefc6d6f5f4e159782 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_model_top_pkg.sv @@ -0,0 +1,255 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// Placeholder for complete register model. This placeholder allows +// compilation of generated environment without modification. +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +package mldsa_reg_model_top_pkg; + + import uvm_pkg::*; +// pragma uvmf custom additional_imports begin + import mldsa_reg_uvm::*; +// pragma uvmf custom additional_imports end + + `include "uvm_macros.svh" + + /* DEFINE REGISTER CLASSES */ +// pragma uvmf custom define_register_classes begin + //-------------------------------------------------------------------- + // Class: mldsa_example_reg0 + // + //-------------------------------------------------------------------- + class mldsa_example_reg0 extends uvm_reg; + `uvm_object_utils(mldsa_example_reg0) + + rand uvm_reg_field example_field; + + // Function: new + // + function new(string name = "mldsa_example_reg0"); + super.new(name, 8, UVM_NO_COVERAGE); + endfunction + + + // Function: build + // + virtual function void build(); + example_field = uvm_reg_field::type_id::create("example_field"); + example_field.configure(this, 8, 0, "RW", 0, 8'h00, 1, 1, 1); + endfunction + endclass + + //-------------------------------------------------------------------- + // Class: mldsa_example_reg1 + // + //-------------------------------------------------------------------- + class mldsa_example_reg1 extends uvm_reg; + `uvm_object_utils(mldsa_example_reg1) + + rand uvm_reg_field example_field; + + // Function: new + // + function new(string name = "mldsa_example_reg1"); + super.new(name, 8, UVM_NO_COVERAGE); + endfunction + + + // Function: build + // + virtual function void build(); + example_field = uvm_reg_field::type_id::create("example_field"); + example_field.configure(this, 8, 0, "RW", 0, 8'h00, 1, 1, 1); + endfunction + endclass +// pragma uvmf custom define_register_classes end + +// pragma uvmf custom define_block_map_coverage_class begin + //-------------------------------------------------------------------- + // Class: mldsa_fixme_map_coverage + // + // Coverage for the 'fixme_map' in 'mldsa_reg_model' + //-------------------------------------------------------------------- + class mldsa_fixme_map_coverage extends uvm_object; + `uvm_object_utils(mldsa_fixme_map_coverage) + + covergroup ra_cov(string name) with function sample(uvm_reg_addr_t addr, bit is_read); + + option.per_instance = 1; + option.name = name; + + ADDR: coverpoint addr { + bins example_reg0 = {'h0}; + bins example_reg1 = {'h1}; + } + + RW: coverpoint is_read { + bins RD = {1}; + bins WR = {0}; + } + + ACCESS: cross ADDR, RW; + + endgroup: ra_cov + + function new(string name = "mldsa_fixme_map_coverage"); + ra_cov = new(name); + endfunction: new + + function void sample(uvm_reg_addr_t offset, bit is_read); + ra_cov.sample(offset, is_read); + endfunction: sample + + endclass: mldsa_fixme_map_coverage + + class mldsa_AHB_map_coverage extends uvm_object; + `uvm_object_utils(mldsa_AHB_map_coverage) + + covergroup ra_cov(string name) with function sample(uvm_reg_addr_t addr, bit is_read); + + option.per_instance = 1; + option.name = name; + + // FIXME + ADDR: coverpoint addr { + bins example_reg0 = {'h0}; + bins example_reg1 = {'h1}; + } + + RW: coverpoint is_read { + bins RD = {1}; + bins WR = {0}; + } + + ACCESS: cross ADDR, RW; + + endgroup: ra_cov + + function new(string name = "mldsa_AHB_map_coverage"); + ra_cov = new(name); + endfunction: new + + function void sample(uvm_reg_addr_t offset, bit is_read); + ra_cov.sample(offset, is_read); + endfunction: sample + + endclass: mldsa_AHB_map_coverage +// pragma uvmf custom define_block_map_coverage_class end + + //-------------------------------------------------------------------- + // Class: mldsa_reg_model_top + // + //-------------------------------------------------------------------- + + class mldsa_reg_model_top extends mldsa_reg; + `uvm_object_utils(mldsa_reg_model_top) + + mldsa_AHB_map_coverage AHB_map_cg; + + function new(string name = "mldsa_reg_model_top"); + super.new(name); + endfunction + + + + + virtual function void build(); + super.build(); + // Build coverage for address map + if (has_coverage(UVM_CVR_ADDR_MAP)) begin + AHB_map_cg = mldsa_AHB_map_coverage::type_id::create("AHB_map_cg"); + AHB_map_cg.ra_cov.set_inst_name({this.get_full_name(), "_AHB_cg"}); + void'(set_coverage(UVM_CVR_ADDR_MAP)); + end + + endfunction + + function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map); + if (get_coverage(UVM_CVR_ADDR_MAP)) begin + if (map.get_name() == "mldsa_AHB_map") begin + AHB_map_cg.sample(offset, is_read); + end + end + endfunction: sample + + endclass + + +// class mldsa_reg_model_top extends uvm_reg_block; +// `uvm_object_utils(mldsa_reg_model_top) +// // pragma uvmf custom instantiate_registers_within_block begin +// rand mldsa_reg mldsa_rm; +// // pragma uvmf custom instantiate_registers_within_block end + + +// uvm_reg_map mldsa_AHB_map; // Block map +// mldsa_AHB_map_coverage AHB_map_cg; +// //mldsa_fixme_map_coverage fixme_map_cg; + +// // Function: new +// // +// function new(string name = ""); +// super.new(name, build_coverage(UVM_CVR_ALL)); +// endfunction + +// // Function: build +// // +// virtual function void build(); +// if(has_coverage(UVM_CVR_ADDR_MAP)) begin +// AHB_map_cg = mldsa_AHB_map_coverage::type_id::create("AHB_map_cg"); +// AHB_map_cg.ra_cov.set_inst_name({this.get_full_name(),"_AHB_cg"}); +// void'(set_coverage(UVM_CVR_ADDR_MAP)); +// end +// this.mldsa_AHB_map = create_map("mldsa_AHB_map", 0, 4, UVM_LITTLE_ENDIAN); + +// this.mldsa_rm = new("mldsa_rm"); +// this.mldsa_rm.configure(this); +// // Build the internal registers of mldsa_rm +// this.mldsa_rm.build(); +// // Add registers to the AHB map +// this.build_ext_maps(); + +// // Lock the register model +// this.lock_model(); + +// endfunction + +// virtual function void build_ext_maps(); +// uvm_reg regs[$]; + +// // Get registers from the default map of mldsa_rm +// this.mldsa_rm.default_map.get_registers(regs, UVM_NO_HIER); + +// // Add registers to the AHB map +// foreach (regs[c_reg]) begin +// this.mldsa_AHB_map.add_reg(regs[c_reg], regs[c_reg].get_offset(this.mldsa_rm.default_map)); +// end + +// endfunction + + +// // Function: sample +// // +// function void sample(uvm_reg_addr_t offset, bit is_read, uvm_reg_map map); +// if(get_coverage(UVM_CVR_ADDR_MAP)) begin +// if(map.get_name() == "mldsa_AHB_map") begin +// AHB_map_cg.sample(offset, is_read); +// end +// end +// endfunction: sample + +// endclass + +endpackage + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_sample.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_sample.svh new file mode 100644 index 0000000000000000000000000000000000000000..2f6d99c3533c180382f9e64703c71c40c9109bd6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_sample.svh @@ -0,0 +1,574 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef MLDSA_REG_SAMPLE + `define MLDSA_REG_SAMPLE + + /*----------------------- MLDSA_REG__MLDSA_NAME SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_NAME::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(NAME_bit_cg[bt]) this.NAME_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*NAME*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_NAME::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(NAME_bit_cg[bt]) this.NAME_bit_cg[bt].sample(NAME.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( NAME.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_VERSION SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_VERSION::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERSION_bit_cg[bt]) this.VERSION_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*VERSION*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_VERSION::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERSION_bit_cg[bt]) this.VERSION_bit_cg[bt].sample(VERSION.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( VERSION.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_CTRL SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_CTRL::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(CTRL_bit_cg[bt]) this.CTRL_bit_cg[bt].sample(data[0 + bt]); + foreach(ZEROIZE_bit_cg[bt]) this.ZEROIZE_bit_cg[bt].sample(data[3 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[2:0]/*CTRL*/ , data[3:3]/*ZEROIZE*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_CTRL::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(CTRL_bit_cg[bt]) this.CTRL_bit_cg[bt].sample(CTRL.get_mirrored_value() >> bt); + foreach(ZEROIZE_bit_cg[bt]) this.ZEROIZE_bit_cg[bt].sample(ZEROIZE.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( CTRL.get_mirrored_value() , ZEROIZE.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_STATUS SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_STATUS::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(READY_bit_cg[bt]) this.READY_bit_cg[bt].sample(data[0 + bt]); + foreach(VALID_bit_cg[bt]) this.VALID_bit_cg[bt].sample(data[1 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*READY*/ , data[1:1]/*VALID*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_STATUS::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(READY_bit_cg[bt]) this.READY_bit_cg[bt].sample(READY.get_mirrored_value() >> bt); + foreach(VALID_bit_cg[bt]) this.VALID_bit_cg[bt].sample(VALID.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( READY.get_mirrored_value() , VALID.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_ENTROPY SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_ENTROPY::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(ENTROPY_bit_cg[bt]) this.ENTROPY_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*ENTROPY*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_ENTROPY::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(ENTROPY_bit_cg[bt]) this.ENTROPY_bit_cg[bt].sample(ENTROPY.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( ENTROPY.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_SEED SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_SEED::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(SEED_bit_cg[bt]) this.SEED_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*SEED*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_SEED::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(SEED_bit_cg[bt]) this.SEED_bit_cg[bt].sample(SEED.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( SEED.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_SIGN_RND SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_SIGN_RND::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(SIGN_RND_bit_cg[bt]) this.SIGN_RND_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*SIGN_RND*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_SIGN_RND::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(SIGN_RND_bit_cg[bt]) this.SIGN_RND_bit_cg[bt].sample(SIGN_RND.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( SIGN_RND.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_MSG SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_MSG::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(MSG_bit_cg[bt]) this.MSG_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*MSG*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_MSG::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(MSG_bit_cg[bt]) this.MSG_bit_cg[bt].sample(MSG.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( MSG.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__MLDSA_VERIFY_RES SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__MLDSA_VERIFY_RES::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERIFY_RES_bit_cg[bt]) this.VERIFY_RES_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*VERIFY_RES*/ ); + end + endfunction + + function void mldsa_reg__MLDSA_VERIFY_RES::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERIFY_RES_bit_cg[bt]) this.VERIFY_RES_bit_cg[bt].sample(VERIFY_RES.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( VERIFY_RES.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__GLOBAL_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__global_intr_en_t::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_en_bit_cg[bt]) this.error_en_bit_cg[bt].sample(data[0 + bt]); + foreach(notif_en_bit_cg[bt]) this.notif_en_bit_cg[bt].sample(data[1 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*error_en*/ , data[1:1]/*notif_en*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__global_intr_en_t::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_en_bit_cg[bt]) this.error_en_bit_cg[bt].sample(error_en.get_mirrored_value() >> bt); + foreach(notif_en_bit_cg[bt]) this.notif_en_bit_cg[bt].sample(notif_en.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( error_en.get_mirrored_value() , notif_en.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__ERROR_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__error_intr_en_t::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_en_bit_cg[bt]) this.error_internal_en_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*error_internal_en*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__error_intr_en_t::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_en_bit_cg[bt]) this.error_internal_en_bit_cg[bt].sample(error_internal_en.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( error_internal_en.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__NOTIF_INTR_EN_T SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__notif_intr_en_t::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_en_bit_cg[bt]) this.notif_cmd_done_en_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*notif_cmd_done_en*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__notif_intr_en_t::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_en_bit_cg[bt]) this.notif_cmd_done_en_bit_cg[bt].sample(notif_cmd_done_en.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( notif_cmd_done_en.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_DD3DCF0A SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*agg_sts*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(agg_sts.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( agg_sts.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__GLOBAL_INTR_T_AGG_STS_E6399B4A SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*agg_sts*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) this.agg_sts_bit_cg[bt].sample(agg_sts.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( agg_sts.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__ERROR_INTR_T_ERROR_INTERNAL_STS_83ADAB02 SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_sts_bit_cg[bt]) this.error_internal_sts_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*error_internal_sts*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_sts_bit_cg[bt]) this.error_internal_sts_bit_cg[bt].sample(error_internal_sts.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( error_internal_sts.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__NOTIF_INTR_T_NOTIF_CMD_DONE_STS_1C68637E SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_sts_bit_cg[bt]) this.notif_cmd_done_sts_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*notif_cmd_done_sts*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_sts_bit_cg[bt]) this.notif_cmd_done_sts_bit_cg[bt].sample(notif_cmd_done_sts.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( notif_cmd_done_sts.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__ERROR_INTR_TRIG_T SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__error_intr_trig_t::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_trig_bit_cg[bt]) this.error_internal_trig_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*error_internal_trig*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__error_intr_trig_t::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_trig_bit_cg[bt]) this.error_internal_trig_bit_cg[bt].sample(error_internal_trig.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( error_internal_trig.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__NOTIF_INTR_TRIG_T SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__notif_intr_trig_t::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_trig_bit_cg[bt]) this.notif_cmd_done_trig_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*notif_cmd_done_trig*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__notif_intr_trig_t::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_trig_bit_cg[bt]) this.notif_cmd_done_trig_bit_cg[bt].sample(notif_cmd_done_trig.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( notif_cmd_done_trig.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_60DDFF93 SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*cnt*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( cnt.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_T_CNT_BE67D6D5 SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[31:0]/*cnt*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) this.cnt_bit_cg[bt].sample(cnt.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( cnt.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_15E6ED7E SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*pulse*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( pulse.get_mirrored_value() ); + end + endfunction + + /*----------------------- MLDSA_REG__INTR_BLOCK_T__INTR_COUNT_INCR_T_PULSE_6173128E SAMPLE FUNCTIONS -----------------------*/ + function void mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(data[0 + bt]); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( data[0:0]/*pulse*/ ); + end + endfunction + + function void mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) this.pulse_bit_cg[bt].sample(pulse.get_mirrored_value() >> bt); + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample( pulse.get_mirrored_value() ); + end + endfunction + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_uvm.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_uvm.sv new file mode 100644 index 0000000000000000000000000000000000000000..0e41ccc99dadd663023db23c2396a1944a63ba40 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/registers/mldsa_reg_uvm.sv @@ -0,0 +1,942 @@ + +// This file was autogenerated by PeakRDL-uvm +package mldsa_reg_uvm; + `include "uvm_macros.svh" + import uvm_pkg::*; + `include "mldsa_reg_covergroups.svh" + // Reg - mldsa_reg::MLDSA_NAME + class mldsa_reg__MLDSA_NAME extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_NAME_bit_cg NAME_bit_cg[32]; + mldsa_reg__MLDSA_NAME_fld_cg fld_cg; + rand uvm_reg_field NAME; + + function new(string name = "mldsa_reg__MLDSA_NAME"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.NAME = new("NAME"); + this.NAME.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(NAME_bit_cg[bt]) NAME_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_NAME + + // Reg - mldsa_reg::MLDSA_VERSION + class mldsa_reg__MLDSA_VERSION extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_VERSION_bit_cg VERSION_bit_cg[32]; + mldsa_reg__MLDSA_VERSION_fld_cg fld_cg; + rand uvm_reg_field VERSION; + + function new(string name = "mldsa_reg__MLDSA_VERSION"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.VERSION = new("VERSION"); + this.VERSION.configure(this, 32, 0, "RO", 1, 'h0, 0, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERSION_bit_cg[bt]) VERSION_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_VERSION + + // Reg - mldsa_reg::MLDSA_CTRL + class mldsa_reg__MLDSA_CTRL extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_CTRL_bit_cg CTRL_bit_cg[3]; + mldsa_reg__MLDSA_CTRL_bit_cg ZEROIZE_bit_cg[1]; + mldsa_reg__MLDSA_CTRL_fld_cg fld_cg; + rand uvm_reg_field CTRL; + rand uvm_reg_field ZEROIZE; + + function new(string name = "mldsa_reg__MLDSA_CTRL"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.CTRL = new("CTRL"); + this.CTRL.configure(this, 3, 0, "WO", 1, 'h0, 1, 1, 0); + this.ZEROIZE = new("ZEROIZE"); + this.ZEROIZE.configure(this, 1, 3, "WO", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(CTRL_bit_cg[bt]) CTRL_bit_cg[bt] = new(); + foreach(ZEROIZE_bit_cg[bt]) ZEROIZE_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_CTRL + + // Reg - mldsa_reg::MLDSA_STATUS + class mldsa_reg__MLDSA_STATUS extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_STATUS_bit_cg READY_bit_cg[1]; + mldsa_reg__MLDSA_STATUS_bit_cg VALID_bit_cg[1]; + mldsa_reg__MLDSA_STATUS_fld_cg fld_cg; + rand uvm_reg_field READY; + rand uvm_reg_field VALID; + + function new(string name = "mldsa_reg__MLDSA_STATUS"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.READY = new("READY"); + this.READY.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + this.VALID = new("VALID"); + this.VALID.configure(this, 1, 1, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(READY_bit_cg[bt]) READY_bit_cg[bt] = new(); + foreach(VALID_bit_cg[bt]) VALID_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_STATUS + + // Reg - mldsa_reg::MLDSA_ENTROPY + class mldsa_reg__MLDSA_ENTROPY extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_ENTROPY_bit_cg ENTROPY_bit_cg[32]; + mldsa_reg__MLDSA_ENTROPY_fld_cg fld_cg; + rand uvm_reg_field ENTROPY; + + function new(string name = "mldsa_reg__MLDSA_ENTROPY"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.ENTROPY = new("ENTROPY"); + this.ENTROPY.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(ENTROPY_bit_cg[bt]) ENTROPY_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_ENTROPY + + // Reg - mldsa_reg::MLDSA_SEED + class mldsa_reg__MLDSA_SEED extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_SEED_bit_cg SEED_bit_cg[32]; + mldsa_reg__MLDSA_SEED_fld_cg fld_cg; + rand uvm_reg_field SEED; + + function new(string name = "mldsa_reg__MLDSA_SEED"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.SEED = new("SEED"); + this.SEED.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(SEED_bit_cg[bt]) SEED_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_SEED + + // Reg - mldsa_reg::MLDSA_SIGN_RND + class mldsa_reg__MLDSA_SIGN_RND extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_SIGN_RND_bit_cg SIGN_RND_bit_cg[32]; + mldsa_reg__MLDSA_SIGN_RND_fld_cg fld_cg; + rand uvm_reg_field SIGN_RND; + + function new(string name = "mldsa_reg__MLDSA_SIGN_RND"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.SIGN_RND = new("SIGN_RND"); + this.SIGN_RND.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(SIGN_RND_bit_cg[bt]) SIGN_RND_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_SIGN_RND + + // Reg - mldsa_reg::MLDSA_MSG + class mldsa_reg__MLDSA_MSG extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_MSG_bit_cg MSG_bit_cg[32]; + mldsa_reg__MLDSA_MSG_fld_cg fld_cg; + rand uvm_reg_field MSG; + + function new(string name = "mldsa_reg__MLDSA_MSG"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.MSG = new("MSG"); + this.MSG.configure(this, 32, 0, "WO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(MSG_bit_cg[bt]) MSG_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_MSG + + // Reg - mldsa_reg::MLDSA_VERIFY_RES + class mldsa_reg__MLDSA_VERIFY_RES extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__MLDSA_VERIFY_RES_bit_cg VERIFY_RES_bit_cg[32]; + mldsa_reg__MLDSA_VERIFY_RES_fld_cg fld_cg; + rand uvm_reg_field VERIFY_RES; + + function new(string name = "mldsa_reg__MLDSA_VERIFY_RES"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.VERIFY_RES = new("VERIFY_RES"); + this.VERIFY_RES.configure(this, 32, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(VERIFY_RES_bit_cg[bt]) VERIFY_RES_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__MLDSA_VERIFY_RES + + // Mem - mldsa_reg::MLDSA_PUBKEY + class mldsa_reg__MLDSA_PUBKEY extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_PUBKEY"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 648, 32, "RW"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_PUBKEY + + // Mem - mldsa_reg::MLDSA_SIGNATURE + class mldsa_reg__MLDSA_SIGNATURE extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_SIGNATURE"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 1157, 32, "RW"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_SIGNATURE + + // Mem - mldsa_reg::MLDSA_PRIVKEY_OUT + class mldsa_reg__MLDSA_PRIVKEY_OUT extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_PRIVKEY_OUT"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 1224, 32, "RO"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_PRIVKEY_OUT + + // Mem - mldsa_reg::MLDSA_PRIVKEY_IN + class mldsa_reg__MLDSA_PRIVKEY_IN extends uvm_reg_block; + rand uvm_mem m_mem; + + function new(string name = "mldsa_reg__MLDSA_PRIVKEY_IN"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4.0, UVM_NO_ENDIAN); + this.m_mem = new("m_mem", 1224, 32, "RW"); + this.m_mem.configure(this); + this.default_map.add_mem(this.m_mem, 0); + endfunction : build + endclass : mldsa_reg__MLDSA_PRIVKEY_IN + + // Reg - mldsa_reg::intr_block_t::global_intr_en_t + class mldsa_reg__intr_block_t__global_intr_en_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__global_intr_en_t_bit_cg error_en_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_en_t_bit_cg notif_en_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_en_t_fld_cg fld_cg; + rand uvm_reg_field error_en; + rand uvm_reg_field notif_en; + + function new(string name = "mldsa_reg__intr_block_t__global_intr_en_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_en = new("error_en"); + this.error_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0); + this.notif_en = new("notif_en"); + this.notif_en.configure(this, 1, 1, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_en_bit_cg[bt]) error_en_bit_cg[bt] = new(); + foreach(notif_en_bit_cg[bt]) notif_en_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__global_intr_en_t + + // Reg - mldsa_reg::intr_block_t::error_intr_en_t + class mldsa_reg__intr_block_t__error_intr_en_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__error_intr_en_t_bit_cg error_internal_en_bit_cg[1]; + mldsa_reg__intr_block_t__error_intr_en_t_fld_cg fld_cg; + rand uvm_reg_field error_internal_en; + + function new(string name = "mldsa_reg__intr_block_t__error_intr_en_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_internal_en = new("error_internal_en"); + this.error_internal_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_en_bit_cg[bt]) error_internal_en_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__error_intr_en_t + + // Reg - mldsa_reg::intr_block_t::notif_intr_en_t + class mldsa_reg__intr_block_t__notif_intr_en_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__notif_intr_en_t_bit_cg notif_cmd_done_en_bit_cg[1]; + mldsa_reg__intr_block_t__notif_intr_en_t_fld_cg fld_cg; + rand uvm_reg_field notif_cmd_done_en; + + function new(string name = "mldsa_reg__intr_block_t__notif_intr_en_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.notif_cmd_done_en = new("notif_cmd_done_en"); + this.notif_cmd_done_en.configure(this, 1, 0, "RW", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_en_bit_cg[bt]) notif_cmd_done_en_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__notif_intr_en_t + + // Reg - mldsa_reg::intr_block_t::global_intr_t_agg_sts_dd3dcf0a + class mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_bit_cg agg_sts_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a_fld_cg fld_cg; + rand uvm_reg_field agg_sts; + + function new(string name = "mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.agg_sts = new("agg_sts"); + this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a + + // Reg - mldsa_reg::intr_block_t::global_intr_t_agg_sts_e6399b4a + class mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_bit_cg agg_sts_bit_cg[1]; + mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a_fld_cg fld_cg; + rand uvm_reg_field agg_sts; + + function new(string name = "mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.agg_sts = new("agg_sts"); + this.agg_sts.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(agg_sts_bit_cg[bt]) agg_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a + + // Reg - mldsa_reg::intr_block_t::error_intr_t_error_internal_sts_83adab02 + class mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_bit_cg error_internal_sts_bit_cg[1]; + mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02_fld_cg fld_cg; + rand uvm_reg_field error_internal_sts; + + function new(string name = "mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_internal_sts = new("error_internal_sts"); + this.error_internal_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_sts_bit_cg[bt]) error_internal_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 + + // Reg - mldsa_reg::intr_block_t::notif_intr_t_notif_cmd_done_sts_1c68637e + class mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_bit_cg notif_cmd_done_sts_bit_cg[1]; + mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e_fld_cg fld_cg; + rand uvm_reg_field notif_cmd_done_sts; + + function new(string name = "mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.notif_cmd_done_sts = new("notif_cmd_done_sts"); + this.notif_cmd_done_sts.configure(this, 1, 0, "W1C", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_sts_bit_cg[bt]) notif_cmd_done_sts_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e + + // Reg - mldsa_reg::intr_block_t::error_intr_trig_t + class mldsa_reg__intr_block_t__error_intr_trig_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__error_intr_trig_t_bit_cg error_internal_trig_bit_cg[1]; + mldsa_reg__intr_block_t__error_intr_trig_t_fld_cg fld_cg; + rand uvm_reg_field error_internal_trig; + + function new(string name = "mldsa_reg__intr_block_t__error_intr_trig_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.error_internal_trig = new("error_internal_trig"); + this.error_internal_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(error_internal_trig_bit_cg[bt]) error_internal_trig_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__error_intr_trig_t + + // Reg - mldsa_reg::intr_block_t::notif_intr_trig_t + class mldsa_reg__intr_block_t__notif_intr_trig_t extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__notif_intr_trig_t_bit_cg notif_cmd_done_trig_bit_cg[1]; + mldsa_reg__intr_block_t__notif_intr_trig_t_fld_cg fld_cg; + rand uvm_reg_field notif_cmd_done_trig; + + function new(string name = "mldsa_reg__intr_block_t__notif_intr_trig_t"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.notif_cmd_done_trig = new("notif_cmd_done_trig"); + this.notif_cmd_done_trig.configure(this, 1, 0, "W1S", 0, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(notif_cmd_done_trig_bit_cg[bt]) notif_cmd_done_trig_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__notif_intr_trig_t + + // Reg - mldsa_reg::intr_block_t::intr_count_t_cnt_60ddff93 + class mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93 extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93_bit_cg cnt_bit_cg[32]; + mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93_fld_cg fld_cg; + rand uvm_reg_field cnt; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.cnt = new("cnt"); + this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93 + + // Reg - mldsa_reg::intr_block_t::intr_count_t_cnt_be67d6d5 + class mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5 extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5_bit_cg cnt_bit_cg[32]; + mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5_fld_cg fld_cg; + rand uvm_reg_field cnt; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.cnt = new("cnt"); + this.cnt.configure(this, 32, 0, "RW", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(cnt_bit_cg[bt]) cnt_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5 + + // Reg - mldsa_reg::intr_block_t::intr_count_incr_t_pulse_15e6ed7e + class mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_bit_cg pulse_bit_cg[1]; + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e_fld_cg fld_cg; + rand uvm_reg_field pulse; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.pulse = new("pulse"); + this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e + + // Reg - mldsa_reg::intr_block_t::intr_count_incr_t_pulse_6173128e + class mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e extends uvm_reg; + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; + + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_bit_cg pulse_bit_cg[1]; + mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e_fld_cg fld_cg; + rand uvm_reg_field pulse; + + function new(string name = "mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e"); + super.new(name, 32, build_coverage(UVM_CVR_ALL)); + endfunction : new + extern virtual function void sample_values(); + extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + + virtual function void build(); + this.pulse = new("pulse"); + this.pulse.configure(this, 1, 0, "RO", 1, 'h0, 1, 1, 0); + if (has_coverage(UVM_CVR_REG_BITS)) begin + foreach(pulse_bit_cg[bt]) pulse_bit_cg[bt] = new(); + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); + endfunction : build + endclass : mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e + + // Regfile - mldsa_reg::intr_block_t + class mldsa_reg__intr_block_t extends uvm_reg_block; + rand mldsa_reg__intr_block_t__global_intr_en_t global_intr_en_r; + rand mldsa_reg__intr_block_t__error_intr_en_t error_intr_en_r; + rand mldsa_reg__intr_block_t__notif_intr_en_t notif_intr_en_r; + rand mldsa_reg__intr_block_t__global_intr_t_agg_sts_dd3dcf0a error_global_intr_r; + rand mldsa_reg__intr_block_t__global_intr_t_agg_sts_e6399b4a notif_global_intr_r; + rand mldsa_reg__intr_block_t__error_intr_t_error_internal_sts_83adab02 error_internal_intr_r; + rand mldsa_reg__intr_block_t__notif_intr_t_notif_cmd_done_sts_1c68637e notif_internal_intr_r; + rand mldsa_reg__intr_block_t__error_intr_trig_t error_intr_trig_r; + rand mldsa_reg__intr_block_t__notif_intr_trig_t notif_intr_trig_r; + rand mldsa_reg__intr_block_t__intr_count_t_cnt_60ddff93 error_internal_intr_count_r; + rand mldsa_reg__intr_block_t__intr_count_t_cnt_be67d6d5 notif_cmd_done_intr_count_r; + rand mldsa_reg__intr_block_t__intr_count_incr_t_pulse_15e6ed7e error_internal_intr_count_incr_r; + rand mldsa_reg__intr_block_t__intr_count_incr_t_pulse_6173128e notif_cmd_done_intr_count_incr_r; + + function new(string name = "mldsa_reg__intr_block_t"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4, UVM_NO_ENDIAN); + this.global_intr_en_r = new("global_intr_en_r"); + this.global_intr_en_r.configure(this); + + this.global_intr_en_r.build(); + this.default_map.add_reg(this.global_intr_en_r, 'h0); + this.error_intr_en_r = new("error_intr_en_r"); + this.error_intr_en_r.configure(this); + + this.error_intr_en_r.build(); + this.default_map.add_reg(this.error_intr_en_r, 'h4); + this.notif_intr_en_r = new("notif_intr_en_r"); + this.notif_intr_en_r.configure(this); + + this.notif_intr_en_r.build(); + this.default_map.add_reg(this.notif_intr_en_r, 'h8); + this.error_global_intr_r = new("error_global_intr_r"); + this.error_global_intr_r.configure(this); + + this.error_global_intr_r.build(); + this.default_map.add_reg(this.error_global_intr_r, 'hc); + this.notif_global_intr_r = new("notif_global_intr_r"); + this.notif_global_intr_r.configure(this); + + this.notif_global_intr_r.build(); + this.default_map.add_reg(this.notif_global_intr_r, 'h10); + this.error_internal_intr_r = new("error_internal_intr_r"); + this.error_internal_intr_r.configure(this); + + this.error_internal_intr_r.build(); + this.default_map.add_reg(this.error_internal_intr_r, 'h14); + this.notif_internal_intr_r = new("notif_internal_intr_r"); + this.notif_internal_intr_r.configure(this); + + this.notif_internal_intr_r.build(); + this.default_map.add_reg(this.notif_internal_intr_r, 'h18); + this.error_intr_trig_r = new("error_intr_trig_r"); + this.error_intr_trig_r.configure(this); + + this.error_intr_trig_r.build(); + this.default_map.add_reg(this.error_intr_trig_r, 'h1c); + this.notif_intr_trig_r = new("notif_intr_trig_r"); + this.notif_intr_trig_r.configure(this); + + this.notif_intr_trig_r.build(); + this.default_map.add_reg(this.notif_intr_trig_r, 'h20); + this.error_internal_intr_count_r = new("error_internal_intr_count_r"); + this.error_internal_intr_count_r.configure(this); + + this.error_internal_intr_count_r.build(); + this.default_map.add_reg(this.error_internal_intr_count_r, 'h100); + this.notif_cmd_done_intr_count_r = new("notif_cmd_done_intr_count_r"); + this.notif_cmd_done_intr_count_r.configure(this); + + this.notif_cmd_done_intr_count_r.build(); + this.default_map.add_reg(this.notif_cmd_done_intr_count_r, 'h180); + this.error_internal_intr_count_incr_r = new("error_internal_intr_count_incr_r"); + this.error_internal_intr_count_incr_r.configure(this); + + this.error_internal_intr_count_incr_r.build(); + this.default_map.add_reg(this.error_internal_intr_count_incr_r, 'h200); + this.notif_cmd_done_intr_count_incr_r = new("notif_cmd_done_intr_count_incr_r"); + this.notif_cmd_done_intr_count_incr_r.configure(this); + + this.notif_cmd_done_intr_count_incr_r.build(); + this.default_map.add_reg(this.notif_cmd_done_intr_count_incr_r, 'h204); + endfunction : build + endclass : mldsa_reg__intr_block_t + + // Addrmap - mldsa_reg + class mldsa_reg extends uvm_reg_block; + rand mldsa_reg__MLDSA_NAME MLDSA_NAME[2]; + rand mldsa_reg__MLDSA_VERSION MLDSA_VERSION[2]; + rand mldsa_reg__MLDSA_CTRL MLDSA_CTRL; + rand mldsa_reg__MLDSA_STATUS MLDSA_STATUS; + rand mldsa_reg__MLDSA_ENTROPY MLDSA_ENTROPY[16]; + rand mldsa_reg__MLDSA_SEED MLDSA_SEED[8]; + rand mldsa_reg__MLDSA_SIGN_RND MLDSA_SIGN_RND[8]; + rand mldsa_reg__MLDSA_MSG MLDSA_MSG[16]; + rand mldsa_reg__MLDSA_VERIFY_RES MLDSA_VERIFY_RES[16]; + rand mldsa_reg__MLDSA_PUBKEY MLDSA_PUBKEY; + rand mldsa_reg__MLDSA_SIGNATURE MLDSA_SIGNATURE; + rand mldsa_reg__MLDSA_PRIVKEY_OUT MLDSA_PRIVKEY_OUT; + rand mldsa_reg__MLDSA_PRIVKEY_IN MLDSA_PRIVKEY_IN; + rand mldsa_reg__intr_block_t intr_block_rf; + + function new(string name = "mldsa_reg"); + super.new(name); + endfunction : new + + virtual function void build(); + this.default_map = create_map("reg_map", 0, 4, UVM_NO_ENDIAN); + foreach(this.MLDSA_NAME[i0]) begin + this.MLDSA_NAME[i0] = new($sformatf("MLDSA_NAME[%0d]", i0)); + this.MLDSA_NAME[i0].configure(this); + + this.MLDSA_NAME[i0].build(); + this.default_map.add_reg(this.MLDSA_NAME[i0], 'h0 + i0*'h4); + end + foreach(this.MLDSA_VERSION[i0]) begin + this.MLDSA_VERSION[i0] = new($sformatf("MLDSA_VERSION[%0d]", i0)); + this.MLDSA_VERSION[i0].configure(this); + + this.MLDSA_VERSION[i0].build(); + this.default_map.add_reg(this.MLDSA_VERSION[i0], 'h8 + i0*'h4); + end + this.MLDSA_CTRL = new("MLDSA_CTRL"); + this.MLDSA_CTRL.configure(this); + + this.MLDSA_CTRL.build(); + this.default_map.add_reg(this.MLDSA_CTRL, 'h10); + this.MLDSA_STATUS = new("MLDSA_STATUS"); + this.MLDSA_STATUS.configure(this); + + this.MLDSA_STATUS.build(); + this.default_map.add_reg(this.MLDSA_STATUS, 'h14); + foreach(this.MLDSA_ENTROPY[i0]) begin + this.MLDSA_ENTROPY[i0] = new($sformatf("MLDSA_ENTROPY[%0d]", i0)); + this.MLDSA_ENTROPY[i0].configure(this); + + this.MLDSA_ENTROPY[i0].build(); + this.default_map.add_reg(this.MLDSA_ENTROPY[i0], 'h18 + i0*'h4); + end + foreach(this.MLDSA_SEED[i0]) begin + this.MLDSA_SEED[i0] = new($sformatf("MLDSA_SEED[%0d]", i0)); + this.MLDSA_SEED[i0].configure(this); + + this.MLDSA_SEED[i0].build(); + this.default_map.add_reg(this.MLDSA_SEED[i0], 'h58 + i0*'h4); + end + foreach(this.MLDSA_SIGN_RND[i0]) begin + this.MLDSA_SIGN_RND[i0] = new($sformatf("MLDSA_SIGN_RND[%0d]", i0)); + this.MLDSA_SIGN_RND[i0].configure(this); + + this.MLDSA_SIGN_RND[i0].build(); + this.default_map.add_reg(this.MLDSA_SIGN_RND[i0], 'h78 + i0*'h4); + end + foreach(this.MLDSA_MSG[i0]) begin + this.MLDSA_MSG[i0] = new($sformatf("MLDSA_MSG[%0d]", i0)); + this.MLDSA_MSG[i0].configure(this); + + this.MLDSA_MSG[i0].build(); + this.default_map.add_reg(this.MLDSA_MSG[i0], 'h98 + i0*'h4); + end + foreach(this.MLDSA_VERIFY_RES[i0]) begin + this.MLDSA_VERIFY_RES[i0] = new($sformatf("MLDSA_VERIFY_RES[%0d]", i0)); + this.MLDSA_VERIFY_RES[i0].configure(this); + + this.MLDSA_VERIFY_RES[i0].build(); + this.default_map.add_reg(this.MLDSA_VERIFY_RES[i0], 'hd8 + i0*'h4); + end + this.MLDSA_PUBKEY = new("MLDSA_PUBKEY"); + this.MLDSA_PUBKEY.configure(this); + this.MLDSA_PUBKEY.build(); + this.default_map.add_submap(this.MLDSA_PUBKEY.default_map, 'h1000); + this.MLDSA_SIGNATURE = new("MLDSA_SIGNATURE"); + this.MLDSA_SIGNATURE.configure(this); + this.MLDSA_SIGNATURE.build(); + this.default_map.add_submap(this.MLDSA_SIGNATURE.default_map, 'h2000); + this.MLDSA_PRIVKEY_OUT = new("MLDSA_PRIVKEY_OUT"); + this.MLDSA_PRIVKEY_OUT.configure(this); + this.MLDSA_PRIVKEY_OUT.build(); + this.default_map.add_submap(this.MLDSA_PRIVKEY_OUT.default_map, 'h4000); + this.MLDSA_PRIVKEY_IN = new("MLDSA_PRIVKEY_IN"); + this.MLDSA_PRIVKEY_IN.configure(this); + this.MLDSA_PRIVKEY_IN.build(); + this.default_map.add_submap(this.MLDSA_PRIVKEY_IN.default_map, 'h6000); + this.intr_block_rf = new("intr_block_rf"); + this.intr_block_rf.configure(this); + this.intr_block_rf.build(); + this.default_map.add_submap(this.intr_block_rf.default_map, 'h8000); + endfunction : build + endclass : mldsa_reg + + `include "mldsa_reg_sample.svh" +endpackage: mldsa_reg_uvm diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_configuration.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_configuration.svh new file mode 100644 index 0000000000000000000000000000000000000000..221fe36445a3db01d09e66199fbc4d573692e929 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_configuration.svh @@ -0,0 +1,188 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: THis is the configuration for the mldsa environment. +// it contains configuration classes for each agent. It also contains +// environment level configuration variables. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class mldsa_env_configuration +extends uvmf_environment_configuration_base; + + `uvm_object_utils( mldsa_env_configuration ) + + +//Constraints for the configuration variables: + +// Instantiate the register model + mldsa_reg_model_top mldsa_rm; + + covergroup mldsa_configuration_cg; + // pragma uvmf custom covergroup begin + option.auto_bin_max=1024; + // pragma uvmf custom covergroup end + endgroup + + + + + qvip_ahb_lite_slave_env_configuration qvip_ahb_lite_slave_subenv_config; + string qvip_ahb_lite_slave_subenv_interface_names[]; + uvmf_active_passive_t qvip_ahb_lite_slave_subenv_interface_activity[]; + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(mldsa_env_configuration)) mldsa_vsqr_t; + mldsa_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// This function constructs the configuration object for each agent in the environment. +// + function new( string name = "" ); + super.new( name ); + qvip_ahb_lite_slave_subenv_config = qvip_ahb_lite_slave_env_configuration::type_id::create("qvip_ahb_lite_slave_subenv_config"); + + mldsa_configuration_cg=new; + `uvm_warning("COVERAGE_MODEL_REVIEW", "A covergroup has been constructed which may need review because of either generation or re-generation with merging. Please note that configuration variables added as a result of re-generation and merging are not automatically added to the covergroup. Remove this warning after the covergroup has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + +// **************************************************************************** +// FUNCTION : set_vsqr() +// This function is used to assign the vsqr handle. + virtual function void set_vsqr( mldsa_vsqr_t vsqr); + this.vsqr = vsqr; + endfunction : set_vsqr + +// **************************************************************************** +// FUNCTION: post_randomize() +// This function is automatically called after the randomize() function +// is executed. +// + function void post_randomize(); + super.post_randomize(); + // pragma uvmf custom post_randomize begin + // pragma uvmf custom post_randomize end + endfunction + +// **************************************************************************** +// FUNCTION: convert2string() +// This function converts all variables in this class to a single string for +// logfile reporting. This function concatenates the convert2string result for +// each agent configuration in this configuration class. +// + virtual function string convert2string(); + // pragma uvmf custom convert2string begin + return { + + + + "\n", qvip_ahb_lite_slave_subenv_config.convert2string + }; + // pragma uvmf custom convert2string end + endfunction +// **************************************************************************** +// FUNCTION: initialize(); +// This function configures each interface agents configuration class. The +// sim level determines the active/passive state of the agent. The environment_path +// identifies the hierarchy down to and including the instantiation name of the +// environment for this configuration class. Each instance of the environment +// has its own configuration class. The string interface names are used by +// the agent configurations to identify the virtual interface handle to pull from +// the uvm_config_db. +// + function void initialize(uvmf_sim_level_t sim_level, + string environment_path, + string interface_names[], + uvm_reg_block register_model = null, + uvmf_active_passive_t interface_activity[] = {} + ); + + super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity); + + + // Interface initialization for QVIP sub-environments + qvip_ahb_lite_slave_subenv_interface_names = new[1]; + qvip_ahb_lite_slave_subenv_interface_activity = new[1]; + + qvip_ahb_lite_slave_subenv_interface_names = interface_names[0:0]; + qvip_ahb_lite_slave_subenv_interface_activity = interface_activity[0:0]; + + + + // pragma uvmf custom reg_model_config_initialize begin + // Register model creation and configuation + if (register_model == null) begin + uvm_reg::include_coverage("*", UVM_CVR_ALL); // Register coverage config with resource DB, used later by build_coverage() + mldsa_rm = mldsa_reg_model_top::type_id::create("mldsa_rm"); + mldsa_rm.build(); + // mldsa_rm.mldsa_uvm_rmlock_model(); + mldsa_rm.lock_model(); + + // Check if the model is locked and provide an info message + if (mldsa_rm.is_locked()) begin + `uvm_info("LOCK_MODEL", "Register model mldsa_rm is successfully locked.", UVM_LOW) + end else begin + `uvm_error("LOCK_MODEL", "Register model mldsa_rm failed to lock.") + end + // Check if the model is locked and provide an info message + // if (mldsa_rm.mldsa_uvm_rm.is_locked()) begin + // `uvm_info("LOCK_MODEL", "Register model mldsa_uvm_rm is successfully locked.", UVM_LOW) + // end else begin + // `uvm_error("LOCK_MODEL", "Register model mldsa_uvm_rm failed to lock.") + // end + + + // mldsa_rm.build_ext_maps(); + enable_reg_adaptation = 1; + enable_reg_prediction = 1; + end else begin + $cast(mldsa_rm,register_model); + enable_reg_prediction = 1; + end + // pragma uvmf custom reg_model_config_initialize end + + + qvip_ahb_lite_slave_subenv_config.initialize( sim_level, {environment_path,".qvip_ahb_lite_slave_subenv"}, qvip_ahb_lite_slave_subenv_interface_names, mldsa_rm, qvip_ahb_lite_slave_subenv_interface_activity); + + + // pragma uvmf custom initialize begin + qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.agent_cfg.en_cvg.slave = 1'b1; + qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.agent_cfg.en_cvg.master = 1'b1; + qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.agent_cfg.en_cvg.response = 1'b1; + + // Add analysis ports to send Bus traffic to the scoreboard, so that the predictor/scoreboard can check read transfer data + void'(qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.set_monitor_item( "burst_transfer_sb" , ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH)::type_id::get() )); + // Add analysis ports to send Bus traffic to the coverage subscriber + void'(qvip_ahb_lite_slave_subenv_config.ahb_lite_slave_0_cfg.set_monitor_item( "burst_transfer_cov" , ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH)::type_id::get() )); + // pragma uvmf custom initialize end + + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_sequence_base.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_sequence_base.svh new file mode 100644 index 0000000000000000000000000000000000000000..25625c374ea16b38f6d2a40adc69f9616aee9e0a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_sequence_base.svh @@ -0,0 +1,62 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This file contains environment level sequences that will +// be reused from block to top level simulations. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +class mldsa_env_sequence_base #( + type CONFIG_T + ) extends uvmf_virtual_sequence_base #(.CONFIG_T(CONFIG_T)); + + + `uvm_object_param_utils( mldsa_env_sequence_base #( + CONFIG_T + ) ); + `m_uvm_get_type_name_func(mldsa_env_sequence_base) + + // Handle to the environments register model +// This handle needs to be set before use. + mldsa_reg_model_top reg_model; + +// This mldsa_env_sequence_base contains a handle to a mldsa_env_configuration object +// named configuration. This configuration variable contains a handle to each +// sequencer within each agent within this environment and any sub-environments. +// The configuration object handle is automatically assigned in the pre_body in the +// base class of this sequence. The configuration handle is retrieved from the +// virtual sequencer that this sequence is started on. +// Available sequencer handles within the environment configuration: + + // Initiator agent sequencers in mldsa_environment: + + // Responder agent sequencers in mldsa_environment: + + + + + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + + function new(string name = "" ); + super.new(name); + endfunction + + virtual task body(); + + + + endtask + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_typedefs.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_typedefs.svh new file mode 100644 index 0000000000000000000000000000000000000000..5003a3ce95b4acd5a6dd6b279c891f8a531cdc04 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_env_typedefs.svh @@ -0,0 +1,21 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: +// This file contains defines and typedefs to be compiled for use in +// the environment package. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + localparam bit AHB_REQ = 1'b1; + localparam bit NOT_AHB_REQ = 1'b0; + + // pragma uvmf custom additional begin + // pragma uvmf custom additional end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_environment.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_environment.svh new file mode 100644 index 0000000000000000000000000000000000000000..1385cbc23df870d86500dbd49a4b504d91eba4a1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_environment.svh @@ -0,0 +1,177 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This environment contains all agents, predictors and +// scoreboards required for the block level design. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class mldsa_environment extends uvmf_environment_base #( + .CONFIG_T( mldsa_env_configuration + )); + `uvm_component_utils( mldsa_environment ) + + + qvip_ahb_lite_slave_environment #() qvip_ahb_lite_slave_subenv; + uvm_analysis_port #( mvc_sequence_item_base ) qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_ap [string]; + + + + + typedef mldsa_predictor #( + .CONFIG_T(CONFIG_T) + ) + mldsa_pred_t; + mldsa_pred_t mldsa_pred; + typedef mldsa_scoreboard #( + .CONFIG_T(CONFIG_T) + ) + mldsa_sb_t; + mldsa_sb_t mldsa_sb; + + typedef ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_reg_transfer_t; + + typedef reg2ahb_adapter #(ahb_reg_transfer_t, + ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_reg_adapter_t; + + + ahb_reg_adapter_t ahb_reg_adapter; + + typedef ahb_reg_predictor #(ahb_reg_transfer_t, + ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_reg_predictor_t; + + ahb_reg_predictor_t ahb_reg_predictor; + + + + typedef uvmf_virtual_sequencer_base #(.CONFIG_T(mldsa_env_configuration)) mldsa_vsqr_t; + mldsa_vsqr_t vsqr; + + // pragma uvmf custom class_item_additional begin + // pragma uvmf custom class_item_additional end + +// **************************************************************************** +// FUNCTION : new() +// This function is the standard SystemVerilog constructor. +// + function new( string name = "", uvm_component parent = null ); + super.new( name, parent ); + endfunction + +// **************************************************************************** +// FUNCTION: build_phase() +// This function builds all components within this environment. +// + virtual function void build_phase(uvm_phase phase); +// pragma uvmf custom build_phase_pre_super begin +// pragma uvmf custom build_phase_pre_super end + super.build_phase(phase); + qvip_ahb_lite_slave_subenv = qvip_ahb_lite_slave_environment#()::type_id::create("qvip_ahb_lite_slave_subenv",this); + qvip_ahb_lite_slave_subenv.set_config(configuration.qvip_ahb_lite_slave_subenv_config); + + mldsa_pred = mldsa_pred_t::type_id::create("mldsa_pred",this); + mldsa_pred.configuration = configuration; + + mldsa_sb = mldsa_sb_t::type_id::create("mldsa_sb",this); + mldsa_sb.configuration = configuration; + + if (configuration.enable_reg_prediction) begin + ahb_reg_predictor = ahb_reg_predictor_t::type_id::create("ahb_reg_predictor", this); + end +// pragma uvmf custom reg_model_build_phase end + + vsqr = mldsa_vsqr_t::type_id::create("vsqr", this); + vsqr.set_config(configuration); + configuration.set_vsqr(vsqr); + + // pragma uvmf custom build_phase begin + // pragma uvmf custom build_phase end + endfunction + +// **************************************************************************** +// FUNCTION: connect_phase() +// This function makes all connections within this environment. Connections +// typically inclue agent to predictor, predictor to scoreboard and scoreboard +// to agent. +// + virtual function void connect_phase(uvm_phase phase); + + super.connect_phase(phase); + qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_ap = qvip_ahb_lite_slave_subenv.ahb_lite_slave_0.ap; + + qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_ap["burst_transfer"].connect(mldsa_pred.ahb_slave_0_ae); + + qvip_ahb_lite_slave_subenv_ahb_lite_slave_0_ap["burst_transfer_sb"].connect(mldsa_sb.actual_ahb_analysis_export); + mldsa_pred.mldsa_sb_ahb_ap.connect(mldsa_sb.expected_ahb_analysis_export); + + + + + if ( configuration.qvip_ahb_lite_slave_subenv_interface_activity[0] == ACTIVE ) + uvm_config_db #(mvc_sequencer)::set(null,UVMF_SEQUENCERS,configuration.qvip_ahb_lite_slave_subenv_interface_names[0],qvip_ahb_lite_slave_subenv.ahb_lite_slave_0.m_sequencer ); + + + + + // pragma uvmf custom reg_model_connect_phase begin + // Create register model adapter if required + if (configuration.enable_reg_prediction || + configuration.enable_reg_adaptation) begin + ahb_reg_adapter = ahb_reg_adapter_t::type_id::create("reg2ahb_adapter"); + ahb_reg_adapter.en_n_bits = 1; // This is to allow the adapter to generate addresses + // that are not aligned to 64-bit width (the native AHB interface width) + end + + if ((configuration.enable_reg_adaptation) && (qvip_ahb_lite_slave_subenv.ahb_lite_slave_0.m_sequencer != null )) + configuration.mldsa_rm.default_map.set_sequencer(qvip_ahb_lite_slave_subenv.ahb_lite_slave_0.m_sequencer, ahb_reg_adapter); + // Set map and adapter handles within uvm predictor + if (configuration.enable_reg_prediction) begin + ahb_reg_predictor.map = configuration.mldsa_rm.default_map; + ahb_reg_predictor.adapter = ahb_reg_adapter; + mldsa_pred.mldsa_ahb_reg_ap.connect(ahb_reg_predictor.bus_item_export); + end + // pragma uvmf custom reg_model_connect_phase end + endfunction + +// **************************************************************************** +// FUNCTION: end_of_simulation_phase() +// This function is executed just prior to executing run_phase. This function +// was added to the environment to sample environment configuration settings +// just before the simulation exits time 0. The configuration structure is +// randomized in the build phase before the environment structure is constructed. +// Configuration variables can be customized after randomization in the build_phase +// of the extended test. +// If a sequence modifies values in the configuration structure then the sequence is +// responsible for sampling the covergroup in the configuration if required. +// + virtual function void start_of_simulation_phase(uvm_phase phase); + configuration.mldsa_configuration_cg.sample(); + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_predictor.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_predictor.svh new file mode 100644 index 0000000000000000000000000000000000000000..87df028c54d5b69c56bac5b87f208ce9b79467fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_predictor.svh @@ -0,0 +1,721 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +// +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +// mldsa_sb_ahb_ap broadcasts transactions of type ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + +class mldsa_predictor #( + type CONFIG_T, + type BASE_T = uvm_component + ) + extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( mldsa_predictor #( + CONFIG_T, + BASE_T + ) +) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + + // Instantiate the analysis ports + uvm_analysis_port #(mvc_sequence_item_base) mldsa_sb_ahb_ap; + + + // Instantiate QVIP analysis exports + uvm_analysis_imp_ahb_slave_0_ae #(mvc_sequence_item_base, mldsa_predictor #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) ahb_slave_0_ae; + + // Transaction variable for predicted values to be sent out mldsa_sb_ahb_ap + // Once a transaction is sent through an analysis_port, another transaction should + // be constructed for the next predicted transaction. + typedef ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) mldsa_sb_ahb_ap_output_transaction_t; + mldsa_sb_ahb_ap_output_transaction_t mldsa_sb_ahb_ap_output_transaction; + // Code for sending output transaction out through mldsa_sb_ahb_ap + // mldsa_sb_ahb_ap.write(mldsa_sb_ahb_ap_output_transaction); + + + // Create QVIP transaction handles for debug visibility + mvc_sequence_item_base ahb_slave_0_ae_debug_t; + // Create transaction handles for visibility in visualizer + + // pragma uvmf custom class_item_additional begin + string dilithium_command; + bit expect_predictor_verif_failure; + // pragma uvmf custom class_item_additional end + + uvm_analysis_port #(mvc_sequence_item_base) mldsa_ahb_reg_ap; + uvm_reg_map p_mldsa_map; // Block map + mldsa_reg_model_top p_mldsa_rm; + + bit [31:0] SEED [0:7]; //32 Bytes + bit [31:0] SK []; //4896 Bytes + bit [31:0] PK []; //2592 Bytes + bit [31:0] MSG [0:15]; //64 Bytes + bit [31:0] SIG []; //4628 Bytes + bit [31:0] VERIF []; //64 Bytes + + bit lock_IP; + bit valid; + bit [31:0] data; + uvm_status_e status; + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // Construct arrays + SK = new[1224]; + PK = new[648]; + SIG = new[1157]; + VERIF = new[16]; + lock_IP = 0; + data = '0; + //`uvm_warning("PREDICTOR_REVIEW", "This predictor has been created either through generation or re-generation with merging. Remove this warning after the predictor has been reviewed.") + + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + ahb_slave_0_ae = new("ahb_slave_0_ae", this); + mldsa_sb_ahb_ap =new("mldsa_sb_ahb_ap", this ); + mldsa_ahb_reg_ap = new("mldsa_ahb_reg_ap", this); + + p_mldsa_rm = configuration.mldsa_rm; + p_mldsa_map = p_mldsa_rm.get_default_map(); + + // pragma uvmf custom build_phase begin + // Read the configuration parameter + if (!uvm_config_db#(string)::get(this, "", "dilithium_command", dilithium_command)) begin + dilithium_command = "test_dilithium5"; // default value + end + `uvm_info("PREDICTOR", $sformatf("DILITHIUM_COMMAND to be used: %s", dilithium_command), UVM_LOW) + + if (!uvm_config_db#(bit)::get(this, "", "expect_predictor_verif_failure", expect_predictor_verif_failure)) begin + expect_predictor_verif_failure = 0; // default value + end + `uvm_info("PREDICTOR", $sformatf("expect_predictor_verif_failure to be used: %d", expect_predictor_verif_failure), UVM_LOW) + // pragma uvmf custom build_phase end + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + endtask + + + // FUNCTION: write_ahb_slave_0_ae + // QVIP transactions received through ahb_slave_0_ae initiate the execution of this function. + // This function casts incoming QVIP transactions into the correct protocol type and then performs prediction + // of DUT output values based on DUT input, configuration and state + virtual function void write_ahb_slave_0_ae(mvc_sequence_item_base _t); + logic [31:0] written_value, expected_value; + uvm_reg_addr_t privkey_out_base_addr, privkey_in_base_addr, signature_base_addr, pubkey_base_addr; + uvm_reg_addr_t privkey_out_size, privkey_in_size, signature_size, pubkey_size; + uvm_reg_addr_t reg_addr; + uvm_mem privkey_out_mem, privkey_in_mem, signature_mem, pubkey_mem; + uvm_reg reg_obj; + bit MEM_range_true; + // pragma uvmf custom ahb_slave_0_ae_predictor begin + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) t; + ahb_slave_0_ae_debug_t = _t; + if (!$cast(t,_t)) begin + `uvm_fatal("PRED","Cast from mvc_sequence_item_base to ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) in write_ahb_slave_0_ae failed!") + end + // `uvm_info("PRED", "Transaction Received through ahb_slave_0_ae", UVM_MEDIUM) + // `uvm_info("PRED",{" Data: ",t.convert2string()}, UVM_FULL) + // Construct one of each output transaction type. + mldsa_sb_ahb_ap_output_transaction = mldsa_sb_ahb_ap_output_transaction_t::type_id::create("mldsa_sb_ahb_ap_output_transaction"); + // UVMF_CHANGE_ME: Implement predictor model here. + + reg_obj = p_mldsa_rm.default_map.get_reg_by_offset(t.address); + + + + +//========================================================================================== + + privkey_out_base_addr = p_mldsa_rm.default_map.get_submap_offset(p_mldsa_rm.MLDSA_PRIVKEY_OUT.default_map); + privkey_out_mem = p_mldsa_rm.default_map.get_mem_by_offset(privkey_out_base_addr); + privkey_out_size = uvm_reg_addr_t'(privkey_out_mem.get_size()); + // Check if MLDSA_PRIVKEY_OUT memory is correctly retrieved + if (privkey_out_mem != null) begin + //`uvm_info("PRED_AHB", $sformatf("MLDSA_PRIVKEY_OUT: Base Addr = 0x%0h, Size = %0d", privkey_out_base_addr, privkey_out_size), UVM_LOW) + end + else begin + `uvm_fatal("PRED_AHB", "Could not retrieve MLDSA_PRIVKEY_OUT memory from sub-map") + end + + // Retrieve base address and memory object for MLDSA_PRIVKEY_IN + privkey_in_base_addr = p_mldsa_rm.default_map.get_submap_offset(p_mldsa_rm.MLDSA_PRIVKEY_IN.default_map); + privkey_in_mem = p_mldsa_rm.default_map.get_mem_by_offset(privkey_in_base_addr); + privkey_in_size = uvm_reg_addr_t'(privkey_in_mem.get_size()); + + // Check if MLDSA_PRIVKEY_IN memory is correctly retrieved + if (privkey_in_mem != null) begin + //`uvm_info("PRED_AHB", $sformatf("MLDSA_PRIVKEY_IN: Base Addr = 0x%0h, Size = %0d", privkey_in_base_addr, privkey_in_size), UVM_LOW) + end + else begin + `uvm_fatal("PRED_AHB", "Could not retrieve MLDSA_PRIVKEY_IN memory from sub-map") + end + + // Retrieve base address and memory object for MLDSA_SIGNATURE + signature_base_addr = p_mldsa_rm.default_map.get_submap_offset(p_mldsa_rm.MLDSA_SIGNATURE.default_map); + signature_mem = p_mldsa_rm.default_map.get_mem_by_offset(signature_base_addr); + signature_size = uvm_reg_addr_t'(signature_mem.get_size()); + + // Check if MLDSA_SIGNATURE memory is correctly retrieved + if (signature_mem != null) begin + //`uvm_info("PRED_AHB", $sformatf("MLDSA_SIGNATURE: Base Addr = 0x%0h, Size = %0d", signature_base_addr, signature_size), UVM_LOW) + end + else begin + `uvm_fatal("PRED_AHB", "Could not retrieve MLDSA_SIGNATURE memory from sub-map") + end + + // Retrieve base address and memory object for MLDSA_PUBKEY + pubkey_base_addr = p_mldsa_rm.default_map.get_submap_offset(p_mldsa_rm.MLDSA_PUBKEY.default_map); + pubkey_mem = p_mldsa_rm.default_map.get_mem_by_offset(pubkey_base_addr); + pubkey_size = uvm_reg_addr_t'(pubkey_mem.get_size()); + + // Check if MLDSA_PUBKEY memory is correctly retrieved + if (pubkey_mem != null) begin + //`uvm_info("PRED_AHB", $sformatf("MLDSA_PUBKEY: Base Addr = 0x%0h, Size = %0d", pubkey_base_addr, pubkey_size), UVM_LOW) + end + else begin + `uvm_fatal("PRED_AHB", "Could not retrieve MLDSA_PUBKEY memory from sub-map") + end + reg_addr = t.address; + MEM_range_true = (reg_addr >= privkey_in_base_addr && reg_addr < privkey_in_base_addr + privkey_in_size * 4) + || + (reg_addr >= privkey_out_base_addr && reg_addr < privkey_out_base_addr + privkey_out_size * 4) + || + (reg_addr >= signature_base_addr && reg_addr < signature_base_addr + signature_size * 4) + || + (reg_addr >= pubkey_base_addr && reg_addr < pubkey_base_addr + pubkey_size * 4); + +//=========================================================================================== + if (t.RnW == 1'b1) begin // write + if (reg_obj == null && !MEM_range_true) begin + `uvm_error("PRED_AHB", $sformatf("AHB transaction to address: 0x%x decodes to null from AHB_map", t.address)) + end + else begin + uvm_reg_addr_t base_addr; + int idx; + if (reg_addr >= p_mldsa_rm.MLDSA_SEED[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_SEED[$size(p_mldsa_rm.MLDSA_SEED)-1].get_address(p_mldsa_map)) begin + base_addr = p_mldsa_rm.MLDSA_SEED[0].get_address(p_mldsa_map); + idx = (reg_addr - base_addr) / 4; + SEED[idx] = t.data[0][31:0]; + end + else if (reg_addr >= p_mldsa_rm.MLDSA_MSG[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_MSG[$size(p_mldsa_rm.MLDSA_MSG)-1].get_address(p_mldsa_map)) begin + base_addr = p_mldsa_rm.MLDSA_MSG[0].get_address(p_mldsa_map); + idx = (reg_addr - base_addr) / 4; + MSG[idx] = t.data[0][31:0]; + end + // Accessing data in MLDSA_PRIVKEY_IN + else if (reg_addr >= privkey_in_base_addr && reg_addr < privkey_in_base_addr + privkey_in_size * 4) begin + idx = (reg_addr - privkey_in_base_addr) / 4; + SK[idx] = t.data[0][31:0]; + //`uvm_info("PRED_AHB", $sformatf("Writing to MLDSA_PRIVKEY_IN: Addr = 0x%0h, Data = 0x%0h", reg_addr, t.data[0][31:0]), UVM_LOW) + end + // Accessing data in MLDSA_PUBKEY + else if (reg_addr >= pubkey_base_addr && reg_addr < pubkey_base_addr + pubkey_size * 4) begin + idx = (reg_addr - pubkey_base_addr) / 4; + PK[idx] = t.data[0][31:0]; + //`uvm_info("PRED_AHB", $sformatf("Writing to MLDSA_PUBKEY: Addr = 0x%0h, Data = 0x%0h", reg_addr, t.data[0][31:0]), UVM_LOW) + end + // Accessing data in MLDSA_SIGNATURE + else if (reg_addr >= signature_base_addr && reg_addr < signature_base_addr + signature_size * 4) begin + idx = (reg_addr - signature_base_addr) / 4; + SIG[idx] = t.data[0][31:0]; + //`uvm_info("PRED_AHB", $sformatf("Writing to MLDSA_SIGNATURE: Addr = 0x%0h, Data = 0x%0h", reg_addr, t.data[0][31:0]), UVM_LOW) + end + else if (reg_addr == p_mldsa_rm.MLDSA_CTRL.get_address(p_mldsa_map)) begin + run_executable(t.data[0][2:0]); + zeroize_registers(t.data[0][3]); + end + else if (reg_addr >= p_mldsa_rm.MLDSA_SIGN_RND[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_SIGN_RND[$size(p_mldsa_rm.MLDSA_SIGN_RND)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_SIGN_RND at address: 0x%x", reg_addr), UVM_HIGH) + end + else begin + `uvm_error("PRED_AHB", $sformatf("Unhandled register write at address: 0x%x", reg_addr)) + end + end + end + else if (t.RnW == 1'b0) begin // read + if (reg_obj == null && !MEM_range_true) begin + `uvm_error("PRED_AHB", $sformatf("AHB transaction to address: 0x%x decodes to null from AHB_map", t.address)) + end + else begin + uvm_reg_addr_t base_addr; + // uvm_reg_addr_t reg_addr = t.address; + int idx; + // Accessing data in MLDSA_PRIVKEY_OUT + if (reg_addr >= privkey_out_base_addr && reg_addr < privkey_out_base_addr + privkey_out_size * 4) begin + idx = (reg_addr - privkey_out_base_addr) / 4; + if (idx < privkey_out_size) begin + t.data[0][31:0] = SK[idx]; // Example read from SK + //`uvm_info("PRED_AHB", $sformatf("Reading from MLDSA_PRIVKEY_OUT: Addr = 0x%0h, Data = 0x%0h", reg_addr, t.data[0][31:0]), UVM_LOW) + end + else begin + `uvm_error("PRED_AHB", "Private key out read out of bounds") + end + end + // Accessing data in MLDSA_PUBKEY + else if (reg_addr >= pubkey_base_addr && reg_addr < pubkey_base_addr + pubkey_size * 4) begin + idx = (reg_addr - pubkey_base_addr) / 4; + if (idx < pubkey_size) begin + t.data[0][31:0] = PK[idx]; // Example read from SIG + //`uvm_info("PRED_AHB", $sformatf("Reading from MLDSA_PUBKEY: Addr = 0x%0h, Data = 0x%0h", reg_addr, t.data[0][31:0]), UVM_LOW) + end + else begin + `uvm_error("PRED_AHB", "Pubkey read out of bounds") + end + end + // Accessing data in MLDSA_SIGNATURE + else if (reg_addr >= signature_base_addr && reg_addr < signature_base_addr + signature_size * 4) begin + idx = (reg_addr - signature_base_addr) / 4; + if (idx < signature_size) begin + t.data[0][31:0] = SIG[idx]; // Example read from SIG + //`uvm_info("PRED_AHB", $sformatf("Reading from MLDSA_SIGNATURE: Addr = 0x%0h, Data = 0x%0h", reg_addr, t.data[0][31:0]), UVM_LOW) + end + else begin + `uvm_error("PRED_AHB", "Signature read out of bounds") + end + end + else if (reg_addr >= p_mldsa_rm.MLDSA_VERIFY_RES[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_VERIFY_RES[$size(p_mldsa_rm.MLDSA_VERIFY_RES)-1].get_address(p_mldsa_map)) begin + base_addr = p_mldsa_rm.MLDSA_VERIFY_RES[0].get_address(p_mldsa_map); + idx = (reg_addr - base_addr) / 4; + if (idx < $size(VERIF)) begin + t.data[0][31:0] = VERIF[idx]; + end + else begin + `uvm_error("PRED_AHB", "Verification result read out of bounds") + end + end + else if (reg_addr >= p_mldsa_rm.MLDSA_NAME[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_NAME[$size(p_mldsa_rm.MLDSA_NAME)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_NAME at address: 0x%x", reg_addr), UVM_HIGH) + end + else if (reg_addr >= p_mldsa_rm.MLDSA_VERSION[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_VERSION[$size(p_mldsa_rm.MLDSA_VERSION)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_VERSION at address: 0x%x", reg_addr), UVM_HIGH) + end + else if (reg_addr == p_mldsa_rm.MLDSA_CTRL.get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_CTRL at address: 0x%x", reg_addr), UVM_HIGH) + end + else if (reg_addr == p_mldsa_rm.MLDSA_STATUS.get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_STATUS at address: 0x%x", reg_addr), UVM_HIGH) + // // This part checks if data is valid + // data = t.data[0][31:0]; + // valid = data[1]; + // if (valid) begin + // lock_IP = 0; + // `uvm_info("PRED_AHB", $sformatf("The IP done signal released the lock"), UVM_LOW) + // end else begin + // lock_IP = lock_IP; + // end + end + else if (reg_addr >= p_mldsa_rm.MLDSA_ENTROPY[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_ENTROPY[$size(p_mldsa_rm.MLDSA_ENTROPY)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_ENTROPY at address: 0x%x", reg_addr), UVM_HIGH) + end + else if (reg_addr >= p_mldsa_rm.MLDSA_SEED[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_SEED[$size(p_mldsa_rm.MLDSA_SEED)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_SEED at address: 0x%x", reg_addr), UVM_HIGH) + end + else if (reg_addr >= p_mldsa_rm.MLDSA_SIGN_RND[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_SIGN_RND[$size(p_mldsa_rm.MLDSA_SIGN_RND)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_SIGN_RND at address: 0x%x", reg_addr), UVM_HIGH) + end + else if (reg_addr >= p_mldsa_rm.MLDSA_MSG[0].get_address(p_mldsa_map) && + reg_addr <= p_mldsa_rm.MLDSA_MSG[$size(p_mldsa_rm.MLDSA_MSG)-1].get_address(p_mldsa_map)) begin + `uvm_info("PRED_AHB", $sformatf("Skipping register MLDSA_MSG at address: 0x%x", reg_addr), UVM_HIGH) + end + // Add more cases as needed for other registers + else begin + `uvm_error("PRED_AHB", $sformatf("Unhandled register read at address: 0x%x", reg_addr)) + end + // Send the transaction to the scoreboard + mldsa_sb_ahb_ap_output_transaction.copy(t); + mldsa_sb_ahb_ap.write(mldsa_sb_ahb_ap_output_transaction); + end + end + + + // Code for sending output transaction out through mldsa_sb_ahb_ap + // pragma uvmf custom ahb_slave_0_ae_predictor end + endfunction + + function void run_executable(bit [2:0] op_code); + string input_file; + string output_file; + string line; + int words_read; + bit [31:0] value; + int fd; + if (!lock_IP) begin + case (op_code) + 3'b000: begin + `uvm_info("PRED", "CTRL Reg is written 3'b00 (No operation)...", UVM_MEDIUM) + end + 3'b001: begin + lock_IP = 1; + output_file = "./keygen_input.hex"; + input_file = "./keygen_output.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", op_code-1); // KeyGen cmd + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // $system("test_dilithium5 keygen_input.hex keygen_output.hex"); + $system($sformatf("./%s keygen_input.hex keygen_output.hex >> keygen.log", dilithium_command)); + `uvm_info("PRED", $sformatf("%s is being executed", dilithium_command), UVM_MEDIUM) + `uvm_info("PRED", "CTRL Reg is configured to perform KeyGen", UVM_MEDIUM) + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + read_line(fd, 1224, SK); // Read 4864-byte Secret Key to the file + $fclose(fd); + end + 3'b010: begin + lock_IP = 1; + output_file = "./signing_input.hex"; + input_file = "./signing_ouput.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", op_code-1); // Signature generation cmd + write_file(fd, 16, MSG); // Write 64-byte Message to the file + write_file(fd, 1224, SK); // Write 4864-byte Secret Key to the file + $fclose(fd); + //$system("test_dilithium5 signing_input.hex signing_ouput.hex"); + $system($sformatf("./%s signing_input.hex signing_ouput.hex >> signing.log", dilithium_command)); + `uvm_info("PRED", "CTRL Reg is configured to perform Signature Generation", UVM_MEDIUM) + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%08x\n", value)); + read_line(fd, 1157, SIG);// Read 4864-byte Signature to the file + SIG[0] = SIG[0] >> 8; + $fclose(fd); + end + 3'b011: begin + lock_IP = 1; + if ( ! expect_predictor_verif_failure) begin + output_file = "./verif_input.hex"; + input_file = "./verif_ouput.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", op_code-1); // Verification cmd + //$fwrite(fd, "00001253\n"); // Signature lenght + // write_file(fd, 1157, SIG); // Write 4864-byte Signature to the file + write_file_without_newline(fd, 1157, SIG); + $fwrite(fd, "%02X%02X%02X", SIG[0][7:0],SIG[0][15:8],SIG[0][23:16]); + write_file(fd, 16, MSG); // Write 64-byte message to the file + write_file(fd, 648, PK); // Write 2592-byte Public Key to the file + $fclose(fd); + $system($sformatf("./%s verif_input.hex verif_ouput.hex >> verif.log", dilithium_command)); + `uvm_info("PRED", "CTRL Reg is configured to perform Verification", UVM_MEDIUM) + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 16, VERIF);// Read 16 dword verify result from the file + $fclose(fd); + end + else begin + input_file = "./verif_ouput.hex"; + $system($sformatf("./%s verif_failure_input_test.hex verif_ouput.hex >> verif.log", dilithium_command)); + `uvm_info("PRED", "CTRL Reg is configured to perform Verification", UVM_MEDIUM) + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + read_line(fd, 16, VERIF);// Read 16 dword verify result from the file + $fclose(fd); + end + end + 3'b100: begin + lock_IP = 1; + output_file = "./keygen_input.hex"; + input_file = "./keygen_output.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 0); // KeyGen cmd + write_file(fd, 32/4, SEED); // Write 32-byte SEED to the file + $fclose(fd); + // $system("test_dilithium5 keygen_input.hex keygen_output.hex"); + $system($sformatf("./%s keygen_input.hex keygen_output.hex >> keygen.log", dilithium_command)); + `uvm_info("PRED", $sformatf("%s is being executed", dilithium_command), UVM_MEDIUM) + `uvm_info("PRED", "CTRL Reg is configured to perform KeyGen", UVM_MEDIUM) + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + read_line(fd, 648, PK); // Read 2592-byte Public Key to the file + read_line(fd, 1224, SK); // Read 4864-byte Secret Key to the file + $fclose(fd); + //Perform Signing + output_file = "./signing_input.hex"; + input_file = "./signing_ouput.hex"; + // Open the file for writing + fd = $fopen(output_file, "w"); + if (fd == 0) begin + $display("ERROR: Failed to open file: %s", output_file); + return; + end + $fwrite(fd, "%02X\n", 1); // Signature generation cmd + write_file(fd, 16, MSG); // Write 64-byte Message to the file + write_file(fd, 1224, SK); // Write 4864-byte Secret Key to the file + $fclose(fd); + //$system("test_dilithium5 signing_input.hex signing_ouput.hex"); + $system($sformatf("./%s signing_input.hex signing_ouput.hex >> signing.log", dilithium_command)); + `uvm_info("PRED", "CTRL Reg is configured to perform Signature Generation", UVM_MEDIUM) + // Open the file for reading + fd = $fopen(input_file, "r"); + if (fd == 0) begin + `uvm_error("PRED", $sformatf("Failed to open input_file: %s", input_file)); + return; + end + else begin + // Skip the first line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%02x\n", value)); + end + // Skip the second line + void'($fgets(line, fd)); // Read a line from the file + void'($sscanf(line, "%08x\n", value)); + read_line(fd, 1157, SIG);// Read 4864-byte Signature to the file + SIG[0] = SIG[0] >> 8; + $fclose(fd); + + end + endcase + end + if (lock_IP) + `uvm_info("PRED_RUN_EXE", $sformatf("The IP is locked"), UVM_LOW) + endfunction + + + function void zeroize_registers(bit zeroize); + + // Define the zero_value at the beginning + uvm_reg_data_t zero_value = 32'b0; + + if (zeroize) begin + lock_IP = 0; + + // Zeroize local variables + foreach (SEED[i]) begin + SEED[i] = 32'b0; + end + foreach (SK[i]) begin + SK[i] = 32'b0; + end + foreach (PK[i]) begin + PK[i] = 32'b0; + end + foreach (MSG[i]) begin + MSG[i] = 32'b0; + end + foreach (SIG[i]) begin + SIG[i] = 32'b0; + end + foreach (VERIF[i]) begin + VERIF[i] = 32'b0; + end + + // Zeroize registers in the register block using set method + foreach (p_mldsa_rm.MLDSA_NAME[i]) begin + p_mldsa_rm.MLDSA_NAME[i].set(zero_value); + end + foreach (p_mldsa_rm.MLDSA_VERSION[i]) begin + p_mldsa_rm.MLDSA_VERSION[i].set(zero_value); + end + p_mldsa_rm.MLDSA_CTRL.set(zero_value); + p_mldsa_rm.MLDSA_STATUS.set(zero_value); + foreach (p_mldsa_rm.MLDSA_ENTROPY[i]) begin + p_mldsa_rm.MLDSA_ENTROPY[i].set(zero_value); + end + foreach (p_mldsa_rm.MLDSA_SEED[i]) begin + p_mldsa_rm.MLDSA_SEED[i].set(zero_value); + end + foreach (p_mldsa_rm.MLDSA_SIGN_RND[i]) begin + p_mldsa_rm.MLDSA_SIGN_RND[i].set(zero_value); + end + foreach (p_mldsa_rm.MLDSA_MSG[i]) begin + p_mldsa_rm.MLDSA_MSG[i].set(zero_value); + end + foreach (p_mldsa_rm.MLDSA_VERIFY_RES[i]) begin + p_mldsa_rm.MLDSA_VERIFY_RES[i].set(zero_value); + end + //foreach (p_mldsa_rm.MLDSA_PRIVKEY_OUT[i]) begin + // p_mldsa_rm.MLDSA_PRIVKEY_OUT[i].set(zero_value); + //end + //foreach (p_mldsa_rm.MLDSA_PRIVKEY_IN[i]) begin + // p_mldsa_rm.MLDSA_PRIVKEY_IN[i].set(zero_value); + //end + //foreach (p_mldsa_rm.MLDSA_PUBKEY[i]) begin + // p_mldsa_rm.MLDSA_PUBKEY[i].set(zero_value); + //end + //foreach (p_mldsa_rm.MLDSA_SIGNATURE[i]) begin + // p_mldsa_rm.MLDSA_SIGNATURE[i].set(zero_value); + //end + end + endfunction + + + + + function void read_line(int fd, int bit_length_words, ref bit [31:0] array []); + string line; + int words_read; + bit [31:0] word; + bit [31:0] reversed_word; + + // Read the data from the file line by line + words_read = 0; + while (!$feof(fd) && words_read < bit_length_words) begin + line = ""; + void'($fgets(line, fd)); // Read a line from the file + while ($sscanf(line, "%08x", word) == 1) begin + reversed_word = {word[7:0], word[15:8], word[23:16], word[31:24]}; + array[(bit_length_words-1)-words_read] = reversed_word; + words_read++; + // Remove the parsed part from the line + line = line.substr(8); + end + end + endfunction + + function void write_file(int fd, int bit_length_words, bit [31:0] array []); + int i; + int words_to_write; + + // Write the data from the array to the file + words_to_write = bit_length_words; + for (i = 0; i < words_to_write; i++) begin + $fwrite(fd, "%02X%02X%02X%02X", array[(words_to_write-1)-i][7:0], array[(words_to_write-1)-i][15:8], + array[(words_to_write-1)-i][23:16],array[(words_to_write-1)-i][31:24]); + end + $fwrite(fd, "\n"); + + endfunction + + function void write_file_without_newline(int fd, int bit_length_words, bit [31:0] array []); + int i; + int words_to_write; + + // Write the data from the array to the file + words_to_write = bit_length_words; + for (i = 0; i < words_to_write-1; i++) begin + $fwrite(fd, "%02X%02X%02X%02X", array[(words_to_write-1)-i][7:0], array[(words_to_write-1)-i][15:8], + array[(words_to_write-1)-i][23:16],array[(words_to_write-1)-i][31:24]); + end + + endfunction + + + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_scoreboard.svh b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_scoreboard.svh new file mode 100644 index 0000000000000000000000000000000000000000..d7b2f1c00e9d7bc36f1dc6bd5229f9cf230ef348 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/src/mldsa_scoreboard.svh @@ -0,0 +1,292 @@ +//---------------------------------------------------------------------- +// Created with uvmf_gen version 2022.3 +//---------------------------------------------------------------------- +// pragma uvmf custom header begin +// pragma uvmf custom header end +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// +// DESCRIPTION: This analysis component contains analysis_exports for receiving +// data and analysis_ports for sending data. +// +// This analysis component has the following analysis_exports that receive the +// listed transaction type. +// +// actual_ahb_analysis_export receives transactions of type ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) +// +// This analysis component has the following analysis_ports that can broadcast +// the listed transaction type. +// +//---------------------------------------------------------------------- +//---------------------------------------------------------------------- +// + + +class mldsa_scoreboard #( + type CONFIG_T, + type BASE_T = uvm_component + ) + extends BASE_T; + + // Factory registration of this class + `uvm_component_param_utils( mldsa_scoreboard #( + CONFIG_T, + BASE_T + ) +) + + + // Instantiate a handle to the configuration of the environment in which this component resides + CONFIG_T configuration; + + + // Instantiate the analysis exports + uvm_analysis_imp_actual_ahb_analysis_export #(mvc_sequence_item_base, mldsa_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) actual_ahb_analysis_export; + + + + // Instantiate QVIP analysis exports + uvm_analysis_imp_expected_ahb_analysis_export #(mvc_sequence_item_base, mldsa_scoreboard #( + .CONFIG_T(CONFIG_T), + .BASE_T(BASE_T) + ) +) expected_ahb_analysis_export; + + + // pragma uvmf custom class_item_additional begin + // Use Queues for AHB/APB txns since there is no get_key() method + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_expected_q [$]; + + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_actual_q [$]; + + + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, + ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, + ahb_lite_slave_0_params::AHB_NUM_SLAVES, + ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, + ahb_lite_slave_0_params::AHB_WDATA_WIDTH, + ahb_lite_slave_0_params::AHB_RDATA_WIDTH) ahb_expected_verif_q [$]; + + + // pragma uvmf custom class_item_additional end + bit expect_verif_failure = 0; + int transaction_count = 0; + int verif_transaction_count = 0; + int match_count = 0; + int mismatch_count = 0; + int verif_unexpected_match_count = 0; + int nothing_to_compare_against_count = 0; + event entry_received; + mldsa_reg_model_top scbr_mldsa_rm; + uvm_reg_map scbr_mldsa_map; // Block map + + // FUNCTION: new + function new(string name, uvm_component parent); + super.new(name,parent); + // pragma uvmf custom new begin + // pragma uvmf custom new end + endfunction + + // FUNCTION: build_phase + virtual function void build_phase (uvm_phase phase); + + actual_ahb_analysis_export = new("actual_ahb_analysis_export", this); + expected_ahb_analysis_export = new("expected_ahb_analysis_export", this); + // pragma uvmf custom build_phase begin + + if (!uvm_config_db#(bit)::get(this, "", "expect_verif_failure", expect_verif_failure)) begin + expect_verif_failure = '0; // default value + end + + `uvm_info("SCOREBOARD", $sformatf("expect_verif_failure to be used: %d", expect_verif_failure), UVM_LOW) + // Instantiate the register model + // scbr_mldsa_rm = mldsa_reg_model_top::type_id::create("scbr_mldsa_rm", this); + scbr_mldsa_rm = configuration.mldsa_rm; + scbr_mldsa_map = scbr_mldsa_rm.get_default_map(); + // pragma uvmf custom build_phase end + endfunction + + // FUNCTION: write_actual_ahb_analysis_export + // Transactions received through actual_ahb_analysis_export initiate the execution of this function. + // This function performs prediction of DUT output values based on DUT input, configuration and state + // FUNCTION: write_actual_ahb_analysis_export + // QVIP transactions received through actual_ahb_analysis_export initiate the execution of this function. + // This function casts incoming QVIP transactions into the correct protocol type and then performs prediction + // of DUT output values based on DUT input, configuration and state + virtual function void write_actual_ahb_analysis_export(mvc_sequence_item_base _t); + // pragma uvmf custom actual_ahb_analysis_export_scoreboard begin + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) t; + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) t_exp; + bit txn_eq; + if (!$cast(t,_t)) begin + `uvm_fatal("SCBD_AHB","Cast from mvc_sequence_item_base to ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) in write_actual_ahb_analysis_export failed!") + end + // `uvm_info("SCBD_AHB", "Transaction Received through actual_ahb_analysis_export", UVM_MEDIUM) + // `uvm_info("SCBD_AHB",{" Data: ",t.convert2string()}, UVM_HIGH) + + if (t.RnW == 1'b0) begin + // `uvm_info("SCBD_AHB", "Transaction is a read", UVM_MEDIUM) + // Check if the transaction address matches any of the registers to be skipped + if ((t.address >= scbr_mldsa_rm.MLDSA_NAME[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_NAME[$size(scbr_mldsa_rm.MLDSA_NAME)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_VERSION[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_VERSION[$size(scbr_mldsa_rm.MLDSA_VERSION)-1].get_address(scbr_mldsa_map)) || + (t.address == scbr_mldsa_rm.MLDSA_CTRL.get_address(scbr_mldsa_map)) || + (t.address == scbr_mldsa_rm.MLDSA_STATUS.get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_ENTROPY[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_ENTROPY[$size(scbr_mldsa_rm.MLDSA_ENTROPY)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_SEED[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_SEED[$size(scbr_mldsa_rm.MLDSA_SEED)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_SIGN_RND[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_SIGN_RND[$size(scbr_mldsa_rm.MLDSA_SIGN_RND)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_MSG[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_MSG[$size(scbr_mldsa_rm.MLDSA_MSG)-1].get_address(scbr_mldsa_map)) + ) begin + `uvm_info("SCBD_AHB", $sformatf("Skipping register access in scoreboard at address: 0x%x", t.address), UVM_HIGH) + end + else if ( (t.address >= scbr_mldsa_rm.MLDSA_VERIFY_RES[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_VERIFY_RES[$size(scbr_mldsa_rm.MLDSA_VERIFY_RES)-1].get_address(scbr_mldsa_map)) && + expect_verif_failure && + ahb_expected_verif_q.size() > 0) + begin + t_exp = ahb_expected_verif_q.pop_front(); + txn_eq = (t_exp.data[0][31:0] == t.data[0][31:0]); + // `uvm_info("SCBD_AHB",{" Poped Data: ",t_exp.convert2string()}, UVM_MEDIUM) + if ((t_exp.data[0][31:0] == t.data[0][31:0])) begin + verif_unexpected_match_count++; + // `uvm_info ("SCBD_AHB", $sformatf("Actual AHB txn with {Address: 0x%x} {Data: 0x%x} {RnW: %p} matches expected",t.address,t.data[0],t.RnW), UVM_MEDIUM) + end + verif_transaction_count++; + if (verif_transaction_count==16 && verif_unexpected_match_count==16) begin + verif_transaction_count = 0; + `uvm_error("SCBD_AHB", $sformatf("Although the verification failure is expected, the verif result matches with the successful verif output")) + end + else if (verif_transaction_count==16 && verif_unexpected_match_count<16) begin + verif_transaction_count = 0; + end + end + else if (ahb_expected_q.size() > 0) begin + t_exp = ahb_expected_q.pop_front(); + txn_eq = (t_exp.data[0][31:0] == t.data[0][31:0]); + // `uvm_info("SCBD_AHB",{" Poped Data: ",t_exp.convert2string()}, UVM_MEDIUM) + if ((t_exp.data[0][31:0] == t.data[0][31:0])) begin + match_count++; + // `uvm_info ("SCBD_AHB", $sformatf("Actual AHB txn with {Address: 0x%x} {Data: 0x%x} {RnW: %p} matches expected",t.address,t.data[0],t.RnW), UVM_MEDIUM) + end + else begin + mismatch_count++; + `uvm_error("SCBD_AHB", $sformatf("Actual AHB txn with {Address: 0x%x} {Data: 0x%x} {RnW: %p} {Resp: %p} does not match expected: {Address: 0x%x} {Data: 0x%x} {RnW: %p} {Resp: %p}",t.address,t.data[0],t.RnW,t.resp[0],t_exp.address,t_exp.data[0],t_exp.RnW,t_exp.resp[0])) + end + end + else begin + `uvm_info("FIXME_CUSTOM_SCOREBOARD", "UVMF_CHANGE_ME: The mldsa_scoreboard::write_actual_ahb_analysis_export function needs to be completed with custom scoreboard functionality for unexpected actual transactions",UVM_HIGH) + `uvm_error("SCBD_AHB",$sformatf("NO PREDICTED ENTRY TO COMPARE AGAINST:%s",t.convert2string())) + nothing_to_compare_against_count++; + end + -> entry_received; + end + + // pragma uvmf custom actual_ahb_analysis_export_scoreboard end + endfunction + + + /// FUNCTION: write_expected_ahb_analysis_export + // QVIP transactions received through expected_ahb_analysis_export initiate the execution of this function. + // This function casts incoming QVIP transactions into the correct protocol type and then performs prediction + // of DUT output values based on DUT input, configuration and state + virtual function void write_expected_ahb_analysis_export(mvc_sequence_item_base _t); + // pragma uvmf custom expected_ahb_analysis_export_scoreboard begin + ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) t; + if (!$cast(t,_t)) begin + `uvm_fatal("SCBD_AHB","Cast from mvc_sequence_item_base to ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH) in write_expected_ahb_analysis_export failed!") + end + // `uvm_info("SCBD_AHB", "Transaction Received through expected_ahb_analysis_export", UVM_MEDIUM) + // `uvm_info("SCBD_AHB",{" Data: ",t.convert2string()}, UVM_HIGH) + if (t.RnW == 1'b0) begin + // `uvm_info("SCBD_AHB", "Transaction is a read", UVM_MEDIUM) + // Check if the transaction address matches any of the registers to be skipped + if ((t.address >= scbr_mldsa_rm.MLDSA_NAME[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_NAME[$size(scbr_mldsa_rm.MLDSA_NAME)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_VERSION[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_VERSION[$size(scbr_mldsa_rm.MLDSA_VERSION)-1].get_address(scbr_mldsa_map)) || + (t.address == scbr_mldsa_rm.MLDSA_CTRL.get_address(scbr_mldsa_map)) || + (t.address == scbr_mldsa_rm.MLDSA_STATUS.get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_ENTROPY[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_ENTROPY[$size(scbr_mldsa_rm.MLDSA_ENTROPY)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_SEED[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_SEED[$size(scbr_mldsa_rm.MLDSA_SEED)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_SIGN_RND[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_SIGN_RND[$size(scbr_mldsa_rm.MLDSA_SIGN_RND)-1].get_address(scbr_mldsa_map)) || + (t.address >= scbr_mldsa_rm.MLDSA_MSG[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_MSG[$size(scbr_mldsa_rm.MLDSA_MSG)-1].get_address(scbr_mldsa_map)) + ) begin + `uvm_info("SCBD_AHB", $sformatf("Skipping monitor message in scoreboard at address: 0x%x", t.address), UVM_HIGH) + end + else if ( (t.address >= scbr_mldsa_rm.MLDSA_VERIFY_RES[0].get_address(scbr_mldsa_map) && + t.address <= scbr_mldsa_rm.MLDSA_VERIFY_RES[$size(scbr_mldsa_rm.MLDSA_VERIFY_RES)-1].get_address(scbr_mldsa_map)) && + expect_verif_failure + )begin + + ahb_expected_verif_q.push_back(t); + -> entry_received; + end + else begin + + ahb_expected_q.push_back(t); + + transaction_count++; + -> entry_received; + end + end + + // pragma uvmf custom expected_ahb_analysis_export_scoreboard end + endfunction + + + // FUNCTION: extract_phase + virtual function void extract_phase(uvm_phase phase); +// pragma uvmf custom extract_phase begin + super.extract_phase(phase); +// pragma uvmf custom extract_phase end + endfunction + + // FUNCTION: check_phase + virtual function void check_phase(uvm_phase phase); +// pragma uvmf custom check_phase begin + super.check_phase(phase); +// pragma uvmf custom check_phase end + endfunction + + // FUNCTION: report_phase + virtual function void report_phase(uvm_phase phase); +// pragma uvmf custom report_phase begin + super.report_phase(phase); + `uvm_info("SCBD_REPORT", $sformatf("Total Matches: %0d", match_count), UVM_LOW) + `uvm_info("SCBD_REPORT", $sformatf("Total Mismatches: %0d", mismatch_count), UVM_LOW) + `uvm_info("SCBD_REPORT", $sformatf("No Predicted Entries to Compare Against: %0d", nothing_to_compare_against_count), UVM_LOW) + if (mismatch_count == 0) + $display("* TESTCASE PASSED"); + else + $display("* TESTCASE FAILED"); +// pragma uvmf custom report_phase end + endfunction + +endclass + +// pragma uvmf custom external begin +// pragma uvmf custom external end + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_environment.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_environment.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9e9af6454f3bf714dda4064f67692b4f36ce0c3f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_environment.yaml @@ -0,0 +1,51 @@ +uvmf: + environments: + mldsa: + agents: [] + analysis_components: + - name: mldsa_pred + parameters: [] + type: mldsa_predictor + - name: mldsa_sb + parameters: [] + type: mldsa_scoreboard + analysis_exports: [] + analysis_ports: [] + config_constraints: [] + config_vars: [] + existing_library_component: 'True' + hvl_pkg_parameters: [] + imports: + - name: mvc_pkg + - name: mgc_ahb_v2_0_pkg + - name: rw_txn_pkg + non_uvmf_components: [] + parameters: [] + qvip_connections: + - ap_key: burst_transfer + driver: qvip_ahb_lite_slave_subenv_ahb_lite_slave_0 + receiver: mldsa_pred.ahb_slave_0_ae + validate: 'false' + - ap_key: trans_ap + driver: qvip_ahb_lite_slave_subenv_ahb_lite_slave_0 + receiver: mldsa_sb.actual_ahb_analysis_export + validate: 'false' + qvip_memory_agents: [] + qvip_subenvs: + - name: qvip_ahb_lite_slave_subenv + type: qvip_ahb_lite_slave + register_model: + maps: + - interface: qvip_ahb_lite_slave_subenv.ahb_lite_slave_0 + name: fixme_map + qvip_agent: 'True' + reg_block_class: mldsa_reg_model_top + reg_model_package: mldsa_reg_model_top_pkg + use_adapter: 'True' + use_explicit_prediction: 'True' + scoreboards: [] + subenvs: [] + tlm_connections: + - driver: mldsa_pred.mldsa_sb_ahb_ap + receiver: mldsa_sb.expected_ahb_analysis_export + validate: 'false' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_util_comp_mldsa_predictor.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_util_comp_mldsa_predictor.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2a3171ec4705c90c6aa1957d8493544fe90e6853 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_util_comp_mldsa_predictor.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + mldsa_predictor: + analysis_ports: + - name: mldsa_sb_ahb_ap + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + existing_library_component: 'True' + qvip_analysis_exports: + - name: ahb_slave_0_ae + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + type: predictor diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_util_comp_mldsa_scoreboard.yaml b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_util_comp_mldsa_scoreboard.yaml new file mode 100644 index 0000000000000000000000000000000000000000..658310515356f21a93588e3ee31b2a6b71e8017a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/mldsa_top/uvmf/uvmf_template_output/verification_ip/environment_packages/mldsa_env_pkg/yaml/mldsa_util_comp_mldsa_scoreboard.yaml @@ -0,0 +1,11 @@ +uvmf: + util_components: + mldsa_scoreboard: + analysis_exports: + - name: actual_ahb_analysis_export + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + existing_library_component: 'True' + qvip_analysis_exports: + - name: expected_ahb_analysis_export + type: 'ahb_master_burst_transfer #(ahb_lite_slave_0_params::AHB_NUM_MASTERS, ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS, ahb_lite_slave_0_params::AHB_NUM_SLAVES, ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH, ahb_lite_slave_0_params::AHB_WDATA_WIDTH, ahb_lite_slave_0_params::AHB_RDATA_WIDTH)' + type: scoreboard diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..62dbad600ad5cefd6133b6ffee4e4d0a7477e3b9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/compile.yml @@ -0,0 +1,49 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [norm_check_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/norm_check_defines_pkg.sv + tb: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/norm_check_defines_pkg.sv +--- +provides: [norm_check] +schema_version: 2.4.0 +requires: + - norm_check_pkg + - mldsa_defines +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/norm_check.sv + - $COMPILE_ROOT/rtl/norm_check_ctrl.sv + - $COMPILE_ROOT/rtl/norm_check_top.sv + tops: [norm_check] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/norm_check/config/design_lint/norm_check/sglint_waivers +--- +provides: [norm_check_tb] +schema_version: 2.4.0 +requires: + - norm_check + - norm_check_pkg + - mldsa_defines +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/norm_check_tb.sv + tops: [norm_check_tb] \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check.vf new file mode 100644 index 0000000000000000000000000000000000000000..33f33bf1c8b4fe8f4bb76a7da05f1399416394d8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check.vf @@ -0,0 +1,9 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..80f1f7fe33289fd41f8afea1184d05b1f8b0e8ab --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check_pkg.vf @@ -0,0 +1,3 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..15794e27ef2883471c6ef0007a4d78f723d0a54e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/config/norm_check_tb.vf @@ -0,0 +1,11 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/tb +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv +${ADAMSBRIDGE_ROOT}/src/norm_check/tb/norm_check_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check.sv new file mode 100644 index 0000000000000000000000000000000000000000..956e1b0bfc7573429580610f344a15de7e46967f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check.sv @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// norm_check.sv +// -------- +// Performs: invalid = (coeff > bound) && (coeff < q-bound) + +module norm_check + import norm_check_defines_pkg::*; + import mldsa_params_pkg::*; + #( + parameter MLDSA_Q = 8380417, + parameter GAMMA1 = 2**19, + // parameter MLDSA_GAMMA2 = (MLDSA_Q-1)/32, + parameter BETA = 120, + parameter GAMMA1_MINUS_BETA = GAMMA1 - BETA, + parameter GAMMA2_MINUS_BETA = MLDSA_GAMMA2 - BETA + ) + ( + input wire enable, + input chk_norm_mode_t mode, + input wire [REG_SIZE-2:0] opa_i, + output logic invalid + ); + + logic [REG_SIZE-2:0] bound; + logic [REG_SIZE-2:0] q_minus_bound; + + always_comb begin + case(mode) + z_bound: bound = GAMMA1_MINUS_BETA; + r0_bound: bound = GAMMA2_MINUS_BETA; + ct0_bound: bound = MLDSA_GAMMA2; + default: bound = 'h0; + endcase + + q_minus_bound = MLDSA_Q - bound; + end + + always_comb invalid = enable & (opa_i >= bound) & (opa_i <= q_minus_bound); +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..e0e2f467c7039ec0ed441c3758e14bce2902588d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_ctrl.sv @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// norm_check_ctrl.sv +// -------- +// Manages memory accesses for check norm module. Two reads are done +// to perform 8 coeff checks per cycle. First port reads 0, 2, 4, etc, while second +// port reads 1, 3, 5, etc +// Assumes that one enable triggers check for all polynomials of chosen vector and +// assumes all polynomials of the vector are stored in continuous addr space in memory + +module norm_check_ctrl + import mldsa_params_pkg::*; + import norm_check_defines_pkg::*; + #( + parameter MLDSA_N = 256, + parameter MLDSA_L = 7, + parameter MLDSA_K = 8 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire norm_check_enable, + input chk_norm_mode_t mode, + + input wire [5:0] randomness, + + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] mem_base_addr, + output mem_if_t mem_rd_req, + output logic check_enable, + output logic norm_check_done + ); + + + chk_read_state_e read_fsm_state_ps, read_fsm_state_ns; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr, locked_based_addr; + + //Flags + logic incr_rd_addr; + logic last_poly_last_addr; + logic norm_check_busy; + + logic [4:0] latched_out_randomness; + logic latched_in_randomness; + logic [4:0] increment_addr; + logic [6:0] neutral_cnt; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + latched_out_randomness <= 'h0; + latched_in_randomness <= 'h0; + increment_addr <= 'h0; + mem_rd_addr <= 'h0; + neutral_cnt <= 'h0; + locked_based_addr <= 'h0; + end + else if (zeroize) begin + latched_out_randomness <= 'h0; + latched_in_randomness <= 'h0; + increment_addr <= 'h0; + mem_rd_addr <= 'h0; + neutral_cnt <= 'h0; + locked_based_addr <= 'h0; + end + else begin + if (norm_check_enable) begin + latched_out_randomness <= randomness[5:1]; + latched_in_randomness <= randomness[0]; + increment_addr <= randomness[5:1]; + mem_rd_addr <= {{(MLDSA_MEM_ADDR_WIDTH-6){1'b0}}, randomness}; + neutral_cnt <= 'h0; + locked_based_addr <= mem_base_addr; + end + else if (incr_rd_addr) begin + latched_in_randomness <= latched_in_randomness; + latched_out_randomness <= latched_out_randomness; + increment_addr <= increment_addr; + mem_rd_addr <= {mem_rd_addr[MLDSA_MEM_ADDR_WIDTH-1:6], increment_addr, latched_in_randomness}; + neutral_cnt <= neutral_cnt + 'h1; + end + else if (~incr_rd_addr) begin + latched_in_randomness <= randomness[0]; + latched_out_randomness <= latched_out_randomness; + increment_addr <= increment_addr + 'h1; + mem_rd_addr <= {mem_rd_addr[MLDSA_MEM_ADDR_WIDTH-1:1], ~latched_in_randomness}; + neutral_cnt <= neutral_cnt + 'h1; + end + end + end + + //Addr assignment + always_comb begin + mem_rd_req.addr = mem_rd_addr+locked_based_addr; + + mem_rd_req.rd_wr_en = ((read_fsm_state_ps == CHK_RD_MEM) | (read_fsm_state_ps == CHK_WAIT)) ? RW_READ : RW_IDLE; + end + + //Last addr flag + always_comb last_poly_last_addr = (neutral_cnt == ((MLDSA_N/4))-1); + + //Ctrl flags + always_comb begin + norm_check_busy = (read_fsm_state_ps != CHK_IDLE); + end + + //FSM + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= CHK_IDLE; + else if (zeroize) + read_fsm_state_ps <= CHK_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; + end + + always_comb begin + read_fsm_state_ns = read_fsm_state_ps; + incr_rd_addr = 'b0; + norm_check_done = 0; + + case(read_fsm_state_ps) + CHK_IDLE: begin + read_fsm_state_ns = norm_check_enable ? CHK_RD_MEM : CHK_IDLE; + end + CHK_RD_MEM: begin + read_fsm_state_ns = last_poly_last_addr ? CHK_DONE : CHK_WAIT; + incr_rd_addr = 'b0; + end + CHK_WAIT: begin + read_fsm_state_ns = last_poly_last_addr ? CHK_DONE : CHK_RD_MEM; + incr_rd_addr = 'b1; + end + CHK_DONE: begin + read_fsm_state_ns = CHK_IDLE; + norm_check_done = 'b1; + end + default begin + read_fsm_state_ns = CHK_IDLE; + end + endcase + end + + always_comb check_enable = (read_fsm_state_ps == CHK_RD_MEM) | (read_fsm_state_ps == CHK_WAIT); + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..a43a619def879fb00ecab651b9b728c6d152b917 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_defines_pkg.sv @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// norm_check_defines_pkg.sv +// -------- +// Validity norm check parameters for the digital signature algorithm (DSA). +// +// +//====================================================================== + +`ifndef ABR_NORM_CHECK_DEFINES +`define ABR_NORM_CHECK_DEFINES + +package norm_check_defines_pkg; + + parameter z_bound = 2'h0, r0_bound = 2'h1, ct0_bound = 2'h2; + typedef logic [1:0] chk_norm_mode_t; + + typedef enum logic [1:0] {CHK_IDLE, CHK_RD_MEM, CHK_WAIT, CHK_DONE} chk_read_state_e; +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..a6916a5ffe7f0c3591e919c9af1bb2f55b3913c7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/rtl/norm_check_top.sv @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// norm_check_top.sv +// -------- +// Performs the 3 validity checks (z, r0, ct0) needed for signing algorithm based on mode selection +// Generates one final invalid bit that is accumulated across all polynomials of the chosen vector +// Since this module only has to read from memory, two addresses are read per cycle to increase bandwidth +// and reduce latency, i.e. 8 coeffs are processed per cycle, and 8 check units are instantiated + +// Once the norm_check_done is asserted, the invalid flag needs to be latched at the top level +// for future use in signing algo. Assuming it takes 1 cycle to latch the value, ready is asserted 1 cycle later +// to let HLC know that norm_check operation is done for that vector and next one can be queued +// TODO: see if this needs any changes + +// TODO: embed z and r0 checks in decompose? +// TODO: need a restart input (other than zeroize) + +module norm_check_top + import mldsa_params_pkg::*; + import norm_check_defines_pkg::*; + #( + parameter MLDSA_N = 256 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire norm_check_enable, + input chk_norm_mode_t mode, + + input wire shuffling_enable, + input wire [5:0] randomness, + + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] mem_base_addr, + output mem_if_t mem_rd_req, + input [4*REG_SIZE-1:0] mem_rd_data, + output logic invalid, + output logic norm_check_ready, + output logic norm_check_done + ); + + logic [3:0] check_a_invalid; + logic check_enable, check_enable_reg; + logic norm_check_done_int; + logic latched_shuffling_enable; + logic randomness_enable; + logic [5:0] controller_randomness; + + + assign randomness_enable = latched_shuffling_enable | shuffling_enable; + assign controller_randomness = randomness_enable ? randomness: '0; + + generate + for (genvar i = 0; i < 4; i++) begin + norm_check check_inst ( + .enable(check_enable_reg), + .mode(mode), + .opa_i(mem_rd_data[(REG_SIZE-2)+(i*REG_SIZE):i*REG_SIZE]), + .invalid(check_a_invalid[i]) + ); + end + endgenerate + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + norm_check_done <= 'b0; + else if (zeroize) + norm_check_done <= 'b0; + else + norm_check_done <= norm_check_done_int; + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + invalid <= 'b0; + else if (zeroize | norm_check_done) + invalid <= 'b0; + else + invalid <= invalid | (|check_a_invalid);// | (|check_b_invalid); + end + + //Delay flops + //Give one cycle for HLC to capture invalid flag + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + norm_check_ready <= 'b0; + check_enable_reg <= 'b0; + latched_shuffling_enable <= 'b0; + end + else if (zeroize) begin + norm_check_ready <= 'b0; + check_enable_reg <= 'b0; + latched_shuffling_enable <= 'b0; + end + else begin + norm_check_ready <= norm_check_done; + check_enable_reg <= check_enable; + if (norm_check_enable) + latched_shuffling_enable <= shuffling_enable; + else if (norm_check_done) + latched_shuffling_enable <= 'b0; + end + + end + + norm_check_ctrl + norm_check_ctrl_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .norm_check_enable(norm_check_enable), + .randomness(controller_randomness), + .mode(mode), + .mem_base_addr(mem_base_addr), + .mem_rd_req(mem_rd_req), + .norm_check_done(norm_check_done_int), + .check_enable(check_enable) + ); + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/stimulus/tests/directed/norm_check_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/stimulus/tests/directed/norm_check_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..3085bd9b195ef07e4092d3b8c1b5d1fa81b4b9a2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/stimulus/tests/directed/norm_check_normal_test.yml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +# plusargs: +# - +ECC_TEST_VECTOR_FILE='${CALIPTRA_ROOT}/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex' +# - +ECC_TEST='ECC_normal_test' + +testname: norm_check_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/tb/norm_check_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/tb/norm_check_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..c31892a9a943defc45d69442d5ab3607991da588 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/norm_check/tb/norm_check_tb.sv @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// norm_check_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module norm_check_tb + import mldsa_params_pkg::*; + import norm_check_defines_pkg::*; +#( + parameter NUM_WR = 4, + parameter NUM_RD = 4, + parameter BUFFER_DATA_W = 8 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +parameter MLDSA_Q = 8380417; +parameter MLDSA_ETA = 2; +parameter MLDSA_TAU = 60; +parameter MLDSA_GAMMA1 = 2**19; +parameter MLDSA_GAMMA2 = (MLDSA_Q -1)/32; +parameter MLDSA_BETA = MLDSA_TAU * MLDSA_ETA; + +parameter Z_BOUND = MLDSA_GAMMA1 - MLDSA_BETA; +parameter R0_BOUND = MLDSA_GAMMA2 - MLDSA_BETA; +parameter CT0_BOUND = MLDSA_GAMMA2; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg zeroize_tb; +reg en_tb; +reg shuffling_enable_tb; +reg [5:0] randomness_tb; +reg [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_tb; +wire invalid_tb; +wire norm_check_done_tb; +chk_norm_mode_t mode_tb; + +parameter NUM_OF_COEFF = 256 * 7; // Adjust as per your design +parameter NUM_OF_MEM_WORDS = NUM_OF_COEFF / 4; +reg [3:0][REG_SIZE-1:0] input_mem [0:NUM_OF_MEM_WORDS-1]; + +mem_if_t mem_rd_req_tb; +reg [3:0][REG_SIZE-1:0] mem_rd_data_tb; + +int mem_word_index; + +generate + genvar k; + for (k = 0; k < 4; k = k +1) begin : mem_blocks + normcheck_dual_port_memory #( + .ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH), + .DATA_WIDTH(REG_SIZE), + .DEPTH(NUM_OF_MEM_WORDS) + ) + input_memory ( + .clk(clk_tb), + .addr_a(mem_rd_req_tb.addr), + .data_in_a(24'h0), + .we_a(1'b0), + .data_out_a(mem_rd_data_tb[k]), + .addr_b('0), // Unused + .data_in_b(24'h0), + .we_b(1'b0), + .data_out_b() + ); + end +endgenerate + +norm_check_top dut( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .norm_check_enable(en_tb), + .shuffling_enable(shuffling_enable_tb), + .randomness(randomness_tb), + .mode(mode_tb), + .mem_base_addr(src_base_tb), + .mem_rd_req(mem_rd_req_tb), + .mem_rd_data(mem_rd_data_tb), + .invalid(invalid_tb), + .norm_check_ready(), + .norm_check_done(norm_check_done_tb) +); + +//---------------------------------------------------------------- +// clk_gen +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + zeroize_tb = 0; + en_tb = 0; + src_base_tb = 'h0; + shuffling_enable_tb = '0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + #(2 * CLK_PERIOD); + + $display("End of reset"); + end +endtask // reset_dut + +task overwrite_memory_content(input reg [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr); + int i; + for (i = 0; i < 64; i = i + 1) begin + mem_blocks[0].input_memory.mem[i+src_base_addr] = input_mem[i][0]; + mem_blocks[1].input_memory.mem[i+src_base_addr] = input_mem[i][1]; + mem_blocks[2].input_memory.mem[i+src_base_addr] = input_mem[i][2]; + mem_blocks[3].input_memory.mem[i+src_base_addr] = input_mem[i][3]; + end +endtask + +task z_bound_norm_check_test; + // Z_BOUND Test + $display("Z bound mode\n"); + mode_tb = z_bound; + src_base_tb = 'h0; + + mem_word_index = 0; + for (int i = 0; i < 64; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,Z_BOUND-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-Z_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,Z_BOUND)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,Z_BOUND)); + mem_word_index = mem_word_index + 1; + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (invalid_tb) $error("Expected z check to be valid, received invalid\n"); + else $display("Norm check for z is successful\n"); +endtask + +task r0_bound_norm_check_test; + //R0_BOUND Test + $display("r0 bound mode\n"); + mode_tb = r0_bound; + src_base_tb = 'h40; + + mem_word_index = 0; + for (int i = 0; i < 64; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + mem_word_index = mem_word_index + 1; + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (invalid_tb) $error("Expected r0 check to be valid, received invalid\n"); + else $display("Norm check for r0 is successful\n"); + +endtask + +task ct0_bound_norm_check_test; + // CT0_BOUND Test + $display("ct0 bound mode\n"); + mode_tb = ct0_bound; + src_base_tb = 'h80; + + mem_word_index = '0; + for (int i = 0; i < 64; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + mem_word_index = mem_word_index + 1; + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (invalid_tb) $error("Expected r0 check to be valid, received invalid\n"); + else $display("Norm check for r0 is successful\n"); + +endtask + +task rejected_ct0_bound_norm_check_test; + // Rejected Test + $display("Rejected test for ct0 bound mode\n"); + mode_tb = ct0_bound; + src_base_tb = 'hC0; + + mem_word_index = 0; + for (int poly = 0; poly < 8; poly++) begin + $display("Starting poly %0d", poly); + for (int i = 0; i < 32; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(CT0_BOUND,MLDSA_Q-1)); + mem_word_index = mem_word_index + 1; + end + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + repeat (2) @(posedge clk_tb); + + @(posedge clk_tb); + wait (norm_check_done_tb); + if (invalid_tb) $display("Norm check for ct0 is rejected as expected\n"); + else $error("Expected ct0 check to be invalid, received valid\n"); + +endtask + +task rejected_z_bound_norm_check_test; + // Z_BOUND Test + $display("Z bound mode\n"); + mode_tb = z_bound; + src_base_tb = 'h0; + + mem_word_index = 0; + for (int i = 0; i < 64; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,Z_BOUND-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-Z_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,Z_BOUND)); + if (i==63) begin + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(Z_BOUND,MLDSA_Q-Z_BOUND)); + end + else begin + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,Z_BOUND)); + end + mem_word_index = mem_word_index + 1; + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (invalid_tb) $display("Norm check for z is rejected as expected\n"); + else $error("Expected z check to be invalid, received valid\n"); +endtask + +task rejected_r0_bound_norm_check_test; + //R0_BOUND Test + $display("r0 bound mode\n"); + mode_tb = r0_bound; + src_base_tb = 'h40; + + mem_word_index = 0; + for (int i = 0; i < 64; i++) begin + if (i==0) + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0, MLDSA_Q-R0_BOUND-1)); + else + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + mem_word_index = mem_word_index + 1; + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (invalid_tb) $display("Norm check for r0 is rejected as expected\n"); + else $error("Expected r0 check to be invalid, received valid\n"); + +endtask + +task randomized_rejected_r0_bound_norm_check_test; + //R0_BOUND Test + int inner_index; + mode_tb = r0_bound; + src_base_tb = $urandom_range(0, 127); + repeat (3) @(posedge clk_tb); + + mem_word_index = 0; + for (int i = 0; i < 64; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1)); + mem_word_index = mem_word_index + 1; + end + mem_word_index = $urandom_range(0, 63); + inner_index = $urandom_range(0, 3); + input_mem[mem_word_index][inner_index] = REG_SIZE'($urandom_range(R0_BOUND, MLDSA_Q-R0_BOUND-1)); + + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (!invalid_tb) begin + $display("The incorrect range (%x) is inserted in %d and %d\n",input_mem[mem_word_index][inner_index], mem_word_index, inner_index ); + $error("Expected r0 check to be invalid, received valid at %t\n", $time); + end + +endtask + +task randomized_ct0_bound_norm_check_test; + // CT0_BOUND Test + mode_tb = ct0_bound; + src_base_tb = $urandom_range(0, 127); + repeat (3) @(posedge clk_tb); + + mem_word_index = '0; + for (int i = 0; i < 64; i++) begin + input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,CT0_BOUND-1)); + mem_word_index = mem_word_index + 1; + end + overwrite_memory_content(src_base_tb); + @(negedge clk_tb); + en_tb = 1'b1; + @(posedge clk_tb); + @(negedge clk_tb); + en_tb = 1'b0; + repeat (2) @(posedge clk_tb); + + wait (norm_check_done_tb); + if (invalid_tb) $error("Expected r0 check to be valid, received invalid\n"); + +endtask + +task norm_check_test; + $display("Starting check norm ctrl test\n"); + z_bound_norm_check_test(); + repeat (2) @(posedge clk_tb); + r0_bound_norm_check_test(); + repeat (2) @(posedge clk_tb); + ct0_bound_norm_check_test(); + repeat (2) @(posedge clk_tb); + rejected_ct0_bound_norm_check_test(); + repeat (2) @(posedge clk_tb); + rejected_z_bound_norm_check_test(); + repeat (2) @(posedge clk_tb); + rejected_r0_bound_norm_check_test(); + repeat (10000) randomized_rejected_r0_bound_norm_check_test(); + repeat (10000) randomized_ct0_bound_norm_check_test(); + $display("Ctrl test done\n"); +endtask + +initial begin + fork + begin + init_sim(); + reset_dut(); + shuffling_enable_tb = '0; + norm_check_test(); + shuffling_enable_tb = '1; + norm_check_test(); + end + begin + while(1) begin + @(posedge clk_tb); + randomness_tb = $urandom_range(0,64); + end + end + join_any + $finish; +end + +endmodule + +// Memory module definition (normcheck_dual_port_memory) +module normcheck_dual_port_memory +#( + parameter ADDR_WIDTH = 15, + parameter DATA_WIDTH = 32, + parameter DEPTH = 256 +) +( + input wire clk, + + // Port A + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] data_in_a, + input wire we_a, // Write enable for port A + output reg [DATA_WIDTH-1:0] data_out_a, + + // Port B (Unused in this testbench) + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] data_in_b, + input wire we_b, // Write enable for port B + output reg [DATA_WIDTH-1:0] data_out_b +); + + // Memory array + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + // Port A logic + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= data_in_a; + end + data_out_a <= mem[addr_a]; + end + + // Port B logic (Unused) + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= data_in_b; + end + data_out_b <= mem[addr_b]; + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/custom_data_types.py b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/custom_data_types.py new file mode 100644 index 0000000000000000000000000000000000000000..085d75bf07743f6b6fb6729f5e7a9899bbc42d88 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/custom_data_types.py @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import random + +class CustomUnsignedInteger: + def __init__(self, value, min_value=0, max_value=255): + if not isinstance(value, int): + raise TypeError("Value must be an integer.") + if not (min_value <= value <= max_value): + raise ValueError(f"Value must be within the range {min_value}-{max_value}.") + self.value = value + self.min_value = min_value + self.max_value = max_value + + def __str__(self): + return str(self.value) + + def __repr__(self): + return f"CustomUnsignedInteger({self.value}, {self.min_value}, {self.max_value})" + + def __add__(self, other): + if isinstance(other, CustomUnsignedInteger): + result = self.value + other.value + return CustomUnsignedInteger(result % (self.max_value + 1), self.min_value, self.max_value) + elif isinstance(other, int): + result = self.value + other + return CustomUnsignedInteger(result % (self.max_value + 1), self.min_value, self.max_value) + else: + raise TypeError("Unsupported operand type for +.") + + def __sub__(self, other): + if isinstance(other, CustomUnsignedInteger): + result = self.value - other.value + return CustomUnsignedInteger((result + (self.max_value + 1)) % (self.max_value + 1), self.min_value, self.max_value) + elif isinstance(other, int): + result = self.value - other + return CustomUnsignedInteger((result + (self.max_value + 1)) % (self.max_value + 1), self.min_value, self.max_value) + else: + raise TypeError("Unsupported operand type for -.") + + def __mul__(self, other): + if isinstance(other, CustomUnsignedInteger): + result = self.value * other.value + return CustomUnsignedInteger(result % (self.max_value + 1), self.min_value, self.max_value) + elif isinstance(other, int): + result = self.value * other + return CustomUnsignedInteger(result % (self.max_value + 1), self.min_value, self.max_value) + else: + raise TypeError("Unsupported operand type for *.") + + def generate_random(self): + self.value = random.randint(self.min_value, self.max_value) + + def __int__(self): + if self.value is not None: + return self.value + else: + raise TypeError("CustomUnsignedInteger value is None.") + + +import numpy as np + +class BitSplitter: + def __init__(self, number, num_bits): + """ + Initialize the BitSplitter with an integer and the number of bits. + + :param number: The integer number to split into bits. + :param num_bits: The number of bits to consider for the binary representation. + """ + self.number = number + self.num_bits = num_bits + self.bits = self.split_to_bits() + self.Y = self.reverse_bits() + + def split_to_bits(self): + """ + Split the integer into a numpy array of bits according to num_bits. + + :return: A numpy array of bits (0 or 1) from the most significant to the least significant. + """ + bits = [(self.number >> i) & 1 for i in range(self.num_bits-1, -1, -1)] + return np.array(bits, dtype=np.uint8) + + def reverse_bits(self): + """ + Reverse the entire bit array to represent bits from LSB to MSB. + + :return: Reversed numpy array of bits. + """ + return self.bits[::-1] + + def get_slice(self, high, low): + """ + Get a slice of the reversed bit array, from high to low (inclusive). + + :param high: High index of the slice (inclusive). + :param low: Low index of the slice (inclusive). + :return: A numpy array representing the slice from high to low bits of the reversed array Y. + """ + # Check for index bounds and logic + if high < low or high >= self.num_bits or low < 0: + raise ValueError("Invalid high or low indices for bit slice.") + # Fetch directly from Y + return self.Y[low:high + 1][::-1] + + + @staticmethod + def bits_to_int(bits_array): + """ + Convert a numpy array of bits back into an integer, independently of the array's length. + + :param bits_array: A numpy array of bits to be converted. + :return: Integer value of the binary number represented by the bits array. + """ + return int(''.join(bits_array.astype(str)), 2) + + + @staticmethod + def leftpadding(bits_array, numOfZeros): + padded_array = np.pad(bits_array, (numOfZeros, 0), 'constant', constant_values=(0, 0)) + return padded_array + + @staticmethod + def rightpadding(bits_array, numOfZeros): + padded_array = np.pad(bits_array, (0, numOfZeros), 'constant', constant_values=(0, 0)) + return padded_array + + + + def __repr__(self): + return f"Number: {self.number} (Binary: {''.join(map(str, self.bits))})" + + + +def get_slice(bits_array, high, low): + Y = bits_array[::-1] + shape = Y.shape + size = shape[0] + # Check for index bounds and logic + if high < low or high >= size or low < 0: + raise ValueError("Invalid high or low indices for bit slice.") + # Fetch directly from Y + return Y[low:high + 1][::-1] + + + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/masked_gadgets.py b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/masked_gadgets.py new file mode 100644 index 0000000000000000000000000000000000000000..d737495230862a71f4b5a34a599606eb6283fcdc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/masked_gadgets.py @@ -0,0 +1,921 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +from masking_params import * +from custom_data_types import * + +def one_share_mult(a0, a1, b): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + #get a random number ranging [0, MultMod-1] + randomness.generate_random() + r1 = int(randomness.value) #optional + #refresh the shares + a00 = int(a0+r1) % MultMod + a10 = int(a1-r1) % MultMod + c0 = int(a00*b) % MultMod + c1 = int(a10*b) % MultMod + return c0, c1 + +def two_share_mult(a0, a1, b0, b1): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + #get a random number ranging [0, MultMod-1] + randomness.generate_random() + r1 = int(randomness.value) + # #refresh the shares + # a00 = int(a0+r1) % MultMod + # a10 = int(a1-r1) % MultMod + # c0 = int(a00*b) % MultMod + # c1 = int(a10*b) % MultMod + c0 = int(a0*b0) % MultMod + d0 = int(a1*b0) % MultMod + c1 = int(a0*b1) % MultMod + d1 = int(a1*b1) % MultMod + e0 = int(c1+r1) % MultMod + e1 = int(d0-r1) % MultMod + final_res0 = int(c0+e0) % MultMod + final_res1 = int(d1+e1) % MultMod + return final_res0, final_res1 + +def maskedAdder(a0, a1, b0, b1): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + #get a random number ranging [0, MultMod-1] + randomness.generate_random() + r0 = int(randomness.value) + randomness.generate_random() + r1 = int(randomness.value) + #refresh the shares + a00 = int(a0+r0) % MultMod + a10 = int(a1-r0) % MultMod + # Each operand should have a different randomness + b00 = int(b0+r1) % MultMod + b10 = int(b1-r1) % MultMod + # Perform Addition + c0 = int(a00+b00) % MultMod + c1 = int(a10+b10) % MultMod + return c0, c1 + + +def maskedGS_BFU_noReduction(u0, u1, v0, v1, twiddle): + # Calculate the negative v (-v) = DILITHIUM_Q - v + v00 = (DILITHIUM_Q-v0) % MultMod + v10 = (DILITHIUM_Q-v1) % MultMod + + up0, up1 = maskedAdder(u0, u1, v0, v1) + down0, down1 = maskedAdder(u0, u1, v00, v10) + down00, down10 = one_share_mult(down0, down1, twiddle) + # + # BE CAREFUL: + # The result are still in mod(Q) not in mod(q) + # Assume that we implemented a reduction circuit for it + # First, we merge and then reduce to q and split again + # However, the actual implementation will have a circuit + # to perform a masked reduction routine + down = int(down00+down10) % MultMod + down = down % DILITHIUM_Q + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + randomness.generate_random() + r0 = int(randomness.value) + down01 = int(down-r0) % MultMod + down11 = r0 + return up0, up1, down01, down11 + + +def AND_DOM(x0, x1, y0, y1): + randomness = CustomUnsignedInteger(0, 0, 1) + randomness.generate_random() + r1 = int(randomness.value) + x0y0_clk1 = x0 & y0 + x0y1_clk1 = x0 & y1 + x1y0_clk1 = x1 & y0 + x1y1_clk1 = x1 & y1 + x0y0_clk2 = x0y0_clk1 + x0y1_clk2 = x0y1_clk1 ^ r1 + x1y0_clk2 = x1y0_clk1 ^ r1 + x1y1_clk2 = x1y1_clk1 + x0_clk3 = x0y0_clk2 ^ x0y1_clk2 + x1_clk3 = x1y0_clk2 ^ x1y1_clk2 + + return x0_clk3, x1_clk3 + +def maskedFullAdder(x0, x1, y0, y1, c0, c1): + randomness = CustomUnsignedInteger(0, 0, 1) + #================================== + # Refresh the shares + randomness.generate_random() + r1 = int(randomness.value) + y0 = y0 ^ r1 + y1 = y1 ^ r1 + randomness.generate_random() + r1 = int(randomness.value) + x0 = x0 ^ r1 + x1 = x1 ^ r1 + #================================== + a0 = x0 ^ y0 + a1 = x1 ^ y1 + sumBit0 = c0 ^ a0 + sumBit1 = c1 ^ a1 + and0, and1 = AND_DOM(a0, a1, (x0 ^ c0), (x1 ^ c1)) + carryBit0 = and0 ^ x0 + carryBit1 = and1 ^ x1 + return carryBit0, carryBit1, sumBit0, sumBit1 + +def A2BConv(Arith0, Arith1): + randomness = CustomUnsignedInteger(0, 0, 1) + # Split an integer into its bits + splitter = BitSplitter(Arith0, numOfBits) + x0Bits = splitter.bits + splitter = BitSplitter(Arith1, numOfBits) + x1Bits = splitter.bits + X0 = np.zeros(numOfBits, dtype=np.uint8) + X1 = np.zeros(numOfBits, dtype=np.uint8) + # Initialize the carry bits with zero + c0 = c1 = 0 + for i in range (numOfBits-1,-1,-1): + randomness.generate_random() + r0 = int(randomness.value) + randomness.generate_random() + r1 = int(randomness.value) + x0=x0Bits[i] ^ r0 + x1=r0 + y0=x1Bits[i] ^ r1 + y1=r1 + c0, c1, X0[i], X1[i] = maskedFullAdder(x0, x1, y0, y1, c0, c1) + + Boolean0 = splitter.bits_to_int(X0) + Boolean1 = splitter.bits_to_int(X1) + + return Boolean0, Boolean1 + + +def maskedN_bitAdder(x0, x1, y0, y1, num_of_bits): + splitter = BitSplitter(x0, num_of_bits) + x0Bits = splitter.bits + splitter = BitSplitter(x1, num_of_bits) + x1Bits = splitter.bits + splitter = BitSplitter(y0, num_of_bits) + y0Bits = splitter.bits + splitter = BitSplitter(y1, num_of_bits) + y1Bits = splitter.bits + c0 = c1 = 0 + # Initialize the array for the result (sum) + sum_result0 = np.zeros(num_of_bits+1, dtype=np.uint8) + sum_result1 = np.zeros(num_of_bits+1, dtype=np.uint8) + # Perform bit-wise addition using full adder from LSB to MSB + for i in range(num_of_bits - 1, -1, -1): + c0, c1, sum_result0[i+1], sum_result1[i+1] = maskedFullAdder(x0Bits[i], x1Bits[i], y0Bits[i], y1Bits[i], c0, c1) + + sum_result0[0] = c0 + sum_result1[0] = c1 + + Boolean0 = splitter.bits_to_int(sum_result0) + Boolean1 = splitter.bits_to_int(sum_result1) + + return Boolean0, Boolean1 + + +def maskedN_bitBooleanAdder(x0, x1, y0, y1, num_of_bits): + c0 = c1 = 0 + # Initialize the array for the result (sum) + sum_result0 = np.zeros(num_of_bits+1, dtype=np.uint8) + sum_result1 = np.zeros(num_of_bits+1, dtype=np.uint8) + # Perform bit-wise addition using full adder from LSB to MSB + for i in range(num_of_bits - 1, -1, -1): + c0, c1, sum_result0[i+1], sum_result1[i+1] = maskedFullAdder(x0[i], x1[i], y0[i], y1[i], c0, c1) #sum result is num_bits+1 + + sum_result0[0] = c0 + sum_result1[0] = c1 + + return sum_result0, sum_result1 + + # sum {0, 1,1, 1} 7+1 = {1, 0, 0, 0 } + # sum[4] + # sum[0] + +def maskedN_bitBooleanAdder_for_normal_ops(x0, x1, y0, y1, num_of_bits, sub): + if sub: + c0 = 1 + c1 = 0 + y0 = np.bitwise_not(y0) & 1 # Ensure bits are in {0,1} + y1 = y1.copy() # y1 remains the same + else: + c0 = c1 = 0 + # Initialize the array for the result (sum) + sum_result0 = np.zeros(num_of_bits+1, dtype=np.uint8) + sum_result1 = np.zeros(num_of_bits+1, dtype=np.uint8) + # Perform bit-wise addition using full adder from LSB to MSB + for i in range(num_of_bits - 1, -1, -1): + c0, c1, sum_result0[i+1], sum_result1[i+1] = maskedFullAdder(x0[i], x1[i], y0[i], y1[i], c0, c1) + + sum_result0[0] = c0 + sum_result1[0] = c1 + + return sum_result0, sum_result1 + +def unMaskedModAddition(x0, x1, y0, y1): + x = x0 ^ x1 + y = y0 ^ y1 + z = (x+y) % DILITHIUM_Q + randomness = CustomUnsignedInteger(0, 0, (2**23)-1) + # Refresh the shares -- not optional + randomness.generate_random() + r1 = int(randomness.value) + z0 = z ^ r1 + z1 = r1 + return z0, z1 + +def unMaskedModSub(x0, x1, y0, y1): + x = x0 ^ x1 + y = y0 ^ y1 + z = (x-y) % DILITHIUM_Q + randomness = CustomUnsignedInteger(0, 0, (2**23)-1) + # Refresh the shares + randomness.generate_random() + r1 = int(randomness.value) + z0 = z ^ r1 + z1 = r1 + return z0, z1 + + +def masked_modular_add_sub_with_MUX(x0, x1, y0, y1, k=23, sub=0, debug=0): + if debug == 1: + print("Starting masked_modular_add_sub_with_MUX") + print(f"x0: {x0}, x1: {x1}, y0: {y0}, y1: {y1}, k: {k}, sub: {sub}") + + splitter0 = BitSplitter(x0, k) + x0Bits = splitter0.bits + splitter1 = BitSplitter(x1, k) + x1Bits = splitter1.bits + + splitter2 = BitSplitter(y0, k) + y0Bits = splitter2.bits + splitter3 = BitSplitter(y1, k) + y1Bits = splitter3.bits + + splitter4 = BitSplitter(DILITHIUM_Q, k) + Q0Bits = splitter4.bits + splitter5 = BitSplitter(0, k) + Q1Bits = splitter5.bits + + if debug == 1: + print("\nBit splitting done:") + print(f"x0Bits: {x0Bits}") + print(f"x1Bits: {x1Bits}") + print(f"y0Bits: {y0Bits}") + print(f"y1Bits: {y1Bits}") + print(f"Q0Bits: {Q0Bits}") + print(f"Q1Bits: {Q1Bits}") + + rc0_0, rc0_1 = maskedN_bitBooleanAdder_for_normal_ops(x0Bits, x1Bits, y0Bits, y1Bits, num_of_bits = k, sub=sub) + r0_0 = get_slice(rc0_0, high=k-1, low=0) + r0_1 = get_slice(rc0_1, high=k-1, low=0) + c0_0 = get_slice(rc0_0, high=k, low=k) + c0_1 = get_slice(rc0_1, high=k, low=k) + + if debug == 1: + print("\nAfter first addition/subtraction:") + print(f"rc0_0: {rc0_0}") + print(f"rc0_1: {rc0_1}") + print(f"r0_0: {r0_0}") + print(f"r0_1: {r0_1}") + print(f"c0_0: {c0_0}") + print(f"c0_1: {c0_1}") + + rc1_0, rc1_1 = maskedN_bitBooleanAdder_for_normal_ops(r0_0, r0_1, Q0Bits, Q1Bits, num_of_bits = k, sub=(not sub)) + r1_0 = get_slice(rc1_0, high=k-1, low=0) + r1_1 = get_slice(rc1_1, high=k-1, low=0) + c1_0 = get_slice(rc1_0, high=k, low=k) + c1_1 = get_slice(rc1_1, high=k, low=k) + + if debug == 1: + print("\nAfter second addition/subtraction:") + print(f"rc1_0: {rc1_0}") + print(f"rc1_1: {rc1_1}") + print(f"r1_0: {r1_0}") + print(f"r1_1: {r1_1}") + print(f"c1_0: {c1_0}") + print(f"c1_1: {c1_1}") + + if sub: + s0 = np.pad(c0_0, (k-1, 0), 'constant', constant_values=(c0_0[0], 0)) + s1 = np.pad(c0_1, (k-1, 0), 'constant', constant_values=(c0_1[0], 0)) + if debug == 1: + print("\nSubtraction selected:") + print(f"c0_0: {c0_0}") + print(f"c0_1: {c0_1}") + print(f"s0: {s0}") + print(f"s1: {s1}") + else: + c0c1_0 = np.bitwise_xor(c0_0, c1_0) + c0c1_1 = np.bitwise_xor(c0_1, c1_1) + inv_c0c1_0 = np.bitwise_not(c0c1_0) & 1 + inv_c0c1_1 = c0c1_1.copy() + s0 = np.pad(inv_c0c1_0, (k-1, 0), 'constant', constant_values=(inv_c0c1_0[0], 0)) + s1 = np.pad(inv_c0c1_1, (k-1, 0), 'constant', constant_values=(inv_c0c1_1[0], 0)) + if debug == 1: + print("\nAddition selected:") + print(f"c0c1_0: {c0c1_0}") + print(f"c0c1_1: {c0c1_1}") + print(f"inv_c0c1_0: {inv_c0c1_0}") + print(f"inv_c0c1_1: {inv_c0c1_1}") + print(f"s0: {s0}") + print(f"s1: {s1}") + + x0y0 = np.bitwise_xor(r0_0, r1_0) + x1y1 = np.bitwise_xor(r0_1, r1_1) + #Stages before the following steps should be registered with FFs + randomness0 = CustomUnsignedInteger(0, 0, (k**2)-1) + randomness0.generate_random() + k_bit_randomness = int(randomness0.value) + splitter0 = BitSplitter(k_bit_randomness, k) + k_bit_randomness = splitter0.bits + x0y0k = np.bitwise_xor(x0y0, k_bit_randomness) + x1y1k = np.bitwise_xor(x1y1, k_bit_randomness) + #Stages before the following steps should be registered with FFs + if debug == 1: + print("\nAfter XOR with randomness:") + print(f"x0y0: {x0y0}") + print(f"x1y1: {x1y1}") + print(f"k_bit_randomness: {k_bit_randomness}") + print(f"x0y0k: {x0y0k}") + print(f"x1y1k: {x1y1k}") + + xy_and_s0 = np.zeros_like(s0, dtype=np.uint8) + xy_and_s1 = np.zeros_like(s0, dtype=np.uint8) + for i in range(k): + xy_and_s0[i], xy_and_s1[i] = AND_DOM(s0[i], s1[i], x0y0k[i], x1y1k[i]) + + if debug == 1: + print("\nAfter AND_DOM:") + print(f"xy_and_s0: {xy_and_s0}") + print(f"xy_and_s1: {xy_and_s1}") + + + k_bit_randomness = int(randomness0.value) + splitter0 = BitSplitter(k_bit_randomness, k) + k_bit_randomness = splitter0.bits + r1_0k = np.bitwise_xor(r1_0, k_bit_randomness) + r1_1k = np.bitwise_xor(r1_1, k_bit_randomness) + #Stages before the following steps should be registered with FFs + result0_bits = np.bitwise_xor(xy_and_s0, r1_0k) + result1_bits = np.bitwise_xor(xy_and_s1, r1_1k) + result0 = splitter0.bits_to_int(result0_bits) + result1 = splitter1.bits_to_int(result1_bits) + # result0 = splitter0.bits_to_int(r1_0) + # result1 = splitter1.bits_to_int(r1_1) + + if debug == 1: + print("\nFinal result:") + print(f"result0_bits: {result0_bits}") + print(f"result1_bits: {result1_bits}") + print(f"result0: {result0}") + print(f"result1: {result1}") + + return result0, result1 + +def masked_modular_add_with_conc(d0, d1, z0, z1, k=23, debug=0): + sub = 0 + if debug == 1: + print("Starting masked_modular_add_sub_with_MUX") + print(f"x0: {d0}, x1: {d1}, y0: {z0}, y1: {z1}, k: {k}, sub: {sub}") + + splitter0 = BitSplitter(d0, 11) + x0Bits = splitter0.bits + splitter1 = BitSplitter(d1, 11) + x1Bits = splitter1.bits + + splitter2 = BitSplitter(z0, 13) + y0Bits = splitter2.bits + splitter3 = BitSplitter(z1, 13) + y1Bits = splitter3.bits + + splitter4 = BitSplitter(DILITHIUM_Q, k) + Q0Bits = splitter4.bits + splitter5 = BitSplitter(0, k) + Q1Bits = splitter5.bits + + if debug == 1: + print("\nBit splitting done:") + print(f"x0Bits: {x0Bits}") + print(f"x1Bits: {x1Bits}") + print(f"y0Bits: {y0Bits}") + print(f"y1Bits: {y1Bits}") + print(f"Q0Bits: {Q0Bits}") + print(f"Q1Bits: {Q1Bits}") + + # rc0_0, rc0_1 = maskedN_bitBooleanAdder_for_normal_ops(x0Bits, x1Bits, y0Bits, y1Bits, num_of_bits = k, sub=sub) + # r0_0 = get_slice(rc0_0, high=k-1, low=0) + # r0_1 = get_slice(rc0_1, high=k-1, low=0) + # c0_0 = get_slice(rc0_0, high=k, low=k) + # c0_1 = get_slice(rc0_1, high=k, low=k) + r0_0 = np.zeros_like(Q0Bits, dtype=np.uint8) + r0_1 = np.zeros_like(Q0Bits, dtype=np.uint8) + c0_0 = get_slice(x0Bits, high=10, low=10) + c0_1 = get_slice(x1Bits, high=10, low=10) + + for i in range(10): + # Assign values directly since they are likely scalars + r0_0[i] = x0Bits[i+1] + r0_1[i] = x1Bits[i+1] + + for i in range(13): + # Assign values directly since they are likely scalars + r0_0[i+10] = y0Bits[i] + r0_1[i+10] = y1Bits[i] + + + if debug == 1: + print("\nAfter first addition/subtraction:") + # print(f"rc0_0: {rc0_0}") + # print(f"rc0_1: {rc0_1}") + print(f"r0_0: {r0_0}") + print(f"r0_1: {r0_1}") + print(f"c0_0: {c0_0}") + print(f"c0_1: {c0_1}") + + rc1_0, rc1_1 = maskedN_bitBooleanAdder_for_normal_ops(r0_0, r0_1, Q0Bits, Q1Bits, num_of_bits = k, sub=(not sub)) + r1_0 = get_slice(rc1_0, high=k-1, low=0) + r1_1 = get_slice(rc1_1, high=k-1, low=0) + c1_0 = get_slice(rc1_0, high=k, low=k) + c1_1 = get_slice(rc1_1, high=k, low=k) + + if debug == 1: + print("\nAfter second addition/subtraction:") + print(f"rc1_0: {rc1_0}") + print(f"rc1_1: {rc1_1}") + print(f"r1_0: {r1_0}") + print(f"r1_1: {r1_1}") + print(f"c1_0: {c1_0}") + print(f"c1_1: {c1_1}") + + if sub: + s0 = np.pad(c0_0, (k-1, 0), 'constant', constant_values=(c0_0[0], 0)) + s1 = np.pad(c0_1, (k-1, 0), 'constant', constant_values=(c0_1[0], 0)) + if debug == 1: + print("\nSubtraction selected:") + print(f"c0_0: {c0_0}") + print(f"c0_1: {c0_1}") + print(f"s0: {s0}") + print(f"s1: {s1}") + else: + c0c1_0 = np.bitwise_xor(c0_0, c1_0) + c0c1_1 = np.bitwise_xor(c0_1, c1_1) + inv_c0c1_0 = np.bitwise_not(c0c1_0) & 1 + inv_c0c1_1 = c0c1_1.copy() + s0 = np.pad(inv_c0c1_0, (k-1, 0), 'constant', constant_values=(inv_c0c1_0[0], 0)) + s1 = np.pad(inv_c0c1_1, (k-1, 0), 'constant', constant_values=(inv_c0c1_1[0], 0)) + if debug == 1: + print("\nAddition selected:") + print(f"c0c1_0: {c0c1_0}") + print(f"c0c1_1: {c0c1_1}") + print(f"inv_c0c1_0: {inv_c0c1_0}") + print(f"inv_c0c1_1: {inv_c0c1_1}") + print(f"s0: {s0}") + print(f"s1: {s1}") + + x0y0 = np.bitwise_xor(r0_0, r1_0) + x1y1 = np.bitwise_xor(r0_1, r1_1) + #Stages before the following steps should be registered with FFs + randomness0 = CustomUnsignedInteger(0, 0, (k**2)-1) + randomness0.generate_random() + k_bit_randomness = int(randomness0.value) + splitter0 = BitSplitter(k_bit_randomness, k) + k_bit_randomness = splitter0.bits + x0y0k = np.bitwise_xor(x0y0, k_bit_randomness) + x1y1k = np.bitwise_xor(x1y1, k_bit_randomness) + #Stages before the following steps should be registered with FFs + if debug == 1: + print("\nAfter XOR with randomness:") + print(f"x0y0: {x0y0}") + print(f"x1y1: {x1y1}") + print(f"k_bit_randomness: {k_bit_randomness}") + print(f"x0y0k: {x0y0k}") + print(f"x1y1k: {x1y1k}") + + xy_and_s0 = np.zeros_like(s0, dtype=np.uint8) + xy_and_s1 = np.zeros_like(s0, dtype=np.uint8) + for i in range(k): + xy_and_s0[i], xy_and_s1[i] = AND_DOM(s0[i], s1[i], x0y0k[i], x1y1k[i]) + + if debug == 1: + print("\nAfter AND_DOM:") + print(f"xy_and_s0: {xy_and_s0}") + print(f"xy_and_s1: {xy_and_s1}") + + + k_bit_randomness = int(randomness0.value) + splitter0 = BitSplitter(k_bit_randomness, k) + k_bit_randomness = splitter0.bits + r1_0k = np.bitwise_xor(r1_0, k_bit_randomness) + r1_1k = np.bitwise_xor(r1_1, k_bit_randomness) + #Stages before the following steps should be registered with FFs + result0_bits = np.bitwise_xor(xy_and_s0, r1_0k) + result1_bits = np.bitwise_xor(xy_and_s1, r1_1k) + result0 = splitter0.bits_to_int(result0_bits) + result1 = splitter1.bits_to_int(result1_bits) + # result0 = splitter0.bits_to_int(r1_0) + # result1 = splitter1.bits_to_int(r1_1) + + if debug == 1: + print("\nFinal result:") + print(f"result0_bits: {result0_bits}") + print(f"result1_bits: {result1_bits}") + print(f"result0: {result0}") + print(f"result1: {result1}") + + return result0, result1 + + +def maskedReduction46(x0, x1): + splitter0 = BitSplitter(x0, numOfBits) + x0Bits = splitter0.bits + splitter1 = BitSplitter(x1, numOfBits) + x1Bits = splitter1.bits + z0_45_23 = splitter0.get_slice(high=45, low=23) + z1_45_23 = splitter1.get_slice(high=45, low=23) + z0_45_33 = splitter0.get_slice(high=45, low=33) + z1_45_33 = splitter1.get_slice(high=45, low=33) + z0_45_43 = splitter0.get_slice(high=45, low=43) + z1_45_43 = splitter1.get_slice(high=45, low=43) + z0_12_0 = splitter0.get_slice(high=12, low=0) + z1_12_0 = splitter1.get_slice(high=12, low=0) + z0_22_13 = splitter0.get_slice(high=22, low=13) + z1_22_13 = splitter1.get_slice(high=22, low=13) + z0_32_23 = splitter0.get_slice(high=32, low=23) + z1_32_23 = splitter1.get_slice(high=32, low=23) + z0_42_33 = splitter0.get_slice(high=42, low=33) + z1_42_33 = splitter1.get_slice(high=42, low=33) + + tmp0, tmp1 = maskedN_bitBooleanAdder(z0_22_13, z1_22_13, z0_32_23, z1_32_23, 10) + tmp00, tmp10 = maskedN_bitBooleanAdder(splitter0.leftpadding(z0_45_43, 7), + splitter1.leftpadding(z1_45_43, 7), + z0_42_33, z1_42_33, 10) + c0_11_0, c1_11_0 = maskedN_bitBooleanAdder(tmp0, tmp1, tmp00, tmp10, 11) + c0_11_10 = get_slice(c0_11_0, high=11, low=10) + c1_11_10 = get_slice(c1_11_0, high=11, low=10) + c0_9_0 = get_slice(c0_11_0, high=9, low=0) + c1_9_0 = get_slice(c1_11_0, high=9, low=0) + d0_10_0, d1_10_0 = maskedN_bitBooleanAdder(splitter0.leftpadding(c0_11_10, 8), + splitter1.leftpadding(c1_11_10, 8), + c0_9_0, c1_9_0, 10) + d0_23_0 = splitter0.rightpadding(d0_10_0, 13) + d1_23_0 = splitter1.rightpadding(d1_10_0, 13) + + d0 = splitter0.bits_to_int(d0_23_0) + d1 = splitter1.bits_to_int(d1_23_0) + z0_12 = splitter0.bits_to_int(z0_12_0) + z1_12 = splitter1.bits_to_int(z1_12_0) + d0_22_debug, d1_22_debug = unMaskedModAddition(d0, d1, z0_12, z1_12) + int_d0_10_0 = splitter0.bits_to_int(d0_10_0) + int_d0_10_1 = splitter1.bits_to_int(d1_10_0) + d0_22, d1_22 = masked_modular_add_with_conc(int_d0_10_0, int_d0_10_1, z0_12, z1_12, k=ModulArithBits, debug =0) + if ((d0_22_debug ^d1_22_debug)!= (d0_22^d1_22)): + print(f"Error in add model({d0 ^ d1},{z0_12 ^ z1_12}) exp={(d0_22^d1_22)} and actual={(d0_22_debug ^d1_22_debug)}") + actual_add0, actual_add1 = masked_modular_add_with_conc(d0_10_0, d1_10_0, z0_12, z1_12, k=ModulArithBits, debug =1) + # elif (d0 ^d1)>=DILITHIUM_Q: + # print(f"d ({d0 ^ d1}) is bigger than q") + # print(f"Error in add model({d0 ^ d1},{z0_12 ^ z1_12}) exp={(d0_22^d1_22)} and actual={(d0_22_debug ^d1_22_debug)}") + + + tmp0, tmp1 = maskedN_bitBooleanAdder(splitter0.leftpadding(c0_11_10, 1), + splitter1.leftpadding(c1_11_10, 1), + z0_45_43, z1_45_43, 3) + f0_13_0, f1_13_0 = maskedN_bitBooleanAdder(splitter0.leftpadding(tmp0, 9), + splitter1.leftpadding(tmp1, 9), + z0_45_33, z1_45_33, 13) + + + + f0 = splitter0.bits_to_int(f0_13_0) + f1 = splitter1.bits_to_int(f1_13_0) + z0_45 = splitter0.bits_to_int(z0_45_23) + z1_45 = splitter1.bits_to_int(z1_45_23) + e0_22_debug, e1_22debug = unMaskedModAddition(f0, f1, z0_45, z1_45) + e0_22, e1_22 = masked_modular_add_sub_with_MUX(f0, f1, z0_45, z1_45, k=ModulArithBits, sub=0, debug =0) + if (e0_22_debug ^e1_22debug)!= (e0_22^e1_22) and ((f0 ^ f1)=DILITHIUM_Q: + print(f"f ({f0 ^ f1}) is bigger than q") + elif (z0_45 ^ z1_45)>=DILITHIUM_Q: + print(f"z ({(z0_45 ^ z1_45)}) is bigger than q") + # ab0, ab1 = unMaskedModSub(d0_22, d1_22, e0_22, e1_22) + ab0, ab1 = masked_modular_add_sub_with_MUX(d0_22, d1_22, e0_22, e1_22, k=ModulArithBits, sub=1, debug =0) + + return ab0, ab1 + + + + +def B2A(x0, x1): + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + randomness.generate_random() + r0 = int(randomness.value) + x0 = x0 ^ r0 + x1 = x1 ^ r0 + randomness.generate_random() + Gamma = int(randomness.value) + T0 = x0 ^ Gamma + T1 = int(T0 - Gamma) % MultMod + T2 = T1 ^ x0 + Gamma0 = (Gamma ^ x1) + A0 = x0 ^ Gamma0 + A1 = int(A0 - Gamma0) % MultMod + a0 = A1 ^ T2 + a1 = x1 + return a0, a1 + +# Roller does the following: +# if a >= 2**23 - 2**13 + 1: +# if a + 2**13 - 1 >= 2**23 + +# 1000 >> 3 --> 1 + +# input: u0 = 0, u1 = 1 +# output: red0 = 1010 red1 = 0111 --> combine = 'd17 % 16 = 1 +# +def maskedAdderReduction(u0, u1): + uRolled0 = (u0 + Roller) % MultMod + uRolled1 = u1 + print(f"rolled_shares = {uRolled0: X}, {uRolled1: X}") + print(f"rolled_combin = {uRolled0+uRolled1: X}") + # We need its only int(1+numOfBits/2)-bit so the adder size + # can be reduced from 46 to 24 + # 2**23 is 1 in 24th bit + uBoolean0, uBoolean1 = A2BConv(uRolled0, uRolled1) + print(f"boolean_shares = {uBoolean0: X}, {uBoolean1: X}") + print(f"boolean_combin = {uBoolean0^uBoolean1: X}") + c0 = (uBoolean0 >> int(numOfBits/2)) & 1 + c1 = (uBoolean1 >> int(numOfBits/2)) & 1 + red0, red1 = B2A(c0, c1) #converts to 46-bit arith domain not just 1 bit! (pad inputs on MSB part with 0s if needed) + print(f"arith_shares = {red0: X}, {red1: X}") + print(f"arith_combin = {red0+red1: X}") + q0 = red0 * ((0-DILITHIUM_Q)% MultMod) + q1 = red1 * ((0-DILITHIUM_Q)% MultMod) + print(f"prime_shares = {q0: X}, {q1: X}") + print(f"prime_combin = {q0+q1: X}") + uReduced0 = (u0+q0) % MultMod + uReduced1 = (u1+q1) % MultMod + print(f"res_redux_shares = {uReduced0: X}, {uReduced1: X}") + print(f"res_redux_combin = {uReduced0+uReduced1: X}") + return uReduced0, uReduced1 + +def maskedBFUAdder(x0, x1, y0, y1): + u0, u1 = maskedAdder(x0, x1, y0, y1) + print(f"add_res_shares = {u0: X}, {u1: X}") + print(f"add_res_combin = {u0+u1: X}") + uReduced0, uReduced1 = maskedAdderReduction(u0, u1) + return uReduced0, uReduced1 + + +def maskedBFUSub(x0, x1, y0, y1): + y_new0 = (DILITHIUM_Q-y0) % MultMod + y_new1 = (0-y1) % MultMod + print(f"y_new_shares = {y_new0: X}, {y_new1: X}") + print(f"y_new_combin = {y_new0+y_new1: X}") + v0, v1 = maskedAdder(x0, x1, y_new0, y_new1) + vReduced0, vReduced1 = maskedAdderReduction(v0, v1) + return vReduced0, vReduced1 + +def maskedBFUMult(x0, x1, omega): + v0, v1 = one_share_mult(x0, x1, omega) + vBoolean0, vBoolean1 = A2BConv(v0, v1) + v23Boolean0, v23Boolean1 = maskedReduction46(vBoolean0, vBoolean1) + vArith0, vArith1 = B2A(v23Boolean0, v23Boolean1) + return vArith0, vArith1 + + +def maskedBFU_GS(u0, u1, v0, v1, omega): + t0, t1 = maskedBFUSub(u0, u1, v0, v1) + u0, u1 = maskedBFUAdder(u0, u1, v0, v1) + v0, v1 = maskedBFUMult(t0, t1, omega) + return u0, u1, v0, v1 + +def maskedBFU_CT(u0, u1, v0, v1, omega): + t0, t1 = maskedBFUMult(v0, v1, omega) + v0, v1 = maskedBFUSub(u0, u1, t0, t1) + u0, u1 = maskedBFUAdder(u0, u1, t0, t1) + return u0, u1, v0, v1 + +def maskedBFU_GS_div2(u0, u1, v0, v1, omega): + t0, t1 = maskedBFUSub(u0, u1, v0, v1) + t0, t1 = nonMaksed_div2(t0, t1) + u0, u1 = maskedBFUAdder(u0, u1, v0, v1) + u0, u1 = nonMaksed_div2(u0, u1) + v0, v1 = maskedBFUMult(t0, t1, omega) + return u0, u1, v0, v1 + +def nonMaksed_div2(x0, x1): + x= (x0+x1) % MultMod + if x & 1: + x = (x >> 1) + ((DILITHIUM_Q + 1) // 2) + else: + x = x >> 1 + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + randomness.generate_random() + r1 = int(randomness.value) + x0 = int(x-r1) % MultMod + x1 = r1 + return x0, x1 + +def masked_inv_NTT2x2_div2(poly_r): + zetas, zetas_inv = zeta_generator() + + r = copy.deepcopy(poly_r) + + k1={} + zeta1={} + + for l in range(0, DILITHIUM_LOGN - (DILITHIUM_LOGN & 1), 2): + m = 1 << l + for i in range(0, DILITHIUM_N, 1 << (l + 2)): + k1[0] = ((DILITHIUM_N - (i >> 1)) >> l) - 1 + k1[1] = k1[0] - 1 + k2 = ((DILITHIUM_N - (i >> 1)) >> (l + 1)) - 1 + zeta1[0] = zetas_inv[k1[0]] + zeta1[1] = zetas_inv[k1[1]] + zeta2 = zetas_inv[k2] + + for j in range(i, i + m): + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + u00 = r[j] + v00 = r[j + m] + u01 = r[j + 2 * m] + v01 = r[j + 3 * m] + + randomness.generate_random() + r1 = int(randomness.value) + u00_0 = int(u00-r1) % MultMod + u00_1 = r1 + randomness.generate_random() + r1 = int(randomness.value) + v00_0 = int(v00-r1) % MultMod + v00_1 = r1 + + randomness.generate_random() + r1 = int(randomness.value) + u01_0 = int(u01-r1) % MultMod + u01_1 = r1 + randomness.generate_random() + r1 = int(randomness.value) + v01_0 = int(v01-r1) % MultMod + v01_1 = r1 + u10_0, u10_1, u11_0, u11_1 = maskedBFU_GS_div2(u00_0, u00_1, v00_0, v00_1, zeta1[0]) + v10_0, v10_1, v11_0, v11_1 = maskedBFU_GS_div2(u01_0, u01_1, v01_0, v01_1, zeta1[1]) + + u20_0, u20_1, u21_0, u21_1 = maskedBFU_GS_div2(u10_0, u10_1, v10_0, v10_1, zeta2) + v20_0, v20_1, v21_0, v21_1 = maskedBFU_GS_div2(u11_0, u11_1, v11_0, v11_1, zeta2) + + r[j] = (u20_0 + u20_1) % MultMod + r[j + m] = (v20_0 + v20_1) % MultMod + r[j + 2 * m] = (u21_0 + u21_1) % MultMod + r[j + 3 * m] = (v21_0 + v21_1) % MultMod + + return r + +import copy + +def inv_NTT2x2_div2(poly_r): + zetas, zetas_inv = zeta_generator() + + r = copy.deepcopy(poly_r) + + k1={} + zeta1={} + + for l in range(0, DILITHIUM_LOGN - (DILITHIUM_LOGN & 1), 2): + m = 1 << l + for i in range(0, DILITHIUM_N, 1 << (l + 2)): + k1[0] = ((DILITHIUM_N - (i >> 1)) >> l) - 1 + k1[1] = k1[0] - 1 + k2 = ((DILITHIUM_N - (i >> 1)) >> (l + 1)) - 1 + zeta1[0] = zetas_inv[k1[0]] + zeta1[1] = zetas_inv[k1[1]] + zeta2 = zetas_inv[k2] + + for j in range(i, i + m): + u00 = r[j] + v00 = r[j + m] + u01 = r[j + 2 * m] + v01 = r[j + 3 * m] + + u10, u11 = gs_bf_div2(u00, v00, zeta1[0]) + v10, v11 = gs_bf_div2(u01, v01, zeta1[1]) + + u20, u21 = gs_bf_div2(u10, v10, zeta2) + v20, v21 = gs_bf_div2(u11, v11, zeta2) + + r[j] = u20 + r[j + m] = v20 + r[j + 2 * m] = u21 + r[j + 3 * m] = v21 + + return r + +def bit_reversal(x): + binary_string = format(x, '08b') + reversed_binary_string = binary_string[::-1] + reversed_decimal = int(reversed_binary_string, 2) + return reversed_decimal + +def zeta_generator(): + + tree=np.zeros(DILITHIUM_N) + for i in range (DILITHIUM_N): + tree[i] = bit_reversal(i) + + tmp={} + tmp[0] = 1 + + zetas={} + zetas_inv={} + + for i in range (1, DILITHIUM_N, 1): + tmp[i] = (tmp[i-1] * DILITHIUM_ROOT_OF_UNITY) % DILITHIUM_Q + + for i in range (0, DILITHIUM_N, 1): + zetas[i] = tmp[tree[i]] + zetas[i] = zetas[i] + zetas_inv[i] = -zetas[i] % DILITHIUM_Q + + return zetas, zetas_inv + +def gs_bf_div2(u, v, z): + t = div2((u - v) % DILITHIUM_Q) + u = div2((u + v) % DILITHIUM_Q) + v = (t * z) % DILITHIUM_Q + return u, v + +def div2(x): + if x & 1: + return (x >> 1) + ((DILITHIUM_Q + 1) // 2) + else: + return x >> 1 + +def fwd_NTT(poly_r): + + r = copy.deepcopy(poly_r) + zetas, zetas_inv = zeta_generator() + + k = 0 + m = 128 + while (m > 0): + start = 0 + while (start < DILITHIUM_N): + k += 1 + zeta = zetas[k] + for j in range(start, start+m): + r[j], r[j + m] = ct_bf(r[j], r[j + m], zeta) + start = start + 2 * m + m >>= 1 + + return r + +def ct_bf(u, v, z): + t = (v * z) % DILITHIUM_Q + v = (u - t) % DILITHIUM_Q + u = (u + t) % DILITHIUM_Q + return u, v + +def modular_add_with_MUX(a, b, debug =0): + rc0 = (a+b) + r0 = rc0 & ((2**ModulArithBits)-1) + c0 = rc0 >> ModulArithBits + rc1 = (r0 - DILITHIUM_Q) + r1 = rc1 & ((2**ModulArithBits)-1) + c1 = rc1 >> ModulArithBits + c0c1 = (c1 ^ c0) &1 + if debug: + print(f"r0={r0}, r1={r1} and c0={c0}, c1={c1} and c0^c1= {c0c1}") + if c0c1 == 1: + return r0 + else: + return r1 + +def modular_sub_with_MUX(a, b, debug =0): + rc0 = int(a-b) + r0 = rc0 & ((2**ModulArithBits)-1) + c0 = rc0 >> ModulArithBits + rc1 = r0 + DILITHIUM_Q + r1 = rc1 & ((2**ModulArithBits)-1) + if debug: + print(f"r0={r0}, r1={r1} and c0={c0}") + c0 = c0 &1 + if c0 == 1: + return r1 + else: + return r0 + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/masking_params.py b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/masking_params.py new file mode 100644 index 0000000000000000000000000000000000000000..876b5403b6b1f93cf59963b768eb4bdf31007321 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/masking_params.py @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +numOfBits = 46 +MultMod = 2**numOfBits +DILITHIUM_Q = 8380417 +BooleanMod = 2**int(numOfBits/2) +Roller = (2**13)-1 +DILITHIUM_N = 256 +DILITHIUM_LOGN = 8 +DILITHIUM_ROOT_OF_UNITY = 1753 +ModulArithBits = int(numOfBits/2) + +# numOfBits = 8 +# MultMod = 2**numOfBits +# DILITHIUM_Q = 7 +# BooleanMod = 2**int(numOfBits/2) + +# numOfBits = 10 +# MultMod = 2**numOfBits +# DILITHIUM_Q = 23 +# BooleanMod = 2**int(numOfBits/2) +# Roller = (2**3)+1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/testForMasking.py b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/testForMasking.py new file mode 100644 index 0000000000000000000000000000000000000000..e59f432f7646b8edcc114ee64860b03c96887633 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/Model/testForMasking.py @@ -0,0 +1,488 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +from masked_gadgets import * + + +def test_one_share_mult(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + a = int(operands.value) + operands.generate_random() + b = int(operands.value) + expected = a*b + randomness.generate_random() + r1 = int(randomness.value) + a0 = int(a-r1) % MultMod + a1 = r1 + c0,c1 = one_share_mult(a0, a1, b) + gotten = int(c0+c1) % MultMod + if gotten != expected: + print(f"Multiplication gives an Error; gotten = {gotten}, while exp = {expected}") + + +# test_one_share_mult(numTest=10000) + + +def test_maskedAdder(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + a = int(operands.value) + operands.generate_random() + b = int(operands.value) + expected = a+b + randomness.generate_random() + r0 = int(randomness.value) + a0 = int(a-r0) % MultMod + a1 = r0 + randomness.generate_random() + r1 = int(randomness.value) + b0 = int(b-r1) % MultMod + b1 = r1 + c0,c1 = maskedAdder(a0, a1, b0, b1) + gotten = int(c0+c1) % MultMod + if gotten != expected: + print(f"Adder gives an Error; gotten = {gotten}, while exp = {expected}") + +# test_maskedAdder(numTest=100000) + + +def test_maskedSubtractor(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + a = int(operands.value) + operands.generate_random() + b = (int(operands.value)) + # + # BE CAREFUL: + # The result are still in mod(Q) not in mod(q) + # + expected = (a-b) % DILITHIUM_Q + randomness.generate_random() + r0 = int(randomness.value) + a0 = int(a-r0) % MultMod + a1 = r0 + + b_new = (DILITHIUM_Q-b) % MultMod + randomness.generate_random() + r1 = int(randomness.value) + b0 = int(b_new-r1) % MultMod + b1 = r1 + c0,c1 = maskedAdder(a0, a1, b0, b1) + gotten = int(c0+c1) % MultMod + gotten = gotten % DILITHIUM_Q + if gotten != expected: + print(f"Subtractor gives an Error; gotten = {gotten}, while exp = {expected}") + +# test_maskedSubtractor(numTest=1000) + + +def test_maskedGS_BFU_noReduction(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + twiddles = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + u = int(operands.value) + operands.generate_random() + v = (int(operands.value)) + twiddles.generate_random() + omega = int(twiddles.value) + # + # BE CAREFUL: + # The result are still in mod(Q) not in mod(q) + # + t = (u - v) % DILITHIUM_Q + u_exp = (u + v) % DILITHIUM_Q + v_exp = (t * omega) % DILITHIUM_Q + + randomness.generate_random() + r0 = int(randomness.value) + u0 = int(u-r0) % MultMod + u1 = r0 + + randomness.generate_random() + r1 = int(randomness.value) + v0 = int(v-r1) % MultMod + v1 = r1 + + u00, u10, v00, v10 = maskedGS_BFU_noReduction(u0, u1, v0, v1, omega) + u_gotten = int(u00+u10) % MultMod + # This one is for upper bridge + if u_gotten>= DILITHIUM_Q: + u_gotten = u_gotten-DILITHIUM_Q + v_gotten = int(v00+v10) % MultMod + if u_gotten != u_exp: + print(f"Upper branch of gives an Error; gotten = {u_gotten}, while exp = {u_exp}") + if v_gotten != v_exp: + print(f"Upper branch of gives an Error; gotten = {v_gotten}, while exp = {v_exp}") + +# test_maskedGS_BFU_noReduction(numTest=1000000) + + +def test_maskedFullAdder(numTest = 10): + # Construct randomness class + operands = CustomUnsignedInteger(0, 0, 1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + x = int(operands.value) + operands.generate_random() + y = int(operands.value) + operands.generate_random() + c = int(operands.value) + operands.generate_random() + r0 = int(operands.value) + operands.generate_random() + r1 = int(operands.value) + operands.generate_random() + r2 = int(operands.value) + x0 = x ^ r0 + y0 = y ^ r1 + c0 = c ^ r2 + x1 = r0 + y1 = r1 + c1 = r2 + + c0,c1, s0,s1 = maskedFullAdder(x0, x1, y0, y1, c0, c1) + carry = (c0 ^ c1) << 1 + sum = (s0 ^ s1) + gotten = carry + sum + if gotten != (x+y+c): + print(f"Multiplication gives an Error; gotten = {gotten}, while exp = {(x+y+c)}") + +# test_maskedFullAdder(numTest=1000000) + + + +def test_A2BConv(numTest = 10): + # Construct randomness class + operands = CustomUnsignedInteger(0, 0, MultMod-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + a = int(operands.value) + operands.generate_random() + r0 = int(operands.value) + a0 = (a-r0) % MultMod + a1 = r0 + c0,c1 = A2BConv(a0, a1) + gotten = c0 ^ c1 + if gotten != a: + print(f"A2B gives an Error; gotten = {gotten}, while exp = {a}") + +# test_A2BConv(numTest=1000) + +def test_maskedN_bitAdder(numTest = 10): + # Construct randomness class + operands = CustomUnsignedInteger(0, 0, MultMod-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + x = int(operands.value) + operands.generate_random() + y = int(operands.value) + operands.generate_random() + r0 = int(operands.value) + operands.generate_random() + r1 = int(operands.value) + x0 = x ^ r0 + y0 = y ^ r1 + x1 = r0 + y1 = r1 + + s0,s1 = maskedN_bitAdder(x0, x1, y0, y1, numOfBits) + gotten = (s0 ^ s1) + if gotten != (x+y): + print(f"Multiplication gives an Error; gotten = {gotten}, while exp = {(x+y)}") + +# test_maskedN_bitAdder(numTest=100000) + + + + + +# test_ModularReductionMult(numTest = 1000000) + +def test_maskedReduction46(numTest = 10): + # Construct randomness class + operands = CustomUnsignedInteger(0, 0, (2**23)-1) + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + x = int(operands.value) + # x = 2638949 + operands.generate_random() + y = int(operands.value) + # y = 3599593 + excepted = int(x*y) % DILITHIUM_Q + z = x*y + randomness.generate_random() + r0 = int(randomness.value) + z0 = z ^ r0 + z1 = r0 + ab0, ab1 = maskedReduction46(z0, z1) + gotten = ab0 ^ ab1 + if gotten != excepted: + print(f"Multiplication gives an Error; gotten = {gotten}, while exp = {excepted}") + + +# test_maskedReduction46(numTest = 1000000) + + +def test_B2A(numTest = 10): + # Construct randomness class + operands = CustomUnsignedInteger(0, 0, BooleanMod-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + x = int(operands.value) + operands.generate_random() + r = int(operands.value) + x0 = x ^ r + x1 = r + excepted = x + a0, a1 = B2A(x0, x1) + gotten = int(a0 + a1) % MultMod + if gotten != excepted: + print(f"Multiplication gives an Error; gotten = {gotten}, while exp = {excepted}") + +# test_B2A(numTest = 1000000) + +def test_maskedBFUAdder(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + a = int(operands.value) + operands.generate_random() + b = int(operands.value) + expected = (a+b) % DILITHIUM_Q + randomness.generate_random() + r0 = int(randomness.value) + a0 = int(a-r0) % MultMod + a1 = r0 + randomness.generate_random() + r1 = int(randomness.value) + b0 = int(b-r1) % MultMod + b1 = r1 + + a0, a1 = maskedBFUAdder(a0, a1, b0, b1) + gotten = int(a0 + a1) % MultMod + # print(f"Gotten = {gotten: X}, Expected = {expected: X}") + if gotten != expected: + print(f"Addition gives an Error; gotten = {gotten: X}, while exp = {expected: X}") + +#test_maskedBFUAdder(numTest = 1000) + +def gs_bf(u, v, z): + t = (u - v) % DILITHIUM_Q + u = (u + v) % DILITHIUM_Q + v = (t * z) % DILITHIUM_Q + return u, v + + +def ct_bf(u, v, z): + t = (v * z) % DILITHIUM_Q + v = (u - t) % DILITHIUM_Q + u = (u + t) % DILITHIUM_Q + return u, v + + +def test_maskedBFU_GS(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + u = int(operands.value) + operands.generate_random() + v = int(operands.value) + operands.generate_random() + omega = int(operands.value) + exp_u, exp_v = gs_bf(u, v, omega) + randomness.generate_random() + r0 = int(randomness.value) + u0 = int(u-r0) % MultMod + u1 = r0 + randomness.generate_random() + r1 = int(randomness.value) + v0 = int(v-r1) % MultMod + v1 = r1 + uNew0, uNew1, vNew0, vNew1 = maskedBFU_GS(u0, u1, v0, v1, omega) + uNew = int(uNew0 + uNew1) % MultMod + vNew = int(vNew0 + vNew1) % MultMod + if uNew != exp_u: + print(f"GS Upper branch gives an Error; gotten = {uNew}, while exp = {exp_u}") + if vNew != exp_v: + print(f"GS Lower branch gives an Error; gotten = {vNew}, while exp = {exp_v}") + + + + +def test_maskedBFU_CT(numTest = 10): + # Construct randomness class + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + operands.generate_random() + u = int(operands.value) + operands.generate_random() + v = int(operands.value) + operands.generate_random() + omega = int(operands.value) + exp_u, exp_v = ct_bf(u, v, omega) + randomness.generate_random() + r0 = int(randomness.value) + u0 = int(u-r0) % MultMod + u1 = r0 + randomness.generate_random() + r1 = int(randomness.value) + v0 = int(v-r1) % MultMod + v1 = r1 + uNew0, uNew1, vNew0, vNew1 = maskedBFU_CT(u0, u1, v0, v1, omega) + uNew = int(uNew0 + uNew1) % MultMod + vNew = int(vNew0 + vNew1) % MultMod + if uNew != exp_u: + print(f"CT Upper branch gives an Error; gotten = {uNew}, while exp = {exp_u}") + if vNew != exp_v: + print(f"CT Lower branch gives an Error; gotten = {vNew}, while exp = {exp_v}") + +def test_twoshare_mult(numTest = 10): + randomness = CustomUnsignedInteger(0, 0, MultMod-1) + operands = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(0, numTest): + #get a random number ranging [0, DILITHIUM_Q-1] + #generate inputs + operands.generate_random() + u = int(operands.value) + operands.generate_random() + v = int(operands.value) + #calculate expected result + exp_uv = u*v + #Split inputs to shares + randomness.generate_random() + r0 = int(randomness.value) + u0 = int(u-r0) % MultMod + u1 = r0 + randomness.generate_random() + r1 = int(randomness.value) + v0 = int(v-r1) % MultMod + v1 = r1 + #Test two share mult + uv0, uv1 = two_share_mult(u0, u1, v0, v1) + uv = int(uv0 + uv1) % MultMod + #Check result + if uv != exp_uv: + print(f"Incorrect mult op. Operands: {u, v}, Shares: {u0, u1, v0, v1} Exp = {exp_uv}, actual = {uv}") + + + + +test_maskedBFU_CT(numTest = 100000) +test_maskedBFU_GS(numTest = 100000) +test_twoshare_mult(numTest = 100000) + +def test_masked_inv_NTT2x2_div2(numTest = 10): + for test_i in range(numTest): + r_init = {} + for i in range (DILITHIUM_N): + r_init[i] = random.randrange(DILITHIUM_Q) # + + #using ref model + r_in_ntt = fwd_NTT(r_init) + + #using 2x2 div2 architecture + r_from_ntt2x2_div2 = inv_NTT2x2_div2(r_in_ntt) + r_from_ntt2x2_div2_masked = masked_inv_NTT2x2_div2(r_in_ntt) + #check 2x2 div2 architecture + if (r_from_ntt2x2_div2 != r_init): + print("Error in inv_ntt2x2 div2 model") + if (r_from_ntt2x2_div2_masked != r_init): + print("Error in masked inv_ntt2x2 div2 model") + +def test_nonMaskedmodularOps(numTest = 10): + randomness = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + for i in range(numTest): + randomness.generate_random() + a = int(randomness.value) + randomness.generate_random() + b = int(randomness.value) + exp_sub = (a-b) % DILITHIUM_Q + exp_add = (a+b) % DILITHIUM_Q + actual_sub = modular_sub_with_MUX(a, b) + actual_add = modular_add_with_MUX(a, b) + if (exp_sub != actual_sub): + print(f"Error in sub model({a},{b}) exp={exp_sub} and actual={actual_sub}") + actual_sub = modular_sub_with_MUX(a, b, 1) + if (exp_add != actual_add): + print(f"Error in add model({a},{b}) exp={exp_add} and actual={actual_add}") + actual_add = modular_add_with_MUX(a, b, 1) + +# test_masked_inv_NTT2x2_div2(numTest = 100) +# test_nonMaskedmodularOps(numTest = 100000) + +def test_MaskedmodularOps(numTest = 10): + randomness0 = CustomUnsignedInteger(0, 0, DILITHIUM_Q-1) + randomness1 = CustomUnsignedInteger(0, 0, BooleanMod-1) + for i in range(numTest): + randomness0.generate_random() + a = int(randomness0.value) + randomness1.generate_random() + r0 = int(randomness1.value) + a1 = r0 + a0 = a ^ r0 + randomness0.generate_random() + b = int(randomness0.value) + randomness1.generate_random() + r0 = int(randomness1.value) + b1 = r0 + b0 = b ^ r0 + #### TBD ############# + exp_sub = (a-b) % DILITHIUM_Q + exp_add = (a+b) % DILITHIUM_Q + actual_sub0, actual_sub1 = masked_modular_add_sub_with_MUX(a0, a1, b0, b1, k=ModulArithBits, sub=1, debug =0) + actual_add0, actual_add1 = masked_modular_add_sub_with_MUX(a0, a1, b0, b1, k=ModulArithBits, sub=0, debug =0) + if (exp_sub != (actual_sub0 ^ actual_sub1)): + print(f"Error in sub model({a},{b}) exp={exp_sub} and actual={(actual_sub0 ^ actual_sub1)}") + actual_sub0, actual_sub1 = masked_modular_add_sub_with_MUX(a0, a1, b0, b1, k=ModulArithBits, sub=1, debug =1) + if (exp_add != (actual_add0 ^ actual_add1)): + print(f"Error in add model({a},{b}) exp={exp_add} and actual={(actual_add0 ^ actual_add1)}") + actual_add0, actual_add1 = masked_modular_add_sub_with_MUX(a0, a1, b0, b1, k=ModulArithBits, sub=0, debug =1) + + + +# test_MaskedmodularOps(numTest = 100000) +test_maskedReduction46(numTest = 1000000) + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/butterfly_top_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/butterfly_top_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..c0a15a1e5b3df8fb9886d5a76aab510e03fc5068 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/butterfly_top_tb.vf @@ -0,0 +1,55 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/butterfly_top_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..98dc4e7a53c47fb198bfb27c2395a2d0d35ae49d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/compile.yml @@ -0,0 +1,168 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [ntt_pkg] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/ntt_defines_pkg.sv + tb: + directories: + - $COMPILE_ROOT/rtl + files: + - $COMPILE_ROOT/rtl/ntt_defines_pkg.sv +--- +provides: [butterfly_top_tb] +schema_version: 2.4.0 +requires: + - ntt_top + - ntt_pkg +targets: + tb: + directories: + - $COMPILE_ROOT/tb + files: + - $COMPILE_ROOT/tb/butterfly_top_tb.sv + tops: [butterfly_top_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ntt hex to $PWD" && cp $COMPILE_ROOT/tb/zeta.txt . && cp $COMPILE_ROOT/tb/zeta_inv.hex . && cp $COMPILE_ROOT/tb/ntt_stage2.hex . && cp $COMPILE_ROOT/tb/ntt_stage2_out.hex .' +--- +provides: [ntt_top] +schema_version: 2.4.0 +requires: + - ntt_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/ntt_butterfly2x2.sv + - $COMPILE_ROOT/rtl/ntt_butterfly.sv + - $COMPILE_ROOT/rtl/ntt_mult_dsp.sv + - $COMPILE_ROOT/rtl/ntt_mult_reduction.sv + - $COMPILE_ROOT/rtl/ntt_special_adder.sv + - $COMPILE_ROOT/rtl/ntt_masked_special_adder.sv + - $COMPILE_ROOT/rtl/ntt_masked_mult_redux46.sv + - $COMPILE_ROOT/rtl/ntt_div2.sv + - $COMPILE_ROOT/rtl/ntt_buffer.sv + - $COMPILE_ROOT/rtl/ntt_shuffle_buffer.sv + - $COMPILE_ROOT/rtl/ntt_twiddle_lookup.sv + - $COMPILE_ROOT/rtl/ntt_ctrl.sv + - $COMPILE_ROOT/rtl/ntt_top.sv + - $COMPILE_ROOT/rtl/ntt_masked_BFU_add_sub.sv + - $COMPILE_ROOT/rtl/ntt_masked_BFU_mult.sv + - $COMPILE_ROOT/rtl/ntt_masked_gs_butterfly.sv + - $COMPILE_ROOT/rtl/ntt_masked_pwm.sv + - $COMPILE_ROOT/rtl/ntt_masked_butterfly1x2.sv + - $COMPILE_ROOT/rtl/ntt_hybrid_butterfly_2x2.sv + # tb: + # directories: [$COMPILE_ROOT/rtl] + # files: + # - $COMPILE_ROOT/tb/ntt_ram_tdp_file.sv + # - $COMPILE_ROOT/tb/ntt_wrapper.sv + + tops: [ntt_top] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/ntt/config/design_lint/ntt_top/sglint_waivers +--- +provides: [ntt_top_tb] +schema_version: 2.4.0 +requires: + - ntt_top + - ntt_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/ntt_top_tb.sv + - $COMPILE_ROOT/tb/ntt_ram_tdp_file.sv + - $COMPILE_ROOT/tb/ntt_wrapper.sv + tops: [ntt_top_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ntt hex to $PWD" && cp $COMPILE_ROOT/tb/test_vectors/zeta.txt . && cp $COMPILE_ROOT/tb/test_vectors/zeta_inv.hex . && cp $COMPILE_ROOT/tb/test_vectors/ntt_stage0_mem.hex . && cp $COMPILE_ROOT/tb/test_vectors/rand_ntt_stage0_mem.hex . && cp $COMPILE_ROOT/tb/test_vectors/ntt_stage0_out.hex . && cp $COMPILE_ROOT/tb/test_vectors/ntt_stage67.hex . && cp $COMPILE_ROOT/tb/test_vectors/pwm_iter1.hex . && cp $COMPILE_ROOT/tb/test_vectors/pwm_iter2.hex .' + +--- +provides: [ntt_mult_reduction_tb] +schema_version: 2.4.0 +requires: + - ntt_top +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/ntt_mult_reduction_tb.sv + tops: [ntt_mult_reduction_tb] + +--- +provides: [ntt_masked_mult_reduction_tb] +schema_version: 2.4.0 +requires: + - ntt_top +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/ntt_masked_mult_redux46_tb.sv + - $COMPILE_ROOT/tb/ntt_masked_mult_redux46_auto_tb.sv + tops: [ntt_masked_mult_redux46_auto_tb] + +--- +provides: [ntt_top_masking_tb] +schema_version: 2.4.0 +requires: + - ntt_top +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/ntt_top_masking_tb.sv + tops: [ntt_top_masking_tb] + +--- +provides: [ntt_utb] +schema_version: 2.4.0 +requires: + - mldsa_uvm_lib + - ntt_top + - ntt_pkg +targets: + tb: + directories: [$COMPILE_ROOT/utb] + files: + - $COMPILE_ROOT/utb/ntt_utb_top/ntt_utb_defines.sv + - $COMPILE_ROOT/utb/interfaces/ntt_if.sv + - $COMPILE_ROOT/utb/interfaces/mem_if.sv + - $COMPILE_ROOT/utb/mem_agent/mem_txn.sv + - $COMPILE_ROOT/utb/mem_agent/mem_agent_config.sv + - $COMPILE_ROOT/utb/mem_agent/mem_sequencer.sv + - $COMPILE_ROOT/utb/mem_agent/mem_driver.sv + - $COMPILE_ROOT/utb/mem_agent/mem_mon.sv + - $COMPILE_ROOT/utb/mem_agent/mem_agent.sv + - $COMPILE_ROOT/utb/ntt_agent/ntt_txn.sv + - $COMPILE_ROOT/utb/ntt_agent/ntt_sequencer.sv + - $COMPILE_ROOT/utb/ntt_agent/ntt_driver.sv + - $COMPILE_ROOT/utb/ntt_agent/ntt_mon.sv + - $COMPILE_ROOT/utb/ntt_agent/ntt_agent.sv + - $COMPILE_ROOT/utb/scoreboard/ntt_sb.sv + - $COMPILE_ROOT/utb/env/ntt_env.sv + - $COMPILE_ROOT/utb/sequences/ntt_seq/ntt_base_seq.sv + - $COMPILE_ROOT/utb/sequences/ntt_seq/ntt_fwd_seq.sv + - $COMPILE_ROOT/utb/sequences/ntt_seq/ntt_inv_seq.sv + - $COMPILE_ROOT/utb/sequences/ntt_seq_lib.sv + - $COMPILE_ROOT/utb/sequences/mem_seq_lib.sv + - $COMPILE_ROOT/utb/sequences/ntt_virtual_seq.sv + - $COMPILE_ROOT/utb/tests/ntt_base_test.sv + - $COMPILE_ROOT/utb/tests/ntt_combined_test.sv + - $COMPILE_ROOT/utb/ntt_utb_top/ntt_utb_top.sv + - $COMPILE_ROOT/tb/ntt_ram_tdp_file.sv + - $COMPILE_ROOT/tb/ntt_wrapper.sv + tops: [ntt_utb_top] diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/design_lint/ntt_top/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/design_lint/ntt_top/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_masked_mult_reduction_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_masked_mult_reduction_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..9f86117934ae2aca5bad25e3bb86d838b1676faf --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_masked_mult_reduction_tb.vf @@ -0,0 +1,56 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_masked_mult_redux46_tb.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_masked_mult_redux46_auto_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_mult_reduction_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_mult_reduction_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..3a30c57e27963d17cc6c19ab63e20e7856333cea --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_mult_reduction_tb.vf @@ -0,0 +1,55 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_mult_reduction_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..12d50b2a43babd4457fa56086eaedaee3b8fc1f9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_pkg.vf @@ -0,0 +1,35 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top.vf new file mode 100644 index 0000000000000000000000000000000000000000..76c5e3727e187bb6cbdc554a6f918b4a0bb9188d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top.vf @@ -0,0 +1,53 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top_masking_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top_masking_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..aacbbb7cf3ba6e100350aea45fb2a289564f567e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top_masking_tb.vf @@ -0,0 +1,55 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_top_masking_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..e149b99be25ca500d1f006cf220737563aa55bce --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_top_tb.vf @@ -0,0 +1,57 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_top_tb.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_ram_tdp_file.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_wrapper.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_utb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_utb.vf new file mode 100644 index 0000000000000000000000000000000000000000..47b6b5cab444b5f85860c3e24a0c7068811de748 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/config/ntt_utb.vf @@ -0,0 +1,84 @@ ++incdir+${UVM_HOME}/src ++incdir+${UVM_HOME}/src/dpi ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/utb +${UVM_HOME}/src/uvm_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_utb_top/ntt_utb_defines.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/interfaces/ntt_if.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/interfaces/mem_if.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/mem_agent/mem_txn.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/mem_agent/mem_agent_config.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/mem_agent/mem_sequencer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/mem_agent/mem_driver.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/mem_agent/mem_mon.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/mem_agent/mem_agent.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_agent/ntt_txn.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_agent/ntt_sequencer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_agent/ntt_driver.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_agent/ntt_mon.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_agent/ntt_agent.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/scoreboard/ntt_sb.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/env/ntt_env.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/sequences/ntt_seq/ntt_base_seq.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/sequences/ntt_seq/ntt_fwd_seq.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/sequences/ntt_seq/ntt_inv_seq.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/sequences/ntt_seq_lib.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/sequences/mem_seq_lib.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/sequences/ntt_virtual_seq.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/tests/ntt_base_test.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/tests/ntt_combined_test.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/utb/ntt_utb_top/ntt_utb_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_ram_tdp_file.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/tb/ntt_wrapper.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_buffer.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_buffer.sv new file mode 100644 index 0000000000000000000000000000000000000000..922a1d285d025a1c7fc9a573e687ba0e2556718e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_buffer.sv @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_buffer.sv +// -------- +// Set of 4 buffers of widths 4, 5, 6 and 7 slots. These buffers will +// temporarily hold data from NTT memory and collect 4 coefficients for each +// address being read/written to. This buffer will be configured based on bf mode at ntt_top level. +// In NTT mode (ct mode), buffer will contain data read from memory before +// it is consumed by butterfly2x2. In INTT mode (gs mode), buffer will contain +// data to be written to memory (bf2x2 outputs). When all 4 coefficients for a given +// op have arrived, the data is passed to bf2x2 module or written to NTT memory (based on bf mode) +//====================================================================== + +module ntt_buffer + import ntt_defines_pkg::*; +#( + parameter REG_SIZE = 23 + // parameter NUM_COEFF = 4 +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + input wire wren, //enables writes to the buffer + input wire rden, //enables reads to the buffer + input wire wr_rst_count, + input wire rd_rst_count, + input mode_t mode, + input wire [(4*REG_SIZE)-1:0] data_i, + output logic buf0_valid, + output logic [(4*REG_SIZE)-1:0] data_o +); + + logic [3:0][REG_SIZE-1:0] buf0; //holds 4 entries + logic [4:0][REG_SIZE-1:0] buf1; //holds 5 entries + logic [5:0][REG_SIZE-1:0] buf2; //holds 6 entries + logic [6:0][REG_SIZE-1:0] buf3; //holds 7 entries + + logic [1:0] data_i_count, data_i_count_reg; + logic [1:0] data_o_count; + logic wren_reg; + + + //Write/read + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buf0 <= 'h0; + buf1 <= 'h0; + buf2 <= 'h0; + buf3 <= 'h0; + + end + else if (zeroize) begin + buf0 <= 'h0; + buf1 <= 'h0; + buf2 <= 'h0; + buf3 <= 'h0; + + end + else if (wren) begin + buf0 <= {data_i[REG_SIZE-1:0], buf0[3:1]}; + buf1 <= {data_i[(2*REG_SIZE)-1:REG_SIZE], buf1[4:1]}; + buf2 <= {data_i[(3*REG_SIZE)-1:(2*REG_SIZE)], buf2[5:1]}; + buf3 <= {data_i[(4*REG_SIZE)-1:(3*REG_SIZE)], buf3[6:1]}; + end + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + data_o_count <= 'h0; + else if (zeroize) + data_o_count <= 'h0; + else if (rd_rst_count) + data_o_count <= 'h0; + else if (rden) + data_o_count <= data_o_count + 'h1; + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + data_i_count <= 'h0; + data_i_count_reg <= 'h0; + end + else if (zeroize) begin + data_i_count <= 'h0; + data_i_count_reg <= 'h0; + end + else if (wr_rst_count) begin + data_i_count <= 'h0; + data_i_count_reg <= 'h0; + end + else if (wren) begin + data_i_count <= data_i_count + 'h1; + data_i_count_reg <= data_i_count; + end + end + + assign buf0_valid = (data_i_count_reg == 'd3); + + always_comb begin + case(data_o_count) + 'd0: data_o = {buf0[3],buf0[2],buf0[1],buf0[0]}; + 'd1: data_o = {buf1[3],buf1[2],buf1[1],buf1[0]}; + 'd2: data_o = {buf2[3],buf2[2],buf2[1],buf2[0]}; + 'd3: data_o = {buf3[3],buf3[2],buf3[1],buf3[0]}; + endcase + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_butterfly.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_butterfly.sv new file mode 100644 index 0000000000000000000000000000000000000000..53593126cdc34a5b31d4e8e613320da394f0fa2b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_butterfly.sv @@ -0,0 +1,306 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_butterfly.sv +// -------- +// Combined butterfly unit that performs NTT and INTT. All operations +// are modular. This unit operates in 5 modes - NTT, INTT and PWM, PWA, PWS +// Inputs u and v are fetched from s memory, w values come from ROM +// containing required twiddle factors. +// PWM mode performs point-wise multiplication and accumulation +//====================================================================== + +module ntt_butterfly + import ntt_defines_pkg::*; +#( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_Q_DIV2_ODD = (MLDSA_Q + 1) / 2 +) +( + //Clock and reset + input wire clk, + input wire reset_n, + input wire zeroize, + + //Data ports + input mode_t mode, + input wire accumulate, + + input wire [REG_SIZE-1:0] opu_i, + input wire [REG_SIZE-1:0] opv_i, + input wire [REG_SIZE-1:0] opw_i, + + output logic [REG_SIZE-1:0] u_o, + output logic [REG_SIZE-1:0] v_o, + output logic [REG_SIZE-1:0] pwm_res_o +); + + //Input wires + logic [REG_SIZE-1:0] u_reg, u_reg_d2, u_reg_d3, u_reg_d4; + // logic [REG_SIZE-1:0] v_reg, v_reg_d2, v_reg_d3, v_reg_d4; + logic [REG_SIZE-1:0] w_reg, w_reg_d2, w_reg_d3, w_reg_d4; //w_reg_d4 only used in pwm mode + + //Multiplier wires + logic [(2*REG_SIZE)-1:0] vw, vw_reg, mul_res; + logic [REG_SIZE-1:0] mul_res_reduced; + logic [REG_SIZE-1:0] mul_opa, mul_opb; + + //Subtractor wires + logic [REG_SIZE-1:0] u_minus_v, u_minus_v_div2; + + //Adder wires + logic [REG_SIZE-1:0] add_opa, add_opb; + logic [REG_SIZE-1:0] add_res, add_res_d1, add_res_d2, add_res_d3, add_res_d4, sub_res; + logic [REG_SIZE-1:0] add_res_div2, sub_res_div2, mul_res_reduced_div2; + + //Flop u input to match multiplier output (4 cycle delay) + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + u_reg <= 'h0; + u_reg_d2 <= 'h0; + u_reg_d3 <= 'h0; + u_reg_d4 <= 'h0; + + w_reg <= 'h0; + w_reg_d2 <= 'h0; + w_reg_d3 <= 'h0; + w_reg_d4 <= 'h0; + end + else if (zeroize) begin + u_reg <= 'h0; + u_reg_d2 <= 'h0; + u_reg_d3 <= 'h0; + u_reg_d4 <= 'h0; + + w_reg <= 'h0; + w_reg_d2 <= 'h0; + w_reg_d3 <= 'h0; + w_reg_d4 <= 'h0; + end + else begin + u_reg <= opu_i; + u_reg_d2 <= u_reg; + u_reg_d3 <= u_reg_d2; + u_reg_d4 <= u_reg_d3; + + //Used in GS/PWM mode only + w_reg <= opw_i; + w_reg_d2 <= w_reg; + w_reg_d3 <= w_reg_d2; + w_reg_d4 <= w_reg_d3; + end + end + + //4 cycle delay to match critical path + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + add_res_d1 <= 'h0; + add_res_d2 <= 'h0; + add_res_d3 <= 'h0; + add_res_d4 <= 'h0; + end + else if (zeroize) begin + add_res_d1 <= 'h0; + add_res_d2 <= 'h0; + add_res_d3 <= 'h0; + add_res_d4 <= 'h0; + end + else begin + add_res_d1 <= add_res; + add_res_d2 <= add_res_d1; + add_res_d3 <= add_res_d2; + add_res_d4 <= add_res_d3; + end + end + + //Mode mux for outputs + always_comb begin + unique case(mode) + ct: begin + u_o = add_res; + v_o = sub_res; + pwm_res_o = 'h0; + end + gs: begin + u_o = add_res_div2; + v_o = mul_res_reduced; //_div2; + pwm_res_o = 'h0; + end + pwm:begin + u_o = accumulate ? add_res : mul_res_reduced; //TODO: see if pwm_res_o is good enough or reuse u_o to save routing/area + v_o = 'h0; + pwm_res_o = accumulate ? add_res : mul_res_reduced; + end + pwa:begin + u_o = add_res; + v_o = 'h0; + pwm_res_o = add_res; + end + pws:begin + u_o = u_minus_v; + v_o = 'h0; + pwm_res_o = u_minus_v; + end + default: begin + u_o = 'h0; + v_o = 'h0; + pwm_res_o = 'h0; + end + endcase + end + + //Mode mux for inputs + //0 - NTT, 1 - INTT, 2 - PWM + always_comb begin + unique case(mode) + ct: begin + add_opa = u_reg_d4; + add_opb = mul_res_reduced; + mul_opa = opv_i; + mul_opb = opw_i; + end + gs: begin + add_opa = opu_i; + add_opb = opv_i; + mul_opa = u_minus_v_div2; //u_minus_v + mul_opb = w_reg; + end + pwm:begin + add_opa = w_reg_d4; + add_opb = mul_res_reduced; + mul_opa = opu_i; + mul_opb = opv_i; + end + pwa:begin + add_opa = opu_i; + add_opb = opv_i; + mul_opa = 'h0; + mul_opb = 'h0; + end + default: begin + add_opa = 'h0; + add_opb = 'h0; + mul_opa = 'h0; + mul_opb = 'h0; + end + endcase + end + + //Mod sub - used in GS + abr_add_sub_mod #( + .REG_SIZE(REG_SIZE) + ) + sub_inst_0( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .add_en_i(1'b1), + .sub_i(1'b1), + .opa_i(opu_i), + .opb_i(opv_i), + .prime_i(MLDSA_Q), //TODO: convert prime input to param everywhere + .res_o(u_minus_v), + .ready_o() + ); + + //Mod sub - used in CT + abr_add_sub_mod #( + .REG_SIZE(REG_SIZE) + ) + sub_inst_1( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .add_en_i(1'b1), + .sub_i(1'b1), + .opa_i(u_reg_d4), + .opb_i(mul_res_reduced), + .prime_i(MLDSA_Q), + .res_o(sub_res), + .ready_o() + ); + + //Mod add - used in CT and GS + abr_add_sub_mod #( + .REG_SIZE(REG_SIZE) + ) + add_inst_0( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .add_en_i(1'b1), + .sub_i(1'b0), + .opa_i(add_opa), + .opb_i(add_opb), + .prime_i(MLDSA_Q), + .res_o(add_res), + .ready_o() + ); + + //Mod mult - used in CT, GS, PWM + + ntt_mult_dsp #( + .RADIX(REG_SIZE) + ) + mul_inst_0 ( + .A_i(mul_opa), + .B_i(mul_opb), + .P_o(mul_res) + ); + + ntt_mult_reduction #( + .REG_SIZE(REG_SIZE), + .PRIME(MLDSA_Q) + ) + mul_redux_inst_0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .opa_i(mul_res), + .res_o(mul_res_reduced), + .ready_o() + ); + + //Output div2 - used in GS + ntt_div2 #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + div2_inst_0 ( + .op_i (add_res_d4), + .res_o (add_res_div2) + ); + + ntt_div2 #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + div2_inst_2 ( + .op_i (u_minus_v), + .res_o (u_minus_v_div2) + ); + + // div2 #( + // .REG_SIZE(REG_SIZE), + // .MLDSA_Q(MLDSA_Q) + // ) + // div2_inst_2 ( + // .op_i (mul_res_reduced), + // .res_o (mul_res_reduced_div2) + // ); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_butterfly2x2.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_butterfly2x2.sv new file mode 100644 index 0000000000000000000000000000000000000000..7023cf8ce41a48b3e1babbf145db4d1a6a3be1c3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_butterfly2x2.sv @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_butterfly2x2.sv +// -------- +// Network of 4 butterfly units connected in a 2x2 layout. Inputs to these +// are u00, v00, u01, v01, w00, w01 (as an example), coming from a buffer. Outputs of +// the 1st stage are passed onto the second stage (u10, v10, u11, v11, w10, w11). +// The final outputs are buffered and written back to memory at the top level +//====================================================================== + +module ntt_butterfly2x2 + import ntt_defines_pkg::*; +#( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_Q_DIV2_ODD = (MLDSA_Q + 1) / 2 +) +( + //Clock and reset + input wire clk, + input wire reset_n, + input wire zeroize, + + //Data ports + input mode_t mode, + input wire enable, + input bf_uvwi_t uvw_i, + input pwo_uvwi_t pw_uvw_i, + input wire accumulate, + + output bf_uvo_t uv_o, + output pwo_t pwo_uv_o, + output logic ready_o +); + + logic [REG_SIZE-1:0] u00; + logic [REG_SIZE-1:0] u01; + logic [REG_SIZE-1:0] v00; + logic [REG_SIZE-1:0] v01; + + logic [REG_SIZE-1:0] u10_int, u10; + logic [REG_SIZE-1:0] u11_int, u11; + logic [REG_SIZE-1:0] v10_int, v10; + logic [REG_SIZE-1:0] v11_int, v11; + + logic [REG_SIZE-1:0] w00; + logic [REG_SIZE-1:0] w01; + logic [REG_SIZE-1:0] w10; + logic [REG_SIZE-1:0] w11; + logic [UNMASKED_BF_STAGE1_LATENCY-1:0][REG_SIZE-1:0] w10_reg, w11_reg; //Shift w10 by 5 cycles to match 1st stage BF latency + logic pwo_mode; + logic [UNMASKED_BF_LATENCY-1:0] ready_reg; + + //Each butterfly unit takes u, v, w inputs and produces + //u, v outputs for the next stage to consume. Each butterfly + //has a maximum latency of 5 clks + //Each worst-case path (ct or gs) contains a modular multiplication + //and a modular add/sub. Multiplication takes a max of 4 clks + //(Multiplication module has 2 flops + 2 add/sub reductions in a single path). + //Add/sub takes 1 clk to produce results. + //So, worst case latency = 4 + 1 = 5 clks + + //Flop the twiddle factor 5x to correctly pass in values to the 2nd set of bf units + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + w10_reg <= 'h0; + w11_reg <= 'h0; + end + else if (zeroize) begin + w10_reg <= 'h0; + w11_reg <= 'h0; + end + else begin + w10_reg <= {uvw_i.w10_i, w10_reg[UNMASKED_BF_STAGE1_LATENCY-1:1]}; + w11_reg <= {uvw_i.w11_i, w11_reg[UNMASKED_BF_STAGE1_LATENCY-1:1]}; + end + end + + assign pwo_mode = (mode inside {pwm, pwa, pws}); + + always_comb begin + if (pwo_mode) begin + u00 = pw_uvw_i.u0_i; + v00 = pw_uvw_i.v0_i; + w00 = pw_uvw_i.w0_i; + + u01 = pw_uvw_i.u1_i; + v01 = pw_uvw_i.v1_i; + w01 = pw_uvw_i.w1_i; + + u10 = pw_uvw_i.u2_i; + v10 = pw_uvw_i.v2_i; + w10 = pw_uvw_i.w2_i; + + u11 = pw_uvw_i.u3_i; + v11 = pw_uvw_i.v3_i; + w11 = pw_uvw_i.w3_i; + + end + else begin + u00 = uvw_i.u00_i; + v00 = uvw_i.v00_i; + w00 = uvw_i.w00_i; + + u01 = uvw_i.u01_i; + v01 = uvw_i.v01_i; + w01 = uvw_i.w01_i; + + u10 = u10_int; + v10 = v10_int; + w10 = w10_reg[0]; + + u11 = u11_int; + v11 = v11_int; + w11 = w11_reg[0]; + end + end + + ntt_butterfly #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + bf_inst00( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .opu_i(u00), + .opv_i(v00), + .opw_i(w00), + .accumulate(accumulate), + .u_o(u10_int), + .v_o(u11_int), + .pwm_res_o(pwo_uv_o.uv0) + ); + + ntt_butterfly #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + bf_inst01( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .opu_i(u01), + .opv_i(v01), + .opw_i(w01), + .accumulate(accumulate), + .u_o(v10_int), + .v_o(v11_int), + .pwm_res_o(pwo_uv_o.uv1) + ); + + ntt_butterfly #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + bf_inst10( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .opu_i(u10), + .opv_i(v10), + .opw_i(w10), //(uvw_i.w10_i), + .accumulate(accumulate), + .u_o(uv_o.u20_o), + .v_o(uv_o.v20_o), + .pwm_res_o(pwo_uv_o.uv2) + ); + + ntt_butterfly #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + bf_inst11( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .opu_i(u11), + .opv_i(v11), + .opw_i(w11), //(uvw_i.w11_i), + .accumulate(accumulate), + .u_o(uv_o.u21_o), + .v_o(uv_o.v21_o), + .pwm_res_o(pwo_uv_o.uv3) + ); + + //Determine when results are ready + //--------------------------------------------- + //For the first 10 cycles, ntt_butterfly2x2 does not produce any valid output. + //We wait for 10 clks before asserting ready. After that, there's a valid output every clk. + //ntt_top controller will disable bf2x2 and that will reset ready while transitioning + //from one stage to next after all writes of current stage have finished. + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + ready_reg <= 'b0; + else if (zeroize) + ready_reg <= 'b0; + else begin + unique case(mode) + ct: ready_reg <= {enable, ready_reg[UNMASKED_BF_LATENCY-1:1]}; + gs: ready_reg <= {enable, ready_reg[UNMASKED_BF_LATENCY-1:1]}; + pwm: ready_reg <= accumulate ? {5'h0, enable, ready_reg[UNMASKED_PWM_LATENCY-1:1]} : {6'h0, enable, ready_reg[UNMASKED_PWM_LATENCY-2:1]}; + pwa: ready_reg <= {9'h0, enable}; + pws: ready_reg <= {9'h0, enable}; + default: ready_reg <= 'h0; + endcase + end + end + + assign ready_o = ready_reg[0]; + + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..191fec65e858983e251aa53ff4c7c6ee442f3022 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_ctrl.sv @@ -0,0 +1,1018 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_ctrl.sv +// -------- +// This block: +// 1. Keeps track of stages of bf2x2 operation in ct, gs, pwo modes +// 2. Controls wr/rd addr of NTT mem +// 3. Controls rd addr of twiddle ROM +// 4. Performs shuffling of wr/rd addr +// Note: Latency changes in BFU must be reflected in the latency params here and in bf2x2 for correct pipeline operation +//====================================================================== + +module ntt_ctrl + import ntt_defines_pkg::*; +#( + parameter REG_SIZE = 23, + parameter RADIX = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_Q_DIV2_ODD = (MLDSA_Q+1)/2, + parameter MLDSA_N = 256, + parameter MLDSA_LOGN = 8, + parameter MEM_ADDR_WIDTH = 15 +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + input mode_t ntt_mode, + input wire ntt_enable, + input wire butterfly_ready, + input wire buf0_valid, + input wire sampler_valid, + input wire accumulate, + //NTT/INTT base addr + input ntt_mem_addr_t ntt_mem_base_addr, + //PWO base addr + input pwo_mem_addr_t pwo_mem_base_addr, + input wire shuffle_en, + input wire [5:0] random, //4+2 bits + + output logic bf_enable, + output logic [2:0] opcode, + output logic masking_en_ctrl, + output logic buf_wren, + output logic buf_rden, + output logic [1:0] buf_wrptr, + output logic [1:0] buf_rdptr, + output logic [6:0] twiddle_addr, + + output logic [MEM_ADDR_WIDTH-1:0] mem_rd_addr, + output logic [MEM_ADDR_WIDTH-1:0] mem_wr_addr, + output logic mem_rd_en, + output logic mem_wr_en, + output logic buf_wr_rst_count, + output logic buf_rd_rst_count, + + //PWO outputs + output logic [MEM_ADDR_WIDTH-1:0] pw_mem_rd_addr_a, + output logic [MEM_ADDR_WIDTH-1:0] pw_mem_rd_addr_b, + output logic [MEM_ADDR_WIDTH-1:0] pw_mem_rd_addr_c, + output logic [MEM_ADDR_WIDTH-1:0] pw_mem_wr_addr_c, + output logic pw_rden, + output logic pw_wren, + output logic busy, + output logic done +); + +//Parameters +localparam NTT_NUM_ROUNDS = 4; +localparam PWO_NUM_ROUNDS = 1; +localparam NTT_READ_ADDR_STEP = 16; +localparam NTT_WRITE_ADDR_STEP = 1; +localparam INTT_READ_ADDR_STEP = 1; +localparam INTT_WRITE_ADDR_STEP = 16; +localparam PWO_READ_ADDR_STEP = 1; +localparam PWO_WRITE_ADDR_STEP = 1; + +localparam [MEM_ADDR_WIDTH-1:0] MEM_LAST_ADDR = 63; + +//FSM states +ntt_read_state_t read_fsm_state_ps, read_fsm_state_ns; +ntt_write_state_t write_fsm_state_ps, write_fsm_state_ns; + +//BF enable flags +logic bf_enable_fsm, bf_enable_reg, bf_enable_reg_d2; + +//Buffer signals +logic buf_wr_rst_count_ntt, buf_rd_rst_count_ntt; +logic buf_wr_rst_count_intt, buf_rd_rst_count_intt; +logic [1:0] buf_count; + +//Shuffle buffer signals +logic [3:0] chunk_rand_offset; +logic [3:0] chunk_count; +logic [1:0] index_rand_offset, index_count, mem_rd_index_ofst; +logic [1:0] buf_rdptr_int; +logic [1:0] buf_rdptr_f; +logic [UNMASKED_BF_LATENCY:0][1:0] buf_rdptr_reg; +//logic [INTT_WRBUF_LATENCY-1:0][1:0] buf_wrptr_reg; +logic [MASKED_INTT_WRBUF_LATENCY-1:0][1:0] buf_wrptr_reg; +// logic [MASKED_BF_STAGE1_LATENCY:0][3:0] chunk_count_reg; +logic [MASKED_INTT_WRBUF_LATENCY-3:0][3:0] chunk_count_reg; //buf latency not rqd + +logic latch_chunk_rand_offset, latch_index_rand_offset; +logic last_rd_addr, last_wr_addr; +logic mem_wr_en_fsm, mem_wr_en_reg; +logic mem_rd_en_fsm, mem_rd_en_reg; +logic pw_rden_fsm, pw_rden_reg; +logic pw_wren_fsm, pw_wren_reg; + +//Mode flags +logic ct_mode, gs_mode, pwo_mode; //point-wise operations mode +logic pwm_mode, pwa_mode, pws_mode; +logic pwm_intt_mode; + +//Addr internal wires +logic [MEM_ADDR_WIDTH-1:0] src_base_addr, interim_base_addr, dest_base_addr; +logic [MEM_ADDR_WIDTH-1:0] pw_base_addr_a, pw_base_addr_b, pw_base_addr_c; +logic [MEM_ADDR_WIDTH-1:0] pw_mem_rd_addr_a_nxt, pw_mem_rd_addr_b_nxt, pw_mem_rd_addr_c_nxt, pw_mem_wr_addr_c_nxt; +logic incr_mem_rd_addr; +logic incr_mem_wr_addr; +logic rst_rd_addr, rst_wr_addr; //TODO: need both? +logic [MEM_ADDR_WIDTH:0] mem_rd_addr_nxt, mem_wr_addr_nxt; //One extra bit in addr to roll over addr, so we can wraparound in the addr range +logic [MEM_ADDR_WIDTH-1:0] mem_rd_base_addr, mem_wr_base_addr; +logic [4:0] rd_addr_step, wr_addr_step; +logic rd_addr_wraparound; +logic wr_addr_wraparound; + +//PWO wires +logic incr_pw_rd_addr, incr_pw_wr_addr; //TODO: need both? +logic rst_pw_addr; + +//Twiddle ROM wires +logic incr_twiddle_addr, incr_twiddle_addr_fsm, incr_twiddle_addr_reg, incr_twiddle_addr_reg_d2; +logic twiddle_mode, rst_twiddle_addr; +logic [6:0] twiddle_rand_offset; +logic [6:0] twiddle_end_addr, twiddle_addr_reg, twiddle_addr_reg_d2, twiddle_addr_reg_d3, twiddle_addr_int, twiddle_offset; + +//FSM round signals +logic [$clog2(NTT_NUM_ROUNDS):0] num_rounds; +logic [$clog2(NTT_NUM_ROUNDS):0] rounds_count; +logic incr_rounds; +logic rst_rounds; + +//Done, busy flags +logic stage_done; +logic ntt_done; +logic intt_done; +logic pwo_done; +logic ntt_busy; +logic pwo_busy; + +//Valid count wires - counts 64 cycles of valid +logic [6:0] wr_valid_count; +logic [6:0] rd_valid_count_int, rd_valid_count; +logic wr_data_valid; +logic rd_data_valid; +logic rst_wr_valid_count, rst_rd_valid_count; + +//Read FSM +//Common arcs +logic arc_IDLE_RD_STAGE; +logic arc_RD_EXEC_RD_STAGE; +logic arc_RD_STAGE_IDLE; + +//NTT Arcs +logic arc_RD_STAGE_RD_BUF; +logic arc_RD_BUF_RD_EXEC; +logic arc_RD_EXEC_RD_BUF; +logic arc_RD_EXEC_EXEC_WAIT; +logic arc_EXEC_WAIT_RD_STAGE; + +//INTT Arcs +logic arc_RD_STAGE_RD_EXEC; +logic arc_RD_STAGE_RD_EXEC_OPT; + +//PWO Arc +logic arc_EXEC_WAIT_RD_EXEC; + +//Other signals +logic buf_wren_ntt, buf_wren_ntt_reg; +logic buf_wren_intt, buf_wren_intt_reg; +logic buf_rden_ntt, buf_rden_ntt_reg; +logic buf_rden_intt; + +//Write FSM +//Common arcs +logic arc_IDLE_WR_STAGE; +logic arc_WR_MEM_WR_STAGE; +logic arc_WR_STAGE_IDLE; + +//NTT Arcs +logic arc_WR_STAGE_WR_MEM; + +//INTT Arcs +logic arc_WR_STAGE_WR_BUF; +logic arc_WR_BUF_WR_MEM; +logic arc_WR_MEM_WR_BUF; +logic arc_WR_MEM_WR_WAIT; +logic arc_WR_WAIT_WR_STAGE; + +//PWO Arcs +logic arc_WR_STAGE_WR_WAIT; +logic arc_WR_WAIT_WR_MEM; +logic arc_WR_STAGE_WR_MEM_OPT; + +//------------------------------------------ +always_comb begin + ct_mode = (ntt_mode == ct); + gs_mode = (ntt_mode == gs) | ((ntt_mode == pwm_intt) & (rounds_count > 'h0)); + pwo_mode = ntt_mode inside {pwm, pwa, pws}; + pwm_mode = (ntt_mode == pwm); + pwa_mode = (ntt_mode == pwa); + pws_mode = (ntt_mode == pws); + pwm_intt_mode = (ntt_mode == pwm_intt) & (rounds_count == 'h0); +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + opcode <= ct; //default + masking_en_ctrl <= 'b0; + end + else if (zeroize) begin + opcode <= ct; + masking_en_ctrl <= 'b0; + end + else begin + if (pwm_intt_mode) begin //1st round + opcode <= pwm_intt; + masking_en_ctrl <= 'b1; + end + else if (ntt_mode == pwm_intt) begin //subseq rounds + opcode <= gs; + masking_en_ctrl <= 'b0; + end + else begin + opcode <= ntt_mode; //all others + masking_en_ctrl <= 'b0; + end + end +end + +//------------------------------------------ +//Rounds counter +//------------------------------------------ +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + rounds_count <= 'h0; + else if (zeroize) + rounds_count <= 'h0; + else if (rst_rounds) + rounds_count <= 'h0; + else if (incr_rounds && (rounds_count < num_rounds)) + rounds_count <= rounds_count + 'h1; + else if (rounds_count == num_rounds) + rounds_count <= 'h0; +end +assign num_rounds = (ntt_mode inside {ct, gs, pwm_intt}) ? NTT_NUM_ROUNDS : PWO_NUM_ROUNDS; + +//------------------------------------------ +//Done flags +//------------------------------------------ +//Stage is done when round counter is incremented and both fsms are in stage state +assign stage_done = (rounds_count > 'h0) && (read_fsm_state_ps == RD_STAGE) && (write_fsm_state_ps == WR_STAGE);//incr_rounds; +assign ntt_done = ct_mode && (rounds_count == NTT_NUM_ROUNDS); +assign intt_done = gs_mode && (rounds_count == NTT_NUM_ROUNDS); +assign pwo_done = pwo_mode && (rounds_count == PWO_NUM_ROUNDS); +assign done = ntt_done | intt_done | pwo_done; + +//------------------------------------------ +//Mem read/write addr counter +//------------------------------------------ +//NTT mem addr +always_comb begin + src_base_addr = (ct_mode | gs_mode) ? ntt_mem_base_addr.src_base_addr : 'h0; //not used in pwm_intt + interim_base_addr = (ct_mode | gs_mode | pwm_intt_mode) ? ntt_mem_base_addr.interim_base_addr : 'h0; + dest_base_addr = (ct_mode | gs_mode | pwm_intt_mode) ? ntt_mem_base_addr.dest_base_addr : 'h0; + + pw_base_addr_a = (pwo_mode | pwm_intt_mode) ? pwo_mem_base_addr.pw_base_addr_a : 'h0; + pw_base_addr_b = (pwo_mode | pwm_intt_mode) ? pwo_mem_base_addr.pw_base_addr_b : 'h0; + pw_base_addr_c = pwo_mode ? pwo_mem_base_addr.pw_base_addr_c : 'h0; //not used in pwm_intt. TODO check when PWMA is enabled in masking +end +//Wraparound - indicates if we need to start at next addr (Eg. 0, 16, 32, 48, 1, 17, 33, 49, 2, ...) +//Wraparound allows addr to transition from 48 to 1, 49 to 2, etc instead of overflowing +always_comb begin + mem_rd_base_addr = (rounds_count == 'h0) ? src_base_addr : rounds_count[0] ? interim_base_addr : dest_base_addr; + mem_wr_base_addr = rounds_count[0] ? dest_base_addr : interim_base_addr; + + if (shuffle_en) begin + mem_rd_addr_nxt = (gs_mode | pwo_mode) ? (4*chunk_count) + (rd_addr_step*mem_rd_index_ofst) + mem_rd_base_addr : mem_rd_addr + rd_addr_step; + mem_wr_addr_nxt = ct_mode ? (MEM_ADDR_WIDTH+1)'((4*chunk_count_reg[0]) + (wr_addr_step*buf_rdptr_reg[0]) + mem_wr_base_addr) : (gs_mode | pwm_intt_mode) ? mem_wr_addr + wr_addr_step : (MEM_ADDR_WIDTH+1)'((4*chunk_count_reg[4]) + (wr_addr_step*buf_rdptr_reg[4])); + end + else begin + mem_rd_addr_nxt = mem_rd_addr + rd_addr_step; + mem_wr_addr_nxt = mem_wr_addr + wr_addr_step; + end + + rd_addr_wraparound = mem_rd_addr_nxt > {1'b0,mem_rd_base_addr} + MEM_LAST_ADDR; + wr_addr_wraparound = mem_wr_addr_nxt > {1'b0,mem_wr_base_addr} + MEM_LAST_ADDR; +end + +//Read addr +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_rd_addr <= 'h0; + end + else if (zeroize) begin + mem_rd_addr <= 'h0; + end + else if (rst_rd_addr) begin + if (shuffle_en) + mem_rd_addr <= ct_mode ? mem_rd_base_addr + chunk_rand_offset : (gs_mode | pwo_mode) ? mem_rd_base_addr + (4*chunk_rand_offset) : mem_rd_base_addr; + else + mem_rd_addr <= mem_rd_base_addr; + end + else if (incr_mem_rd_addr) begin + if (shuffle_en) + mem_rd_addr <= (ct_mode & last_rd_addr) ? mem_rd_base_addr : rd_addr_wraparound ? MEM_ADDR_WIDTH'(mem_rd_addr_nxt - MEM_LAST_ADDR) : mem_rd_addr_nxt[MEM_ADDR_WIDTH-1:0]; + else + mem_rd_addr <= rd_addr_wraparound ? MEM_ADDR_WIDTH'(mem_rd_addr_nxt - MEM_LAST_ADDR) : mem_rd_addr_nxt[MEM_ADDR_WIDTH-1:0]; + end +end + +//Write addr +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_wr_addr <= 'h0; + end + else if (zeroize) begin + mem_wr_addr <= 'h0; + end + else if (rst_wr_addr) begin + if (shuffle_en) + mem_wr_addr <= (ct_mode | pwo_mode) ? mem_wr_base_addr + (4*chunk_rand_offset) : (gs_mode | pwm_intt_mode) ? mem_wr_base_addr + chunk_rand_offset : mem_wr_base_addr; + else + mem_wr_addr <= mem_wr_base_addr; + end + else if (incr_mem_wr_addr) begin + if (shuffle_en) + mem_wr_addr <= ((gs_mode | pwm_intt_mode) & last_wr_addr) ? mem_wr_base_addr : wr_addr_wraparound ? MEM_ADDR_WIDTH'(mem_wr_addr_nxt - MEM_LAST_ADDR) : mem_wr_addr_nxt[MEM_ADDR_WIDTH-1:0]; + else + mem_wr_addr <= wr_addr_wraparound ? MEM_ADDR_WIDTH'(mem_wr_addr_nxt - MEM_LAST_ADDR) : mem_wr_addr_nxt[MEM_ADDR_WIDTH-1:0]; + end +end + +always_comb begin + pw_mem_rd_addr_a_nxt = pw_base_addr_a + (4*chunk_count) + (PWO_READ_ADDR_STEP*mem_rd_index_ofst); + pw_mem_rd_addr_b_nxt = pw_base_addr_b + (4*chunk_count) + (PWO_READ_ADDR_STEP*mem_rd_index_ofst); + pw_mem_rd_addr_c_nxt = accumulate ? pw_base_addr_c + ((4*chunk_count)+(PWO_READ_ADDR_STEP*mem_rd_index_ofst)) : 'h0; //TODO check timing + pw_mem_wr_addr_c_nxt = accumulate ? pw_base_addr_c + (4*chunk_count_reg[UNMASKED_PWM_LATENCY-2]) + (PWO_WRITE_ADDR_STEP*buf_rdptr_reg[UNMASKED_PWM_LATENCY-2]) + : (pwa_mode | pws_mode) ? pw_base_addr_c + (4*chunk_count_reg[7]) + (PWO_WRITE_ADDR_STEP*buf_rdptr_reg[7]) + : pw_base_addr_c + (4*chunk_count_reg[UNMASKED_PWM_LATENCY-1]) + (PWO_WRITE_ADDR_STEP*buf_rdptr_reg[UNMASKED_PWM_LATENCY-1]); //2 +end + +//PWO addr +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + pw_mem_rd_addr_a <= '0; + pw_mem_rd_addr_b <= '0; + pw_mem_rd_addr_c <= '0; + pw_mem_wr_addr_c <= '0; + end + else if (zeroize) begin + pw_mem_rd_addr_a <= '0; + pw_mem_rd_addr_b <= '0; + pw_mem_rd_addr_c <= '0; + pw_mem_wr_addr_c <= '0; + end + else if (rst_pw_addr) begin + pw_mem_rd_addr_a <= shuffle_en ? (4*chunk_rand_offset) + pw_base_addr_a : pw_base_addr_a; + pw_mem_rd_addr_b <= shuffle_en ? (4*chunk_rand_offset) + pw_base_addr_b : pw_base_addr_b; + pw_mem_rd_addr_c <= shuffle_en ? (4*chunk_rand_offset) + pw_base_addr_c : pw_base_addr_c; + pw_mem_wr_addr_c <= shuffle_en ? (4*chunk_rand_offset) + pw_base_addr_c : pw_base_addr_c; + end + else begin + if (incr_pw_rd_addr) begin + if (shuffle_en) begin + pw_mem_rd_addr_a <= pw_mem_rd_addr_a_nxt; + pw_mem_rd_addr_b <= pw_mem_rd_addr_b_nxt; + pw_mem_rd_addr_c <= accumulate ? pw_mem_rd_addr_c_nxt : 'h0; //addr in sync with a, b. However, the data is flopped 4 cycles inside BF to align with mul result + end + else begin + pw_mem_rd_addr_a <= pw_mem_rd_addr_a + PWO_READ_ADDR_STEP; + pw_mem_rd_addr_b <= pw_mem_rd_addr_b + PWO_READ_ADDR_STEP; + pw_mem_rd_addr_c <= accumulate ? pw_mem_rd_addr_c + PWO_READ_ADDR_STEP : 'h0; //addr in sync with a, b. However, the data is flopped 4 cycles inside BF to align with mul result + end + end + if (incr_pw_wr_addr) begin + pw_mem_wr_addr_c <= shuffle_en ? pw_mem_wr_addr_c_nxt : pw_mem_wr_addr_c + PWO_WRITE_ADDR_STEP; + end + end +end + + +//------------------------------------------ +//Twiddle addr logic +//------------------------------------------ +always_comb begin + unique case(rounds_count) + 'h0: begin + twiddle_end_addr = ct_mode ? 'd0 : 'd63; + twiddle_offset = 'h0; + twiddle_rand_offset = ct_mode ? 'h0 : pwm_intt_mode ? 7'((4*chunk_count_reg[MASKED_INTT_WRBUF_LATENCY-MASKED_PWM_LATENCY-3]) + buf_wrptr_reg[MASKED_INTT_WRBUF_LATENCY-MASKED_PWM_LATENCY-1]) : 7'((4*chunk_count_reg[UNMASKED_BF_LATENCY]) + buf_wrptr_reg[INTT_WRBUF_LATENCY-1]); //pwm_intt mode only applies to round 0. Other rounds follow gs calc + end + 'h1: begin + twiddle_end_addr = ct_mode ? 'd3 : 'd15; + twiddle_offset = ct_mode ? 'd1 : 'd64; + twiddle_rand_offset = ct_mode ? 7'(buf_rdptr_int) : 7'((chunk_count_reg[UNMASKED_BF_LATENCY] % 4)*4 + buf_wrptr_reg[INTT_WRBUF_LATENCY-1]); + end + 'h2: begin + twiddle_end_addr = ct_mode ? 'd15 : 'd3; + twiddle_offset = ct_mode ? 'd5 : 'd80; + twiddle_rand_offset = ct_mode ? 7'((chunk_count % 'd4)*'d4 + buf_rdptr_int) : 7'(buf_wrptr_reg[INTT_WRBUF_LATENCY-1]); + end + 'h3: begin + twiddle_end_addr = ct_mode ? 'd63 : 'd0; + twiddle_offset = ct_mode ? 'd21 : 'd84; + twiddle_rand_offset = ct_mode ? 7'((chunk_count % 'd16)*4 + buf_rdptr_int) : 'h0; + end + default: begin + twiddle_end_addr = 'h0; + twiddle_offset = 'h0; + twiddle_rand_offset = 'h0; + end + endcase +end + +//Flop the incr and twiddle_addr to align with memory read latency +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + incr_twiddle_addr_reg <= 'b0; + incr_twiddle_addr_reg_d2 <= 'b0; + end + else if (zeroize) begin + incr_twiddle_addr_reg <= 'b0; + incr_twiddle_addr_reg_d2 <= 'b0; + end + else begin + incr_twiddle_addr_reg <= incr_twiddle_addr_fsm; + incr_twiddle_addr_reg_d2 <= incr_twiddle_addr_reg; + end +end + +assign incr_twiddle_addr = ct_mode ? incr_twiddle_addr_fsm : incr_twiddle_addr_reg; + + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + twiddle_addr_reg <= 'h0; + else if (zeroize) + twiddle_addr_reg <= 'h0; + else if (incr_twiddle_addr) + twiddle_addr_reg <= shuffle_en ? twiddle_rand_offset : (twiddle_addr_reg == twiddle_end_addr) ? 'h0 : twiddle_addr_reg + 'd1; + else if (rst_twiddle_addr) + twiddle_addr_reg <= 'h0; +end + +assign twiddle_addr_int = (~shuffle_en | ct_mode) ? twiddle_addr_reg + twiddle_offset : twiddle_rand_offset + twiddle_offset; + +//------------------------------------------ +//Busy logic +//------------------------------------------ +assign busy = ntt_busy | pwo_busy; +assign ntt_busy = (read_fsm_state_ps != RD_IDLE) && (write_fsm_state_ps != WR_IDLE) && (ct_mode | gs_mode); +assign pwo_busy = (read_fsm_state_ps != RD_IDLE) && (write_fsm_state_ps != WR_IDLE) && (pwo_mode | pwm_intt_mode); + +//------------------------------------------ +//Valid count - to check that all 64 addr have been processed - check writes to mem +//------------------------------------------ +always_comb wr_data_valid = (gs_mode | pwm_intt_mode) ? buf0_valid : butterfly_ready; //ct or pwo mode - look for bf_ready +always_comb rd_data_valid = ct_mode ? buf0_valid : gs_mode ? bf_enable_fsm : sampler_valid; + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + wr_valid_count <= 'h0; + else if (zeroize) + wr_valid_count <= 'h0; + else if (rst_wr_valid_count) + wr_valid_count <= 'h0; + else if (wr_data_valid) + wr_valid_count <= (gs_mode | pwm_intt_mode) ? (wr_valid_count > 'h40) ? 'h0 : wr_valid_count + 'h4 + : wr_valid_count + 'h1; +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + rd_valid_count <= 'h0; + else if (zeroize) + rd_valid_count <= 'h0; + else if (rst_rd_valid_count) + rd_valid_count <= 'h0; + else if (rd_data_valid) + rd_valid_count <= ct_mode ? (rd_valid_count > 'h40) ? 'h0 : rd_valid_count + 'h4 + : rd_valid_count + 'h1; + +end + +//------------------------------------------ +//Buffer count - start count when buf0_valid is received +//Once counter starts, count until 3 to signify that all 4 buffers +//are valid. Then wait at 0 until next buf0_valid comes in +//------------------------------------------ +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + buf_count <= 'h0; + else if (zeroize) + buf_count <= 'h0; + else if (buf0_valid) + buf_count <= buf_count + 1; + else if (buf_count > 0 && buf_count < 3) + buf_count <= buf_count + 1; + else + buf_count <= 'h0; +end + +//------------------------------------------ +//Shuffle buffer +//------------------------------------------ +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + chunk_rand_offset <= 'h0; + chunk_count <= 'h0; + end + else if (zeroize) begin + chunk_rand_offset <= 'h0; + chunk_count <= 'h0; + end + else if (latch_chunk_rand_offset) begin + chunk_rand_offset <= random[5:2]; + chunk_count <= random[5:2]; + end + else if ((ct_mode & (buf_count == 'h3)) | (((gs_mode | pwm_intt_mode) | (pwo_mode & incr_pw_rd_addr)) & (index_count == 'h3))) begin //update chunk after every 4 cycles - TODO: stop chunk counting when there's no incr_rd_addr in ntt/intt modes + chunk_count <= (chunk_count == 'hf) ? 'h0 : chunk_count + 'h1; + end +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + index_rand_offset <= 'h0; + + end + else if (zeroize) begin + index_rand_offset <= 'h0; + + end + else if (latch_index_rand_offset) begin + index_rand_offset <= random[1:0]; + end + +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buf_rdptr_reg <= 'h0; + buf_wrptr_reg <= 'h0; + end + else if (zeroize) begin + buf_rdptr_reg <= 'h0; + buf_wrptr_reg <= 'h0; + end + else if (ct_mode & (buf_rden_ntt | butterfly_ready)) begin + buf_rdptr_reg <= {buf_rdptr_int, buf_rdptr_reg[UNMASKED_BF_LATENCY:1]}; + end + else if ((gs_mode & (incr_mem_rd_addr | butterfly_ready))) begin + buf_wrptr_reg <= {{(MASKED_INTT_WRBUF_LATENCY-INTT_WRBUF_LATENCY){2'h0}}, mem_rd_index_ofst, buf_wrptr_reg[INTT_WRBUF_LATENCY-1:1]}; + end + else if (pwo_mode & (incr_pw_rd_addr | butterfly_ready)) begin + buf_rdptr_reg <= {mem_rd_index_ofst, buf_rdptr_reg[UNMASKED_BF_LATENCY:1]}; //TODO: create new reg with apt name for PWO + end + else if ((pwm_intt_mode)) begin + buf_wrptr_reg <= {mem_rd_index_ofst, buf_wrptr_reg[MASKED_INTT_WRBUF_LATENCY-1:1]}; + end + else if ((pwm_intt_mode)) begin + buf_wrptr_reg <= {mem_rd_index_ofst, buf_wrptr_reg[MASKED_INTT_WRBUF_LATENCY-1:1]}; + end + else begin + buf_rdptr_reg <= 'h0; + buf_wrptr_reg <= 'h0; + end +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buf_rdptr_f <= 'h0; + end + else if (zeroize) begin + buf_rdptr_f <= 'h0; + end + else begin + buf_rdptr_f <= buf_rdptr_int; + end +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + index_count <= 'h0; + end + else if (zeroize) begin + index_count <= 'h0; + end + else if ((gs_mode & incr_mem_rd_addr) | ((pwo_mode | pwm_intt_mode) & incr_pw_rd_addr)) begin + index_count <= index_count + 'h1; + end +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + chunk_count_reg <= 'h0; + end + else if (zeroize) begin + chunk_count_reg <= 'h0; + end + //chunk update can't use incr_mem_rd_addr in pwm_intt mode. + else if (pwm_intt_mode/* & incr_pw_rd_addr*/) begin + chunk_count_reg <= {chunk_count, chunk_count_reg[MASKED_INTT_WRBUF_LATENCY-3:1]}; + end + else if (buf_rden_ntt | butterfly_ready | (gs_mode & incr_mem_rd_addr) | (pwo_mode & incr_pw_rd_addr)) begin //TODO: replace gs condition with an fsm generated flag perhaps? + chunk_count_reg <= {{(MASKED_BF_STAGE1_LATENCY+1-UNMASKED_BF_LATENCY){4'h0}}, chunk_count, chunk_count_reg[UNMASKED_BF_LATENCY:1]}; + end +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buf_wrptr <= 'h0; + end + else if (zeroize) begin + buf_wrptr <= 'h0; + end + else if (buf_wren & (ct_mode | ~shuffle_en)) begin //ct mode - buf writes are in order + buf_wrptr <= (buf_wrptr == 'h3) ? 'h0 : buf_wrptr + 'h1; + end + else if (buf_wren_intt & (gs_mode | pwm_intt_mode) & shuffle_en) begin // gs mode + buf_wrptr <= buf_wrptr_reg[0]; + end +end + +always_comb begin + last_rd_addr = (mem_rd_addr == mem_rd_base_addr + MEM_LAST_ADDR); + last_wr_addr = (mem_wr_addr == mem_wr_base_addr + MEM_LAST_ADDR); + buf_rdptr_int = (shuffle_en & ct_mode) ? index_rand_offset + buf_count : buf_count; //TODO: flop? + buf_rdptr = (shuffle_en & ct_mode) ? buf_rdptr_f : buf_count; + latch_chunk_rand_offset = arc_IDLE_WR_STAGE | arc_WR_MEM_WR_STAGE | arc_WR_WAIT_WR_STAGE; + latch_index_rand_offset = ct_mode ? (buf_wrptr == 'h3) : ((gs_mode | pwm_intt_mode) | (pwo_mode & incr_pw_rd_addr)) & (arc_RD_STAGE_RD_EXEC | (index_count == 'h3)); + mem_rd_index_ofst = (pwo_mode | gs_mode | pwm_intt_mode) ? (index_count + index_rand_offset) : 'h0; +end + + +//------------------------------------------ +//NTT/INTT Read FSM +//------------------------------------------ +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= RD_IDLE; + else if (zeroize) + read_fsm_state_ps <= RD_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; +end + +//Arc assignments +always_comb begin + //Start NTT/INTT op when fsm is in IDLE state and there's an enable coming in + arc_IDLE_RD_STAGE = (read_fsm_state_ps == RD_IDLE) && ntt_enable ; //FSM will not enter IDLE state until entire NTT/INTT is done, so we will not accept any new commands + //For these two arcs, perf can be possibly optimized: + //When fsm comes back to stage, reads are done, butterfly is executing the last 10 inputs + //write fsm needs to write last 10 outputs to memory + //If we let read fsm to advance to next round, there is a latency of 4 cycles (from buffer) + 10 cycles (from butterfly) + //before the output is written back to memory. This is best case (no bubbles) + //In this case, there is time for butterfly to produce output while the writes from previous round finish + //TODO: review this assumption. For now, assuming we wait until entire round on both read and write side is done + + //Check to make sure all writes from prev round have finished before moving onto next round in read fsm + arc_RD_STAGE_RD_BUF = (read_fsm_state_ps == RD_STAGE) && (write_fsm_state_ps == WR_STAGE) && (ct_mode && !ntt_done); + arc_RD_STAGE_RD_EXEC = (read_fsm_state_ps == RD_STAGE) && (write_fsm_state_ps == WR_STAGE) && (((gs_mode | pwm_intt_mode) && !intt_done) || (pwo_mode && (!pwo_done /*|| ntt_enable*/))); + + //Don't wait for writes to complete before transitioning to next round. (See above TODO) + arc_RD_STAGE_RD_EXEC_OPT= (read_fsm_state_ps == RD_STAGE) && /*(write_fsm_state_ps == WR_STAGE) &&*/ ((gs_mode && !intt_done) || (pwo_mode && (!pwo_done /*|| ntt_enable*/))); + + //This arc is only for ct mode. When buffer is valid, bf2x2 can be enabled + arc_RD_BUF_RD_EXEC = (read_fsm_state_ps == RD_BUF ) && buf0_valid; + + //This arc is only for ct mode. If there's no buf0_valid, all 4 buffers have been emptied and total valid_count is < 64, go back to buf state and wait for it to fill up + //Indicates that buf0, 1, 2 3 have finished executing and there's no valid input, so wait for buf to fill up again + //Since there's an input buffer, valid_count is counted in steps of 4, so it ends at 64 + arc_RD_EXEC_RD_BUF = (read_fsm_state_ps == RD_EXEC ) && ct_mode && (!buf0_valid && (buf_count == 0)) && (rd_valid_count < 'h40); + + //This arc is only for gs mode. Execution is done when all 63 addr locations have been read. Since there's no input buffer, valid_count ends at 63. + arc_RD_EXEC_RD_STAGE = (read_fsm_state_ps == RD_EXEC ) && ((gs_mode || pwo_mode || pwm_intt_mode) && (rd_valid_count == 'h3f)); + + //All rounds of NTT or INTT are done. Go to IDLE and wait for next command. In PWO mode, if ntt_enable is given, start next op + arc_RD_STAGE_IDLE = (read_fsm_state_ps == RD_STAGE) && (ntt_done || intt_done || (pwo_done && !ntt_enable)); + + //This arc is only for ct mode. Move to EXEC_WAIT state when the last read is done. No more reads to perform, but the buffer needs to be emptied + arc_RD_EXEC_EXEC_WAIT = (read_fsm_state_ps == RD_EXEC ) && ((ct_mode && (((buf_count == 'h3) && (rd_valid_count == 'h3c)))) || (pwo_mode && !sampler_valid)); + + //This arc is only for pwo mode. Move back to RD_EXEC when sampler_valid is available + arc_EXEC_WAIT_RD_EXEC = (read_fsm_state_ps == EXEC_WAIT) && (pwo_mode && sampler_valid && (rd_valid_count < 'h3f)); + + //This arc is only for ct mode. When valid_count is 64 and buf_count is 3 (meaning all 4 buffers have been used), move to RD_STAGE indicating that round is done + arc_EXEC_WAIT_RD_STAGE = (read_fsm_state_ps == EXEC_WAIT) && (rd_valid_count == 'h40) && (buf_count == 'h3); +end + +always_comb begin + read_fsm_state_ns = read_fsm_state_ps; + buf_wren_ntt = 1'b0; + buf_rden_ntt = 1'b0; + incr_mem_rd_addr = 1'b0; + bf_enable_fsm = 1'b0; + mem_rd_en_fsm = 1'b0; + incr_twiddle_addr_fsm = 1'b0; + rd_addr_step = 'h0; + rst_rd_addr = 1'b0; + rst_rd_valid_count = 1'b0; + buf_wr_rst_count_ntt = 1'b0; + buf_rd_rst_count_ntt = 1'b0; + rst_twiddle_addr = 1'b0; + incr_pw_rd_addr = 1'b0; + pw_rden_fsm = 1'b0; + unique case(read_fsm_state_ps) + RD_IDLE: begin + read_fsm_state_ns = arc_IDLE_RD_STAGE ? RD_STAGE : RD_IDLE; + rst_rd_addr = 1'b1; + rst_rd_valid_count = 1'b1; + buf_wr_rst_count_ntt = 1'b1; + buf_rd_rst_count_ntt = 1'b1; + rst_twiddle_addr = 1'b1; + end + RD_STAGE: begin + read_fsm_state_ns = arc_RD_STAGE_RD_BUF ? RD_BUF : + arc_RD_STAGE_RD_EXEC ? RD_EXEC : + arc_RD_STAGE_IDLE ? RD_IDLE : RD_STAGE; + rst_rd_addr = 1'b1; + rst_rd_valid_count = 1'b1; + //reset if in ntt mode, since writes won't use the buffer, it's safe to reset buffer + buf_wr_rst_count_ntt = ct_mode; + buf_rd_rst_count_ntt = ct_mode; + rst_twiddle_addr = !butterfly_ready; + end + RD_BUF: begin + read_fsm_state_ns = arc_RD_BUF_RD_EXEC ? RD_EXEC : RD_BUF; + buf_wren_ntt = 1'b1; + buf_rden_ntt = buf0_valid; + incr_mem_rd_addr = 1'b1; + mem_rd_en_fsm = 1'b1; + bf_enable_fsm = buf0_valid; //Enable bf2x2 as soon as buf is valid + incr_twiddle_addr_fsm = buf0_valid; + rd_addr_step = NTT_READ_ADDR_STEP; + end + RD_EXEC: begin + read_fsm_state_ns = arc_RD_EXEC_RD_BUF ? RD_BUF : + arc_RD_EXEC_RD_STAGE ? RD_STAGE : + arc_RD_EXEC_EXEC_WAIT ? EXEC_WAIT : RD_EXEC; + buf_wren_ntt = ct_mode; + buf_rden_ntt = ct_mode; + incr_mem_rd_addr = (ntt_mode inside {ct, gs, pwm_intt}) & !pwm_intt_mode; + if (shuffle_en) + mem_rd_en_fsm = ((ntt_mode inside {ct, gs, pwm_intt}) & !pwm_intt_mode) ? (mem_rd_addr <= MEM_LAST_ADDR + mem_rd_base_addr) & ~arc_RD_EXEC_EXEC_WAIT : 1'b0; + else + mem_rd_en_fsm = ((ntt_mode inside {ct, gs, pwm_intt}) & !pwm_intt_mode) ? (mem_rd_addr <= MEM_LAST_ADDR + mem_rd_base_addr) : 1'b0; + bf_enable_fsm = pwo_mode ? sampler_valid : 1'b1; + incr_twiddle_addr_fsm = ntt_mode inside {ct, gs, pwm_intt}; + rd_addr_step = ct_mode ? NTT_READ_ADDR_STEP : INTT_READ_ADDR_STEP; + incr_pw_rd_addr = sampler_valid & (pwo_mode | pwm_intt_mode); + pw_rden_fsm = sampler_valid & (pwo_mode | pwm_intt_mode); + end + EXEC_WAIT: begin + read_fsm_state_ns = arc_EXEC_WAIT_RD_STAGE ? RD_STAGE : arc_EXEC_WAIT_RD_EXEC ? RD_EXEC : EXEC_WAIT; + buf_wren_ntt = (buf_count < 3) && !pwo_mode; + buf_rden_ntt = !pwo_mode; + buf_wr_rst_count_ntt = 1'b1; //There are no more mem reads, so buf writes need to halt + buf_rd_rst_count_ntt = 1'b0; //There are still some entries in buf that BF2x2 needs to pick up + bf_enable_fsm = pwo_mode ? sampler_valid : (buf_count <= 3); + incr_twiddle_addr_fsm = (ct_mode | gs_mode | pwm_intt_mode); + rd_addr_step = NTT_READ_ADDR_STEP; + incr_pw_rd_addr = ((pwo_mode | pwm_intt_mode) & sampler_valid); + pw_rden_fsm = ((pwo_mode | pwm_intt_mode) & sampler_valid); + end + default: begin + read_fsm_state_ns = RD_IDLE; + end + endcase +end + +//------------------------------------------ +//NTT/INTT Write FSM +//------------------------------------------ +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + write_fsm_state_ps <= WR_IDLE; + else if (zeroize) + write_fsm_state_ps <= WR_IDLE; + else + write_fsm_state_ps <= write_fsm_state_ns; +end + +//Arc assignments +always_comb begin + //Start NTT/INTT op when fsm is in IDLE state and there's an enable coming in + arc_IDLE_WR_STAGE = (write_fsm_state_ps == WR_IDLE) && ntt_enable ; + + if (shuffle_en) begin + //This arc is only for ct mode. No buffer in the path, so wait for all addr to be written (0-63) before transitioning to WR_STAGE + arc_WR_MEM_WR_STAGE = (write_fsm_state_ps == WR_MEM) && ((ct_mode) && (wr_valid_count == 'h3f)); //(mem_wr_addr == (mem_wr_base_addr + MEM_LAST_ADDR)); //this arc is for ct mode, + + //This arc is only for ct mode since there's no output buffer + arc_WR_STAGE_WR_MEM = (write_fsm_state_ps == WR_STAGE) && ((ct_mode && !ntt_done) || (pwo_mode && !pwo_done)); // || (pwo_mode && (!pwo_done /*|| ntt_enable*/))); + end + else begin + arc_WR_MEM_WR_STAGE = (write_fsm_state_ps == WR_MEM) && ((ct_mode || pwo_mode) && (wr_valid_count == 'h3f)); //(mem_wr_addr == (mem_wr_base_addr + MEM_LAST_ADDR)); //this arc is for ct mode, + arc_WR_STAGE_WR_MEM = (write_fsm_state_ps == WR_STAGE) && (ct_mode && !ntt_done); + end + + //All rounds of NTT or INTT are done. Go to IDLE and wait for next command + arc_WR_STAGE_IDLE = (write_fsm_state_ps == WR_STAGE) && (ntt_done || intt_done || pwo_done); + + //pwm arc. If in WR_STAGE, read fsm is executing, go back to WR_MEM state to perform current round's writes + arc_WR_STAGE_WR_MEM_OPT = (write_fsm_state_ps == WR_STAGE) && (read_fsm_state_ps == RD_EXEC) && (pwo_mode && pwo_busy); + + //This arc is only for gs mode + arc_WR_STAGE_WR_BUF = (write_fsm_state_ps == WR_STAGE) && (gs_mode || pwm_intt_mode) && !intt_done; + + //pwm arc. If in WR STAGE, transition directly to wait + arc_WR_STAGE_WR_WAIT = (write_fsm_state_ps == WR_STAGE) && (pwo_mode && !pwo_done); + + //This arc is only for gs mode. Start writing to memory when buf0_valid is asserted + arc_WR_BUF_WR_MEM = (write_fsm_state_ps == WR_BUF) && ((gs_mode || pwm_intt_mode) && buf0_valid); + + //This arc is only for gs mode. If there's no buf0_valid, all 4 buffers have been emptied and total valid_count is < 64, go back to buf state and wait for it to fill up + //Indicates that buf0, 1, 2 3 have finished executing and there's no valid input, so wait for buf to fill up again + //Since there's an output buffer, valid_count is counted in steps of 4, so it ends at 64 + arc_WR_MEM_WR_BUF = (write_fsm_state_ps == WR_MEM) && ((gs_mode || pwm_intt_mode) && (!buf0_valid && (buf_count == 0)) && (wr_valid_count < 'h40)); + + //Move to WR_WAIT state when the last outputs from bf2x2 have been captured in the buffers. They still need to be shifted out of the buffers and into memory, so keep buf_wren 1 here + //Assumption - no bubbles in NTT or INTT. If bubbles, need to consider sampler_valid + //TODO: can WR_WAIT state be removed? fsm can finish all 64 addr in WR_MEM state? + arc_WR_MEM_WR_WAIT = shuffle_en ? (write_fsm_state_ps == WR_MEM) && (((gs_mode || pwm_intt_mode) && (buf0_valid && (wr_valid_count == 'h3c))) || (pwo_mode && butterfly_ready && (wr_valid_count == 'h3f))) + : (write_fsm_state_ps == WR_MEM) && (((gs_mode || pwm_intt_mode) && (buf0_valid && (wr_valid_count == 'h3c))) || (pwo_mode && !butterfly_ready && (wr_valid_count < 'h3f))); // || (ct_mode && (wr_valid_count == 'h3f))); + + //This arc is only for pwo mode. Move back from wait to write state when there's a valid BFU output + arc_WR_WAIT_WR_MEM = (write_fsm_state_ps == WR_WAIT) && (pwo_mode && butterfly_ready); + + //When valid_count is 64 and buf_count is 3 (meaning all 4 buffers have been used), move to WR_STAGE indicating that round is done + arc_WR_WAIT_WR_STAGE = shuffle_en ? (write_fsm_state_ps == WR_WAIT) && (((gs_mode || pwm_intt_mode) && (buf_count == 'h3)) || ct_mode || pwo_mode) + : (write_fsm_state_ps == WR_WAIT) && (!pwo_mode && (buf_count == 'h3)); +end + +always_comb begin + write_fsm_state_ns = write_fsm_state_ps; + buf_wren_intt = 1'b0; + buf_rden_intt = 1'b0; + incr_mem_wr_addr = 1'b0; + mem_wr_en_fsm = 1'b0; + wr_addr_step = 'h0; + rst_wr_addr = 1'b0; + rst_wr_valid_count = 1'b0; + buf_wr_rst_count_intt = 1'b0; + buf_rd_rst_count_intt = 1'b0; + incr_pw_wr_addr = 1'b0; + pw_wren_fsm = 1'b0; + rst_pw_addr = 1'b0; + unique case(write_fsm_state_ps) + WR_IDLE: begin + write_fsm_state_ns = arc_IDLE_WR_STAGE ? WR_STAGE : WR_IDLE; + rst_wr_addr = 1'b1; + rst_wr_valid_count = 1'b1; + rst_pw_addr = 1'b1; + end + WR_STAGE: begin + if (shuffle_en) + write_fsm_state_ns = arc_WR_STAGE_WR_MEM ? WR_MEM : + arc_WR_STAGE_WR_BUF ? WR_BUF : + // arc_WR_STAGE_WR_WAIT? WR_WAIT : + arc_WR_STAGE_IDLE ? WR_IDLE : WR_STAGE; + else + write_fsm_state_ns = arc_WR_STAGE_WR_MEM ? WR_MEM : + arc_WR_STAGE_WR_BUF ? WR_BUF : + arc_WR_STAGE_WR_WAIT? WR_WAIT : + arc_WR_STAGE_IDLE ? WR_IDLE : WR_STAGE; + rst_wr_addr = 1'b1; + rst_wr_valid_count = 1'b1; + buf_wr_rst_count_intt = gs_mode; + buf_rd_rst_count_intt = gs_mode; + rst_pw_addr = pwo_mode; + end + WR_BUF: begin + write_fsm_state_ns = arc_WR_BUF_WR_MEM ? WR_MEM : WR_BUF; + buf_wren_intt = butterfly_ready; + buf_rden_intt = buf0_valid; + incr_mem_wr_addr = buf0_valid; + mem_wr_en_fsm = buf0_valid; + wr_addr_step = INTT_WRITE_ADDR_STEP; + end + WR_MEM: begin + write_fsm_state_ns = arc_WR_MEM_WR_BUF ? WR_BUF : + arc_WR_MEM_WR_STAGE ? WR_STAGE : + arc_WR_MEM_WR_WAIT ? WR_WAIT : WR_MEM; + buf_wren_intt = gs_mode | pwm_intt_mode ; + buf_rden_intt = gs_mode | pwm_intt_mode ; + incr_mem_wr_addr = ct_mode ? butterfly_ready : (gs_mode | pwm_intt_mode) ? 1'b1 : 1'b0; + mem_wr_en_fsm = ct_mode ? butterfly_ready : (gs_mode | pwm_intt_mode) ? 1'b1 : 1'b0; + wr_addr_step = ct_mode ? NTT_WRITE_ADDR_STEP : INTT_WRITE_ADDR_STEP; + incr_pw_wr_addr = pwo_mode & butterfly_ready; + pw_wren_fsm = pwo_mode & butterfly_ready; + end + WR_WAIT: begin + if (shuffle_en) begin + write_fsm_state_ns = arc_WR_WAIT_WR_STAGE ? WR_STAGE : WR_WAIT; + wr_addr_step = (gs_mode | pwm_intt_mode) ? INTT_WRITE_ADDR_STEP : NTT_WRITE_ADDR_STEP; + end + else begin + write_fsm_state_ns = arc_WR_WAIT_WR_STAGE ? WR_STAGE : arc_WR_WAIT_WR_MEM ? WR_MEM : WR_WAIT; + wr_addr_step = INTT_WRITE_ADDR_STEP; + end + buf_wren_intt = shuffle_en ? 'b0 : (buf_count <= 'h3); + buf_rden_intt = shuffle_en ? (gs_mode | pwm_intt_mode) : 'b1; + incr_mem_wr_addr = (ct_mode | gs_mode | pwm_intt_mode); + mem_wr_en_fsm = shuffle_en ? (gs_mode | pwm_intt_mode) : (ct_mode | gs_mode | pwm_intt_mode); //TODO: clean up with (!shuffle_en & ct) | gs | pwm_intt + + incr_pw_wr_addr = shuffle_en ? pwo_mode & arc_WR_WAIT_WR_STAGE : arc_WR_WAIT_WR_MEM; + pw_wren_fsm = shuffle_en ? 'b0 : arc_WR_WAIT_WR_MEM; + end + default: begin + write_fsm_state_ns = WR_IDLE; + end + endcase +end + +always_comb begin + rst_rounds = (read_fsm_state_ps == RD_IDLE) && (write_fsm_state_ps == WR_IDLE); + incr_rounds = arc_WR_MEM_WR_STAGE | arc_WR_WAIT_WR_STAGE; //TODO: revisit for high-perf mode (if we go with above opt) + if (shuffle_en) begin + buf_wren = pwo_mode ? 1'b0 : buf_wren_ntt_reg | buf_wren_intt_reg; + buf_rden = pwo_mode ? 1'b0 : ct_mode ? buf_rden_ntt_reg : buf_rden_intt; + bf_enable = (gs_mode | pwm_intt_mode | pwo_mode) ? bf_enable_reg_d2 : bf_enable_reg; //bf_enable_fsm; //In gs mode, memory is directly feeding bf2x2, so we need to enable it one cycle later + mem_wr_en = (gs_mode | pwm_intt_mode) ? mem_wr_en_fsm : mem_wr_en_reg; + mem_rd_en = (gs_mode | pwm_intt_mode | pwo_mode) ? mem_rd_en_reg : mem_rd_en_fsm; + twiddle_addr = (gs_mode | pwm_intt_mode) ? twiddle_addr_reg_d3 : twiddle_addr_int; //TODO check latency in pwm_intt mode + pw_rden = pw_rden_reg; + pw_wren = pwm_mode ? pw_wren_reg : pw_wren_reg; + end + else begin + buf_wren = pwo_mode ? 1'b0 : buf_wren_ntt_reg | buf_wren_intt; + buf_rden = pwo_mode ? 1'b0 : buf_rden_ntt | buf_rden_intt; + bf_enable = (gs_mode | pwm_intt_mode | pwo_mode) ? bf_enable_reg : bf_enable_fsm; //In gs mode, memory is directly feeding bf2x2, so we need to enable it one cycle later + mem_wr_en = mem_wr_en_fsm; + mem_rd_en = mem_rd_en_fsm; + twiddle_addr = twiddle_addr_int; + pw_rden = pw_rden_fsm; + pw_wren = pw_wren_fsm; + end + buf_wr_rst_count = pwo_mode ? 1'b1 : buf_wr_rst_count_ntt | buf_wr_rst_count_intt; + buf_rd_rst_count = pwo_mode ? 1'b1 : buf_rd_rst_count_ntt | buf_rd_rst_count_intt; + + +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buf_wren_ntt_reg <= 'b0; + buf_wren_intt_reg <= 'b0; + buf_rden_ntt_reg <= 'b0; + bf_enable_reg <= 'b0; + bf_enable_reg_d2 <= 'b0; + mem_wr_en_reg <= 'b0; + mem_rd_en_reg <= 'b0; + twiddle_addr_reg_d2 <= 'h0; + twiddle_addr_reg_d3 <= 'h0; + pw_rden_reg <= '0; + pw_wren_reg <= '0; + end + else if (zeroize) begin + buf_wren_ntt_reg <= 'b0; + buf_wren_intt_reg <= 'b0; + buf_rden_ntt_reg <= 'b0; + bf_enable_reg <= 'b0; + bf_enable_reg_d2 <= 'b0; + mem_wr_en_reg <= 'b0; + mem_rd_en_reg <= 'b0; + twiddle_addr_reg_d2 <= 'h0; + twiddle_addr_reg_d3 <= 'h0; + pw_rden_reg <= '0; + pw_wren_reg <= '0; + end + else begin + buf_wren_ntt_reg <= buf_wren_ntt; + buf_wren_intt_reg <= buf_wren_intt; + buf_rden_ntt_reg <= buf_rden_ntt; + bf_enable_reg <= bf_enable_fsm; + bf_enable_reg_d2 <= bf_enable_reg; + mem_wr_en_reg <= mem_wr_en_fsm; + mem_rd_en_reg <= mem_rd_en_fsm; + twiddle_addr_reg_d2 <= twiddle_addr_int; + twiddle_addr_reg_d3 <= twiddle_addr_reg_d2; + pw_rden_reg <= pw_rden_fsm; + pw_wren_reg <= pw_wren_fsm; + end +end + + + +//TODO: add assertions for: +//1. buf_wren_ntt and buf_wren_intt should be mutex + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..9e86be7a3394959160fc2fc9928e7f78c8a284cf --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_defines_pkg.sv @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// ntt_defines_pkg.sv +// -------- +// NTT interface parameters for the digital signature algorithm (DSA). +// +// +//====================================================================== + +`ifndef MLDSA_NTT_DEFINES +`define MLDSA_NTT_DEFINES + +package ntt_defines_pkg; + import mldsa_params_pkg::*; + +parameter NTT_REG_SIZE = REG_SIZE-1; +parameter MASKED_WIDTH = 46; +// parameter MEM_DEPTH = 2**MLDSA_MEM_ADDR_WIDTH; + +//---------------------- +//Latency params for NTT +//---------------------- +parameter INTT_WRBUF_LATENCY = 13; +parameter UNMASKED_BF_LATENCY = 10; //5 cycles per butterfly * 2 instances in serial = 10 clks +parameter UNMASKED_PWM_LATENCY = 5; //latency of modular multiplier + modular addition to perform accumulation +parameter UNMASKED_PWA_LATENCY = 1; //latency of modular addition +parameter UNMASKED_PWS_LATENCY = 1; //latency of modular subtraction +parameter UNMASKED_BF_STAGE1_LATENCY = UNMASKED_BF_LATENCY/2; + +parameter MASKED_PWM_LATENCY = 211; //For 1 masked pwm operation +parameter MASKED_BF_STAGE1_LATENCY = 266; //For 1 masked butterfly operation +parameter MASKED_PWM_MASKED_INTT_LATENCY = MASKED_PWM_LATENCY + MASKED_BF_STAGE1_LATENCY; //PWM+stage1 INTT latency +parameter MASKED_INTT_LATENCY = MASKED_BF_STAGE1_LATENCY + UNMASKED_BF_STAGE1_LATENCY; //masked INTT latency +parameter MASKED_PWM_INTT_LATENCY = MASKED_PWM_LATENCY + MASKED_INTT_LATENCY + 1; //TODO: adjust for PWMA case. Adding 1 cyc as a placeholder for it +parameter MASKED_ADD_SUB_LATENCY = 53; //For 1 masked add/sub operation +parameter MASKED_INTT_WRBUF_LATENCY = MASKED_PWM_LATENCY + MASKED_INTT_LATENCY + 3; //masked PWM+INTT latency + mem latency for shuffled reads to begin (does not include PWMA case) + +// typedef enum logic [2:0] {ct, gs, pwm, pwa, pws} mode_t; +//TODO: tb has issue with enums in top level ports. For now, using this workaround +//Need to try something like bundling enable and mode into a struct to support enum. +localparam ct =3'd0, + gs =3'd1, + pwm=3'd2, + pwa=3'd3, + pws=3'd4, + pwm_intt = 3'd5; + +typedef logic [2:0] mode_t; + +//NTT ports +typedef struct packed { + logic [NTT_REG_SIZE-1:0] u00_i; + logic [NTT_REG_SIZE-1:0] u01_i; + logic [NTT_REG_SIZE-1:0] v00_i; + logic [NTT_REG_SIZE-1:0] v01_i; + logic [NTT_REG_SIZE-1:0] w00_i; + logic [NTT_REG_SIZE-1:0] w01_i; + logic [NTT_REG_SIZE-1:0] w10_i; + logic [NTT_REG_SIZE-1:0] w11_i; +} bf_uvwi_t; + +typedef struct packed { + //input a + logic [NTT_REG_SIZE-1:0] u0_i; + logic [NTT_REG_SIZE-1:0] u1_i; + logic [NTT_REG_SIZE-1:0] u2_i; + logic [NTT_REG_SIZE-1:0] u3_i; + //input b + logic [NTT_REG_SIZE-1:0] v0_i; + logic [NTT_REG_SIZE-1:0] v1_i; + logic [NTT_REG_SIZE-1:0] v2_i; + logic [NTT_REG_SIZE-1:0] v3_i; + //accumulated input c (comes from dest mem) + logic [NTT_REG_SIZE-1:0] w0_i; + logic [NTT_REG_SIZE-1:0] w1_i; + logic [NTT_REG_SIZE-1:0] w2_i; + logic [NTT_REG_SIZE-1:0] w3_i; + //input w for INTT operation that follows pwm. TODO: for only PWM/PWMA ops, this needs to be 0 + logic [NTT_REG_SIZE-1:0] twiddle_w0_i; + logic [NTT_REG_SIZE-1:0] twiddle_w1_i; + logic [NTT_REG_SIZE-1:0] twiddle_w2_i; + logic [NTT_REG_SIZE-1:0] twiddle_w3_i; +} hybrid_bf_uvwi_t; + +typedef struct packed { + logic [NTT_REG_SIZE-1:0] u20_o; + logic [NTT_REG_SIZE-1:0] u21_o; + logic [NTT_REG_SIZE-1:0] v20_o; + logic [NTT_REG_SIZE-1:0] v21_o; +} bf_uvo_t; + +typedef struct packed { + logic [1:0][MASKED_WIDTH-1:0] u00_i; + logic [1:0][MASKED_WIDTH-1:0] u01_i; + logic [1:0][MASKED_WIDTH-1:0] v00_i; + logic [1:0][MASKED_WIDTH-1:0] v01_i; + logic [1:0][MASKED_WIDTH-1:0] w00_i; + logic [1:0][MASKED_WIDTH-1:0] w01_i; +} masked_bf_uvwi_t; //Only used in masked INTT stage 1 + +typedef struct packed { + logic [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] interim_base_addr; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr; +} ntt_mem_addr_t; + +typedef struct packed { + logic [MLDSA_MEM_ADDR_WIDTH-1:0] pw_base_addr_a; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] pw_base_addr_b; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] pw_base_addr_c; +} pwo_mem_addr_t; + +//PWO ports +typedef struct packed { + //input a + logic [NTT_REG_SIZE-1:0] u0_i; + logic [NTT_REG_SIZE-1:0] u1_i; + logic [NTT_REG_SIZE-1:0] u2_i; + logic [NTT_REG_SIZE-1:0] u3_i; + //input b + logic [NTT_REG_SIZE-1:0] v0_i; + logic [NTT_REG_SIZE-1:0] v1_i; + logic [NTT_REG_SIZE-1:0] v2_i; + logic [NTT_REG_SIZE-1:0] v3_i; + //accumulated input c (comes from dest mem) + logic [NTT_REG_SIZE-1:0] w0_i; + logic [NTT_REG_SIZE-1:0] w1_i; + logic [NTT_REG_SIZE-1:0] w2_i; + logic [NTT_REG_SIZE-1:0] w3_i; +} pwo_uvwi_t; + +typedef struct packed { + logic [NTT_REG_SIZE-1:0] uv0; + logic [NTT_REG_SIZE-1:0] uv1; + logic [NTT_REG_SIZE-1:0] uv2; + logic [NTT_REG_SIZE-1:0] uv3; +} pwo_t; + +typedef enum logic [2:0] {RD_IDLE, RD_STAGE, RD_BUF, RD_EXEC, EXEC_WAIT} ntt_read_state_t; +typedef enum logic [2:0] {WR_IDLE, WR_STAGE, WR_BUF, WR_MEM, WR_WAIT} ntt_write_state_t; + +endpackage + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_div2.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_div2.sv new file mode 100644 index 0000000000000000000000000000000000000000..2376eb4f259103058172260b5def429be1e9b4f0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_div2.sv @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_div2.sv +// -------- +// This unit performs division by 2 on butterfly outputs +//====================================================================== + +module ntt_div2 + #( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_Q_DIV2_ODD = (MLDSA_Q + 1) / 2 + ) + ( + input wire [REG_SIZE-1:0] op_i, + output logic [REG_SIZE-1:0] res_o + ); + + //No need to perform reduction for the addition here. + //If op_i = Q-1 (which is max even value allowed), op_i >> 1 is less than Q. + //If op_i = Q-2 (which is max odd value allowed), (op_i >> 1) + DIITHIUM_Q_DIV2_ODD is also less than Q. + always_comb res_o = op_i[0] ? (op_i >> 1) + MLDSA_Q_DIV2_ODD + : REG_SIZE'(op_i >> 1); + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv new file mode 100644 index 0000000000000000000000000000000000000000..f73356cd06247d66134bd60d21566b35da84da26 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv @@ -0,0 +1,467 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_hybrid_butterfly_2x2.sv +// -------- +// This module consists of masked PWMs, followed by 1st stage of masked and unmasked BFUs followed by +// 2nd stage of unmasked BFUs. In case of masking_en, PWMs are triggered and +// masked branch is taken for computing 1st stage outputs. In case of unmasked operation, +// both branches are enabled but unmasked outputs are passed to next stage. Final outputs are 23-bit values + +module ntt_hybrid_butterfly_2x2 + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; +#( + parameter WIDTH = 46, + parameter HALF_WIDTH = WIDTH/2 +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + + input mode_t mode, + input wire enable, + input wire masking_en, + input bf_uvwi_t uvw_i, //Inputs are original form + input pwo_uvwi_t pw_uvw_i, //PWO inputs are original form + input hybrid_bf_uvwi_t hybrid_pw_uvw_i, //PWM+INTT inputs. TODO: combine and mux with pwo inputs? + input wire [4:0][WIDTH-1:0] rnd_i, + input wire accumulate, + + output bf_uvo_t uv_o, //Outputs are original form + output pwo_t pwo_uv_o, + output logic ready_o +); + +//---------------------- +//Unmasked wires +//---------------------- +//Inputs to 1st stage +logic [HALF_WIDTH-1:0] u00, u01, v00, v01; +logic [HALF_WIDTH-1:0] w00, w01, w10, w11; +//Outputs of 1st stage +logic [HALF_WIDTH-1:0] u10_int, u11_int, v10_int, v11_int; +//Inputs to 2nd stage +logic [HALF_WIDTH-1:0] u10, u11, v10, v11; +//Outputs of 2nd stage +// logic [HALF_WIDTH-1:0] u20, u21, v20, v21; +logic masking_en_reg; + +//Other internal wires +logic [UNMASKED_BF_STAGE1_LATENCY-1:0][HALF_WIDTH-1:0] w10_reg, w11_reg; //Shift w10 by 5 cycles to match 1st stage BF latency +// logic [MASKED_PWM_LATENCY-1:0][HALF_WIDTH-1:0] masked_w00_reg, masked_w01_reg; +logic [MASKED_BF_STAGE1_LATENCY-1:0][HALF_WIDTH-1:0] masked_w10_reg, masked_w11_reg; +logic pwo_mode, pwm_intt_mode; +// logic [UNMASKED_BF_LATENCY-1:0] ready_reg; +logic [MASKED_PWM_INTT_LATENCY-1:0] masked_ready_reg; + +//Shares - TODO replace with struct? +logic [1:0][WIDTH-1:0] u00_share, u01_share, v00_share, v01_share, u10_share, v10_share, u11_share, v11_share; +logic [1:0][WIDTH-1:0] w00_share, w01_share, w10_share, w11_share; //, w10_reg_share, w11_reg_share; +logic [1:0][WIDTH-1:0] uv00_share, uv01_share, uv10_share, uv11_share; +logic [1:0][WIDTH-1:0] uv00_share_reg, uv01_share_reg, uv10_share_reg, uv11_share_reg; +logic [1:0][WIDTH-1:0] twiddle_w00_share, twiddle_w01_share; +bf_uvo_t masked_gs_stage1_uvo; + +//w delay flops +//Flop the twiddle factor 5x to correctly pass in values to the 2nd set of bf units +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + w10_reg <= 'h0; + w11_reg <= 'h0; + masking_en_reg <= 'b0; + end + else if (zeroize) begin + w10_reg <= 'h0; + w11_reg <= 'h0; + masking_en_reg <= 'b0; + end + else begin + w10_reg <= {uvw_i.w10_i, w10_reg[UNMASKED_BF_STAGE1_LATENCY-1:1]}; + w11_reg <= {uvw_i.w11_i, w11_reg[UNMASKED_BF_STAGE1_LATENCY-1:1]}; + masking_en_reg <= masking_en; + end +end + +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + masked_w10_reg <= 'h0; + end + else if (zeroize) begin + masked_w10_reg <= 'h0; + end + else begin + masked_w10_reg <= {hybrid_pw_uvw_i.twiddle_w2_i, masked_w10_reg[MASKED_BF_STAGE1_LATENCY-1:1]}; + end +end + +assign masked_w11_reg = masked_w10_reg; //used only in masked INTT, both are equal, so can opt num of flops + +assign pwo_mode = (mode inside {pwm, pwa, pws}); +assign pwm_intt_mode = (mode == pwm_intt) & masking_en; + +//Input assignments - TODO: add input flops for u, v, w, and rnd? +always_comb begin + if (pwo_mode) begin + u00 = pw_uvw_i.u0_i; + v00 = pw_uvw_i.v0_i; + w00 = pw_uvw_i.w0_i; + + u01 = pw_uvw_i.u1_i; + v01 = pw_uvw_i.v1_i; + w01 = pw_uvw_i.w1_i; + + u10 = pw_uvw_i.u2_i; + v10 = pw_uvw_i.v2_i; + w10 = pw_uvw_i.w2_i; + + u11 = pw_uvw_i.u3_i; + v11 = pw_uvw_i.v3_i; + w11 = pw_uvw_i.w3_i; + + end + else if (pwm_intt_mode) begin //TODO: clean up + u00 = hybrid_pw_uvw_i.u0_i; + v00 = hybrid_pw_uvw_i.v0_i; + w00 = hybrid_pw_uvw_i.w0_i; + + u01 = hybrid_pw_uvw_i.u1_i; + v01 = hybrid_pw_uvw_i.v1_i; + w01 = hybrid_pw_uvw_i.w1_i; + + u10 = hybrid_pw_uvw_i.u2_i; + v10 = hybrid_pw_uvw_i.v2_i; + w10 = hybrid_pw_uvw_i.w2_i; + + u11 = hybrid_pw_uvw_i.u3_i; + v11 = hybrid_pw_uvw_i.v3_i; + w11 = hybrid_pw_uvw_i.w3_i; + end + else begin //Only applies to unmasked ops since in masking, intt receives inputs from pwm and not from the API + u00 = uvw_i.u00_i; + v00 = uvw_i.v00_i; + w00 = uvw_i.w00_i; + + u01 = uvw_i.u01_i; + v01 = uvw_i.v01_i; + w01 = uvw_i.w01_i; + + u10 = u10_int; + v10 = v10_int; + w10 = w10_reg[0]; + + u11 = u11_int; + v11 = v11_int; + w11 = w11_reg[0]; + end +end + +//Split into shares +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < 2; i++) begin + u00_share[i] <= 'h0; + u01_share[i] <= 'h0; + u10_share[i] <= 'h0; + u11_share[i] <= 'h0; + + v00_share[i] <= 'h0; + v01_share[i] <= 'h0; + v10_share[i] <= 'h0; + v11_share[i] <= 'h0; + + w00_share[i] <= 'h0; + w01_share[i] <= 'h0; + w10_share[i] <= 'h0; + w11_share[i] <= 'h0; + + twiddle_w00_share[i] <= 'h0; + twiddle_w01_share[i] <= 'h0; + end + end + else if (zeroize) begin + for (int i = 0; i < 2; i++) begin + u00_share[i] <= 'h0; + u01_share[i] <= 'h0; + u10_share[i] <= 'h0; + u11_share[i] <= 'h0; + + v00_share[i] <= 'h0; + v01_share[i] <= 'h0; + v10_share[i] <= 'h0; + v11_share[i] <= 'h0; + + w00_share[i] <= 'h0; + w01_share[i] <= 'h0; + w10_share[i] <= 'h0; + w11_share[i] <= 'h0; + + twiddle_w00_share[i] <= 'h0; + twiddle_w01_share[i] <= 'h0; + end + end + else begin + //Split u inputs + u00_share[0] <= WIDTH'(u00) - rnd_i[0]; + u00_share[1] <= rnd_i[0]; + + u01_share[0] <= WIDTH'(u01) - rnd_i[0]; + u01_share[1] <= rnd_i[0]; + + u10_share[0] <= WIDTH'(u10) - rnd_i[0]; + u10_share[1] <= rnd_i[0]; + + u11_share[0] <= WIDTH'(u11) - rnd_i[0]; + u11_share[1] <= rnd_i[0]; + + //Split v inputs + v00_share[0] <= WIDTH'(v00) - rnd_i[1]; + v00_share[1] <= rnd_i[1]; + + v01_share[0] <= WIDTH'(v01) - rnd_i[1]; + v01_share[1] <= rnd_i[1]; + + v10_share[0] <= WIDTH'(v10) - rnd_i[1]; + v10_share[1] <= rnd_i[1]; + + v11_share[0] <= WIDTH'(v11) - rnd_i[1]; + v11_share[1] <= rnd_i[1]; + + //Split w inputs + w00_share[0] <= WIDTH'(w00) - rnd_i[2]; + w00_share[1] <= rnd_i[2]; + + w01_share[0] <= WIDTH'(w01) - rnd_i[2]; + w01_share[1] <= rnd_i[2]; + + w10_share[0] <= WIDTH'(w10) - rnd_i[2]; + w10_share[1] <= rnd_i[2]; + + w11_share[0] <= WIDTH'(w11) - rnd_i[2]; + w11_share[1] <= rnd_i[2]; + + twiddle_w00_share[0] <= WIDTH'(hybrid_pw_uvw_i.twiddle_w0_i) - rnd_i[3]; + twiddle_w00_share[1] <= rnd_i[3]; + + twiddle_w01_share[0] <= WIDTH'(hybrid_pw_uvw_i.twiddle_w1_i) - rnd_i[3]; + twiddle_w01_share[1] <= rnd_i[3]; + end +end + +//---------------------------------------------------- +//Masked PWMs - Used in masked PWM+INTT mode only - 210 clks +//---------------------------------------------------- +ntt_masked_pwm #( + .WIDTH(WIDTH) +) pwm_inst00 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .accumulate(accumulate), + .u(u00_share), + .v(v00_share), + .w(w00_share), + .rnd({rnd_i[4], rnd_i[3], rnd_i[2], rnd_i[1], rnd_i[0]}), + .res(uv00_share) +); + +ntt_masked_pwm #( + .WIDTH(WIDTH) +) pwm_inst01 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .accumulate(accumulate), + .u(u01_share), + .v(v01_share), + .w(w01_share), + .rnd({rnd_i[0], rnd_i[4], rnd_i[3], rnd_i[2], rnd_i[1]}), + .res(uv01_share) +); + +ntt_masked_pwm #( + .WIDTH(WIDTH) +) pwm_inst10 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .accumulate(accumulate), + .u(u10_share), + .v(v10_share), + .w(w10_share), + .rnd({rnd_i[1], rnd_i[0], rnd_i[4], rnd_i[3], rnd_i[2]}), + .res(uv10_share) +); + +ntt_masked_pwm #( + .WIDTH(WIDTH) +) pwm_inst11 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .accumulate(accumulate), + .u(u11_share), + .v(v11_share), + .w(w11_share), + .rnd({rnd_i[2], rnd_i[1], rnd_i[0], rnd_i[4], rnd_i[3]}), + .res(uv11_share) +); + +//--------------------------- +//Refresh randomness +//--------------------------- +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < 2; i++) begin + uv00_share_reg[i] <= 'h0; + uv01_share_reg[i] <= 'h0; + uv10_share_reg[i] <= 'h0; + uv11_share_reg[i] <= 'h0; + end + end + else if (zeroize) begin + for (int i = 0; i < 2; i++) begin + uv00_share_reg[i] <= 'h0; + uv01_share_reg[i] <= 'h0; + uv10_share_reg[i] <= 'h0; + uv11_share_reg[i] <= 'h0; + end + end + else begin + uv00_share_reg[0] <= uv00_share[0] - rnd_i[0]; + uv01_share_reg[0] <= uv01_share[0] - rnd_i[1]; + uv10_share_reg[0] <= uv10_share[0] - rnd_i[2]; + uv11_share_reg[0] <= uv11_share[0] - rnd_i[3]; + + uv00_share_reg[1] <= uv00_share[1] + rnd_i[0]; + uv01_share_reg[1] <= uv01_share[1] + rnd_i[1]; + uv10_share_reg[1] <= uv10_share[1] + rnd_i[2]; + uv11_share_reg[1] <= uv11_share[1] + rnd_i[3]; + end +end + +//---------------------------------------------------- +//Masked BFU stage 1 - Used in masked PWM+INTT mode only - 264 clks +//PWM outputs: uv00[1:0], uv01[1:0], uv10[1:0], uv11[1:0] +//---------------------------------------------------- +ntt_masked_butterfly1x2 #( + .WIDTH(WIDTH) +) masked_bf_1x2_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .uvw_i({uv00_share_reg, uv10_share_reg, uv01_share_reg, uv11_share_reg, twiddle_w00_share, twiddle_w01_share}), + .rnd_i({rnd_i[4], rnd_i[3], rnd_i[2], rnd_i[1], rnd_i[0]}), + .uv_o(masked_gs_stage1_uvo) +); + +//---------------------------------------------------- +//Unmasked BFU stage 1 - Used in all other modes +//---------------------------------------------------- +ntt_butterfly #( + .REG_SIZE(HALF_WIDTH) +) unmasked_bf_inst00 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .opu_i((masking_en & pwm_intt_mode) ? HALF_WIDTH'(0) : u00), + .opv_i((masking_en & pwm_intt_mode) ? HALF_WIDTH'(0) : v00), + .opw_i((masking_en & pwm_intt_mode) ? HALF_WIDTH'(0) : w00), + .accumulate(accumulate), + .u_o(u10_int), + .v_o(u11_int), + .pwm_res_o(pwo_uv_o.uv0) +); + +ntt_butterfly #( + .REG_SIZE(HALF_WIDTH) +) unmasked_bf_inst01 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .opu_i((masking_en & pwm_intt_mode) ? HALF_WIDTH'(0) : u01), + .opv_i((masking_en & pwm_intt_mode) ? HALF_WIDTH'(0) : v01), + .opw_i((masking_en & pwm_intt_mode) ? HALF_WIDTH'(0) : w01), + .accumulate(accumulate), + .u_o(v10_int), + .v_o(v11_int), + .pwm_res_o(pwo_uv_o.uv1) +); + +//---------------------------------------------------- +//Unmasked BFU stage 2 - Used in all modes (irrespective of masking_en) +//---------------------------------------------------- +ntt_butterfly #( + .REG_SIZE(HALF_WIDTH) +) unmasked_bf_inst10 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode((masking_en & pwm_intt_mode) ? gs : mode), + .opu_i((masking_en & pwm_intt_mode) ? masked_gs_stage1_uvo.u20_o : u10), + .opv_i((masking_en & pwm_intt_mode) ? masked_gs_stage1_uvo.v20_o : v10), + .opw_i((masking_en & pwm_intt_mode) ? masked_w10_reg[0] : pwo_mode ? w10 : w10_reg[0]), + .accumulate(accumulate), + .u_o(uv_o.u20_o), + .v_o(uv_o.v20_o), + .pwm_res_o(pwo_uv_o.uv2) +); + +ntt_butterfly #( + .REG_SIZE(HALF_WIDTH) +) unmasked_bf_inst11 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode((masking_en & pwm_intt_mode) ? gs : mode), + .opu_i((masking_en & pwm_intt_mode) ? masked_gs_stage1_uvo.u21_o : u11), + .opv_i((masking_en & pwm_intt_mode) ? masked_gs_stage1_uvo.v21_o : v11), + .opw_i((masking_en & pwm_intt_mode) ? masked_w11_reg[0] : pwo_mode ? w11 : w11_reg[0]), + .accumulate(accumulate), + .u_o(uv_o.u21_o), + .v_o(uv_o.v21_o), + .pwm_res_o(pwo_uv_o.uv3) +); + +//---------------------------------------------------- +//Determine when results are ready +//---------------------------------------------------- +//ready_o logic +always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + masked_ready_reg <= 'b0; + else if (zeroize) + masked_ready_reg <= 'b0; + else begin + unique case(mode) //471:0 delay flop for enable - TODO: optimize + ct: masked_ready_reg <= {{(MASKED_PWM_INTT_LATENCY-UNMASKED_BF_LATENCY){1'b0}}, enable, masked_ready_reg[UNMASKED_BF_LATENCY-1:1]}; + gs: masked_ready_reg <= {{(MASKED_PWM_INTT_LATENCY-UNMASKED_BF_LATENCY){1'b0}}, enable, masked_ready_reg[UNMASKED_BF_LATENCY-1:1]}; + pwm: masked_ready_reg <= accumulate ? {{(MASKED_PWM_INTT_LATENCY-UNMASKED_PWM_LATENCY){1'b0}}, enable, masked_ready_reg[UNMASKED_PWM_LATENCY-1:1]} : {6'h0, enable, masked_ready_reg[UNMASKED_PWM_LATENCY-2:1]}; + pwm_intt: masked_ready_reg <= accumulate ? {enable, masked_ready_reg[MASKED_PWM_INTT_LATENCY-1:1]} : {1'b0, enable, masked_ready_reg[MASKED_PWM_INTT_LATENCY-2:1]}; //TODO revisit + pwa: masked_ready_reg <= {{MASKED_PWM_INTT_LATENCY-1{1'b0}}, enable}; + pws: masked_ready_reg <= {{MASKED_PWM_INTT_LATENCY-1{1'b0}}, enable}; + default: masked_ready_reg <= 'h0; + endcase + end +end + +assign ready_o = masked_ready_reg[0]; + + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv new file mode 100644 index 0000000000000000000000000000000000000000..91b7b4e9de86b0018e86f087e7a41e842a88cc68 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_BFU_adder - total end-to-end latency = 53 clks +//====================================================================== + +module ntt_masked_BFU_add_sub + import ntt_defines_pkg::*; + import mldsa_params_pkg::*; +#( + parameter WIDTH = 46, + parameter HALF_WIDTH = WIDTH/2, + parameter ROLLER = WIDTH'(2**13-1) +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + input wire sub, + input wire [1:0][WIDTH-1:0] u, + input wire [1:0][WIDTH-1:0] v, + input wire [WIDTH-1:0] rnd0, rnd1, rnd2, rnd3, + output logic [1:0] res [WIDTH-1:0] +); + + //Internal signals + logic [1:0][WIDTH-1:0] v_int, add_res; + logic [WIDTH+4:0][1:0][WIDTH-1:0] add_res_reg; //TODO parameterize + logic [1:0] add_res_rolled [WIDTH-1:0]; + logic [1:0] add_res_bool [WIDTH-1:0]; + logic [1:0] add_res_arith [WIDTH-1:0]; + logic [WIDTH-1:0] prime0, prime1, add_res_rolled0, add_res_rolled1; + logic [1:0][WIDTH-1:0] add_res_reduced, prime_packed; + logic [1:0] prime [WIDTH-1:0]; + logic [WIDTH-1:0] add_res_bool0, add_res_bool1, add_res_arith0, add_res_arith1; + + //Add flops to inputs to avoid pruning TODO + always_comb begin + if (sub) begin + v_int[0] = MLDSA_Q - v[0]; + v_int[1] = (~v[1] + 'h1); + end + else begin + v_int[0] = v[0]; + v_int[1] = v[1]; + end + end + + //Perform addition on input shares - 1 clk latency + abr_masked_N_bit_Arith_adder #( + .WIDTH(WIDTH) + ) masked_adder_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .x(u), + .y(v_int), + .s(add_res) + ); + + //Adder delay flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i <= WIDTH+4; i++) begin + add_res_reg[i] <= 'h0; + end + end + else if (zeroize) begin + for (int i = 0; i <= WIDTH+4; i++) begin + add_res_reg[i] <= 'h0; + end + end + else begin + add_res_reg <= {add_res, add_res_reg[WIDTH+4:1]}; + end + end + + //maskedAdder + reduction: + always_comb begin + add_res_rolled0 = add_res[0] + ROLLER; + add_res_rolled1 = add_res[1]; + for (int i = 0; i < WIDTH; i++) begin + add_res_rolled[i][0] = add_res_rolled0[i]; + add_res_rolled[i][1] = add_res_rolled1[i]; + end + end + + //Takes 48 clks + abr_masked_A2B_conv #( + .WIDTH(WIDTH) + ) a2b_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .x(add_res_rolled), + .rnd(rnd1), + .rnd_for_Boolean0(rnd2), + .rnd_for_Boolean1(rnd3), + .s(add_res_bool) + ); + + logic [1:0] temp0 [WIDTH-1:0]; + + //Convert 1 bit to 46 bit to pass to B2A converter - 1 clk + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < WIDTH; i++) begin + temp0[i] <= 2'b0; + end + end + else if (zeroize) begin + for (int i = 0; i < WIDTH; i++) begin + temp0[i] <= 2'b0; + end + end + else begin + for (int i = 0; i < WIDTH; i++) begin + if (i==0) begin + temp0[i] <= {add_res_bool[HALF_WIDTH][1], add_res_bool[HALF_WIDTH][0]}; + end + else begin + temp0[i] <= '0; + end + end + end + end + + //Convert 24th bit to arithmetic domain - 2 clks + abr_masked_B2A_conv #( + .WIDTH(WIDTH) + ) b2a_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .rnd(rnd0), + .x_boolean(temp0), + .x_arith(add_res_arith) + ); + + //Organize wires for easier use and debug + always_comb begin + for(int i = 0; i< WIDTH; i++) begin + add_res_bool0[i] = add_res_bool[i][0]; + add_res_bool1[i] = add_res_bool[i][1]; + add_res_arith0[i] = add_res_arith[i][0]; + add_res_arith1[i] = add_res_arith[i][1]; + end + + //If bit[23] = 1, subtract Q from adder result + prime0 = WIDTH'(add_res_arith0 * (~MLDSA_Q+'h1)); + prime1 = WIDTH'(add_res_arith1 * (~MLDSA_Q+'h1)); + prime_packed[0] = prime0; + prime_packed[1] = prime1; + add_res_reduced[0] = add_res_reg[0][0]+prime_packed[0]; + add_res_reduced[1] = add_res_reg[0][1]+prime_packed[1]; + end + + //Output flop - 1 clk + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < WIDTH; i++) + res[i] <= 2'h0; + end + else if (zeroize) begin + for (int i = 0; i < WIDTH; i++) + res[i] <= 2'h0; + end + else begin + for (int i = 0; i < WIDTH; i++) begin + res[i] <= {add_res_reduced[1][i],add_res_reduced[0][i]}; + end + end + end + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_BFU_mult.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_BFU_mult.sv new file mode 100644 index 0000000000000000000000000000000000000000..c4ccbaf0ba836aff070fc760786ec87df2a0de0a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_BFU_mult.sv @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_BFU_mult +// Performs two share multiplication and reduction - total latency = 210 clks +//====================================================================== + +module ntt_masked_BFU_mult + import ntt_defines_pkg::*; + import mldsa_params_pkg::*; +#( + parameter WIDTH = 46, + parameter HALF_WIDTH = WIDTH/2, + parameter ROLLER = WIDTH'(2**13-1) +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + input wire [1:0][WIDTH-1:0] u, + input wire [1:0][WIDTH-1:0] v, + input wire [WIDTH-1:0] rnd0, rnd1, rnd2, rnd3, rnd4, + output logic [1:0] res [WIDTH-1:0] +); + + //Internal signals + logic [1:0] mul_res [WIDTH-1:0]; + logic [WIDTH-1:0] mul_res0, mul_res1, mul_res_combined, mul_res_combined_share0; + logic [1:0] mul_res_refresh [WIDTH-1:0]; + logic [1:0] mul_res_bool [WIDTH-1:0]; + logic [WIDTH-1:0] mul_res_bool0, mul_res_bool1; + logic [1:0][WIDTH-1:0] temp, final_res; + logic [1:0] mul_res_bool_reduced [HALF_WIDTH-1:0]; + logic [1:0] mul_res_bool_reduced_padded [WIDTH-1:0]; + logic [1:0] mul_res_reduced [WIDTH-1:0]; + logic [WIDTH-1:0] mul_res_bool_redux0, mul_res_bool_redux1, mul_res_redux0, mul_res_redux1; + + //Perform mul on input shares - 2 clk + abr_masked_N_bit_mult_two_share #( + .WIDTH(WIDTH) + ) masked_two_share_mult_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .random(rnd0), + .x(u), + .y(v), + .z(mul_res) + ); + + always_comb begin + for(int i = 0; i < WIDTH; i++) begin + mul_res0[i] = mul_res[i][0]; + mul_res1[i] = mul_res[i][1]; + end + mul_res_combined = (mul_res0 + mul_res1) % MLDSA_Q; + mul_res_combined_share0 = mul_res_combined - rnd0; + for (int i = 0; i < WIDTH; i++) begin + mul_res_refresh[i][0] = mul_res_combined_share0[i]; + mul_res_refresh[i][1] = rnd0[i]; + end + end + + //48 clks + abr_masked_A2B_conv #( + .WIDTH(WIDTH) + ) a2b_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .x(mul_res), + .rnd(rnd1), + .rnd_for_Boolean0(rnd2), + .rnd_for_Boolean1(rnd3), + .s(mul_res_bool) + ); + + //Mult reduction46 - 157 clks + ntt_masked_mult_redux46 #( + .WIDTH(WIDTH) + ) mult_redux46_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .rnd0_11(rnd0[10:0]), + .rnd1_11(rnd0[21:11]), + .rnd2_11(rnd0[32:22]), + .rnd0_12(rnd0[44:33]), + .rnd0_4(rnd1[3:0]), + .rnd0_14(rnd1[17:4]), + .rnd_3WIDTH({rnd4[HALF_WIDTH-1:0], rnd3[HALF_WIDTH-1:0], rnd2[HALF_WIDTH-1:0]}), + .x(mul_res_bool), + .y(mul_res_bool_reduced) + ); + + always_comb begin + for (int i = 0; i < HALF_WIDTH; i++) begin + mul_res_bool_reduced_padded[i][0] = mul_res_bool_reduced[i][0]; + mul_res_bool_reduced_padded[i][1] = mul_res_bool_reduced[i][1]; + end + for (int i = HALF_WIDTH; i < WIDTH; i++) begin + mul_res_bool_reduced_padded[i] = 2'b00; + end + end + + //B2A - 2 clks + abr_masked_B2A_conv #( + .WIDTH(WIDTH) + ) b2a_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .rnd(rnd0), + .x_boolean(mul_res_bool_reduced_padded), + .x_arith(mul_res_reduced) + ); + + always_comb begin + + for (int i = 0; i < WIDTH; i++) begin + mul_res_redux0[i] = mul_res_reduced[i][0]; + mul_res_redux1[i] = mul_res_reduced[i][1]; + end + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < WIDTH; i++) + res[i] <= 2'h0; + end + else if (zeroize) begin + for (int i = 0; i < WIDTH; i++) + res[i] <= 2'h0; + end + else begin + res <= mul_res_reduced; + end + end + + always_comb begin + for ( int i = 0; i < WIDTH; i++) begin + final_res[0][i] = res[i][0]; + final_res[1][i] = res[i][1]; + end + + end + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv new file mode 100644 index 0000000000000000000000000000000000000000..b1caca8e4f318123b21702e4826940cfc780b151 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// ntt_masked_butterfly1x2.sv +// -------- +// 1. Performs 1st stage of masked INTT operation +// 2. Combines output shares +// 3. Performs div2 on combined outputs (unmasked) +// Total latency = 264 clks + +module ntt_masked_butterfly1x2 + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; + #( + parameter WIDTH = 46, + parameter HALF_WIDTH = WIDTH/2 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + // input wire enable, + input masked_bf_uvwi_t uvw_i, + input [4:0][WIDTH-1:0] rnd_i, + + output bf_uvo_t uv_o + ); + + logic [1:0][WIDTH-1:0] u00, v00, w00; + logic [1:0][WIDTH-1:0] u01, v01, w01; + logic [1:0] u10_int [WIDTH-1:0]; + logic [1:0] v10_int [WIDTH-1:0]; + logic [1:0] u11_int [WIDTH-1:0]; + logic [1:0] v11_int [WIDTH-1:0]; + logic [1:0][WIDTH-1:0] u10_packed, v10_packed, u11_packed, v11_packed; + logic [HALF_WIDTH-1:0] u10_combined, v10_combined, u11_combined, v11_combined; + logic [HALF_WIDTH-1:0] u10_div2, v10_div2, u11_div2, v11_div2; + + always_comb begin + u00 = uvw_i.u00_i; + v00 = uvw_i.v00_i; + w00 = uvw_i.w00_i; + + u01 = uvw_i.u01_i; + v01 = uvw_i.v01_i; + w01 = uvw_i.w01_i; + end + + //264 + ntt_masked_gs_butterfly #( + .WIDTH(WIDTH) + ) masked_bf_inst00 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .opu_i(u00), + .opv_i(v00), + .opw_i(w00), + .rnd_i({rnd_i[4], rnd_i[3], rnd_i[2], rnd_i[1], rnd_i[0]}), + .u_o(u10_int), + .v_o(v10_int) //TODO: swap outputs here or inputs to 2nd stage? + ); + + ntt_masked_gs_butterfly #( + .WIDTH(WIDTH) + ) masked_bf_inst01 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .opu_i(u01), + .opv_i(v01), + .opw_i(w01), + .rnd_i({rnd_i[0], rnd_i[4], rnd_i[3], rnd_i[2], rnd_i[1]}), + .u_o(u11_int), + .v_o(v11_int) //TODO: swap outputs here or inputs to 2nd stage? + ); + + always_comb begin + for (int i = 0; i < WIDTH; i++) begin + u10_packed[0][i] = u10_int[i][0]; + u10_packed[1][i] = u10_int[i][1]; + u11_packed[0][i] = u11_int[i][0]; + u11_packed[1][i] = u11_int[i][1]; + v10_packed[0][i] = v10_int[i][0]; + v10_packed[1][i] = v10_int[i][1]; + v11_packed[0][i] = v11_int[i][0]; + v11_packed[1][i] = v11_int[i][1]; + end + u10_combined = HALF_WIDTH'(u10_packed[0] + u10_packed[1]); + v10_combined = HALF_WIDTH'(v10_packed[0] + v10_packed[1]); + u11_combined = HALF_WIDTH'(u11_packed[0] + u11_packed[1]); + v11_combined = HALF_WIDTH'(v11_packed[0] + v11_packed[1]); + end + + //Perform div2 on combined outputs + ntt_div2 #( + .REG_SIZE(HALF_WIDTH), + .MLDSA_Q(mldsa_params_pkg::MLDSA_Q) + ) div2_inst0 ( + .op_i(u10_combined), + .res_o(u10_div2) + ); + + ntt_div2 #( + .REG_SIZE(HALF_WIDTH), + .MLDSA_Q(mldsa_params_pkg::MLDSA_Q) + ) div2_inst1 ( + .op_i(v10_combined), + .res_o(v10_div2) + ); + + ntt_div2 #( + .REG_SIZE(HALF_WIDTH), + .MLDSA_Q(mldsa_params_pkg::MLDSA_Q) + ) div2_inst2 ( + .op_i(u11_combined), + .res_o(u11_div2) + ); + + ntt_div2 #( + .REG_SIZE(HALF_WIDTH), + .MLDSA_Q(mldsa_params_pkg::MLDSA_Q) + ) div2_inst3 ( + .op_i(v11_combined), + .res_o(v11_div2) + ); + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + uv_o <= 'h0; + end + else if (zeroize) begin + uv_o <= 'h0; + end + else begin + uv_o.u20_o <= u10_div2; + uv_o.u21_o <= v10_div2; //u11_div2; + uv_o.v20_o <= u11_div2; //v10_div2; + uv_o.v21_o <= v11_div2; + end + end + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv new file mode 100644 index 0000000000000000000000000000000000000000..8c4964b7285db71366414dc3b3a4891477074bc1 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// ntt_masked_gs_butterfly.sv +// -------- +// Only performs gs (INTT) mode of operation. All blocks are masked +// Latency = 264 clks + +module ntt_masked_gs_butterfly + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; + #( + parameter WIDTH = 46 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire [1:0][WIDTH-1:0] opu_i, + input wire [1:0][WIDTH-1:0] opv_i, + input wire [1:0][WIDTH-1:0] opw_i, + input wire [4:0][WIDTH-1:0] rnd_i, + + output logic [1:0] u_o [WIDTH-1:0], //TODO: make packed? + output logic [1:0] v_o [WIDTH-1:0] + ); + + logic [MASKED_ADD_SUB_LATENCY-1:0][1:0][WIDTH-1:0] w_reg; + logic [1:0] add_res [WIDTH-1:0]; + logic [1:0] sub_res [WIDTH-1:0]; + logic [1:0] mul_res [WIDTH-1:0]; + logic [1:0][WIDTH-1:0] sub_res_packed; + + logic [1:0] add_res_reg [WIDTH-1:0]; + logic [WIDTH-1:0] add_res_reg0, add_res_reg1; + + logic [WIDTH-1:0] add_res0, add_res1, mul_res0, mul_res1, u_o_0, u_o_1, v_o_0, v_o_1; + + //53 clks + ntt_masked_BFU_add_sub #( + .WIDTH(WIDTH) + ) add_inst_0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .sub(1'b0), + .u(opu_i), + .v(opv_i), + .rnd0(rnd_i[0]), + .rnd1(rnd_i[1]), + .rnd2(rnd_i[2]), + .rnd3(rnd_i[3]), + .res(add_res) //u+v + ); + + abr_delay_masked_shares #( + .WIDTH(WIDTH), + .N(MASKED_PWM_LATENCY-1) //Inputs to BF multiplier are internal to this block. There's no input flop in the path, so latency is 1 clk less than the mult latency defined in the pkg + ) add_res_delay_inst ( + .clk(clk), + .rst_n(reset_n), + .zeroize(zeroize), + .input_reg(add_res), + .delayed_reg(add_res_reg) + ); + + //53 clks + ntt_masked_BFU_add_sub #( + .WIDTH(WIDTH) + ) sub_inst_0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .sub(1'b1), + .u(opu_i), + .v(opv_i), + .rnd0(rnd_i[1]), //Different rand order + .rnd1(rnd_i[2]), + .rnd2(rnd_i[3]), + .rnd3(rnd_i[0]), + .res(sub_res) //u-v + ); + + always_comb begin + for (int i = 0; i < WIDTH; i++) begin + add_res0[i] = add_res[i][0]; + add_res1[i] = add_res[i][1]; + sub_res_packed[0][i] = sub_res[i][0]; + sub_res_packed[1][i] = sub_res[i][1]; + + add_res_reg0[i] = add_res_reg[i][0]; + add_res_reg1[i] = add_res_reg[i][1]; + end + end + + //w delay flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < MASKED_ADD_SUB_LATENCY; i++) begin + w_reg[i] <= 'h0; + end + end + else if (zeroize) begin + for (int i = 0; i < MASKED_ADD_SUB_LATENCY; i++) begin + w_reg[i] <= 'h0; + end + end + else begin + w_reg <= {opw_i, w_reg[MASKED_ADD_SUB_LATENCY-1:1]}; + end + end + + //210 clks + ntt_masked_BFU_mult #( + .WIDTH(WIDTH) + ) mult_inst_0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .u(sub_res_packed), + .v(w_reg[0]), + .rnd0(rnd_i[2]), + .rnd1(rnd_i[3]), + .rnd2(rnd_i[0]), + .rnd3(rnd_i[1]), + .rnd4(WIDTH'(rnd_i[2]+rnd_i[3])), + .res(mul_res) //(u-v)*w + ); + + always_comb begin + for (int i = 0; i < WIDTH; i++) begin + mul_res0[i] = mul_res[i][0]; + mul_res1[i] = mul_res[i][1]; + end + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + for (int i = 0; i < WIDTH; i++) begin + u_o[i] <= 2'b0; + v_o[i] <= 2'b0; + end + end + else if (zeroize) begin + for (int i = 0; i < WIDTH; i++) begin + u_o[i] <= 2'b0; + v_o[i] <= 2'b0; + end + end + else begin + u_o <= add_res_reg; //div2 done outside 1st stage of butterfly (in 2x2) + v_o <= mul_res; //div2 done outside 1st stage of butterfly (in 2x2) + end + end + + always_comb begin + for (int i = 0; i < WIDTH; i++) begin + u_o_0[i] = u_o[i][0]; + u_o_1[i] = u_o[i][1]; + + v_o_0[i] = v_o[i][0]; + v_o_1[i] = v_o[i][1]; + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_mult_redux46.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_mult_redux46.sv new file mode 100644 index 0000000000000000000000000000000000000000..60275994404ca0ee4f8991fbada01def6ce36209 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_mult_redux46.sv @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_mult_redux46 +// Performs masked multiplication reduction for MLDSA +// It has 157 Cycle Latency +//====================================================================== + +module ntt_masked_mult_redux46 + import ntt_defines_pkg::*; + import mldsa_params_pkg::*; +#( + parameter WIDTH = 46 +) +( + input wire clk, + input wire rst_n, + input wire zeroize, + input wire [10:0] rnd0_11, + input wire [10:0] rnd1_11, + input wire [10:0] rnd2_11, + input wire [11:0] rnd0_12, + input wire [3:0] rnd0_4, + input wire [13:0] rnd0_14, + input wire [3*(WIDTH/2)-1:0] rnd_3WIDTH, + input wire [1:0] x [WIDTH-1:0], + output logic [1:0] y [WIDTH/2-1:0] +); + + // Intermediate wires for the sliced values + logic [4:0] cnt; + logic [1:0] z_45_23 [22:0]; + logic [1:0] z_45_23_delayed [22:0]; + logic [1:0] z_45_33 [13:0]; + logic [1:0] z_45_33_delayed [13:0]; + logic [1:0] z_45_43 [3:0]; + logic [1:0] z_45_43_delayed [3:0]; + logic [1:0] z_45_43_padded_8 [10:0]; + logic [1:0] z_12_0 [12:0]; + logic [1:0] z_12_0_delayed [12:0]; + logic [1:0] z_22_13 [10:0]; + logic [1:0] z_32_23 [10:0]; + logic [1:0] z_42_33 [10:0]; + + logic [1:0] tmp [10:0]; + logic [1:0] tmp_padded [11:0]; + logic [1:0] tmp0 [10:0]; + logic [1:0] tmp0_padded [11:0]; + logic [1:0] c0_11 [11:0]; + logic [1:0] c11_10 [1:0]; + logic [1:0] c11_10_padded_9 [10:0]; + logic [1:0] c11_10_padded_2 [3:0]; + logic [1:0] c9_0 [9:0]; + logic [1:0] c9_0_padded [10:0]; + + logic [1:0] d10_0 [10:0]; + logic [1:0] d22_0 [22:0]; + logic [1:0] d22_0_delayed [22:0]; + + + logic [1:0] f3_0 [3:0]; + logic [1:0] f3_0_padded_10 [13:0]; + logic [1:0] f13_0 [13:0]; + logic [1:0] f13_0_padded_9 [22:0]; + + + logic [1:0] e22_0 [22:0]; + + // Use always_comb block to split x into various z arrays using for loops + always_comb begin + // Counter for z_45_23 + cnt = 0; + for (int i = 23; i <= 45; i = i + 1) begin + z_45_23[cnt] = x[i]; + cnt = cnt + 1; + end + + // Counter for z_45_33 + cnt = 0; + for (int i = 33; i <= 45; i = i + 1) begin + z_45_33[cnt[3:0]] = x[i]; + cnt = cnt + 1; + end + z_45_33[13] = 2'b00; + + // Counter for z_45_43 + cnt = 0; + for (int i = 43; i <= 45; i = i + 1) begin + z_45_43[cnt[1:0]] = x[i]; + z_45_43_padded_8[cnt[3:0]] = x[i]; + cnt = cnt + 1; + end + z_45_43[3] = 2'b00; + z_45_43_padded_8[3] = 2'b00; + for (int i = 0; i < 7; i = i + 1) //i < 8 + z_45_43_padded_8[i+4] = 2'b00; + + // Counter for z_12_0 + cnt = 0; + for (int i = 0; i <= 12; i = i + 1) begin + z_12_0[cnt[3:0]] = x[i]; + cnt = cnt + 1; + end + + // Counter for z_22_13 + cnt = 0; + for (int i = 13; i <= 22; i = i + 1) begin + z_22_13[cnt[3:0]] = x[i]; + cnt = cnt + 1; + end + z_22_13[10] = 2'b00; + + // Counter for z_32_23 + cnt = 0; + for (int i = 23; i <= 32; i = i + 1) begin + z_32_23[cnt[3:0]] = x[i]; + cnt = cnt + 1; + end + z_32_23[10] = 2'b00; + + // Counter for z_42_33 + cnt = 0; + for (int i = 33; i <= 42; i = i + 1) begin + z_42_33[cnt[3:0]] = x[i]; + cnt = cnt + 1; + end + z_42_33[10] = 2'b00; + + cnt = 0; + for (int i = 10; i <= 11; i = i + 1) begin + c11_10[cnt[0]] = c0_11[i]; + c11_10_padded_9[cnt[3:0]] = c0_11[i]; + c11_10_padded_2[cnt[1:0]] = c0_11[i]; + cnt = cnt + 1; + end + c11_10_padded_2[2] = 2'b00; + c11_10_padded_2[3] = 2'b00; + for (int i = 0; i < 9; i = i + 1) + c11_10_padded_9[i+2] = 2'b00; + + cnt = 0; + for (int i = 0; i <= 9; i = i + 1) begin + c9_0[cnt[3:0]] = c0_11[i]; + c9_0_padded[cnt[3:0]] = c0_11[i]; + cnt = cnt + 1; + end + c9_0_padded[10] = 2'b00; + + + for (int i = 0; i < 4; i = i + 1) + f3_0_padded_10[i] = f3_0[i]; + for (int i = 0; i < 10; i = i + 1) + f3_0_padded_10[i+4] = 2'b00; + + for (int i = 0; i < 14; i = i + 1) + f13_0_padded_9[i] = f13_0[i]; + for (int i = 0; i < 9; i = i + 1) + f13_0_padded_9[i+14] = 2'b00; + + for (int i = 0; i < 11; i = i + 1) begin + tmp_padded[i] = tmp[i]; + tmp0_padded[i] = tmp0[i]; + end + tmp_padded[11] = 2'b00; + tmp0_padded[11] = 2'b00; + end + + // Cycle 0 to 12 + abr_masked_N_bit_Boolean_adder #( + .WIDTH(11) + ) bool_adder_22_13_and_32_23 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(z_22_13), + .y(z_32_23), + .rnd(rnd0_11), + .s(tmp) + ); + + // Cycle 0 to 12 + abr_masked_N_bit_Boolean_adder #( + .WIDTH(11) + ) bool_adder_45_43_and_42_33 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(z_42_33), + .y(z_45_43_padded_8), + .rnd(rnd1_11), + .s(tmp0) + ); + + // Cycle 12+1 to 26 + abr_masked_N_bit_Boolean_adder #( + .WIDTH(12) + ) bool_adder_tmp_and_tmp0 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(tmp_padded), + .y(tmp0_padded), + .rnd(rnd0_12), + .s(c0_11) + ); + + + // Cycle 26+1 to 39 + abr_masked_N_bit_Boolean_adder #( + .WIDTH(11) + ) bool_adder_c0_9_and_c11_10 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(c11_10_padded_9), + .y(c9_0_padded), + .rnd(rnd2_11), + .s(d10_0) + ); + + // Cycle 0 to 40 + abr_delay_masked_shares #( + .WIDTH(13), + .N(40) // Delays 36 cycles + ) delay_z12_0 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .input_reg(z_12_0), + .delayed_reg(z_12_0_delayed) + ); + + //28 cycles + ntt_masked_special_adder add_with_conc_d10_and_z12( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .rnd(rnd_3WIDTH), + .d10_0(d10_0), + .z_12_0(z_12_0_delayed), + .res_o_masked(d22_0) + ); + + // Cycle 0 to 26+1 + abr_delay_masked_shares #( + .WIDTH(4), + .N(27) // Delays 36 cycles + ) delay_z_45_43 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .input_reg(z_45_43), + .delayed_reg(z_45_43_delayed) + ); + + // Cycle 26 to 33 + abr_masked_N_bit_Boolean_adder #( + .WIDTH(4) + ) bool_adder_c11_10_and_z_45_43 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(c11_10_padded_2), + .y(z_45_43_delayed), + .rnd(rnd0_4), + .s(f3_0) + ); + + + // Cycle 0 to 33 + abr_delay_masked_shares #( + .WIDTH(14), + .N(33) // Delays 36 cycles + ) delay_z_45_33 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .input_reg(z_45_33), + .delayed_reg(z_45_33_delayed) + ); + + // Cycle 33 to 48 + abr_masked_N_bit_Boolean_adder #( + .WIDTH(14) + ) bool_adder_c11_10_and_z_45_33 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .x(f3_0_padded_10), + .y(z_45_33_delayed), + .rnd(rnd0_14), + .s(f13_0) + ); + + // Cycle 0 to 48+1 + abr_delay_masked_shares #( + .WIDTH(23), + .N(49) // Delays 36 cycles + ) delay_z_45_23 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .input_reg(z_45_23), + .delayed_reg(z_45_23_delayed) + ); + + //54 cycles + abr_masked_add_sub_mod_Boolean mod_adder_z_45_23_and_f13_0 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .rnd(rnd_3WIDTH), + .sub_i (1'b0), + .opa_i_masked(z_45_23_delayed), + .opb_i_masked(f13_0_padded_9), + .res_o_masked(e22_0) + ); + + // Cycle 39 to 94 + abr_delay_masked_shares #( + .WIDTH(23), + .N(35) // Delays 34 cycles + ) delay_d_22_0 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .input_reg(d22_0), + .delayed_reg(d22_0_delayed) + ); + + //54 cycles + abr_masked_add_sub_mod_Boolean mod_adder_d22_0_and_e22_0 ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .rnd(rnd_3WIDTH), + .sub_i (1'b1), + .opa_i_masked(d22_0_delayed), + .opb_i_masked(e22_0), + .res_o_masked(y) + ); + + +endmodule: ntt_masked_mult_redux46 + + + + +// module abr_masked_add_sub_mod_Boolean #( +// parameter WIDTH = 23, +// parameter PRIME = 23'd8380417 +// ) +// ( +// // Clock and reset. +// input wire clk, +// input wire rst_n, +// input wire zeroize, +// input logic [3*WIDTH-1:0] rnd, + +// input wire sub_i, +// input wire [1:0] opa_i_masked [WIDTH-1:0], +// input wire [1:0] opb_i_masked [WIDTH-1:0], +// output logic [1:0] res_o_masked [WIDTH-1:0] +// ); + + +// // The rest of your variables +// logic [1:0] opa_i_masked_padded [WIDTH:0]; +// logic [1:0] opb_i_masked_padded [WIDTH:0]; +// logic [1:0] opa_2_masked_padded [WIDTH:0]; +// logic [1:0] prime [WIDTH:0]; +// logic [1:0] r0_c0 [WIDTH:0]; +// logic [1:0] r1_c1 [WIDTH:0]; +// logic [1:0] r0_c0_delayed [WIDTH:0]; + +// // Reconstruct unmasked inputs and prepare padded masked operands +// always_comb begin +// for (int i = 0; i < WIDTH; i = i + 1) begin +// // Combine the masked shares to get unmasked values +// opa_i_masked_padded[i] = opa_i_masked[i]; +// // Prepare padded masked operands +// if (sub_i) begin +// opb_i_masked_padded[i][0] = opb_i_masked[i][0]; +// opb_i_masked_padded[i][1] = ~opb_i_masked[i][1]; +// prime[i] = {1'b0, PRIME[i]}; +// end +// else begin +// opb_i_masked_padded[i] = opb_i_masked[i]; +// prime[i] = {1'b0, ~PRIME[i]}; +// end + +// end +// // Padded bits +// opa_i_masked_padded[WIDTH] = 2'b00; +// opb_i_masked_padded[WIDTH] = 2'b00; +// prime[WIDTH] = 2'b00; +// end + +// // Assign opa_2_masked_padded after r0_c0 is available +// always_comb begin +// for (int i = 0; i < WIDTH; i = i + 1) begin +// opa_2_masked_padded[i] = r0_c0[i]; +// end +// opa_2_masked_padded[WIDTH] = 2'b00; +// end + +// // Instantiate the masked subtractor +// abr_masked_N_bit_Boolean_sub #( +// .WIDTH(WIDTH+1) +// ) r0_sub_or_add ( +// .clk(clk), +// .rst_n(rst_n), +// .zeroize(zeroize), +// .sub_i(sub_i), +// .x(opa_i_masked_padded), +// .y(opb_i_masked_padded), +// .rnd(rnd[WIDTH:0]), +// .s(r0_c0) +// ); + + +// // Delay the masked outputs +// abr_delay_masked_shares #( +// .WIDTH(WIDTH+1), +// .N(WIDTH+3) // Delays 26 cycles +// ) delay_r0_c0 ( +// .clk(clk), +// .rst_n(rst_n), +// .zeroize(zeroize), +// .input_reg(r0_c0), +// .delayed_reg(r0_c0_delayed) +// ); + + +// // Instantiate the masked adder +// abr_masked_N_bit_Boolean_sub #( +// .WIDTH(WIDTH+1) +// ) r1_sub_or_add ( +// .clk(clk), +// .rst_n(rst_n), +// .zeroize(zeroize), +// .sub_i(~sub_i), +// .x(opa_2_masked_padded), +// .y(prime), +// .rnd(rnd[WIDTH:0]), +// .s(r1_c1) +// ); + +// // Instantiate the masked MUX +// abr_masked_MUX #( +// .WIDTH(WIDTH) +// ) r0_MUX_r0 ( +// .clk(clk), +// .rst_n(rst_n), +// .zeroize(zeroize), +// .sub_i(sub_i), +// .carry0(r0_c0_delayed[WIDTH]), +// .carry1(r1_c1[WIDTH]), +// .r0(r0_c0_delayed[WIDTH-1:0]), +// .r1(r1_c1[WIDTH-1:0]), +// .rnd_xor(rnd[WIDTH*2-1:WIDTH]), +// .rnd_and(rnd[WIDTH*3-1:2*WIDTH]), +// .res_o_masked(res_o_masked) +// ); + +// endmodule + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_pwm.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_pwm.sv new file mode 100644 index 0000000000000000000000000000000000000000..ff934a91cff8f53d9835b680b26d335d1aeff692 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_pwm.sv @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_pwm.sv +// -------- +// This module performs masked pwm operation with or without accumulate +// on input shares. Always performs (u*v)+w (top level needs to drive 0 +// to the w input if not in accumulate mode) +// 210 clks if PWM, 263 clks if PWMA + +module ntt_masked_pwm + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; +#( + parameter WIDTH = 46 +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + input wire accumulate, + input wire [1:0][WIDTH-1:0] u, + input wire [1:0][WIDTH-1:0] v, + input wire [1:0][WIDTH-1:0] w, + input wire [4:0][WIDTH-1:0] rnd, + output logic [1:0][WIDTH-1:0] res +); + + logic [1:0] mul_res [WIDTH-1:0]; + logic [1:0] w_reg [WIDTH-1:0]; + logic [1:0] w_unpacked [WIDTH-1:0]; + logic [1:0][WIDTH-1:0] mul_res_packed, w_reg_packed; + logic [1:0] res_unpacked [WIDTH-1:0]; + + always_comb begin + for (int i = 0; i < WIDTH; i++) begin + w_unpacked[i][0] = w[0][i]; + w_unpacked[i][1] = w[1][i]; + + w_reg_packed[0][i] = 'h0; //w_reg[i][0]; + w_reg_packed[1][i] = 'h0; //w_reg[i][1]; //TODO: fix + + mul_res_packed[0][i] = mul_res[i][0]; + mul_res_packed[1][i] = mul_res[i][1]; + end + end + + //210 clks + ntt_masked_BFU_mult #( + .WIDTH(WIDTH) + ) mult_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .u(u), + .v(v), + .rnd0(rnd[0]), + .rnd1(rnd[1]), + .rnd2(rnd[2]), + .rnd3(rnd[3]), + .rnd4(rnd[4]), + .res(mul_res) + ); + + // //Delay reading addr until after PWM is done to do accumulate + // abr_delay_masked_shares #( + // .WIDTH(WIDTH), + // .N(MASKED_PWM_LATENCY-1) + // ) w_delay ( + // .clk(clk), + // .rst_n(reset_n), + // .zeroize(zeroize), + // .input_reg(w_unpacked), + // .delayed_reg(w_reg) + // ); + + //53 clks (accumulate case) + ntt_masked_BFU_add_sub #( + .WIDTH(WIDTH) + ) add_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .sub(1'b0), + .u(mul_res_packed), + .v(w_reg_packed), + .rnd0(rnd[0]), + .rnd1(rnd[1]), + .rnd2(rnd[2]), + .rnd3(rnd[3]), + .res(res_unpacked) + ); + + always_comb begin + for (int i = 0; i < WIDTH; i++) begin + res[0][i] = accumulate ? res_unpacked[i][0] : mul_res[i][0]; + res[1][i] = accumulate ? res_unpacked[i][1] : mul_res[i][1]; + end + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_special_adder.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_special_adder.sv new file mode 100644 index 0000000000000000000000000000000000000000..f20cb42eb35b93f8d7b485aaafda216bac6a8b9e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_masked_special_adder.sv @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_special_adder.sv +// -------- +// Special modular addtion module to compute opa+-opb % prime +// to be used special multreduction module, but with masking method. +// +// +//====================================================================== + +module ntt_masked_special_adder #( + parameter WIDTH = 23, + parameter WIDTH2 = 11, + parameter WIDTH3 = 13, + parameter PRIME = 23'd8380417 + ) + ( + // Clock and reset. + input wire clk, + input wire rst_n, + input wire zeroize, + input logic [3*WIDTH-1:0] rnd, + + input wire [1:0] d10_0 [WIDTH2-1:0], + input wire [1:0] z_12_0 [WIDTH3-1:0], + output logic [1:0] res_o_masked [WIDTH-1:0] +); + + + logic [1:0] opa_2_masked_padded [WIDTH:0]; + logic [1:0] prime [WIDTH:0]; + logic [1:0] r0_c0 [WIDTH:0]; + logic [1:0] r1_c1 [WIDTH:0]; + logic [1:0] r0_c0_delayed [WIDTH:0]; + + always_comb begin + for (int i = 0; i buffer contains data read from memory before it's consumed by BF2x2 +// INTT mode --> buffer contains data from BF2x2 to be written to memory + +// This buffer is customized to support shuffling countermeasure for NTT. It's an +// addressable buffer with the following attributes: +// NTT mode --> writes to buffer are in order. Starting read addr is randomized +// INTT mode --> Starting write addr is randomized. Reads from buffer are in order + +module ntt_shuffle_buffer + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; + #( + parameter REG_SIZE = 24 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + input mode_t mode, + input wire shuffle_en, + input wire wren, + input wire rden, + input wire [1:0] wrptr, + input wire [1:0] rdptr, + input wire wr_rst_count, + // input wire rd_rst_count, + input wire [(4*REG_SIZE)-1:0] data_i, + output logic buf_valid, + output logic [(4*REG_SIZE)-1:0] data_o + ); + + //buffer*[0] is lo, buffer*[1] is hi + logic [1:0][3:0][3:0][REG_SIZE-1:0] buffer; //2x4x4 buffer [lo_hi][] + + logic [1:0] data_i_count, data_i_count_reg; + logic lo_hi, lo_hi_reg, lo_hi_rd; //0 - lo, 1 - hi + + //Write + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buffer <= 'h0; + end + else if (zeroize) begin + buffer <= 'h0; + end + else if (wren) begin + buffer[lo_hi][wrptr] <= data_i; //4 coeff into lo/hi buf0/1/2/3 based on wrptr + end + end + + //Buffer valid + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + data_i_count <= 'h0; + data_i_count_reg <= 'h0; + end + else if (zeroize) begin + data_i_count <= 'h0; + data_i_count_reg <= 'h0; + end + else if (wr_rst_count) begin + data_i_count <= 'h0; + data_i_count_reg <= 'h0; + end + else if (wren) begin + data_i_count <= data_i_count + 'h1; + data_i_count_reg <= data_i_count; + end + end + + always_comb begin + buf_valid = (data_i_count_reg == 'd3); + lo_hi = buf_valid ^ lo_hi_reg; + lo_hi_rd = (shuffle_en & (mode == 0)) ? lo_hi_reg : lo_hi; //shuffling delays logic by a cycle, so that needs to be accounted for here as well + end + + //lo hi + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + lo_hi_reg <= 'b0; + else if (zeroize) + lo_hi_reg <= 'b0; + else if (buf_valid) + lo_hi_reg <= ~lo_hi_reg; + end + + //assign output + always_comb begin + data_o = '0; + if (lo_hi_rd) begin + data_o = {buffer[0][3][rdptr], buffer[0][2][rdptr], buffer[0][1][rdptr], buffer[0][0][rdptr]}; + end else if (~lo_hi_rd) begin + data_o = {buffer[1][3][rdptr], buffer[1][2][rdptr], buffer[1][1][rdptr], buffer[1][0][rdptr]}; + end + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_special_adder.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_special_adder.sv new file mode 100644 index 0000000000000000000000000000000000000000..d19c5a664a34d5b794b5c8126379b79e059d24e2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_special_adder.sv @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_special_adder.sv +// -------- +// Special modular addtion module to compute opa+-opb % prime +// to be used special multreduction module +// +// +//====================================================================== + +module ntt_special_adder #( + parameter REG_SIZE = 24 + ) + ( + // Clock and reset. + input wire clk, + input wire reset_n, + input wire zeroize, + + // DATA PORT + input wire add_en_i, + input wire [10:0] opa_i, + input wire [12:0] opb_i, + input wire [REG_SIZE-1:0] prime_i, + output logic [REG_SIZE-1:0] res_o, + output logic ready_o +); + + logic [REG_SIZE-1 : 0] opb1; + logic [REG_SIZE-1 : 0] r0; + logic [REG_SIZE-1 : 0] r1; + logic carry0; + + logic [REG_SIZE-1 : 0] r0_reg; + logic carry0_reg; + + logic carry1; + logic [1 : 0] push_result_reg; + + + always_comb {carry0, r0} = {opa_i, opb_i}; + always_comb opb1 = ~prime_i; + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_1( + .a_i(r0_reg), + .b_i(opb1), + .cin_i(1'b1), + .s_o(r1), + .cout_o(carry1) + ); + + always_ff @(posedge clk or negedge reset_n) + begin + if(!reset_n) begin + r0_reg <= '0; + carry0_reg <= '0; + end + else if (zeroize) begin + r0_reg <= '0; + carry0_reg <= '0; + end + else if (add_en_i) begin + r0_reg <= r0; + carry0_reg <= carry0; + end + end + + // Determines when results are ready + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + push_result_reg <= 2'b0; + else if (zeroize) + push_result_reg <= 2'b0; + else if (add_en_i) + push_result_reg <= 2'b10; + else // one shift to right + push_result_reg <= 2'(push_result_reg >> 1); + end + + assign ready_o = push_result_reg[0]; + + assign res_o = (carry0_reg ^ carry1)? r1 : r0_reg; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..c124c5e7b0ccb0497f1535a6c0561cdc662aefd6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_top.sv @@ -0,0 +1,559 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_top.sv +// -------- +// This block does multiple things: +// 1. Keeps track of stages of bf2x2 operation +// 2. Reads appropriate addr of ROM and passes w input to bf2x2 +// 3. Orchestrates memory writes and reads and passes u and v inputs to bf2x2 +// 4. Controls direct PWM inputs to bf2x2 in pwm mode +// 5. Maintains mode input to bf2x2 and related input/output muxes +// 6. Aligns data and control delays associated with bf2x2 module +// The design accounts for 1 cycle read latency from memory +// and adds flops to inputs of the bf2x2 (data and enable) +// In addition to this, data inputs are flopped internal to bf2x2 to balance +// delays between both paths and maintain constant time +//====================================================================== + +module ntt_top + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; +#( + parameter REG_SIZE = 24, + parameter NTT_REG_SIZE = REG_SIZE-1, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_Q_DIV2_ODD = (MLDSA_Q + 1) / 2, + parameter MLDSA_N = 256, + parameter MLDSA_LOGN = $clog2(MLDSA_N), + parameter MEM_ADDR_WIDTH = 15, + parameter MEM_DATA_WIDTH = 4*REG_SIZE, + parameter WIDTH = 46 +) +( + //Clock and reset + input wire clk, + input wire reset_n, + input wire zeroize, + + //Ctrl signal ports + input mode_t mode, + input wire ntt_enable, + + //NTT base addr ports + input ntt_mem_addr_t ntt_mem_base_addr, + + //PWM base addr ports + input pwo_mem_addr_t pwo_mem_base_addr, + + //PWM control + input wire accumulate, + + //Sampler IF + input wire sampler_valid, + + input wire shuffle_en, + input wire masking_en, + input wire [5:0] random, + input wire [4:0][WIDTH-1:0] rnd_i, + + //Memory if + //Reuse between pwm c, ntt + output mem_if_t mem_wr_req, + output mem_if_t mem_rd_req, + output logic [MEM_DATA_WIDTH-1:0] mem_wr_data, + input wire [MEM_DATA_WIDTH-1:0] mem_rd_data, + + //Memory IF for PWM + output mem_if_t pwm_a_rd_req, + output mem_if_t pwm_b_rd_req, + input wire [MEM_DATA_WIDTH-1:0] pwm_a_rd_data, + //Reuse between pwm mem data or sampler data (mux should be outside) + input wire [MEM_DATA_WIDTH-1:0] pwm_b_rd_data, + + output logic ntt_busy, + output logic ntt_done + +); + //NTT mem signals + //Write IF + logic mem_wren, mem_wren_reg, mem_wren_mux; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_wr_addr, mem_wr_addr_reg, mem_wr_addr_mux; + logic [MEM_DATA_WIDTH-1:0] mem_wr_data_int, mem_wr_data_reg, mem_wr_data_reg_d2; + + //Read IF + logic mem_rden; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr; + logic [(4*REG_SIZE)-1:0] mem_rd_data_reg; + + //Butterfly IF signals + bf_uvwi_t uvw_i; + bf_uvo_t uv_o, uv_o_reg; + logic bf_enable, bf_enable_reg, bf_enable_mux; + logic bf_ready; + logic buf0_valid; + + //Internal + logic [6:0] twiddle_addr, twiddle_addr_reg; + logic buf_wren; + logic buf_rden; + logic buf_wr_rst_count, buf_rd_rst_count; + + //buffer IF + logic [(4*REG_SIZE)-1:0] buf_data_i, buf_data_o; + logic [(3*NTT_REG_SIZE)-1:0] twiddle_factor, twiddle_factor_reg; + logic [1:0] buf_wrptr, buf_rdptr; + + //PWM mem IF + pwo_uvwi_t pw_uvw_i; + pwo_t pwo_uv_o; + logic pw_wren, pw_wren_reg; + logic pw_rden, pw_rden_dest_mem; + logic sampler_valid_reg; + logic [MEM_DATA_WIDTH-1:0] pwm_b_rd_data_reg; + //PWM+INTT IF - masking + hybrid_bf_uvwi_t hybrid_pw_uvw_i; + + //Flop ntt_ctrl pwm output wr addr to align with BFU output flop + logic [MLDSA_MEM_ADDR_WIDTH-1:0] pwm_wr_addr_c_reg; + logic [(4*REG_SIZE)-1:0] pwm_wr_data_reg; + + //ntt_ctrl output connections + logic [MLDSA_MEM_ADDR_WIDTH-1:0] pw_mem_wr_addr_c; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] pw_mem_rd_addr_c, pw_mem_rd_addr_a, pw_mem_rd_addr_b; + + //pwm mem data_out connections + logic [(4*REG_SIZE)-1:0] pwm_rd_data_a, pwm_rd_data_b, pwm_rd_data_c; + + //Flop pwm mem data_out before sending to BFU + logic [(4*REG_SIZE)-1:0] pwm_rd_data_a_reg, pwm_rd_data_b_reg, pwm_rd_data_c_reg; + + //Modes + logic ct_mode; + logic gs_mode; + logic pwo_mode; + logic pwm_mode, pwa_mode, pws_mode; + logic pwm_intt_mode; + mode_t opcode; + logic masking_en_ctrl; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + ct_mode <= 0; + gs_mode <= 0; + pwo_mode <= 0; + pwm_mode <= 0; + pwa_mode <= 0; + pws_mode <= 0; + pwm_intt_mode <= 0; + end + else begin + ct_mode <= (mode == ct); + gs_mode <= (mode == gs); + pwo_mode <= (mode inside {pwm, pwa, pws}); + pwm_mode <= (mode == pwm); + pwa_mode <= (mode == pwa); + pws_mode <= (mode == pws); + pwm_intt_mode <= (mode == pwm_intt); + end + end + + assign pw_rden_dest_mem = accumulate ? pw_rden : 1'b0; + + //Mem IF assignments: + //mem wr - NTT/INTT mode, write ntt data. PWO mode, write pwm/a/s data + assign mem_wr_req.rd_wr_en = !pwo_mode ? (mem_wren_mux ? RW_WRITE : RW_IDLE) //TODO convert mem_wren_mux to rw enum + : (pw_wren_reg ? RW_WRITE : RW_IDLE); + assign mem_wr_req.addr = !pwo_mode ? mem_wr_addr_mux : pwm_wr_addr_c_reg; + assign mem_wr_data_int = !pwo_mode ? (ct_mode ? {1'b0, uv_o_reg.v21_o, 1'b0, uv_o_reg.u21_o, 1'b0, uv_o_reg.v20_o, 1'b0, uv_o_reg.u20_o} : buf_data_o) + : pwm_wr_data_reg; + assign mem_wr_data = shuffle_en ? pwm_mode ? mem_wr_data_reg : (pwa_mode | pws_mode) ? mem_wr_data_reg : mem_wr_data_int + : mem_wr_data_int; + + //mem rd - NTT/INTT mode, read ntt data. PWM mode, read accumulate data from c mem. PWA/S mode, unused + assign mem_rd_req.rd_wr_en = (ct_mode | gs_mode | pwm_intt_mode) ? (mem_rden ? RW_READ : RW_IDLE) : pwm_mode ? (pw_rden_dest_mem ? RW_READ : RW_IDLE) : RW_IDLE; + assign mem_rd_req.addr = (ct_mode | gs_mode | pwm_intt_mode) ? mem_rd_addr : pwm_mode ? pw_mem_rd_addr_c : 'h0; + assign pwm_rd_data_c = (pwm_mode && accumulate) ? mem_rd_data : 'h0; //TODO: masked pwm (Ay) mode + + //pwm rd a - PWO mode - read a operand from mem. NTT/INTT mode, not used + assign pwm_a_rd_req.rd_wr_en = (pwo_mode | pwm_intt_mode) ? (pw_rden ? RW_READ : RW_IDLE) : RW_IDLE; + assign pwm_a_rd_req.addr = (pwo_mode | pwm_intt_mode) ? pw_mem_rd_addr_a : 'h0; + assign pwm_rd_data_a = (pwo_mode | pwm_intt_mode) ? pwm_a_rd_data : 'h0; //TODO: clean up mux. Just connect input directly to logic + + //pwm rd b - PWO mode - read b operand from mem. Or operand b can also be connected directly to sampler, so in that case, addr/rden are not used + always_comb begin + if (shuffle_en) begin + pwm_b_rd_req.rd_wr_en = sampler_valid_reg & (pwo_mode | pwm_intt_mode) ? (pw_rden ? RW_READ : RW_IDLE) : RW_IDLE; //pw_rden is delayed a clk due to shuffling, so use delayed sampler_valid to line it up + pwm_b_rd_req.addr = sampler_valid_reg & (pwo_mode | pwm_intt_mode) ? pw_mem_rd_addr_b : 'h0; + pwm_rd_data_b = pwm_b_rd_data_reg; + end + else begin + pwm_b_rd_req.rd_wr_en = sampler_valid & (pwo_mode | pwm_intt_mode) ? (pw_rden ? RW_READ : RW_IDLE) : RW_IDLE; + pwm_b_rd_req.addr = sampler_valid & (pwo_mode | pwm_intt_mode) ? pw_mem_rd_addr_b : 'h0; + pwm_rd_data_b = pwm_b_rd_data; + end + end + + + ntt_ctrl #( + .MEM_ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH) + ) + ntt_ctrl_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .ntt_mode(mode), + .ntt_enable(ntt_enable), + .butterfly_ready(bf_ready), + .buf0_valid(buf0_valid), + .sampler_valid(sampler_valid), + .shuffle_en(shuffle_en), + .random(random), + + .ntt_mem_base_addr(ntt_mem_base_addr), + .pwo_mem_base_addr(pwo_mem_base_addr), + .accumulate(accumulate), + + .bf_enable(bf_enable), + .opcode(opcode), + .masking_en_ctrl(masking_en_ctrl), + .buf_wren(buf_wren), + .buf_rden(buf_rden), + .buf_wrptr(buf_wrptr), + .buf_rdptr(buf_rdptr), + .twiddle_addr(twiddle_addr), + + .mem_rd_addr(mem_rd_addr), + .mem_wr_addr(mem_wr_addr), + .mem_rd_en(mem_rden), + .mem_wr_en(mem_wren), + .buf_wr_rst_count(buf_wr_rst_count), + .buf_rd_rst_count(buf_rd_rst_count), + + .pw_mem_rd_addr_a(pw_mem_rd_addr_a), + .pw_mem_rd_addr_b(pw_mem_rd_addr_b), + .pw_mem_rd_addr_c(pw_mem_rd_addr_c), + .pw_mem_wr_addr_c(pw_mem_wr_addr_c), + .pw_rden(pw_rden), + .pw_wren(pw_wren), + .busy(ntt_busy), + .done(ntt_done) + ); + + //Twiddle lookup + ntt_twiddle_lookup #( + .ADDR_WIDTH(7), + .DATA_WIDTH(NTT_REG_SIZE) + ) w_rom ( + .mode(mode), + .raddr(twiddle_addr), + .rdata(twiddle_factor) + ); + + always_comb begin + unique case(mode) + ct: begin + uvw_i.w00_i = twiddle_factor[NTT_REG_SIZE-1:0]; + uvw_i.w01_i = twiddle_factor[NTT_REG_SIZE-1:0]; + uvw_i.w10_i = twiddle_factor[(2*NTT_REG_SIZE)-1:NTT_REG_SIZE]; + uvw_i.w11_i = twiddle_factor[(3*NTT_REG_SIZE)-1:(2*NTT_REG_SIZE)]; + end + gs, pwm_intt: begin + if (shuffle_en) begin + uvw_i.w11_i = twiddle_factor[(3*NTT_REG_SIZE)-1:(2*NTT_REG_SIZE)]; + uvw_i.w10_i = twiddle_factor[(3*NTT_REG_SIZE)-1:(2*NTT_REG_SIZE)]; + uvw_i.w01_i = twiddle_factor[(2*NTT_REG_SIZE)-1:NTT_REG_SIZE]; + uvw_i.w00_i = twiddle_factor[NTT_REG_SIZE-1:0]; + end + else begin + uvw_i.w11_i = twiddle_factor_reg[(3*NTT_REG_SIZE)-1:(2*NTT_REG_SIZE)]; + uvw_i.w10_i = twiddle_factor_reg[(3*NTT_REG_SIZE)-1:(2*NTT_REG_SIZE)]; + uvw_i.w01_i = twiddle_factor_reg[(2*NTT_REG_SIZE)-1:NTT_REG_SIZE]; + uvw_i.w00_i = twiddle_factor_reg[NTT_REG_SIZE-1:0]; + end + end + default: begin + uvw_i.w11_i = 'h0; + uvw_i.w10_i = 'h0; + uvw_i.w01_i = 'h0; + uvw_i.w00_i = 'h0; + end + endcase + end + + /* + //Butterfly 2x2 + ntt_butterfly2x2 #( + .REG_SIZE(NTT_REG_SIZE), + .MLDSA_Q(MLDSA_Q) + ) + bf2x2 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .enable(bf_enable_mux), + .uvw_i(uvw_i), + .uv_o(uv_o), + .pw_uvw_i(pw_uvw_i), + .accumulate(accumulate), + .pwo_uv_o(pwo_uv_o), + .ready_o(bf_ready) + ); + */ + + ntt_hybrid_butterfly_2x2 #( + .WIDTH(WIDTH) + ) + hybrid_bf2x2 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(opcode), + .enable(bf_enable_mux), + .masking_en(masking_en), + .uvw_i(uvw_i), + .pw_uvw_i(pw_uvw_i), + .hybrid_pw_uvw_i(hybrid_pw_uvw_i), + .rnd_i(rnd_i), + .accumulate(accumulate), + .uv_o(uv_o), + .pwo_uv_o(pwo_uv_o), + .ready_o(bf_ready) + ); + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_rd_data_reg <= 'h0; + bf_enable_reg <= 'b0; + twiddle_addr_reg <= 'h0; + twiddle_factor_reg <= 'h0; + + uv_o_reg <= 'h0; + mem_wren_reg <= 'b0; + mem_wr_addr_reg <= 'h0; + + //pwm + pwm_rd_data_a_reg <= 'h0; + pwm_rd_data_b_reg <= 'h0; + pwm_rd_data_c_reg <= 'h0; + pwm_wr_data_reg <= 'h0; + + pwm_wr_addr_c_reg <= 'h0; + + pw_wren_reg <= 'b0; + mem_wr_data_reg <= 'h0; + mem_wr_data_reg_d2 <= 'h0; + sampler_valid_reg <= 'h0; + pwm_b_rd_data_reg <= 'h0; + + end + else if (zeroize) begin + mem_rd_data_reg <= 'h0; + bf_enable_reg <= 'b0; + twiddle_addr_reg <= 'h0; + twiddle_factor_reg <= 'h0; + + uv_o_reg <= 'h0; + mem_wren_reg <= 'b0; + mem_wr_addr_reg <= 'h0; + + pwm_rd_data_a_reg <= 'h0; + pwm_rd_data_b_reg <= 'h0; + pwm_rd_data_c_reg <= 'h0; + pwm_wr_data_reg <= 'h0; + + pwm_wr_addr_c_reg <= 'h0; + + pw_wren_reg <= 'b0; + mem_wr_data_reg <= 'h0; + mem_wr_data_reg_d2 <= 'h0; + sampler_valid_reg <= 'h0; + pwm_b_rd_data_reg <= 'h0; + end + else begin + mem_rd_data_reg <= mem_rd_data; + bf_enable_reg <= bf_enable; + twiddle_addr_reg <= twiddle_addr; + twiddle_factor_reg <= twiddle_factor; + + uv_o_reg <= uv_o; + mem_wren_reg <= mem_wren; + mem_wr_addr_reg <= mem_wr_addr; + + //pwm + pwm_wr_addr_c_reg <= pw_mem_wr_addr_c; + + pwm_rd_data_a_reg <= pwm_rd_data_a; + pwm_rd_data_b_reg <= pwm_rd_data_b; + pwm_rd_data_c_reg <= pwm_rd_data_c; + pwm_wr_data_reg <= {1'b0, pwo_uv_o.uv3, 1'b0, pwo_uv_o.uv2, 1'b0, pwo_uv_o.uv1, 1'b0, pwo_uv_o.uv0}; + + pw_wren_reg <= pw_wren; + mem_wr_data_reg <= mem_wr_data_int; + mem_wr_data_reg_d2 <= mem_wr_data_reg; + sampler_valid_reg <= sampler_valid; + pwm_b_rd_data_reg <= pwm_b_rd_data; + end + end + + //Buffer (input or output side) + assign buf_data_i = ct_mode ? mem_rd_data : shuffle_en ? {1'b0, uv_o_reg.v21_o, 1'b0, uv_o_reg.v20_o, 1'b0, uv_o_reg.u21_o, 1'b0, uv_o_reg.u20_o} + : {1'b0, uv_o.v21_o, 1'b0, uv_o.v20_o, 1'b0, uv_o.u21_o, 1'b0, uv_o.u20_o}; + + always_comb begin + unique case(opcode) + ct: begin + uvw_i.u00_i = buf_data_o[REG_SIZE-2:0] ; + uvw_i.u01_i = buf_data_o[(2*REG_SIZE)-2:REG_SIZE] ; + uvw_i.v00_i = buf_data_o[(3*REG_SIZE)-2:(2*REG_SIZE)] ; + uvw_i.v01_i = buf_data_o[(4*REG_SIZE)-2:(3*REG_SIZE)] ; + + pw_uvw_i = 'h0; + end + gs: begin + uvw_i.u00_i = mem_rd_data_reg[REG_SIZE-2:0]; + uvw_i.u01_i = mem_rd_data_reg[(3*REG_SIZE)-2:(2*REG_SIZE)]; + uvw_i.v00_i = mem_rd_data_reg[(2*REG_SIZE)-2:REG_SIZE]; + uvw_i.v01_i = mem_rd_data_reg[(4*REG_SIZE)-2:(3*REG_SIZE)]; + + pw_uvw_i = 'h0; + end + pwm, pwm_intt: begin + uvw_i.u00_i = 'h0; + uvw_i.u01_i = 'h0; + uvw_i.v00_i = 'h0; + uvw_i.v01_i = 'h0; + + pw_uvw_i.u0_i = pwm_rd_data_a_reg[REG_SIZE-2:0]; + pw_uvw_i.u1_i = pwm_rd_data_a_reg[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.u2_i = pwm_rd_data_a_reg[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.u3_i = pwm_rd_data_a_reg[(4*REG_SIZE)-2:(3*REG_SIZE)]; + + if (shuffle_en) begin + pw_uvw_i.v0_i = pwm_rd_data_b[REG_SIZE-2:0]; + pw_uvw_i.v1_i = pwm_rd_data_b[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.v2_i = pwm_rd_data_b[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.v3_i = pwm_rd_data_b[(4*REG_SIZE)-2:(3*REG_SIZE)]; + end + else begin + pw_uvw_i.v0_i = pwm_rd_data_b_reg[REG_SIZE-2:0]; + pw_uvw_i.v1_i = pwm_rd_data_b_reg[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.v2_i = pwm_rd_data_b_reg[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.v3_i = pwm_rd_data_b_reg[(4*REG_SIZE)-2:(3*REG_SIZE)]; + end + + pw_uvw_i.w0_i = pwm_rd_data_c_reg[REG_SIZE-2:0]; + pw_uvw_i.w1_i = pwm_rd_data_c_reg[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.w2_i = pwm_rd_data_c_reg[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.w3_i = pwm_rd_data_c_reg[(4*REG_SIZE)-2:(3*REG_SIZE)]; + end + pwa, pws: begin + uvw_i.u00_i = 'h0; + uvw_i.u01_i = 'h0; + uvw_i.v00_i = 'h0; + uvw_i.v01_i = 'h0; + + pw_uvw_i.u0_i = pwm_rd_data_a_reg[REG_SIZE-2:0]; + pw_uvw_i.u1_i = pwm_rd_data_a_reg[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.u2_i = pwm_rd_data_a_reg[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.u3_i = pwm_rd_data_a_reg[(4*REG_SIZE)-2:(3*REG_SIZE)]; + + if (shuffle_en) begin + pw_uvw_i.v0_i = pwm_rd_data_b/*_reg*/[REG_SIZE-2:0]; + pw_uvw_i.v1_i = pwm_rd_data_b/*_reg*/[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.v2_i = pwm_rd_data_b/*_reg*/[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.v3_i = pwm_rd_data_b/*_reg*/[(4*REG_SIZE)-2:(3*REG_SIZE)]; + end + else begin + pw_uvw_i.v0_i = pwm_rd_data_b_reg[REG_SIZE-2:0]; + pw_uvw_i.v1_i = pwm_rd_data_b_reg[(2*REG_SIZE)-2:REG_SIZE]; + pw_uvw_i.v2_i = pwm_rd_data_b_reg[(3*REG_SIZE)-2:(2*REG_SIZE)]; + pw_uvw_i.v3_i = pwm_rd_data_b_reg[(4*REG_SIZE)-2:(3*REG_SIZE)]; + end + + pw_uvw_i.w0_i = 'h0; + pw_uvw_i.w1_i = 'h0; + pw_uvw_i.w2_i = 'h0; + pw_uvw_i.w3_i = 'h0; + end + default: begin + uvw_i.u00_i = 'h0; + uvw_i.u01_i = 'h0; + uvw_i.v00_i = 'h0; + uvw_i.v01_i = 'h0; + + pw_uvw_i.u0_i = 'h0; + pw_uvw_i.u1_i = 'h0; + pw_uvw_i.u2_i = 'h0; + pw_uvw_i.u3_i = 'h0; + + pw_uvw_i.v0_i = 'h0; + pw_uvw_i.v1_i = 'h0; + pw_uvw_i.v2_i = 'h0; + pw_uvw_i.v3_i = 'h0; + + pw_uvw_i.w0_i = 'h0; + pw_uvw_i.w1_i = 'h0; + pw_uvw_i.w2_i = 'h0; + pw_uvw_i.w3_i = 'h0; + end + endcase + end + + always_comb hybrid_pw_uvw_i = {pw_uvw_i, uvw_i.w00_i, uvw_i.w01_i, uvw_i.w10_i, uvw_i.w11_i}; + + assign bf_enable_mux = ct_mode ? bf_enable : bf_enable_reg; + assign mem_wren_mux = ~shuffle_en & ct_mode ? mem_wren_reg : mem_wren; + assign mem_wr_addr_mux = ~shuffle_en & ct_mode ? mem_wr_addr_reg : mem_wr_addr; + + /* + ntt_buffer #( + .REG_SIZE(REG_SIZE) + ) buffer_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .wren(buf_wren), //TODO: review for high-perf mode + .rden(buf_rden), + .wr_rst_count(buf_wr_rst_count), + .rd_rst_count(buf_rd_rst_count), + .mode(mode), + .data_i(buf_data_i), + .buf0_valid(buf0_valid), + .data_o(buf_data_o) + ); + */ + + ntt_shuffle_buffer #( + .REG_SIZE(REG_SIZE) + ) buffer_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .shuffle_en(shuffle_en), + .wren(buf_wren), + .rden(buf_rden), + .wrptr(buf_wrptr), + .rdptr(buf_rdptr), + .wr_rst_count(buf_wr_rst_count), + .data_i(buf_data_i), + .buf_valid(buf0_valid), + .data_o(buf_data_o) + ); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_twiddle_lookup.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_twiddle_lookup.sv new file mode 100644 index 0000000000000000000000000000000000000000..bcfadfb27d830a68735ea616bf640ff99b7d8d67 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/rtl/ntt_twiddle_lookup.sv @@ -0,0 +1,739 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// twiddle_rom.sv +// -------- +// ROM contains twiddle factors for NTT and INTT +// +// +//====================================================================== + +module ntt_twiddle_lookup + import ntt_defines_pkg::*; +#( + parameter ADDR_WIDTH = 7, + parameter DATA_WIDTH = 24 +) +( + + input mode_t mode, + input wire [ADDR_WIDTH-1:0] raddr, + output logic [(3*DATA_WIDTH)-1:0] rdata +); + +reg [(3*DATA_WIDTH)-1:0] ntt_twiddle_mem [84:0]; +reg [(3*DATA_WIDTH)-1:0] intt_twiddle_mem [84:0]; + +always_comb begin + rdata = (mode == ct) ? ntt_twiddle_mem[raddr] : (mode inside {gs, pwm_intt}) ? intt_twiddle_mem[raddr] : 'h0; +end + +logic [255 : 0][(DATA_WIDTH)-1:0] zeta; +logic [255 : 0][(DATA_WIDTH)-1:0] zetainv; + +assign zeta[0] = 23'h000001; +assign zeta[1] = 23'h495E02; +assign zeta[2] = 23'h397567; +assign zeta[3] = 23'h396569; +assign zeta[4] = 23'h4F062B; +assign zeta[5] = 23'h53DF73; +assign zeta[6] = 23'h4FE033; +assign zeta[7] = 23'h4F066B; +assign zeta[8] = 23'h76B1AE; +assign zeta[9] = 23'h360DD5; +assign zeta[10] = 23'h28EDB0; +assign zeta[11] = 23'h207FE4; +assign zeta[12] = 23'h397283; +assign zeta[13] = 23'h70894A; +assign zeta[14] = 23'h088192; +assign zeta[15] = 23'h6D3DC8; +assign zeta[16] = 23'h4C7294; +assign zeta[17] = 23'h41E0B4; +assign zeta[18] = 23'h28A3D2; +assign zeta[19] = 23'h66528A; +assign zeta[20] = 23'h4A18A7; +assign zeta[21] = 23'h794034; +assign zeta[22] = 23'h0A52EE; +assign zeta[23] = 23'h6B7D81; +assign zeta[24] = 23'h4E9F1D; +assign zeta[25] = 23'h1A2877; +assign zeta[26] = 23'h2571DF; +assign zeta[27] = 23'h1649EE; +assign zeta[28] = 23'h7611BD; +assign zeta[29] = 23'h492BB7; +assign zeta[30] = 23'h2AF697; +assign zeta[31] = 23'h22D8D5; +assign zeta[32] = 23'h36F72A; +assign zeta[33] = 23'h30911E; +assign zeta[34] = 23'h29D13F; +assign zeta[35] = 23'h492673; +assign zeta[36] = 23'h50685F; +assign zeta[37] = 23'h2010A2; +assign zeta[38] = 23'h3887F7; +assign zeta[39] = 23'h11B2C3; +assign zeta[40] = 23'h0603A4; +assign zeta[41] = 23'h0E2BED; +assign zeta[42] = 23'h10B72C; +assign zeta[43] = 23'h4A5F35; +assign zeta[44] = 23'h1F9D15; +assign zeta[45] = 23'h428CD4; +assign zeta[46] = 23'h3177F4; +assign zeta[47] = 23'h20E612; +assign zeta[48] = 23'h341C1D; +assign zeta[49] = 23'h1AD873; +assign zeta[50] = 23'h736681; +assign zeta[51] = 23'h49553F; +assign zeta[52] = 23'h3952F6; +assign zeta[53] = 23'h62564A; +assign zeta[54] = 23'h65AD05; +assign zeta[55] = 23'h439A1C; +assign zeta[56] = 23'h53AA5F; +assign zeta[57] = 23'h30B622; +assign zeta[58] = 23'h087F38; +assign zeta[59] = 23'h3B0E6D; +assign zeta[60] = 23'h2C83DA; +assign zeta[61] = 23'h1C496E; +assign zeta[62] = 23'h330E2B; +assign zeta[63] = 23'h1C5B70; +assign zeta[64] = 23'h2EE3F1; +assign zeta[65] = 23'h137EB9; +assign zeta[66] = 23'h57A930; +assign zeta[67] = 23'h3AC6EF; +assign zeta[68] = 23'h3FD54C; +assign zeta[69] = 23'h4EB2EA; +assign zeta[70] = 23'h503EE1; +assign zeta[71] = 23'h7BB175; +assign zeta[72] = 23'h2648B4; +assign zeta[73] = 23'h1EF256; +assign zeta[74] = 23'h1D90A2; +assign zeta[75] = 23'h45A6D4; +assign zeta[76] = 23'h2AE59B; +assign zeta[77] = 23'h52589C; +assign zeta[78] = 23'h6EF1F5; +assign zeta[79] = 23'h3F7288; +assign zeta[80] = 23'h175102; +assign zeta[81] = 23'h075D59; +assign zeta[82] = 23'h1187BA; +assign zeta[83] = 23'h52ACA9; +assign zeta[84] = 23'h773E9E; +assign zeta[85] = 23'h0296D8; +assign zeta[86] = 23'h2592EC; +assign zeta[87] = 23'h4CFF12; +assign zeta[88] = 23'h404CE8; +assign zeta[89] = 23'h4AA582; +assign zeta[90] = 23'h1E54E6; +assign zeta[91] = 23'h4F16C1; +assign zeta[92] = 23'h1A7E79; +assign zeta[93] = 23'h03978F; +assign zeta[94] = 23'h4E4817; +assign zeta[95] = 23'h31B859; +assign zeta[96] = 23'h5884CC; +assign zeta[97] = 23'h1B4827; +assign zeta[98] = 23'h5B63D0; +assign zeta[99] = 23'h5D787A; +assign zeta[100] = 23'h35225E; +assign zeta[101] = 23'h400C7E; +assign zeta[102] = 23'h6C09D1; +assign zeta[103] = 23'h5BD532; +assign zeta[104] = 23'h6BC4D3; +assign zeta[105] = 23'h258ECB; +assign zeta[106] = 23'h2E534C; +assign zeta[107] = 23'h097A6C; +assign zeta[108] = 23'h3B8820; +assign zeta[109] = 23'h6D285C; +assign zeta[110] = 23'h2CA4F8; +assign zeta[111] = 23'h337CAA; +assign zeta[112] = 23'h14B2A0; +assign zeta[113] = 23'h558536; +assign zeta[114] = 23'h28F186; +assign zeta[115] = 23'h55795D; +assign zeta[116] = 23'h4AF670; +assign zeta[117] = 23'h234A86; +assign zeta[118] = 23'h75E826; +assign zeta[119] = 23'h78DE66; +assign zeta[120] = 23'h05528C; +assign zeta[121] = 23'h7ADF59; +assign zeta[122] = 23'h0F6E17; +assign zeta[123] = 23'h5BF3DA; +assign zeta[124] = 23'h459B7E; +assign zeta[125] = 23'h628B34; +assign zeta[126] = 23'h5DBECB; +assign zeta[127] = 23'h1A9E7B; +assign zeta[128] = 23'h0006D9; +assign zeta[129] = 23'h6257C5; +assign zeta[130] = 23'h574B3C; +assign zeta[131] = 23'h69A8EF; +assign zeta[132] = 23'h289838; +assign zeta[133] = 23'h64B5FE; +assign zeta[134] = 23'h7EF8F5; +assign zeta[135] = 23'h2A4E78; +assign zeta[136] = 23'h120A23; +assign zeta[137] = 23'h0154A8; +assign zeta[138] = 23'h09B7FF; +assign zeta[139] = 23'h435E87; +assign zeta[140] = 23'h437FF8; +assign zeta[141] = 23'h5CD5B4; +assign zeta[142] = 23'h4DC04E; +assign zeta[143] = 23'h4728AF; +assign zeta[144] = 23'h7F735D; +assign zeta[145] = 23'h0C8D0D; +assign zeta[146] = 23'h0F66D5; +assign zeta[147] = 23'h5A6D80; +assign zeta[148] = 23'h61AB98; +assign zeta[149] = 23'h185D96; +assign zeta[150] = 23'h437F31; +assign zeta[151] = 23'h468298; +assign zeta[152] = 23'h662960; +assign zeta[153] = 23'h4BD579; +assign zeta[154] = 23'h28DE06; +assign zeta[155] = 23'h465D8D; +assign zeta[156] = 23'h49B0E3; +assign zeta[157] = 23'h09B434; +assign zeta[158] = 23'h7C0DB3; +assign zeta[159] = 23'h5A68B0; +assign zeta[160] = 23'h409BA9; +assign zeta[161] = 23'h64D3D5; +assign zeta[162] = 23'h21762A; +assign zeta[163] = 23'h658591; +assign zeta[164] = 23'h246E39; +assign zeta[165] = 23'h48C39B; +assign zeta[166] = 23'h7BC759; +assign zeta[167] = 23'h4F5859; +assign zeta[168] = 23'h392DB2; +assign zeta[169] = 23'h230923; +assign zeta[170] = 23'h12EB67; +assign zeta[171] = 23'h454DF2; +assign zeta[172] = 23'h30C31C; +assign zeta[173] = 23'h285424; +assign zeta[174] = 23'h13232E; +assign zeta[175] = 23'h7FAF80; +assign zeta[176] = 23'h2DBFCB; +assign zeta[177] = 23'h022A0B; +assign zeta[178] = 23'h7E832C; +assign zeta[179] = 23'h26587A; +assign zeta[180] = 23'h6B3375; +assign zeta[181] = 23'h095B76; +assign zeta[182] = 23'h6BE1CC; +assign zeta[183] = 23'h5E061E; +assign zeta[184] = 23'h78E00D; +assign zeta[185] = 23'h628C37; +assign zeta[186] = 23'h3DA604; +assign zeta[187] = 23'h4AE53C; +assign zeta[188] = 23'h1F1D68; +assign zeta[189] = 23'h6330BB; +assign zeta[190] = 23'h7361B8; +assign zeta[191] = 23'h5EA06C; +assign zeta[192] = 23'h671AC7; +assign zeta[193] = 23'h201FC6; +assign zeta[194] = 23'h5BA4FF; +assign zeta[195] = 23'h60D772; +assign zeta[196] = 23'h08F201; +assign zeta[197] = 23'h6DE024; +assign zeta[198] = 23'h080E6D; +assign zeta[199] = 23'h56038E; +assign zeta[200] = 23'h695688; +assign zeta[201] = 23'h1E6D3E; +assign zeta[202] = 23'h2603BD; +assign zeta[203] = 23'h6A9DFA; +assign zeta[204] = 23'h07C017; +assign zeta[205] = 23'h6DBFD4; +assign zeta[206] = 23'h74D0BD; +assign zeta[207] = 23'h63E1E3; +assign zeta[208] = 23'h519573; +assign zeta[209] = 23'h7AB60D; +assign zeta[210] = 23'h2867BA; +assign zeta[211] = 23'h2DECD4; +assign zeta[212] = 23'h58018C; +assign zeta[213] = 23'h3F4CF5; +assign zeta[214] = 23'h0B7009; +assign zeta[215] = 23'h427E23; +assign zeta[216] = 23'h3CBD37; +assign zeta[217] = 23'h273333; +assign zeta[218] = 23'h673957; +assign zeta[219] = 23'h1A4B5D; +assign zeta[220] = 23'h196926; +assign zeta[221] = 23'h1EF206; +assign zeta[222] = 23'h11C14E; +assign zeta[223] = 23'h4C76C8; +assign zeta[224] = 23'h3CF42F; +assign zeta[225] = 23'h7FB19A; +assign zeta[226] = 23'h6AF66C; +assign zeta[227] = 23'h2E1669; +assign zeta[228] = 23'h3352D6; +assign zeta[229] = 23'h034760; +assign zeta[230] = 23'h085260; +assign zeta[231] = 23'h741E78; +assign zeta[232] = 23'h2F6316; +assign zeta[233] = 23'h6F0A11; +assign zeta[234] = 23'h07C0F1; +assign zeta[235] = 23'h776D0B; +assign zeta[236] = 23'h0D1FF0; +assign zeta[237] = 23'h345824; +assign zeta[238] = 23'h0223D4; +assign zeta[239] = 23'h68C559; +assign zeta[240] = 23'h5E8885; +assign zeta[241] = 23'h2FAA32; +assign zeta[242] = 23'h23FC65; +assign zeta[243] = 23'h5E6942; +assign zeta[244] = 23'h51E0ED; +assign zeta[245] = 23'h65ADB3; +assign zeta[246] = 23'h2CA5E6; +assign zeta[247] = 23'h79E1FE; +assign zeta[248] = 23'h7B4064; +assign zeta[249] = 23'h35E1DD; +assign zeta[250] = 23'h433AAC; +assign zeta[251] = 23'h464ADE; +assign zeta[252] = 23'h1CFE14; +assign zeta[253] = 23'h73F1CE; +assign zeta[254] = 23'h10170E; +assign zeta[255] = 23'h74B6D7; + +//------------------------------------------------------------------------------------ + + +assign zetainv[0] = 23'h7FE000; +assign zetainv[1] = 23'h3681FF; +assign zetainv[2] = 23'h466A9A; +assign zetainv[3] = 23'h467A98; +assign zetainv[4] = 23'h30D9D6; +assign zetainv[5] = 23'h2C008E; +assign zetainv[6] = 23'h2FFFCE; +assign zetainv[7] = 23'h30D996; +assign zetainv[8] = 23'h092E53; +assign zetainv[9] = 23'h49D22C; +assign zetainv[10] = 23'h56F251; +assign zetainv[11] = 23'h5F601D; +assign zetainv[12] = 23'h466D7E; +assign zetainv[13] = 23'h0F56B7; +assign zetainv[14] = 23'h775E6F; +assign zetainv[15] = 23'h12A239; +assign zetainv[16] = 23'h336D6D; +assign zetainv[17] = 23'h3DFF4D; +assign zetainv[18] = 23'h573C2F; +assign zetainv[19] = 23'h198D77; +assign zetainv[20] = 23'h35C75A; +assign zetainv[21] = 23'h069FCD; +assign zetainv[22] = 23'h758D13; +assign zetainv[23] = 23'h146280; +assign zetainv[24] = 23'h3140E4; +assign zetainv[25] = 23'h65B78A; +assign zetainv[26] = 23'h5A6E22; +assign zetainv[27] = 23'h699613; +assign zetainv[28] = 23'h09CE44; +assign zetainv[29] = 23'h36B44A; +assign zetainv[30] = 23'h54E96A; +assign zetainv[31] = 23'h5D072C; +assign zetainv[32] = 23'h48E8D7; +assign zetainv[33] = 23'h4F4EE3; +assign zetainv[34] = 23'h560EC2; +assign zetainv[35] = 23'h36B98E; +assign zetainv[36] = 23'h2F77A2; +assign zetainv[37] = 23'h5FCF5F; +assign zetainv[38] = 23'h47580A; +assign zetainv[39] = 23'h6E2D3E; +assign zetainv[40] = 23'h79DC5D; +assign zetainv[41] = 23'h71B414; +assign zetainv[42] = 23'h6F28D5; +assign zetainv[43] = 23'h3580CC; +assign zetainv[44] = 23'h6042EC; +assign zetainv[45] = 23'h3D532D; +assign zetainv[46] = 23'h4E680D; +assign zetainv[47] = 23'h5EF9EF; +assign zetainv[48] = 23'h4BC3E4; +assign zetainv[49] = 23'h65078E; +assign zetainv[50] = 23'h0C7980; +assign zetainv[51] = 23'h368AC2; +assign zetainv[52] = 23'h468D0B; +assign zetainv[53] = 23'h1D89B7; +assign zetainv[54] = 23'h1A32FC; +assign zetainv[55] = 23'h3C45E5; +assign zetainv[56] = 23'h2C35A2; +assign zetainv[57] = 23'h4F29DF; +assign zetainv[58] = 23'h7760C9; +assign zetainv[59] = 23'h44D194; +assign zetainv[60] = 23'h535C27; +assign zetainv[61] = 23'h639693; +assign zetainv[62] = 23'h4CD1D6; +assign zetainv[63] = 23'h638491; +assign zetainv[64] = 23'h50FC10; +assign zetainv[65] = 23'h6C6148; +assign zetainv[66] = 23'h2836D1; +assign zetainv[67] = 23'h451912; +assign zetainv[68] = 23'h400AB5; +assign zetainv[69] = 23'h312D17; +assign zetainv[70] = 23'h2FA120; +assign zetainv[71] = 23'h042E8C; +assign zetainv[72] = 23'h59974D; +assign zetainv[73] = 23'h60EDAB; +assign zetainv[74] = 23'h624F5F; +assign zetainv[75] = 23'h3A392D; +assign zetainv[76] = 23'h54FA66; +assign zetainv[77] = 23'h2D8765; +assign zetainv[78] = 23'h10EE0C; +assign zetainv[79] = 23'h406D79; +assign zetainv[80] = 23'h688EFF; +assign zetainv[81] = 23'h7882A8; +assign zetainv[82] = 23'h6E5847; +assign zetainv[83] = 23'h2D3358; +assign zetainv[84] = 23'h08A163; +assign zetainv[85] = 23'h7D4929; +assign zetainv[86] = 23'h5A4D15; +assign zetainv[87] = 23'h32E0EF; +assign zetainv[88] = 23'h3F9319; +assign zetainv[89] = 23'h353A7F; +assign zetainv[90] = 23'h618B1B; +assign zetainv[91] = 23'h30C940; +assign zetainv[92] = 23'h656188; +assign zetainv[93] = 23'h7C4872; +assign zetainv[94] = 23'h3197EA; +assign zetainv[95] = 23'h4E27A8; +assign zetainv[96] = 23'h275B35; +assign zetainv[97] = 23'h6497DA; +assign zetainv[98] = 23'h247C31; +assign zetainv[99] = 23'h226787; +assign zetainv[100] = 23'h4ABDA3; +assign zetainv[101] = 23'h3FD383; +assign zetainv[102] = 23'h13D630; +assign zetainv[103] = 23'h240ACF; +assign zetainv[104] = 23'h141B2E; +assign zetainv[105] = 23'h5A5136; +assign zetainv[106] = 23'h518CB5; +assign zetainv[107] = 23'h766595; +assign zetainv[108] = 23'h4457E1; +assign zetainv[109] = 23'h12B7A5; +assign zetainv[110] = 23'h533B09; +assign zetainv[111] = 23'h4C6357; +assign zetainv[112] = 23'h6B2D61; +assign zetainv[113] = 23'h2A5ACB; +assign zetainv[114] = 23'h56EE7B; +assign zetainv[115] = 23'h2A66A4; +assign zetainv[116] = 23'h34E991; +assign zetainv[117] = 23'h5C957B; +assign zetainv[118] = 23'h09F7DB; +assign zetainv[119] = 23'h07019B; +assign zetainv[120] = 23'h7A8D75; +assign zetainv[121] = 23'h0500A8; +assign zetainv[122] = 23'h7071EA; +assign zetainv[123] = 23'h23EC27; +assign zetainv[124] = 23'h3A4483; +assign zetainv[125] = 23'h1D54CD; +assign zetainv[126] = 23'h222136; +assign zetainv[127] = 23'h654186; +assign zetainv[128] = 23'h7FD928; +assign zetainv[129] = 23'h1D883C; +assign zetainv[130] = 23'h2894C5; +assign zetainv[131] = 23'h163712; +assign zetainv[132] = 23'h5747C9; +assign zetainv[133] = 23'h1B2A03; +assign zetainv[134] = 23'h00E70C; +assign zetainv[135] = 23'h559189; +assign zetainv[136] = 23'h6DD5DE; +assign zetainv[137] = 23'h7E8B59; +assign zetainv[138] = 23'h762802; +assign zetainv[139] = 23'h3C817A; +assign zetainv[140] = 23'h3C6009; +assign zetainv[141] = 23'h230A4D; +assign zetainv[142] = 23'h321FB3; +assign zetainv[143] = 23'h38B752; +assign zetainv[144] = 23'h006CA4; +assign zetainv[145] = 23'h7352F4; +assign zetainv[146] = 23'h70792C; +assign zetainv[147] = 23'h257281; +assign zetainv[148] = 23'h1E3469; +assign zetainv[149] = 23'h67826B; +assign zetainv[150] = 23'h3C60D0; +assign zetainv[151] = 23'h395D69; +assign zetainv[152] = 23'h19B6A1; +assign zetainv[153] = 23'h340A88; +assign zetainv[154] = 23'h5701FB; +assign zetainv[155] = 23'h398274; +assign zetainv[156] = 23'h362F1E; +assign zetainv[157] = 23'h762BCD; +assign zetainv[158] = 23'h03D24E; +assign zetainv[159] = 23'h257751; +assign zetainv[160] = 23'h3F4458; +assign zetainv[161] = 23'h1B0C2C; +assign zetainv[162] = 23'h5E69D7; +assign zetainv[163] = 23'h1A5A70; +assign zetainv[164] = 23'h5B71C8; +assign zetainv[165] = 23'h371C66; +assign zetainv[166] = 23'h0418A8; +assign zetainv[167] = 23'h3087A8; +assign zetainv[168] = 23'h46B24F; +assign zetainv[169] = 23'h5CD6DE; +assign zetainv[170] = 23'h6CF49A; +assign zetainv[171] = 23'h3A920F; +assign zetainv[172] = 23'h4F1CE5; +assign zetainv[173] = 23'h578BDD; +assign zetainv[174] = 23'h6CBCD3; +assign zetainv[175] = 23'h003081; +assign zetainv[176] = 23'h522036; +assign zetainv[177] = 23'h7DB5F6; +assign zetainv[178] = 23'h015CD5; +assign zetainv[179] = 23'h598787; +assign zetainv[180] = 23'h14AC8C; +assign zetainv[181] = 23'h76848B; +assign zetainv[182] = 23'h13FE35; +assign zetainv[183] = 23'h21D9E3; +assign zetainv[184] = 23'h06FFF4; +assign zetainv[185] = 23'h1D53CA; +assign zetainv[186] = 23'h4239FD; +assign zetainv[187] = 23'h34FAC5; +assign zetainv[188] = 23'h60C299; +assign zetainv[189] = 23'h1CAF46; +assign zetainv[190] = 23'h0C7E49; +assign zetainv[191] = 23'h213F95; +assign zetainv[192] = 23'h18C53A; +assign zetainv[193] = 23'h5FC03B; +assign zetainv[194] = 23'h243B02; +assign zetainv[195] = 23'h1F088F; +assign zetainv[196] = 23'h76EE00; +assign zetainv[197] = 23'h11FFDD; +assign zetainv[198] = 23'h77D194; +assign zetainv[199] = 23'h29DC73; +assign zetainv[200] = 23'h168979; +assign zetainv[201] = 23'h6172C3; +assign zetainv[202] = 23'h59DC44; +assign zetainv[203] = 23'h154207; +assign zetainv[204] = 23'h781FEA; +assign zetainv[205] = 23'h12202D; +assign zetainv[206] = 23'h0B0F44; +assign zetainv[207] = 23'h1BFE1E; +assign zetainv[208] = 23'h2E4A8E; +assign zetainv[209] = 23'h0529F4; +assign zetainv[210] = 23'h577847; +assign zetainv[211] = 23'h51F32D; +assign zetainv[212] = 23'h27DE75; +assign zetainv[213] = 23'h40930C; +assign zetainv[214] = 23'h746FF8; +assign zetainv[215] = 23'h3D61DE; +assign zetainv[216] = 23'h4322CA; +assign zetainv[217] = 23'h58ACCE; +assign zetainv[218] = 23'h18A6AA; +assign zetainv[219] = 23'h6594A4; +assign zetainv[220] = 23'h6676DB; +assign zetainv[221] = 23'h60EDFB; +assign zetainv[222] = 23'h6E1EB3; +assign zetainv[223] = 23'h336939; +assign zetainv[224] = 23'h42EBD2; +assign zetainv[225] = 23'h002E67; +assign zetainv[226] = 23'h14E995; +assign zetainv[227] = 23'h51C998; +assign zetainv[228] = 23'h4C8D2B; +assign zetainv[229] = 23'h7C98A1; +assign zetainv[230] = 23'h778DA1; +assign zetainv[231] = 23'h0BC189; +assign zetainv[232] = 23'h507CEB; +assign zetainv[233] = 23'h10D5F0; +assign zetainv[234] = 23'h781F10; +assign zetainv[235] = 23'h0872F6; +assign zetainv[236] = 23'h72C011; +assign zetainv[237] = 23'h4B87DD; +assign zetainv[238] = 23'h7DBC2D; +assign zetainv[239] = 23'h171AA8; +assign zetainv[240] = 23'h21577C; +assign zetainv[241] = 23'h5035CF; +assign zetainv[242] = 23'h5BE39C; +assign zetainv[243] = 23'h2176BF; +assign zetainv[244] = 23'h2DFF14; +assign zetainv[245] = 23'h1A324E; +assign zetainv[246] = 23'h533A1B; +assign zetainv[247] = 23'h05FE03; +assign zetainv[248] = 23'h049F9D; +assign zetainv[249] = 23'h49FE24; +assign zetainv[250] = 23'h3CA555; +assign zetainv[251] = 23'h399523; +assign zetainv[252] = 23'h62E1ED; +assign zetainv[253] = 23'h0BEE33; +assign zetainv[254] = 23'h6FC8F3; +assign zetainv[255] = 23'h0B292A; + +// assign ntt_twiddle_mem[0] = 'h000001; +assign ntt_twiddle_mem[0] = {zeta[3], zeta[2], zeta[1]}; +assign ntt_twiddle_mem[1] = {zeta[9], zeta[8], zeta[4]}; +assign ntt_twiddle_mem[2] = {zeta[11], zeta[10], zeta[5]}; +assign ntt_twiddle_mem[3] = {zeta[13], zeta[12], zeta[6]}; +assign ntt_twiddle_mem[4] = {zeta[15], zeta[14], zeta[7]}; +assign ntt_twiddle_mem[5] = {zeta[33], zeta[32], zeta[16]}; +assign ntt_twiddle_mem[6] = {zeta[35], zeta[34], zeta[17]}; +assign ntt_twiddle_mem[7] = {zeta[37], zeta[36], zeta[18]}; +assign ntt_twiddle_mem[8] = {zeta[39], zeta[38], zeta[19]}; +assign ntt_twiddle_mem[9] = {zeta[41], zeta[40], zeta[20]}; +assign ntt_twiddle_mem[10] = {zeta[43], zeta[42], zeta[21]}; +assign ntt_twiddle_mem[11] = {zeta[45], zeta[44], zeta[22]}; +assign ntt_twiddle_mem[12] = {zeta[47], zeta[46], zeta[23]}; +assign ntt_twiddle_mem[13] = {zeta[49], zeta[48], zeta[24]}; +assign ntt_twiddle_mem[14] = {zeta[51], zeta[50], zeta[25]}; +assign ntt_twiddle_mem[15] = {zeta[53], zeta[52], zeta[26]}; +assign ntt_twiddle_mem[16] = {zeta[55], zeta[54], zeta[27]}; +assign ntt_twiddle_mem[17] = {zeta[57], zeta[56], zeta[28]}; +assign ntt_twiddle_mem[18] = {zeta[59], zeta[58], zeta[29]}; +assign ntt_twiddle_mem[19] = {zeta[61], zeta[60], zeta[30]}; +assign ntt_twiddle_mem[20] = {zeta[63], zeta[62], zeta[31]}; +assign ntt_twiddle_mem[21] = {zeta[129], zeta[128], zeta[64]}; +assign ntt_twiddle_mem[22] = {zeta[131], zeta[130], zeta[65]}; +assign ntt_twiddle_mem[23] = {zeta[133], zeta[132], zeta[66]}; +assign ntt_twiddle_mem[24] = {zeta[135], zeta[134], zeta[67]}; +assign ntt_twiddle_mem[25] = {zeta[137], zeta[136], zeta[68]}; +assign ntt_twiddle_mem[26] = {zeta[139], zeta[138], zeta[69]}; +assign ntt_twiddle_mem[27] = {zeta[141], zeta[140], zeta[70]}; +assign ntt_twiddle_mem[28] = {zeta[143], zeta[142], zeta[71]}; +assign ntt_twiddle_mem[29] = {zeta[145], zeta[144], zeta[72]}; +assign ntt_twiddle_mem[30] = {zeta[147], zeta[146], zeta[73]}; +assign ntt_twiddle_mem[31] = {zeta[149], zeta[148], zeta[74]}; +assign ntt_twiddle_mem[32] = {zeta[151], zeta[150], zeta[75]}; +assign ntt_twiddle_mem[33] = {zeta[153], zeta[152], zeta[76]}; +assign ntt_twiddle_mem[34] = {zeta[155], zeta[154], zeta[77]}; +assign ntt_twiddle_mem[35] = {zeta[157], zeta[156], zeta[78]}; +assign ntt_twiddle_mem[36] = {zeta[159], zeta[158], zeta[79]}; +assign ntt_twiddle_mem[37] = {zeta[161], zeta[160], zeta[80]}; +assign ntt_twiddle_mem[38] = {zeta[163], zeta[162], zeta[81]}; +assign ntt_twiddle_mem[39] = {zeta[165], zeta[164], zeta[82]}; +assign ntt_twiddle_mem[40] = {zeta[167], zeta[166], zeta[83]}; +assign ntt_twiddle_mem[41] = {zeta[169], zeta[168], zeta[84]}; +assign ntt_twiddle_mem[42] = {zeta[171], zeta[170], zeta[85]}; +assign ntt_twiddle_mem[43] = {zeta[173], zeta[172], zeta[86]}; +assign ntt_twiddle_mem[44] = {zeta[175], zeta[174], zeta[87]}; +assign ntt_twiddle_mem[45] = {zeta[177], zeta[176], zeta[88]}; +assign ntt_twiddle_mem[46] = {zeta[179], zeta[178], zeta[89]}; +assign ntt_twiddle_mem[47] = {zeta[181], zeta[180], zeta[90]}; +assign ntt_twiddle_mem[48] = {zeta[183], zeta[182], zeta[91]}; +assign ntt_twiddle_mem[49] = {zeta[185], zeta[184], zeta[92]}; +assign ntt_twiddle_mem[50] = {zeta[187], zeta[186], zeta[93]}; +assign ntt_twiddle_mem[51] = {zeta[189], zeta[188], zeta[94]}; +assign ntt_twiddle_mem[52] = {zeta[191], zeta[190], zeta[95]}; +assign ntt_twiddle_mem[53] = {zeta[193], zeta[192], zeta[96]}; +assign ntt_twiddle_mem[54] = {zeta[195], zeta[194], zeta[97]}; +assign ntt_twiddle_mem[55] = {zeta[197], zeta[196], zeta[98]}; +assign ntt_twiddle_mem[56] = {zeta[199], zeta[198], zeta[99]}; +assign ntt_twiddle_mem[57] = {zeta[201], zeta[200], zeta[100]}; +assign ntt_twiddle_mem[58] = {zeta[203], zeta[202], zeta[101]}; +assign ntt_twiddle_mem[59] = {zeta[205], zeta[204], zeta[102]}; +assign ntt_twiddle_mem[60] = {zeta[207], zeta[206], zeta[103]}; +assign ntt_twiddle_mem[61] = {zeta[209], zeta[208], zeta[104]}; +assign ntt_twiddle_mem[62] = {zeta[211], zeta[210], zeta[105]}; +assign ntt_twiddle_mem[63] = {zeta[213], zeta[212], zeta[106]}; +assign ntt_twiddle_mem[64] = {zeta[215], zeta[214], zeta[107]}; +assign ntt_twiddle_mem[65] = {zeta[217], zeta[216], zeta[108]}; +assign ntt_twiddle_mem[66] = {zeta[219], zeta[218], zeta[109]}; +assign ntt_twiddle_mem[67] = {zeta[221], zeta[220], zeta[110]}; +assign ntt_twiddle_mem[68] = {zeta[223], zeta[222], zeta[111]}; +assign ntt_twiddle_mem[69] = {zeta[225], zeta[224], zeta[112]}; +assign ntt_twiddle_mem[70] = {zeta[227], zeta[226], zeta[113]}; +assign ntt_twiddle_mem[71] = {zeta[229], zeta[228], zeta[114]}; +assign ntt_twiddle_mem[72] = {zeta[231], zeta[230], zeta[115]}; +assign ntt_twiddle_mem[73] = {zeta[233], zeta[232], zeta[116]}; +assign ntt_twiddle_mem[74] = {zeta[235], zeta[234], zeta[117]}; +assign ntt_twiddle_mem[75] = {zeta[237], zeta[236], zeta[118]}; +assign ntt_twiddle_mem[76] = {zeta[239], zeta[238], zeta[119]}; +assign ntt_twiddle_mem[77] = {zeta[241], zeta[240], zeta[120]}; +assign ntt_twiddle_mem[78] = {zeta[243], zeta[242], zeta[121]}; +assign ntt_twiddle_mem[79] = {zeta[245], zeta[244], zeta[122]}; +assign ntt_twiddle_mem[80] = {zeta[247], zeta[246], zeta[123]}; +assign ntt_twiddle_mem[81] = {zeta[249], zeta[248], zeta[124]}; +assign ntt_twiddle_mem[82] = {zeta[251], zeta[250], zeta[125]}; +assign ntt_twiddle_mem[83] = {zeta[253], zeta[252], zeta[126]}; +assign ntt_twiddle_mem[84] = {zeta[255], zeta[254], zeta[127]}; +//-------------------------------------------------------- + +assign intt_twiddle_mem[0] = {zetainv[127], zetainv[254], zetainv[255]}; +assign intt_twiddle_mem[1] = {zetainv[126], zetainv[252], zetainv[253]}; +assign intt_twiddle_mem[2] = {zetainv[125], zetainv[250], zetainv[251]}; +assign intt_twiddle_mem[3] = {zetainv[124], zetainv[248], zetainv[249]}; +assign intt_twiddle_mem[4] = {zetainv[123], zetainv[246], zetainv[247]}; +assign intt_twiddle_mem[5] = {zetainv[122], zetainv[244], zetainv[245]}; +assign intt_twiddle_mem[6] = {zetainv[121], zetainv[242], zetainv[243]}; +assign intt_twiddle_mem[7] = {zetainv[120], zetainv[240], zetainv[241]}; +assign intt_twiddle_mem[8] = {zetainv[119], zetainv[238], zetainv[239]}; +assign intt_twiddle_mem[9] = {zetainv[118], zetainv[236], zetainv[237]}; +assign intt_twiddle_mem[10] = {zetainv[117], zetainv[234], zetainv[235]}; +assign intt_twiddle_mem[11] = {zetainv[116], zetainv[232], zetainv[233]}; +assign intt_twiddle_mem[12] = {zetainv[115], zetainv[230], zetainv[231]}; +assign intt_twiddle_mem[13] = {zetainv[114], zetainv[228], zetainv[229]}; +assign intt_twiddle_mem[14] = {zetainv[113], zetainv[226], zetainv[227]}; +assign intt_twiddle_mem[15] = {zetainv[112], zetainv[224], zetainv[225]}; +assign intt_twiddle_mem[16] = {zetainv[111], zetainv[222], zetainv[223]}; +assign intt_twiddle_mem[17] = {zetainv[110], zetainv[220], zetainv[221]}; +assign intt_twiddle_mem[18] = {zetainv[109], zetainv[218], zetainv[219]}; +assign intt_twiddle_mem[19] = {zetainv[108], zetainv[216], zetainv[217]}; +assign intt_twiddle_mem[20] = {zetainv[107], zetainv[214], zetainv[215]}; +assign intt_twiddle_mem[21] = {zetainv[106], zetainv[212], zetainv[213]}; +assign intt_twiddle_mem[22] = {zetainv[105], zetainv[210], zetainv[211]}; +assign intt_twiddle_mem[23] = {zetainv[104], zetainv[208], zetainv[209]}; +assign intt_twiddle_mem[24] = {zetainv[103], zetainv[206], zetainv[207]}; +assign intt_twiddle_mem[25] = {zetainv[102], zetainv[204], zetainv[205]}; +assign intt_twiddle_mem[26] = {zetainv[101], zetainv[202], zetainv[203]}; +assign intt_twiddle_mem[27] = {zetainv[100], zetainv[200], zetainv[201]}; +assign intt_twiddle_mem[28] = {zetainv[99], zetainv[198], zetainv[199]}; +assign intt_twiddle_mem[29] = {zetainv[98], zetainv[196], zetainv[197]}; +assign intt_twiddle_mem[30] = {zetainv[97], zetainv[194], zetainv[195]}; +assign intt_twiddle_mem[31] = {zetainv[96], zetainv[192], zetainv[193]}; +assign intt_twiddle_mem[32] = {zetainv[95], zetainv[190], zetainv[191]}; +assign intt_twiddle_mem[33] = {zetainv[94], zetainv[188], zetainv[189]}; +assign intt_twiddle_mem[34] = {zetainv[93], zetainv[186], zetainv[187]}; +assign intt_twiddle_mem[35] = {zetainv[92], zetainv[184], zetainv[185]}; +assign intt_twiddle_mem[36] = {zetainv[91], zetainv[182], zetainv[183]}; +assign intt_twiddle_mem[37] = {zetainv[90], zetainv[180], zetainv[181]}; +assign intt_twiddle_mem[38] = {zetainv[89], zetainv[178], zetainv[179]}; +assign intt_twiddle_mem[39] = {zetainv[88], zetainv[176], zetainv[177]}; +assign intt_twiddle_mem[40] = {zetainv[87], zetainv[174], zetainv[175]}; +assign intt_twiddle_mem[41] = {zetainv[86], zetainv[172], zetainv[173]}; +assign intt_twiddle_mem[42] = {zetainv[85], zetainv[170], zetainv[171]}; +assign intt_twiddle_mem[43] = {zetainv[84], zetainv[168], zetainv[169]}; +assign intt_twiddle_mem[44] = {zetainv[83], zetainv[166], zetainv[167]}; +assign intt_twiddle_mem[45] = {zetainv[82], zetainv[164], zetainv[165]}; +assign intt_twiddle_mem[46] = {zetainv[81], zetainv[162], zetainv[163]}; +assign intt_twiddle_mem[47] = {zetainv[80], zetainv[160], zetainv[161]}; +assign intt_twiddle_mem[48] = {zetainv[79], zetainv[158], zetainv[159]}; +assign intt_twiddle_mem[49] = {zetainv[78], zetainv[156], zetainv[157]}; +assign intt_twiddle_mem[50] = {zetainv[77], zetainv[154], zetainv[155]}; +assign intt_twiddle_mem[51] = {zetainv[76], zetainv[152], zetainv[153]}; +assign intt_twiddle_mem[52] = {zetainv[75], zetainv[150], zetainv[151]}; +assign intt_twiddle_mem[53] = {zetainv[74], zetainv[148], zetainv[149]}; +assign intt_twiddle_mem[54] = {zetainv[73], zetainv[146], zetainv[147]}; +assign intt_twiddle_mem[55] = {zetainv[72], zetainv[144], zetainv[145]}; +assign intt_twiddle_mem[56] = {zetainv[71], zetainv[142], zetainv[143]}; +assign intt_twiddle_mem[57] = {zetainv[70], zetainv[140], zetainv[141]}; +assign intt_twiddle_mem[58] = {zetainv[69], zetainv[138], zetainv[139]}; +assign intt_twiddle_mem[59] = {zetainv[68], zetainv[136], zetainv[137]}; +assign intt_twiddle_mem[60] = {zetainv[67], zetainv[134], zetainv[135]}; +assign intt_twiddle_mem[61] = {zetainv[66], zetainv[132], zetainv[133]}; +assign intt_twiddle_mem[62] = {zetainv[65], zetainv[130], zetainv[131]}; +assign intt_twiddle_mem[63] = {zetainv[64], zetainv[128], zetainv[129]}; +assign intt_twiddle_mem[64] = {zetainv[31], zetainv[62], zetainv[63]}; +assign intt_twiddle_mem[65] = {zetainv[30], zetainv[60], zetainv[61]}; +assign intt_twiddle_mem[66] = {zetainv[29], zetainv[58], zetainv[59]}; +assign intt_twiddle_mem[67] = {zetainv[28], zetainv[56], zetainv[57]}; +assign intt_twiddle_mem[68] = {zetainv[27], zetainv[54], zetainv[55]}; +assign intt_twiddle_mem[69] = {zetainv[26], zetainv[52], zetainv[53]}; +assign intt_twiddle_mem[70] = {zetainv[25], zetainv[50], zetainv[51]}; +assign intt_twiddle_mem[71] = {zetainv[24], zetainv[48], zetainv[49]}; +assign intt_twiddle_mem[72] = {zetainv[23], zetainv[46], zetainv[47]}; +assign intt_twiddle_mem[73] = {zetainv[22], zetainv[44], zetainv[45]}; +assign intt_twiddle_mem[74] = {zetainv[21], zetainv[42], zetainv[43]}; +assign intt_twiddle_mem[75] = {zetainv[20], zetainv[40], zetainv[41]}; +assign intt_twiddle_mem[76] = {zetainv[19], zetainv[38], zetainv[39]}; +assign intt_twiddle_mem[77] = {zetainv[18], zetainv[36], zetainv[37]}; +assign intt_twiddle_mem[78] = {zetainv[17], zetainv[34], zetainv[35]}; +assign intt_twiddle_mem[79] = {zetainv[16], zetainv[32], zetainv[33]}; +assign intt_twiddle_mem[80] = {zetainv[7], zetainv[14], zetainv[15]}; +assign intt_twiddle_mem[81] = {zetainv[6], zetainv[12], zetainv[13]}; +assign intt_twiddle_mem[82] = {zetainv[5], zetainv[10], zetainv[11]}; +assign intt_twiddle_mem[83] = {zetainv[4], zetainv[8], zetainv[9]}; +assign intt_twiddle_mem[84] = {zetainv[1], zetainv[2], zetainv[3]}; + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/butterfly_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/butterfly_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..756ed5e01be089a1dfa5022c0e3f9660f472c748 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/butterfly_normal_test.yml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +# plusargs: +# - +ECC_TEST_VECTOR_FILE='${CALIPTRA_ROOT}/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex' +# - +ECC_TEST='ECC_normal_test' + +testname: butterfly_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/ntt_masking_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/ntt_masking_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..28eb238f3b9c0879fa01680b22043a34b4e4c99d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/ntt_masking_normal_test.yml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +# plusargs: +# - +ECC_TEST_VECTOR_FILE='${CALIPTRA_ROOT}/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex' +# - +ECC_TEST='ECC_normal_test' + +testname: ntt_masking_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/ntt_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/ntt_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..e709abcdcc84603d0ef48f22e8f19e2bc160cf91 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/tests/directed/ntt_normal_test.yml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +# plusargs: +# - +ECC_TEST_VECTOR_FILE='${CALIPTRA_ROOT}/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex' +# - +ECC_TEST='ECC_normal_test' + +testname: ntt_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/testsuites/ntt_nightly_directed_regression.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/testsuites/ntt_nightly_directed_regression.yml new file mode 100644 index 0000000000000000000000000000000000000000..bfbe665ef21648fed9439785a89ee70c69b89935 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/stimulus/testsuites/ntt_nightly_directed_regression.yml @@ -0,0 +1,8 @@ +document: + schema: 1.0 + +contents: + - tests: + tags: ["L0", "directed", "nightly", "NTT"] + paths: + - ${ADAMSBRIDGE_ROOT}/src/ntt_top/stimulus/tests/directed/ntt_normal_test.yml diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/butterfly_top_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/butterfly_top_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..c481f7fac6ee155e658a85fbca9b3946646d0ca4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/butterfly_top_tb.sv @@ -0,0 +1,617 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// butterfly_top_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module butterfly_top_tb + import ntt_defines_pkg::*; +#( + parameter TEST_VECTOR_NUM = 10, + parameter PRIME = 23'd8380417, + parameter REG_SIZE = 23 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg [31 : 0] cycle_ctr; +reg [31 : 0] error_ctr; +reg [31 : 0] tc_ctr; + +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; + +reg [REG_SIZE-1:0] A, B, U, V, w; +reg [REG_SIZE-1:0] U_out, V_out; +reg [REG_SIZE-1:0] GS_V, pwm_res; +reg [REG_SIZE-1:0] GS_U; +reg [REG_SIZE-1:0] res; +mode_t mode_tb; +reg enable, sub; +reg ready; +reg zeroize_tb; + +reg [REG_SIZE-1:0] u00, u01, v00, v01, w00, w01, w10, w11; +reg [REG_SIZE-1:0] U20_out, U21_out, V20_out, V21_out; + +string operation; +reg [23:0] zeta [255:0]; +reg [23:0] zeta_inv [255:0]; +reg [23:0] in_val [255*4:0]; +reg [23:0] out_val [255*4:0]; +reg [23:0] out_observed [255*4:0]; +reg [23:0] intt_out_observed [255*4:0]; + +bf_uvwi_t uvw_tb; +bf_uvo_t uv_o_tb; + +//---------------------------------------------------------------- +// Device Under Test. +//---------------------------------------------------------------- + +butterfly2x2 #( + .REG_SIZE(23), + .RADIX(23), + .MLDSA_Q(PRIME) +) +dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .mode(mode_tb), + .enable(enable), + .uvw_i(uvw_tb), + .uv_o(uv_o_tb), + .ready_o(ready) +); + +// butterfly #( +// .REG_SIZE(23), +// .RADIX(23), +// .MLDSA_Q(PRIME) +// ) +// dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .mode(mode_tb), +// .enable(enable), +// .opu_i(U), +// .opv_i(V), +// .opw_i(w), +// .u_o(U_out), +// .v_o(V_out), +// // .intt_u_o(GS_U), +// // .intt_v_o(GS_V), +// .pwm_res_o(pwm_res), +// .ready_o(ready) +// ); + +// ecc_add_sub_mod_alter #( +// .REG_SIZE(23) +// ) +// dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(), +// .add_en_i(enable), +// .sub_i(sub), +// .opa_i(A), +// .opb_i(B), +// .prime_i(PRIME), +// .res_o(res), //result ready in 2 cycles after enable is asserted +// .ready_o() + +// ); + +// mult_mod_alter #( +// .RADIX(23), +// .REG_SIZE(23), +// .PRIME(PRIME) +// ) +// dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(1'b0), +// .enable(enable), +// .opa_i(A), +// .opb_i(B), +// .res_o(res), +// .ready_o() +// ); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + + +//---------------------------------------------------------------- +// sys_monitor() +// +// An always running process that creates a cycle counter and +// conditionally displays information about the DUT. +//---------------------------------------------------------------- +always +begin : sys_monitor + #(CLK_PERIOD); + cycle_ctr = cycle_ctr + 1; +end + + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; +begin + $display("*** Toggle reset."); +// cptra_pwrgood_tb = '0; + reset_n_tb = 0; + +// #(2 * CLK_PERIOD); +// cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); +end +endtask // reset_dut + +//---------------------------------------------------------------- +// display_test_results() +// +// Display the accumulated test results. +//---------------------------------------------------------------- +task display_test_results; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d tests completed - %02d test cases did not complete successfully.", + tc_ctr, error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_results + +//---------------------------------------------------------------- +// init_sim() +// +// Initialize all counters and testbed functionality as well +// as setting the DUT inputs to defined values. +//---------------------------------------------------------------- + task init_sim; + int i; + begin + $display("Start of init"); + cycle_ctr = 32'h00000000; + error_ctr = 32'h00000000; + tc_ctr = 32'h00000000; + + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + + A = 'h0; + B = 'h0; + U = 'h0; + V = 'h0; + w = 'h0; + mode_tb = ct; + enable = 1'b0; + zeroize_tb = 1'b0; + sub = 1'b0; + // u00 = 'h0; v00 = 'h0; u01 = 'h0; v01 = 'h0; + // w00 = 'h0; w01 = 'h0; w10 = 'h0; w11 = 'h0; + uvw_tb.u00_i = 'h0; + uvw_tb.v00_i = 'h0; + uvw_tb.u01_i = 'h0; + uvw_tb.v01_i = 'h0; + uvw_tb.w00_i = 'h0; + uvw_tb.w01_i = 'h0; + uvw_tb.w10_i = 'h0; + uvw_tb.w11_i = 'h0; + operation = "init"; + for (i = 0; i < 256; i++) begin + zeta[i] = 0; + zeta_inv[i] = 0; + end + for (i = 0; i < 256*4; i++) begin + in_val[i] = 'h0; + out_val[i] = 'h0; + out_observed[i] = 'h0; + intt_out_observed[i] = 'h0; + end + $display("End of init"); + end + endtask + + task butterfly_test(); + begin + U <= 8380416; + V <= 10000; + w <= 1; + mode_tb <= ct; + enable <= 1'b1; + zeroize_tb <= 1'b0; + operation = "NTT"; + // #(CLK_PERIOD); + // enable <= 1'b0; + #(4*CLK_PERIOD); + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + + // #(CLK_PERIOD); + // #(CLK_HALF_PERIOD); + U <= 11; + V <= 22; + w <= 1; + // mode_tb <= ct; + // enable <= 1'b1; + // zeroize_tb <= 1'b0; + // operation = "NTT"; + // #(CLK_PERIOD); + // enable <= 1'b0; + #(4*CLK_PERIOD); + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + + // #(CLK_PERIOD); + // #(CLK_HALF_PERIOD); + U <= 55; + V <= 66; + w <= 5; + // mode_tb <= ct; + // enable <= 1'b1; + // zeroize_tb <= 1'b0; + // operation = "NTT"; + // #(CLK_PERIOD); + // enable <= 1'b0; + #(4*CLK_PERIOD); + while(dut.ready_o == 1'b0) + #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + + + + U <= U_out; + V <= V_out; + w <= 5; //'h7fe000; + mode_tb <= gs; + enable <= 1'b1; + operation = "INTT"; + // #(CLK_PERIOD); + // enable <= 1'b0; + #(4*CLK_PERIOD); + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + end + endtask + + task butterfly_2coeff_test(); + begin + U <= 8380416; + V <= 10000; + w <= 1; + mode_tb <= ct; + enable <= 1'b1; + zeroize_tb <= 1'b0; + operation = "NTT"; + // #(CLK_PERIOD); + // enable <= 1'b0; + #(4*CLK_PERIOD); + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + #(CLK_PERIOD); + + U <= U_out; + V <= V_out; + w <= 1; //'h7fe000; + mode_tb <= gs; + enable <= 1'b1; + operation = "INTT"; + // #(CLK_PERIOD); + // enable <= 1'b0; + #(4*CLK_PERIOD); + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + + end + endtask + + task zeroize_dut(); + begin + zeroize_tb <= 1'b1; + #(CLK_PERIOD); + zeroize_tb <= 1'b0; + #(5*CLK_PERIOD); + end + endtask + + task pwm_test(); + begin + mode_tb <= pwm; + enable <= 1'b1; + operation = "PWM"; + U <= 1234; + V <= 8380417; + w <= 8380416; + // #(CLK_PERIOD); + // enable <= 1'b0; + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + $display("U = %d, V = %d, w = %d, ntt u = %d, ntt v = %d, pwm_res", U, V, w, U_out, V_out, pwm_res); + + end + endtask + + task intt_butterfly2x2_div2_test(); + int a; + int test_cnt; + + fork + begin + enable <= 1'b1; + @(posedge clk_tb); + enable <= 1'b0; + end + begin + for (int j = 0; j < 64; j++) begin + int k1 = 3; //fix harcoding later TODO + int k2 = 2; + int k3 = 1; + + // u00 <= out_observed[j*4]; + uvw_tb.u00_i <= out_observed[j*4]; + uvw_tb.u01_i <= out_observed[(j*4)+1]; + uvw_tb.v00_i <= out_observed[(j*4)+2]; + uvw_tb.v01_i <= out_observed[(j*4)+3]; + + uvw_tb.w00_i <= zeta_inv[k1]; + uvw_tb.w01_i <= zeta_inv[k2]; + uvw_tb.w10_i <= zeta_inv[k3]; + uvw_tb.w11_i <= zeta_inv[k3]; + + mode_tb <= gs; + // enable <= 1'b1; + zeroize_tb <= 1'b0; + operation = $sformatf("INTT %0d, %0d, %0d, %0d", j*4, (j*4)+1, (j*4)+2, (j*4)+3); + $display("operation = %s", operation); + @(posedge clk_tb); + // enable <= 1'b0; //HERE + end + end + + begin + for (int j = 0; j < 64+11; j++) begin + if (dut.ready_o && (test_cnt < 256)) begin + $display("Capturing result %h, j = %d, test_cnt = %d", uv_o_tb.u20_o, j, test_cnt); + test_cnt++; + a = j-11; //by the time ready is 1, j advances to 11 + intt_out_observed[a*4] = uv_o_tb.u20_o; //U20_out; + intt_out_observed[(a*4)+1] = uv_o_tb.u21_o; //U21_out; + intt_out_observed[(a*4)+2] = uv_o_tb.v20_o; //V20_out; + intt_out_observed[(a*4)+3] = uv_o_tb.v21_o; //V21_out; + $display("out observed is now %h at location %d", intt_out_observed[a*4], a*4); + end + @(posedge clk_tb); + end + end + join + + if (intt_out_observed == in_val) + $display("INTT operation success\n"); + else begin + $display("Test failed at INTT operation\n"); + $display("INTT: U20_out = %h, out_observed[0] = %h, out_val[0] = %h", uv_o_tb.u20_o, intt_out_observed[0], out_val[0]); + end + enable <= 1'b0; + @(posedge clk_tb); + endtask + + task butterfly2x2_test(); + begin + int a; + int test_cnt; + // u00 <= 'h0; v00 <= 'd128; u01 <= 'd64; v01 <= 'd192; + // w00 <= 'h495E02; /*w01 <= 'h495e02;*/ w10 <= 'h397567; w11 <= 'h396569; + fork + begin + enable <= 1'b1; + @(posedge clk_tb); + enable <= 1'b0; + end + begin + // for (int l = 256; l > 0; l-2) begin + // int m = 1 << (l-2); + int l = 6; + int i; + $display("Stage %d and %d\n", 8-l, (8-l)+1); + for (i = 0; i < 256; i = i + 64) begin + for (int j = 0; j < 64; j++) begin //i = 0, m = 64 for 1st stage + int k1 = (256+i) >> l; + int k2 = (256+i) >> l-1; + int k3 = k2 + 1; + + $display("In for loop, j = %d at time %t, ready = %d\n", j, $time, dut.ready_o); + + // u00 <= in_val[j*4]; + uvw_tb.u00_i <= in_val[j*4] ; + uvw_tb.u01_i <= in_val[(j*4) + 1]; + uvw_tb.v00_i <= in_val[(j*4) + 2]; + uvw_tb.v01_i <= in_val[(j*4)+3]; + + uvw_tb.w00_i <= zeta[k1]; + uvw_tb.w01_i <= zeta[k1]; + uvw_tb.w10_i <= zeta[k2]; + uvw_tb.w11_i <= zeta[k3]; + // $display("w00 = %h", w00); + mode_tb <= ct; + // enable <= 1'b1; + zeroize_tb <= 1'b0; + operation = $sformatf("NTT %0d, %0d, %0d, %0d", j*4, (j*4)+1, (j*4)+2, (j*4)+3); + $display("operation = %s", operation); + + @(posedge clk_tb); + end //j + end //i + // end //l + end + begin + for (int j = 0; j < 64+11; j++) begin + if (dut.ready_o && (test_cnt < 256)) begin + $display("Capturing result %h, j = %d, test_cnt = %d", uv_o_tb.u20_o, j, test_cnt); + test_cnt++; + a = j-11; //by the time ready is 1, j advances to 11 + out_observed[a*4] = uv_o_tb.u20_o; //U20_out; + out_observed[(a*4)+1] = uv_o_tb.u21_o; //U21_out; + out_observed[(a*4)+2] = uv_o_tb.v20_o; //V20_out; + out_observed[(a*4)+3] = uv_o_tb.v21_o; //V21_out; + $display("out observed is now %h at location %d", out_observed[a*4], a*4); + end + #(CLK_PERIOD); + end + end + join + + if (out_observed == out_val) begin + $display("NTT operation success\n"); + end + else begin + $display("Test failed at NTT operation\n"); + $display("NTT: U20_out = %h, out_observed[0] = %h, out_val[0] = %h", U20_out, out_observed[0], out_val[0]); + end + enable <= 1'b0; + // if ((U20_out == out_val[0]) & (U21_out == out_val[1]) & (V20_out == out_val[2]) & (V21_out == out_val[3])) + // $display("Test case passed for fwd NTT!\n"); + // else begin + // $error("Test case failed\n"); + // $finish; + // end + // $display("u20 = %d, u21 = %d, v20 = %d, v21 = %d", U20_out, U21_out, V20_out, V21_out); + + // $display("Expected: u20 = 3139780, u21 = 4687447, v20 = 4217002, v21 = 4716605\n"); + + #(CLK_PERIOD); + // enable <= 1'b1; + // u00 <= U20_out; v00 <= V20_out; u01 <= U21_out; v01 <= V21_out; + // w00 <= 'h7fe000; w01 <= 'h3681ff; w10 <= 'h466a9a; w11 <= 'h467a98; + // mode_tb <= ct; + // // enable <= 1'b1; + // zeroize_tb <= 1'b0; + // operation = "NTT 2"; + // // #(CLK_PERIOD); + // // enable <= 1'b0; + // while(dut.ready_o == 1'b0) + // #(CLK_PERIOD); + // enable <= 1'b0; + // $display("u20 = %h, u21 = %h, v20 = %h, v21 = %h", U20_out, U21_out, V20_out, V21_out); + + end + endtask + + // task read_ntt_hex(input string fname); + // integer fin; + // integer rv; + // integer line_cnt; + // reg [23:0] val[255:0]; + // fin = $fopen(fname, "r"); + // if (fin == 0) + // $error("Cannot open file %s for reading", fname); + // while (!$feof(fin)) begin + // rv = $fscanf(fin, "%h\n", val); + // if(rv != 1) begin + // $error("Failed to read matching string"); + // $fclose(fin); + // $finish; + // end + // end + // $display("zeta 0 = %h", val[0]); + // $fclose(fin); + // endtask + + task read_ntt_hex(); + begin + end + endtask + +//---------------------------------------------------------------- +// ecc_test() +// +//---------------------------------------------------------------- + initial begin + init_sim(); + reset_dut(); + $readmemh("zeta.txt", zeta); + $readmemh("zeta_inv.hex", zeta_inv); + $display("Zeta values are %h, %h, %h, ...", zeta[0], zeta[1], zeta[2]); + $display("Zeta inv values are %h, %h, %h, ...", zeta_inv[0], zeta_inv[1], zeta_inv[2]); + $readmemh("ntt_stage2.hex", in_val); + $display("in_val = %h, %h, %h, ...", in_val[0], in_val[1], in_val[2]); + $readmemh("ntt_stage2_out.hex", out_val); + $display("out_val = %h, %h, %h, ...", out_val[0], out_val[1], out_val[2]); + #(CLK_PERIOD); + #(CLK_HALF_PERIOD); + + // butterfly_test(); + // zeroize_dut(); + // enable <= 1'b0; + // butterfly_2coeff_test(); + // zeroize_dut(); + // enable <= 1'b0; + butterfly2x2_test(); + intt_butterfly2x2_div2_test(); + // zeroize_dut(); + // enable <= 1'b0; + // pwm_test(); + // read_ntt_hex("ntt_test_vector.hex"); + + #(10*CLK_PERIOD); + + $finish; + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_masked_mult_redux46_auto_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_masked_mult_redux46_auto_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..2f5dfcc22a31395456084c85b772b57ad67b2f6e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_masked_mult_redux46_auto_tb.sv @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_mult_redux46_auto_tb.sv +// -------- +// +// +//====================================================================== + +module ntt_masked_mult_redux46_auto_tb; + + // Parameters + parameter WIDTH = 46; + parameter WIDTH_RND = 63; + parameter PRIME = 23'd8380417; + parameter LATENCY = 156; + parameter NUM_OF_TEST_VECTOR = 1000000; + + // Clock and reset + reg clk; + reg rst_n; + + // Inputs and outputs + reg zeroize; + reg [WIDTH_RND-1:0] rnd; + reg [(WIDTH/2)*3-1:0] rnd_width3; + reg [WIDTH-1:0] actual_input; + reg [WIDTH-1:0] random_mask; + reg [WIDTH/2-1:0] expected_output; + reg [WIDTH/2-1:0] expected_output_shift_reg [0:LATENCY-1]; + integer cycle_count; + + // Masked input shares + logic [1:0] x_share [WIDTH-1:0]; + wire [1:0] y_share [WIDTH/2-1:0]; + logic [WIDTH/2-1:0] y; + + // Assign x_share and reconstruct y + always_comb begin + for (int i = 0; i < WIDTH; i = i + 1) begin + x_share[i][0] = actual_input[i] ^ random_mask[i]; + x_share[i][1] = random_mask[i]; + end + for (int i = 0; i < WIDTH/2; i = i + 1) begin + y[i] = y_share[i][0] ^ y_share[i][1]; + end + end + + // Instantiate the DUT + ntt_masked_mult_redux46 #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .rnd0_11(rnd[10:0]), + .rnd1_11(rnd[21:11]), + .rnd2_11(rnd[32:22]), + .rnd0_12(rnd[44:33]), + .rnd0_4(rnd[48:45]), + .rnd0_14(rnd[62:49]), + .rnd_3WIDTH(rnd_width3), + .x(x_share), + .y(y_share) + ); + + // Clock generation + always #5 clk = ~clk; + + // Testbench logic + always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + cycle_count <= 0; + // Initialize shift registers + for (int i = 0; i < LATENCY; i = i + 1) begin + expected_output_shift_reg[i] <= 0; + end + end else begin + // Generate new inputs + actual_input <= {$urandom, $urandom} % (PRIME**2); + random_mask <= {$urandom, $urandom}; + + // Compute expected output + expected_output <= actual_input % PRIME; + + // Shift the expected outputs + for (int i = LATENCY-1; i > 0; i = i - 1) begin + expected_output_shift_reg[i] <= expected_output_shift_reg[i - 1]; + end + + // Store new expected output + expected_output_shift_reg[0] <= expected_output; + + // Provide random numbers + rnd <= {$urandom, $urandom, $urandom}; + rnd_width3 <= {$urandom, $urandom, $urandom}; + + // Compare output after latency + if (cycle_count >= LATENCY+2) begin + if (y !== expected_output_shift_reg[LATENCY-1]) begin + $display("Mismatch at cycle %0d: expected %0d, got %0d", cycle_count, expected_output_shift_reg[LATENCY-1], y); + end + // else begin + // $display("Match at cycle %0d: output %0d", cycle_count, y); + // end + end + + cycle_count <= cycle_count + 1; + + if (cycle_count >= NUM_OF_TEST_VECTOR) begin + $stop; + end + if ((cycle_count%10000) == 9999) begin + $display("Hit the interval %d", cycle_count); + end + end + end + + // Initialize clock and reset + initial begin + clk = 0; + rst_n = 0; + zeroize = 0; + cycle_count = 0; + rnd = '0; + rnd_width3 = '0; + #10 rst_n = 1; + end + +endmodule: ntt_masked_mult_redux46_auto_tb diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_masked_mult_redux46_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_masked_mult_redux46_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..ec620e19ec6cc127d10e9934b423d5959616ea07 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_masked_mult_redux46_tb.sv @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_masked_mult_redux46_tb.sv +// -------- +// +// +//====================================================================== + +module ntt_masked_mult_redux46_tb; + + // Parameters + parameter WIDTH = 46; + parameter WIDTH_RND = 63; + parameter PRIME = 23'd8380417; + + // Clock and reset + reg clk; + reg rst_n; + + // Inputs and outputs + reg zeroize; + logic [WIDTH_RND-1:0] rnd; + reg [WIDTH-1:0] x; + reg [WIDTH/2-1:0] y; + reg [WIDTH-1:0] random_mask; + reg [WIDTH-1:0] actual_input; + reg [10:0] d_10_0; + reg [22:0] d_22_0; + reg [22:0] z_45_23; + reg [23:0] d_22_0_r0c0; + reg [23:0] d_22_0_r1c1; + reg c0c1; + reg [11:0] c_11_0; + reg [13:0] f_14_0; + reg [22:0] e_22_0, res_22_0; + + // Masked input shares + reg [1:0] x_share [WIDTH-1:0]; + wire [1:0] y_share [WIDTH/2-1:0]; + + // Queue to store inputs + typedef struct { + logic [1:0] x_boolean [WIDTH-1:0]; + logic [WIDTH-1:0] rnd; + } input_t; + input_t input_queue [(WIDTH + 2)]; + + always_comb begin + for (int i = 0; i < WIDTH; i = i + 1) begin + x_share[i][0] = actual_input[i] ^ random_mask[i]; + x_share[i][1] = random_mask[i]; + end + for (int i = 0; i < WIDTH/2; i = i + 1) begin + y[i] = y_share[i][0] ^ y_share[i][1]; + end + c_11_0 = actual_input[45:43] + actual_input[42:33] + actual_input[32:23] + actual_input[22:13]; + d_10_0 = c_11_0[11:10] + c_11_0[9:0]; + f_14_0 = actual_input[45:43] + actual_input[45:33] + c_11_0[11:10]; + d_22_0_r0c0 = {d_10_0,actual_input[12:0]}; + d_22_0_r1c1 = d_22_0_r0c0 - 23'd8380417; + c0c1 = d_22_0_r0c0[23] ^ d_22_0_r1c1[23]; + d_22_0 = c0c1 ? d_22_0_r1c1[22:0] : d_22_0_r0c0[22:0]; + e_22_0 = (f_14_0+actual_input[45:23]) % PRIME; + res_22_0 = (d_22_0 - e_22_0) % PRIME; + z_45_23 = actual_input[45:23]; + end + always begin + @(negedge clk); + rnd = 0; + end + + // Instantiate the DUT + ntt_masked_mult_redux46 #( + .WIDTH(WIDTH) + ) dut ( + .clk(clk), + .rst_n(rst_n), + .zeroize(zeroize), + .rnd0_11(rnd[10:0]), + .rnd1_11(rnd[21:11]), + .rnd2_11(rnd[32:22]), + .rnd0_12(rnd[44:33]), + .rnd0_4(rnd[48:45]), + .rnd0_14(rnd[62:49]), + .rnd_3WIDTH(69'h0), + .x(x_share), + .y(y_share) + ); + + // Clock generation + always #5 clk = ~clk; + + // Test vectors + initial begin + // Initialize clock and reset + clk = 0; + rst_n = 0; + zeroize = 0; + + actual_input = 46'd0; + random_mask = 0; + #10 rst_n = 1; + repeat (3) @(negedge clk); + + @(negedge clk); + actual_input = 46'd39066633300384; + random_mask = 0; + $display("%d and mod(Q) = %d",actual_input, (actual_input % PRIME)); + @(negedge clk); + actual_input = 46'd36135737955137; + random_mask = 0; + $display("%d and mod(Q) = %d",actual_input, (actual_input % PRIME)); + @(negedge clk); + actual_input = 46'd39840167205202; + random_mask = 0; + $display("%d and mod(Q) = %d",actual_input, (actual_input % PRIME)); + + + repeat(10000) @(posedge clk); + #1; + $stop; + end + + + + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_mult_reduction_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_mult_reduction_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..e986b7c4f924775cbad3c7034db1606e9ae27a59 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_mult_reduction_tb.sv @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_mult_reduction_tb.sv +// -------- +// +// +//====================================================================== + +module ntt_mult_reduction_tb + #( + parameter PRIME = 23'd8380417, + parameter REG_SIZE = 23, + parameter numOfTest = 1000 + ) +(); + + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +reg [31 : 0] cycle_ctr; +reg [31 : 0] error_ctr; +reg [31 : 0] tc_ctr; + +reg clk_tb; +reg reset_n_tb; +reg zeroize_tb; +reg [(2*REG_SIZE)-1:0] opa_i_tb; +reg [REG_SIZE-1:0] res_o_tb; +reg bf_ready_tb; + +logic [REG_SIZE-1:0] a; +logic [REG_SIZE-1:0] b; +logic [REG_SIZE-1:0] expected; + +ntt_mult_reduction #( + .REG_SIZE(REG_SIZE), + .PRIME(PRIME) +) +dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .opa_i(opa_i_tb), + .res_o(res_o_tb), + .ready_o(ready_o_tb) +); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +//---------------------------------------------------------------- +// sys_monitor() +// +// An always running process that creates a cycle counter and +// conditionally displays information about the DUT. +//---------------------------------------------------------------- +always +begin : sys_monitor + #(CLK_PERIOD); + cycle_ctr = cycle_ctr + 1; +end + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + end +endtask // reset_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + +//---------------------------------------------------------------- +// init_sim() +// +// Initialize all counters and testbed functionality as well +// as setting the DUT inputs to defined values. +//---------------------------------------------------------------- +task init_sim; + begin + $display("Start of init\n"); + cycle_ctr = 32'h00000000; + error_ctr = 32'h00000000; + tc_ctr = 32'h00000000; + + clk_tb = 0; + reset_n_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// ntt_mult_test() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task ntt_mult_test(input [REG_SIZE-1 : 0] op_a, + input [REG_SIZE-1 : 0] op_b); + begin + + $display("*** ntt_mult_test."); + #(CLK_PERIOD); + + opa_i_tb = a * b; + #(CLK_PERIOD); + + expected = opa_i_tb % PRIME; + #(5 * CLK_PERIOD); + + if (res_o_tb == expected) + $display("*** successful"); + else begin + $display("*** failed"); + $display("TC%01d: Expected: 0x%06x", tc_ctr, expected); + $display("TC%01d: Got: 0x%06x", tc_ctr, res_o_tb); + error_ctr = error_ctr + 1; + end + + tc_ctr = tc_ctr + 1; + #(2 * CLK_PERIOD); + end +endtask // ntt_mult_test + + +initial begin + init_sim(); + reset_dut(); + + @(posedge clk_tb); + + $display("Starting ntt_mult reduction test\n"); + + a = 30; + b = 40; + ntt_mult_test(a, b); + + a = 3054463; + b = 809589; + ntt_mult_test(a, b); + + a = 3082050; + b = 5637242; + ntt_mult_test(a, b); + + for (int i = 0; i < numOfTest; i++) begin + a = $urandom_range(0, PRIME - 1); + b = $urandom_range(0, PRIME - 1); + ntt_mult_test(a, b); + end + + display_test_result(); + + repeat(10) @(posedge clk_tb); + $display(" -- Testbench for ntt_mult reduction done. --"); + $finish; +end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_ram_tdp_file.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_ram_tdp_file.sv new file mode 100644 index 0000000000000000000000000000000000000000..380ffe64c1f901fbf60fca218c4444b597c66583 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_ram_tdp_file.sv @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_ram_tdp_file.sv +// -------- +// Temp NTT Data Memory to store intermediate results from point multiplication. +// +// +//====================================================================== + +module ntt_ram_tdp_file #( + parameter ADDR_WIDTH = 10, + parameter DATA_WIDTH = 32 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire ena, + input wire wea, + input wire [ADDR_WIDTH-1 : 0] addra, + input wire [DATA_WIDTH-1 : 0] dina, + output logic [DATA_WIDTH-1 : 0] douta, + + input wire enb, + input wire web, + input wire [ADDR_WIDTH-1 : 0] addrb, + input wire [DATA_WIDTH-1 : 0] dinb, + output logic [DATA_WIDTH-1 : 0] doutb, + + //TODO: temporary inputs. Remove after high-level memory is ready + input wire load_tb_values, + input wire [ADDR_WIDTH-1:0] load_tb_addr + ); + + // Declare the RAM variable + localparam ADDR_LENGTH = 2**ADDR_WIDTH; + reg [DATA_WIDTH-1:0] mem[ADDR_LENGTH-1:0], mem_tb[ADDR_LENGTH-1:0]; + + + //for tb purpose - TODO: temp, remove after high-level memory is ready + initial begin + $display("In ram, initing mem_tb\n"); + $readmemh("ntt_stage0_mem.hex", mem_tb); + end + + + always_ff @ (posedge clk or negedge reset_n) + begin : reading_memory + if (!reset_n) begin + douta <= '0; + doutb <= '0; + end + else if (zeroize) begin + douta <= '0; + doutb <= '0; + end + else begin + if (ena) + douta <= mem[addra]; + + if (enb) + doutb <= mem[addrb]; + end + end // reading_memory + + always_ff @ (posedge clk or negedge reset_n) + begin : writing_memory + if (!reset_n) begin + for (int i0 = 0; i0 < ADDR_LENGTH; i0++) + mem[i0] <= '0; + end + else if (zeroize) begin + for (int i0 = 0; i0 < ADDR_LENGTH; i0++) + mem[i0] <= '0; + end + else if (load_tb_values) + mem[load_tb_addr] <= mem_tb[load_tb_addr]; + else begin + if (ena & wea) + mem[addra] <= dina; + + if (enb & web) + mem[addrb] <= dinb; + end + end // writing_memory + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_ref.py b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_ref.py new file mode 100644 index 0000000000000000000000000000000000000000..ab2fc23c37ebdbf347d2ac9bbc0755e3ef5d0fdd --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_ref.py @@ -0,0 +1,316 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +# NTT Reference Implementation + +import numpy as np +import copy +import random + +### Dilithium Parameter +DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1 +DILITHIUM_N = 256 +DILITHIUM_LOGN = 8 +DILITHIUM_ROOT_OF_UNITY = 1753 + +### Butterfly +def ct_bf(u, v, z): + global DILITHIUM_Q + t = (v * z) % DILITHIUM_Q + v = (u - t) % DILITHIUM_Q + u = (u + t) % DILITHIUM_Q + return u, v + +def gs_bf(u, v, z): + global DILITHIUM_Q + t = (u - v) % DILITHIUM_Q + u = (u + v) % DILITHIUM_Q + v = (t * z) % DILITHIUM_Q + return u, v + +def gs_bf_div2(u, v, z): + global DILITHIUM_Q + t = div2((u - v) % DILITHIUM_Q) + u = div2((u + v) % DILITHIUM_Q) + v = (t * z) % DILITHIUM_Q + return u, v + +def div2(x): + global DILITHIUM_Q + if x & 1: + return (x >> 1) + ((DILITHIUM_Q + 1) // 2) + else: + return x >> 1 + +### Twiddle factor +def bit_reversal(x): + binary_string = format(x, '08b') + reversed_binary_string = binary_string[::-1] + reversed_decimal = int(reversed_binary_string, 2) + return reversed_decimal + +def zeta_generator(): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_ROOT_OF_UNITY + + tree=np.zeros(DILITHIUM_N) + for i in range (DILITHIUM_N): + tree[i] = bit_reversal(i) + + tmp={} + tmp[0] = 1 + + zetas={} + zetas_inv={} + + for i in range (1, DILITHIUM_N, 1): + tmp[i] = (tmp[i-1] * DILITHIUM_ROOT_OF_UNITY) % DILITHIUM_Q + + for i in range (0, DILITHIUM_N, 1): + zetas[i] = tmp[tree[i]] + zetas[i] = zetas[i] + zetas_inv[i] = -zetas[i] % DILITHIUM_Q + + return zetas, zetas_inv + +### ref NTTT/INTT model +def fwd_NTT(poly_r): + global DILITHIUM_Q + global DILITHIUM_N + global zetas + + r = copy.deepcopy(poly_r) + + k = 0 + m = 128 + while (m > 0): + start = 0 + while (start < DILITHIUM_N): + k += 1 + zeta = zetas[k] + for j in range(start, start+m): + r[j], r[j + m] = ct_bf(r[j], r[j + m], zeta) + start = start + 2 * m + m >>= 1 + + return r + +def inv_NTT(poly_r): + global DILITHIUM_Q + global DILITHIUM_N + global zetas_inv + + r = copy.deepcopy(poly_r) + + k = DILITHIUM_N + m = 1 + while (m < DILITHIUM_N): + start = 0 + while (start < DILITHIUM_N): + k -= 1 + zeta = zetas_inv[k] + for j in range(start, start+m): + r[j], r[j + m] = gs_bf(r[j], r[j + m], zeta) + start = start + 2 * m + m <<= 1 + + f = 8347681 # 256^-1 mod DILITHIUM_Q + for j in range(DILITHIUM_N): + r[j] = f*r[j] % DILITHIUM_Q + + return r + +### 2x2 NTT/INTT model +def fwd_NTT2x2(poly_r): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_LOGN + global zetas + + r = copy.deepcopy(poly_r) + + k2={} + zeta2={} + + for l in range(DILITHIUM_LOGN, 0, -2): + m = 1 << (l - 2) + for i in range(0, DILITHIUM_N, 1 << l): + k1 = (DILITHIUM_N + i) >> l + k2[0] = (DILITHIUM_N + i) >> (l - 1) + k2[1] = k2[0] + 1 + zeta1 = zetas[k1] + zeta2[0] = zetas[k2[0]] + zeta2[1] = zetas[k2[1]] + + for j in range(i, i + m): + u00 = r[j] + u01 = r[j + m] + v00 = r[j + 2 * m] + v01 = r[j + 3 * m] + + u10, u11 = ct_bf(u00, v00, zeta1) + v10, v11 = ct_bf(u01, v01, zeta1) + + u20, v20 = ct_bf(u10, v10, zeta2[0]) + u21, v21 = ct_bf(u11, v11, zeta2[1]) + + r[j] = u20 + r[j + m] = v20 + r[j + 2 * m] = u21 + r[j + 3 * m] = v21 + + return r + +def inv_NTT2x2(poly_r): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_LOGN + global zetas_inv + + r = copy.deepcopy(poly_r) + + k1={} + zeta1={} + + for l in range(0, DILITHIUM_LOGN - (DILITHIUM_LOGN & 1), 2): + m = 1 << l + for i in range(0, DILITHIUM_N, 1 << (l + 2)): + k1[0] = ((DILITHIUM_N - (i >> 1)) >> l) - 1 + k1[1] = k1[0] - 1 + k2 = ((DILITHIUM_N - (i >> 1)) >> (l + 1)) - 1 + zeta1[0] = zetas_inv[k1[0]] + zeta1[1] = zetas_inv[k1[1]] + zeta2 = zetas_inv[k2] + + for j in range(i, i + m): + u00 = r[j] + v00 = r[j + m] + u01 = r[j + 2 * m] + v01 = r[j + 3 * m] + + u10, u11 = gs_bf(u00, v00, zeta1[0]) + v10, v11 = gs_bf(u01, v01, zeta1[1]) + + u20, u21 = gs_bf(u10, v10, zeta2) + v20, v21 = gs_bf(u11, v11, zeta2) + + r[j] = u20 + r[j + m] = v20 + r[j + 2 * m] = u21 + r[j + 3 * m] = v21 + + f = 8347681 # 256^-1 mod DILITHIUM_Q + for j in range(DILITHIUM_N): + r[j] = f*r[j] % DILITHIUM_Q + + return r + + +def inv_NTT2x2_div2(poly_r): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_LOGN + global zetas_inv + + r = copy.deepcopy(poly_r) + + k1={} + zeta1={} + + for l in range(0, DILITHIUM_LOGN - (DILITHIUM_LOGN & 1), 2): + m = 1 << l + for i in range(0, DILITHIUM_N, 1 << (l + 2)): + k1[0] = ((DILITHIUM_N - (i >> 1)) >> l) - 1 + k1[1] = k1[0] - 1 + k2 = ((DILITHIUM_N - (i >> 1)) >> (l + 1)) - 1 + zeta1[0] = zetas_inv[k1[0]] + zeta1[1] = zetas_inv[k1[1]] + zeta2 = zetas_inv[k2] + + for j in range(i, i + m): + u00 = r[j] + v00 = r[j + m] + u01 = r[j + 2 * m] + v01 = r[j + 3 * m] + + u10, u11 = gs_bf_div2(u00, v00, zeta1[0]) + v10, v11 = gs_bf_div2(u01, v01, zeta1[1]) + + u20, u21 = gs_bf_div2(u10, v10, zeta2) + v20, v21 = gs_bf_div2(u11, v11, zeta2) + + r[j] = u20 + r[j + m] = v20 + r[j + 2 * m] = u21 + r[j + 3 * m] = v21 + + return r + + +def print_table(label, data, rows, cols): + print(label) + values = list(data.values()) + for i in range(0, len(values), cols): + row_values = values[i:i + cols] + print(" ".join(f"{value:06X}" for value in row_values)) + +zetas, zetas_inv = zeta_generator() +## print zeta values for NTT +print("zeta=") +for i in range (DILITHIUM_N): + print(hex(zetas[i])[2:].upper().zfill(6)) + +## print zeta_inv values for INTT +print("zetas_inv=") +for i in range (DILITHIUM_N): + print(hex(zetas_inv[i])[2:].upper().zfill(6)) + +### Test +test_no = 1 +for test_i in range(test_no): + r_init = {} + for i in range (DILITHIUM_N): + r_init[i] = i % DILITHIUM_Q #random.randrange(DILITHIUM_Q) # + + #using ref model + r_in_ntt = fwd_NTT(r_init) + r_from_ntt = inv_NTT(r_in_ntt) + #check ref model + if (r_init != r_from_ntt): + print("Error in ref model") + + #using 2x2 architecture + r_in_ntt2x2 = fwd_NTT2x2(r_init) + r_from_ntt2x2 = inv_NTT2x2(r_in_ntt2x2) + #check 2x2 architecture + if (r_in_ntt != r_in_ntt2x2): + print("Error in ntt2x2 model") + if (r_from_ntt2x2 != r_init): + print("Error in inv_ntt2x2 model") + + #using 2x2 div2 architecture + r_from_ntt2x2_div2 = inv_NTT2x2_div2(r_in_ntt2x2) + #check 2x2 div2 architecture + if (r_from_ntt2x2_div2 != r_init): + print("Error in inv_ntt2x2 div2 model") + + +print_table("r_init=", r_init, rows=16, cols=16) +print_table("r_in_ntt=", r_in_ntt, rows=16, cols=16) +print_table("r_in_ntt2x2=", r_in_ntt2x2, rows=16, cols=16) +print_table("r_from_ntt=", r_from_ntt, rows=16, cols=16) +print_table("r_from_ntt2x2=", r_from_ntt2x2, rows=16, cols=16) +print_table("r_from_ntt2x2_div2=", r_from_ntt2x2_div2, rows=16, cols=16) diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_top_masking_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_top_masking_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..409a536504da613b133504ad9ad02d44200b2daa --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_top_masking_tb.sv @@ -0,0 +1,618 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_top_masking_tb.sv +// -------- +//====================================================================== + +`default_nettype none + +module ntt_top_masking_tb + + import ntt_defines_pkg::*; + import mldsa_params_pkg::*; + +#( + parameter TEST_VECTOR_NUM = 10, + parameter PRIME = 23'd8380417, + parameter REG_SIZE = 23, + parameter MEM_DEPTH = 32768, //32 KB + parameter MEM_ADDR_WIDTH = $clog2(MEM_DEPTH) +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg [31 : 0] cycle_ctr; +reg [31 : 0] error_ctr; +reg [31 : 0] tc_ctr; + +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg enable_tb; +reg bf_ready_tb; + +mode_t mode_tb; + +reg [23:0] zeta [255:0]; +reg [23:0] zeta_inv [255:0]; + +string operation; + +logic sub; +logic [45:0] actual_u, actual_v, actual_w; +logic [1:0][45:0] u; +logic [1:0][45:0] v; +logic [1:0][45:0] w; +logic [45:0] rnd0, rnd1, rnd2, rnd3; +logic wren_tb, rden_tb; +logic [1:0] wrptr_tb, rdptr_tb; +logic [5:0] random_tb; +bf_uvwi_t uvw_i_tb; +masked_bf_uvwi_t masked_uvw_i_tb; +pwo_uvwi_t pw_uvw_i_tb; +hybrid_bf_uvwi_t hybrid_uvw_i_tb; +bf_uvo_t uv_o_tb; +logic [REG_SIZE-1:0] u10, u11, v10, v11; +//---------------------------------------------------------------- +// Device Under Test. +//---------------------------------------------------------------- + +// ntt_masked_BFU_add_sub dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .sub(sub), +// .u(u), +// .v(v), +// .rnd0(rnd0), +// .rnd1(rnd1), +// .rnd2(rnd2), +// .rnd3(rnd3), +// .res() +// ); + +// ntt_masked_BFU_mult dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .u(u), +// .v(v), +// .rnd0(rnd0), +// .rnd1(rnd1), +// .rnd2(rnd2), +// .rnd3(rnd3), +// .rnd4(rnd0+rnd1), +// .res() +// ); + +// ntt_masked_pwm dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .u(u), +// .v(v), +// .w(w), +// .accumulate(1'b1), +// .rnd({rnd0+rnd1, rnd3, rnd2, rnd1, rnd0}), +// .res() +// ); + +// ntt_masked_butterfly1x2 dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .uvw_i(masked_uvw_i_tb), +// .rnd_i({rnd0+rnd1, rnd3, rnd2, rnd1, rnd0}), +// .uv_o() +// ); + +// ntt_masked_gs_butterfly dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .opu_i(u), +// .opv_i(v), +// .opw_i(w), +// .rnd_i({rnd0+rnd1, rnd3, rnd2, rnd1, rnd0}), +// .u_o(), +// .v_o() +// ); + +ntt_hybrid_butterfly_2x2 dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .mode(mode_tb), + .enable(enable_tb), + .masking_en(1'b1), + .uvw_i(uvw_i_tb), + .pw_uvw_i(pw_uvw_i_tb), + .hybrid_pw_uvw_i(), + .rnd_i({rnd0+rnd1, rnd3, rnd2, rnd1, rnd0}), + .accumulate(1'b0), + .uv_o(), + .pwo_uv_o(), + .ready_o() +); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; + rnd0 = $random(); + rnd1 = $random(); + rnd2 = $random(); + rnd3 = $random(); +end // clk_gen + +//---------------------------------------------------------------- +// sys_monitor() +// +// An always running process that creates a cycle counter and +// conditionally displays information about the DUT. +//---------------------------------------------------------------- +always +begin : sys_monitor + #(CLK_PERIOD); + cycle_ctr = cycle_ctr + 1; +end + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + // cptra_pwrgood_tb = '0; + reset_n_tb = 0; + + // #(2 * CLK_PERIOD); + // cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + +//---------------------------------------------------------------- +// init_sim() +// +// Initialize all counters and testbed functionality as well +// as setting the DUT inputs to defined values. +//---------------------------------------------------------------- +task init_sim; + int i; + begin + $display("Start of init\n"); + cycle_ctr = 32'h00000000; + error_ctr = 32'h00000000; + tc_ctr = 32'h00000000; + + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + + zeroize_tb = 'b0; + enable_tb = 'b0; + wren_tb = 'b0; rden_tb = 'b0; + wrptr_tb = 'h0; rdptr_tb = 'h0; + + mode_tb = ct; + + //NTT ctrl + bf_ready_tb = 1'b0; + random_tb <= 'h0; + + //Masking + for (int i = 0; i < 46; i++) begin + u[i] = 2'h0; + v[i] = 2'h0; + end + actual_u = 'h0; + actual_v = 'h0; + actual_w = 'h0; + sub = 'h0; + + rnd0 = 'h0; + rnd1 = 'h0; + rnd2 = 'h0; + rnd3 = 'h0; + + uvw_i_tb.u00_i = 'h0; + uvw_i_tb.u01_i = 'h0; + uvw_i_tb.v00_i = 'h0; + uvw_i_tb.v01_i = 'h0; + uvw_i_tb.w00_i = 'h0; + uvw_i_tb.w01_i = 'h0; + uvw_i_tb.w10_i = 'h0; + uvw_i_tb.w11_i = 'h0; + + pw_uvw_i_tb.u0_i = 'h0; + pw_uvw_i_tb.v0_i = 'h0; + pw_uvw_i_tb.w0_i = 'h0; + + pw_uvw_i_tb.u1_i = 'h0; + pw_uvw_i_tb.v1_i = 'h0; + pw_uvw_i_tb.w1_i = 'h0; + + pw_uvw_i_tb.u2_i = 'h0; + pw_uvw_i_tb.v2_i = 'h0; + pw_uvw_i_tb.w2_i = 'h0; + + pw_uvw_i_tb.u3_i = 'h0; + pw_uvw_i_tb.v3_i = 'h0; + pw_uvw_i_tb.w3_i = 'h0; + + hybrid_uvw_i_tb.u0_i = 'h0; + hybrid_uvw_i_tb.u1_i = 'h0; + hybrid_uvw_i_tb.u2_i = 'h0; + hybrid_uvw_i_tb.u3_i = 'h0; + + hybrid_uvw_i_tb.v0_i = 'h0; + hybrid_uvw_i_tb.v1_i = 'h0; + hybrid_uvw_i_tb.v2_i = 'h0; + hybrid_uvw_i_tb.v3_i = 'h0; + + hybrid_uvw_i_tb.w0_i = 'h0; + hybrid_uvw_i_tb.w1_i = 'h0; + hybrid_uvw_i_tb.w2_i = 'h0; + hybrid_uvw_i_tb.w3_i = 'h0; + + hybrid_uvw_i_tb.twiddle_w0_i = 'h0; + hybrid_uvw_i_tb.twiddle_w1_i = 'h0; + hybrid_uvw_i_tb.twiddle_w2_i = 'h0; + hybrid_uvw_i_tb.twiddle_w3_i = 'h0; + + masked_uvw_i_tb = {'h0, 'h0, 'h0, 'h0, 'h0, 'h0}; + + u10 = 'h0; + u11 = 'h0; + v10 = 'h0; + v11 = 'h0; + + $display("End of init\n"); + end +endtask + +/* +task masked_BFU_adder_test(); + logic [45:0] u_array, v_array; + logic [45:0] rand0, rand1; + sub = 1; + for (int i = 0; i < 1000; i++) begin + @(posedge clk_tb); + fork + begin + actual_u = $random()%PRIME; + actual_v = $random()%PRIME; + u_array = actual_u; + v_array = actual_v; + rand0 = $random()%PRIME; + rand1 = $random()%PRIME; + + u[0] = actual_u-rand0; + u[1] = rand0; + v[0] = actual_v-rand1; + v[1] = rand1; + // $display("u0 = %h, u1 = %h, v0 = %h, v1 = %h", u[0], u[1], v[0], v[1]); + end + begin + repeat(54) @(posedge clk_tb); + if (!sub) begin + if ((dut.add_res_reduced[1] + dut.add_res_reduced[0]) != ((u_array + v_array)%PRIME)) begin + $error("Addition Mismatch: exp_output = %h output shares = %h %h actual output = %h", (u_array + v_array)%PRIME, dut.add_res_reduced[0], dut.add_res_reduced[1], dut.add_res_reduced[0] + dut.add_res_reduced[1]); + end + end + else begin + if ((dut.add_res_reduced[1] + dut.add_res_reduced[0]) != ((u_array - v_array + PRIME)%PRIME)) begin + $error("Subtraction Mismatch: exp_output = %h output shares = %h %h actual output = %h", (u_array + PRIME + (~v_array+'h1))%PRIME, dut.add_res_reduced[0], dut.add_res_reduced[1], dut.add_res_reduced[0] + dut.add_res_reduced[1]); + end + end + end + join + end +endtask + + +task masked_BFU_mult_test(); + logic [45:0] u_array, v_array; + logic [45:0] rand0, rand1; + + for (int i = 0; i < 10; i++) begin + @(posedge clk_tb); + fork + begin + actual_u = $random()%PRIME; + actual_v = $random()%PRIME; + u_array = actual_u; + v_array = actual_v; + rand0 = $random()%PRIME; + rand1 = $random()%PRIME; + + // $display("actual u = %h, actual v = %h", actual_u, actual_v); + + u[0] = actual_u-rand0; + u[1] = rand0; + v[0] = actual_v-rand1; + v[1] = rand1; + // $display("u0 = %h, u1 = %h, v0 = %h, v1 = %h", u[0], u[1], v[0], v[1]); + end + begin + repeat(210) @(posedge clk_tb); + if ((dut.final_res[1] + dut.final_res[0]) != ((u_array * v_array)%PRIME)) begin + $error("Multiplication Mismatch: exp_output = %h output shares = %h %h actual output = %h", (u_array * v_array)%PRIME, dut.final_res[0], dut.final_res[1], dut.final_res[0] + dut.final_res[1]); + end + end + join + end +endtask +*/ + + +// task masked_gs_butterfly_test(); +// logic [45:0] rand0, rand1, rand2; +// logic [45:0] actual_u_normalized; +// for (int i = 0; i < 10; i++) begin +// @(posedge clk_tb); +// fork +// begin +// actual_u = $random()%PRIME; +// actual_v = $random()%PRIME; +// actual_w = 'h2; +// if (actual_u < actual_v) +// actual_u_normalized = actual_u + PRIME; +// else +// actual_u_normalized = actual_u; +// // u_array = actual_u; +// // v_array = actual_v; +// rand0 = $random()%PRIME; +// rand1 = $random()%PRIME; +// rand2 = $random()%PRIME; + +// // $display("actual u = %h, actual v = %h", actual_u, actual_v); + +// u[0] = actual_u-rand0; +// u[1] = rand0; +// v[0] = actual_v-rand1; +// v[1] = rand1; +// w[0] = actual_w-rand2; +// w[1] = rand2; +// // $display("u0 = %h, u1 = %h, v0 = %h, v1 = %h", u[0], u[1], v[0], v[1]); +// end +// begin +// repeat(264) @(posedge clk_tb); +// if ((dut.u_o_0 + dut.u_o_1) != ((actual_u_normalized + actual_v)%PRIME)) begin +// $error("U = u+v Mismatch: exp_output = %h output shares = %h %h actual output = %h", (actual_u_normalized + actual_v)%PRIME, dut.u_o_0, dut.u_o_1, dut.u_o_0 + dut.u_o_1); +// end +// if ((dut.v_o_0 + dut.v_o_1) != (((actual_u_normalized - actual_v)*actual_w)%PRIME)) begin +// $error("V = (u-v)w Mismatch: exp_output = %h output shares = %h %h actual output = %h", ((actual_u_normalized - actual_v)*actual_w)%PRIME, dut.v_o_0, dut.v_o_1, dut.v_o_0 + dut.v_o_1); +// end +// end +// join +// end +// endtask + +/* +task masked_pwm_test(); + logic [45:0] rand0, rand1, rand2; + for (int i = 0; i < 10; i++) begin + @(posedge clk_tb); + fork + begin + actual_u = $random()%PRIME; + actual_v = $random()%PRIME; + actual_w = 'h2; + + // u_array = actual_u; + // v_array = actual_v; + rand0 = $random()%PRIME; + rand1 = $random()%PRIME; + rand2 = $random()%PRIME; + + // $display("actual u = %h, actual v = %h", actual_u, actual_v); + + u[0] = actual_u-rand0; + u[1] = rand0; + v[0] = actual_v-rand1; + v[1] = rand1; + w[0] = actual_w-rand2; + w[1] = rand2; + // $display("u0 = %h, u1 = %h, v0 = %h, v1 = %h", u[0], u[1], v[0], v[1]); + end + begin + repeat(264) @(posedge clk_tb); + if ((dut.res[0] + dut.res[1]) != ((((actual_u * actual_v)%PRIME)+actual_w) % PRIME)) begin + $error("U = u*v+w Mismatch: exp_output = %h output shares = %h %h actual output = %h", ((((actual_u * actual_v)%PRIME)+actual_w) % PRIME), dut.res[0], dut.res[1], dut.res[0] + dut.res[1]); + end + end + join + end +endtask +*/ + +task div2(logic [REG_SIZE-1:0] in, output logic [REG_SIZE-1:0] out); + if (in[0]) begin + out = (in >> 1) + ((PRIME+1)/2); + end + else begin + out = (in >> 1); + end +endtask +/* +task masked_bfu_1x2_test(); + logic [45:0] rand0, rand1, rand2; + logic [REG_SIZE:0] temp; + for (int i = 0; i < 10; i++) begin + @(posedge clk_tb); + fork + begin + actual_u = $random()%PRIME; + actual_v = $random()%PRIME; + actual_w = 'h2; + + // u_array = actual_u; + // v_array = actual_v; + rand0 = $random()%PRIME; + rand1 = $random()%PRIME; + rand2 = $random()%PRIME; + + $display("actual u = %h, actual v = %h", actual_u, actual_v); + + u[0] = actual_u-rand0; + u[1] = rand0; + v[0] = actual_v-rand1; + v[1] = rand1; + w[0] = actual_w-rand2; + w[1] = rand2; + + masked_uvw_i_tb.u00_i = u; + masked_uvw_i_tb.u01_i = u; + masked_uvw_i_tb.v00_i = v; + masked_uvw_i_tb.v01_i = v; + masked_uvw_i_tb.w00_i = w; + masked_uvw_i_tb.w01_i = w; + // $display("u0 = %h, u1 = %h, v0 = %h, v1 = %h", u[0], u[1], v[0], v[1]); + end + begin + repeat(267) @(posedge clk_tb); + $display("actual u = %h, actual v = %h", actual_u, actual_v); + u10 = (actual_u+actual_v)%PRIME; + if (actual_u < actual_v) + temp = actual_u + PRIME; + else + temp = actual_u; + v10 = (((temp-actual_v)%PRIME)*actual_w)%PRIME; + $display("u10 = %h", u10); + $display("v10 = %h", v10); + $display("----------"); + div2(u10, uv_o_tb.u20_o); + div2(v10, uv_o_tb.u21_o); + div2(u10, uv_o_tb.v20_o); //since same inputs + div2(v10, uv_o_tb.v21_o); + + if (dut.uv_o != uv_o_tb) + $error("Data mismatch. Expected = {%h, %h, %h, %h}, Observed = {%h, %h, %h, %h}", uv_o_tb.u20_o, uv_o_tb.u21_o, uv_o_tb.v20_o, uv_o_tb.v21_o, dut.uv_o.u20_o, dut.uv_o.u21_o, dut.uv_o.v20_o, dut.uv_o.v21_o); + else + $display("Success: Matched results"); + end + join + end +endtask +*/ + +task masked_hybrid_bf_2x2_test(); + logic [45:0] rand0, rand1, rand2; + for (int j = 0; j < 6; j++) begin + mode_tb = j; + for (int i = 0; i < 10; i++) begin + @(posedge clk_tb); + enable_tb = 1'b1; + fork + begin + actual_u = $random()%PRIME; + actual_v = $random()%PRIME; + actual_w = 'h2; + + // u_array = actual_u; + // v_array = actual_v; + rand0 = $random()%PRIME; + rand1 = $random()%PRIME; + rand2 = $random()%PRIME; + + // $display("actual u = %h, actual v = %h", actual_u, actual_v); + + u[0] = actual_u-rand0; + u[1] = rand0; + v[0] = actual_v-rand1; + v[1] = rand1; + w[0] = actual_w-rand2; + w[1] = rand2; + + uvw_i_tb.u00_i = actual_u; + uvw_i_tb.u01_i = actual_u; + uvw_i_tb.v00_i = actual_v; + uvw_i_tb.v01_i = actual_v; + uvw_i_tb.w00_i = actual_w; + uvw_i_tb.w01_i = actual_w; + uvw_i_tb.w10_i = actual_w; + uvw_i_tb.w11_i = actual_w; + + pw_uvw_i_tb.u0_i = actual_u; + pw_uvw_i_tb.v0_i = actual_v; + pw_uvw_i_tb.w0_i = actual_w; + + pw_uvw_i_tb.u1_i = actual_u; + pw_uvw_i_tb.v1_i = actual_v; + pw_uvw_i_tb.w1_i = actual_w; + + pw_uvw_i_tb.u2_i = actual_u; + pw_uvw_i_tb.v2_i = actual_v; + pw_uvw_i_tb.w2_i = actual_w; + + pw_uvw_i_tb.u3_i = actual_u; + pw_uvw_i_tb.v3_i = actual_v; + pw_uvw_i_tb.w3_i = actual_w; + //$display("u0 = %h, u1 = %h, v0 = %h, v1 = %h", u[0], u[1], v[0], v[1]); + end + // begin //TODO + // repeat(470) @(posedge clk_tb); //467 clks + // if ((dut.res[0] + dut.res[1]) != ((((actual_u * actual_v)%PRIME)+actual_w) % PRIME)) begin + // $error("U = u*v+w Mismatch: exp_output = %h output shares = %h %h actual output = %h", ((((actual_u * actual_v)%PRIME)+actual_w) % PRIME), dut.res[0], dut.res[1], dut.res[0] + dut.res[1]); + // end + // end + join + end + enable_tb = 1'b0; + @(posedge clk_tb); + end +endtask + + +initial begin + init_sim(); + reset_dut(); + + @(posedge clk_tb); + $display("Starting masked ntt test\n"); + + // masked_BFU_adder_test(); + // masked_BFU_mult_test(); + // masked_gs_butterfly_test(); + // masked_pwm_test(); + masked_bfu_1x2_test(); + // masked_hybrid_bf_2x2_test(); + + repeat(1000) @(posedge clk_tb); + $finish; +end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_top_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_top_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..572b2f72ecd6892984505ca6faaee2a1088f0df8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_top_tb.sv @@ -0,0 +1,683 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_top_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module ntt_top_tb + + import ntt_defines_pkg::*; + import mldsa_params_pkg::*; + +#( + parameter TEST_VECTOR_NUM = 10, + parameter PRIME = 23'd8380417, + parameter REG_SIZE = 23, + parameter MEM_DEPTH = 32768, //32 KB + parameter MEM_ADDR_WIDTH = $clog2(MEM_DEPTH) +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg [31 : 0] cycle_ctr; +reg [31 : 0] error_ctr; +reg [31 : 0] tc_ctr; + +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg enable_tb; +reg bf_ready_tb; +reg [(4*REG_SIZE)-1:0] data_i_tb, data_o_tb; + +reg [7:0] addr0, addr1, addr2, addr3; +mode_t mode_tb; +reg [REG_SIZE-1:0] data0, data1, data2, data3; + +reg [23:0] zeta [255:0]; +reg [23:0] zeta_inv [255:0]; +reg [(4*(REG_SIZE+1))-1:0] ntt_mem_tb [63:0]; + +reg load_tb_values; +reg [MLDSA_MEM_ADDR_WIDTH-1:0] load_tb_addr; + +reg [7:0] src_base_addr, interim_base_addr, dest_base_addr; +reg acc_tb, svalid_tb, sampler_mode_tb; +reg ntt_done_tb; + +ntt_mem_addr_t ntt_mem_base_addr_tb; +pwo_mem_addr_t pwo_mem_base_addr_tb; + +string operation; + +logic sub; +logic [45:0] actual_u, actual_v, actual_w; +logic [1:0][45:0] u; +logic [1:0][45:0] v; +logic [1:0][45:0] w; +logic [45:0] rnd0, rnd1, rnd2, rnd3; +logic wren_tb, rden_tb; +logic [1:0] wrptr_tb, rdptr_tb; +logic [5:0] random_tb; +bf_uvwi_t uvw_i_tb; +pwo_uvwi_t pw_uvw_i_tb; +logic masking_en_tb; + +//---------------------------------------------------------------- +// Device Under Test. +//---------------------------------------------------------------- +// ntt_buffer #( +// .REG_SIZE(REG_SIZE), +// .NUM_COEFF(4) +// ) dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .enable(enable_tb), +// .data_i(data_i_tb), +// .data_o(data_o_tb) +// ); + +// twiddle_rom dut ( +// .zeroize(), +// .mode (mode_tb), +// .raddr00(addr0), +// .raddr01(addr1), +// .raddr10(addr2), +// .raddr11(addr3), +// .rdata00(data0), +// .rdata01(data1), +// .rdata10(data2), +// .rdata11(data3) +// ); + +// ntt_ctrl dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .ntt_mode(mode_tb), +// .ntt_enable(enable_tb), +// .butterfly_ready(bf_ready_tb) +// ); + +// ntt_top dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .mode(mode_tb), +// .ntt_enable(enable_tb), +// .load_tb_values(load_tb_values), +// .load_tb_addr(load_tb_addr), +// // .src_base_addr(src_base_addr), +// // .interim_base_addr(interim_base_addr), +// // .dest_base_addr(dest_base_addr), +// // .pw_base_addr_a(8'd0), +// // .pw_base_addr_b(8'd0), +// // .pw_base_addr_c(8'd0), +// .ntt_mem_base_addr(ntt_mem_base_addr_tb), +// .pwo_mem_base_addr(pwo_mem_base_addr_tb), +// .accumulate(acc_tb), +// .sampler_valid(svalid_tb) +// ); + +ntt_wrapper dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .mode(mode_tb), + .ntt_enable(enable_tb), + .load_tb_values(load_tb_values), + .load_tb_addr(load_tb_addr), + .shuffle_en(1'b1), + .random(random_tb), + .masking_en(masking_en_tb), + .rnd_i(230'h0), + .ntt_mem_base_addr(ntt_mem_base_addr_tb), + .pwo_mem_base_addr(pwo_mem_base_addr_tb), + .accumulate(acc_tb), + .sampler_valid(svalid_tb), + .sampler_mode(sampler_mode_tb), + .sampler_data(96'hFFFFFF), + .ntt_done(ntt_done_tb), + .ntt_busy() +); + +// ntt_shuffle_buffer dut ( +// .clk(clk_tb), +// .reset_n(reset_n_tb), +// .zeroize(zeroize_tb), +// .wren(wren_tb), +// .rden(rden_tb), +// .wrptr(wrptr_tb), +// .rdptr(rdptr_tb), +// .wr_rst_count(), +// .data_i(data_i_tb), +// .buf_valid(), +// .data_o() +// ); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; + rnd0 = $random(); + rnd1 = $random(); + rnd2 = $random(); + rnd3 = $random(); +end // clk_gen + +//---------------------------------------------------------------- +// sys_monitor() +// +// An always running process that creates a cycle counter and +// conditionally displays information about the DUT. +//---------------------------------------------------------------- +always +begin : sys_monitor + #(CLK_PERIOD); + cycle_ctr = cycle_ctr + 1; +end + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + // cptra_pwrgood_tb = '0; + reset_n_tb = 0; + + // #(2 * CLK_PERIOD); + // cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + +//---------------------------------------------------------------- +// init_sim() +// +// Initialize all counters and testbed functionality as well +// as setting the DUT inputs to defined values. +//---------------------------------------------------------------- +task init_sim; + int i; + begin + $display("Start of init\n"); + cycle_ctr = 32'h00000000; + error_ctr = 32'h00000000; + tc_ctr = 32'h00000000; + + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + + data_i_tb = 'h0; + zeroize_tb = 'b0; + enable_tb = 'b0; + wren_tb = 'b0; rden_tb = 'b0; + wrptr_tb = 'h0; rdptr_tb = 'h0; + + mode_tb = ct; + addr0 = 'h0; addr1 = 'h0; addr2 = 'h0; addr3 = 'h0; + + ntt_mem_base_addr_tb.src_base_addr = 'h0; + ntt_mem_base_addr_tb.interim_base_addr = 'h0; + ntt_mem_base_addr_tb.dest_base_addr = 'h0; + + pwo_mem_base_addr_tb.pw_base_addr_a = 'h0; + pwo_mem_base_addr_tb.pw_base_addr_b = 'h40; + pwo_mem_base_addr_tb.pw_base_addr_c = 'h80; + + //NTT ctrl + bf_ready_tb = 1'b0; + acc_tb = 1'b0; + svalid_tb = 1'b0; + sampler_mode_tb = 1'b0; + random_tb <= 'h0; + + //Masking + for (int i = 0; i < 46; i++) begin + u[i] = 2'h0; + v[i] = 2'h0; + end + actual_u = 'h0; + actual_v = 'h0; + actual_w = 'h0; + sub = 'h0; + + rnd0 = 'h0; + rnd1 = 'h0; + rnd2 = 'h0; + rnd3 = 'h0; + + uvw_i_tb.u00_i = 'h0; + uvw_i_tb.u01_i = 'h0; + uvw_i_tb.v00_i = 'h0; + uvw_i_tb.v01_i = 'h0; + uvw_i_tb.w00_i = 'h0; + uvw_i_tb.w01_i = 'h0; + + pw_uvw_i_tb.u0_i = 'h0; + pw_uvw_i_tb.v0_i = 'h0; + pw_uvw_i_tb.w0_i = 'h0; + + pw_uvw_i_tb.u1_i = 'h0; + pw_uvw_i_tb.v1_i = 'h0; + pw_uvw_i_tb.w1_i = 'h0; + + pw_uvw_i_tb.u2_i = 'h0; + pw_uvw_i_tb.v2_i = 'h0; + pw_uvw_i_tb.w2_i = 'h0; + + pw_uvw_i_tb.u3_i = 'h0; + pw_uvw_i_tb.v3_i = 'h0; + pw_uvw_i_tb.w3_i = 'h0; + + masking_en_tb = 'b0; + + $display("End of init\n"); + end +endtask + +task buffer_test(); + reg [REG_SIZE-1:0] i; + reg [1:0] j; + wren_tb <= 1'b1; + rden_tb <= 'b1; + for (i = 0; i < 64; i++) begin + // data_i_tb <= {(i*23'd64)+23'd192, (i*23'd64)+23'd128, (i*23'd64)+23'd64, (i*23'd64)}; + wrptr_tb <= i%4; + j = $urandom_range(3); + rdptr_tb <= (i%4)+j; + data_i_tb <= {(i*23'd64)+23'd3, (i*23'd64)+23'd2, (i*23'd64)+23'd1, i*23'd64}; //{23'd3, 23'd2, 23'd1, 23'd0}; + @(posedge clk_tb); + end + wren_tb <= 1'b0; + rden_tb <= 'b0; +endtask + +task twiddle_rom_test(); + int i; + for(i = 0; i < 256; i++) begin + addr0 <= i; addr1 <= i; addr2 <= i; addr3 <= i; + if (data0 != zeta[i]) + $display("Error, test failed while reading NTT twiddle rom at index %0d, observed value = %h, actual value = %h", i, data0, zeta[i]); + // if (data1 != zeta[i]) + // $display("Error, test failed while reading NTT twiddle rom at index %0d", i); + // if (data2 != zeta[i]) + // $display("Error, test failed while reading NTT twiddle rom at index %0d", i); + // if (data3 != zeta[i]) + // $display("Error, test failed while reading NTT twiddle rom at index %0d", i); + + // @(posedge clk_tb); + end + mode_tb <= gs; + for(i = 0; i < 256; i++) begin + addr0 <= i; addr1 <= i; addr2 <= i; addr3 <= i; + if (data0 != zeta_inv[i]) + $display("Error, test failed while reading INTT twiddle rom at index %0d, observed value = %h, actual value = %h", i, data0, zeta_inv[i]); + // if (data1 != zeta_inv[i]) + // $display("Error, test failed while reading INTT twiddle rom at index %0d", i); + // if (data2 != zeta_inv[i]) + // $display("Error, test failed while reading INTT twiddle rom at index %0d", i); + // if (data3 != zeta_inv[i]) + // $display("Error, test failed while reading INTT twiddle rom at index %0d", i); + // @(posedge clk_tb); + end + @(posedge clk_tb); +endtask + +task ntt_ctrl_test(); + mode_tb = ct; + enable_tb = 1; + repeat(16) @(posedge clk_tb); //IDLE - STAGE - RD MEM - RD AND EXE = 1 + 1 + 4 + 10 = 16 clk delay + bf_ready_tb = 1'b1; + repeat(64) @(posedge clk_tb); + bf_ready_tb = 1'b0; + repeat(10) @(posedge clk_tb); + bf_ready_tb = 1'b1; + repeat(64) @(posedge clk_tb); + bf_ready_tb = 1'b0; +endtask + +task ntt_top_test(); + fork + begin + while(1) begin + random_tb <= $urandom(); + @(posedge clk_tb); + end + end + begin + $display("NTT operation\n"); + operation = "NTT"; + mode_tb = ct; + enable_tb = 1; + ntt_mem_base_addr_tb.src_base_addr = 8'd0; + ntt_mem_base_addr_tb.interim_base_addr = 8'd64; + ntt_mem_base_addr_tb.dest_base_addr = 8'd128; + acc_tb = 1'b0; + svalid_tb = 1'b1; + @(posedge clk_tb); + enable_tb = 1'b0; + + $display("Waiting for ntt_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received ntt_done\n"); + + + $display("INTT operation\n"); + operation = "INTT"; + mode_tb = gs; + enable_tb = 1; + ntt_mem_base_addr_tb.src_base_addr = 8'd128; //read from addr where ntt stored its results + ntt_mem_base_addr_tb.interim_base_addr = 8'd64; + ntt_mem_base_addr_tb.dest_base_addr = 8'd128; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for intt_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received intt_done\n"); + + $display("PWM operation 1\n"); + operation = "PWM 1 no acc"; + // $readmemh("pwm_iter1.hex", ntt_mem_tb); + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + // for (int i = 0; i < 64; i++) begin + // if (dut.pwm_mem_c.mem[i+0] != ntt_mem_tb[i]) + // $display("Error: PWM data mismatch at index %0d (pw_base_addr_c = %0d). Actual data = %h, expected data = %h", i, 0, dut.pwm_mem_c.mem[i+0], ntt_mem_tb[i]); + // @(posedge clk_tb); + // end + + + $display("PWM operation 2\n"); + operation = "PWM 2 no acc"; + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWM operation 3\n"); + operation = "PWM 3 acc"; + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b1; + $readmemh("pwm_iter2.hex", ntt_mem_tb); + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + // $readmemh("pwm_iter2.hex", ntt_mem_tb); + // for (int i = 0; i < 64; i++) begin + // if (dut.pwm_mem_c.mem[i+0] != ntt_mem_tb[i]) + // $display("Error: PWM data mismatch at index %0d (pw_base_addr_c = %0d). Actual data = %h, expected data = %h", i, 0, dut.pwm_mem_c.mem[i+0], ntt_mem_tb[i]); + // @(posedge clk_tb); + // end + + $display("PWA operation 1\n"); + operation = "PWA 1"; + mode_tb = pwa; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWA operation 2\n"); + operation = "PWA 2"; + mode_tb = pwa; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWA operation 3\n"); + operation = "PWA 3"; + mode_tb = pwa; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWS operation 1\n"); + operation = "PWS 1"; + mode_tb = pws; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWS operation 2\n"); + operation = "PWS 2"; + mode_tb = pws; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWS operation 3\n"); + operation = "PWS 3"; + mode_tb = pws; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + svalid_tb = 1'b0; + @(posedge clk_tb); + + + + $display("PWM + sampler operation 1\n"); + operation = "PWM sampler"; + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b0; + sampler_mode_tb = 1'b1; + repeat(2) @(posedge clk_tb); + svalid_tb <= 1'b1; + @(posedge clk_tb); + enable_tb = 1'b0; + repeat(10) @(posedge clk_tb); + svalid_tb <= 1'b0; + repeat(10) @(posedge clk_tb); + svalid_tb <= 1'b1; + repeat(10) @(posedge clk_tb); + svalid_tb <= 1'b0; + repeat(10) @(posedge clk_tb); + svalid_tb <= 1'b1; + repeat(45) @(posedge clk_tb); + svalid_tb <= 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + $display("PWM+INTT operation\n"); + operation = "PWM INTT"; + mode_tb = pwm_intt; + enable_tb = 1; + acc_tb = 1'b0; + svalid_tb = 1'b1; + masking_en_tb = 1'b1; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + svalid_tb = 1'b0; + @(posedge clk_tb); + + end + join_any + $display("End of test\n"); +endtask +/* +task pwm_opt_test(); + $display("PWM operation 1\n"); + $readmemh("pwm_iter1.hex", ntt_mem_tb); + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b0; + svalid_tb = 1'b1; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for rd_exec\n"); + while(dut.ntt_top_inst0.ntt_ctrl_inst0.read_fsm_state_ps != RD_EXEC) + @(posedge clk_tb); + $display("Waiting for rd_stage\n"); + while(dut.ntt_top_inst0.ntt_ctrl_inst0.read_fsm_state_ps != RD_STAGE) + @(posedge clk_tb); + $display("Read fsm transitioned to rd_stage state. Queuing next pwm\n"); + + // for (int i = 0; i < 64; i++) begin + // if (dut.pwm_mem_c.mem[i+0] != ntt_mem_tb[i]) + // $display("Error: PWM data mismatch at index %0d (pw_base_addr_c = %0d). Actual data = %h, expected data = %h", i, 0, dut.pwm_mem_c.mem[i+0], ntt_mem_tb[i]); + // @(posedge clk_tb); + // end + + + $display("PWM operation 2\n"); + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b0; + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for rd_exec\n"); + while(dut.ntt_top_inst0.ntt_ctrl_inst0.read_fsm_state_ps != RD_EXEC) + @(posedge clk_tb); + $display("Waiting for rd_stage\n"); + while(dut.ntt_top_inst0.ntt_ctrl_inst0.read_fsm_state_ps != RD_STAGE) + @(posedge clk_tb); + $display("Read fsm transitioned to rd_stage state. Queuing next pwm\n"); + + $display("PWM operation 3\n"); + mode_tb = pwm; + enable_tb = 1; + acc_tb = 1'b1; + $readmemh("pwm_iter2.hex", ntt_mem_tb); + @(posedge clk_tb); + enable_tb = 1'b0; + $display("Waiting for pwo_done\n"); + while(ntt_done_tb == 1'b0) + @(posedge clk_tb); + $display("Received pwo_done\n"); + + for (int i = 0; i < 64; i++) begin + if (dut.ntt_mem.mem[i+0] != ntt_mem_tb[i]) + $display("Error: PWM data mismatch at index %0d (pw_base_addr_c = %0d). Actual data = %h, expected data = %h", i, 0, dut.ntt_mem.mem[i+0], ntt_mem_tb[i]); + @(posedge clk_tb); + end +endtask +*/ +task init_mem(); + for (int i = 0; i < 512; i++) begin + load_tb_addr = i; + load_tb_values = 1'b1; + @(posedge clk_tb); + end + load_tb_values = 1'b0; + load_tb_addr = 'h0; +endtask + +initial begin + init_sim(); + reset_dut(); + // $readmemh("zeta.txt", zeta); + // $readmemh("zeta_inv.hex", zeta_inv); + + @(posedge clk_tb); + $display("Starting init mem\n"); + init_mem(); + // $readmemh("ntt_stage67.hex", ntt_mem_tb); + @(posedge clk_tb); + // buffer_test(); + // twiddle_rom_test(); + // ntt_ctrl_test(); + $display("Starting ntt test\n"); + ntt_top_test(); + // pwm_opt_test(); + repeat(1000) @(posedge clk_tb); + $finish; +end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_wrapper.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_wrapper.sv new file mode 100644 index 0000000000000000000000000000000000000000..8a38573d932af56bdcc3058ea385023a0569c412 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/ntt_wrapper.sv @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// ntt_wrapper.sv +// Temp Top level that contains NTT and mem +// TODO: remove after top level NTT integration is done +//====================================================================== + +module ntt_wrapper + import ntt_defines_pkg::*; + import mldsa_params_pkg::*; +#( + parameter REG_SIZE = 24, + parameter RADIX = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_N = 256, + parameter MEM_ADDR_WIDTH = 14, + parameter MEM_DATA_WIDTH = 96 +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + + input mode_t mode, + input wire ntt_enable, + input wire shuffle_en, + input wire masking_en, + input wire [5:0] random, + input wire [4:0][45:0] rnd_i, + + //TB purpose - remove later TODO + input wire load_tb_values, + input wire [MEM_ADDR_WIDTH-1:0] load_tb_addr, + + input ntt_mem_addr_t ntt_mem_base_addr, + input pwo_mem_addr_t pwo_mem_base_addr, + input wire accumulate, + input wire sampler_valid, + input wire sampler_mode, + input wire [MEM_DATA_WIDTH-1:0] sampler_data, + output logic ntt_done, + output logic ntt_busy + +); + + //NTT, PWM C memory IF + mem_if_t mem_wr_req; + mem_if_t mem_rd_req; + logic [MEM_DATA_WIDTH-1:0] mem_wr_data; + logic [MEM_DATA_WIDTH-1:0] mem_rd_data; + + + //PWM A/B, PWA/S memory IF + mem_if_t pwm_a_rd_req; + mem_if_t pwm_b_rd_req; + logic [MEM_DATA_WIDTH-1:0] pwm_a_rd_data; + logic [MEM_DATA_WIDTH-1:0] pwm_b_rd_data; + + //NTT/PWM muxes + logic ntt_mem_wren, ntt_mem_rden; + logic [MEM_ADDR_WIDTH-1:0] ntt_mem_wr_addr; + logic [MEM_ADDR_WIDTH-1:0] ntt_mem_rd_addr; + logic [MEM_DATA_WIDTH-1:0] ntt_mem_wr_data; + logic [MEM_DATA_WIDTH-1:0] ntt_mem_rd_data; + + logic pwm_mem_a_rden, pwm_mem_b_rden; + + //Modes + logic ct_mode; + logic gs_mode; + logic pwo_mode; + logic pwm_mode, pwa_mode, pws_mode; + + assign ct_mode = (mode == ct); + assign gs_mode = (mode == gs); + assign pwo_mode = (mode inside {pwm, pwa, pws}); + assign pwm_mode = (mode == pwm); + assign pwa_mode = (mode == pwa); + assign pws_mode = (mode == pws); + + //NTT mem + assign ntt_mem_wren = (mem_wr_req.rd_wr_en == RW_WRITE); + assign ntt_mem_rden = (mem_rd_req.rd_wr_en == RW_READ); + // assign ntt_mem_wr_addr = (ct_mode | gs_mode) ? mem_wr_req.addr : pwm_mem_c_wr_addr; + // assign ntt_mem_rd_addr = (ct_mode | gs_mode) ? mem_rd_req.addr : pwm_mem_c_rd_addr; + // assign ntt_mem_wr_data = (ct_mode | gs_mode) ? mem_wr_data : pwm_mem_c_wr_data; + + //PWM mem + assign pwm_mem_a_rden = (pwm_a_rd_req.rd_wr_en == RW_READ); + assign pwm_mem_b_rden = (pwm_b_rd_req.rd_wr_en == RW_READ); + + ntt_ram_tdp_file #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(4*REG_SIZE) + ) ntt_mem ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .ena(ntt_mem_wren), + .wea(ntt_mem_wren), + .addra(mem_wr_req.addr), + .dina(mem_wr_data), + .douta(), //Need only one read port, so this can be 0 + .enb(ntt_mem_rden), + .web(1'b0), //Need only one write port so this can be 0 + .addrb(mem_rd_req.addr), + .dinb(), + .doutb(mem_rd_data), + .load_tb_values(load_tb_values), + .load_tb_addr(load_tb_addr) + ); + + ntt_ram_tdp_file #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(4*REG_SIZE) + ) pwm_mem_a ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .ena(), + .wea(), + .addra(), + .dina(), + .douta(), //Need only one read port, so this can be 0 + .enb(pwm_mem_a_rden), //(pw_rden_d1), + .web(1'b0), //Need only one write port so this can be 0 + .addrb(pwm_a_rd_req.addr), //(pwm_rd_addr_a_reg), + .dinb(), + .doutb(pwm_a_rd_data), + .load_tb_values(load_tb_values), + .load_tb_addr(load_tb_addr) + ); + + ntt_ram_tdp_file #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(4*REG_SIZE) + ) pwm_mem_b ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .ena(), + .wea(), + .addra(), + .dina(), + .douta(), //Need only one read port, so this can be 0 + .enb(pwm_mem_b_rden), //(pw_rden_d1), + .web(1'b0), //Need only one write port so this can be 0 + .addrb(pwm_b_rd_req.addr), //(pwm_rd_addr_b_reg), + .dinb(), + .doutb(pwm_b_rd_data), + .load_tb_values(load_tb_values), + .load_tb_addr(load_tb_addr) + ); + + ntt_top #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q), + .MLDSA_N(MLDSA_N), + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH) + ) + ntt_top_inst0 ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .mode(mode), + .ntt_enable(ntt_enable), + .ntt_mem_base_addr(ntt_mem_base_addr), + .pwo_mem_base_addr(pwo_mem_base_addr), + .accumulate(accumulate), + .sampler_valid(sampler_valid), + .shuffle_en(shuffle_en), + .masking_en(masking_en), + .random(random), + .rnd_i(rnd_i), + //NTT mem IF + .mem_wr_req(mem_wr_req), + .mem_rd_req(mem_rd_req), + .mem_wr_data(mem_wr_data), + .mem_rd_data(mem_rd_data), + //PWM mem IF + .pwm_a_rd_req(pwm_a_rd_req), + .pwm_b_rd_req(pwm_b_rd_req), + .pwm_a_rd_data(pwm_a_rd_data), + .pwm_b_rd_data(sampler_mode ? sampler_data : pwm_b_rd_data), + .ntt_busy(ntt_busy), + .ntt_done(ntt_done) + ); +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0.hex new file mode 100644 index 0000000000000000000000000000000000000000..68591f8d6c69a4827fd042b08d8067ab489e73cb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0.hex @@ -0,0 +1,64 @@ +000000 000040 000080 0000C0 +000001 000041 000081 0000C1 +000002 000042 000082 0000C2 +000003 000043 000083 0000C3 +000004 000044 000084 0000C4 +000005 000045 000085 0000C5 +000006 000046 000086 0000C6 +000007 000047 000087 0000C7 +000008 000048 000088 0000C8 +000009 000049 000089 0000C9 +00000A 00004A 00008A 0000CA +00000B 00004B 00008B 0000CB +00000C 00004C 00008C 0000CC +00000D 00004D 00008D 0000CD +00000E 00004E 00008E 0000CE +00000F 00004F 00008F 0000CF +000010 000050 000090 0000D0 +000011 000051 000091 0000D1 +000012 000052 000092 0000D2 +000013 000053 000093 0000D3 +000014 000054 000094 0000D4 +000015 000055 000095 0000D5 +000016 000056 000096 0000D6 +000017 000057 000097 0000D7 +000018 000058 000098 0000D8 +000019 000059 000099 0000D9 +00001A 00005A 00009A 0000DA +00001B 00005B 00009B 0000DB +00001C 00005C 00009C 0000DC +00001D 00005D 00009D 0000DD +00001E 00005E 00009E 0000DE +00001F 00005F 00009F 0000DF +000020 000060 0000A0 0000E0 +000021 000061 0000A1 0000E1 +000022 000062 0000A2 0000E2 +000023 000063 0000A3 0000E3 +000024 000064 0000A4 0000E4 +000025 000065 0000A5 0000E5 +000026 000066 0000A6 0000E6 +000027 000067 0000A7 0000E7 +000028 000068 0000A8 0000E8 +000029 000069 0000A9 0000E9 +00002A 00006A 0000AA 0000EA +00002B 00006B 0000AB 0000EB +00002C 00006C 0000AC 0000EC +00002D 00006D 0000AD 0000ED +00002E 00006E 0000AE 0000EE +00002F 00006F 0000AF 0000EF +000030 000070 0000B0 0000F0 +000031 000071 0000B1 0000F1 +000032 000072 0000B2 0000F2 +000033 000073 0000B3 0000F3 +000034 000074 0000B4 0000F4 +000035 000075 0000B5 0000F5 +000036 000076 0000B6 0000F6 +000037 000077 0000B7 0000F7 +000038 000078 0000B8 0000F8 +000039 000079 0000B9 0000F9 +00003A 00007A 0000BA 0000FA +00003B 00007B 0000BB 0000FB +00003C 00007C 0000BC 0000FC +00003D 00007D 0000BD 0000FD +00003E 00007E 0000BE 0000FE +00003F 00007F 0000BF 0000FF \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0_mem.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0_mem.hex new file mode 100644 index 0000000000000000000000000000000000000000..a316ab7cf7d4c1b4c985650aca08ee6cfc7c6747 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0_mem.hex @@ -0,0 +1,256 @@ +000003000002000001000000 +000007000006000005000004 +00000B00000A000009000008 +00000F00000E00000D00000C +000013000012000011000010 +000017000016000015000014 +00001B00001A000019000018 +00001F00001E00001D00001C +000023000022000021000020 +000027000026000025000024 +00002B00002A000029000028 +00002F00002E00002D00002C +000033000032000031000030 +000037000036000035000034 +00003B00003A000039000038 +00003F00003E00003D00003C +000043000042000041000040 +000047000046000045000044 +00004B00004A000049000048 +00004F00004E00004D00004C +000053000052000051000050 +000057000056000055000054 +00005B00005A000059000058 +00005F00005E00005D00005C +000063000062000061000060 +000067000066000065000064 +00006B00006A000069000068 +00006F00006E00006D00006C +000073000072000071000070 +000077000076000075000074 +00007B00007A000079000078 +00007F00007E00007D00007C +000083000082000081000080 +000087000086000085000084 +00008B00008A000089000088 +00008F00008E00008D00008C +000093000092000091000090 +000097000096000095000094 +00009B00009A000099000098 +00009F00009E00009D00009C +0000A30000A20000A10000A0 +0000A70000A60000A50000A4 +0000AB0000AA0000A90000A8 +0000AF0000AE0000AD0000AC +0000B30000B20000B10000B0 +0000B70000B60000B50000B4 +0000BB0000BA0000B90000B8 +0000BF0000BE0000BD0000BC +0000C30000C20000C10000C0 +0000C70000C60000C50000C4 +0000CB0000CA0000C90000C8 +0000CF0000CE0000CD0000CC +0000D30000D20000D10000D0 +0000D70000D60000D50000D4 +0000DB0000DA0000D90000D8 +0000DF0000DE0000DD0000DC +0000E30000E20000E10000E0 +0000E70000E60000E50000E4 +0000EB0000EA0000E90000E8 +0000EF0000EE0000ED0000EC +0000F30000F20000F10000F0 +0000F70000F60000F50000F4 +0000FB0000FA0000F90000F8 +0000FF0000FE0000FD0000FC +000003000002000001000000 +000007000006000005000004 +00000B00000A000009000008 +00000F00000E00000D00000C +000013000012000011000010 +000017000016000015000014 +00001B00001A000019000018 +00001F00001E00001D00001C +000023000022000021000020 +000027000026000025000024 +00002B00002A000029000028 +00002F00002E00002D00002C +000033000032000031000030 +000037000036000035000034 +00003B00003A000039000038 +00003F00003E00003D00003C +000043000042000041000040 +000047000046000045000044 +00004B00004A000049000048 +00004F00004E00004D00004C +000053000052000051000050 +000057000056000055000054 +00005B00005A000059000058 +00005F00005E00005D00005C +000063000062000061000060 +000067000066000065000064 +00006B00006A000069000068 +00006F00006E00006D00006C +000073000072000071000070 +000077000076000075000074 +00007B00007A000079000078 +00007F00007E00007D00007C +000083000082000081000080 +000087000086000085000084 +00008B00008A000089000088 +00008F00008E00008D00008C +000093000092000091000090 +000097000096000095000094 +00009B00009A000099000098 +00009F00009E00009D00009C +0000A30000A20000A10000A0 +0000A70000A60000A50000A4 +0000AB0000AA0000A90000A8 +0000AF0000AE0000AD0000AC +0000B30000B20000B10000B0 +0000B70000B60000B50000B4 +0000BB0000BA0000B90000B8 +0000BF0000BE0000BD0000BC +0000C30000C20000C10000C0 +0000C70000C60000C50000C4 +0000CB0000CA0000C90000C8 +0000CF0000CE0000CD0000CC +0000D30000D20000D10000D0 +0000D70000D60000D50000D4 +0000DB0000DA0000D90000D8 +0000DF0000DE0000DD0000DC +0000E30000E20000E10000E0 +0000E70000E60000E50000E4 +0000EB0000EA0000E90000E8 +0000EF0000EE0000ED0000EC +0000F30000F20000F10000F0 +0000F70000F60000F50000F4 +0000FB0000FA0000F90000F8 +0000FF0000FE0000FD0000FC +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 +000000000000000000000000 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0_out.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0_out.hex new file mode 100644 index 0000000000000000000000000000000000000000..5463ced53ed26942616174b3d409c289e760066e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage0_out.hex @@ -0,0 +1,64 @@ +2FE8C4 478657 4058AA 47F83D +6C4196 710326 16DBDD 0B9F6D +28BA67 1A9FF4 6D3F11 4F269E +651339 441CC3 43C244 12CDCE +218C0A 6D9992 1A4577 5654FF +5DE4DC 173660 70A8AB 19FC2F +1A5DAD 40B32F 472BDE 5D8360 +56B67F 6A2FFE 1DAF11 212A90 +132F50 13CCCC 741245 64B1C1 +4F8822 3D499B 4A9578 2858F1 +0C00F3 66C66A 2118AB 6BE022 +4859C5 106338 777BDF 2F8752 +04D296 39E007 4DFF12 730E83 +412B68 635CD6 248245 36B5B3 +7D843A 0CF9A4 7AE579 7A3CE4 +39FD0B 367673 5168AC 3DE414 +7655DD 5FF342 27EBDF 018B44 +32CEAE 099010 7E4F13 451275 +6F2780 330CDF 54D246 08B9A5 +2BA051 5C89AE 2B5579 4C40D6 +67F923 06267C 01D8AC 0FE806 +2471F4 2FA34B 583BE0 536F37 +60CAC6 59201A 2EBF13 171667 +1D4397 02BCE8 054246 5A9D98 +599C69 2C39B7 5BA57A 1E44C8 +16153A 55B686 3228AD 61CBF9 +526E0C 7F3355 08ABE0 257329 +0EE6DD 28D023 5F0F14 68FA5A +4B3FAF 524CF2 359247 2CA18A +07B880 7BC9C1 0C157A 7028BB +441152 25668F 6278AE 33CFEB +008A23 4EE35E 38FBE1 77571C +3CE2F5 78602D 0F7F14 3AFE4C +793BC7 21FCFB 65E248 7E857D +35B498 4B79CA 3C657B 422CAD +720D6A 74F699 12E8AE 05D3DD +2E863B 1E9367 694BE2 495B0E +6ADF0D 481036 3FCF15 0D023E +2757DE 718D05 165248 50896F +63B0B0 1B29D3 6CB57C 14309F +202981 44A6A2 4338AF 57B7D0 +5C8253 6E2371 19BBE2 1B5F00 +18FB24 17C03F 701F16 5EE631 +5553F6 413D0E 46A249 228D61 +11CCC7 6AB9DD 1D257C 661492 +4E2599 1456AB 7388B0 29BBC2 +0A9E6A 3DD37A 4A0BE3 6D42F3 +46F73C 675049 208F16 30EA23 +03700D 10ED17 76F24A 747154 +3FC8DF 3A69E6 4D757D 381884 +7C21B1 63E6B5 23F8B0 7B9FB5 +389A82 0D8383 7A5BE4 3F46E5 +74F354 370052 50DF17 02EE15 +316C25 607D21 27624A 467546 +6DC4F7 0A19EF 7DC57E 0A1C76 +2A3DC8 3396BE 5448B1 4DA3A7 +66969A 5D138D 2ACBE4 114AD7 +230F6B 06B05B 014F17 54D208 +5F683D 302D2A 57B24B 187938 +1BE10E 59A9F9 2E357E 5C0069 +5839E0 0346C7 04B8B1 1FA799 +14B2B1 2CC396 5B1BE5 632ECA +510B83 564065 319F18 26D5FA +0D8454 7FBD34 08224B 6A5D2B \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage2.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage2.hex new file mode 100644 index 0000000000000000000000000000000000000000..b065f054047901fe237edae77af363c6fc1b2e4a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage2.hex @@ -0,0 +1,64 @@ +2FE8C4 7655DD 3CE2F5 03700D +6C4196 32CEAE 793BC7 3FC8DF +28BA67 6F2780 35B498 7C21B1 +651339 2BA051 720D6A 389A82 +218C0A 67F923 2E863B 74F354 +5DE4DC 2471F4 6ADF0D 316C25 +1A5DAD 60CAC6 2757DE 6DC4F7 +56B67F 1D4397 63B0B0 2A3DC8 +132F50 599C69 202981 66969A +4F8822 16153A 5C8253 230F6B +0C00F3 526E0C 18FB24 5F683D +4859C5 0EE6DD 5553F6 1BE10E +04D296 4B3FAF 11CCC7 5839E0 +412B68 07B880 4E2599 14B2B1 +7D843A 441152 0A9E6A 510B83 +39FD0B 008A23 46F73C 0D8454 +4058AA 27EBDF 0F7F14 76F24A +16DBDD 7E4F13 65E248 4D757D +6D3F11 54D246 3C657B 23F8B0 +43C244 2B5579 12E8AE 7A5BE4 +1A4577 01D8AC 694BE2 50DF17 +70A8AB 583BE0 3FCF15 27624A +472BDE 2EBF13 165248 7DC57E +1DAF11 054246 6CB57C 5448B1 +741245 5BA57A 4338AF 2ACBE4 +4A9578 3228AD 19BBE2 014F17 +2118AB 08ABE0 701F16 57B24B +777BDF 5F0F14 46A249 2E357E +4DFF12 359247 1D257C 04B8B1 +248245 0C157A 7388B0 5B1BE5 +7AE579 6278AE 4A0BE3 319F18 +5168AC 38FBE1 208F16 08224B +478657 5FF342 78602D 10ED17 +710326 099010 21FCFB 3A69E6 +1A9FF4 330CDF 4B79CA 63E6B5 +441CC3 5C89AE 74F699 0D8383 +6D9992 06267C 1E9367 370052 +173660 2FA34B 481036 607D21 +40B32F 59201A 718D05 0A19EF +6A2FFE 02BCE8 1B29D3 3396BE +13CCCC 2C39B7 44A6A2 5D138D +3D499B 55B686 6E2371 06B05B +66C66A 7F3355 17C03F 302D2A +106338 28D023 413D0E 59A9F9 +39E007 524CF2 6AB9DD 0346C7 +635CD6 7BC9C1 1456AB 2CC396 +0CF9A4 25668F 3DD37A 564065 +367673 4EE35E 675049 7FBD34 +47F83D 018B44 3AFE4C 747154 +0B9F6D 451275 7E857D 381884 +4F269E 08B9A5 422CAD 7B9FB5 +12CDCE 4C40D6 05D3DD 3F46E5 +5654FF 0FE806 495B0E 02EE15 +19FC2F 536F37 0D023E 467546 +5D8360 171667 50896F 0A1C76 +212A90 5A9D98 14309F 4DA3A7 +64B1C1 1E44C8 57B7D0 114AD7 +2858F1 61CBF9 1B5F00 54D208 +6BE022 257329 5EE631 187938 +2F8752 68FA5A 228D61 5C0069 +730E83 2CA18A 661492 1FA799 +36B5B3 7028BB 29BBC2 632ECA +7A3CE4 33CFEB 6D42F3 26D5FA +3DE414 77571C 30EA23 6A5D2B \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage2_out.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage2_out.hex new file mode 100644 index 0000000000000000000000000000000000000000..1d6a655cf79106c30106ae26d218dec09651c07c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage2_out.hex @@ -0,0 +1,64 @@ +4DCD22 1D9E1F 2EFDE0 2539EF +62BA67 32C617 171AB1 04AB27 +77A7AC 47EE0F 7F1783 63FC60 +0CB4F0 5D1607 673454 436D98 +21A235 723DFF 4F5125 22DED0 +368F7A 0785F6 376DF6 025008 +4B7CBF 1CADEE 1F8AC7 61A141 +606A04 31D5E6 07A798 411279 +755749 46FDDE 6FA46A 2083B1 +0A648D 5C25D6 57C13B 7FD4EA +1F51D2 714DCE 3FDE0C 5F4622 +343F17 0695C5 27FADD 3EB75A +492C5C 1BBDBD 1017AE 1E2892 +5E19A1 30E5B5 781480 7D79CB +7306E6 460DAD 603151 5CEB03 +08142A 5B35A5 484E22 3C5C3B +00349B 609D92 34ECB3 6BA3C8 +75744C 14A7FD 77D98A 5939A3 +6AD3FC 489269 3AE660 46CF7E +6033AC 7C7CD5 7DD337 346559 +55935C 308740 40E00D 21FB34 +4AF30C 6471AC 03ECE3 0F910F +4052BC 187C17 46D9BA 7D06EB +35B26C 4C6683 09E690 6A9CC6 +2B121C 0070EE 4CD367 5832A1 +2071CC 345B5A 0FE03D 45C87C +15D17C 6845C6 52CD14 335E57 +0B312C 1C5031 15D9EA 20F432 +0090DC 503A9D 58C6C1 0E8A0D +75D08D 044508 1BD397 7BFFE9 +6B303D 382F74 5EC06E 6995C4 +608FED 6C19E0 21CD44 572B9F +5A69A3 375739 6932FA 232586 +6CD3CA 744A65 354890 2DC5D8 +7F3DF1 315D90 015E26 38662A +11C817 6E50BC 4D53BD 43067C +24323E 2B63E7 196953 4DA6CE +369C65 685713 655EEA 584720 +49068C 256A3E 317480 62E772 +5B70B3 625D6A 7D6A17 6D87C4 +6DDADA 1F7095 497FAD 782816 +006500 5C63C1 159543 02E867 +12CF27 1976EC 618ADA 0D88B9 +25394E 566A18 2DA070 18290B +37A375 137D43 799607 22C95D +4A0D9C 50706F 45AB9D 2D69AF +5C77C3 0D839A 11C133 380A01 +6EE1EA 4A76C6 5DB6CA 42AA53 +3C22AE 182DB0 70474A 5B494C +5CB178 3010E1 5B1F54 465C09 +7D4042 47F412 45F75E 316EC6 +1DEF0B 5FD743 30CF68 1C8183 +3E7DD5 77BA74 1BA772 079440 +5F0C9F 0FBDA4 067F7C 7286FE +7F9B69 27A0D5 713787 5D99BB +204A32 3F8406 5C0F91 48AC78 +40D8FC 576737 46E79B 33BF35 +6167C6 6F4A68 31BFA5 1ED1F2 +02168F 074D98 1C97AF 09E4AF +22A559 1F30C9 076FB9 74D76D +433423 3713FA 7227C4 5FEA2A +63C2ED 4EF72B 5CFFCE 4AFCE7 +0471B6 66DA5C 47D7D8 360FA4 +250080 7EBD8D 32AFE2 212261 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage67.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage67.hex new file mode 100644 index 0000000000000000000000000000000000000000..45176171da919dcc7ef7c42c68ea5487f3d63a8a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/ntt_stage67.hex @@ -0,0 +1,64 @@ +6E487E53FAD14B87B67A6F0F +33B7D322E6090DC9253E366C +5167F13A7D403BB163161800 +71D5C86D05F17BE2CD798D85 +0007F9591F39563B377D20D5 +7668D4745664230AA37F1751 +73E8AD09092025956B6411D6 +5A1D2E082A5145BD32077BDA +5C689800FEFF00647022A083 +375E7E00B09952F9B106ADDF +3217A74323F84AA5745A8498 +3CAACF7C0B111F216B5521CC +24F5611A2CAF507ED50D86E3 +2081AB3507A426270007AF66 +1CA4D75E75E7759906750FC7 +710C094F395B6FFEA91CAFDE +4FFBC60D25806405913DBEAA +2C631B7DBDB8799341332561 +1FC55D103A986BDB7210714B +44EA6E5DCF664ACB2A12B912 +7AEC3925FE604AE7D776C946 +258CA7403DC92FEE9A1B938A +7C46560AADCE5C668461BADD +7708B750FFAA2AF50D028FF5 +4099BE5EFAE02B386A6F69E6 +5D95216D9C8E6A58E03CCC42 +6F896E54D49C726F222ED821 +2567E632A9844D5A11527A97 +5F48483C875E2ED9F72E6FAB +5775BA78CE31215B4A1FCC1F +624EF9348EC34941F47F84F5 +1E508F3E07EA4468132FF2AE +3FC05F0234B0466DED7FAF9B +2D775012AFC26C9E3329A45C +714EEB31B25227FB8828E288 +45C1B169631A60DFC5449A18 +551945326A7C43646452E3C3 +1219F47D454D5C82B8306DD9 +1EB9B02BDD9777A4CB2EF327 +6B63795DD53D5495C54A962E +53D4CA11FB2802447B294220 +098DE6450AE02489EF2BD05A +69F3332CB8131ED54D7C2CDC +353F2B796D2B327F0332512C +04C06F28B5DB21917E10CF59 +11C6E2780E4C04185C466EF3 +4DDB16346E647920C25F5013 +01966E3268845BDF95134BEE +0E052B3D0359620E1D03D910 +563C061399F929E9834156B9 +268AD9080FFC1BBC126ACB1B +1F533220337B7A1CF24D7F52 +695D0858234038BD4E025EA9 +6110405C451A6EB38653E808 +37A7A5138EA80154BC0DF7F2 +1B1BEF5EBE1D34AAD97F9F93 +0F8A3F3F5E9369834D1139AB +1395C93660520EFF896040E6 +0B96FA0032D01219AD18B194 +70BA7B25914850C2AA61FB37 +0EEC2913DAE5147FB76F0655 +15D02E4EEE3202F5C23B921F +6BADBE39A2F1010B932502C0 +32089B7B36B90EFBCB64073F \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwa.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwa.hex new file mode 100644 index 0000000000000000000000000000000000000000..b8bfd7d1e1de36015c39308b10c33b65901cfd39 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwa.hex @@ -0,0 +1,64 @@ +000006000004000002000000 +00000E00000C00000A000008 +000016000014000012000010 +00001E00001C00001A000018 +000026000024000022000020 +00002E00002C00002A000028 +000036000034000032000030 +00003E00003C00003A000038 +000046000044000042000040 +00004E00004C00004A000048 +000056000054000052000050 +00005E00005C00005A000058 +000066000064000062000060 +00006E00006C00006A000068 +000076000074000072000070 +00007E00007C00007A000078 +000086000084000082000080 +00008E00008C00008A000088 +000096000094000092000090 +00009E00009C00009A000098 +0000A60000A40000A20000A0 +0000AE0000AC0000AA0000A8 +0000B60000B40000B20000B0 +0000BE0000BC0000BA0000B8 +0000C60000C40000C20000C0 +0000CE0000CC0000CA0000C8 +0000D60000D40000D20000D0 +0000DE0000DC0000DA0000D8 +0000E60000E40000E20000E0 +0000EE0000EC0000EA0000E8 +0000F60000F40000F20000F0 +0000FE0000FC0000FA0000F8 +000106000104000102000100 +00010E00010C00010A000108 +000116000114000112000110 +00011E00011C00011A000118 +000126000124000122000120 +00012E00012C00012A000128 +000136000134000132000130 +00013E00013C00013A000138 +000146000144000142000140 +00014E00014C00014A000148 +000156000154000152000150 +00015E00015C00015A000158 +000166000164000162000160 +00016E00016C00016A000168 +000176000174000172000170 +00017E00017C00017A000178 +000186000184000182000180 +00018E00018C00018A000188 +000196000194000192000190 +00019E00019C00019A000198 +0001A60001A40001A20001A0 +0001AE0001AC0001AA0001A8 +0001B60001B40001B20001B0 +0001BE0001BC0001BA0001B8 +0001C60001C40001C20001C0 +0001CE0001CC0001CA0001C8 +0001D60001D40001D20001D0 +0001DE0001DC0001DA0001D8 +0001E60001E40001E20001E0 +0001EE0001EC0001EA0001E8 +0001F60001F40001F20001F0 +0001FE0001FC0001FA0001F8 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwm_iter1.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwm_iter1.hex new file mode 100644 index 0000000000000000000000000000000000000000..ebc417bacd9083e05ad3f0791d9b8e7d16a35c76 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwm_iter1.hex @@ -0,0 +1,64 @@ +000009000004000001000000 +000031000024000019000010 +000079000064000051000040 +0000E10000C40000A9000090 +000169000144000121000100 +0002110001E40001B9000190 +0002D90002A4000271000240 +0003C1000384000349000310 +0004C9000484000441000400 +0005F10005A4000559000510 +0007390006E4000691000640 +0008A10008440007E9000790 +000A290009C4000961000900 +000BD1000B64000AF9000A90 +000D99000D24000CB1000C40 +000F81000F04000E89000E10 +001189001104001081001000 +0013B1001324001299001210 +0015F90015640014D1001440 +0018610017C4001729001690 +001AE9001A440019A1001900 +001D91001CE4001C39001B90 +002059001FA4001EF1001E40 +0023410022840021C9002110 +0026490025840024C1002400 +0029710028A40027D9002710 +002CB9002BE4002B11002A40 +003021002F44002E69002D90 +0033A90032C40031E1003100 +003751003664003579003490 +003B19003A24003931003840 +003F01003E04003D09003C10 +004309004204004101004000 +004731004624004519004410 +004B79004A64004951004840 +004FE1004EC4004DA9004C90 +005469005344005221005100 +0059110057E40056B9005590 +005DD9005CA4005B71005A40 +0062C1006184006049005F10 +0067C9006684006541006400 +006CF1006BA4006A59006910 +0072390070E4006F91006E40 +0077A10076440074E9007390 +007D29007BC4007A61007900 +0082D1008164007FF9007E90 +0088990087240085B1008440 +008E81008D04008B89008A10 +009489009304009181009000 +009AB1009924009799009610 +00A0F9009F64009DD1009C40 +00A76100A5C400A42900A290 +00ADE900AC4400AAA100A900 +00B49100B2E400B13900AF90 +00BB5900B9A400B7F100B640 +00C24100C08400BEC900BD10 +00C94900C78400C5C100C400 +00D07100CEA400CCD900CB10 +00D7B900D5E400D41100D240 +00DF2100DD4400DB6900D990 +00E6A900E4C400E2E100E100 +00EE5100EC6400EA7900E890 +00F61900F42400F23100F040 +00FE0100FC0400FA0900F810 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwm_iter2.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwm_iter2.hex new file mode 100644 index 0000000000000000000000000000000000000000..d3fc4b86f71130de2134592f721b3b66350ce6dd --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pwm_iter2.hex @@ -0,0 +1,64 @@ +000012000008000002000000 +000062000048000032000020 +0000F20000C80000A2000080 +0001C2000188000152000120 +0002D2000288000242000200 +0004220003C8000372000320 +0005B20005480004E2000480 +000782000708000692000620 +000992000908000882000800 +000BE2000B48000AB2000A20 +000E72000DC8000D22000C80 +001142001088000FD2000F20 +0014520013880012C2001200 +0017A20016C80015F2001520 +001B32001A48001962001880 +001F02001E08001D12001C20 +002312002208002102002000 +002762002648002532002420 +002BF2002AC80029A2002880 +0030C2002F88002E52002D20 +0035D2003488003342003200 +003B220039C8003872003720 +0040B2003F48003DE2003C80 +004682004508004392004220 +004C92004B08004982004800 +0052E2005148004FB2004E20 +0059720057C8005622005480 +006042005E88005CD2005B20 +0067520065880063C2006200 +006EA2006CC8006AF2006920 +007632007448007262007080 +007E02007C08007A12007820 +008612008408008202008000 +008E62008C48008A32008820 +0096F20094C80092A2009080 +009FC2009D88009B52009920 +00A8D200A68800A44200A200 +00B22200AFC800AD7200AB20 +00BBB200B94800B6E200B480 +00C58200C30800C09200BE20 +00CF9200CD0800CA8200C800 +00D9E200D74800D4B200D220 +00E47200E1C800DF2200DC80 +00EF4200EC8800E9D200E720 +00FA5200F78800F4C200F200 +0105A20102C800FFF200FD20 +011132010E48010B62010880 +011D02011A08011712011420 +012912012608012302012000 +013562013248012F32012C20 +0141F2013EC8013BA2013880 +014EC2014B88014852014520 +015BD2015888015542015200 +0169220165C8016272015F20 +0176B2017348016FE2016C80 +018482018108017D92017A20 +019292018F08018B82018800 +01A0E2019D480199B2019620 +01AF7201ABC801A82201A480 +01BE4201BA8801B6D201B320 +01CD5201C98801C5C201C200 +01DCA201D8C801D4F201D120 +01EC3201E84801E46201E080 +01FC0201F80801F41201F020 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pws.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pws.hex new file mode 100644 index 0000000000000000000000000000000000000000..a7ffb477c61588351431a5394f626a763a8c406a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pws.hex @@ -0,0 +1,64 @@ +7FDFF77FDFEB7FDFC77FDFD1 +7FDFFE7FDFE87FDFFC7FDFE0 +7FDFB57FDFDC7FDFC47FDFD6 +7FDFA97FDFB87FDFD17FDFCA +7FDFF87FDFFA7FDFF47FDFF5 +7FDFE57FDFE57FDFCC7FDFD5 +7FDFA27FDFD97FDFA77FDFE6 +7FDFA67FDFD57FDFDA7FDFE2 +7FDFDC7FDFC37FDFCE7FDFED +7FDFAD7FDFA67FDFEE7FDFFE +7FDFD47FDFA97FDFDE7FDFF5 +7FDFBD7FDFF07FDFC27FDFC9 +7FDFFC7FDFD37FDF9E7FDFB2 +7FDFF37FDFD37FDFB87FDFCB +7FDFE47FDFF17FDFBA7FDFC4 +7FDFC47FDFE47FDFA67FDFDC +7FDFA87FDFF87FDFA27FDFA4 +7FDFE87FDFD67FDFBC7FDFA8 +7FDFF57FDFE97FDFCC7FDFCA +7FDFBE7FDFBD7FDFFB7FDFFD +7FDFB77FDFC97FDF9F7FDFA4 +7FDFFF7FDFDC7FDFCF7FDFD1 +7FDFB27FDFA27FDFC57FDFF3 +7FDFB57FDFCE7FDFE47FDFE1 +7FDFE67FDFCC7FDFC07FDFD5 +7FDFCD7FDFDE7FDFFB7FDFAB +7FDFE97FDFDD7FDFDF7FDF9E +7FDFEB7FDFA47FDFAF7FDFEC +7FDFF17FDFE37FDFE97FDFC2 +7FDFEF7FDFE77FDFB47FDFA1 +7FDFDA7FDFF57FDFE47FDFA0 +7FDFEE7FDFF07FDFF17FDFDC +7FDF9D7FDFD67FDFE97FDFE2 +7FDFF47FDFE27FDFEC7FDFF6 +7FDFE47FDFF77FDFC67FDFE8 +7FDFE47FDFAF7FDFF97FDFA2 +7FDFED7FDFF77FDFE0000000 +7FDFE17FDFB97FDFB97FDFB2 +7FDFBE7FDFDD7FDFEA7FDFB5 +7FDFFC7FDFBE7FDF9D7FDFC2 +7FDFD47FDFB47FDFD07FDFE0 +7FDFA77FDFDC7FDFFB7FDFF0 +7FDFAE7FDFC17FDFCA7FDFE5 +7FDFF37FDFF47FDFBF7FDFC9 +7FDF9D7FDFC17FDFB67FDFD5 +7FDFBB7FDFEB7FDFA47FDFFA +7FDFAB7FDFFB7FDFF27FDFFD +7FDFFC7FDFB47FDFDB7FDFD6 +7FDFFC7FDFEC7FDFEE7FDFD3 +7FDFEA7FDFAF7FDFDD7FDFFD +7FDFA97FDFEA7FDFF87FDFDF +7FDFCA7FDF9F7FDFA97FDFBC +7FDFE37FDFA97FDFB47FE000 +7FDFA17FE0007FDFCE7FDFF7 +7FDFCD7FDFED7FDFEB7FDFC4 +7FDFB77FDFBF7FDFBD7FDFDB +7FDFB97FDFCF7FDFE27FDFF7 +7FDFAC7FDFD87FDFB97FDFF7 +7FDFDB7FDFDB7FDFE47FDFE2 +7FDFF57FDFE57FDFF17FDFEA +7FDFD87FDFEA7FDFCE7FDFBF +7FDFEA7FDFEE7FDFC67FDFF5 +7FDFDA7FDFF47FDFBF7FDFF4 +7FDFB67FDFDB7FDFE97FDFF2 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pws_input.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pws_input.hex new file mode 100644 index 0000000000000000000000000000000000000000..fd2e709ebb534af6164193f227c24a1a99c47dec --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/pws_input.hex @@ -0,0 +1,64 @@ +00000D00001800003B000030 +00000A00001F00000A000025 +00005700002F000046000033 +00006700005700003D000043 +00001C00001900001E00001C +00003300003200004A000040 +00007A000042000073000033 +00007A00004A00004400003B +000048000060000054000034 +00007B000081000038000027 +00005800008200004C000034 +00007300003F00006C000064 +00003800006000009400007F +00004500006400007E00006A +00005800004A000080000075 +00007C00005B000098000061 +00009C00004B0000A000009D +00006000007100008A00009D +00005700006200007E00007F +000092000092000053000050 +00009D00008A0000B30000AD +00005900007B000087000084 +0000AA0000B9000095000066 +0000AB00009100007A00007C +00007E0000970000A200008C +00009B00008900006B0000BA +00008300008E00008B0000CB +0000850000CB0000BF000081 +0000830000900000890000AF +0000890000900000C20000D4 +0000A20000860000960000D9 +00009200008F00008D0000A1 +0000E70000AD00009900009F +0000940000A500009A00008F +0000A80000940000C40000A1 +0000AC0000E00000950000EB +0000A700009C0000B2000090 +0000B70000DE0000DD0000E3 +0000DE0000BE0000B00000E4 +0000A40000E10001010000DB +0000D00000EF0000D20000C1 +0001010000CB0000AB0000B5 +0000FE0000EA0000E00000C4 +0000BD0000BB0000EF0000E4 +0001170000F20000FC0000DC +0000FD0000CC0001120000BB +0001110000C00000C80000BC +0000C400010B0000E30000E7 +0000C80000D70000D40000EE +0000DE0001180000E90000C8 +0001230000E10000D20000EA +000106000130000125000111 +0000F100012A00011E0000D1 +0001370000D70001080000DE +00010F0000EE0000EF000115 +000129000120000121000102 +00012B0001140001000000EA +00013C00010F00012D0000EE +000111000110000106000107 +0000FB00010A0000FD000103 +00011C000109000124000132 +00010E000109000130000100 +00012200010700013B000105 +00014A00012400011500010B \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/rand_ntt_stage0_mem.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/rand_ntt_stage0_mem.hex new file mode 100644 index 0000000000000000000000000000000000000000..f415eacca7e62bba8ad55d722f32fdab01b149ea --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/rand_ntt_stage0_mem.hex @@ -0,0 +1,64 @@ +02673C01F03440AC3451C151 +08AA7223F2727DC2FD067153 +64FB1C5917BE68AEE94FF723 +6375B83455EF3E78A30AE248 +02BD757FB6A85656073E3712 +3212960E4B5971136A14D817 +7F392634B53B4B71DB32CDA2 +0A5DDE4DA4382957392C32E5 +55E124655E1639EEA84AD3D9 +4155F8502C4D4CE09118CC7F +14C0AE5A8A9A08F072146875 +5E2EED7B985905D61E2CE2FC +1686772727B418E8E06072A5 +5B8ACE4CA6433A16184425B4 +5B24AF6176273B4AE86E6B9E +2668607B97123C386233FCDA +452AE754063A61F6367CE1CB +59528B0AC815343E770F4F9D +17CE1D41F31921346C4252F7 +6EB1625592527FC466438D61 +0FAEBC016B84221F7968147C +7EC4406CA2352AF07D1DD976 +0E2AF9657FC41D2900087C29 +6E1B685342E76A83052FAA08 +5DAA6306708C55CE6B209B4A +7661E40F153239825C5919CB +2C4EAE2FD1AC134A1F3D0F62 +61D5750091495B204319AD13 +632E0D3CB87955E1213F3D35 +44F63927C9D0451FF642E3F2 +6A22866288FD34B445337B2D +7ADDA617ECC32B1B9A0C796B +09BDF271EBB84BFFA664C8A7 +5BD32F533AF95E919B0EF779 +510CD711BD106D8F9F471A36 +7230C87CAE36189053433FA0 +1F81D70528441173F7138DB6 +66B1D4292354584D583644CC +0AF45F73DD7C2DE548369254 +435EC52361CC2DDA9A1D4514 +359C9B3FCFBC0031EC6D62F5 +40B9351BF12A30D3806BF530 +78A1751144E62DE1C46A36BF +1E124809246F40EE0B7C1D86 +25810631FBA83231157A6D12 +21BF372593FC10A7BC5E3A00 +697DA119CA566A90936037B3 +73FAFE3EFEE325EFF74F4F60 +18DE4135D84924E12C21CCA6 +59FF2D1C284060B6BB4F994D +6DC68579684A1311E626041D +508CAE0753E52786E228FE9E +73F1965F25646D322145481F +64FAFB1E6BDF37777E107B5C +4DE29F2C2A4207FD950E7E41 +351D650D59353E694D01C1BB +43DCC03E14543AC1533C26D6 +687AA918D41B750E6D3D21C3 +6043E23214B40E83A2108A65 +545CE336BB9E044041765B71 +53EAC72E9E1773321057B105 +0920D03E78354EC81C06F761 +7592617FCF6D5AFBB12AAECD +4FD8A2675CA64AD1984A4335 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/zeta.txt b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/zeta.txt new file mode 100644 index 0000000000000000000000000000000000000000..04d2e6fbda49b3ec455e30980aecaa4a5a14284d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/zeta.txt @@ -0,0 +1,256 @@ +000001 +495E02 +397567 +396569 +4F062B +53DF73 +4FE033 +4F066B +76B1AE +360DD5 +28EDB0 +207FE4 +397283 +70894A +088192 +6D3DC8 +4C7294 +41E0B4 +28A3D2 +66528A +4A18A7 +794034 +0A52EE +6B7D81 +4E9F1D +1A2877 +2571DF +1649EE +7611BD +492BB7 +2AF697 +22D8D5 +36F72A +30911E +29D13F +492673 +50685F +2010A2 +3887F7 +11B2C3 +0603A4 +0E2BED +10B72C +4A5F35 +1F9D15 +428CD4 +3177F4 +20E612 +341C1D +1AD873 +736681 +49553F +3952F6 +62564A +65AD05 +439A1C +53AA5F +30B622 +087F38 +3B0E6D +2C83DA +1C496E +330E2B +1C5B70 +2EE3F1 +137EB9 +57A930 +3AC6EF +3FD54C +4EB2EA +503EE1 +7BB175 +2648B4 +1EF256 +1D90A2 +45A6D4 +2AE59B +52589C +6EF1F5 +3F7288 +175102 +075D59 +1187BA +52ACA9 +773E9E +0296D8 +2592EC +4CFF12 +404CE8 +4AA582 +1E54E6 +4F16C1 +1A7E79 +03978F +4E4817 +31B859 +5884CC +1B4827 +5B63D0 +5D787A +35225E +400C7E +6C09D1 +5BD532 +6BC4D3 +258ECB +2E534C +097A6C +3B8820 +6D285C +2CA4F8 +337CAA +14B2A0 +558536 +28F186 +55795D +4AF670 +234A86 +75E826 +78DE66 +05528C +7ADF59 +0F6E17 +5BF3DA +459B7E +628B34 +5DBECB +1A9E7B +0006D9 +6257C5 +574B3C +69A8EF +289838 +64B5FE +7EF8F5 +2A4E78 +120A23 +0154A8 +09B7FF +435E87 +437FF8 +5CD5B4 +4DC04E +4728AF +7F735D +0C8D0D +0F66D5 +5A6D80 +61AB98 +185D96 +437F31 +468298 +662960 +4BD579 +28DE06 +465D8D +49B0E3 +09B434 +7C0DB3 +5A68B0 +409BA9 +64D3D5 +21762A +658591 +246E39 +48C39B +7BC759 +4F5859 +392DB2 +230923 +12EB67 +454DF2 +30C31C +285424 +13232E +7FAF80 +2DBFCB +022A0B +7E832C +26587A +6B3375 +095B76 +6BE1CC +5E061E +78E00D +628C37 +3DA604 +4AE53C +1F1D68 +6330BB +7361B8 +5EA06C +671AC7 +201FC6 +5BA4FF +60D772 +08F201 +6DE024 +080E6D +56038E +695688 +1E6D3E +2603BD +6A9DFA +07C017 +6DBFD4 +74D0BD +63E1E3 +519573 +7AB60D +2867BA +2DECD4 +58018C +3F4CF5 +0B7009 +427E23 +3CBD37 +273333 +673957 +1A4B5D +196926 +1EF206 +11C14E +4C76C8 +3CF42F +7FB19A +6AF66C +2E1669 +3352D6 +034760 +085260 +741E78 +2F6316 +6F0A11 +07C0F1 +776D0B +0D1FF0 +345824 +0223D4 +68C559 +5E8885 +2FAA32 +23FC65 +5E6942 +51E0ED +65ADB3 +2CA5E6 +79E1FE +7B4064 +35E1DD +433AAC +464ADE +1CFE14 +73F1CE +10170E +74B6D7 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/zeta_inv.hex b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/zeta_inv.hex new file mode 100644 index 0000000000000000000000000000000000000000..2e317c3fd680c350b37fd7d6bd79d3707b2fcd43 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/tb/test_vectors/zeta_inv.hex @@ -0,0 +1,256 @@ +7FE000 +3681FF +466A9A +467A98 +30D9D6 +2C008E +2FFFCE +30D996 +092E53 +49D22C +56F251 +5F601D +466D7E +0F56B7 +775E6F +12A239 +336D6D +3DFF4D +573C2F +198D77 +35C75A +069FCD +758D13 +146280 +3140E4 +65B78A +5A6E22 +699613 +09CE44 +36B44A +54E96A +5D072C +48E8D7 +4F4EE3 +560EC2 +36B98E +2F77A2 +5FCF5F +47580A +6E2D3E +79DC5D +71B414 +6F28D5 +3580CC +6042EC +3D532D +4E680D +5EF9EF +4BC3E4 +65078E +0C7980 +368AC2 +468D0B +1D89B7 +1A32FC +3C45E5 +2C35A2 +4F29DF +7760C9 +44D194 +535C27 +639693 +4CD1D6 +638491 +50FC10 +6C6148 +2836D1 +451912 +400AB5 +312D17 +2FA120 +042E8C +59974D +60EDAB +624F5F +3A392D +54FA66 +2D8765 +10EE0C +406D79 +688EFF +7882A8 +6E5847 +2D3358 +08A163 +7D4929 +5A4D15 +32E0EF +3F9319 +353A7F +618B1B +30C940 +656188 +7C4872 +3197EA +4E27A8 +275B35 +6497DA +247C31 +226787 +4ABDA3 +3FD383 +13D630 +240ACF +141B2E +5A5136 +518CB5 +766595 +4457E1 +12B7A5 +533B09 +4C6357 +6B2D61 +2A5ACB +56EE7B +2A66A4 +34E991 +5C957B +09F7DB +07019B +7A8D75 +0500A8 +7071EA +23EC27 +3A4483 +1D54CD +222136 +654186 +7FD928 +1D883C +2894C5 +163712 +5747C9 +1B2A03 +00E70C +559189 +6DD5DE +7E8B59 +762802 +3C817A +3C6009 +230A4D +321FB3 +38B752 +006CA4 +7352F4 +70792C +257281 +1E3469 +67826B +3C60D0 +395D69 +19B6A1 +340A88 +5701FB +398274 +362F1E +762BCD +03D24E +257751 +3F4458 +1B0C2C +5E69D7 +1A5A70 +5B71C8 +371C66 +0418A8 +3087A8 +46B24F +5CD6DE +6CF49A +3A920F +4F1CE5 +578BDD +6CBCD3 +003081 +522036 +7DB5F6 +015CD5 +598787 +14AC8C +76848B +13FE35 +21D9E3 +06FFF4 +1D53CA +4239FD +34FAC5 +60C299 +1CAF46 +0C7E49 +213F95 +18C53A +5FC03B +243B02 +1F088F +76EE00 +11FFDD +77D194 +29DC73 +168979 +6172C3 +59DC44 +154207 +781FEA +12202D +0B0F44 +1BFE1E +2E4A8E +0529F4 +577847 +51F32D +27DE75 +40930C +746FF8 +3D61DE +4322CA +58ACCE +18A6AA +6594A4 +6676DB +60EDFB +6E1EB3 +336939 +42EBD2 +002E67 +14E995 +51C998 +4C8D2B +7C98A1 +778DA1 +0BC189 +507CEB +10D5F0 +781F10 +0872F6 +72C011 +4B87DD +7DBC2D +171AA8 +21577C +5035CF +5BE39C +2176BF +2DFF14 +1A324E +533A1B +05FE03 +049F9D +49FE24 +3CA555 +399523 +62E1ED +0BEE33 +6FC8F3 +0B292A \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/env/ntt_env.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/env/ntt_env.sv new file mode 100644 index 0000000000000000000000000000000000000000..10674d763c211de725be71fdecd8bce0821dfc94 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/env/ntt_env.sv @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_env extends uvm_env; + `uvm_component_utils(ntt_env) + + ntt_agent ntt_agent_i; + // NTT memory + mem_agent ntt_mem_i; + // PWM_a memory + mem_agent pwm_a_mem_i; + // PWM_b memory + mem_agent pwm_b_mem_i; + + ntt_sb ntt_sb_i; + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + ntt_agent_i = ntt_agent::type_id::create(.name("ntt_agent_i"), .parent(this)); + // Mempory agents for NTT, and two operands of PWMs + ntt_mem_i = mem_agent::type_id::create(.name("ntt_mem_i"), .parent(this)); + pwm_a_mem_i = mem_agent::type_id::create(.name("pwm_a_mem_i"), .parent(this)); + pwm_b_mem_i = mem_agent::type_id::create(.name("pwm_b_mem_i"), .parent(this)); + + //Scoreboard + ntt_sb_i = ntt_sb::type_id::create(.name("ntt_sb_i"), .parent(this)); + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + ntt_agent_i.ntt_ap.connect(ntt_sb_i.ntt_ap); + + ntt_mem_i.mem_ap.connect(ntt_sb_i.ntt_mem_ap); + pwm_a_mem_i.mem_ap.connect(ntt_sb_i.pwm_a_mem_ap); + pwm_b_mem_i.mem_ap.connect(ntt_sb_i.pwm_b_mem_ap); + endfunction: connect_phase + +endclass: ntt_env \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/interfaces/mem_if.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/interfaces/mem_if.sv new file mode 100644 index 0000000000000000000000000000000000000000..0d4f4fb0212e4491f800a2f08a4355b4f97a2848 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/interfaces/mem_if.sv @@ -0,0 +1,65 @@ + +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +interface mem_if(input bit clk); + import mldsa_params_pkg::*; + logic reset_n; + mem_if_t mem_port0_req; + mem_if_t mem_port1_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] p0_read_data; + logic [MLDSA_MEM_DATA_WIDTH-1:0] p0_write_data; + logic [MLDSA_MEM_DATA_WIDTH-1:0] p1_read_data; + logic [MLDSA_MEM_DATA_WIDTH-1:0] p1_write_data; + logic update_mem; + string mem_path; + + + + + clocking mem_s_cb @ (posedge clk); + default input #1step output #1ns; + input reset_n; + input mem_port0_req; + input mem_port1_req; + input p0_read_data; + input p0_write_data; + input p1_read_data; + input p1_write_data; + endclocking: mem_s_cb + + // modport mem_m_sync_mp(clocking mem_m_cb); + modport mem_s_sync_mp(clocking mem_s_cb); + + task update_mem_task(input logic [MLDSA_MEM_ADDR_WIDTH-1:0] addr, input logic [MLDSA_MEM_DATA_WIDTH-1:0] data); + // Time zero assignment to update memory content using hierarchical reference + case (mem_path) + "mem_ntt": ntt_utb_top.ntt_mem.mem[addr] = data; + "mem_pwm_a": ntt_utb_top.pwm_mem_a.mem[addr] = data; + "mem_pwm_b": ntt_utb_top.pwm_mem_b.mem[addr] = data; + default: $fatal("Unknown memory path: %s", mem_path); + endcase + endtask: update_mem_task + + task read_mem(input logic [MLDSA_MEM_ADDR_WIDTH-1:0] addr, output logic [MLDSA_MEM_DATA_WIDTH-1:0] data); + // Read the memory content using hierarchical reference + case (mem_path) + "mem_ntt": data = ntt_utb_top.ntt_mem.mem[addr]; + "mem_pwm_a": data = ntt_utb_top.pwm_mem_a.mem[addr]; + "mem_pwm_b": data = ntt_utb_top.pwm_mem_b.mem[addr]; + default: $fatal("Unknown memory path: %s", mem_path); + endcase + endtask: read_mem + +endinterface: mem_if \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/interfaces/ntt_if.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/interfaces/ntt_if.sv new file mode 100644 index 0000000000000000000000000000000000000000..d67034af0a5566cfc2404780ffdd099878e46710 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/interfaces/ntt_if.sv @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +import ntt_defines_pkg::*; +import mldsa_params_pkg::*; + +interface ntt_if(input bit clk); + + logic reset_n; + logic zeroize; + mode_t mode; + logic ntt_enable; + + ntt_mem_addr_t ntt_mem_base_addr; + pwo_mem_addr_t pwo_mem_base_addr; + + logic accumulate; + logic sampler_valid; + logic sampler_mode; + logic [MLDSA_MEM_DATA_WIDTH-1:0]sampler_data; + + logic ntt_done; + logic stage_done; + + clocking ntt_m_cb @ (posedge clk); + default input #1step output #1ns; + input reset_n; + output zeroize; + output mode; + output ntt_enable; + + output ntt_mem_base_addr; + output pwo_mem_base_addr; + + output accumulate; + output sampler_valid; + output sampler_mode; + output sampler_data; + + input ntt_done; + input stage_done; + endclocking: ntt_m_cb + + clocking ntt_s_cb@ (posedge clk); + default input #1step output #1ns; + input reset_n; + input zeroize; + input mode; + input ntt_enable; + + input ntt_mem_base_addr; + input pwo_mem_base_addr; + + input accumulate; + input sampler_valid; + input sampler_mode; + input sampler_data; + + input ntt_done; + input stage_done; + endclocking :ntt_s_cb + + modport ntt_m_sync_mp(clocking ntt_m_cb); + modport ntt_s_sync_mp(clocking ntt_s_cb); + +endinterface: ntt_if \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_agent.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_agent.sv new file mode 100644 index 0000000000000000000000000000000000000000..2cb7423b734f03b6ba60fe60b4039f1fdcc05597 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_agent.sv @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class mem_agent extends uvm_agent; + + `uvm_component_utils(mem_agent) + + uvm_analysis_port#(mem_txn) mem_ap; + + mem_sequencer mem_sqcr_i; + mem_driver mem_driver_i; + mem_mon mem_mon_i; + + function new(string name, uvm_component parent); + super.new(name, parent); + mem_ap = new("mem_ap", this); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + mem_sqcr_i = mem_sequencer::type_id::create(.name("mem_sqcr_i"), .parent(this)); + mem_driver_i = mem_driver::type_id::create(.name("mem_driver_i"), .parent(this)); + mem_mon_i = mem_mon::type_id::create(.name("mem_mon_i"), .parent(this)); + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + mem_driver_i.seq_item_port.connect(mem_sqcr_i.seq_item_export); + mem_mon_i.mem_ap.connect(mem_ap); + endfunction: connect_phase + +endclass: mem_agent \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_agent_config.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_agent_config.sv new file mode 100644 index 0000000000000000000000000000000000000000..cdfbffc11559aa20eca4d62948f038d6713ba42c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_agent_config.sv @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class mem_agent_config extends uvm_object; + `uvm_object_utils(mem_agent_config) + + string mem_path; + + function new(string name = "mem_agent_config"); + super.new(name); + endfunction + + function void set_mem_path(string path); + mem_path = path; + endfunction + + function string get_mem_path(); + return mem_path; + endfunction +endclass: mem_agent_config \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_driver.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_driver.sv new file mode 100644 index 0000000000000000000000000000000000000000..6ef5a87c0fe42276cf5b64b397d904fc134b30c2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_driver.sv @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class mem_driver extends uvm_driver#(mem_txn); + `uvm_component_utils(mem_driver) + + virtual mem_if mem_vif; + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase + + task run_phase(uvm_phase phase); + + mem_txn mem_txn_i; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] addr; + forever begin + @(negedge mem_vif.clk); + seq_item_port.try_next_item(mem_txn_i); + if (mem_txn_i != null) begin + if(mem_txn_i.update_mem == 1 ) begin + mem_vif.update_mem <= mem_txn_i.update_mem; + for (int i = 0; i<(2**MLDSA_MEM_ADDR_WIDTH); i++ ) begin + addr = i; + mem_vif.update_mem_task(addr, mem_txn_i.artificialMemory[addr]); + end + seq_item_port.item_done(); + end + else begin + mem_vif.update_mem <= 0; + end + end + else begin + mem_vif.update_mem <= 0; + end + end + + endtask + +endclass diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_mon.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_mon.sv new file mode 100644 index 0000000000000000000000000000000000000000..ee1cf19d220fa105c375b28a0837a5fdf0446375 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_mon.sv @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class mem_mon extends uvm_monitor; + `uvm_component_utils(mem_mon) + + uvm_analysis_port#(mem_txn) mem_ap; + virtual mem_if mem_vif; + + function new(string name, uvm_component parent); + super.new(name, parent); + mem_ap = new("mem_ap", this); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase + + task run_phase(uvm_phase phase); + logic port0_readFollowUp; + logic port1_readFollowUp; + mem_txn port0_mem_txn_i_pending; + mem_txn port1_mem_txn_i_pending; + port0_readFollowUp = 'h0; + port1_readFollowUp = 'h0; + port0_mem_txn_i_pending = mem_txn::type_id::create("port0_mem_txn_i_pending"); + port1_mem_txn_i_pending = mem_txn::type_id::create("port1_mem_txn_i_pending"); + port0_mem_txn_i_pending.reset_indicator = 0; + port1_mem_txn_i_pending.reset_indicator = 0; + @(negedge mem_vif.reset_n); + forever begin + @(posedge mem_vif.clk); + // check if memory is updated by the TB + mem_TB_update_check(); + mem_port0_read_write_decoder (port0_readFollowUp, port0_mem_txn_i_pending); + mem_port1_read_write_decoder (port1_readFollowUp, port1_mem_txn_i_pending); + + end + + endtask + + task mem_TB_update_check(); + mem_txn mem_txn_i; + if (mem_vif.update_mem) begin + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.update_mem = mem_vif.update_mem; + for (int i = 0; i<(2**MLDSA_MEM_ADDR_WIDTH); i++ ) begin + mem_vif.read_mem(i, mem_txn_i.artificialMemory[i]); + end + mem_ap.write(mem_txn_i); + end + endtask: mem_TB_update_check + + + task mem_port0_read_write_decoder (inout logic readFollowUp, inout mem_txn mem_txn_i_pending); + mem_txn mem_txn_i; + logic [3:0] mem_states; + mem_states = {mem_vif.mem_s_cb.reset_n, mem_vif.mem_s_cb.mem_port0_req.rd_wr_en, readFollowUp}; + casez (mem_states) + 4'b0???: begin + // Reset is active and others are ignored + + // This if condition avoids sending multiple items to scoreboard + // This if has a lock mechanism and the lock is released in + // non-reset states. + if (mem_txn_i_pending.reset_indicator == 0) begin + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + // the indicator flag is high, meaning is DUT is in reset state + mem_txn_i.reset_indicator = 1; + // mem_txn_i.mem_port0_req = '{default: '0}; + mem_txn_i.mem_port0_req.rd_wr_en = mem_rw_mode_e'(RW_IDLE); + mem_txn_i.mem_port0_req.addr = 'h0; + mem_txn_i.p0_read_data = 'h0; + mem_txn_i.p0_write_data = 'h0; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 1; + mem_ap.write(mem_txn_i); + end + end + {1'b1, mem_rw_mode_e'(RW_WRITE), 1'b0}: begin + // Write observed but there is also a pending read + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port0_req = mem_vif.mem_s_cb.mem_port0_req; + mem_txn_i.p0_read_data = 'h0; + mem_txn_i.p0_write_data = mem_vif.mem_s_cb.p0_write_data; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + mem_ap.write(mem_txn_i); + end + {1'b1, mem_rw_mode_e'(RW_WRITE), 1'b1}: begin + // Write comes but there is also a pending read + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port0_req = mem_txn_i_pending.mem_port0_req; + mem_txn_i.p0_read_data = mem_vif.mem_s_cb.p0_read_data; + mem_txn_i.p0_write_data = 'h0; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + // Pending read request is being sent + mem_ap.write(mem_txn_i); + // Now write request is being sent. + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port0_req = mem_vif.mem_s_cb.mem_port0_req; + mem_txn_i.p0_read_data = 'h0; + mem_txn_i.p0_write_data = mem_vif.mem_s_cb.p0_write_data; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + mem_ap.write(mem_txn_i); + end + {1'b1, mem_rw_mode_e'(RW_READ), 1'b0}: begin + // Read is requested but the RAM needs one cycle to respond + mem_txn_i_pending.mem_port0_req = mem_vif.mem_s_cb.mem_port0_req; + readFollowUp = 1; + mem_txn_i_pending.reset_indicator = 0; + end + {1'b1, mem_rw_mode_e'(RW_READ), 1'b1}: begin + // Another read is requested while the pending read + // is going to be sent + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port0_req = mem_txn_i_pending.mem_port0_req; + mem_txn_i.p0_read_data = mem_vif.mem_s_cb.p0_read_data; + mem_txn_i.p0_write_data = 'h0; + // Read is requested but the RAM needs one cycle to respond + mem_txn_i_pending.mem_port0_req = mem_vif.mem_s_cb.mem_port0_req; + readFollowUp = 1; + mem_txn_i_pending.reset_indicator = 0; + mem_ap.write(mem_txn_i); + end + {1'b1, mem_rw_mode_e'(RW_IDLE), 1'b0}: begin + // Memory is Idle + end + {1'b1, mem_rw_mode_e'(RW_IDLE), 1'b1}: begin + // Mem is in the idle state but there is also a pending read + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port0_req = mem_txn_i_pending.mem_port0_req; + mem_txn_i.p0_read_data = mem_vif.mem_s_cb.p0_read_data; + mem_txn_i.p0_write_data = 'h0; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + // Pending read request is being sent + mem_ap.write(mem_txn_i); + end + default: begin + // Handle unexpected states + `uvm_error("MEM_MON", "Unexpected state in mem_states for port 0") + end + endcase + endtask: mem_port0_read_write_decoder + + task mem_port1_read_write_decoder (inout logic readFollowUp, inout mem_txn mem_txn_i_pending); + mem_txn mem_txn_i; + logic [3:0] mem_states; + mem_states = {mem_vif.mem_s_cb.reset_n, mem_vif.mem_s_cb.mem_port1_req.rd_wr_en, readFollowUp}; + casez (mem_states) + 4'b0???: begin + // Reset is active and others are ignored + + // This if condition avoids sending multiple items to scoreboard + // This if has a lock mechanism and the lock is released in + // non-reset states. + if (mem_txn_i_pending.reset_indicator == 0) begin + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + // the indicator flag is high, meaning is DUT is in reset state + mem_txn_i.reset_indicator = 1; + mem_txn_i.mem_port1_req.rd_wr_en = mem_rw_mode_e'(RW_IDLE); + mem_txn_i.mem_port1_req.addr = 'h0; + mem_txn_i.p1_read_data = 'h0; + mem_txn_i.p1_write_data = 'h0; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 1; + mem_ap.write(mem_txn_i); + end + end + {1'b1, mem_rw_mode_e'(RW_WRITE), 1'b0}: begin + // Write observed but there is also a pending read + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port1_req = mem_vif.mem_s_cb.mem_port1_req; + mem_txn_i.p1_read_data = 'h0; + mem_txn_i.p1_write_data = mem_vif.mem_s_cb.p1_write_data; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + mem_ap.write(mem_txn_i); + end + {1'b1, mem_rw_mode_e'(RW_WRITE), 1'b1}: begin + // Write comes but there is also a pending read + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port1_req = mem_txn_i_pending.mem_port1_req; + mem_txn_i.p1_read_data = mem_vif.mem_s_cb.p1_read_data; + mem_txn_i.p1_write_data = 'h0; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + // Pending read request is being sent + mem_ap.write(mem_txn_i); + // Now write request is being sent. + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port1_req = mem_vif.mem_s_cb.mem_port1_req; + mem_txn_i.p1_read_data = 'h0; + mem_txn_i.p1_write_data = mem_vif.mem_s_cb.p1_write_data; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + mem_ap.write(mem_txn_i); + end + {1'b1, mem_rw_mode_e'(RW_READ), 1'b0}: begin + // Read is requested but the RAM needs one cycle to respond + mem_txn_i_pending.mem_port1_req = mem_vif.mem_s_cb.mem_port1_req; + readFollowUp = 1; + mem_txn_i_pending.reset_indicator = 0; + end + {1'b1, mem_rw_mode_e'(RW_READ), 1'b1}: begin + // Another read is requested while the pending read + // is going to be sent + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port1_req = mem_txn_i_pending.mem_port1_req; + mem_txn_i.p1_read_data = mem_vif.mem_s_cb.p1_read_data; + mem_txn_i.p1_write_data = 'h0; + // Read is requested but the RAM needs one cycle to respond + mem_txn_i_pending.mem_port1_req = mem_vif.mem_s_cb.mem_port1_req; + readFollowUp = 1; + mem_txn_i_pending.reset_indicator = 0; + mem_ap.write(mem_txn_i); + end + {1'b1, mem_rw_mode_e'(RW_IDLE), 1'b0}: begin + // Memory is Idle + end + {1'b1, mem_rw_mode_e'(RW_IDLE), 1'b1}: begin + // Mem is in the idle state but there is also a pending read + mem_txn_i = mem_txn::type_id::create("mem_txn_i"); + mem_txn_i.mem_port1_req = mem_txn_i_pending.mem_port1_req; + mem_txn_i.p1_read_data = mem_vif.mem_s_cb.p1_read_data; + mem_txn_i.p1_write_data = 'h0; + readFollowUp = 0; + mem_txn_i_pending.reset_indicator = 0; + // Pending read request is being sent + mem_ap.write(mem_txn_i); + end + default: begin + // Handle unexpected states + `uvm_error("MEM_MON", "Unexpected state in mem_states for port 1") + end + endcase + endtask: mem_port1_read_write_decoder + +endclass \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_sequencer.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_sequencer.sv new file mode 100644 index 0000000000000000000000000000000000000000..66948318153368ef80e941aaf8ca62e2914fafe5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_sequencer.sv @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +typedef uvm_sequencer#(mem_txn) mem_sequencer; \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_txn.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_txn.sv new file mode 100644 index 0000000000000000000000000000000000000000..f0b3785507d200a4b9563743bb11c244d38cf348 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/mem_agent/mem_txn.sv @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// import ntt_utb_defines::*; +// import ntt_defines_pkg::*; +// import uvm_pkg::*; + + +class mem_txn extends uvm_sequence_item; + + rand bit reset_n; + rand bit reset_indicator; + rand mem_if_t mem_port0_req; + rand mem_if_t mem_port1_req; + rand bit [MLDSA_MEM_DATA_WIDTH-1:0] p0_read_data; + rand bit [MLDSA_MEM_DATA_WIDTH-1:0] p0_write_data; + rand bit [MLDSA_MEM_DATA_WIDTH-1:0] p1_read_data; + rand bit [MLDSA_MEM_DATA_WIDTH-1:0] p1_write_data; + rand bit update_mem; + rand bit [MLDSA_MEM_DATA_WIDTH-1:0] artificialMemory []; + + // Define constants + localparam int MLDSA_Q = 23'd8380417; + + + function new(string name = ""); + super.new(name); + artificialMemory = new[MLDSA_MEM_MAX_DEPTH]; + endfunction: new + + //Constraint for artificialMemory + constraint artificialMemory_c { + foreach (artificialMemory[i]) { + (artificialMemory[i][23:0] < MLDSA_Q) && + (artificialMemory[i][47:24] < MLDSA_Q) && + (artificialMemory[i][71:48] < MLDSA_Q) && + (artificialMemory[i][95:72] < MLDSA_Q); + } + } + + + `uvm_object_utils_begin(mem_txn) + `uvm_field_int(reset_n, UVM_ALL_ON) + `uvm_field_int(mem_port0_req.addr, UVM_ALL_ON) + `uvm_field_enum(mem_rw_mode_e, mem_port0_req.rd_wr_en, UVM_ALL_ON) + `uvm_field_int(mem_port1_req.addr, UVM_ALL_ON) + `uvm_field_enum(mem_rw_mode_e, mem_port1_req.rd_wr_en, UVM_ALL_ON) + `uvm_field_int(p0_read_data, UVM_ALL_ON) + `uvm_field_int(p0_write_data, UVM_ALL_ON) + `uvm_field_int(p1_read_data, UVM_ALL_ON) + `uvm_field_int(p1_write_data, UVM_ALL_ON) + `uvm_field_int(update_mem, UVM_ALL_ON) + `uvm_field_array_int(artificialMemory, UVM_ALL_ON) + `uvm_object_utils_end + + + +endclass: mem_txn diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_agent.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_agent.sv new file mode 100644 index 0000000000000000000000000000000000000000..e5cc6490c58c21f5647a4f07f986c4ebcfbf5082 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_agent.sv @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_agent extends uvm_agent; + + `uvm_component_utils(ntt_agent) + + uvm_analysis_port#(ntt_txn) ntt_ap; + + ntt_sequencer ntt_sqcr_i; + ntt_driver ntt_driver_i; + ntt_mon ntt_input_mon_i; + + function new(string name, uvm_component parent); + super.new(name, parent); + ntt_ap = new("ntt_ap", this); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + ntt_sqcr_i = ntt_sequencer::type_id::create(.name("ntt_sqcr_i"), .parent(this)); + ntt_driver_i = ntt_driver::type_id::create(.name("ntt_driver_i"), .parent(this)); + ntt_input_mon_i = ntt_mon::type_id::create(.name("ntt_input_mon_i"), .parent(this)); + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + ntt_driver_i.seq_item_port.connect(ntt_sqcr_i.seq_item_export); + ntt_input_mon_i.ntt_input_ap.connect(ntt_ap); + endfunction: connect_phase + +endclass: ntt_agent \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_driver.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_driver.sv new file mode 100644 index 0000000000000000000000000000000000000000..a8f7f04089d8924c393ab744476a8c8014bba7a5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_driver.sv @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_driver extends uvm_driver#(ntt_txn); + `uvm_component_utils(ntt_driver) + + virtual ntt_if ntt_vif; + // Member variables to store the base addresses + ntt_mem_addr_t stored_ntt_mem_base_addr; + pwo_mem_addr_t stored_pwo_mem_base_addr; + mode_t mode; + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase + + task run_phase(uvm_phase phase); + + ntt_txn ntt_txn_i; + int txn_count; + + txn_count = 1; + stored_ntt_mem_base_addr <= '{default:0}; + stored_pwo_mem_base_addr <= '{default:0}; + + forever begin + @ntt_vif.ntt_m_cb; + seq_item_port.try_next_item(ntt_txn_i); + if(ntt_txn_i != null ) begin + ntt_vif.ntt_m_cb.zeroize <= ntt_txn_i.zeroize; + ntt_vif.ntt_m_cb.mode <= ntt_txn_i.mode; + ntt_vif.ntt_m_cb.ntt_enable <= ntt_txn_i.ntt_enable; + + ntt_vif.ntt_m_cb.ntt_mem_base_addr <= ntt_txn_i.ntt_mem_base_addr; + ntt_vif.ntt_m_cb.pwo_mem_base_addr <= ntt_txn_i.pwo_mem_base_addr; + + // Update stored values with the new transaction values + stored_ntt_mem_base_addr <= ntt_txn_i.ntt_mem_base_addr; + stored_pwo_mem_base_addr <= ntt_txn_i.pwo_mem_base_addr; + mode <= ntt_txn_i.mode; + + ntt_vif.ntt_m_cb.accumulate <= ntt_txn_i.accumulate; + ntt_vif.ntt_m_cb.sampler_valid <= ntt_txn_i.sampler_valid; + ntt_vif.ntt_m_cb.sampler_mode <= ntt_txn_i.sampler_mode; + ntt_vif.ntt_m_cb.sampler_data <= ntt_txn_i.sampler_data; + seq_item_port.item_done(); + end else begin + ntt_vif.ntt_m_cb.zeroize <= 'h0; + ntt_vif.ntt_m_cb.mode <= mode; + ntt_vif.ntt_m_cb.ntt_enable <= 'h0; + + // Use stored values instead of resetting to zero + ntt_vif.ntt_m_cb.ntt_mem_base_addr <= stored_ntt_mem_base_addr; + ntt_vif.ntt_m_cb.pwo_mem_base_addr <= stored_pwo_mem_base_addr; + + ntt_vif.ntt_m_cb.accumulate <= 'h0; + ntt_vif.ntt_m_cb.sampler_valid <= 'h0; + ntt_vif.ntt_m_cb.sampler_mode <= 'h0; + ntt_vif.ntt_m_cb.sampler_data <= 'h0; + end + end + + endtask + +endclass \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_mon.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_mon.sv new file mode 100644 index 0000000000000000000000000000000000000000..49af8aa4f5477f4bea8ad5c071550ebccafd7a85 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_mon.sv @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_mon extends uvm_monitor; + + `uvm_component_utils(ntt_mon) + + // Analysis port for sending transactions to the scoreboard + uvm_analysis_port#(ntt_txn) ntt_input_ap; + // Virtual interface for connecting to the DUT signals + virtual ntt_if ntt_vif; + + // Constructor to initialize the monitor + function new(string name, uvm_component parent); + super.new(name, parent); + ntt_input_ap = new("ntt_input_ap", this); + endfunction: new + + // Build phase to get the virtual interface + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase + + // Run phase to monitor the DUT signals and send transactions to the scoreboard + task run_phase(uvm_phase phase); + int stage_idx = 0; // Variable to track the current stage index + + forever begin + @ntt_vif.ntt_s_cb; // Wait for a change on the ntt_s_cb signal + + if (ntt_vif.ntt_s_cb.ntt_enable) begin + ntt_txn ntt_txn_i; + ntt_txn_i = ntt_txn::type_id::create("ntt_txn_i"); + + // Capture relevant signals from the DUT + ntt_txn_i.zeroize = ntt_vif.ntt_s_cb.zeroize; + ntt_txn_i.mode = ntt_vif.ntt_s_cb.mode; + ntt_txn_i.ntt_enable = ntt_vif.ntt_s_cb.ntt_enable; + ntt_txn_i.ntt_mem_base_addr = ntt_vif.ntt_s_cb.ntt_mem_base_addr; + ntt_txn_i.pwo_mem_base_addr = ntt_vif.ntt_s_cb.pwo_mem_base_addr; + ntt_txn_i.accumulate = ntt_vif.ntt_s_cb.accumulate; + ntt_txn_i.sampler_valid = ntt_vif.ntt_s_cb.sampler_valid; + ntt_txn_i.sampler_mode = ntt_vif.ntt_s_cb.sampler_mode; + ntt_txn_i.sampler_data = ntt_vif.ntt_s_cb.sampler_data; + ntt_txn_i.ntt_done = ntt_vif.ntt_s_cb.ntt_done; + ntt_txn_i.stage_done = 0; // Set stage_done to 0 initially + ntt_txn_i.stage_idx = 0; // Set stage_idx to 0 initially + + // Initialize stage index when ntt_enable is asserted + stage_idx = 0; + + // Send the transaction to the scoreboard + ntt_input_ap.write(ntt_txn_i); + end + else if (ntt_vif.ntt_s_cb.stage_done) begin + ntt_txn ntt_txn_i; + ntt_txn_i = ntt_txn::type_id::create("ntt_txn_i"); + + // Capture relevant signals from the DUT + ntt_txn_i.zeroize = ntt_vif.ntt_s_cb.zeroize; + ntt_txn_i.mode = ntt_vif.ntt_s_cb.mode; + ntt_txn_i.ntt_enable = ntt_vif.ntt_s_cb.ntt_enable; + ntt_txn_i.ntt_mem_base_addr = ntt_vif.ntt_s_cb.ntt_mem_base_addr; + ntt_txn_i.pwo_mem_base_addr = ntt_vif.ntt_s_cb.pwo_mem_base_addr; + ntt_txn_i.accumulate = ntt_vif.ntt_s_cb.accumulate; + ntt_txn_i.sampler_valid = ntt_vif.ntt_s_cb.sampler_valid; + ntt_txn_i.sampler_mode = ntt_vif.ntt_s_cb.sampler_mode; + ntt_txn_i.sampler_data = ntt_vif.ntt_s_cb.sampler_data; + ntt_txn_i.ntt_done = ntt_vif.ntt_s_cb.ntt_done; + ntt_txn_i.stage_done = ntt_vif.ntt_s_cb.stage_done; + ntt_txn_i.stage_idx = stage_idx; // Set stage_idx to 0 initially + stage_idx++; + + // Send the transaction to the scoreboard + ntt_input_ap.write(ntt_txn_i); + end + else if (ntt_vif.ntt_s_cb.ntt_done) begin + ntt_txn ntt_txn_i; + ntt_txn_i = ntt_txn::type_id::create("ntt_txn_i"); + + // Capture relevant signals from the DUT + ntt_txn_i.zeroize = ntt_vif.ntt_s_cb.zeroize; + ntt_txn_i.mode = ntt_vif.ntt_s_cb.mode; + ntt_txn_i.ntt_enable = ntt_vif.ntt_s_cb.ntt_enable; + ntt_txn_i.ntt_mem_base_addr = ntt_vif.ntt_s_cb.ntt_mem_base_addr; + ntt_txn_i.pwo_mem_base_addr = ntt_vif.ntt_s_cb.pwo_mem_base_addr; + ntt_txn_i.accumulate = ntt_vif.ntt_s_cb.accumulate; + ntt_txn_i.sampler_valid = ntt_vif.ntt_s_cb.sampler_valid; + ntt_txn_i.sampler_mode = ntt_vif.ntt_s_cb.sampler_mode; + ntt_txn_i.sampler_data = ntt_vif.ntt_s_cb.sampler_data; + ntt_txn_i.ntt_done = ntt_vif.ntt_s_cb.ntt_done; + ntt_txn_i.stage_done = ntt_vif.ntt_s_cb.stage_done; + ntt_txn_i.stage_idx = stage_idx; // Set stage_idx to 0 initially + + // Send the transaction to the scoreboard + ntt_input_ap.write(ntt_txn_i); + end + end + endtask + +endclass + + + + +// class ntt_mon extends uvm_monitor; + +// `uvm_component_utils(ntt_mon) + +// uvm_analysis_port#(ntt_txn) ntt_input_ap; +// virtual ntt_if ntt_vif; + +// function new(string name, uvm_component parent); +// super.new(name, parent); +// ntt_input_ap = new("ntt_input_ap", this); +// endfunction: new + +// function void build_phase(uvm_phase phase); +// super.build_phase(phase); +// // assert( uvm_config_db#( virtual ntt_if )::get( this, "", "ntt_vif", ntt_vif)); +// endfunction: build_phase + +// task run_phase(uvm_phase phase); + +// forever begin +// @ntt_vif.ntt_s_cb; +// if(ntt_vif.ntt_s_cb.ntt_enable) begin +// ntt_txn ntt_txn_i; +// ntt_txn_i = ntt_txn::type_id::create("ntt_txn_i"); + +// ntt_txn_i.zeroize = ntt_vif.ntt_s_cb.zeroize; +// ntt_txn_i.mode = ntt_vif.ntt_s_cb.mode; +// ntt_txn_i.ntt_enable = ntt_vif.ntt_s_cb.ntt_enable; + +// ntt_txn_i.ntt_mem_base_addr = ntt_vif.ntt_s_cb.ntt_mem_base_addr; +// ntt_txn_i.pwo_mem_base_addr = ntt_vif.ntt_s_cb.pwo_mem_base_addr; + +// ntt_txn_i.accumulate = ntt_vif.ntt_s_cb.accumulate; +// ntt_txn_i.sampler_valid = ntt_vif.ntt_s_cb.sampler_valid; +// ntt_txn_i.sampler_mode = ntt_vif.ntt_s_cb.sampler_mode; +// ntt_txn_i.sampler_data = ntt_vif.ntt_s_cb.sampler_data; + +// ntt_txn_i.ntt_done = ntt_vif.ntt_s_cb.ntt_done; + +// ntt_input_ap.write(ntt_txn_i); +// end +// end + +// endtask + +// endclass \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_sequencer.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_sequencer.sv new file mode 100644 index 0000000000000000000000000000000000000000..ee3d7c46be6aac63e32fa47a071e3c701ac95ca2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_sequencer.sv @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +typedef uvm_sequencer#(ntt_txn) ntt_sequencer; \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_txn.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_txn.sv new file mode 100644 index 0000000000000000000000000000000000000000..4665ffa614640ca9aedbb73411ff61900306f94a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_agent/ntt_txn.sv @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// import ntt_utb_defines::*; +// import ntt_defines_pkg::*; + +class ntt_txn extends uvm_sequence_item; + + rand bit zeroize; + rand mode_t mode; + rand bit ntt_enable; + + + rand ntt_mem_addr_t ntt_mem_base_addr; + rand pwo_mem_addr_t pwo_mem_base_addr; + + rand bit accumulate; + rand bit sampler_valid; + rand bit sampler_mode; + rand bit [MLDSA_MEM_DATA_WIDTH-1:0] sampler_data; + rand bit ntt_done; + rand bit stage_done; + rand int stage_idx; + + localparam MEM_DEPTH = MLDSA_MEM_MAX_DEPTH; + + constraint ntt_c { + ntt_enable == 1; + } + + + // Constraints for ntt_mem_base_addr + constraint ntt_mem_base_addr_c { + // src_base_addr must be a multiple of 64 and within the valid address range + ntt_mem_base_addr.src_base_addr % 64 == 0; + ntt_mem_base_addr.src_base_addr < (MEM_DEPTH-64); + + ntt_mem_base_addr.interim_base_addr == ntt_mem_base_addr.src_base_addr + 64; + + // dest_base_addr must be a multiple of 64, within the valid address range, and different from src_base_addr + ntt_mem_base_addr.dest_base_addr % 64 == 0; + ntt_mem_base_addr.dest_base_addr < (MEM_DEPTH-64); + ntt_mem_base_addr.dest_base_addr != ntt_mem_base_addr.interim_base_addr; + } + + function new(string name = ""); + super.new(name); + endfunction: new + + `uvm_object_utils_begin(ntt_txn) + `uvm_field_int(zeroize, UVM_ALL_ON) + `uvm_field_int(mode, UVM_ALL_ON) + `uvm_field_int(ntt_enable, UVM_ALL_ON) + `uvm_field_int(ntt_mem_base_addr.src_base_addr, UVM_ALL_ON) + `uvm_field_int(ntt_mem_base_addr.interim_base_addr, UVM_ALL_ON) + `uvm_field_int(ntt_mem_base_addr.dest_base_addr, UVM_ALL_ON) + `uvm_field_int(pwo_mem_base_addr.pw_base_addr_a, UVM_ALL_ON) + `uvm_field_int(pwo_mem_base_addr.pw_base_addr_b, UVM_ALL_ON) + `uvm_field_int(pwo_mem_base_addr.pw_base_addr_c, UVM_ALL_ON) + `uvm_field_int(accumulate, UVM_ALL_ON) + `uvm_field_int(sampler_valid, UVM_ALL_ON) + `uvm_field_int(sampler_mode, UVM_ALL_ON) + `uvm_field_int(sampler_data, UVM_ALL_ON) + `uvm_field_int(stage_done, UVM_ALL_ON) + `uvm_field_int(stage_idx, UVM_ALL_ON) + `uvm_object_utils_end + +endclass: ntt_txn diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_utb_top/ntt_utb_defines.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_utb_top/ntt_utb_defines.sv new file mode 100644 index 0000000000000000000000000000000000000000..fd771c6b5cacc5285c44dd855139b60b157e5fda --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_utb_top/ntt_utb_defines.sv @@ -0,0 +1,539 @@ + +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +import uvm_pkg::*; + +`uvm_analysis_imp_decl(_ntt_txn) +`uvm_analysis_imp_decl(_ntt_mem_txn) +`uvm_analysis_imp_decl(_pwm_a_mem_txn) +`uvm_analysis_imp_decl(_pwm_b_mem_txn) + +parameter logic [22:0] zetas[0:255] = '{ + 23'd1, + 23'd4808194, + 23'd3765607, + 23'd3761513, + 23'd5178923, + 23'd5496691, + 23'd5234739, + 23'd5178987, + 23'd7778734, + 23'd3542485, + 23'd2682288, + 23'd2129892, + 23'd3764867, + 23'd7375178, + 23'd557458, + 23'd7159240, + 23'd5010068, + 23'd4317364, + 23'd2663378, + 23'd6705802, + 23'd4855975, + 23'd7946292, + 23'd676590, + 23'd7044481, + 23'd5152541, + 23'd1714295, + 23'd2453983, + 23'd1460718, + 23'd7737789, + 23'd4795319, + 23'd2815639, + 23'd2283733, + 23'd3602218, + 23'd3182878, + 23'd2740543, + 23'd4793971, + 23'd5269599, + 23'd2101410, + 23'd3704823, + 23'd1159875, + 23'd394148, + 23'd928749, + 23'd1095468, + 23'd4874037, + 23'd2071829, + 23'd4361428, + 23'd3241972, + 23'd2156050, + 23'd3415069, + 23'd1759347, + 23'd7562881, + 23'd4805951, + 23'd3756790, + 23'd6444618, + 23'd6663429, + 23'd4430364, + 23'd5483103, + 23'd3192354, + 23'd556856, + 23'd3870317, + 23'd2917338, + 23'd1853806, + 23'd3345963, + 23'd1858416, + 23'd3073009, + 23'd1277625, + 23'd5744944, + 23'd3852015, + 23'd4183372, + 23'd5157610, + 23'd5258977, + 23'd8106357, + 23'd2508980, + 23'd2028118, + 23'd1937570, + 23'd4564692, + 23'd2811291, + 23'd5396636, + 23'd7270901, + 23'd4158088, + 23'd1528066, + 23'd482649, + 23'd1148858, + 23'd5418153, + 23'd7814814, + 23'd169688, + 23'd2462444, + 23'd5046034, + 23'd4213992, + 23'd4892034, + 23'd1987814, + 23'd5183169, + 23'd1736313, + 23'd235407, + 23'd5130263, + 23'd3258457, + 23'd5801164, + 23'd1787943, + 23'd5989328, + 23'd6125690, + 23'd3482206, + 23'd4197502, + 23'd7080401, + 23'd6018354, + 23'd7062739, + 23'd2461387, + 23'd3035980, + 23'd621164, + 23'd3901472, + 23'd7153756, + 23'd2925816, + 23'd3374250, + 23'd1356448, + 23'd5604662, + 23'd2683270, + 23'd5601629, + 23'd4912752, + 23'd2312838, + 23'd7727142, + 23'd7921254, + 23'd348812, + 23'd8052569, + 23'd1011223, + 23'd6026202, + 23'd4561790, + 23'd6458164, + 23'd6143691, + 23'd1744507, + 23'd1753, + 23'd6444997, + 23'd5720892, + 23'd6924527, + 23'd2660408, + 23'd6600190, + 23'd8321269, + 23'd2772600, + 23'd1182243, + 23'd87208, + 23'd636927, + 23'd4415111, + 23'd4423672, + 23'd6084020, + 23'd5095502, + 23'd4663471, + 23'd8352605, + 23'd822541, + 23'd1009365, + 23'd5926272, + 23'd6400920, + 23'd1596822, + 23'd4423473, + 23'd4620952, + 23'd6695264, + 23'd4969849, + 23'd2678278, + 23'd4611469, + 23'd4829411, + 23'd635956, + 23'd8129971, + 23'd5925040, + 23'd4234153, + 23'd6607829, + 23'd2192938, + 23'd6653329, + 23'd2387513, + 23'd4768667, + 23'd8111961, + 23'd5199961, + 23'd3747250, + 23'd2296099, + 23'd1239911, + 23'd4541938, + 23'd3195676, + 23'd2642980, + 23'd1254190, + 23'd8368000, + 23'd2998219, + 23'd141835, + 23'd8291116, + 23'd2513018, + 23'd7025525, + 23'd613238, + 23'd7070156, + 23'd6161950, + 23'd7921677, + 23'd6458423, + 23'd4040196, + 23'd4908348, + 23'd2039144, + 23'd6500539, + 23'd7561656, + 23'd6201452, + 23'd6757063, + 23'd2105286, + 23'd6006015, + 23'd6346610, + 23'd586241, + 23'd7200804, + 23'd527981, + 23'd5637006, + 23'd6903432, + 23'd1994046, + 23'd2491325, + 23'd6987258, + 23'd507927, + 23'd7192532, + 23'd7655613, + 23'd6545891, + 23'd5346675, + 23'd8041997, + 23'd2647994, + 23'd3009748, + 23'd5767564, + 23'd4148469, + 23'd749577, + 23'd4357667, + 23'd3980599, + 23'd2569011, + 23'd6764887, + 23'd1723229, + 23'd1665318, + 23'd2028038, + 23'd1163598, + 23'd5011144, + 23'd3994671, + 23'd8368538, + 23'd7009900, + 23'd3020393, + 23'd3363542, + 23'd214880, + 23'd545376, + 23'd7609976, + 23'd3105558, + 23'd7277073, + 23'd508145, + 23'd7826699, + 23'd860144, + 23'd3430436, + 23'd140244, + 23'd6866265, + 23'd6195333, + 23'd3123762, + 23'd2358373, + 23'd6187330, + 23'd5365997, + 23'd6663603, + 23'd2926054, + 23'd7987710, + 23'd8077412, + 23'd3531229, + 23'd4405932, + 23'd4606686, + 23'd1900052, + 23'd7598542, + 23'd1054478, + 23'd7648983 +}; + +logic [23:0] zetas_inv[0:255] = '{ + 23'd8380416, + 23'd3572223, + 23'd4614810, + 23'd4618904, + 23'd3201494, + 23'd2883726, + 23'd3145678, + 23'd3201430, + 23'd601683, + 23'd4837932, + 23'd5698129, + 23'd6250525, + 23'd4615550, + 23'd1005239, + 23'd7822959, + 23'd1221177, + 23'd3370349, + 23'd4063053, + 23'd5717039, + 23'd1674615, + 23'd3524442, + 23'd434125, + 23'd7703827, + 23'd1335936, + 23'd3227876, + 23'd6666122, + 23'd5926434, + 23'd6919699, + 23'd642628, + 23'd3585098, + 23'd5564778, + 23'd6096684, + 23'd4778199, + 23'd5197539, + 23'd5639874, + 23'd3586446, + 23'd3110818, + 23'd6279007, + 23'd4675594, + 23'd7220542, + 23'd7986269, + 23'd7451668, + 23'd7284949, + 23'd3506380, + 23'd6308588, + 23'd4018989, + 23'd5138445, + 23'd6224367, + 23'd4965348, + 23'd6621070, + 23'd817536, + 23'd3574466, + 23'd4623627, + 23'd1935799, + 23'd1716988, + 23'd3950053, + 23'd2897314, + 23'd5188063, + 23'd7823561, + 23'd4510100, + 23'd5463079, + 23'd6526611, + 23'd5034454, + 23'd6522001, + 23'd5307408, + 23'd7102792, + 23'd2635473, + 23'd4528402, + 23'd4197045, + 23'd3222807, + 23'd3121440, + 23'd274060, + 23'd5871437, + 23'd6352299, + 23'd6442847, + 23'd3815725, + 23'd5569126, + 23'd2983781, + 23'd1109516, + 23'd4222329, + 23'd6852351, + 23'd7897768, + 23'd7231559, + 23'd2962264, + 23'd565603, + 23'd8210729, + 23'd5917973, + 23'd3334383, + 23'd4166425, + 23'd3488383, + 23'd6392603, + 23'd3197248, + 23'd6644104, + 23'd8145010, + 23'd3250154, + 23'd5121960, + 23'd2579253, + 23'd6592474, + 23'd2391089, + 23'd2254727, + 23'd4898211, + 23'd4182915, + 23'd1300016, + 23'd2362063, + 23'd1317678, + 23'd5919030, + 23'd5344437, + 23'd7759253, + 23'd4478945, + 23'd1226661, + 23'd5454601, + 23'd5006167, + 23'd7023969, + 23'd2775755, + 23'd5697147, + 23'd2778788, + 23'd3467665, + 23'd6067579, + 23'd653275, + 23'd459163, + 23'd8031605, + 23'd327848, + 23'd7369194, + 23'd2354215, + 23'd3818627, + 23'd1922253, + 23'd2236726, + 23'd6635910, + 23'd8378664, + 23'd1935420, + 23'd2659525, + 23'd1455890, + 23'd5720009, + 23'd1780227, + 23'd59148, + 23'd5607817, + 23'd7198174, + 23'd8293209, + 23'd7743490, + 23'd3965306, + 23'd3956745, + 23'd2296397, + 23'd3284915, + 23'd3716946, + 23'd27812, + 23'd7557876, + 23'd7371052, + 23'd2454145, + 23'd1979497, + 23'd6783595, + 23'd3956944, + 23'd3759465, + 23'd1685153, + 23'd3410568, + 23'd5702139, + 23'd3768948, + 23'd3551006, + 23'd7744461, + 23'd250446, + 23'd2455377, + 23'd4146264, + 23'd1772588, + 23'd6187479, + 23'd1727088, + 23'd5992904, + 23'd3611750, + 23'd268456, + 23'd3180456, + 23'd4633167, + 23'd6084318, + 23'd7140506, + 23'd3838479, + 23'd5184741, + 23'd5737437, + 23'd7126227, + 23'd12417, + 23'd5382198, + 23'd8238582, + 23'd89301, + 23'd5867399, + 23'd1354892, + 23'd7767179, + 23'd1310261, + 23'd2218467, + 23'd458740, + 23'd1921994, + 23'd4340221, + 23'd3472069, + 23'd6341273, + 23'd1879878, + 23'd818761, + 23'd2178965, + 23'd1623354, + 23'd6275131, + 23'd2374402, + 23'd2033807, + 23'd7794176, + 23'd1179613, + 23'd7852436, + 23'd2743411, + 23'd1476985, + 23'd6386371, + 23'd5889092, + 23'd1393159, + 23'd7872490, + 23'd1187885, + 23'd724804, + 23'd1834526, + 23'd3033742, + 23'd338420, + 23'd5732423, + 23'd5370669, + 23'd2612853, + 23'd4231948, + 23'd7630840, + 23'd4022750, + 23'd4399818, + 23'd5811406, + 23'd1615530, + 23'd6657188, + 23'd6715099, + 23'd6352379, + 23'd7216819, + 23'd3369273, + 23'd4385746, + 23'd11879, + 23'd1370517, + 23'd5360024, + 23'd5016875, + 23'd8165537, + 23'd7835041, + 23'd770441, + 23'd5274859, + 23'd1103344, + 23'd7872272, + 23'd553718, + 23'd7520273, + 23'd4949981, + 23'd8240173, + 23'd1514152, + 23'd2185084, + 23'd5256655, + 23'd6022044, + 23'd2193087, + 23'd3014420, + 23'd1716814, + 23'd5454363, + 23'd392707, + 23'd303005, + 23'd4849188, + 23'd3974485, + 23'd3773731, + 23'd6480365, + 23'd781875, + 23'd7325939, + 23'd731434 +}; \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_utb_top/ntt_utb_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_utb_top/ntt_utb_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..dd5f5d513d60552ed59fb77f5c2788413ab7ffc5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/ntt_utb_top/ntt_utb_top.sv @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// import ntt_defines_pkg::*; + +module ntt_utb_top + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = 24, + parameter RADIX = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_N = 256 +); + + // Clock and reset + bit clk; + bit rst; + + ntt_if ntt_if_i(clk); + mem_if ntt_mem_if_i(clk); + mem_if pwm_a_mem_if_i(clk); + mem_if pwm_b_mem_if_i(clk); + + // Connect reset to the interfaces + assign ntt_if_i.reset_n = rst; + assign ntt_mem_if_i.reset_n = rst; + assign pwm_a_mem_if_i.reset_n = rst; + assign pwm_b_mem_if_i.reset_n = rst; + + // UNUSED PORTs + assign pwm_a_mem_if_i.mem_port0_req.rd_wr_en = mem_rw_mode_e'(RW_IDLE); + assign pwm_a_mem_if_i.mem_port0_req.addr = 'h0; + assign pwm_b_mem_if_i.mem_port0_req.rd_wr_en = mem_rw_mode_e'(RW_IDLE); + assign pwm_b_mem_if_i.mem_port0_req.addr = 'h0; + + //Port a signal that indicates NTT completes its stages + localparam int DELAY_CYCLES = 2; + logic [DELAY_CYCLES-1:0] stage_done_array; + logic delayed_done; + logic wired_ntt_done; + assign ntt_if_i.stage_done = stage_done_array[DELAY_CYCLES-1]; + assign ntt_if_i.ntt_done = delayed_done; + + + + // TAKEN FROM ntt_wrapper + + //NTT, PWM C memory IF + mem_if_t mem_port0_req; + mem_if_t mem_rd_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] mem_wr_data; + logic [MLDSA_MEM_DATA_WIDTH-1:0] mem_rd_data; + + + //PWM A/B, PWA/S memory IF + mem_if_t pwm_a_rd_req; + mem_if_t pwm_b_rd_req; + logic [MLDSA_MEM_DATA_WIDTH-1:0] pwm_a_rd_data; + logic [MLDSA_MEM_DATA_WIDTH-1:0] pwm_b_rd_data; + + //NTT/PWM muxes + logic ntt_mem_wren, ntt_mem_rden; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] ntt_mem_wr_addr; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] ntt_mem_rd_addr; + logic [MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_wr_data; + logic [MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_rd_data; + + logic pwm_mem_a_rden, pwm_mem_b_rden; + + //Modes + logic ct_mode; + logic gs_mode; + logic pwo_mode; + logic pwm_mode, pwa_mode, pws_mode; + + logic [5:0] random_utb; + + assign ct_mode = (ntt_if_i.mode == ct); + assign gs_mode = (ntt_if_i.mode == gs); + assign pwo_mode = (ntt_if_i.mode inside {pwm, pwa, pws}); + assign pwm_mode = (ntt_if_i.mode == pwm); + assign pwa_mode = (ntt_if_i.mode == pwa); + assign pws_mode = (ntt_if_i.mode == pws); + + //NTT mem + assign ntt_mem_wren = (ntt_mem_if_i.mem_port0_req.rd_wr_en == RW_WRITE); + assign ntt_mem_rden = (ntt_mem_if_i.mem_port1_req.rd_wr_en == RW_READ); + + //PWM mem + assign pwm_mem_a_rden = (pwm_a_mem_if_i.mem_port1_req.rd_wr_en == RW_READ); + assign pwm_mem_b_rden = (pwm_b_mem_if_i.mem_port1_req.rd_wr_en == RW_READ); + + ntt_ram_tdp_file #( + .ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH), + .DATA_WIDTH(4*REG_SIZE) + ) ntt_mem ( + .clk(clk), + .reset_n(rst), + .zeroize(ntt_if_i.zeroize), + .ena(ntt_mem_wren), + .wea(ntt_mem_wren), + .addra(ntt_mem_if_i.mem_port0_req.addr), + .dina(ntt_mem_if_i.p0_write_data), + .douta(), //Need only one read port, so this can be 0 + .enb(ntt_mem_rden), + .web(1'b0), //Need only one write port so this can be 0 + .addrb(ntt_mem_if_i.mem_port1_req.addr), + .dinb(), + .doutb(ntt_mem_if_i.p1_read_data), + .load_tb_values(1'b0), + .load_tb_addr({MLDSA_MEM_ADDR_WIDTH{1'b0}}) + ); + + ntt_ram_tdp_file #( + .ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH), + .DATA_WIDTH(4*REG_SIZE) + ) pwm_mem_a ( + .clk(clk), + .reset_n(rst), + .zeroize(ntt_if_i.zeroize), + .ena(), + .wea(), + .addra(), + .dina(), + .douta(), //Need only one read port, so this can be 0 + .enb(pwm_mem_a_rden), //(pw_rden_d1), + .web(1'b0), //Need only one write port so this can be 0 + .addrb(pwm_a_mem_if_i.mem_port1_req.addr), //(pwm_rd_addr_a_reg), + .dinb(), + .doutb(pwm_a_mem_if_i.p1_read_data), + .load_tb_values(1'b0), + .load_tb_addr({MLDSA_MEM_ADDR_WIDTH{1'b0}}) + ); + + ntt_ram_tdp_file #( + .ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH), + .DATA_WIDTH(4*REG_SIZE) + ) pwm_mem_b ( + .clk(clk), + .reset_n(rst), + .zeroize(ntt_if_i.zeroize), + .ena(), + .wea(), + .addra(), + .dina(), + .douta(), //Need only one read port, so this can be 0 + .enb(pwm_mem_b_rden), //(pw_rden_d1), + .web(1'b0), //Need only one write port so this can be 0 + .addrb(pwm_b_mem_if_i.mem_port1_req.addr), //(pwm_rd_addr_b_reg), + .dinb(), + .doutb(pwm_b_mem_if_i.p1_read_data), + .load_tb_values(1'b0), + .load_tb_addr({MLDSA_MEM_ADDR_WIDTH{1'b0}}) + ); + + ntt_top #( + .REG_SIZE(REG_SIZE), + .MLDSA_Q(MLDSA_Q), + .MLDSA_N(MLDSA_N), + .MEM_ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH) + ) + ntt_top_inst0 ( + .clk(clk), + .reset_n(rst), + .zeroize(ntt_if_i.zeroize), + .mode(ntt_if_i.mode), + .ntt_enable(ntt_if_i.ntt_enable), + + .ntt_mem_base_addr(ntt_if_i.ntt_mem_base_addr), + .pwo_mem_base_addr(ntt_if_i.pwo_mem_base_addr), + + .accumulate(ntt_if_i.accumulate), + .sampler_valid(ntt_if_i.sampler_valid), + .shuffle_en(1'b0), + .masking_en(1'b0), + .random(random_utb), + .rnd_i(230'h0), + //NTT mem IF + .mem_wr_req(ntt_mem_if_i.mem_port0_req), + .mem_rd_req(ntt_mem_if_i.mem_port1_req), + .mem_wr_data(ntt_mem_if_i.p0_write_data), + .mem_rd_data(ntt_mem_if_i.p1_read_data), + //PWM mem IF + .pwm_a_rd_req(pwm_a_mem_if_i.mem_port1_req), + .pwm_b_rd_req(pwm_b_mem_if_i.mem_port1_req), + .pwm_a_rd_data(pwm_a_mem_if_i.p1_read_data), + .pwm_b_rd_data(ntt_if_i.sampler_mode ? ntt_if_i.sampler_data : pwm_a_mem_if_i.p1_read_data), + .ntt_busy(), + .ntt_done(wired_ntt_done) + ); + + + always_ff @(posedge clk) begin + stage_done_array <= {stage_done_array[DELAY_CYCLES-2:0], ntt_top_inst0.ntt_ctrl_inst0.stage_done}; + delayed_done <= wired_ntt_done; + end + + always begin + #1 clk = ~clk; + random_utb = {4'h5, $urandom_range(0,3)}; + end + + initial begin + clk = 0; + rst = 1; + #10; rst = 0; + #10; rst = 1; + end + + initial begin + // Set the virtual interfaces in the UVM configuration database + ntt_mem_if_i.mem_path = "mem_ntt"; + pwm_a_mem_if_i.mem_path = "mem_pwm_a"; + pwm_b_mem_if_i.mem_path = "mem_pwm_b"; + uvm_config_db#(virtual ntt_if)::set(null, "*", "ntt_vif", ntt_if_i); + uvm_config_db#(virtual mem_if)::set(null, "*", "ntt_mem_vif", ntt_mem_if_i); + uvm_config_db#(virtual mem_if)::set(null, "*", "pwm_a_mem_vif", pwm_a_mem_if_i); + uvm_config_db#(virtual mem_if)::set(null, "*", "pwm_b_mem_vif", pwm_b_mem_if_i); + run_test(); + end + + +endmodule: ntt_utb_top \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/scoreboard/ntt_sb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/scoreboard/ntt_sb.sv new file mode 100644 index 0000000000000000000000000000000000000000..cd4595ebeb79bdc27f156d0d262122c591ce148f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/scoreboard/ntt_sb.sv @@ -0,0 +1,667 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_sb extends uvm_scoreboard; + // import mldsa_params_pkg::*; + `uvm_component_utils(ntt_sb) + + uvm_analysis_imp_ntt_txn#(ntt_txn, ntt_sb) ntt_ap; + + uvm_analysis_imp_ntt_mem_txn#(mem_txn, ntt_sb) ntt_mem_ap; + uvm_analysis_imp_pwm_a_mem_txn#(mem_txn, ntt_sb) pwm_a_mem_ap; + uvm_analysis_imp_pwm_b_mem_txn#(mem_txn, ntt_sb) pwm_b_mem_ap; + + + + localparam MLDSA_Q = 23'd8380417; + localparam MLDSA_N = 256; + localparam MLDSA_LOGN = $clog2(MLDSA_N); + localparam f= 8347681; // 256^-1 mod MLDSA_Q + localparam MEM_DEPTH = MLDSA_MEM_MAX_DEPTH; + // Memory models for the three memories + bit [MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_model [0:MEM_DEPTH-1]; + bit [MLDSA_MEM_DATA_WIDTH-1:0] pwm_a_mem_model [0:MEM_DEPTH-1]; + bit [MLDSA_MEM_DATA_WIDTH-1:0] pwm_b_mem_model [0:MEM_DEPTH-1]; + + bit [MLDSA_MEM_DATA_WIDTH-1:0] ntt_model_inputs [0:MEM_DEPTH-1]; + bit [MLDSA_MEM_DATA_WIDTH-1:0] pwm_a_model_inputs [0:MEM_DEPTH-1]; + bit [MLDSA_MEM_DATA_WIDTH-1:0] pwm_b_model_inputs [0:MEM_DEPTH-1]; + + bit [REG_SIZE-1:0] One_NTT_input [0:MLDSA_N-1]; + bit [REG_SIZE-1:0] model_NTT_output [0:MLDSA_N-1]; + bit [REG_SIZE-1:0] DUT_NTT_output [0:MLDSA_N-1]; + + bit [REG_SIZE-1:0] ntt_memory_for_stages[0:3][0:MLDSA_N-1]; + bit [REG_SIZE-1:0] model_stage_memory[0:3][0:MLDSA_N-1]; + + //try get from each export and print the transactions + ntt_txn ntt_input_txn; + + mem_txn ntt_mem_txn; + mem_txn pwm_a_mem_txn; + mem_txn pwm_b_mem_txn; + + //NTT address assignments: + ntt_mem_addr_t ntt_mem_addrs; + // This bit indicatres that NTT operation ha been started + // another enable is going to be discarded until DUT asserts + // the done signal high. + logic ntt_lock; + // Presents the ntt mode selection. + mode_t mode; + + function new(string name, uvm_component parent); + super.new(name, parent); + ntt_ap = new("ntt_ap", this); + ntt_mem_ap = new("ntt_mem_ap", this); + pwm_a_mem_ap = new("pwm_a_mem_ap", this); + pwm_b_mem_ap = new("pwm_b_mem_ap", this); + ntt_lock = 1'b0; + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction: connect_phase + + virtual function void write_ntt_txn(ntt_txn txn); + ntt_input_txn = txn; + if (ntt_input_txn.ntt_enable == 1'b1 && + (ntt_input_txn.mode == mode_t'(ct) || ntt_input_txn.mode == mode_t'(gs)) && + ntt_lock != 1'b1 + ) begin + // NTT src, dest and iterim addresses are locked. + ntt_mem_addrs = ntt_input_txn.ntt_mem_base_addr; + // NTT mode is locked. + mode = ntt_input_txn.mode; + // NTT locked the NTT check mechanism. + ntt_lock = 1'b1; + + if (mode == mode_t'(ct)) begin + `uvm_info("ntt_sb", "Going to extract NTT coefficients from input vectors", UVM_LOW) + extract_256_coeffs(ntt_model_inputs, ntt_mem_addrs.src_base_addr, -1, One_NTT_input); + // Perform forward NTT + `uvm_info("ntt_sb", "Performing forward NTT with model input", UVM_LOW) + fwd_NTT(One_NTT_input, model_NTT_output); + fwd_2x2_NTT(One_NTT_input, model_stage_memory); + end + else begin + `uvm_info("ntt_sb", "Going to extract INTT coefficients from input vectors", UVM_LOW) + extract_256_coeffs(ntt_model_inputs, ntt_mem_addrs.src_base_addr, -1, One_NTT_input); + // Perform forward NTT + `uvm_info("ntt_sb", "Performing inverse NTT with model input", UVM_LOW) + inv_NTT(One_NTT_input, model_NTT_output); + inv_2x2_NTT_div2(One_NTT_input, model_stage_memory); + end + end + if (ntt_input_txn.stage_done == 1'b1 && ntt_lock == 1'b1) begin + extract_DUTs_NTT_stage_outputs(ntt_input_txn.stage_idx); + end + if (ntt_input_txn.ntt_done == 1'b1 && ntt_lock == 1'b1) begin + `uvm_info("ntt_sb", "Going to extract computed NTT coefficients from DUT", UVM_LOW) + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.dest_base_addr, 3, DUT_NTT_output); + // Compare model and DUT outputs + `uvm_info("ntt_sb", "Comparing model and DUT outputs", UVM_LOW) + compare_E2E_ntt_model_outputs(); + compare_ntt_stages(); + ntt_lock = 1'b0; + end + + `uvm_info("ntt_sb", $sformatf("ntt_input_txn: %s", ntt_input_txn.sprint()), UVM_MEDIUM) + endfunction + + virtual function void write_ntt_mem_txn(mem_txn txn); + ntt_mem_txn = txn; + update_sb_memory_model(ntt_mem_model, ntt_model_inputs, txn); + `uvm_info("ntt_sb", $sformatf("ntt_mem_txn: %s", ntt_mem_txn.sprint()), UVM_MEDIUM) + endfunction + + virtual function void write_pwm_a_mem_txn(mem_txn txn); + pwm_a_mem_txn = txn; + update_sb_memory_model(pwm_a_mem_model, pwm_a_model_inputs, txn); + `uvm_info("ntt_sb", $sformatf("pwm_a_mem_txn: %s", pwm_a_mem_txn.sprint()), UVM_MEDIUM) + endfunction + + virtual function void write_pwm_b_mem_txn(mem_txn txn); + pwm_b_mem_txn = txn; + update_sb_memory_model(pwm_b_mem_model, pwm_b_model_inputs, txn); + `uvm_info("ntt_sb", $sformatf("pwm_b_mem_txn: %s", pwm_b_mem_txn.sprint()), UVM_MEDIUM) + endfunction + + task run_phase(uvm_phase phase); + super.run_phase(phase); + endtask + + + // Function to update the memory model based on the received transactions + function void update_sb_memory_model(ref bit [MLDSA_MEM_DATA_WIDTH-1:0] mem_from_DUT [0:MEM_DEPTH-1], + ref bit [MLDSA_MEM_DATA_WIDTH-1:0] mem_to_model [0:MEM_DEPTH-1], + mem_txn mem_txn_i + ); + if (mem_txn_i.update_mem) begin + for (int i = 0; i < MEM_DEPTH; i++) begin + mem_from_DUT[i] = mem_txn_i.artificialMemory[i]; + mem_to_model[i] = mem_txn_i.artificialMemory[i]; + end + `uvm_info("ntt_sb", "DRIVER UPDATED memory content contents:", UVM_LOW) + end + + if (mem_txn_i.mem_port0_req.rd_wr_en == RW_WRITE) begin + mem_from_DUT[mem_txn_i.mem_port0_req.addr] = mem_txn_i.p0_write_data; + end + if (mem_txn_i.mem_port1_req.rd_wr_en == RW_WRITE) begin + mem_from_DUT[mem_txn_i.mem_port1_req.addr] = mem_txn_i.p1_write_data; + end + endfunction: update_sb_memory_model + + // Function to extract 256 coefficients from the input memory starting at src_base_addr + function void extract_256_coeffs( + input bit [MLDSA_MEM_DATA_WIDTH-1:0] input_memory [0:MEM_DEPTH-1], + input logic [MLDSA_MEM_ADDR_WIDTH-1:0] base_addr, + input int stage_idx, + output bit [REG_SIZE-1:0] NTT_coeffs [0:MLDSA_N-1] + ); + int cnt; + begin + cnt = 0; + if (stage_idx == -1 || stage_idx == 3) begin + // Organize memory into 24-bit coefficients + for (int i = base_addr; i < base_addr+64; i++) begin + NTT_coeffs[4*cnt+0] = input_memory[i][23:0]; // 1st coefficient + NTT_coeffs[4*cnt+1] = input_memory[i][47:24]; // 2nd coefficient + NTT_coeffs[4*cnt+2] = input_memory[i][71:48]; // 3rd coefficient + NTT_coeffs[4*cnt+3] = input_memory[i][95:72]; // 4th coefficient + cnt++; + end + end + else if (stage_idx == 0) begin + // Organize memory into 24-bit coefficients with offsets of 64 + for (int i = 0; i < 64; i++) begin + NTT_coeffs[cnt+0] = input_memory[base_addr+i][23:0]; // 1st coefficient + NTT_coeffs[cnt+64] = input_memory[base_addr+i][47:24]; // 65th coefficient + NTT_coeffs[cnt+128] = input_memory[base_addr+i][71:48]; // 129th coefficient + NTT_coeffs[cnt+192] = input_memory[base_addr+i][95:72]; // 193th coefficient + cnt++; + end + end + else if (stage_idx == 1) begin + // Organize memory into 24-bit coefficients with the described offset pattern for addr_offset == 32 + for (int base = 0; base < 16; base++) begin + for (int i = 0; i < 4; i++) begin + int index = base_addr + base*4 + i; + int coeff_index = base + i*64; + NTT_coeffs[coeff_index] = input_memory[index][23:0]; // 1st coefficient + NTT_coeffs[coeff_index+16] = input_memory[index][47:24]; // 2nd coefficient + NTT_coeffs[coeff_index+32] = input_memory[index][71:48]; // 3rd coefficient + NTT_coeffs[coeff_index+48] = input_memory[index][95:72]; // 4th coefficient + end + end + end + else if (stage_idx == 2) begin + // Organize memory into 24-bit coefficients with the described offset pattern for addr_offset == 16 + for (int i = 0; i < 4; i++) begin + for (int j = 0; j < 16; j++) begin + int index = base_addr + i * 16 + j; + int coeff_index = i + j * 16; + NTT_coeffs[coeff_index] = input_memory[index][23:0]; // 1st coefficient + NTT_coeffs[coeff_index+4] = input_memory[index][47:24]; // 2nd coefficient + NTT_coeffs[coeff_index+8] = input_memory[index][71:48]; // 3rd coefficient + NTT_coeffs[coeff_index+12] = input_memory[index][95:72]; // 4th coefficient + end + end + end + end + endfunction + + + + function void ct_bf( + input logic [22:0] u, // 23-bit input + input logic [22:0] v, // 23-bit input + input logic [22:0] z, // 23-bit input + output logic [22:0] u_out, // 23-bit output + output logic [22:0] v_out // 23-bit output + ); + logic [46:0] t; // 46-bit intermediate variable to handle multiplication + logic [46:0] u_minus; // Temporary variable for intermediate results + + begin + t = (v * z) % MLDSA_Q; + + if (u >= t) begin + u_minus = u - t; + end else begin + u_minus = (u + MLDSA_Q) - t; + end + + u_out = (u + t) % MLDSA_Q; + v_out = u_minus % MLDSA_Q; // Ensure v_out is within the correct range + end + endfunction + + function void gs_bf( + input logic [22:0] u, // 23-bit input + input logic [22:0] v, // 23-bit input + input logic [22:0] z, // 23-bit input + output logic [22:0] u_out, // 23-bit output + output logic [22:0] v_out // 23-bit output + ); + logic [46:0] t; // 46-bit intermediate variable to handle multiplication + logic [46:0] t_minus; // Temporary variable for intermediate results + logic [23:0] u_temp; // Temporary variable for intermediate results + + begin + t_minus = (u >= v) ? (u - v) : (u + MLDSA_Q) - v; + t = t_minus % MLDSA_Q; // Ensure t is within the correct range + u_temp = (u + v) % MLDSA_Q; + u_out = u_temp % MLDSA_Q; + t_minus = (t * z) % MLDSA_Q; // Ensure v_out is within the correct range + v_out = t_minus % MLDSA_Q; + end + endfunction + + + // Function to perform the forward NTT + function void fwd_NTT( + input logic [REG_SIZE-1:0] poly_r[0:MLDSA_N-1], + output logic [REG_SIZE-1:0] r[0:MLDSA_N-1] + ); + int k, m, start, j; + logic [22:0] zeta; + logic [22:0] temp_u, temp_v, u_out, v_out; + + begin + // Initialize r with the 23-bit values from poly_r + for (int i = 0; i < MLDSA_N; i++) begin + r[i] = poly_r[i][22:0]; + end + + k = 0; + m = 128; + + while (m > 0) begin + start = 0; + while (start < MLDSA_N) begin + k += 1; + zeta = zetas[k]; + for (j = start; j < start + m; j++) begin + temp_u = r[j]; + temp_v = r[j + m]; + ct_bf(temp_u, temp_v, zeta, u_out, v_out); + r[j] = u_out; + r[j + m] = v_out; + end + start = start + 2 * m; + end + m = m >> 1; + end + end + endfunction + + + function void fwd_2x2_NTT( + input logic [REG_SIZE-1:0] poly_r[0:MLDSA_N-1], + output logic [REG_SIZE-1:0] r[0:3][0:MLDSA_N-1] // 3D array for storing intermediate stages + ); + int k, m, start, j, stage_idx; + logic [22:0] zeta; + logic [22:0] temp_u, temp_v, u_out, v_out; + logic [REG_SIZE-1:0] temp_r[0:MLDSA_N-1]; // Temporary array for computation + + begin + // Initialize temp_r with the 23-bit values from poly_r + for (int i = 0; i < MLDSA_N; i++) begin + temp_r[i] = poly_r[i][22:0]; + end + + k = 0; + m = 128; + stage_idx = 1; // To track the stages + + while (m > 0) begin + start = 0; + while (start < MLDSA_N) begin + k += 1; + zeta = zetas[k]; + for (j = start; j < start + m; j++) begin + temp_u = temp_r[j]; + temp_v = temp_r[j + m]; + ct_bf(temp_u, temp_v, zeta, u_out, v_out); + temp_r[j] = u_out; + temp_r[j + m] = v_out; + end + start = start + 2 * m; + end + + // Save the intermediate stages after every two stages + if (stage_idx % 2 == 0) begin + for (int i = 0; i < MLDSA_N; i++) begin + r[(stage_idx/2)-1][i] = temp_r[i]; + end + end + + m = m >> 1; + stage_idx++; + end + end + endfunction + + // Function to compare ntt_model_outputs with ntt_mem_model + function void compare_E2E_ntt_model_outputs(); + bit match = 1; + + // Compare ntt_model_outputs with organized DUT memory + for (int i = 0; i < MLDSA_N; i++) begin + if (model_NTT_output[i] != DUT_NTT_output[i]) begin + match = 0; + `uvm_error("ntt_sb", $sformatf("Mismatch at index %0d: model_NTT_output[%0d] = %h, organized_DUT_mem[%0d] = %h", i, i, model_NTT_output[i], i, DUT_NTT_output[i])); + end + end + + if (match) begin + `uvm_info("ntt_sb", "ntt_model_outputs match ntt_mem_model", UVM_LOW) + end else begin + `uvm_error("ntt_sb", "ntt_model_outputs do not match ntt_mem_model") + end + endfunction: compare_E2E_ntt_model_outputs + + + // Function to compare ntt outputs at the stage level + function void compare_ntt_stages(); + bit match = 1; + + // Compare ntt_model_outputs with organized DUT memory + for (int i = 0; i < 3; i++) begin + for (int j = 0; j < MLDSA_N; j++) begin + if (model_stage_memory[i][j] != ntt_memory_for_stages[i][j]) begin + match = 0; + `uvm_error("ntt_sb", $sformatf("Mismatch at index %0d of stage %0d: model_NTT_output[%0d] = %h, DUT_NTT_output[%0d] = %h", + j, (i+1)*2, j, model_stage_memory[i][j], j, ntt_memory_for_stages[i][j])); + end + end + end + + if (match) begin + `uvm_info("ntt_sb", "ntt_model_outputs match ntt_mem_model at the stage level", UVM_LOW) + end else begin + `uvm_error("ntt_sb", "ntt_model_outputs do not match ntt_mem_model at the stage level") + end + endfunction: compare_ntt_stages + + + + + /** + * @brief Extracts the DUT's NTT stage outputs and stores them in the corresponding stage memory. + * + * @param stage_done Indicates whether the current stage is completed. + * @param stage_idx The index of the current stage (0 to 3). + * + * Depending on the stage index, this function extracts the coefficients from the NTT memory model + * using the appropriate base address and offset. The extracted coefficients are then stored in + * the `ntt_memory_for_stages` array for comparison. + */ + function void extract_DUTs_NTT_stage_outputs(input int stage_idx); + bit [REG_SIZE-1:0] tmp_poly [0:MLDSA_N-1]; + begin + case (stage_idx) + -1: begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.src_base_addr, stage_idx, tmp_poly); + for (int i = 0; i < MLDSA_N; i++) begin + ntt_memory_for_stages[stage_idx][i] = tmp_poly[i]; + end + end + 0: begin + if (mode == mode_t'(ct)) begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.interim_base_addr, stage_idx, tmp_poly); + end + else begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.interim_base_addr, 2-stage_idx, tmp_poly); + end + for (int i = 0; i < MLDSA_N; i++) begin + ntt_memory_for_stages[stage_idx][i] = tmp_poly[i]; + end + end + 1: begin + if (mode == mode_t'(ct)) begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.dest_base_addr, stage_idx, tmp_poly); + end + else begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.dest_base_addr, 2-stage_idx, tmp_poly); + end + for (int i = 0; i < MLDSA_N; i++) begin + ntt_memory_for_stages[stage_idx][i] = tmp_poly[i]; + end + end + 2: begin + if (mode == mode_t'(ct)) begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.interim_base_addr, stage_idx, tmp_poly); + end + else begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.interim_base_addr, 2-stage_idx, tmp_poly); + end + for (int i = 0; i < MLDSA_N; i++) begin + ntt_memory_for_stages[stage_idx][i] = tmp_poly[i]; + end + end + 3: begin + if (mode == mode_t'(ct)) begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.dest_base_addr, stage_idx, tmp_poly); + end + else begin + extract_256_coeffs(ntt_mem_model, ntt_mem_addrs.dest_base_addr, 2-stage_idx, tmp_poly); + end + for (int i = 0; i < MLDSA_N; i++) begin + ntt_memory_for_stages[stage_idx][i] = tmp_poly[i]; + end + end + default: begin + `uvm_error("ntt_sb", "Invalid stage_idx. Mldsa has only 4 stages to compare (1-4).") + end + endcase + end + endfunction: extract_DUTs_NTT_stage_outputs + + + function void inv_NTT( + input logic [REG_SIZE-1:0] poly_r[0:MLDSA_N-1], + output logic [REG_SIZE-1:0] r[0:MLDSA_N-1] + ); + int k, m, start, j; + logic [22:0] zeta; + logic [22:0] temp_u, temp_v, u_out, v_out; + logic [46:0] temp_last; + + begin + // Initialize r with the 23-bit values from poly_r + for (int i = 0; i < MLDSA_N; i++) begin + r[i] = poly_r[i][22:0]; + end + + k = MLDSA_N; + m = 1; + + while (m < MLDSA_N) begin + start = 0; + while (start < MLDSA_N) begin + k -= 1; + zeta = zetas_inv[k]; + for (j = start; j < start + m; j++) begin + temp_u = r[j]; + temp_v = r[j + m]; + gs_bf(temp_u, temp_v, zeta, u_out, v_out); + r[j] = u_out; + r[j + m] = v_out; + end + start = start + 2 * m; + end + m = m << 1; + end + for (int i = 0; i < MLDSA_N; i++) begin + temp_last = (f * r[i]) % MLDSA_Q; + r[i] = temp_last % MLDSA_Q; + end + end + endfunction + + function void inv_2x2_NTT( + input logic [REG_SIZE-1:0] poly_r[0:MLDSA_N-1], + output logic [REG_SIZE-1:0] r[0:3][0:MLDSA_N-1] // 3D array for storing intermediate stages + ); + int k, m, start, j, stage_idx; + logic [22:0] zeta; + logic [22:0] temp_u, temp_v, u_out, v_out; + logic [REG_SIZE-1:0] temp_r[0:MLDSA_N-1]; // Temporary array for computation + + begin + // Initialize temp_r with the 23-bit values from poly_r + for (int i = 0; i < MLDSA_N; i++) begin + temp_r[i] = poly_r[i][22:0]; + end + + k = MLDSA_N; + m = 1; + stage_idx = 1; // To track the stages + + while (m < MLDSA_N) begin + start = 0; + while (start < MLDSA_N) begin + k -= 1; + zeta = zetas_inv[k]; + for (j = start; j < start + m; j++) begin + temp_u = temp_r[j]; + temp_v = temp_r[j + m]; + gs_bf(temp_u, temp_v, zeta, u_out, v_out); + temp_r[j] = u_out; + temp_r[j + m] = v_out; + end + start = start + 2 * m; + end + + // Save the intermediate stages after every two stages + if (stage_idx % 2 == 0) begin + for (int i = 0; i < MLDSA_N; i++) begin + r[(stage_idx/2)-1][i] = temp_r[i]; + end + end + + m = m << 1; + stage_idx++; + end + end + endfunction + + + function void gs_bf_div2( + input logic [22:0] u, // 23-bit input + input logic [22:0] v, // 23-bit input + input logic [22:0] z, // 23-bit input + output logic [22:0] u_out, // 23-bit output + output logic [22:0] v_out // 23-bit output + ); + logic [46:0] t; // 46-bit intermediate variable to handle division and addition + logic [46:0] t_minus; // Temporary variable for intermediate results + logic [46:0] u_temp; // Temporary variable for intermediate results + + begin + // Calculate t and perform division by 2 + t_minus = (u >= v) ? (u - v) : (u + MLDSA_Q) - v; + + if (t_minus & 1) begin + t = (t_minus >> 1) + ((MLDSA_Q + 1) >> 1); + end else begin + t = t_minus >> 1; + end + t = t % MLDSA_Q; + + // Calculate u and perform division by 2 + u_temp = (u + v) % MLDSA_Q; + if (u_temp & 1) begin + u_temp = (u_temp >> 1) + ((MLDSA_Q + 1) >> 1); + end else begin + u_temp = u_temp >> 1; + end + u_out = u_temp % MLDSA_Q; + + // Calculate v_out + t_minus = (t * z) % MLDSA_Q; + v_out = t_minus % MLDSA_Q; + end + endfunction + + + function void inv_2x2_NTT_div2( + input logic [REG_SIZE-1:0] poly_r[0:MLDSA_N-1], + output logic [REG_SIZE-1:0] r[0:3][0:MLDSA_N-1] // 3D array for storing intermediate stages + ); + int k1[0:1], k2, m, start, j, stage_idx; + logic [22:0] zeta1[0:1], zeta2; + logic [22:0] u00, v00, u01, v01; + logic [22:0] u10, u11, v10, v11; + logic [22:0] u20, u21, v20, v21; + logic [REG_SIZE-1:0] temp_r[0:MLDSA_N-1]; // Temporary array for computation + + begin + // Initialize temp_r with the 23-bit values from poly_r + for (int i = 0; i < MLDSA_N; i++) begin + temp_r[i] = poly_r[i][22:0]; + end + + m = 1; + stage_idx = 0; // To track the stages + + for (int l = 0; l < 8; l += 2) begin + m = 1 << l; + for (int i = 0; i < MLDSA_N; i += (1 << (l + 2))) begin + k1[0] = ((MLDSA_N - (i >> 1)) >> l) - 1; + k1[1] = k1[0] - 1; + k2 = ((MLDSA_N - (i >> 1)) >> (l + 1)) - 1; + zeta1[0] = zetas_inv[k1[0]]; + zeta1[1] = zetas_inv[k1[1]]; + zeta2 = zetas_inv[k2]; + + for (j = i; j < i + m; j++) begin + u00 = temp_r[j]; + v00 = temp_r[j + m]; + u01 = temp_r[j + 2 * m]; + v01 = temp_r[j + 3 * m]; + + gs_bf_div2(u00, v00, zeta1[0], u10, u11); + gs_bf_div2(u01, v01, zeta1[1], v10, v11); + + gs_bf_div2(u10, v10, zeta2, u20, u21); + gs_bf_div2(u11, v11, zeta2, v20, v21); + + temp_r[j] = u20; + temp_r[j + m] = v20; + temp_r[j + 2 * m] = u21; + temp_r[j + 3 * m] = v21; + end + end + + // Save the intermediate stages after every two stages + for (int i = 0; i < MLDSA_N; i++) begin + r[stage_idx][i] = temp_r[i]; + end + + stage_idx++; + end + end + endfunction + + +endclass: ntt_sb \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/mem_seq_lib.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/mem_seq_lib.sv new file mode 100644 index 0000000000000000000000000000000000000000..5702b0c4992b8dab36d3981c7fc14002deb0bf9b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/mem_seq_lib.sv @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class mem_base_seq extends uvm_sequence#(mem_txn); + + `uvm_object_utils(mem_base_seq) + + function new (string name = ""); + super.new(name); + endfunction: new + +endclass + +class mem_init_seq extends mem_base_seq; + + `uvm_object_utils(mem_init_seq) + mem_txn mem_txn_i; + + function new(string name = ""); + super.new(name); + endfunction: new + + task body(); + mem_txn_i = mem_txn::type_id::create(.name("mem_txn_i")); + start_item(mem_txn_i); + assert(mem_txn_i.randomize() with { + update_mem == 1; + }); + finish_item(mem_txn_i); + endtask: body + +endclass \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_base_seq.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_base_seq.sv new file mode 100644 index 0000000000000000000000000000000000000000..4aa6b654d2e8d8c93e3c9022bd792688234c3222 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_base_seq.sv @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_base_seq extends uvm_sequence#(ntt_txn); + + `uvm_object_utils(ntt_base_seq) + + function new (string name = ""); + super.new(name); + endfunction: new + +endclass \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_fwd_seq.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_fwd_seq.sv new file mode 100644 index 0000000000000000000000000000000000000000..bdb3552161c77c19927d13d76a270930600669fb --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_fwd_seq.sv @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_fwd_seq extends ntt_base_seq; + + `uvm_object_utils(ntt_fwd_seq) + ntt_txn ntt_txn_i; + + function new(string name = ""); + super.new(name); + endfunction: new + + task body(); + ntt_txn_i = ntt_txn::type_id::create(.name("ntt_txn_i")); + start_item(ntt_txn_i); + assert(ntt_txn_i.randomize() with { + ntt_enable == 1; + mode == mode_t'(ct); // Set mode to 'ct' + zeroize == 0; // Set zeroize to 0 + accumulate == 0; + sampler_valid == 0; + sampler_mode == 0; + sampler_data == 0; + }) else begin + `uvm_error("RANDOMIZE_FAIL", "Randomization failed for ntt_txn_i") + end + finish_item(ntt_txn_i); + endtask: body + +endclass \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_inv_seq.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_inv_seq.sv new file mode 100644 index 0000000000000000000000000000000000000000..c84f81097df64141c40bc80ad727acdef249221c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq/ntt_inv_seq.sv @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_inv_seq extends ntt_base_seq; + + `uvm_object_utils(ntt_inv_seq) + ntt_txn ntt_txn_i; + ntt_mem_addr_t ntt_mem_base_addr; // Shared variable for base address + bit use_shared_addr; // Flag to control address assignment + + function new(string name = ""); + super.new(name); + endfunction: new + + task body(); + ntt_txn_i = ntt_txn::type_id::create(.name("ntt_txn_i")); + start_item(ntt_txn_i); + if (use_shared_addr != null) begin + assert(ntt_txn_i.randomize() with { + ntt_enable == 1; + mode == mode_t'(gs); // Set mode to 'gs' + zeroize == 0; // Set zeroize to 0 + accumulate == 0; + sampler_valid == 0; + sampler_mode == 0; + sampler_data == 0; + ntt_mem_base_addr == this.ntt_mem_base_addr; // Use the shared variable + }) else begin + `uvm_error("RANDOMIZE_FAIL", "Randomization failed for ntt_txn_i") + end + end else begin + assert(ntt_txn_i.randomize() with { + ntt_enable == 1; + mode == mode_t'(gs); // Set mode to 'gs' + zeroize == 0; // Set zeroize to 0 + accumulate == 0; + sampler_valid == 0; + sampler_mode == 0; + sampler_data == 0; + }) else begin + `uvm_error("RANDOMIZE_FAIL", "Randomization failed for ntt_txn_i") + end + end + finish_item(ntt_txn_i); + endtask: body + +endclass diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq_lib.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq_lib.sv new file mode 100644 index 0000000000000000000000000000000000000000..9064e19dc7b2ea4dde4b4556e4e8c1c75b980baf --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_seq_lib.sv @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// `include "$COMPILE_ROOT/utb/sequences/ntt_seq/ntt_base_seq.sv" +// `include "$COMPILE_ROOT/utb/sequences/ntt_seq/ntt_fwd_seq.sv" diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_virtual_seq.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_virtual_seq.sv new file mode 100644 index 0000000000000000000000000000000000000000..d8f47e796d13f587dda7231422fe75bd958d688a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/sequences/ntt_virtual_seq.sv @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_virtual_seq extends uvm_sequence#(uvm_sequence_item); + + `uvm_object_utils(ntt_virtual_seq) + + // Declare handles for the sequencers + mem_sequencer mem_seqr; + ntt_sequencer ntt_seqr; + mem_base_seq mem_seq_i; + ntt_base_seq ntt_seq_i; + + function new(string name = ""); + super.new(name); + endfunction: new + + task body(); + fork + begin + mem_seq_i.start(mem_seqr); + end + begin + #10ns; + ntt_seq_i.start(ntt_seqr); + end + join + + // Optionally, you can add more sequences or additional coordination logic here + endtask: body + +endclass + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/test.yml new file mode 100644 index 0000000000000000000000000000000000000000..49601e58c17c311fae1335b6870e15b22d48f47c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/test.yml @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +tests: + - name: ntt_combined_test + seed: 1 + - name: ntt_base_test + seed: 1 \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/tests/ntt_base_test.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/tests/ntt_base_test.sv new file mode 100644 index 0000000000000000000000000000000000000000..a5cda91112ef5d093848d8df99373b0dae04c870 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/tests/ntt_base_test.sv @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_base_test extends uvm_test; + + `uvm_component_utils(ntt_base_test) + + ntt_env ntt_env_i; + mem_init_seq mem_init_seq_i; + ntt_fwd_seq ntt_fwd_seq_i; + ntt_inv_seq ntt_inv_seq_i; + ntt_virtual_seq ntt_virtual_seq_i; + + virtual ntt_if ntt_vif; + virtual mem_if ntt_mem_vif; + virtual mem_if pwm_a_mem_vif; + virtual mem_if pwm_b_mem_vif; + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + ntt_env_i = ntt_env::type_id::create(.name("ntt_env_i"), .parent(this)); + + // Get the virtual interfaces from the UVM configuration database + if (!uvm_config_db#(virtual ntt_if)::get(this, "", "ntt_vif", ntt_vif)) begin + `uvm_fatal("NOVIF", "NTT virtual interface is not gotten by the test"); + end + if (!uvm_config_db#(virtual mem_if)::get(this, "", "ntt_mem_vif", ntt_mem_vif)) begin + `uvm_fatal("NOVIF", "NTT Memory virtual interface is not gotten by the test"); + end + if (!uvm_config_db#(virtual mem_if)::get(this, "", "pwm_a_mem_vif", pwm_a_mem_vif)) begin + `uvm_fatal("NOVIF", "PWM A Memory virtual interface is not gotten by the test"); + end + if (!uvm_config_db#(virtual mem_if)::get(this, "", "pwm_b_mem_vif", pwm_b_mem_vif)) begin + `uvm_fatal("NOVIF", "PWM B Memory virtual interface is not gotten by the test"); + end + + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + ntt_env_i.ntt_agent_i.ntt_driver_i.ntt_vif = ntt_vif; + ntt_env_i.ntt_agent_i.ntt_input_mon_i.ntt_vif = ntt_vif; + + ntt_env_i.ntt_mem_i.mem_driver_i.mem_vif = ntt_mem_vif; + ntt_env_i.ntt_mem_i.mem_mon_i.mem_vif = ntt_mem_vif; + + ntt_env_i.pwm_a_mem_i.mem_driver_i.mem_vif = pwm_a_mem_vif; + ntt_env_i.pwm_a_mem_i.mem_mon_i.mem_vif = pwm_a_mem_vif; + + ntt_env_i.pwm_b_mem_i.mem_driver_i.mem_vif = pwm_b_mem_vif; + ntt_env_i.pwm_b_mem_i.mem_mon_i.mem_vif = pwm_b_mem_vif; + endfunction: connect_phase + + task run_phase(uvm_phase phase); + + mem_init_seq_i = mem_init_seq::type_id::create(.name("mem_init_seq_i")); + ntt_inv_seq_i = ntt_inv_seq::type_id::create(.name("ntt_inv_seq_i")); + ntt_virtual_seq_i = ntt_virtual_seq::type_id::create(.name("ntt_virtual_seq_i")); + + phase.raise_objection(this); + + //-- Wait for DUT reset completion. + #150ns; + + + + // Set the sequencers + ntt_virtual_seq_i.mem_seqr = ntt_env_i.ntt_mem_i.mem_sqcr_i; + ntt_virtual_seq_i.ntt_seqr = ntt_env_i.ntt_agent_i.ntt_sqcr_i; + + // Set the sequences + ntt_virtual_seq_i.mem_seq_i = mem_init_seq_i; + //ntt_virtual_seq_i.ntt_seq_i = ntt_fwd_seq_i; + ntt_virtual_seq_i.ntt_seq_i = ntt_inv_seq_i; + + // Start the virtual sequence + ntt_virtual_seq_i.start(null); + + //-- wait for end + #1400ns ; + + phase.drop_objection(this); + + endtask + + +endclass: ntt_base_test \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/tests/ntt_combined_test.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/tests/ntt_combined_test.sv new file mode 100644 index 0000000000000000000000000000000000000000..45e0e29fd3a834ce9b50e38cdd4bed7651e081c7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/ntt_top/utb/tests/ntt_combined_test.sv @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +class ntt_combined_test extends uvm_test; + + `uvm_component_utils(ntt_combined_test) + + ntt_env ntt_env_i; + mem_init_seq mem_init_seq_i; + ntt_fwd_seq ntt_fwd_seq_i; + ntt_inv_seq ntt_inv_seq_i; + + virtual ntt_if ntt_vif; + virtual mem_if ntt_mem_vif; + virtual mem_if pwm_a_mem_vif; + virtual mem_if pwm_b_mem_vif; + + + // Shared variable to store ntt_mem_base_addr + ntt_mem_addr_t shared_ntt_mem_base_addr; + + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + function void build_phase(uvm_phase phase); + super.build_phase(phase); + ntt_env_i = ntt_env::type_id::create(.name("ntt_env_i"), .parent(this)); + + // Get the virtual interfaces from the UVM configuration database + if (!uvm_config_db#(virtual ntt_if)::get(this, "", "ntt_vif", ntt_vif)) begin + `uvm_fatal("NOVIF", "NTT virtual interface is not gotten by the test"); + end + if (!uvm_config_db#(virtual mem_if)::get(this, "", "ntt_mem_vif", ntt_mem_vif)) begin + `uvm_fatal("NOVIF", "NTT Memory virtual interface is not gotten by the test"); + end + if (!uvm_config_db#(virtual mem_if)::get(this, "", "pwm_a_mem_vif", pwm_a_mem_vif)) begin + `uvm_fatal("NOVIF", "PWM A Memory virtual interface is not gotten by the test"); + end + if (!uvm_config_db#(virtual mem_if)::get(this, "", "pwm_b_mem_vif", pwm_b_mem_vif)) begin + `uvm_fatal("NOVIF", "PWM B Memory virtual interface is not gotten by the test"); + end + + + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + + ntt_env_i.ntt_agent_i.ntt_driver_i.ntt_vif = ntt_vif; + ntt_env_i.ntt_agent_i.ntt_input_mon_i.ntt_vif = ntt_vif; + + ntt_env_i.ntt_mem_i.mem_driver_i.mem_vif = ntt_mem_vif; + ntt_env_i.ntt_mem_i.mem_mon_i.mem_vif = ntt_mem_vif; + + ntt_env_i.pwm_a_mem_i.mem_driver_i.mem_vif = pwm_a_mem_vif; + ntt_env_i.pwm_a_mem_i.mem_mon_i.mem_vif = pwm_a_mem_vif; + + ntt_env_i.pwm_b_mem_i.mem_driver_i.mem_vif = pwm_b_mem_vif; + ntt_env_i.pwm_b_mem_i.mem_mon_i.mem_vif = pwm_b_mem_vif; + endfunction: connect_phase + + task run_phase(uvm_phase phase); + `uvm_info("NTT_COMBINED_TEST", "Running ntt_combined_test", UVM_LOW) + mem_init_seq_i = mem_init_seq::type_id::create(.name("mem_init_seq_i")); + ntt_fwd_seq_i = ntt_fwd_seq::type_id::create(.name("ntt_fwd_seq_i")); + ntt_inv_seq_i = ntt_inv_seq::type_id::create(.name("ntt_inv_seq_i")); + + phase.raise_objection(this); + + //-- Wait for DUT reset completion. + #150ns; + + // Start the memory initialization sequence + mem_init_seq_i.start(ntt_env_i.ntt_mem_i.mem_sqcr_i); + + // Start the forward NTT sequence + ntt_fwd_seq_i.start(ntt_env_i.ntt_agent_i.ntt_sqcr_i); + shared_ntt_mem_base_addr = ntt_fwd_seq_i.ntt_txn_i.ntt_mem_base_addr; // Store the ntt_mem_base_addr + + @ (posedge ntt_vif.ntt_done); // Wait for done signal from the DUT + #100ns; + ntt_inv_seq_i.ntt_mem_base_addr = shared_ntt_mem_base_addr; // Pass the shared ntt_mem_base_addr to the inverse sequence + ntt_inv_seq_i.ntt_mem_base_addr.src_base_addr = shared_ntt_mem_base_addr.dest_base_addr; + ntt_inv_seq_i.use_shared_addr = 1; // Set the flag to control address assignment + ntt_inv_seq_i.start(ntt_env_i.ntt_agent_i.ntt_sqcr_i); // Start the inverse sequence + + //-- wait for end + #1400ns; + + phase.drop_objection(this); + endtask + +endclass: ntt_combined_test diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..ab5b402ddaf075004b4ce2839a7c6ecca41425ad --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/compile.yml @@ -0,0 +1,35 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [pkdecode] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/pkdecode.sv + + tops: [pkdecode] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/pk_decode/config/design_lint/pkdecode/sglint_waivers +--- +provides: [pkdecode_tb] +schema_version: 2.4.0 +requires: + - pkdecode +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/pkdecode_tb.sv + tops: [pkdecode_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying python model to $PWD" && cp $COMPILE_ROOT/tb/unpack_pk.py .' \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/design_lint/pkdecode/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/design_lint/pkdecode/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/pkdecode.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/pkdecode.vf new file mode 100644 index 0000000000000000000000000000000000000000..9fd8c7b3901c61d9a3ef044d569c19d71764a864 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/pkdecode.vf @@ -0,0 +1,34 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl/pkdecode.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/pkdecode_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/pkdecode_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..8331a2d9b5533d4f3d7a3462b43fcdc72fcb1489 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/config/pkdecode_tb.vf @@ -0,0 +1,36 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/pk_decode/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/pk_decode/rtl/pkdecode.sv +${ADAMSBRIDGE_ROOT}/src/pk_decode/tb/pkdecode_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/rtl/pkdecode.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/rtl/pkdecode.sv new file mode 100644 index 0000000000000000000000000000000000000000..fb543d070145f6f0e4c1f7d14485326ccb4b1b16 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/rtl/pkdecode.sv @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// pkdecode.sv +// -------- +// The pkdecode module decodes the t1 polynomials according to the ML-DSA-87 protocol. +// Each set of 10 bits represents a single coefficient, which is then shifted left by +// 13 bits to produce a 24-bit output with the MSB set to zero. This module supports +// parallel processing of coefficients and interfaces with memory for storing the results. +// One cycle read and write latency +//====================================================================== + +module pkdecode + import mldsa_params_pkg::*; + #( + parameter MLDSA_K = 'h8, + parameter MLDSA_N = 'd256, + parameter REG_SIZE = 24, + parameter INPUT_COEFF_SIZE = 10, + parameter API_ADDR_WIDTH = 16 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire pkdecode_enable, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire [API_ADDR_WIDTH-1:0] src_base_addr, + input wire [8*INPUT_COEFF_SIZE-1:0] API_rd_data, + + output logic [API_ADDR_WIDTH-1:0] API_rd_address, + output logic [3:0][REG_SIZE-1:0] mem_a_wr_data, + output logic [3:0][REG_SIZE-1:0] mem_b_wr_data, + output mem_if_t mem_a_wr_req, + output mem_if_t mem_b_wr_req, + + output logic pkdecode_done + ); + + localparam COEFF_WIDTH = 10; + localparam SHIFT_LEFT = 13; + localparam NUM_COEFFS_PER_CYCLE = 8; + localparam THE_LAST_ADDR = (MLDSA_K * MLDSA_N)/8; + // State Machine States + localparam IDLE = 3'b000, + READ = 3'b001, + READ_and_EXEC = 3'b010, + READ_and_WRITE = 3'b011, + WRITE = 3'b100, + DONE = 3'b101; + + // Internal signals + logic [7:0][REG_SIZE-1:0] coefficients; // Extracted 10-bit coefficients + logic [7:0][REG_SIZE-1:0] encoded_coeffs; // Encoded 24-bit coefficients + logic [MLDSA_MEM_ADDR_WIDTH-1:0] locked_dest_addr; + logic [API_ADDR_WIDTH-1:0] locked_src_addr; // this ensures that addresses are captured when the block is enabled + logic [31:0] num_mem_operands, num_api_operands; // encoded each four coeff will increment these by one + logic [2:0] state, next_state; + + + // State Machine + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + state <= IDLE; + end + else if (zeroize) begin + state <= IDLE; + end + else begin + state <= next_state; + end + end + + always_comb begin + case (state) + IDLE: begin + if (pkdecode_enable) + next_state = READ; + else + next_state = IDLE; + end + READ: begin + next_state = READ_and_EXEC; + end + READ_and_EXEC: begin + next_state = READ_and_WRITE; + end + READ_and_WRITE: begin + if (num_api_operands == THE_LAST_ADDR) begin + next_state = WRITE; + end + else begin + next_state = READ_and_WRITE; + end + end + WRITE: begin + next_state = DONE; + end + DONE: begin + next_state = IDLE; + end + default: begin + next_state = IDLE; + end + endcase + end + + + // Extract 10-bit coefficients from API_rd_data + always_comb begin + for (int i = 0; i < NUM_COEFFS_PER_CYCLE; i++) begin + coefficients[i] = {24'h0, API_rd_data[COEFF_WIDTH*i +: COEFF_WIDTH]}; + end + end + + // Encode coefficients into 24-bit format + always_comb begin + for (int i = 0; i < NUM_COEFFS_PER_CYCLE; i++) begin + encoded_coeffs[i] = (coefficients[i] << SHIFT_LEFT); + end + end + + // Assign encoded data to memory write ports + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_a_wr_data <= '{default: 0}; + mem_b_wr_data <= '{default: 0}; + end + else if (zeroize) begin + mem_a_wr_data <= '{default: 0}; + mem_b_wr_data <= '{default: 0}; + end + else begin + mem_a_wr_data <= '{encoded_coeffs[3], encoded_coeffs[2], encoded_coeffs[1], encoded_coeffs[0]}; + mem_b_wr_data <= '{encoded_coeffs[7], encoded_coeffs[6], encoded_coeffs[5], encoded_coeffs[4]}; + end + end + + // Write request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (zeroize) begin + mem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (state == READ_and_WRITE || state == WRITE) begin + mem_a_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_mem_operands}; + mem_b_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_mem_operands + 1}; + end + else begin + mem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + end + + // Memory read request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + API_rd_address <= '0; + end + else if (zeroize) begin + API_rd_address <= '0; + end + else if (state == READ || state == READ_and_EXEC || state == READ_and_WRITE) begin + API_rd_address <= API_ADDR_WIDTH'(locked_src_addr + num_api_operands); + end else begin + API_rd_address <= '0; + end + end + + + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + num_mem_operands <= 'h0; + num_api_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + pkdecode_done <= 'h0; + end + else if (zeroize) begin + num_mem_operands <= 'h0; + num_api_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + pkdecode_done <= 'h0; + end + else begin + if (pkdecode_enable) begin + locked_dest_addr <= dest_base_addr; + locked_src_addr <= src_base_addr; + end + if (state == READ || state == READ_and_EXEC || state == READ_and_WRITE) begin + num_api_operands <= num_api_operands +1'h1; + end + else begin + num_api_operands <= 'h0; + end + if (state == READ_and_WRITE || state == WRITE) begin + num_mem_operands <= num_mem_operands +2'h2; + end + else begin + num_mem_operands <= 'h0; + end + + if (state == DONE) begin + pkdecode_done <= 'h1; + end + else begin + pkdecode_done <= 'h0; + end + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/stimulus/tests/directed/pkdecode_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/stimulus/tests/directed/pkdecode_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..a57d9a5e0c9a5dd0818d70c8a011798c20bc9717 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/stimulus/tests/directed/pkdecode_normal_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: pkdecode_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/tb/pkdecode_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/tb/pkdecode_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..9a3b8fbc56eb6ce336adb569c927d712f6429d8c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/tb/pkdecode_tb.sv @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// pkdecode_tb.sv +// --------------- +// Testbench for pkdecode module +//====================================================================== + +`default_nettype none + +module pkdecode_tb + import mldsa_params_pkg::*; +#( + parameter REG_SIZE = 24, + parameter MLDSA_K = 'h8, + parameter MEM_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH, + parameter API_ADDR_WIDTH = 10 +) +(); +localparam NUM_OF_COEFF = 256 * MLDSA_K; +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg zeroize_tb; +reg pkdecode_enable_tb; +reg [MEM_ADDR_WIDTH-1:0] dest_base_addr_tb; +reg [API_ADDR_WIDTH-1:0] src_base_addr_tb; +wire [3:0][REG_SIZE-1:0] mem_a_wr_data_tb; +wire [3:0][REG_SIZE-1:0] mem_b_wr_data_tb; +wire pkdecode_done_tb; +mem_if_t mem_a_wr_req_tb; +mem_if_t mem_b_wr_req_tb; +reg [79:0] API_rd_data_tb; +reg [API_ADDR_WIDTH-1:0] API_rd_address_tb; + +reg [9:0] input_mem [0:NUM_OF_COEFF-1]; +reg [23:0] expected_output_mem [0:NUM_OF_COEFF-1]; +reg [23:0] actual_output_mem [0:NUM_OF_COEFF-1]; + + +// Instantiate the Device Under Test (DUT) +pkdecode #( + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), + .MLDSA_K(MLDSA_K), + .MLDSA_N(256), + .REG_SIZE(REG_SIZE), + .API_ADDR_WIDTH(API_ADDR_WIDTH) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + + .pkdecode_enable(pkdecode_enable_tb), + .dest_base_addr(dest_base_addr_tb), + .src_base_addr(src_base_addr_tb), + .API_rd_data(API_rd_data_tb), + + .API_rd_address(API_rd_address_tb), + .mem_a_wr_req(mem_a_wr_req_tb), + .mem_b_wr_req(mem_b_wr_req_tb), + .mem_a_wr_data(mem_a_wr_data_tb), + .mem_b_wr_data(mem_b_wr_data_tb), + + .pkdecode_done(pkdecode_done_tb) +); + +wire [REG_SIZE-1:0] dummy_mem_out0, dummy_mem_out1; + +genvar k; +generate + for (k = 0; k < 4; k = k + 1) begin : mem_blocks + sig_dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(REG_SIZE), + .DEPTH(NUM_OF_COEFF+400) + ) + output_memory ( + .clk(clk_tb), + .addr_a(mem_a_wr_req_tb.addr), + .data_in_a(mem_a_wr_data_tb[k]), + .we_a((mem_a_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_a(dummy_mem_out0), + .addr_b(mem_b_wr_req_tb.addr), + .data_in_b(mem_b_wr_data_tb[k]), + .we_b((mem_b_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_b(dummy_mem_out1) + ); + end +endgenerate + +wire [79:0] dummy_mem_out2; + +sig_dual_port_memory #( + .ADDR_WIDTH(API_ADDR_WIDTH), + .DATA_WIDTH(80), + .DEPTH(NUM_OF_COEFF+400) + ) + input_memory ( + .clk(clk_tb), + .addr_a(API_rd_address_tb), + .data_in_a(80'h0), + .we_a(1'b0), + .data_out_a(API_rd_data_tb), + .addr_b(10'b0), + .data_in_b(80'h0), + .we_b(1'b0), + .data_out_b(dummy_mem_out2) + ); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + zeroize_tb = 0; + pkdecode_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + #(3 * CLK_PERIOD); + reset_n_tb = 1; + $display("End of reset"); + end +endtask // reset_dut + +task overwrite_memory_content(reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i; + + // Overwrite input memory with the values from input_mem in big-endian format + for (i = 0; i < (NUM_OF_COEFF / 8); i = i + 1) begin + input_memory.mem[i + src_base_addr] = {input_mem[8*i + 7], input_mem[8*i + 6], + input_mem[8*i + 5], input_mem[8*i + 4], + input_mem[8*i + 3], input_mem[8*i + 2], + input_mem[8*i + 1], input_mem[8*i + 0]}; + end +endtask + +task read_memory_content(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr); + int i, j; + // Read output memory into the actual_output_mem array + for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin + actual_output_mem[4*i + 0] = mem_blocks[0].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 1] = mem_blocks[1].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 2] = mem_blocks[2].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 3] = mem_blocks[3].output_memory.mem[i+dest_base_addr]; + end +endtask + +task read_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + string input_file = "input_pk.hex"; + string output_file = "output_decoded_pk.hex"; + integer file, ret; + int i; + string line; + + // Read input file + file = $fopen(input_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", input_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", input_mem[i]); + i = i + 1; + end + end + $fclose(file); + overwrite_memory_content(src_base_addr); + + // Read expected output file + file = $fopen(output_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", output_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", expected_output_mem[i]); + i = i + 1; + end + end + $fclose(file); +endtask + +task pkdecode_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [API_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + $display("Starting pkdecode test\n"); + read_test_vectors(src_base_addr); + @(posedge clk_tb); + pkdecode_enable_tb = 1; + src_base_addr_tb = src_base_addr; + dest_base_addr_tb = dest_base_addr; + @(posedge clk_tb); + pkdecode_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + + $display("Waiting for pkdecode to complete\n"); + wait (pkdecode_done_tb); + read_memory_content(dest_base_addr); + + $display("Checking output data\n"); + for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin + if (actual_output_mem[i] !== expected_output_mem[i]) begin + $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]); + end + end + $display("Test completed\n"); +endtask + +initial begin + $system($sformatf("python3 unpack_pk.py")); + init_sim(); + reset_dut(); + $display("Reading test vectors from hex files\n"); + pkdecode_test('h0, 'h0); + pkdecode_test('h40, 'h20); + $finish; +end + +endmodule + + +module sig_dual_port_memory + #( + parameter ADDR_WIDTH = 15, + parameter DATA_WIDTH = 32, + parameter DEPTH = 256 + ) + ( + input wire clk, + + // Port A + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] data_in_a, + input wire we_a, // Write enable for port A + output reg [DATA_WIDTH-1:0] data_out_a, + + // Port B + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] data_in_b, + input wire we_b, // Write enable for port B + output reg [DATA_WIDTH-1:0] data_out_b + ); + + // Memory array + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + // Port A logic + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= data_in_a; + end + data_out_a <= mem[addr_a]; + end + + // Port B logic + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= data_in_b; + end + data_out_b <= mem[addr_b]; + end + + endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/tb/unpack_pk.py b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/tb/unpack_pk.py new file mode 100644 index 0000000000000000000000000000000000000000..d20a300f9627d7050f351587263e1239024e261b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/pk_decode/tb/unpack_pk.py @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import random + +# Constants +COEFF_BIT_WIDTH = 10 +SHIFT_LEFT_BITS = 13 +NUM_COEFFS = 256 # Adjust based on the number of coefficients needed +K= 8 +SEED = 12345 # Fixed seed for reproducibility + +def generate_random_coefficients(num_coeffs): + """Generate a list of random 10-bit coefficients.""" + random.seed(SEED) # Set the seed for reproducibility + coefficients = [] + for _ in range(num_coeffs): + coef = random.randint(0, (1 << COEFF_BIT_WIDTH) - 1) + coefficients.append(coef) + return coefficients + +def process_coefficients(coefficients): + """Shift the coefficients left and mask to 24 bits.""" + processed = [] + for coef in coefficients: + # Shift left by 13 bits and mask to ensure 24-bit result with MSB zero + processed_value = (coef << SHIFT_LEFT_BITS) & 0xFFFFFF + processed.append(processed_value) + return processed + +def write_to_hex_file(data, filename, width): + """Write the data to a hex file with specified width.""" + with open(filename, 'w') as f: + for value in data: + f.write(f"{value:0{width}X}\n") # width controls hex digits + +# Generate random coefficients +coefficients = generate_random_coefficients(NUM_COEFFS*K) + +# Process coefficients for expected output +processed_coefficients = process_coefficients(coefficients) + +# Write the coefficients and processed outputs to the respective files +write_to_hex_file(coefficients, 'input_pk.hex', 3) # 10-bit coefficients +write_to_hex_file(processed_coefficients, 'output_decoded_pk.hex', 6) # 24-bit processed values diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..da908d0b449be5da38ebeb0c4fea91e15ce6765c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/compile.yml @@ -0,0 +1,51 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [power2round_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/power2round_defines_pkg.sv +--- +provides: [power2round] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - power2round_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/power2round_top.sv + - $COMPILE_ROOT/rtl/power2round_ctrl.sv + - $COMPILE_ROOT/rtl/power2round_core.sv + - $COMPILE_ROOT/rtl/power2round_skencode.sv + + tops: [power2round_top] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/power2round/config/design_lint/power2round/sglint_waivers +--- +provides: [power2round_tb] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - power2round + - power2round_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/power2round_tb.sv + tops: [power2round_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ref model to ${pwd}" && cp $COMPILE_ROOT/tb/power2round.py .' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/design_lint/power2round/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/design_lint/power2round/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round.vf new file mode 100644 index 0000000000000000000000000000000000000000..9d82c23e5948d4e270eb265acc3df149547e92b7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round.vf @@ -0,0 +1,38 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_top.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_core.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_skencode.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..2f678843d48b0d955695259d85f75dfc2d9dcc56 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/rtl +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..a5f21dff03450db5bff32679df9f1eea91209dff --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/config/power2round_tb.vf @@ -0,0 +1,40 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/power2round/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_top.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_core.sv +${ADAMSBRIDGE_ROOT}/src/power2round/rtl/power2round_skencode.sv +${ADAMSBRIDGE_ROOT}/src/power2round/tb/power2round_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_core.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_core.sv new file mode 100644 index 0000000000000000000000000000000000000000..311301eb78d9b0a55b4422e43f7a78f15a9df6b5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_core.sv @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// power2round_core.sv +// -------- +// Breaks down input coefficient +//====================================================================== + +module power2round_core + #( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_D = 13 + ) + ( + input wire [REG_SIZE-1:0] r, + output logic [MLDSA_D-1:0] r0, + output logic [REG_SIZE-MLDSA_D-1:0] r1 + ); + + localparam power2_d_minus_one = (1 << (MLDSA_D-1)) - 1; + + logic [REG_SIZE : 0] sum0; + logic [REG_SIZE : 0] sum1; + logic [REG_SIZE-MLDSA_D-1:0] r1_temp; + logic [MLDSA_D-1 : 0] r0_temp; + + always_comb begin + sum0 = r + power2_d_minus_one; + r1_temp = sum0[REG_SIZE-1:MLDSA_D]; + sum1 = r - (r1_temp << MLDSA_D); + r0_temp = sum1[MLDSA_D-1 : 0]; + end + + assign r0 = r0_temp; + assign r1 = r1_temp; +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..16b15f461b325c71f0fbfc9519fa1bb30aa022ec --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_ctrl.sv @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// power2round_ctrl.sv +// --------------------- + +module power2round_ctrl + import mldsa_params_pkg::*; + import power2round_defines_pkg::*; + #( + parameter MLDSA_K = 8, + parameter MLDSA_N = 256 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire enable, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] skmem_dest_base_addr, + // input wire [MLDSA_MEM_ADDR_WIDTH-1:0] pk_dest_base_addr, + input wire r_valid, + input wire sk_buff_valid, + input wire sk_buff_full, + + output mem_if_t mem_a_rd_req, + output mem_if_t mem_b_rd_req, + output mem_if_t skmem_a_wr_req, + output mem_if_t skmem_b_wr_req, + output logic pk_t1_wren, + output logic [7 : 0] pk_t1_wr_addr, // K*N*10 / 8coeff_per_write TODO: parameter + output logic sk_buff_enable, + output logic done + ); + + localparam [MLDSA_MEM_ADDR_WIDTH-1 : 0] MAX_MEM_ADDR = (MLDSA_K * (MLDSA_N/4))-2; + localparam [MLDSA_MEM_ADDR_WIDTH-1 : 0] MAX_SKMEM_ADDR = (MLDSA_K * (MLDSA_N/32) * 13)-2; + localparam [7 : 0] MAX_PK_ADDR = ((MLDSA_K * (MLDSA_N/8))-1); + + power2round_read_state_type read_fsm_state_ps, read_fsm_state_ns; + power2round_sk_write_state_type sk_write_fsm_state_ps, sk_write_fsm_state_ns; + power2round_pk_write_state_type pk_write_fsm_state_ps, pk_write_fsm_state_ns; + + + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr, mem_rd_addr_nxt, mem_rd_addr_delay, mem_rd_addr_tmp; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] skmem_wr_addr, skmem_wr_addr_nxt; + logic [7 : 0] pk_wr_addr, pk_wr_addr_nxt; + + logic rst_mem_rd_addr, incr_mem_rd_addr, last_mem_rd_addr; + logic rst_skmem_wr_addr, incr_rskmem_wr_addr, last_skmem_wr_addr; + logic rst_pk_wr_addr, incr_pk_wr_addr, last_pk_wr_addr; + + logic pk_t1_wren_tmp; + +//addr counter + always_comb mem_rd_addr_nxt = mem_rd_addr + 'h2; + always_comb skmem_wr_addr_nxt = skmem_wr_addr + 'h2; + always_comb pk_wr_addr_nxt = pk_wr_addr + 'h1; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_rd_addr <= 'h0; + mem_rd_addr_delay <= 'h0; + skmem_wr_addr <= 'h0; + pk_wr_addr <= 'h0; + end + else if (zeroize) begin + mem_rd_addr <= 'h0; + mem_rd_addr_delay <= 'h0; + skmem_wr_addr <= 'h0; + pk_wr_addr <= 'h0; + end + else begin + if (rst_mem_rd_addr) + mem_rd_addr <= src_base_addr; + else if (incr_mem_rd_addr & ~last_mem_rd_addr) + mem_rd_addr <= mem_rd_addr_nxt; + + mem_rd_addr_delay <= mem_rd_addr; + + if (rst_skmem_wr_addr) + skmem_wr_addr <= skmem_dest_base_addr; + else if (incr_rskmem_wr_addr & ~last_skmem_wr_addr) + skmem_wr_addr <= skmem_wr_addr_nxt; + + if (rst_pk_wr_addr) + pk_wr_addr <= 'h0; //pk_dest_base_addr; + else if (incr_pk_wr_addr & ~last_pk_wr_addr) + pk_wr_addr <= pk_wr_addr_nxt; + end + end + + assign last_mem_rd_addr = (mem_rd_addr == src_base_addr + MAX_MEM_ADDR); + assign last_skmem_wr_addr = (skmem_wr_addr == skmem_dest_base_addr + MAX_SKMEM_ADDR); + assign last_pk_wr_addr = (pk_wr_addr == MAX_PK_ADDR); //pk_dest_base_addr = 'h0; + + // READ FSM + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= T_RD_IDLE; + else if (zeroize) + read_fsm_state_ps <= T_RD_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; + end + + always_comb begin + rst_mem_rd_addr = 'b0; + incr_mem_rd_addr = 'b0; + + case(read_fsm_state_ps) + T_RD_IDLE: begin + read_fsm_state_ns = enable? T_RD_MEM : T_RD_IDLE; + rst_mem_rd_addr = 'b1; + end + T_RD_MEM: begin + read_fsm_state_ns = (last_mem_rd_addr & ~sk_buff_full) ? T_RD_DONE : T_RD_MEM; + incr_mem_rd_addr = ~sk_buff_full; + end + T_RD_DONE: begin + read_fsm_state_ns = sk_buff_full ? T_RD_DONE : T_RD_IDLE; //ensure to capture the last read input + end + default: read_fsm_state_ns = T_RD_IDLE; + endcase + end + + // SK MEM WRITE FSM + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + sk_write_fsm_state_ps <= SK_WR_IDLE; + else if (zeroize) + sk_write_fsm_state_ps <= SK_WR_IDLE; + else + sk_write_fsm_state_ps <= sk_write_fsm_state_ns; + end + + always_comb begin + rst_skmem_wr_addr = 'b0; + incr_rskmem_wr_addr = 'b0; + + case(sk_write_fsm_state_ps) + SK_WR_IDLE: begin + sk_write_fsm_state_ns = (read_fsm_state_ps == T_RD_IDLE)? SK_WR_IDLE : SK_WR_WAIT; + rst_skmem_wr_addr = 'b1; + end + SK_WR_WAIT: begin + sk_write_fsm_state_ns = SK_WR_MEM; + end + SK_WR_MEM: begin + sk_write_fsm_state_ns = last_skmem_wr_addr? SK_WR_DONE : SK_WR_MEM; + incr_rskmem_wr_addr = sk_buff_valid; + end + SK_WR_DONE: begin + sk_write_fsm_state_ns = SK_WR_IDLE; + end + default: sk_write_fsm_state_ns = SK_WR_IDLE; + endcase + end + + + // PK WRITE FSM + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + pk_write_fsm_state_ps <= PK_WR_IDLE; + else if (zeroize) + pk_write_fsm_state_ps <= PK_WR_IDLE; + else + pk_write_fsm_state_ps <= pk_write_fsm_state_ns; + end + + always_comb begin + rst_pk_wr_addr = 'b0; + incr_pk_wr_addr = 'b0; + + case(pk_write_fsm_state_ps) + PK_WR_IDLE: begin + pk_write_fsm_state_ns = (read_fsm_state_ps == T_RD_IDLE)? PK_WR_IDLE : PK_WR_API; + rst_pk_wr_addr = 'b1; + end + PK_WR_API: begin + pk_write_fsm_state_ns = (last_pk_wr_addr & pk_t1_wren_tmp)? PK_WR_DONE : PK_WR_API; + incr_pk_wr_addr = (r_valid & ~sk_buff_full); + end + PK_WR_DONE: begin + pk_write_fsm_state_ns = PK_WR_IDLE; + end + default: pk_write_fsm_state_ns = PK_WR_IDLE; + endcase + end + + always_comb begin + sk_buff_enable = (sk_write_fsm_state_ps == SK_WR_MEM)? (r_valid & ~sk_buff_full) : 'h0; + end + + always_comb mem_rd_addr_tmp = sk_buff_full? mem_rd_addr_delay : mem_rd_addr; + + always_comb begin + mem_a_rd_req.rd_wr_en = (read_fsm_state_ps != T_RD_IDLE) ? RW_READ : RW_IDLE; + mem_a_rd_req.addr = mem_rd_addr_tmp; + + mem_b_rd_req.rd_wr_en = (read_fsm_state_ps != T_RD_IDLE) ? RW_READ : RW_IDLE; + mem_b_rd_req.addr = mem_rd_addr_tmp + 1'h1; + + skmem_a_wr_req.rd_wr_en = ((sk_write_fsm_state_ps == SK_WR_MEM) & sk_buff_valid) ? RW_WRITE : RW_IDLE; + skmem_a_wr_req.addr = skmem_wr_addr; + + skmem_b_wr_req.rd_wr_en = ((sk_write_fsm_state_ps == SK_WR_MEM) & sk_buff_valid) ? RW_WRITE : RW_IDLE; + skmem_b_wr_req.addr = skmem_wr_addr + 'h1; + + pk_t1_wren_tmp = (pk_write_fsm_state_ps == PK_WR_API)? (r_valid & ~sk_buff_full) : 'h0; + pk_t1_wr_addr = pk_wr_addr; + + end + + assign pk_t1_wren = pk_t1_wren_tmp; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + done <= 'h0; + else if (zeroize) + done <= 'h0; + else + done <= (sk_write_fsm_state_ps == SK_WR_DONE); + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..2e0c95a50c3420bcc91b0aee5b4a075acec431db --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_defines_pkg.sv @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// power2round_defines_pkg.sv +// -------- +// power2round parameters for Mldsa +//====================================================================== + +`ifndef MLDSA_POWER2ROUND_DEFINES +`define MLDSA_POWER2ROUND_DEFINES + +package power2round_defines_pkg; + + typedef enum logic [1:0] {T_RD_IDLE, T_RD_MEM, T_RD_DONE} power2round_read_state_type; + typedef enum logic [1:0] {SK_WR_IDLE, SK_WR_WAIT, SK_WR_MEM, SK_WR_DONE} power2round_sk_write_state_type; + typedef enum logic [1:0] {PK_WR_IDLE, PK_WR_API, PK_WR_DONE} power2round_pk_write_state_type; + +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_skencode.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_skencode.sv new file mode 100644 index 0000000000000000000000000000000000000000..3d1cba0ebe256166b12bbddacf0a71db292eff05 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_skencode.sv @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// power2round_skencode.sv +// -------- +// Breaks down input coefficient +//====================================================================== + +module power2round_skencode + #( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_D = 13 + ) + ( + input logic [MLDSA_D-1:0] r0, + output logic [MLDSA_D-1:0] r0_packed + ); + + localparam power2_d_minus_one = (1 << (MLDSA_D-1)); + + logic [MLDSA_D-1 : 0] r0_packed_temp; + + always_comb begin + r0_packed_temp = power2_d_minus_one - r0; + end + + assign r0_packed = r0_packed_temp; +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..7f5322e616731808de937e0e18b7dd827b2f2a3c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/rtl/power2round_top.sv @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// power2round_top.sv +// -------- +//====================================================================== + +module power2round_top + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = 24, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_N = 256, + parameter MLDSA_K = 8, + parameter MLDSA_D = 13, + parameter AHB_DATA_WIDTH = 32 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire enable, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] skmem_dest_base_addr, //skmem API base addr - TODO: finalize size + // input wire [MLDSA_MEM_ADDR_WIDTH-1:0] pk_dest_base_addr, //reg API base addr - TODO: finalize size + + //Input from internal memory + output mem_if_t mem_a_rd_req, + output mem_if_t mem_b_rd_req, + input wire [(4*REG_SIZE)-1:0] mem_rd_data_a, + input wire [(4*REG_SIZE)-1:0] mem_rd_data_b, + //input wire mem_rd_data_valid, // TODO: + + //output to sk mem + output mem_if_t skmem_a_wr_req, + output mem_if_t skmem_b_wr_req, + output logic [AHB_DATA_WIDTH-1:0] skmem_wr_data_a, + output logic [AHB_DATA_WIDTH-1:0] skmem_wr_data_b, + + output logic pk_t1_wren, + output logic [7:0][9:0] pk_t1_wrdata, // TODO: change to parameter + output logic [7:0] pk_t1_wr_addr, // TODO: change to parameter + + output logic done + ); + + + logic [7:0][REG_SIZE-1:0] mem_data_reg; + logic [7:0][MLDSA_D-1:0] r0, r0_packed, r0_packed_reg; + logic [7:0][REG_SIZE-MLDSA_D-2:0] r1, r1_reg; + + logic sk_buff_full; + logic mem_data_reg_valid, r_valid; + logic mem_rd_data_valid; + + logic sk_buff_enable; + logic sk_buff_valid; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + mem_rd_data_valid <= 'h0; + else if (zeroize) + mem_rd_data_valid <= 'h0; + else + mem_rd_data_valid <= (mem_a_rd_req.rd_wr_en == RW_READ); //assuming data is valid 1 cycle after read request + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_data_reg <= 'h0; + mem_data_reg_valid <= 'h0; + end + else if (zeroize) begin + mem_data_reg <= 'h0; + mem_data_reg_valid <= 'h0; + end + else if (~sk_buff_full) begin + {mem_data_reg[3], mem_data_reg[2], mem_data_reg[1], mem_data_reg[0]} <= mem_rd_data_a; + {mem_data_reg[7], mem_data_reg[6], mem_data_reg[5], mem_data_reg[4]} <= mem_rd_data_b; + mem_data_reg_valid <= mem_rd_data_valid; + end + end + + generate + for (genvar i = 0; i < 8; i++) begin + power2round_core #( + .REG_SIZE(REG_SIZE-1), + .MLDSA_Q(MLDSA_Q), + .MLDSA_D(MLDSA_D) + ) + power2round_core_inst ( + .r(mem_data_reg[i][REG_SIZE-2:0]), + .r0(r0[i]), + .r1(r1[i]) + ); + end + endgenerate + + + generate + for (genvar i = 0; i < 8; i++) begin + power2round_skencode #( + .REG_SIZE(REG_SIZE-1), + .MLDSA_Q(MLDSA_Q), + .MLDSA_D(MLDSA_D) + ) + power2round_skencode_inst ( + .r0(r0[i]), + .r0_packed(r0_packed[i]) + ); + end + endgenerate + + generate + for (genvar i = 0; i < 8; i++) begin + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + r0_packed_reg[i] <= 'h0; + r1_reg[i] <= 'h0; + end + else if (zeroize) begin + r0_packed_reg[i] <= 'h0; + r1_reg[i] <= 'h0; + end + else if (~sk_buff_full) begin + r0_packed_reg[i] <= r0_packed[i]; + r1_reg[i] <= r1[i]; + end + end + end + endgenerate + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + r_valid <= 'h0; + else if (zeroize) + r_valid <= 'h0; + else if (~sk_buff_full) + r_valid <= mem_data_reg_valid; + end + + generate + for (genvar i = 0; i < 8; i++) begin + always_comb begin + pk_t1_wrdata[i] = r1_reg[i]; + end + end + endgenerate + + + abr_sample_buffer #( + .NUM_WR(13), + .NUM_RD(8), + .BUFFER_DATA_W(8) + ) + sk_buffer_inst ( + .clk(clk), + .rst_b(reset_n), + .zeroize(zeroize), + .data_valid_i({13{sk_buff_enable}}), + .data_i(r0_packed_reg), + .buffer_full_o(sk_buff_full), + .data_valid_o(sk_buff_valid), + .data_o({skmem_wr_data_b, skmem_wr_data_a}) + ); + + + power2round_ctrl #( + .MLDSA_K(MLDSA_K), + .MLDSA_N(MLDSA_N) + ) + power2round_ctrl_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .enable(enable), + .src_base_addr(src_base_addr), + .skmem_dest_base_addr(skmem_dest_base_addr), + // .pk_dest_base_addr(pk_dest_base_addr), + .r_valid(r_valid), + .sk_buff_valid(sk_buff_valid), + .sk_buff_full(|sk_buff_full), + + .mem_a_rd_req(mem_a_rd_req), + .mem_b_rd_req(mem_b_rd_req), + .skmem_a_wr_req(skmem_a_wr_req), + .skmem_b_wr_req(skmem_b_wr_req), + .pk_t1_wren(pk_t1_wren), + .pk_t1_wr_addr(pk_t1_wr_addr), + .sk_buff_enable(sk_buff_enable), + .done(done) + ); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/stimulus/tests/directed/power2round_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/stimulus/tests/directed/power2round_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..8566325d8028f36e905aad995d04a98fec7a16e9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/stimulus/tests/directed/power2round_normal_test.yml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- + +testname: power2round_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/tb/power2round.py b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/tb/power2round.py new file mode 100644 index 0000000000000000000000000000000000000000..fb623c6a8301448228585fc1adac8e3c8a16719d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/tb/power2round.py @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import numpy as np +import random + +DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1 +DILITHIUM_N = 256 +DILITHIUM_K = 8 +DILITHIUM_D = 13 + + +def vec_power2round(t): + coeff_high = [] + coeff_low = [] + for poly_i in t: + r1, r0 = poly_power2round(poly_i) + coeff_high.append(r1) + coeff_low.append(r0) + return coeff_high, coeff_low + +def poly_power2round(poly): + r1_coeffs = [] + r0_coeffs = [] + for coeff_i in poly: + r1, r0 = power2round(coeff_i) + r1_coeffs.append(r1) + r0_coeffs.append(r0) + return r1_coeffs, r0_coeffs + +def power2round(coeff): + power_2 = (1 << DILITHIUM_D-1) + r = coeff % DILITHIUM_Q + r1 = (r + (power_2 - 1)) >> DILITHIUM_D + r0 = r - (r1 << DILITHIUM_D) + return r1, r0 + +def skencode(value): + value_encodede = (1 << (DILITHIUM_D-1)) - value + return f"{value_encodede:0X}" + +vec = [] +for _ in range(DILITHIUM_K): + poly = [random.randrange(DILITHIUM_Q) for _ in range(DILITHIUM_N)] + vec.append(poly) + +coeff_high, coeff_low = vec_power2round(vec) + +# Export to files +with open("coeff_input.hex", "w") as input_file, \ + open("coeff_high.hex", "w") as high_file, \ + open("coeff_low.hex", "w") as low_file: + + for poly_index, (r1_coeffs, r0_coeffs) in enumerate(zip(coeff_high, coeff_low)): + for i in range(DILITHIUM_N): + input_file.write(f"{vec[poly_index][i]:06X}\n") + high_file.write(f"{r1_coeffs[i]:X}\n") + low_file.write(f"{skencode(r0_coeffs[i])}\n") diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/tb/power2round_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/tb/power2round_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..cb8d15757ff7791866888aba135cc2ce6295e6d0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/power2round/tb/power2round_tb.sv @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// power2round_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module power2round_tb + import mldsa_params_pkg::*; +#( + parameter REG_SIZE = 24, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_N = 256, + parameter MLDSA_K = 8, + parameter OMEGA = 75, + parameter BUFFER_DATA_W = 8, + parameter MEM_ADDR_WIDTH = 15, + parameter AHB_DATA_WIDTH = 32 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +parameter TEST_VECTOR_NUM = 2048; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg [31 : 0] tc_ctr; +reg [31 : 0] error_ctr; + +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg en_tb; +reg [(4*24)-1:0] coeff_tb; +logic done_tb; + +reg [TEST_VECTOR_NUM-1:0][23:0] coeff_input; +reg [TEST_VECTOR_NUM-1:0][9:0] coeff_high; +reg [TEST_VECTOR_NUM-1:0][12:0] coeff_low; + +logic [(4*24)-1:0] mem_rd_data_a_tb, mem_rd_data_b_tb; +logic mem_rd_data_valid_tb; +mem_if_t mem_a_rd_req_tb; +mem_if_t mem_b_rd_req_tb; +mem_if_t skmem_a_wr_req_tb; +mem_if_t skmem_b_wr_req_tb; +logic [AHB_DATA_WIDTH-1:0] skmem_wr_data_a_tb; +logic [AHB_DATA_WIDTH-1:0] skmem_wr_data_b_tb; +logic pk_t1_wren_tb; +logic [7:0][9:0] pk_t1_wrdata_tb; +logic [7:0] pk_t1_wr_addr_tb; + +reg [831:0][31:0] skmem_data; + +power2round_top #( + //.BUFFER_DATA_W(BUFFER_DATA_W) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .enable(en_tb), + .src_base_addr(15'h0), + .skmem_dest_base_addr(15'h0), + .mem_a_rd_req(mem_a_rd_req_tb), + .mem_b_rd_req(mem_b_rd_req_tb), + .mem_rd_data_a(mem_rd_data_a_tb), + .mem_rd_data_b(mem_rd_data_b_tb), + // .mem_rd_data_valid(mem_rd_data_valid_tb), + .skmem_a_wr_req(skmem_a_wr_req_tb), + .skmem_b_wr_req(skmem_b_wr_req_tb), + .skmem_wr_data_a(skmem_wr_data_a_tb), + .skmem_wr_data_b(skmem_wr_data_b_tb), + .pk_t1_wren(pk_t1_wren_tb), + .pk_t1_wrdata(pk_t1_wrdata_tb), + .pk_t1_wr_addr(pk_t1_wr_addr_tb), + .done(done_tb) +); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +//---------------------------------------------------------------- +// init_sim() +// +// Initialize all counters and testbed functionality as well +// as setting the DUT inputs to defined values. +//---------------------------------------------------------------- +task init_sim; + begin + $display("Start of init\n"); + error_ctr = 32'h00000000; + tc_ctr = 32'h00000000; + + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + zeroize_tb = 0; + en_tb = 0; + mem_rd_data_a_tb = 'h0; + mem_rd_data_b_tb = 'h0; + mem_rd_data_valid_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + +//---------------------------------------------------------------- +// display_test_results() +// +// Display the accumulated test results. +//---------------------------------------------------------------- +task display_test_results; +begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d tests completed - %02d test cases did not complete successfully.", + tc_ctr, error_ctr); + $display("* TESTCASE FAILED"); + end +end +endtask // display_test_results + +task read_test_vectors(); + string coeff_input_fname = "coeff_input.hex"; + string coeff_high_fname = "coeff_high.hex"; + string coeff_low_fname = "coeff_low.hex"; + + integer fin; + integer ret; + int test_vector_cnt; + + //generate input vectors and expected results + $system($sformatf("python power2round.py")); + + // read input coeff + fin = $fopen(coeff_input_fname, "r"); + if (fin == 0) + $error("Can't open file %s", coeff_input_fname); + + test_vector_cnt = 0; + while (!$feof(fin)) begin + ret = $fscanf(fin, "%h\n", coeff_input[test_vector_cnt]); + if (ret != 1) begin + $error("Failed to read a matching string"); + $fclose(fin); + $finish; + end + test_vector_cnt++; + end + $fclose(fin); + + $display("Read input test vectors from %s", coeff_input_fname); + + // read coeff high + fin = $fopen(coeff_high_fname, "r"); + if (fin == 0) + $error("Can't open file %s", coeff_high_fname); + + test_vector_cnt = 0; + while (!$feof(fin)) begin + ret = $fscanf(fin, "%h\n", coeff_high[test_vector_cnt]); + if (ret != 1) begin + $error("Failed to read a matching string"); + $fclose(fin); + $finish; + end + test_vector_cnt++; + end + $fclose(fin); + + $display("Read input test vectors from %s", coeff_high_fname); + + + // read coeff low + fin = $fopen(coeff_low_fname, "r"); + if (fin == 0) + $error("Can't open file %s", coeff_low_fname); + + test_vector_cnt = 0; + while (!$feof(fin)) begin + ret = $fscanf(fin, "%h\n", coeff_low[test_vector_cnt]); + if (ret != 1) begin + $error("Failed to read a matching string"); + $fclose(fin); + $finish; + end + test_vector_cnt++; + end + $fclose(fin); + + $display("Read input test vectors from %s", coeff_low_fname); + +endtask + +task power2round_test(); + reg [31 : 0] time_limit; + int pk_index; + begin + time_limit = 0; + pk_index = 0; + skmem_data = 'h0; + $display("Starting power2round test\n"); + //$system($sformatf("python3 power2round.py")); + + @(posedge clk_tb); + en_tb <= 1; + @(posedge clk_tb); + en_tb <= 0; + @(posedge clk_tb); + + while (~done_tb & (time_limit < 1000)) begin + mem_rd_data_a_tb <= (mem_a_rd_req_tb.rd_wr_en == RW_READ)? {coeff_input[4*mem_a_rd_req_tb.addr+3],coeff_input[4*mem_a_rd_req_tb.addr+2],coeff_input[4*mem_a_rd_req_tb.addr+1],coeff_input[4*mem_a_rd_req_tb.addr]} : 'h0; + mem_rd_data_b_tb <= (mem_b_rd_req_tb.rd_wr_en == RW_READ)? {coeff_input[4*mem_b_rd_req_tb.addr+3],coeff_input[4*mem_b_rd_req_tb.addr+2],coeff_input[4*mem_b_rd_req_tb.addr+1],coeff_input[4*mem_b_rd_req_tb.addr]} : 'h0; + mem_rd_data_valid_tb <= (mem_a_rd_req_tb.rd_wr_en == RW_READ); + if (pk_t1_wren_tb) begin + if (pk_index != pk_t1_wr_addr_tb) begin + $display("Error: pk_t1 addr mismatch. Exp: %gh, Ohs: %6h", pk_index, pk_t1_wr_addr_tb); + error_ctr = error_ctr + 1; + end + for (int i=0; i<8; i++) + if (pk_t1_wrdata_tb[i] != coeff_high[8*pk_t1_wr_addr_tb+i]) begin + $display("Error: pk_t1 data mismatch. Exp: %gh, Ohs: %6h", coeff_high[8*pk_t1_wr_addr_tb+i], pk_t1_wrdata_tb[i]); + error_ctr = error_ctr + 1; + end + pk_index++; + tc_ctr = tc_ctr + 8; + end + + if (skmem_a_wr_req_tb.rd_wr_en == RW_WRITE) + skmem_data[skmem_a_wr_req_tb.addr] = skmem_wr_data_a_tb; + + if (skmem_b_wr_req_tb.rd_wr_en == RW_WRITE) + skmem_data[skmem_b_wr_req_tb.addr] = skmem_wr_data_b_tb; + + time_limit = time_limit + 1; + @(posedge clk_tb); + end + + if (pk_index != TEST_VECTOR_NUM/8) begin // 8 coeff per write + $display("Error: pk_t1 write is not completed. Exp: %gh, Ohs: %6h", TEST_VECTOR_NUM/8, pk_index); + error_ctr = error_ctr + 1; + end + + if (skmem_data != coeff_low) begin + $display("Error: coeff_low data mismatch."); + error_ctr = error_ctr + 1; + end + + $display("Test done\n"); + repeat(100) @(posedge clk_tb); + end +endtask + +initial begin + init_sim(); + reset_dut(); + read_test_vectors(); + power2round_test(); + + display_test_results(); + + $display(""); + $display("*** ecc simulation done. ***"); + $finish; + +end +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..9720ebb698184baa3b5128d8abfa5f17c11c2182 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/compile.yml @@ -0,0 +1,33 @@ +--- +provides: [rej_bounded] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/rej_bounded_ctrl.sv + - $COMPILE_ROOT/rtl/rej_bounded2.sv + tops: [rej_bounded_ctrl] +--- +provides: [rej_bounded_tb] +schema_version: 2.4.0 +requires: + - rej_bounded +targets: + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/rej_bounded_tb.sv + tops: [rej_bounded_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ref model to ${pwd}" && cp $COMPILE_ROOT/tb/rej_bounded.py .' +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+CLP_ASSERT_ON + - '-noinherit_timescale=1ns/1ps' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/rej_bounded.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/rej_bounded.vf new file mode 100644 index 0000000000000000000000000000000000000000..2c2539905b62e1f0110f9e2c0d9e1e633bb167a0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/rej_bounded.vf @@ -0,0 +1,35 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded2.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/rej_bounded_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/rej_bounded_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..467f292ac237dce473d80821ad87e4385c89d6ec --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/config/rej_bounded_tb.vf @@ -0,0 +1,37 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/tb ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/tb/rej_bounded_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_bounded/rtl/rej_bounded2.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/rtl/rej_bounded2.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/rtl/rej_bounded2.sv new file mode 100644 index 0000000000000000000000000000000000000000..77c2cb3d6c69bc5f24aeb79702a859b80bd3ea2c --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/rtl/rej_bounded2.sv @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Rej Bounded function computes % 5 of the input sample +//Samples must be < REJ_VALUE to be valid + +module rej_bounded2 + // import ::*; + #( + parameter REJ_SAMPLE_W = 24 + ,parameter REJ_VALUE = 15 + ) + ( + //input data + input logic valid_i, + input logic [3:0] data_i, + + //output data + output logic valid_o, + output logic [2:0] data_o + + ); + + logic [3:0] a; + logic [2:0] b; + + assign a = data_i; + + //Check sample validity + always_comb begin + valid_o = valid_i & (a < REJ_VALUE); + //Perform data_i % 5 + b = a[1:0] - a[3:2]; + data_o = b[2] ? 'd5 + b[2:0] : {1'b0, b[1:0]}; + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/rtl/rej_bounded_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/rtl/rej_bounded_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..5b64b5f969adb06d47376882f3625fc315d5b945 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/rtl/rej_bounded_ctrl.sv @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +module rej_bounded_ctrl + import mldsa_params_pkg::*; + #( + parameter REJ_NUM_SAMPLERS = 8 + ,parameter REJ_SAMPLE_W = 4 + ,parameter REJ_VLD_SAMPLES = 4 + ,parameter REJ_VLD_SAMPLES_W = 24 + ,parameter REJ_VALUE = 15 + ,parameter REJ_BUFFER_W = 3 + ) + ( + input logic clk, + input logic rst_b, + input logic zeroize, + //input data + input logic data_valid_i, + output logic data_hold_o, + input logic [REJ_NUM_SAMPLERS-1:0][REJ_SAMPLE_W-1:0] data_i, + + //output data + output logic data_valid_o, + output logic [REJ_VLD_SAMPLES-1:0][REJ_VLD_SAMPLES_W-1:0] data_o + + ); + + logic [REJ_NUM_SAMPLERS-1:0] sample_valid; + logic [REJ_NUM_SAMPLERS-1:0][REJ_BUFFER_W-1:0] buffer_data; + + logic rej_buffer_valid; + logic [REJ_VLD_SAMPLES-1:0][REJ_BUFFER_W-1:0] rej_buffer; + + logic buffer_full; + + + //Hold if the buffer is full + always_comb data_hold_o = buffer_full; + + generate + for (genvar inst_g = 0; inst_g < REJ_NUM_SAMPLERS; inst_g++) begin : rej_bounded_inst + rej_bounded2 #( + .REJ_SAMPLE_W(REJ_SAMPLE_W), + .REJ_VALUE(REJ_VALUE) + ) rej_bounded_i ( + .valid_i(data_valid_i), + .data_i(data_i[inst_g]), + + .valid_o(sample_valid[inst_g]), + .data_o(buffer_data[inst_g]) + ); + end + endgenerate + + //Buffer valid samples + abr_sample_buffer #( + .NUM_WR(REJ_NUM_SAMPLERS), + .NUM_RD(REJ_VLD_SAMPLES), + .BUFFER_DATA_W(REJ_BUFFER_W) + ) mldsa_sample_buffer_i ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize), + //input data + .data_valid_i(sample_valid), + .data_i(buffer_data), + .buffer_full_o(buffer_full), + //output data + .data_valid_o(rej_buffer_valid), + .data_o(rej_buffer) + ); + + //Output is valid when we have REJ_VLD_SAMPLES worth of valid data + always_comb data_valid_o = rej_buffer_valid; + //Rej buffer value selects between 5 possible outputs (2-(a%5) mod q) + always_comb begin + for (int sample = 0; sample < REJ_VLD_SAMPLES; sample++) begin + unique case (rej_buffer[sample]) + 3'd0 : data_o[sample] = 2; + 3'd1 : data_o[sample] = 1; + 3'd2 : data_o[sample] = 0; + 3'd3 : data_o[sample] = MLDSA_Q-1; + 3'd4 : data_o[sample] = MLDSA_Q-2; + default : data_o[sample] = '0; + endcase + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/stimulus/tests/directed/rej_rand_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/stimulus/tests/directed/rej_rand_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..8b8623e433fc0138e7e1e30da2ef7f4a8e89369b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/stimulus/tests/directed/rej_rand_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: rej_rand_test +seed: 1 #${PLAYBOOK_RANDOM_SEED} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/tb/rej_bounded.py b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/tb/rej_bounded.py new file mode 100644 index 0000000000000000000000000000000000000000..12e2fdee7f857c682c0be6f82c80029db491427e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/tb/rej_bounded.py @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import sys +import os +import binascii +from hashlib import shake_128, shake_256 + +DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1 +DILITHIUM_N = 256 +DILITHIUM_LOGN = 8 +DILITHIUM_ROOT_OF_UNITY = 1753 + +## Category 5 parameters: +DILITHIUM_ETA = 2 +DILITHIUM_ETA_BOUND = 15 +DILITHIUM_TAU = 60 +DILITHIUM_GAMMA1 = 2**19 + + +class Shake(): + def __init__(self, algorithm, block_length): + self.algorithm = algorithm + self.block_length = block_length + self.read_blocks = 0 + self.read_data = b"" + + def absorb(self, input_bytes): + self.read_blocks = 0 + self.read_data = b"" + self.xof = self.algorithm(input_bytes) + + def digest(self, input_bytes, length): + return self.algorithm(input_bytes).digest(length) + + def get_n_blocks(self, n): + byte_count = self.block_length * (self.read_blocks + n) + xof_data = self.xof.digest(byte_count) + self.read_blocks += n + self.read_data = xof_data[-self.block_length*n:] + + def read(self, n): + if n > len(self.read_data): + self.get_n_blocks(5*n) + send = self.read_data[:n] + self.read_data = self.read_data[n:] + return send + +Shake128 = Shake(shake_128, 168) +Shake256 = Shake(shake_256, 136) + +def rejbounded(seed): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_ETA + global DILITHIUM_ETA_BOUND + global buff_arr + + def rejection_sample(xof): + global buff_arr + while True: + js = [] + if (len(buff_arr) == 0): + log_file.write("squeezing\n") + buff_bytes = xof.read(136) + buff_arr = bytearray(buff_bytes) + buff_int = int.from_bytes(buff_bytes, "little") + input_vectors.write(f"{buff_int:0272x}") + j = buff_arr[0] + buff_arr.pop(0) + log_file.write("byte: " + f"{j:02x}" + "\n") + # Consider two values for each byte (top and bottom four bits) + j0 = j & 0x0F + j1 = j >> 4 + + # rejection sample + if j0 < DILITHIUM_ETA_BOUND: + if DILITHIUM_ETA == 2: j0 %= 5 + log_file.write("ack: " + f"{j0:01x}" + "\n") + js.append((DILITHIUM_ETA - j0) % DILITHIUM_Q) + else: log_file.write("rej: " + f"{j0:01x}" + "\n") + if j1 < DILITHIUM_ETA_BOUND: + if DILITHIUM_ETA == 2: j1 %= 5 + log_file.write("ack: " + f"{j1:01x}" + "\n") + js.append((DILITHIUM_ETA - j1) % DILITHIUM_Q) + else: log_file.write("rej: " + f"{j1:01x}" + "\n") + + if js: + return js + + # Initialise the XOF + Shake256.absorb(seed) + buff_arr = bytearray() + coeffs = [] + while len(coeffs) < DILITHIUM_N: + js = rejection_sample(Shake256) + coeffs += js + + # Remove the last byte if we ended up overfilling + if len(coeffs) > DILITHIUM_N: + coeffs = coeffs[:DILITHIUM_N] + + return coeffs + +#open the input vector file for reading +input_seeds = open("input_seeds.txt", "r") +input_vectors = open("input_vectors.txt", "w") +exp_results = open("exp_results.txt", "w") +log_file = open("rej_bounded.log", "w") +Lines = input_seeds.readlines() + +for line in Lines: + Coeffs = rejbounded( bytes(line.strip(),'utf-8') ) + for coeff in Coeffs: + exp_results.write(f"{coeff:06x}"+" ") + input_vectors.write("\n") + exp_results.write("\n") diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/tb/rej_bounded_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/tb/rej_bounded_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..24f3fd3ff0c7e04d6c0b107419fd5e45695ec333 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_bounded/tb/rej_bounded_tb.sv @@ -0,0 +1,440 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// rej_bounded_tb.sv +// -------- +// +//====================================================================== + +import "DPI-C" function string getenv(input string env_name); + +module rej_bounded_tb + //import mldsa_sampler_pkg::*; +( +`ifdef VERILATOR + input bit clk_tb +`endif + ); + + parameter REJ_NUM_SAMPLERS = 8; + parameter REJ_SAMPLE_W = 4; + parameter REJ_VLD_SAMPLES = 4; + parameter REJ_VLD_SAMPLES_W = 24; + parameter REJ_VALUE = 15; + localparam REJ_VLD_SAMPLE_W = $clog2(REJ_VALUE); + parameter PISO_BUFFER_W = 1334; + parameter PISO_INPUT_RATE = 1088; + parameter PISO_OUTPUT_RATE = 32; + parameter MLDSA_Q = 8380417; + parameter MLDSA_Q_WIDTH = $clog2(MLDSA_Q) + 1; + parameter MLDSA_N = 256; + + `ifndef VERILATOR + int MAX_CYCLES; + int VEC_CNT; + + initial begin + // To use this from the command line, add "+MAX_CYCLES=" + // to override the sim timeout + if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin + $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES); + end else begin + MAX_CYCLES = 20_0000; + $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES); + end + if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin + $info("Received argument +VEC_CNT, with value %d", VEC_CNT); + end else begin + VEC_CNT = 10; + $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT); + end + end + `else + parameter MAX_CYCLES = 20_0000; + `endif + + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 5; + + //input data to piso + logic data_valid_i; + logic data_hold_o; + logic [PISO_INPUT_RATE-1:0] data_i; + + //input data + logic piso_valid; + logic piso_hold; + logic [REJ_NUM_SAMPLERS-1:0][REJ_SAMPLE_W-1:0] piso_data; + + //output data + logic data_valid_o; + logic [REJ_VLD_SAMPLES-1:0][MLDSA_Q_WIDTH-1:0] data_o; + + logic zeroize; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] vld_coeff_ctr; + reg [31 : 0] tc_ctr; + +`ifndef VERILATOR + reg clk_tb; +`endif + reg clk_i; + reg reset_n_tb; + reg rst_ni; + reg [31 : 0] read_data; + + assign clk_i = clk_tb; + assign rst_ni = reset_n_tb; + + logic [MLDSA_Q_WIDTH-1:0] exp_result; + logic [MLDSA_Q_WIDTH-1:0] expected_results[$]; // queue of results + + string seed_filename, vector_filename, exp_res_filename; + assign exp_res_filename = "exp_results.txt"; + assign seed_filename = "input_seeds.txt"; + assign vector_filename = "input_vectors.txt"; + + int fd_r_exp; + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + abr_piso #( + .PISO_BUFFER_W(PISO_BUFFER_W), + .PISO_INPUT_RATE(PISO_INPUT_RATE), + .PISO_OUTPUT_RATE(PISO_OUTPUT_RATE) + ) piso_i ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + .valid_i(data_valid_i), + .hold_o(data_hold_o), + .data_i(data_i), + .valid_o(piso_valid), + .hold_i(piso_hold), + .data_o(piso_data) + ); + + rej_bounded_ctrl #( + .REJ_NUM_SAMPLERS(REJ_NUM_SAMPLERS), + .REJ_SAMPLE_W(REJ_SAMPLE_W), + .REJ_VLD_SAMPLES(REJ_VLD_SAMPLES), + .REJ_VALUE(REJ_VALUE) + ) dut ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + //input data + .data_valid_i(piso_valid), + .data_hold_o(piso_hold), + .data_i(piso_data), + + //output data + .data_valid_o(data_valid_o), + .data_o(data_o) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- +`ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen +`endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + + // Test timeout monitor + if(cycle_ctr == MAX_CYCLES) begin + $error("Hit max cycle count (%0d) .. stopping",cycle_ctr); + $finish; + end + end + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + + repeat (2) @(posedge clk_tb); + + $display(""); + end + endtask // reset_dut + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + error_ctr = '0; + tc_ctr = '0; + vld_coeff_ctr = '0; +`ifndef VERILATOR + clk_tb = 0; +`endif + reset_n_tb = 0; + + zeroize = 0; + data_valid_i = '0; + data_i = '0; + + end + endtask // init_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + //---------------------------------------------------------------- + // Scoreboard + //---------------------------------------------------------------- + initial begin + forever begin + @(posedge clk_tb) + if (data_valid_o) begin + if (expected_results.size() >= REJ_VLD_SAMPLES) begin + for (int i = 0; i < REJ_VLD_SAMPLES; i++) begin + vld_coeff_ctr += 1; //increment vld coeff ctr + if (expected_results[0] != data_o[i]) begin + //ERROR + $display("[%t] Expected results mismatch for output index %d", $time, i); + $display("[%t] Actual: %x", $time,data_o[i]); + $display("[%t] Expected: %x", $time,expected_results[0]); + error_ctr += 1; + end + expected_results.pop_front(); + end + end else begin + //ERROR + $display("[%t] Not enough valid samples in the queue", $time); + error_ctr += 1; + end + end + end + + end + + initial begin + forever begin + @(posedge clk_tb) + if (vld_coeff_ctr == 256) begin + zeroize <= 1; + @(posedge clk_tb) + zeroize <= 0; + end + end + end + + initial begin + forever begin + @(posedge zeroize) + vld_coeff_ctr = '0; + expected_results = {}; + end + end + + //---------------------------------------------------------------- + // write_single_msg() + // + // Write the given msg to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_single_msg(logic [PISO_INPUT_RATE-1:0] rand_samples); + begin + data_valid_i <= 1; + data_i <= rand_samples; + + + @(posedge clk_tb); + //Make sure no hold + //drop this transaction if zeroize is set + while ((data_hold_o == 1) & (zeroize == 0)) @(posedge clk_tb); + + //@(posedge clk_tb); + data_valid_i <= 0; + data_i <= 'x; + + end + endtask // write_single_msg + + //---------------------------------------------------------------- + // gen_rand_test_vectors() + //---------------------------------------------------------------- + task gen_rand_test_vectors; + int fd_w; + + fd_w = $fopen(seed_filename, "a"); + if (fd_w == 0) $error("Cannot open file %s for writing", seed_filename); + + for (int i = 0; i < VEC_CNT; i++) begin + //Write random_ eeds + $fwrite(fd_w, "%0d \n", $urandom()); + end + $fclose(fd_w); + //generate input vectors and expected results + $system($sformatf("python rej_bounded.py")); + + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + endtask + + + //---------------------------------------------------------------- + // run_rand_test() + //---------------------------------------------------------------- + parameter PISO_INPUT_CHARS = PISO_INPUT_RATE/4; + parameter PISO_INPUT_DWORDS = PISO_INPUT_RATE/32; + task run_rand_test; + int fd_r_inp; + string line_read; + string line_substr; + int num_states; + logic [PISO_INPUT_DWORDS-1:0][31:0] test_data; + + //open input vectors + fd_r_inp = $fopen(vector_filename, "r"); + if (fd_r_inp == 0) begin + $error("Cannot open file %s for reading", vector_filename); + error_ctr++; + end + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + for (int iter = 0; iter < VEC_CNT; iter++) begin + //get the next exp result + if (!($fgets(line_read, fd_r_exp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + for (int res = 0; res < MLDSA_N; res++) begin + exp_result = line_read.substr(res*7, res*7 + 7-2).atohex(); + expected_results.push_back(exp_result); + end + + //get the next input vector + if (!($fgets(line_read, fd_r_inp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + + num_states = (line_read.len()/PISO_INPUT_CHARS); + //$display("Vector Length: %d", line_read.len()); + //$display("Number of states: %d", num_states); + for (int state = 0; state < num_states; state++) begin + line_substr = line_read.substr(state*PISO_INPUT_CHARS , (state*PISO_INPUT_CHARS)+PISO_INPUT_CHARS-1); + //$display("State: %s", line_substr); + for (int dword = 0; dword < PISO_INPUT_DWORDS; dword++) begin + test_data[dword] = line_substr.substr((PISO_INPUT_CHARS - dword*8 - 8), (PISO_INPUT_CHARS - dword*8 - 1)).atohex(); + //$display("Dword: %d - %h", dword, test_data[dword]); + end + write_single_msg(test_data); + end + + wait (zeroize == 1); + wait (zeroize == 0); + + tc_ctr++; + + end + + $fclose(fd_r_inp); + + endtask // run_hw_if_test + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + + initial + begin : main + $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED")); + $display(" -- Testbench for REJ_BOUNDED started --"); + + init_sim(); + reset_dut(); + + gen_rand_test_vectors(); + run_rand_test(); + + @(posedge clk_tb); + display_test_result(); + + $display(" -- Testbench for REJ_BOUNDED done. --"); + $finish; + end // main + +endmodule // rej_bounded_tb + +//====================================================================== +// EOF rej_bounded_tb.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..ac875c2d89076c88b2f7231a5e96423e60ffaa7a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/compile.yml @@ -0,0 +1,34 @@ +--- +provides: [rej_sampler] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/rej_sampler_ctrl.sv + - $COMPILE_ROOT/rtl/rej_sampler.sv + tops: [rej_sampler_ctrl] +--- +provides: [rej_sampler_tb] +schema_version: 2.4.0 +requires: + - rej_sampler + - mldsa_sampler_pkg +targets: + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/rej_sampler_tb.sv + tops: [rej_sampler_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ref model to ${pwd}" && cp $COMPILE_ROOT/tb/rej_sampler.py .' +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+ABR_ASSERT_ON + - '-noinherit_timescale=1ns/1ps' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/rej_sampler.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/rej_sampler.vf new file mode 100644 index 0000000000000000000000000000000000000000..50f320e33e1f6ab4286add054b945d88d2c5513a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/rej_sampler.vf @@ -0,0 +1,35 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/rej_sampler_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/rej_sampler_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..8c44774fb24b609e53522f89fda542bfc69ad8f5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/config/rej_sampler_tb.vf @@ -0,0 +1,40 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/tb ++incdir+${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/tb/rej_sampler_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/rej_sampler/rtl/rej_sampler.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/rtl/rej_sampler.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/rtl/rej_sampler.sv new file mode 100644 index 0000000000000000000000000000000000000000..15cd06a55abd23797345f8b49e45ba48a88b064a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/rtl/rej_sampler.sv @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Rej sampler function tests each sample for validity +//Valid samples must be < REJ_VALUE + +module rej_sampler + // import ::*; + #( + parameter REJ_SAMPLE_W = 24 + ,parameter REJ_VALUE = 8380417 + ,localparam REJ_VLD_SAMPLE_W = $clog2(REJ_VALUE) + ) + ( + //input data + input logic valid_i, + input logic [REJ_SAMPLE_W-1:0] data_i, + + //output data + output logic valid_o, + output logic [REJ_VLD_SAMPLE_W-1:0] data_o + + ); + + //Check sample validity + always_comb begin + valid_o = valid_i & (data_i[REJ_VLD_SAMPLE_W-1:0] < REJ_VALUE[REJ_VLD_SAMPLE_W-1:0]); + data_o = data_i[REJ_VLD_SAMPLE_W-1:0]; + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/rtl/rej_sampler_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/rtl/rej_sampler_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..5e5bb4593566b14ef1d17450756fb38742e90688 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/rtl/rej_sampler_ctrl.sv @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +module rej_sampler_ctrl + import mldsa_params_pkg::*; + #( + parameter REJ_NUM_SAMPLERS = 5 + ,parameter REJ_SAMPLE_W = 24 + ,parameter REJ_VLD_SAMPLES = 4 + ,parameter REJ_VLD_SAMPLES_W = 24 + ,parameter REJ_VALUE = 8380417 + ,parameter OPT_REJ_BUFFER_DEPTH = 0 + ,parameter REJ_BUFFER_W = $clog2(REJ_VALUE) + ) + ( + input logic clk, + input logic rst_b, + + input logic zeroize, + + //input data + input logic data_valid_i, + output logic data_hold_o, + input logic [REJ_NUM_SAMPLERS-1:0][REJ_SAMPLE_W-1:0] data_i, + + //output data + output logic data_valid_o, + output logic [REJ_VLD_SAMPLES-1:0][REJ_VLD_SAMPLES_W-1:0] data_o + + ); + + logic [REJ_NUM_SAMPLERS-1:0] sample_valid; + logic [REJ_NUM_SAMPLERS-1:0][REJ_BUFFER_W-1:0] buffer_data; + + logic rej_buffer_valid; + logic [REJ_VLD_SAMPLES-1:0][REJ_BUFFER_W-1:0] rej_buffer; + + logic buffer_full; + + //Hold if the buffer is full + always_comb data_hold_o = buffer_full; + + generate + for (genvar inst_g = 0; inst_g < REJ_NUM_SAMPLERS; inst_g++) begin : rej_sampler_inst + //Check sample validity + rej_sampler #( + .REJ_SAMPLE_W(REJ_SAMPLE_W), + .REJ_VALUE(REJ_VALUE) + ) rej_sampler_i ( + .valid_i(data_valid_i), + .data_i(data_i[inst_g]), + + .valid_o(sample_valid[inst_g]), + .data_o(buffer_data[inst_g]) + ); + end + endgenerate + + //Buffer valid samples + abr_sample_buffer #( + .NUM_WR(REJ_NUM_SAMPLERS), + .NUM_RD(REJ_VLD_SAMPLES), + .BUFFER_DATA_W(REJ_BUFFER_W) + ) mldsa_sample_buffer_i ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize), + //input data + .data_valid_i(sample_valid), + .data_i(buffer_data), + .buffer_full_o(buffer_full), + //output data + .data_valid_o(rej_buffer_valid), + .data_o(rej_buffer) + ); + + //Output is valid when we have REJ_VLD_SAMPLES worth of valid data + always_comb data_valid_o = rej_buffer_valid; + //Need to concat the zeros back for diff between sample w and the valid sample bits + always_comb begin + for (int sample = 0; sample < REJ_VLD_SAMPLES; sample++) begin + data_o[sample] = { {REJ_SAMPLE_W-REJ_BUFFER_W{1'b0}} , rej_buffer[sample] }; + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/stimulus/tests/directed/rej_rand_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/stimulus/tests/directed/rej_rand_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..8b8623e433fc0138e7e1e30da2ef7f4a8e89369b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/stimulus/tests/directed/rej_rand_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: rej_rand_test +seed: 1 #${PLAYBOOK_RANDOM_SEED} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/tb/rej_sampler.py b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/tb/rej_sampler.py new file mode 100644 index 0000000000000000000000000000000000000000..74824c7a28093e89c807f9d85442d88767743ac9 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/tb/rej_sampler.py @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import sys +import os +import binascii +from hashlib import shake_128, shake_256 + +DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1 +DILITHIUM_N = 256 +DILITHIUM_LOGN = 8 +DILITHIUM_ROOT_OF_UNITY = 1753 + +## Category 5 parameters: +DILITHIUM_ETA = 2 +DILITHIUM_ETA_BOUND = 15 +DILITHIUM_TAU = 60 +DILITHIUM_GAMMA1 = 2**19 + + +class Shake(): + def __init__(self, algorithm, block_length): + self.algorithm = algorithm + self.block_length = block_length + self.read_blocks = 0 + self.read_data = b"" + + def absorb(self, input_bytes): + self.read_blocks = 0 + self.read_data = b"" + self.xof = self.algorithm(input_bytes) + + def digest(self, input_bytes, length): + return self.algorithm(input_bytes).digest(length) + + def get_n_blocks(self, n): + byte_count = self.block_length * (self.read_blocks + n) + xof_data = self.xof.digest(byte_count) + self.read_blocks += n + self.read_data = xof_data[-self.block_length*n:] + + def read(self, n): + if n > len(self.read_data): + self.get_n_blocks(5*n) + send = self.read_data[:n] + self.read_data = self.read_data[n:] + return send + +Shake128 = Shake(shake_128, 168) +Shake256 = Shake(shake_256, 136) + +def rejection_q(seed): + global DILITHIUM_Q + global DILITHIUM_N + global buff_arr + + def rejection_sample(xof): + global buff_arr + while True: + if (len(buff_arr) == 0): + log_file.write("squeezing\n") + buff_bytes = xof.read(168) + buff_arr = bytearray(buff_bytes) + buff_int = int.from_bytes(buff_bytes, "little") + input_vectors.write(f"{buff_int:0336x}") + j_bytes = buff_arr[0:3] + for i in range (3): + buff_arr.pop(0) + j = int.from_bytes(j_bytes, "little") + j &= 0x7FFFFF + if j < DILITHIUM_Q: + log_file.write("ack: " + f"{j:06x}" + "\n") + return j + log_file.write("rej: " + f"{j:06x}" + "\n") + + # Initialise the XOF + Shake128.absorb(seed) + buff_arr = bytearray() + coeffs = [rejection_sample(Shake128) for _ in range(DILITHIUM_N)] + input_vectors.write("\n") + log_file.write("\n") + return coeffs + +#open the input vector file for reading +input_seeds = open("input_seeds.txt", "r") +input_vectors = open("input_vectors.txt", "w") +exp_results = open("exp_results.txt", "w") +log_file = open("rej_sampler.log", "w") +Lines = input_seeds.readlines() + +for line in Lines: + Coeffs = rejection_q( bytes(line.strip(),'utf-8') ) + for coeff in Coeffs: + exp_results.write(f"{coeff:06x}"+" ") + exp_results.write("\n") diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/tb/rej_sampler_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/tb/rej_sampler_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..f5261f4c67d95728045102773f5935974f535575 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/rej_sampler/tb/rej_sampler_tb.sv @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// rej_sampler_tb.sv +// -------- +// +//====================================================================== + +import "DPI-C" function string getenv(input string env_name); + +module rej_sampler_tb + import mldsa_sampler_pkg::*; + import mldsa_params_pkg::*; +( +`ifdef VERILATOR + input bit clk_tb +`endif + ); + + parameter REJ_NUM_SAMPLERS = 5; + parameter REJ_SAMPLE_W = 24; + parameter REJ_VLD_SAMPLES = 4; + parameter PISO_BUFFER_W = 1440; + parameter PISO_INPUT_RATE = 1344; + parameter PISO_OUTPUT_RATE = 120; + parameter MLDSA_Q = 8380417; + parameter MLDSA_Q_WIDTH = $clog2(MLDSA_Q) + 1; + parameter MLDSA_N = 256; + + + `ifndef VERILATOR + int MAX_CYCLES; + int VEC_CNT; + + initial begin + // To use this from the command line, add "+MAX_CYCLES=" + // to override the sim timeout + if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin + $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES); + end else begin + MAX_CYCLES = 20_0000; + $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES); + end + if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin + $info("Received argument +VEC_CNT, with value %d", VEC_CNT); + end else begin + VEC_CNT = 10; + $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT); + end + end + `else + parameter MAX_CYCLES = 20_0000; + `endif + + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 5; + + //input data to piso + logic data_valid_i; + logic data_hold_o; + logic [PISO_INPUT_RATE-1:0] data_i; + + //input data + logic piso_valid; + logic piso_hold; + logic [REJ_NUM_SAMPLERS-1:0][REJ_SAMPLE_W-1:0] piso_data; + + //output data + logic data_valid_o; + logic [REJ_VLD_SAMPLES-1:0][MLDSA_Q_WIDTH-1:0] data_o; + + logic zeroize; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] vld_coeff_ctr; + reg [31 : 0] tc_ctr; + +`ifndef VERILATOR + reg clk_tb; +`endif + reg clk_i; + reg reset_n_tb; + reg rst_ni; + reg [31 : 0] read_data; + + assign clk_i = clk_tb; + assign rst_ni = reset_n_tb; + + logic [MLDSA_Q_WIDTH-1:0] exp_result; + logic [MLDSA_Q_WIDTH-1:0] expected_results[$]; // queue of results + + string seed_filename, vector_filename, exp_res_filename; + assign exp_res_filename = "exp_results.txt"; + assign seed_filename = "input_seeds.txt"; + assign vector_filename = "input_vectors.txt"; + + int fd_r_exp; + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + abr_piso #( + .PISO_BUFFER_W(PISO_BUFFER_W), + .PISO_INPUT_RATE(PISO_INPUT_RATE), + .PISO_OUTPUT_RATE(PISO_OUTPUT_RATE) + ) piso_i ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + .valid_i(data_valid_i), + .hold_o(data_hold_o), + .data_i(data_i), + .valid_o(piso_valid), + .hold_i(piso_hold), + .data_o(piso_data) + ); + + rej_sampler_ctrl#( + .REJ_NUM_SAMPLERS(REJ_NUM_SAMPLERS), + .REJ_SAMPLE_W(REJ_SAMPLE_W), + .REJ_VLD_SAMPLES(REJ_VLD_SAMPLES), + .REJ_VALUE(MLDSA_Q) + ) dut ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + //input data + .data_valid_i(piso_valid), + .data_hold_o(piso_hold), + .data_i(piso_data), + + //output data + .data_valid_o(data_valid_o), + .data_o(data_o) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- +`ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen +`endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + + // Test timeout monitor + if(cycle_ctr == MAX_CYCLES) begin + $error("Hit max cycle count (%0d) .. stopping",cycle_ctr); + $finish; + end + end + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + + repeat (2) @(posedge clk_tb); + + $display(""); + end + endtask // reset_dut + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + error_ctr = '0; + tc_ctr = '0; + vld_coeff_ctr = '0; +`ifndef VERILATOR + clk_tb = 0; +`endif + reset_n_tb = 0; + + zeroize = 0; + data_valid_i = '0; + data_i = '0; + + end + endtask // init_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + //---------------------------------------------------------------- + // Scoreboard + //---------------------------------------------------------------- + initial begin + forever begin + @(posedge clk_tb) + if (data_valid_o) begin + if (expected_results.size() >= 4) begin + for (int i = 0; i < REJ_VLD_SAMPLES; i++) begin + vld_coeff_ctr += 1; //increment vld coeff ctr + if (expected_results[0] != data_o[i]) begin + //ERROR + $display("[%t] Expected results mismatch for output index %d", $time, i); + $display("[%t] Actual: %x", $time,data_o[i]); + $display("[%t] Expected: %x", $time,expected_results[0]); + error_ctr += 1; + end + expected_results.pop_front(); + end + end else begin + //ERROR + $display("[%t] Not enough valid samples in the queue", $time); + error_ctr += 1; + end + end + end + + end + + initial begin + forever begin + @(posedge clk_tb) + if (vld_coeff_ctr == 256) begin + zeroize <= 1; + @(posedge clk_tb) + zeroize <= 0; + end + end + end + + initial begin + forever begin + @(posedge zeroize) + vld_coeff_ctr = '0; + expected_results = {}; + end + end + + //---------------------------------------------------------------- + // write_single_msg() + // + // Write the given msg to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_single_msg(logic [PISO_INPUT_RATE-1:0] rand_samples); + begin + data_valid_i <= 1; + data_i <= rand_samples; + + //don't like this, but solves the timing issue + @(posedge clk_tb); + //Make sure no hold + //drop this transaction if zeroize is set + while ((data_hold_o == 1) & (zeroize == 0)) @(posedge clk_tb); + + //@(posedge clk_tb); + data_valid_i <= 0; + data_i <= 'x; + + end + endtask // write_single_msg + + //---------------------------------------------------------------- + // gen_rand_test_vectors() + //---------------------------------------------------------------- + task gen_rand_test_vectors; + int fd_w; + + fd_w = $fopen(seed_filename, "a"); + if (fd_w == 0) $error("Cannot open file %s for writing", seed_filename); + + for (int i = 0; i < VEC_CNT; i++) begin + //Write random_ eeds + $fwrite(fd_w, "%0d \n", $urandom()); + end + $fclose(fd_w); + //generate input vectors and expected results + $system($sformatf("python rej_sampler.py")); + + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + endtask + + + //---------------------------------------------------------------- + // run_rand_test() + //---------------------------------------------------------------- + parameter PISO_INPUT_CHARS = PISO_INPUT_RATE/4; + parameter PISO_INPUT_DWORDS = PISO_INPUT_RATE/32; + task run_rand_test; + int fd_r_inp; + string line_read; + string line_substr; + int num_states; + logic [PISO_INPUT_DWORDS-1:0][31:0] test_data; + + //open input vectors + fd_r_inp = $fopen(vector_filename, "r"); + if (fd_r_inp == 0) begin + $error("Cannot open file %s for reading", vector_filename); + error_ctr++; + end + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + for (int iter = 0; iter < VEC_CNT; iter++) begin + //get the next exp result + if (!($fgets(line_read, fd_r_exp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + for (int res = 0; res < MLDSA_N; res++) begin + exp_result = line_read.substr(res*7, res*7 + 7-2).atohex(); + expected_results.push_back(exp_result); + end + + //get the next input vector + if (!($fgets(line_read, fd_r_inp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + + num_states = (line_read.len()/PISO_INPUT_CHARS); + //$display("Vector Length: %d", line_read.len()); + //$display("Number of states: %d", num_states); + for (int state = 0; state < num_states; state++) begin + line_substr = line_read.substr(state*PISO_INPUT_CHARS , (state*PISO_INPUT_CHARS)+PISO_INPUT_CHARS-1); + //$display("State: %s", line_substr); + for (int dword = 0; dword < PISO_INPUT_DWORDS; dword++) begin + test_data[dword] = line_substr.substr((PISO_INPUT_CHARS - dword*8 - 8), (PISO_INPUT_CHARS - dword*8 - 1)).atohex(); + //$display("Dword: %d - %h", dword, test_data[dword]); + end + write_single_msg(test_data); + end + + wait (zeroize == 1); + wait (zeroize == 0); + + tc_ctr++; + + end + + $fclose(fd_r_inp); + + endtask // run_hw_if_test + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + + initial + begin : main + $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED")); + $display(" -- Testbench for REJ_SAMPLER started --"); + + init_sim(); + reset_dut(); + + gen_rand_test_vectors(); + run_rand_test(); + + @(posedge clk_tb); + display_test_result(); + + $display(" -- Testbench for REJ_SAMPLER done. --"); + $finish; + end // main + +endmodule // rej_sampler_tb + +//====================================================================== +// EOF rej_sampler_tb.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..df8a8aebd8a0866374a3de447f203fe4263a0f1f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/compile.yml @@ -0,0 +1,52 @@ +--- +provides: [sample_in_ball_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sample_in_ball_pkg.sv + - $COMPILE_ROOT/rtl/sib_mem.sv + tb: + directories: + - $COMPILE_ROOT/rtl + files: + - $COMPILE_ROOT/rtl/sample_in_ball_pkg.sv + - $COMPILE_ROOT/rtl/sib_mem.sv +--- +provides: [sample_in_ball] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - sample_in_ball_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sample_in_ball_ctrl.sv + - $COMPILE_ROOT/rtl/sample_in_ball_shuffler.sv + - $COMPILE_ROOT/rtl/sample_in_ball.sv + tops: [sample_in_ball_ctrl] +--- +provides: [sample_in_ball_tb] +schema_version: 2.4.0 +requires: + - sample_in_ball + - mldsa_sampler_pkg +targets: + tb: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/sample_in_ball_tb.sv + tops: [sample_in_ball_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying ref model to ${pwd}" && cp $COMPILE_ROOT/tb/sample_in_ball.py .' +global: + tool: + vcs: + default: + - '-assert svaext' + - +define+ABR_ASSERT_ON + - '-noinherit_timescale=1ns/1ps' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball.vf new file mode 100644 index 0000000000000000000000000000000000000000..1335f3d06a0cea0b2ce71407d0f779902ae752de --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball.vf @@ -0,0 +1,38 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..2ffa3146121bc7fd00ec5790f6a4baa50a7ee469 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball_pkg.vf @@ -0,0 +1,4 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..d587627c619af3f0f6a24e2f64bb25bfccd434d0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/config/sample_in_ball_tb.vf @@ -0,0 +1,43 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sample_in_ball/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sib_mem.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/tb/sample_in_ball_tb.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv +${ADAMSBRIDGE_ROOT}/src/sample_in_ball/rtl/sample_in_ball.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball.sv new file mode 100644 index 0000000000000000000000000000000000000000..a9bb9978ac122b71ca8bce02b8fbb1344257f3d3 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball.sv @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either sibress or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Sample In Ball function tests each sample for validitiy +//Valid samples must be <= rej_value_i + +module sample_in_ball + // import ::*; + #( + parameter SIB_SAMPLE_W = 8 + ) + ( + //input data + input logic valid_i, + input logic [SIB_SAMPLE_W-1:0] data_i, + input logic [SIB_SAMPLE_W-1:0] rej_value_i, + + //output data + output logic valid_o + + ); + + always_comb valid_o = valid_i & (data_i <= rej_value_i); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..b9e252e46e8d85207a2e43f3e973d51339f907a6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_ctrl.sv @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either sibress or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + + +module sample_in_ball_ctrl + import sib_pkg::*; + import mldsa_params_pkg::*; + #( + parameter SIB_NUM_SAMPLERS = 4 + ,parameter SIB_SAMPLE_W = 8 + ,parameter SIB_TAU = 60 + ,parameter SIB_NUM_COEFF = 256 + ,localparam MLDSA_Q_WIDTH = $clog2(8380417) + ) + ( + input logic clk, + input logic rst_b, + input logic zeroize, + + //input data + input logic data_valid_i, + output logic data_hold_o, + input logic [SIB_NUM_SAMPLERS-1:0][SIB_SAMPLE_W-1:0] data_i, + output logic sib_done_o, + + //memory if + output logic [1:0] cs_o, + output logic [1:0] we_o, + output logic [1:0][7:2] addr_o, + output logic [1:0][3:0][MLDSA_Q_WIDTH-1:0] wrdata_o, + input logic [1:0][3:0][MLDSA_Q_WIDTH-1:0] rddata_i + + ); + localparam SIB_NUM_DATA_BITS = $bits(data_i); + + sib_fsm_state_e sib_fsm_ns; + sib_fsm_state_e sib_fsm_ps; + + logic last_sample; + + logic [SIB_TAU-1:0] sign_buffer, sign_buffer_d; + logic [(SIB_NUM_DATA_BITS*2)-1:0] sign_buffer_nxt; + logic sign_buffer_en; + logic sign_buffer_ph; + + logic [SIB_SAMPLE_W-1:0] rej_value; + logic rej_value_en; + + logic [SIB_NUM_SAMPLERS-1:0] sampler_valid; + logic sampler_hold; + + logic index_found; + logic [$clog2(SIB_NUM_SAMPLERS)-1:0] valid_index; + logic [SIB_SAMPLE_W-1:0] valid_sample; + logic [SIB_NUM_SAMPLERS-1:0] sampler_mask, sampler_mask_d; + logic sampler_mask_en; + logic sampler_mask_clear; + logic shuffler_valid; + + logic shuffler_hold; + + //FSM Controller + always_comb begin : sib_fsm_state_combo + //default loopback assignment + sib_fsm_ns = sib_fsm_ps; + unique case (sib_fsm_ps) + SIB_IDLE: begin + if (data_valid_i) sib_fsm_ns = SIB_SIGN_BUFFER; + end + SIB_SIGN_BUFFER: begin + if (data_valid_i) sib_fsm_ns = SIB_ACTIVE; + end + SIB_ACTIVE: begin + if (last_sample) sib_fsm_ns = SIB_DONE; + end + SIB_DONE: begin + sib_fsm_ns = sib_fsm_ps; + end + //ERROR + default: begin + sib_fsm_ns = SIB_IDLE; + end + endcase + end + + always_comb begin : sib_fsm_output_combo + data_hold_o = 0; + sign_buffer_en = 0; + sign_buffer_ph = 0; + rej_value_en = 0; + sampler_mask_en = 0; + sampler_mask_clear = 0; + shuffler_valid = 0; + sib_done_o = 0; + unique case (sib_fsm_ps) + SIB_IDLE: begin + sign_buffer_en = data_valid_i; + sign_buffer_ph = 0; + end + SIB_SIGN_BUFFER: begin + sign_buffer_en = data_valid_i; + sign_buffer_ph = 1; + end + SIB_ACTIVE: begin + data_hold_o = sampler_hold | shuffler_hold; + shuffler_valid = index_found; + rej_value_en = index_found & ~shuffler_hold; + sampler_mask_en = index_found & sampler_hold & ~shuffler_hold; + sampler_mask_clear = ~index_found | ~data_hold_o; + end + SIB_DONE: begin + sib_done_o = 1; + end + //ERROR + default: begin + data_hold_o = 1; + end + endcase + end + + always_ff @(posedge clk or negedge rst_b) begin : sib_fsm_state_reg + if (!rst_b) sib_fsm_ps <= SIB_IDLE; + else if (zeroize) sib_fsm_ps <= SIB_IDLE; + else sib_fsm_ps <= sib_fsm_ns; + end + + //Sign buffer + //Gather TAU bits of sign data over TAU/(SIB_NUM_SAMPLERS*SIB_SAMPLE_W) clocks + always_comb sign_buffer_nxt = sign_buffer_ph ? {data_i, {SIB_NUM_DATA_BITS{1'b0}}} : {{SIB_NUM_DATA_BITS{1'b0}}, data_i}; + always_comb sign_buffer_d = sign_buffer | sign_buffer_nxt[SIB_TAU-1:0]; + + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b)begin + sign_buffer <= '0; + end else if (zeroize) begin + sign_buffer <= '0; + end else if (sib_done_o) begin + sign_buffer <= '0; + end else if (sign_buffer_en) begin + sign_buffer <= sign_buffer_d; + end else if (rej_value_en) begin + sign_buffer <= SIB_TAU'(sign_buffer >> 1); + end else begin + sign_buffer <= sign_buffer; + end + end + + //Initialize rejection value to 256 - TAU + //Increment the rejection value whenever a valid sample is found + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b) begin + rej_value <= SIB_NUM_COEFF - SIB_TAU; + end else if (zeroize) begin + rej_value <= SIB_NUM_COEFF - SIB_TAU; + end else if (sib_done_o) begin + rej_value <= SIB_NUM_COEFF - SIB_TAU; + end else if (rej_value_en) begin + rej_value <= rej_value + 1'b1; + end else begin + rej_value <= rej_value; + end + end + + //Find first valid sample + always_comb begin + index_found = 0; + valid_index = 0; + sampler_mask_d = sampler_mask; + for (int i = 0; i < SIB_NUM_SAMPLERS; i++) begin + if (data_valid_i & ~index_found) begin + sampler_mask_d[i] = 0; + if (sampler_valid[i]) begin + index_found = 1; + valid_index = i[$clog2(SIB_NUM_SAMPLERS)-1:0]; + end + end + end + end + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b)begin + sampler_mask <= '1; + end else if (zeroize | sampler_mask_clear) begin + sampler_mask <= '1; + end else if (sampler_mask_en) begin + sampler_mask <= sampler_mask_d; + end else begin + sampler_mask <= sampler_mask; + end + end + + //sample in ball is done when we collect TAU samples (rej value is 255) + always_comb last_sample = (&rej_value) & shuffler_valid & ~shuffler_hold; + always_comb valid_sample = data_i[valid_index]; + + generate + for (genvar inst_g = 0; inst_g < SIB_NUM_SAMPLERS; inst_g++) begin : sample_in_ball_inst + sample_in_ball #( + .SIB_SAMPLE_W(SIB_SAMPLE_W) + ) sample_in_ball_i ( + .valid_i(sampler_mask[inst_g]), + .data_i(data_i[inst_g]), + .rej_value_i(rej_value), + .valid_o(sampler_valid[inst_g]) + ); + end + endgenerate + + always_comb sampler_hold = index_found & (valid_index != (SIB_NUM_SAMPLERS-1)); + + //Shuffler + sample_in_ball_shuffler #( + .SIB_SAMPLE_W(SIB_SAMPLE_W) + ) sib_shuffler_i ( + .clk(clk), + .rst_b(rst_b), + .zeroize(zeroize), + + .valid_i(shuffler_valid), + .hold_o(shuffler_hold), + .indexi_i(rej_value), + .indexj_i(valid_sample), + .sign_i(sign_buffer[0]), + + //memory if + .cs_o(cs_o), + .we_o(we_o), + .addr_o(addr_o), + .wrdata_o(wrdata_o), + .rddata_i(rddata_i) + ); + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..5ac7efd36e929d47b0a176db7f4f0504610a09a0 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_pkg.sv @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +`ifndef ABR_SIB_PKG +`define ABR_SIB_PKG + +package sib_pkg; + + typedef enum logic [1:0] { + SIB_IDLE = 2'b00, + SIB_SIGN_BUFFER = 2'b01, + SIB_ACTIVE = 2'b10, + SIB_DONE = 2'b11 +} sib_fsm_state_e; + +endpackage +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv new file mode 100644 index 0000000000000000000000000000000000000000..36b80a4a72047a376e8a83a1f3810b2deeec1942 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sample_in_ball_shuffler.sv @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either sibress or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +//Sample In Ball Shuffler takes in two indexes (i and j) and a sign bit +//Indexes are used to address a 256 coefficient memory +//The value found in Index j is moved to Index i +//For sign value of 1, the value Q-1 is written to Index j, else 1 is written to Index j + +module sample_in_ball_shuffler + import mldsa_params_pkg::*; + #( + parameter SIB_SAMPLE_W = 8 + ) + ( + input logic clk, + input logic rst_b, + input logic zeroize, + //input data + input logic valid_i, + output logic hold_o, + input logic [SIB_SAMPLE_W-1:0] indexi_i, + input logic [SIB_SAMPLE_W-1:0] indexj_i, + input logic sign_i, + + //memory if + output logic [1:0] cs_o, + output logic [1:0] we_o, + output logic [1:0][7:2] addr_o, + output logic [1:0][3:0][MLDSA_Q_WIDTH-2:0] wrdata_o, + input logic [1:0][3:0][MLDSA_Q_WIDTH-2:0] rddata_i + + ); + + logic read_valid; + logic addr_match; + logic [MLDSA_Q_WIDTH-2:0] nxt_i, nxt_j; + logic [3:0][MLDSA_Q_WIDTH-2:0] wrdata_pre; + + //hold the first phase + always_comb hold_o = valid_i & ~read_valid; + + //Read phase + //Read from entry pointed to by indexi_i and indexj_i + always_comb addr_o[0] = indexj_i[7:2]; + always_comb addr_o[1] = indexi_i[7:2]; + + always_ff @(posedge clk or negedge rst_b) begin + if (!rst_b)begin + read_valid <= 0; + end else if (zeroize) begin + read_valid <= 0; + end else if (valid_i & ~read_valid) begin + read_valid <= 1; + end else begin + read_valid <= 0; + end + end + + always_comb addr_match = indexi_i[7:2] == indexj_i[7:2]; + + //Assign the nxt j value (contents of i, modified by sign bit) + always_comb nxt_j = sign_i ? MLDSA_Q-1 : 1; + + //Write nxt_j into indexj_i location + always_comb begin + unique case (indexj_i[1:0]) + 2'b00: wrdata_o[0] = {rddata_i[0][3],rddata_i[0][2],rddata_i[0][1],nxt_j }; + 2'b01: wrdata_o[0] = {rddata_i[0][3],rddata_i[0][2],nxt_j ,rddata_i[0][0]}; + 2'b10: wrdata_o[0] = {rddata_i[0][3],nxt_j ,rddata_i[0][1],rddata_i[0][0]}; + 2'b11: wrdata_o[0] = {nxt_j ,rddata_i[0][2],rddata_i[0][1],rddata_i[0][0]}; + default: wrdata_o[0] = 'x; + endcase + end + + //Assign the nxt i value (contents of j) + always_comb nxt_i = rddata_i[0][indexj_i[1:0]]; + + //Write nxt_i into indexi_i location + always_comb begin + unique case ({indexi_i[1:0]}) + 2'b00: wrdata_pre = {rddata_i[1][3],rddata_i[1][2],rddata_i[1][1],nxt_i }; + 2'b01: wrdata_pre = {rddata_i[1][3],rddata_i[1][2],nxt_i ,rddata_i[1][0]}; + 2'b10: wrdata_pre = {rddata_i[1][3],nxt_i ,rddata_i[1][1],rddata_i[1][0]}; + 2'b11: wrdata_pre = {nxt_i ,rddata_i[1][2],rddata_i[1][1],rddata_i[1][0]}; + default: wrdata_pre = 'x; + endcase + end + + //If addr match, write nxt_j on same write port + always_comb begin + unique casez ({addr_match, indexj_i[1:0]}) + 3'b0_??: wrdata_o[1] = wrdata_pre; + 3'b1_00: wrdata_o[1] = {wrdata_pre[3],wrdata_pre[2],wrdata_pre[1],nxt_j }; + 3'b1_01: wrdata_o[1] = {wrdata_pre[3],wrdata_pre[2],nxt_j ,wrdata_pre[0]}; + 3'b1_10: wrdata_o[1] = {wrdata_pre[3],nxt_j ,wrdata_pre[1],wrdata_pre[0]}; + 3'b1_11: wrdata_o[1] = {nxt_j ,wrdata_pre[2],wrdata_pre[1],wrdata_pre[0]}; + default: wrdata_o[1] = 'x; + endcase + end + + always_comb cs_o = {2{valid_i}}; + always_comb we_o[0] = read_valid & ~addr_match; + always_comb we_o[1] = read_valid; + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sib_mem.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sib_mem.sv new file mode 100644 index 0000000000000000000000000000000000000000..b0ae102850cc775ee70385add0cec6ab91744976 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/rtl/sib_mem.sv @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module sib_mem #( + parameter DEPTH = 64 + ,parameter NUM_PORTS = 1 + ,parameter DATA_WIDTH = 32 + ,parameter ADDR_WIDTH = $clog2(DEPTH) + + ) + ( + input logic clk_i, + input logic rst_b, + input logic zeroize, + + input logic [NUM_PORTS-1:0] cs_i, + input logic [NUM_PORTS-1:0] we_i, + input logic [NUM_PORTS-1:0][ADDR_WIDTH-1:0] addr_i, + input logic [NUM_PORTS-1:0][DATA_WIDTH-1:0] wdata_i, + output logic [NUM_PORTS-1:0][DATA_WIDTH-1:0] rdata_o + ); + + //storage element + logic [DEPTH-1:0][DATA_WIDTH-1:0] mem; + + always @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + mem <= '0; + end + else if (zeroize) begin + mem <= '0; + end else begin + for (int port = 0; port < NUM_PORTS; port++) begin + if (cs_i[port] & we_i[port]) begin + mem[addr_i[port]] <= wdata_i[port]; + end + end + end + end + + always @(posedge clk_i or negedge rst_b) begin + if (!rst_b) begin + rdata_o <= '0; + end + else if (zeroize) begin + rdata_o <= '0; + end else begin + for (int port = 0; port < NUM_PORTS; port++) begin + if (cs_i[port] & ~we_i[port]) begin + rdata_o[port] <= mem[addr_i[port]]; + end + end + end + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/stimulus/tests/directed/sib_rand_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/stimulus/tests/directed/sib_rand_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..a11a72f191c15eb2324164aa1023a230b1f87b63 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/stimulus/tests/directed/sib_rand_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: sib_rand_test +seed: ${PLAYBOOK_RANDOM_SEED} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/tb/sample_in_ball.py b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/tb/sample_in_ball.py new file mode 100644 index 0000000000000000000000000000000000000000..56805a95831a7ea377f3b776b4f6df056ad7ab72 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/tb/sample_in_ball.py @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import sys +import os +import binascii +from hashlib import shake_128, shake_256 + +DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1 +DILITHIUM_N = 256 +DILITHIUM_LOGN = 8 +DILITHIUM_ROOT_OF_UNITY = 1753 + +## Category 5 parameters: +DILITHIUM_ETA = 2 +DILITHIUM_ETA_BOUND = 15 +DILITHIUM_TAU = 60 +DILITHIUM_GAMMA1 = 2**19 + + +class Shake(): + def __init__(self, algorithm, block_length): + self.algorithm = algorithm + self.block_length = block_length + self.read_blocks = 0 + self.read_data = b"" + + def absorb(self, input_bytes): + self.read_blocks = 0 + self.read_data = b"" + self.xof = self.algorithm(input_bytes) + + def digest(self, input_bytes, length): + return self.algorithm(input_bytes).digest(length) + + def get_n_blocks(self, n): + byte_count = self.block_length * (self.read_blocks + n) + xof_data = self.xof.digest(byte_count) + self.read_blocks += n + self.read_data = xof_data[-self.block_length*n:] + + def read(self, n): + if n > len(self.read_data): + self.get_n_blocks(5*n) + send = self.read_data[:n] + self.read_data = self.read_data[n:] + return send + +Shake128 = Shake(shake_128, 168) +Shake256 = Shake(shake_256, 136) + +def sample_in_ball(seed): + global DILITHIUM_Q + global DILITHIUM_N + global DILITHIUM_TAU + global buff_bytes + global buff_arr + + def rejection_sample(i): + global buff_bytes + global buff_arr + while True: + if (len(buff_arr) == 0): + buff_bytes = Shake256.read(136) + buff_arr = bytearray(buff_bytes) + buff_int = int.from_bytes(buff_bytes, "little") + input_vectors.write(f"{buff_int:0272x}") + j = buff_arr[0] + buff_arr.pop(0) + if j <= i: + log_file.write("ack - i: " + f"{i:02x}" + " j: " + f"{j:02x}" + "\n") + return j + log_file.write("rej - i: " + f"{i:02x}" + " j: " + f"{j:02x}" + "\n") + + # Initialise the XOF + Shake256.absorb(seed) + + # Set the first 8 bytes for the sign, and leave the rest for + # sampling. + buff_bytes = Shake256.read(136) + buff_arr = bytearray(buff_bytes) + buff_int = int.from_bytes(buff_bytes, "little") + input_vectors.write(f"{buff_int:0272x}") + sign_bytes = buff_arr[0:8] + sign_int = int.from_bytes(sign_bytes, "little") + sign_int_big = int.from_bytes(sign_bytes, "little") + log_file.write("sign: " + f"{sign_int_big:016x}" + "\n") + for i in range (8): + buff_arr.pop(0) + + # Set the list of coeffs to be 0 + coeffs = [0 for _ in range(DILITHIUM_N)] + + # Now set tau values of coeffs to be +/-1 + for i in range(DILITHIUM_N - DILITHIUM_TAU, DILITHIUM_N): + j = rejection_sample(i) + coeffs[i] = coeffs[j] + coeffs[j] = (1 - 2*(sign_int & 1)) % DILITHIUM_Q + log_file.write("sign: " + f"{(sign_int & 1):x}" + "\n") + sign_int >>= 1 + + input_vectors.write("\n") + return coeffs + +#open the input vector file for reading +input_seeds = open("input_seeds.txt", "r") +input_vectors = open("input_vectors.txt", "w") +exp_results = open("exp_results.txt", "w") +log_file = open("sib.log", "w") +Lines = input_seeds.readlines() + +for line in Lines: + Coeffs = sample_in_ball( bytes(line.strip(),'utf-8') ) + for coeff in Coeffs: + exp_results.write(f"{coeff:06x}"+" ") + exp_results.write("\n") + + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/tb/sample_in_ball_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/tb/sample_in_ball_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..7c2f2179f8838e15a6393f994fdc14d9fe7c3965 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sample_in_ball/tb/sample_in_ball_tb.sv @@ -0,0 +1,448 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either sibress or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// sample_in_ball_tb.sv +// -------- +// +//====================================================================== + +import "DPI-C" function string getenv(input string env_name); + +module sample_in_ball_tb + import sampler_pkg::*; + import mldsa_params_pkg::*; +( +`ifdef VERILATOR + input bit clk_tb +`endif + ); + + `ifndef VERILATOR + int MAX_CYCLES; + int VEC_CNT; + + initial begin + // To use this from the command line, add "+MAX_CYCLES=" + // to override the sim timeout + if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin + $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES); + end else begin + MAX_CYCLES = 20_0000; + $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES); + end + if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin + $info("Received argument +VEC_CNT, with value %d", VEC_CNT); + end else begin + VEC_CNT = 10; + $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT); + end + end + `else + parameter MAX_CYCLES = 20_0000; + `endif + + parameter DEBUG = 0; + + parameter CLK_HALF_PERIOD = 5; + + //input data to piso + logic data_valid_i; + logic data_hold_o; + logic [SIB_PISO_INPUT_RATE-1:0] data_i; + + //input data to sample in ball + logic piso_valid; + logic piso_hold; + logic [SIB_NUM_SAMPLERS-1:0][SIB_SAMPLE_W-1:0] piso_data; + + logic sib_done; + //memory if + logic [1:0] cs; + logic [1:0] we; + logic [1:0][7:2] addr; + logic [1:0][3:0][MLDSA_Q_WIDTH-2:0] wrdata; + logic [1:0][3:0][MLDSA_Q_WIDTH-2:0] rddata; + + logic zeroize; + + string seed_filename, vector_filename, exp_res_filename; + assign exp_res_filename = "exp_results.txt"; + assign seed_filename = "input_seeds.txt"; + assign vector_filename = "input_vectors.txt"; + + int fd_r_exp; + + //---------------------------------------------------------------- + // Register and Wire declarations. + //---------------------------------------------------------------- + reg [31 : 0] cycle_ctr; + reg [31 : 0] error_ctr; + reg [31 : 0] vld_coeff_ctr; + reg [31 : 0] tc_ctr; + +`ifndef VERILATOR + reg clk_tb; +`endif + reg clk_i; + reg reset_n_tb; + reg rst_ni; + + assign clk_i = clk_tb; + assign rst_ni = reset_n_tb; + + //SRAM + sib_mem + #( + .DATA_WIDTH((MLDSA_Q_WIDTH-1)*4), + .DEPTH (MLDSA_N/4 ), + .NUM_PORTS (2 ) + ) + sib_mem_inst + ( + .clk_i(clk_i), + .zeroize(zeroize), + + .cs_i(cs), + .we_i(we), + .addr_i(addr), + .wdata_i(wrdata), + + .rdata_o(rddata) + ); + + //---------------------------------------------------------------- + // Device Under Test. + //---------------------------------------------------------------- + abr_piso #( + .PISO_BUFFER_W(SIB_PISO_BUFFER_W), + .PISO_INPUT_RATE(SIB_PISO_INPUT_RATE), + .PISO_OUTPUT_RATE(SIB_PISO_OUTPUT_RATE) + ) piso_i ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + .valid_i(data_valid_i), + .hold_o(data_hold_o), + .data_i(data_i), + .valid_o(piso_valid), + .hold_i(piso_hold), + .data_o(piso_data) + ); + + sample_in_ball_ctrl #( + .SIB_NUM_SAMPLERS(SIB_NUM_SAMPLERS), + .SIB_SAMPLE_W(SIB_SAMPLE_W), + .SIB_TAU(SIB_TAU) + ) dut ( + .clk(clk_i), + .rst_b(rst_ni), + .zeroize(zeroize), + //input data + .data_valid_i(piso_valid), + .data_hold_o(piso_hold), + .data_i(piso_data), + .sib_done_o(sib_done), + + //memory_if + .cs_o(cs), + .we_o(we), + .addr_o(addr), + .wrdata_o(wrdata), + .rddata_i(rddata) + ); + + //---------------------------------------------------------------- + // clk_gen + // + // Clock generator process. + //---------------------------------------------------------------- +`ifndef VERILATOR + always + begin : clk_gen + #CLK_HALF_PERIOD + clk_tb = !clk_tb; + end // clk_gen +`endif + + //---------------------------------------------------------------- + // sys_monitor + // + // Generates a cycle counter and displays information about + // the dut as needed. + //---------------------------------------------------------------- + always @(posedge clk_tb) begin : sys_monitor + cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1; + + // Test timeout monitor + if(cycle_ctr == MAX_CYCLES) begin + $error("Hit max cycle count (%0d) .. stopping",cycle_ctr); + $finish; + end + end + + //---------------------------------------------------------------- + // reset_dut() + // + // Toggles reset to force the DUT into a well defined state. + //---------------------------------------------------------------- + task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + zeroize = 0; + + repeat (2) @(posedge clk_tb); + reset_n_tb = 1; + zeroize = 1; + + repeat (1) @(posedge clk_tb); + zeroize = 0; + + $display(""); + end + endtask // reset_dut + + //---------------------------------------------------------------- + // init_sim() + // + // Initialize all counters and testbed functionality as well + // as setting the DUT inputs to defined values. + //---------------------------------------------------------------- + task init_sim; + begin + error_ctr = '0; + tc_ctr = '0; + vld_coeff_ctr = '0; +`ifndef VERILATOR + clk_tb = 0; +`endif + reset_n_tb = 0; + + zeroize = 0; + data_valid_i = '0; + data_i = '0; + + end + endtask // init_dut + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All %02d test cases completed successfully.", tc_ctr); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d test cases completed.", tc_ctr); + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + + task clear_sram; + // Variables + bit [6:0] clear_addr; + int byt; + + // Slam + $display("SRAM clear from %h to %h", 0, MLDSA_N/4); + for (clear_addr = 0; clear_addr < (MLDSA_N/4); clear_addr++) begin + sib_mem_inst.mem[clear_addr[5:0]] = '0; + end + $display("SRAM clear completed"); + endtask + + //---------------------------------------------------------------- + // Scoreboard + //---------------------------------------------------------------- + + initial begin + string exp_res_read; + + logic [MLDSA_Q_WIDTH-2:0] exp_result; + logic [3:0][MLDSA_Q_WIDTH-2:0] actual_result; + + + forever begin + @(posedge clk_tb) + if (sib_done & ~zeroize) begin + //get the next exp result + if (!($fgets(exp_res_read, fd_r_exp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + //check each coefficient + for (int coeff = 0; coeff < MLDSA_N; coeff++) begin + //parse line for expected result + exp_result = exp_res_read.substr(coeff*7, coeff*7+6).atohex(); + + actual_result = sib_mem_inst.mem[coeff/4]; + + if (exp_result != actual_result[coeff%4]) begin + //ERROR + $display("[%t] Expected results mismatch", $time); + $display("[%t] Coefficient entry: %x", $time, coeff); + $display("[%t] Actual: %x", $time,actual_result[coeff%4]); + $display("[%t] Expected: %x", $time,exp_result); + error_ctr += 1; + end + end + end + end + $fclose(fd_r_exp); + end + + + + initial begin + forever begin + @(posedge clk_tb) + if (sib_done == 1) begin + zeroize <= 1; + @(posedge clk_tb) + zeroize <= 0; + end + end + end + + + //---------------------------------------------------------------- + // write_single_msg() + // + // Write the given msg to the DUT using the DUT interface. + //---------------------------------------------------------------- + task write_single_msg(logic [SIB_PISO_INPUT_RATE-1:0] rand_samples); + begin + data_valid_i <= 1; + data_i <= rand_samples; + + //don't like this, but solves the timing issue + @(posedge clk_tb); + //Make sure no hold + //drop this transaction if zeroize is set + while ((data_hold_o == 1) & (zeroize == 0)) @(posedge clk_tb); + + //@(posedge clk_tb); + data_valid_i <= 0; + data_i <= 'x; + + end + endtask // write_single_msg + + //---------------------------------------------------------------- + // gen_rand_test_vectors() + //---------------------------------------------------------------- + task gen_rand_test_vectors; + int fd_w; + + fd_w = $fopen(seed_filename, "a"); + if (fd_w == 0) $error("Cannot open file %s for writing", seed_filename); + + for (int i = 0; i < VEC_CNT; i++) begin + //Write random_ eeds + $fwrite(fd_w, "%0d \n", $urandom()); + end + $fclose(fd_w); + //generate input vectors and expected results + $system($sformatf("python sample_in_ball.py")); + + + //open expected results files + fd_r_exp = $fopen(exp_res_filename, "r"); + if (fd_r_exp == 0) begin + $error("Cannot open file %s for reading", exp_res_filename); + error_ctr++; + end + + endtask + + //---------------------------------------------------------------- + // run_rand_test() + //---------------------------------------------------------------- + parameter PISO_INPUT_CHARS = SIB_PISO_INPUT_RATE/4; + parameter PISO_INPUT_DWORDS = SIB_PISO_INPUT_RATE/32; + task run_rand_test; + int fd_r_inp; + string line_read; + string line_substr; + logic [PISO_INPUT_DWORDS-1:0][31:0] test_data; + + //open input vectors + fd_r_inp = $fopen(vector_filename, "r"); + if (fd_r_inp == 0) begin + $error("Cannot open file %s for reading", vector_filename); + error_ctr++; + end + + for (int iter = 0; iter < VEC_CNT; iter++) begin + + //get the next input vector + if (!($fgets(line_read, fd_r_inp))) begin + $error("Failed to read a new line"); + error_ctr++; + end + + + for (int dword = 0; dword < PISO_INPUT_DWORDS; dword++) begin + test_data[dword] = line_read.substr((PISO_INPUT_CHARS - dword*8 - 8), (PISO_INPUT_CHARS - 1 - dword*8)).atohex(); + end + write_single_msg(test_data); + + + wait (sib_done == 1); + wait (sib_done == 0); + + tc_ctr++; + end + + $fclose(fd_r_inp); + + endtask // run_hw_if_test + + //---------------------------------------------------------------- + // The main test functionality. + //---------------------------------------------------------------- + + initial + begin : main + $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED")); + $display(" -- Testbench for SAMPLE_IN_BALL started --"); + + init_sim(); + reset_dut(); + + gen_rand_test_vectors(); + run_rand_test(); + + @(posedge clk_tb); + display_test_result(); + + $display(" -- Testbench for SAMPLE_IN_BALL done. --"); + $finish; + end // main + +endmodule // sample_in_ball_tb + +//====================================================================== +// EOF sample_in_ball_tb.sv +//====================================================================== diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..93430d87b760e61058a87e27fb14ef127ff14fa6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/compile.yml @@ -0,0 +1,48 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [sigdecode_z_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sigdecode_z_defines_pkg.sv +--- +provides: [sigdecode_z] +schema_version: 2.4.0 +requires: + - mldsa_defines + - sigdecode_z_pkg + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sigdecode_z_top.sv + - $COMPILE_ROOT/rtl/sigdecode_z_unit.sv + - $COMPILE_ROOT/rtl/sigdecode_z_defines_pkg.sv + + tops: [sigdecode_z_top] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/sig_decode_z/config/design_lint/sig_decode_z/sglint_waivers +--- +provides: [sigdecode_z_tb] +schema_version: 2.4.0 +requires: + - sigdecode_z + - sigdecode_z_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/sigdecode_z_tb.sv + tops: [sigdecode_z_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying s1 bytes hex to $PWD" && cp $COMPILE_ROOT/tb/polyz_unpack.py .' \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/design_lint/sig_decode_z/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/design_lint/sig_decode_z/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z.vf new file mode 100644 index 0000000000000000000000000000000000000000..b8600120599418d70980193555bb5e8a5df87367 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z.vf @@ -0,0 +1,37 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..f2d1d6dfb96f81165150060c66e0a2d707d32478 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..ba1a12792e13f5a1ba7611b242eaf13afe8f4a36 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/config/sigdecode_z_tb.vf @@ -0,0 +1,38 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_decode_z/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/rtl/sigdecode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sig_decode_z/tb/sigdecode_z_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..110ce77bfdba3539bc980366701b2a39732c9f4f --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_defines_pkg.sv @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigdecode_z_defines_pkg.sv +// -------- +// Sigdecode parameters for Mldsa +//====================================================================== + +`ifndef MLDSA_SIGDECODE_Z_DEFINES +`define MLDSA_SIGDECODE_Z_DEFINES + +package sigdecode_z_defines_pkg; + import mldsa_params_pkg::*; + + parameter API_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH; + parameter MLDSA_L = 7; + + typedef struct packed { + mem_rw_mode_e rd_wr_en; + logic [API_ADDR_WIDTH-1:0] addr; + } sig_mem_if_t; + +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..4d7f7afb6bf5015d9e20bab8100e3b4df88cdf66 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_top.sv @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigdecode_z_top.sv +// -------- +// @brief Top-level module for the signature decoder for z in the Mldsa scheme. +// +// This module implements the top-level logic for encoding z polynomial (a part of signature) in the +// Mldsa post-quantum cryptographic scheme. The decoder reads encoded byte string from API register, +// processes them through decoding units, and writes the decoded values to a specified +// memory locations starting from the dest address. +// The module interfaces with memory through two parallel read ports and writes the +// decoded data to a destination address in the memory. +// +//====================================================================== + +module sigdecode_z_top + import mldsa_params_pkg::*; + import sigdecode_z_defines_pkg::*; + #( + parameter MEM_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH, + parameter REG_SIZE = 24, + parameter GAMMA1 = 19 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + // Output memory ports + input wire [MEM_ADDR_WIDTH-1:0] dest_base_addr, + output mem_if_t mem_a_wr_req, + output mem_if_t mem_b_wr_req, + output logic [3:0][REG_SIZE-1:0] mem_a_wr_data, + output logic [3:0][REG_SIZE-1:0] mem_b_wr_data, + + // Input API ports + input wire [MEM_ADDR_WIDTH-1:0] sigmem_src_base_addr, + output sig_mem_if_t sigmem_a_rd_req, + output sig_mem_if_t sigmem_b_rd_req, + input wire [3:0][GAMMA1:0] sigmem_a_rd_data, + input wire [3:0][GAMMA1:0] sigmem_b_rd_data, + + //Control and status signals + input wire sigdecode_z_enable, + output logic sigdecode_z_done + ); + + localparam THE_LAST_ADDR = ((MLDSA_L * MLDSA_N)/4)-1; + // State Machine States + localparam IDLE = 3'b000, + READ = 3'b001, + READ_and_EXEC = 3'b010, + READ_EXEC_and_WRITE = 3'b011, + EXEC_and_WRITE = 3'b100, + WRITE = 3'b101, + DONE = 3'b110; + + + logic [31:0] num_mem_operands, num_api_operands; // encoded each four coeff will increment these by one + logic [MEM_ADDR_WIDTH-1:0] locked_dest_addr, locked_src_addr; // this ensures that addresses are captured when the block is enabled + logic [2:0] state, next_state; + + + // State Machine + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + state <= IDLE; + end + else if (zeroize) begin + state <= IDLE; + end + else begin + state <= next_state; + end + end + + always_comb begin + case (state) + IDLE: begin + if (sigdecode_z_enable) + next_state = READ; + else + next_state = IDLE; + end + READ: begin + next_state = READ_and_EXEC; + end + READ_and_EXEC: begin + next_state = READ_EXEC_and_WRITE; + end + READ_EXEC_and_WRITE: begin + if ((num_api_operands+1) == THE_LAST_ADDR) begin + next_state = EXEC_and_WRITE; + end + else begin + next_state = READ_EXEC_and_WRITE; + end + end + EXEC_and_WRITE: begin + next_state = WRITE; + end + WRITE: begin + next_state = DONE; + end + DONE: begin + next_state = IDLE; + end + default: begin + next_state = IDLE; + end + endcase + end + + // Lock the src and dest addresses and initialize the counter + // Assert the done signal when it is needed + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + num_mem_operands <= 'h0; + num_api_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + sigdecode_z_done <= 'h0; + end + else if (zeroize) begin + num_mem_operands <= 'h0; + num_api_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + sigdecode_z_done <= 'h0; + end + else begin + if (sigdecode_z_enable) begin + locked_dest_addr <= dest_base_addr; + locked_src_addr <= sigmem_src_base_addr; + end + + + if (state == READ || state == READ_and_EXEC || state == READ_EXEC_and_WRITE) begin + num_api_operands <= num_api_operands +2'h2; + end + else begin + num_api_operands <= 'h0; + end + if (state == READ_EXEC_and_WRITE || state == EXEC_and_WRITE || state == WRITE) begin + num_mem_operands <= num_mem_operands +2'h2; + end + else begin + num_mem_operands <= 'h0; + end + if (state == DONE) begin + sigdecode_z_done <= 'h1; + end + else begin + sigdecode_z_done <= 'h0; + end + end + end + + // Write request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (zeroize) begin + mem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (state == READ_EXEC_and_WRITE || state == EXEC_and_WRITE || state == WRITE) begin + mem_a_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_mem_operands}; + mem_b_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_mem_operands + 1}; + end + else begin + mem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + end + + // Memory read request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + sigmem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + sigmem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (zeroize) begin + sigmem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + sigmem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (state == READ || state == READ_and_EXEC || state == READ_EXEC_and_WRITE) begin + sigmem_a_rd_req <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_api_operands}; + sigmem_b_rd_req <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_api_operands + 1}; + end else begin + sigmem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + sigmem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + end + + //8 decoding instances + generate + for (genvar i = 0; i < 4; i++) begin : dec_unit + sigdecode_z_unit #( + .REG_SIZE(REG_SIZE), + .GAMMA1(GAMMA1) + ) + upper_encode ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .data_i(sigmem_a_rd_data[i]), + .data_o(mem_a_wr_data[i]) + ); + sigdecode_z_unit #( + .REG_SIZE(REG_SIZE), + .GAMMA1(GAMMA1) + ) + lower_encode ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .data_i(sigmem_b_rd_data[i]), + .data_o(mem_b_wr_data[i]) + ); + end : dec_unit + endgenerate + + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_unit.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_unit.sv new file mode 100644 index 0000000000000000000000000000000000000000..5a67e9f2e2ab0ee4113e2b8329761aeb49257b5e --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/rtl/sigdecode_z_unit.sv @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigdecode_z_unit.sv +// ---------------------------- +// Decodes a part of signature z from a byte string to a polynomials by calculating the following equation: +// γ1 – (z mod q) = γ1 – (q + z) = γ1 – z – q where q is modulo prime and γ1 is constnat +// parameter range. + +module sigdecode_z_unit +#( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 8380417, + parameter GAMMA1 = 19 +) +( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire [GAMMA1:0] data_i, + output logic [REG_SIZE-1:0] data_o //TODO: clean up. At top level, data_o is 24-bits, so add 1 more bit here and assign 0 +); + + localparam MLDSA_GAMMA1_RANGE = 2**GAMMA1; + + logic [REG_SIZE-1:0] opa0; + logic [REG_SIZE-1:0] opb0; + logic [REG_SIZE-1:0] r0; + logic [REG_SIZE-1:0] opb1; + logic [REG_SIZE-1:0] r1; + logic [REG_SIZE-1:0] r0_reg; + + logic carry0; + logic carry1; + logic carry0_reg; + logic sub_n; + logic sub_i; + + assign sub_i = 1'b1; + assign opa0 = MLDSA_GAMMA1_RANGE; + assign opb0 = sub_i ? REG_SIZE'(~data_i) : REG_SIZE'(data_i); + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_0( + .a_i(opa0), + .b_i(opb0), + .cin_i(sub_i), + .s_o(r0), + .cout_o(carry0) + ); + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_1( + .a_i(r0_reg), + .b_i(opb1), + .cin_i(sub_n), + .s_o(r1), + .cout_o(carry1) + ); + + always_ff @(posedge clk or negedge reset_n) + begin + if(!reset_n) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + sub_n <= '0; + end + else if (zeroize) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + sub_n <= '0; + end + else begin + r0_reg <= r0; + carry0_reg <= carry0; + opb1 <= sub_i ? MLDSA_Q : ~MLDSA_Q; + sub_n <= !sub_i; + end + end + + + assign data_o = sub_n ? (carry0_reg ^ carry1) ? {1'b0, r1} : {1'b0, r0_reg} + : (carry0_reg) ? r0_reg : r1; + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/stimulus/tests/directed/sigdecode_z_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/stimulus/tests/directed/sigdecode_z_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..813de43a0917ee9ad1e4348543c0c38b689e6291 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/stimulus/tests/directed/sigdecode_z_normal_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: sigdecode_z_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/tb/polyz_unpack.py b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/tb/polyz_unpack.py new file mode 100644 index 0000000000000000000000000000000000000000..d77bb77cd2104b01d630b5d6b88e28a58351e407 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/tb/polyz_unpack.py @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import numpy as np + +# Constants +N = 256 # Assuming N is 256; adjust as necessary +L = 7 +GAMMA1 = (1 << 19) +MASK_20BIT = (1 << 20) - 1 +Q = 8380417 + +class Poly: + def __init__(self, coeffs): + self.coeffs = coeffs + +def polyz_pack(a): + t = np.zeros(2, dtype=np.uint32) + r = np.zeros(N*L, dtype=np.uint32) + for i in range((N*L) // 2): + if GAMMA1 >= a.coeffs[2*i+0]: + t[0] = (GAMMA1 - a.coeffs[2*i+0]) + else: + t[0] = ((GAMMA1+Q) - a.coeffs[2*i+0]) + + if GAMMA1 >= a.coeffs[2*i+1]: + t[1] = (GAMMA1 - a.coeffs[2*i+1]) + else: + t[1] = ((GAMMA1+Q) - a.coeffs[2*i+1]) + + r[2*i+0] = t[0] + r[2*i+1] = t[1] + + return r + +def generate_random_inputs(): + coeffs = np.random.randint(0, GAMMA1, N*L, dtype=np.uint32) + return Poly(coeffs) + +def write_hex_file(filename, data): + with open(filename, 'w') as f: + for value in data: + f.write(f"{value:X}\n") + +def main(): + # Generate random inputs + poly_a = generate_random_inputs() + + # Run the pack function + r = polyz_pack(poly_a) + + # Write input coefficients to input_z.hex + write_hex_file("input_z.hex", poly_a.coeffs) + + # Write output encoded coefficients to output_encoded_z.hex + write_hex_file("output_decoded_z.hex", r) + +if __name__ == "__main__": + main() diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/tb/sigdecode_z_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/tb/sigdecode_z_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..7b7fbea52da1a5b272969a7fe6deea4bfc5b47c8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_decode_z/tb/sigdecode_z_tb.sv @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// sigdecode_z_tb.sv +// --------------- +// Testbench for sigdecode_z_top module +//====================================================================== + +`default_nettype none + +module sigdecode_z_tb + import mldsa_params_pkg::*; + import sigdecode_z_defines_pkg::*; +#( + parameter REG_SIZE = 24, + parameter MEM_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH, + parameter GAMMA1 = 19 +) +(); +localparam NUM_OF_COEFF = 256* MLDSA_L; +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg zeroize_tb; +reg sigdecode_z_enable_tb; +reg [MEM_ADDR_WIDTH-1:0] src_base_addr_tb; +reg [MEM_ADDR_WIDTH-1:0] dest_base_addr_tb; +wire [3:0][REG_SIZE-1:0] mem_a_wr_data_tb; +wire [3:0][REG_SIZE-1:0] mem_b_wr_data_tb; +wire sigdecode_z_done_tb; +mem_if_t mem_a_wr_req_tb; +mem_if_t mem_b_wr_req_tb; +wire [3:0][19:0] sigmem_a_rd_data_tb; +wire [3:0][19:0] sigmem_b_rd_data_tb; +sig_mem_if_t sigmem_a_rd_req_tb; +sig_mem_if_t sigmem_b_rd_req_tb; + + +reg [19:0] input_mem [0:NUM_OF_COEFF-1]; +reg [23:0] expected_output_mem [0:NUM_OF_COEFF-1]; +reg [23:0] actual_output_mem [0:NUM_OF_COEFF-1]; + + + +sigdecode_z_top #( + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), + .REG_SIZE(REG_SIZE), + .GAMMA1(GAMMA1) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .dest_base_addr(dest_base_addr_tb), + .mem_a_wr_req(mem_a_wr_req_tb), + .mem_b_wr_req(mem_b_wr_req_tb), + .mem_a_wr_data(mem_a_wr_data_tb), + .mem_b_wr_data(mem_b_wr_data_tb), + .sigmem_src_base_addr(src_base_addr_tb), + .sigmem_a_rd_req(sigmem_a_rd_req_tb), + .sigmem_b_rd_req(sigmem_b_rd_req_tb), + .sigmem_a_rd_data(sigmem_a_rd_data_tb), + .sigmem_b_rd_data(sigmem_b_rd_data_tb), + .sigdecode_z_enable(sigdecode_z_enable_tb), + .sigdecode_z_done(sigdecode_z_done_tb) +); + +wire [REG_SIZE-1:0] dummy_mem_out0, dummy_mem_out1; + +genvar k; +generate + for (k = 0; k < 4; k = k +1) begin : mem_blocks + sig_dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(REG_SIZE), + .DEPTH(NUM_OF_COEFF) + ) + output_memory ( + .clk(clk_tb), + .addr_a(mem_a_wr_req_tb.addr), + .data_in_a(mem_a_wr_data_tb[k]), + .we_a((mem_a_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_a(dummy_mem_out0), + .addr_b(mem_b_wr_req_tb.addr), + .data_in_b(mem_b_wr_data_tb[k]), + .we_b((mem_b_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_b(dummy_mem_out1) + ); + sig_dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(GAMMA1+1), + .DEPTH(NUM_OF_COEFF) + ) + input_memory ( + .clk(clk_tb), + .addr_a(sigmem_a_rd_req_tb.addr), + .data_in_a(20'h0), + .we_a(1'b0), + .data_out_a(sigmem_a_rd_data_tb[k]), + .addr_b(sigmem_b_rd_req_tb.addr), + .data_in_b(20'h0), + .we_b(1'b0), + .data_out_b(sigmem_b_rd_data_tb[k]) + ); + end : mem_blocks +endgenerate + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + zeroize_tb = 0; + sigdecode_z_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + #(3 * CLK_PERIOD); + reset_n_tb = 1; + $display("End of reset"); + end +endtask // reset_dut + + +task overwrite_memory_content(reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + + // Overwrite input memory with the values from input_mem + for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin + mem_blocks[0].input_memory.mem[i+src_base_addr] = input_mem[4*i + 0]; + mem_blocks[1].input_memory.mem[i+src_base_addr] = input_mem[4*i + 1]; + mem_blocks[2].input_memory.mem[i+src_base_addr] = input_mem[4*i + 2]; + mem_blocks[3].input_memory.mem[i+src_base_addr] = input_mem[4*i + 3]; + end +endtask + +task read_memory_content(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr); + int i, j; + // Read output memory into the actual_output_mem array + for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin + actual_output_mem[4*i + 0] = mem_blocks[0].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 1] = mem_blocks[1].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 2] = mem_blocks[2].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 3] = mem_blocks[3].output_memory.mem[i+dest_base_addr]; + end +endtask + +task read_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + string input_file = "input_z.hex"; + string output_file = "output_decoded_z.hex"; + integer file, ret; + int i; + string line; + + // Read input file + file = $fopen(input_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", input_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", input_mem[i]); + i = i + 1; + end + end + $fclose(file); + overwrite_memory_content(src_base_addr); + + // Read expected output file + file = $fopen(output_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", output_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", expected_output_mem[i]); + i = i + 1; + end + end + $fclose(file); + +endtask + +task sigdecode_z_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + $display("Starting sigdecode_z test\n"); + read_test_vectors(src_base_addr); + @(posedge clk_tb); + sigdecode_z_enable_tb = 1; + src_base_addr_tb = src_base_addr; + dest_base_addr_tb = dest_base_addr; + @(posedge clk_tb); + sigdecode_z_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + + $display("Waiting for sigdecode_z to complete\n"); + wait (sigdecode_z_done_tb); + read_memory_content(dest_base_addr); + + $display("Checking output data\n"); + for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin + if (actual_output_mem[i] !== expected_output_mem[i]) begin + $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]); + end + end + $display("Test completed\n"); +endtask + +initial begin + $system($sformatf("python3 polyz_unpack.py")); + init_sim(); + reset_dut(); + $display("Reading test vectors from hex files\n"); + sigdecode_z_test('h0,'h0); + sigdecode_z_test('h40, 'h20); + $finish; +end + +endmodule + + +module sig_dual_port_memory +#( + parameter ADDR_WIDTH = 15, + parameter DATA_WIDTH = 32, + parameter DEPTH = 256 +) +( + input wire clk, + + // Port A + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] data_in_a, + input wire we_a, // Write enable for port A + output reg [DATA_WIDTH-1:0] data_out_a, + + // Port B + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] data_in_b, + input wire we_b, // Write enable for port B + output reg [DATA_WIDTH-1:0] data_out_b +); + + // Memory array + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + // Port A logic + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= data_in_a; + end + data_out_a <= mem[addr_a]; + end + + // Port B logic + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= data_in_b; + end + data_out_b <= mem[addr_b]; + end + +endmodule + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..443e5bffcbc7af628a9913dda58b45de0c47bcd8 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/compile.yml @@ -0,0 +1,49 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [sigencode_z_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sigencode_z_defines_pkg.sv +--- +provides: [sigencode_z] +schema_version: 2.4.0 +requires: + - ntt_pkg + - sigencode_z_pkg + - abr_libs + - ntt_top +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sigencode_z_top.sv + - $COMPILE_ROOT/rtl/sigencode_z_unit.sv + - $COMPILE_ROOT/rtl/sigencode_z_defines_pkg.sv + + tops: [sigencode_z_top] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/sig_encode_z/config/design_lint/sig_encode_z/sglint_waivers +--- +provides: [sigencode_z_tb] +schema_version: 2.4.0 +requires: + - sigencode_z + - sigencode_z_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/sigencode_z_tb.sv + tops: [sigencode_z_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying s1 bytes hex to $PWD" && cp $COMPILE_ROOT/tb/polyz_pack.py .' \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/design_lint/sig_encode_z/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/design_lint/sig_encode_z/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z.vf new file mode 100644 index 0000000000000000000000000000000000000000..cc7489cc62e141be4e830669205e17b16423b504 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z.vf @@ -0,0 +1,58 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..a9a7831e57c8e687f99396a351f460c997e3b747 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..c0e6086f190de7f8130eeb24f97103b5ae07dfbe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/config/sigencode_z_tb.vf @@ -0,0 +1,59 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sig_encode_z/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_top.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/rtl/sigencode_z_unit.sv +${ADAMSBRIDGE_ROOT}/src/sig_encode_z/tb/sigencode_z_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..5dabf2e64815aad48a762140ed078fd04c26c5fe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_defines_pkg.sv @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigencode_z_defines_pkg.sv +// -------- +// sigencode_z parameters for Mldsa +//====================================================================== + +`ifndef MLDSA_SIGENCODE_Z_DEFINES +`define MLDSA_SIGENCODE_Z_DEFINES + +package sigencode_z_defines_pkg; + import mldsa_params_pkg::*; + + parameter API_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH; + parameter MLDSA_L = 7; + + typedef struct packed { + mem_rw_mode_e rd_wr_en; + logic [API_ADDR_WIDTH-1:0] addr; + } sig_mem_if_t; + +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..65c2901ad75ec571e8c6e7350a939c741d1e6e55 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_top.sv @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigencode_z_top.sv +// -------- +// @brief Top-level module for the signature encoder in the Mldsa scheme. +// +// This module implements the top-level logic for encoding z polynomial (a part of signature) in the +// Mldsa post-quantum cryptographic scheme. The encoder reads coefficients from memory, +// processes them through encoding units, and writes the encoded values to a specified +// register map. +// The module interfaces with memory through two parallel read ports and writes the +// encoded data to a destination address in the register map. +// +//====================================================================== + +module sigencode_z_top + import mldsa_params_pkg::*; + import sigencode_z_defines_pkg::*; + #( + parameter MEM_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH, + parameter REG_SIZE = 24, + parameter GAMMA1 = 19 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + // Input memory ports + input wire [MEM_ADDR_WIDTH-1:0] src_base_addr, + output mem_if_t mem_a_rd_req, + output mem_if_t mem_b_rd_req, + input wire [3:0][REG_SIZE-1:0] mem_a_rd_data, + input wire [3:0][REG_SIZE-1:0] mem_b_rd_data, + + // Output API ports + input wire [MEM_ADDR_WIDTH-1:0] sigmem_dest_base_addr, + output sig_mem_if_t sigmem_a_wr_req, + output sig_mem_if_t sigmem_b_wr_req, + output logic [3:0][GAMMA1:0] sigmem_a_wr_data, + output logic [3:0][GAMMA1:0] sigmem_b_wr_data, + + //Control and status signals + input wire sigencode_z_enable, + output logic sigencode_z_done + ); + + localparam THE_LAST_ADDR = ((MLDSA_N)/4)-1; + // State Machine States + localparam IDLE = 3'b000, + READ = 3'b001, + READ_and_EXEC = 3'b010, + READ_EXEC_and_WRITE = 3'b011, + EXEC_and_WRITE = 3'b100, + WRITE = 3'b101, + DONE = 3'b110; + + + logic [31:0] num_mem_operands, num_api_operands; // encoded each four coeff will increment these by one + logic [MEM_ADDR_WIDTH-1:0] locked_dest_addr, locked_src_addr; // this ensures that addresses are captured when the block is enabled + logic [2:0] state, next_state; + + + // State Machine + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + state <= IDLE; + end + else if (zeroize) begin + state <= IDLE; + end + else begin + state <= next_state; + end + end + + always_comb begin + case (state) + IDLE: begin + if (sigencode_z_enable) + next_state = READ; + else + next_state = IDLE; + end + READ: begin + next_state = READ_and_EXEC; + end + READ_and_EXEC: begin + next_state = READ_EXEC_and_WRITE; + end + READ_EXEC_and_WRITE: begin + if ((num_mem_operands+1) == THE_LAST_ADDR) begin + next_state = EXEC_and_WRITE; + end + else begin + next_state = READ_EXEC_and_WRITE; + end + end + EXEC_and_WRITE: begin + next_state = WRITE; + end + WRITE: begin + next_state = DONE; + end + DONE: begin + next_state = IDLE; + end + default: begin + next_state = IDLE; + end + endcase + end + + // Lock the src and dest addresses and initialize the counter + // Assert the done signal when it is needed + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + num_mem_operands <= 'h0; + num_api_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + sigencode_z_done <= 'h0; + end + else if (zeroize) begin + num_mem_operands <= 'h0; + num_api_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + sigencode_z_done <= 'h0; + end + else begin + if (sigencode_z_enable) begin + locked_dest_addr <= sigmem_dest_base_addr; + locked_src_addr <= src_base_addr; + end + + + if (state == READ || state == READ_and_EXEC || state == READ_EXEC_and_WRITE) begin + num_mem_operands <= num_mem_operands +2'h2; + end + else begin + num_mem_operands <= 'h0; + end + if (state == READ_EXEC_and_WRITE || state == EXEC_and_WRITE || state == WRITE) begin + num_api_operands <= num_api_operands +2'h2; + end + else begin + num_api_operands <= 'h0; + end + if (state == DONE) begin + sigencode_z_done <= 'h1; + end + else begin + sigencode_z_done <= 'h0; + end + end + end + + // Write request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + sigmem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + sigmem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (zeroize) begin + sigmem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + sigmem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (state == READ_EXEC_and_WRITE || state == EXEC_and_WRITE || state == WRITE) begin + sigmem_a_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_api_operands}; + sigmem_b_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_api_operands + 1}; + end + else begin + sigmem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + sigmem_b_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + end + + // Memory read request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (zeroize) begin + mem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (state == READ || state == READ_and_EXEC || state == READ_EXEC_and_WRITE) begin + mem_a_rd_req <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_mem_operands}; + mem_b_rd_req <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_mem_operands + 1}; + end else begin + mem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + end + + //8 encoding instances + generate + for (genvar i = 0; i < 4; i++) begin : enc_unit + sigencode_z_unit #( + .REG_SIZE(REG_SIZE), + .GAMMA1(GAMMA1) + ) + upper_encode ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .data_i(mem_a_rd_data[i]), + .data_o(sigmem_a_wr_data[i]) + ); + sigencode_z_unit #( + .REG_SIZE(REG_SIZE), + .GAMMA1(GAMMA1) + ) + lower_encode ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .data_i(mem_b_rd_data[i]), + .data_o(sigmem_b_wr_data[i]) + ); + end : enc_unit + endgenerate + + + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_unit.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_unit.sv new file mode 100644 index 0000000000000000000000000000000000000000..93d188557d07645c231ae30b4219a8813dd446e4 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/rtl/sigencode_z_unit.sv @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigencode_z_unit.sv +// ---------------------------- +// Encodes a part of signature z into a byte string by calculating the following equation: +// γ1 – (z mod q) = γ1 – (q + z) = γ1 – z – q where q is modulo prime and γ1 is constnat +// parameter range. + +module sigencode_z_unit + #( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 8380417, + parameter GAMMA1 = 19 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire [REG_SIZE-1:0] data_i, + output logic [GAMMA1:0] data_o //TODO: clean up. At top level, data_o is 24-bits, so add 1 more bit here and assign 0 + ); + + localparam MLDSA_GAMMA1_RANGE = 2**GAMMA1; + + logic [REG_SIZE-1:0] opa0; + logic [REG_SIZE-1:0] opb0; + logic [REG_SIZE-1:0] r0; + logic [REG_SIZE-1:0] opb1; + logic [REG_SIZE-1:0] r1; + logic [REG_SIZE-1:0] r0_reg; + logic [REG_SIZE-1:0] raw_result; + + logic carry0; + logic carry1; + logic carry0_reg; + logic sub_n; + logic sub_i; + + assign sub_i = 1'b1; + assign opa0 = MLDSA_GAMMA1_RANGE; + assign opb0 = sub_i ? ~data_i : data_i; + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_0( + .a_i(opa0), + .b_i(opb0), + .cin_i(sub_i), + .s_o(r0), + .cout_o(carry0) + ); + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_1( + .a_i(r0_reg), + .b_i(opb1), + .cin_i(sub_n), + .s_o(r1), + .cout_o(carry1) + ); + + always_ff @(posedge clk or negedge reset_n) + begin + if(!reset_n) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + sub_n <= '0; + end + else if (zeroize) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + sub_n <= '0; + end + else begin + r0_reg <= r0; + carry0_reg <= carry0; + opb1 <= sub_i ? MLDSA_Q : ~MLDSA_Q; + sub_n <= !sub_i; + end + end + + + assign raw_result = sub_n ? (carry0_reg ^ carry1) ? {1'b0, r1} : {1'b0, r0_reg} + : (carry0_reg) ? r0_reg : r1; + assign data_o = raw_result[GAMMA1:0]; + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/stimulus/tests/directed/sigencode_z_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/stimulus/tests/directed/sigencode_z_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..9020f534334d3f5eb0931152ac74f60eadd670e2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/stimulus/tests/directed/sigencode_z_normal_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: sigencode_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/tb/polyz_pack.py b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/tb/polyz_pack.py new file mode 100644 index 0000000000000000000000000000000000000000..fb17ae531bbc19737cbf5f910d372f7c2c6d6313 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/tb/polyz_pack.py @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import numpy as np + +# Constants +N = 256 # Assuming N is 256; adjust as necessary +L = 7 +GAMMA1 = (1 << 19) +MASK_20BIT = (1 << 20) - 1 +Q = 8380417 + +class Poly: + def __init__(self, coeffs): + self.coeffs = coeffs + +def polyz_pack(a): + t = np.zeros(2, dtype=np.uint32) + r = np.zeros(N*L, dtype=np.uint32) + for i in range((N*L) // 2): + if GAMMA1 >= a.coeffs[2*i+0]: + t[0] = (GAMMA1 - a.coeffs[2*i+0]) & MASK_20BIT + else: + t[0] = ((GAMMA1+Q) - a.coeffs[2*i+0]) & MASK_20BIT + + if GAMMA1 >= a.coeffs[2*i+1]: + t[1] = (GAMMA1 - a.coeffs[2*i+1]) & MASK_20BIT + else: + t[1] = ((GAMMA1+Q) - a.coeffs[2*i+1]) & MASK_20BIT + + r[2*i+0] = t[0] + r[2*i+1] = t[1] + + return r + +def generate_random_inputs(): + coeffs = np.random.randint(0, Q, N*L, dtype=np.uint32) + return Poly(coeffs) + +def write_hex_file(filename, data): + with open(filename, 'w') as f: + for value in data: + f.write(f"{value:X}\n") + +def main(): + # Generate random inputs + poly_a = generate_random_inputs() + + # Run the pack function + r = polyz_pack(poly_a) + + # Write input coefficients to input_z.hex + write_hex_file("input_z.hex", poly_a.coeffs) + + # Write output encoded coefficients to output_encoded_z.hex + write_hex_file("output_encoded_z.hex", r) + +if __name__ == "__main__": + main() diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/tb/sigencode_z_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/tb/sigencode_z_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..6557310adcfb72b4a525d7a2089bedc3f4cd23dc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sig_encode_z/tb/sigencode_z_tb.sv @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// sigencode_z_tb.sv +// --------------- +// Testbench for sigencode_z_top module +//====================================================================== + +`default_nettype none + +module sigencode_z_tb + import mldsa_params_pkg::*; + import ntt_defines_pkg::*; + import sigencode_z_defines_pkg::*; +#( + parameter REG_SIZE = 24, + parameter MEM_ADDR_WIDTH = 15, + parameter GAMMA1 = 19 +) +(); +localparam NUM_OF_COEFF = MLDSA_N * MLDSA_L; +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg zeroize_tb; +reg sigencode_z_enable_tb; +reg [MEM_ADDR_WIDTH-1:0] src_base_addr_tb; +reg [MEM_ADDR_WIDTH-1:0] sigmem_dest_base_addr_tb; +wire [3:0][REG_SIZE-1:0] mem_a_rd_data_tb; +wire [3:0][REG_SIZE-1:0] mem_b_rd_data_tb; +wire sigencode_z_done_tb; +mem_if_t mem_a_rd_req_tb; +mem_if_t mem_b_rd_req_tb; +wire [3:0][19:0] sigmem_a_wr_data_tb; +wire [3:0][19:0] sigmem_b_wr_data_tb; +sig_mem_if_t sigmem_a_wr_req_tb; +sig_mem_if_t sigmem_b_wr_req_tb; + + +reg [23:0] input_mem [0:NUM_OF_COEFF-1]; +reg [19:0] expected_output_mem [0:NUM_OF_COEFF-1]; +reg [19:0] actual_output_mem [0:NUM_OF_COEFF-1]; + + + +sigencode_z_top #( + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), + .REG_SIZE(REG_SIZE), + .GAMMA1(GAMMA1) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .src_base_addr(src_base_addr_tb), + .mem_a_rd_req(mem_a_rd_req_tb), + .mem_b_rd_req(mem_b_rd_req_tb), + .mem_a_rd_data(mem_a_rd_data_tb), + .mem_b_rd_data(mem_b_rd_data_tb), + .sigmem_dest_base_addr(sigmem_dest_base_addr_tb), + .sigmem_a_wr_req(sigmem_a_wr_req_tb), + .sigmem_b_wr_req(sigmem_b_wr_req_tb), + .sigmem_a_wr_data(sigmem_a_wr_data_tb), + .sigmem_b_wr_data(sigmem_b_wr_data_tb), + .sigencode_z_enable(sigencode_z_enable_tb), + .sigencode_z_done(sigencode_z_done_tb) +); + +wire [GAMMA1:0] dummy_mem_out0, dummy_mem_out1; + +genvar k; +generate + for (k = 0; k < 4; k = k +1) begin : mem_blocks + sig_dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(REG_SIZE), + .DEPTH(NUM_OF_COEFF) + ) + input_memory ( + .clk(clk_tb), + .addr_a(mem_a_rd_req_tb.addr), + .data_in_a(24'h0), + .we_a(1'b0), + .data_out_a(mem_a_rd_data_tb[k]), + .addr_b(mem_b_rd_req_tb.addr), + .data_in_b(24'h0), + .we_b(1'b0), + .data_out_b(mem_b_rd_data_tb[k]) + ); + sig_dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(GAMMA1+1), + .DEPTH(NUM_OF_COEFF) + ) + output_memory ( + .clk(clk_tb), + .addr_a(sigmem_a_wr_req_tb.addr), + .data_in_a(sigmem_a_wr_data_tb[k]), + .we_a((sigmem_a_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_a(dummy_mem_out0), + .addr_b(sigmem_b_wr_req_tb.addr), + .data_in_b(sigmem_b_wr_data_tb[k]), + .we_b((sigmem_b_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_b(dummy_mem_out1) + ); + end : mem_blocks +endgenerate + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + zeroize_tb = 0; + sigencode_z_enable_tb = 0; + src_base_addr_tb = 0; + sigmem_dest_base_addr_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + #(3 * CLK_PERIOD); + reset_n_tb = 1; + $display("End of reset"); + end +endtask // reset_dut + + +task overwrite_memory_content(reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + + // Overwrite input memory with the values from input_mem + for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin + mem_blocks[0].input_memory.mem[i+src_base_addr] = input_mem[4*i + 0]; + mem_blocks[1].input_memory.mem[i+src_base_addr] = input_mem[4*i + 1]; + mem_blocks[2].input_memory.mem[i+src_base_addr] = input_mem[4*i + 2]; + mem_blocks[3].input_memory.mem[i+src_base_addr] = input_mem[4*i + 3]; + end +endtask + +task read_memory_content(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr); + int i, j; + // Read output memory into the actual_output_mem array + for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin + actual_output_mem[4*i + 0] = mem_blocks[0].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 1] = mem_blocks[1].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 2] = mem_blocks[2].output_memory.mem[i+dest_base_addr]; + actual_output_mem[4*i + 3] = mem_blocks[3].output_memory.mem[i+dest_base_addr]; + end +endtask + +task read_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + string input_file = "input_z.hex"; + string output_file = "output_encoded_z.hex"; + integer file, ret; + int i; + string line; + + // Read input file + file = $fopen(input_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", input_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", input_mem[i]); + i = i + 1; + end + end + $fclose(file); + overwrite_memory_content(src_base_addr); + + // Read expected output file + file = $fopen(output_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", output_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", expected_output_mem[i]); + i = i + 1; + end + end + $fclose(file); + +endtask + +task sigencode_z_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + $display("Starting sigencode_z test\n"); + read_test_vectors(src_base_addr); + @(posedge clk_tb); + sigencode_z_enable_tb = 1; + src_base_addr_tb = src_base_addr; + sigmem_dest_base_addr_tb = dest_base_addr; + @(posedge clk_tb); + sigencode_z_enable_tb = 0; + src_base_addr_tb = 0; + sigmem_dest_base_addr_tb = 0; + + $display("Waiting for sigencode_z to complete\n"); + wait (sigencode_z_done_tb); + read_memory_content(dest_base_addr); + + $display("Checking output data\n"); + for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin + if (actual_output_mem[i] !== expected_output_mem[i]) begin + $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]); + end + end + $display("Test completed\n"); +endtask + +initial begin + $system($sformatf("python3 polyz_pack.py")); + init_sim(); + reset_dut(); + $display("Reading test vectors from hex files\n"); + sigencode_z_test('h0,'h0); + sigencode_z_test('h40, 'h20); + $finish; +end + +endmodule + + +module sig_dual_port_memory +#( + parameter ADDR_WIDTH = 15, + parameter DATA_WIDTH = 32, + parameter DEPTH = 256 +) +( + input wire clk, + + // Port A + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] data_in_a, + input wire we_a, // Write enable for port A + output reg [DATA_WIDTH-1:0] data_out_a, + + // Port B + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] data_in_b, + input wire we_b, // Write enable for port B + output reg [DATA_WIDTH-1:0] data_out_b +); + + // Memory array + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + // Port A logic + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= data_in_a; + end + data_out_a <= mem[addr_a]; + end + + // Port B logic + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= data_in_b; + end + data_out_b <= mem[addr_b]; + end + +endmodule + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..2281d89bdc2760ebca27d2b32d6524d93fe7af41 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/compile.yml @@ -0,0 +1,48 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [sigdecode_h_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sigdecode_h_defines_pkg.sv +--- +provides: [sigdecode_h] +schema_version: 2.4.0 +requires: + - mldsa_defines + - abr_libs + - sigdecode_h_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/sigdecode_h.sv + - $COMPILE_ROOT/rtl/sigdecode_h_ctrl.sv + + tops: [sigdecode_h] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/sigdecode_h/config/design_lint/sigdecode_h/sglint_waivers +--- +provides: [sigdecode_h_tb] +schema_version: 2.4.0 +requires: + - sigdecode_h + - sigdecode_h_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/sigdecode_h_tb.sv + tops: [sigdecode_h_tb] + # sim: + # pre_exec: 'echo "[PRE-EXEC] Copying r hex to $PWD" && cp $COMPILE_ROOT/tb/r.hex . && cp $COMPILE_ROOT/tb/z.hex .' + diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/design_lint/sigdecode_h/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/design_lint/sigdecode_h/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h.vf new file mode 100644 index 0000000000000000000000000000000000000000..ee077df5540f108bcb38a589d8eb090f74f9a3ec --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h.vf @@ -0,0 +1,36 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..c403684c84a02fc05d21b44aaeaf501708d7c539 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..d8b86379daaaa663a416181ca6f6abf388b57075 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/config/sigdecode_h_tb.vf @@ -0,0 +1,38 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sigdecode_h/tb/sigdecode_h_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h.sv new file mode 100644 index 0000000000000000000000000000000000000000..1bc2d514d9e6bbc94b2ed3c0d0fa1cd07dcc2200 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h.sv @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigdecode_h.sv +// ----------- +// Processes encoded h component of the signature reg and generates hint vectors per polynomial. +// Every index recorded in y byte string indicates a non-zero hint. Remaining are 0s. +// This module reads the y[w+k-1:w] locations to obtain the number of non-zero hints +// per poly. Then it begins to process y[w-1:0] locations to construct the hint vector. +// To keep it consistent with memory layout, the generated coefficients are 24-bits and +// 4 coeffs are written to each memory addr. + +module sigdecode_h + import mldsa_params_pkg::*; + #( + parameter REG_SIZE = 24, + parameter MLDSA_OMEGA = 75, + parameter MLDSA_K = 8, + parameter MLDSA_N = 256 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire [(MLDSA_OMEGA+MLDSA_K)-1:0][7:0] encoded_h_i, + + input wire sigdecode_h_enable, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + + output mem_if_t mem_wr_req, + output logic [(4*REG_SIZE)-1:0] mem_wr_data, + output logic sigdecode_h_done, + output logic sigdecode_h_error + ); + + localparam SIG_H_NUM_DWORDS = ((MLDSA_OMEGA + MLDSA_K + 1)*8)/32; + + // logic [(MLDSA_OMEGA+MLDSA_K)-1:0][7:0] encoded_h; + // logic [SIG_H_NUM_DWORDS-1:0][31:0] encoded_h_reg; + logic [MLDSA_OMEGA-1:0] hint_array; + logic [7:0] hintsum, hintsum_prev_poly, hintsum_curr_poly; + logic [3:0] poly_count; + logic [6:0] rd_ptr; + logic [MLDSA_N-1:0] bitmap; + logic rst_bitmap; + logic [3:0][7:0] hint; + logic [3:0] curr_poly_map; + logic [$clog2(MLDSA_N)-1:0] bitmap_ptr; + logic hint_rd_en; + mem_if_t mem_wr_req_int; + + //TODO: look into remaining_zero - to save some latency, we can save y[w-1:0] as we read them and + //keep track of what coeffs are being written to memory. If we see that the last y[i] coeff has been written + //to memory, we don't need to continue and can exit and move to the next poly. Assumption is that memory contains 0s + //and it's ok for this operation to be non-constant time. + + //Delay flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + hintsum <= 'h0; + hintsum_prev_poly <= 'h0; + mem_wr_data <= 'h0; + hint <= 'h0; + mem_wr_req.addr <= 'h0; + mem_wr_req.rd_wr_en <= RW_IDLE; + sigdecode_h_error <= 'b0; + end + else if (zeroize) begin + hintsum <= 'h0; + hintsum_prev_poly <= 'h0; + mem_wr_data <= 'h0; + hint <= 'h0; + mem_wr_req.addr <= 'h0; + mem_wr_req.rd_wr_en <= RW_IDLE; + sigdecode_h_error <= 'b0; + end + else begin + hintsum <= sigdecode_h_done ? 'h0 : encoded_h_i[MLDSA_OMEGA+poly_count]; + hintsum_prev_poly <= hintsum; + mem_wr_data <= {REG_SIZE'(bitmap[8'(bitmap_ptr+3)]), REG_SIZE'(bitmap[8'(bitmap_ptr+2)]), REG_SIZE'(bitmap[8'(bitmap_ptr+1)]), REG_SIZE'(bitmap[8'(bitmap_ptr)])}; + hint <= hint_rd_en ? {encoded_h_i[7'(rd_ptr+3)], encoded_h_i[7'(rd_ptr+2)], encoded_h_i[7'(rd_ptr+1)], encoded_h_i[7'(rd_ptr)]} : 'h0; + mem_wr_req <= mem_wr_req_int; + sigdecode_h_error <= ~sigdecode_h_done & (hintsum < hintsum_prev_poly); + end + end + + //bitmap construction + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + bitmap <= 'h0; + end + else if (zeroize) begin + bitmap <= 'h0; + end + else if (rst_bitmap) begin + bitmap <= 'h0; + end + else begin + if (curr_poly_map[0]) + bitmap[hint[0]] <= 'b1; + if (curr_poly_map[1]) + bitmap[hint[1]] <= 'b1; + if (curr_poly_map[2]) + bitmap[hint[2]] <= 'b1; + if (curr_poly_map[3]) + bitmap[hint[3]] <= 'b1; + end + end + + always_comb hintsum_curr_poly = hintsum - hintsum_prev_poly; + + sigdecode_h_ctrl sdh_ctrl_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .sigdecode_h_enable(sigdecode_h_enable), + .dest_base_addr(dest_base_addr), + .hintsum_i(hintsum_curr_poly), + .sigdecode_h_error(sigdecode_h_error), + .mem_wr_req(mem_wr_req_int), + .sigdecode_h_done(sigdecode_h_done), + .poly_count(poly_count), + .rd_ptr(rd_ptr), + .rst_bitmap(rst_bitmap), + .curr_poly_map(curr_poly_map), + .bitmap_ptr(bitmap_ptr), + .hint_rd_en(hint_rd_en) + ); + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..aaf093d9e2b3cd2ab7c4d1d12ffef0b872c393a2 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h_ctrl.sv @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigdecode_h_ctrl.sv +// ----------- +// Manages memory writes and read pointer for encoded_h array. +// Keeps track of indices and polynomial count + +module sigdecode_h_ctrl + import mldsa_params_pkg::*; + import sigdecode_h_defines_pkg::*; + #( + parameter MLDSA_N = 256, + parameter MLDSA_K = 8 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire sigdecode_h_enable, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire [7:0] hintsum_i, //points to hintsum of i_th poly shown by poly_count + input wire sigdecode_h_error, + + output mem_if_t mem_wr_req, + output logic sigdecode_h_done, + output logic [3:0] poly_count, //can be used to pass in hintsum + output logic [6:0] rd_ptr, + output logic rst_bitmap, + output logic [3:0] curr_poly_map, + output logic [$clog2(MLDSA_N)-1:0] bitmap_ptr, + output logic hint_rd_en + ); + + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_wr_addr, mem_wr_addr_nxt; + logic incr_wr_addr, rst_wr_addr; + logic last_poly_last_addr_wr, last_poly; + logic incr_poly; + mem_rw_mode_e rd_wr_en; + // logic [3:0] poly_count; + //poly_done_rd is asserted when all indices of curr poly are processed, i.e. rem_hintsum reaches 0 + //poly_done_wr is asserted when all 256 coeffs have been written for that poly to mem (equivalent to incr_poly if incr_poly is trigd by write fsm) + logic hint_rd_en_f; + logic poly_done_rd, poly_done_wr; + logic sigdecode_h_busy; + + //read pointer + logic incr_rd_ptr; + logic [7:0] rem_hintsum, hintsum_mux_sel; + logic [3:0] curr_poly_mux; + logic latch_hintsum, decr_rem_hintsum; + + sdh_read_state_e read_fsm_state_ps, read_fsm_state_ns; + sdh_write_state_e write_fsm_state_ps, write_fsm_state_ns; + + //Read fsm arcs + logic arc_SDH_RD_EXEC_SDH_RD_IDLE; + logic arc_SDH_RD_IDLE_SDH_RD_INIT; + logic arc_SDH_RD_INIT_SDH_RD_HINTSUM; + logic arc_SDH_RD_EXEC_SDH_RD_INIT; + // logic arc_SDH_RD_INIT_SDH_RD_IDLE; + + //Write fsm arcs + logic arc_SDH_WR_IDLE_SDH_WR_INIT; + logic arc_SDH_WR_INIT_SDH_WR_MEM; + logic arc_SDH_WR_MEM_SDH_WR_INIT; + logic arc_SDH_WR_MEM_SDH_WR_IDLE; + logic arc_SDH_WR_INIT_SDH_WR_IDLE; + + //Write addr counter + always_comb mem_wr_addr_nxt = mem_wr_addr + 'h1; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + mem_wr_addr <= 'h0; + end + else if (zeroize) begin + mem_wr_addr <= 'h0; + end + else if (rst_wr_addr) begin + mem_wr_addr <= dest_base_addr; + end + else if (incr_wr_addr) begin + mem_wr_addr <= last_poly_last_addr_wr ? 'h0 : mem_wr_addr_nxt; + end + end + + always_comb poly_done_wr = (mem_wr_addr[5:0] == ((MLDSA_N/4 - 1))); + + //Poly counter + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + poly_count <= 'h0; + end + else if (zeroize) begin + poly_count <= 'h0; + end + else if (incr_poly) + poly_count <= (poly_count == MLDSA_K) ? 'h0 : poly_count + 'h1; + end + + //bitmap ptr counter + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + bitmap_ptr <= 'h0; + end + else if (zeroize) begin + bitmap_ptr <= 'h0; + end + else if (incr_wr_addr) + bitmap_ptr <= poly_done_wr ? 'h0 : bitmap_ptr + 'h4; + end + + //Flags + always_comb begin + last_poly_last_addr_wr = (mem_wr_addr == dest_base_addr + (MLDSA_K * (MLDSA_N/4))-1); + last_poly = (poly_count == MLDSA_K-1); + sigdecode_h_busy = (write_fsm_state_ps != SDH_WR_IDLE); //writes follow reads, so using that for busy + sigdecode_h_done = (read_fsm_state_ps == SDH_RD_IDLE) & (write_fsm_state_ps == SDH_WR_IDLE); + end + + //Curr poly mux + //We read 1 dword (4 bytes) from reg API by default every cycle. If hintsum >= 4, all four we read belong to curr poly + //If hintsum < 4, only a few of the bytes belong to curr poly. This mux decodes that. + //rd_ptr always starts reading from a curr poly index, so valid hints start from lsb. Meaning, there is no chance + //that there is a hint in the lsb side that belongs to next poly and a hint that belongs to curr poly on the msb side + always_comb begin + hintsum_mux_sel = latch_hintsum ? hintsum_i : rem_hintsum; //in the first cycle, take hintsum //TODO: move to reg? + case(hintsum_mux_sel) + 'h0: curr_poly_mux = 'b0000; + 'h1: curr_poly_mux = 'b0001; + 'h2: curr_poly_mux = 'b0011; + 'h3: curr_poly_mux = 'b0111; + default: curr_poly_mux = 'b0000; + endcase + end + + //Hintsum logic + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + rem_hintsum <= 'h0; + curr_poly_map <= 'h0; + end + else if (zeroize) begin + rem_hintsum <= 'h0; + curr_poly_map <= 'h0; + end + else if (latch_hintsum) begin + rem_hintsum <= hintsum_i; + curr_poly_map <= 'h0; + end + else if (poly_done_rd) begin + rem_hintsum <= 'h0; + curr_poly_map <= 'h0; + end + else if (decr_rem_hintsum) begin + rem_hintsum <= (rem_hintsum >= 'h4) ? rem_hintsum - 'h4 : 'h0; //If rem_hintsum < 4, it indicates last cycle of that poly, and we have read all locations of y for that poly, so reset to 0 + curr_poly_map <= (rem_hintsum >= 'h4) ? 'b1111 : curr_poly_mux; + end + end + + always_comb poly_done_rd = (read_fsm_state_ps == SDH_RD_EXEC) & (rem_hintsum == 'h0); + + //Rd ptr logic + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + rd_ptr <= 'h0; + end + else if (zeroize) begin + rd_ptr <= 'h0; + end + else if (incr_rd_ptr) begin + rd_ptr <= (rem_hintsum >= 'h4) ? rd_ptr + 'h4 : 7'(rd_ptr + rem_hintsum); + end + end + + //----------------- + //Read fsm + //----------------- + always_comb begin + arc_SDH_RD_IDLE_SDH_RD_INIT = (read_fsm_state_ps == SDH_RD_IDLE) & sigdecode_h_enable; + arc_SDH_RD_INIT_SDH_RD_HINTSUM = (read_fsm_state_ps == SDH_RD_INIT) & (write_fsm_state_ps == SDH_WR_INIT); + arc_SDH_RD_EXEC_SDH_RD_INIT = (read_fsm_state_ps == SDH_RD_EXEC) & ~last_poly & poly_done_rd; + arc_SDH_RD_EXEC_SDH_RD_IDLE = (read_fsm_state_ps == SDH_RD_EXEC) & ((last_poly & poly_done_rd) | sigdecode_h_error); + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= SDH_RD_IDLE; + else if (zeroize) + read_fsm_state_ps <= SDH_RD_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; + end + + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + hint_rd_en_f <= '0; + else if (zeroize) + hint_rd_en_f <= '0; + else + hint_rd_en_f <= hint_rd_en; + end + + always_comb begin + incr_rd_ptr = 'b0; + read_fsm_state_ns = read_fsm_state_ps; + latch_hintsum = 'b0; + decr_rem_hintsum = 'b0; + hint_rd_en = 'b0; + + case(read_fsm_state_ps) + SDH_RD_IDLE: begin + read_fsm_state_ns = arc_SDH_RD_IDLE_SDH_RD_INIT ? SDH_RD_INIT : SDH_RD_IDLE; + end + SDH_RD_INIT: begin + read_fsm_state_ns = arc_SDH_RD_INIT_SDH_RD_HINTSUM ? SDH_RD_HINTSUM : SDH_RD_INIT; + end + SDH_RD_HINTSUM: begin + read_fsm_state_ns = SDH_RD_EXEC; + latch_hintsum = 'b1; + end + SDH_RD_EXEC: begin + read_fsm_state_ns = arc_SDH_RD_EXEC_SDH_RD_INIT ? SDH_RD_INIT : + arc_SDH_RD_EXEC_SDH_RD_IDLE ? SDH_RD_IDLE : SDH_RD_EXEC; + incr_rd_ptr = (~poly_done_rd); + decr_rem_hintsum = 'b1; + hint_rd_en = ~arc_SDH_RD_EXEC_SDH_RD_INIT & ~arc_SDH_RD_EXEC_SDH_RD_IDLE; + end + endcase + end + + //----------------- + //Write fsm + //----------------- + always_comb begin + arc_SDH_WR_IDLE_SDH_WR_INIT = (write_fsm_state_ps == SDH_WR_IDLE) & sigdecode_h_enable; + arc_SDH_WR_INIT_SDH_WR_MEM = (write_fsm_state_ps == SDH_WR_INIT) & (hint_rd_en_f | poly_done_rd); //hint_rd_en indicates bitmap is going to be constructed, so we can move to WR MEM state + arc_SDH_WR_INIT_SDH_WR_IDLE = (write_fsm_state_ps == SDH_WR_INIT) & sigdecode_h_error; + arc_SDH_WR_MEM_SDH_WR_INIT = (write_fsm_state_ps == SDH_WR_MEM) & ~last_poly & poly_done_wr; + arc_SDH_WR_MEM_SDH_WR_IDLE = (write_fsm_state_ps == SDH_WR_MEM) & ((last_poly & poly_done_wr) | sigdecode_h_error); + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + write_fsm_state_ps <= SDH_WR_IDLE; + else if (zeroize) + write_fsm_state_ps <= SDH_WR_IDLE; + else + write_fsm_state_ps <= write_fsm_state_ns; + end + + always_comb begin + incr_wr_addr = 'b0; + rst_wr_addr = 'b0; + incr_poly = 'b0; + rst_bitmap = 'b0; + rd_wr_en = RW_IDLE; + write_fsm_state_ns = write_fsm_state_ps; + + case(write_fsm_state_ps) + SDH_WR_IDLE: begin + write_fsm_state_ns = arc_SDH_WR_IDLE_SDH_WR_INIT ? SDH_WR_INIT : SDH_WR_IDLE; + rst_wr_addr = 'b1; + end + SDH_WR_INIT: begin + write_fsm_state_ns = arc_SDH_WR_INIT_SDH_WR_MEM ? SDH_WR_MEM : + arc_SDH_WR_INIT_SDH_WR_IDLE ? SDH_WR_IDLE : SDH_WR_INIT; + end + SDH_WR_MEM: begin + write_fsm_state_ns = arc_SDH_WR_MEM_SDH_WR_INIT ? SDH_WR_INIT : + arc_SDH_WR_MEM_SDH_WR_IDLE ? SDH_WR_IDLE : SDH_WR_MEM; + incr_wr_addr = 'b1; + incr_poly = poly_done_wr; + rd_wr_en = RW_WRITE; + rst_bitmap = arc_SDH_WR_MEM_SDH_WR_INIT | arc_SDH_WR_MEM_SDH_WR_IDLE; + end + default: begin + + end + endcase + end + + //Assign outputs + always_comb begin + mem_wr_req.addr = mem_wr_addr; + mem_wr_req.rd_wr_en = rd_wr_en; + end + + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..73bb6d88c68bee6c5fb5df527a95b049497c5d52 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// sigdecode_h_defines_pkg.sv +// -------- +// sigdecode_h parameters for Mldsa +//====================================================================== + +`ifndef MLDSA_SIGDECODE_H_DEFINES +`define MLDSA_SIGDECODE_H_DEFINES + +package sigdecode_h_defines_pkg; + + typedef enum logic [1:0] {SDH_RD_IDLE, SDH_RD_HINTSUM, SDH_RD_INIT, SDH_RD_EXEC} sdh_read_state_e; + typedef enum logic [1:0] {SDH_WR_IDLE, SDH_WR_INIT, SDH_WR_MEM} sdh_write_state_e; + +endpackage + +`endif \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/stimulus/tests/directed/sigdecode_h_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/stimulus/tests/directed/sigdecode_h_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..0d26cf276b90c1c2f92f4b8560e1412a5030ad65 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/stimulus/tests/directed/sigdecode_h_normal_test.yml @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- + +testname: sigdecode_h_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/tb/sigdecode_h_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/tb/sigdecode_h_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..ea4e21ae46869109751d9e217f6a4a509bc83107 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sigdecode_h/tb/sigdecode_h_tb.sv @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// sigdecode_h_tb.sv +// -------- +// +// +// +//====================================================================== + +`default_nettype none + +module sigdecode_h_tb + import mldsa_params_pkg::*; +#( + parameter NUM_WR = 4, + parameter NUM_RD = 4, + parameter BUFFER_DATA_W = 8, + parameter REG_SIZE = 24, + parameter MLDSA_OMEGA = 75, + parameter MLDSA_K = 8 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg en_tb; +reg [MLDSA_OMEGA+MLDSA_K-1:0][7:0] y_tb; +reg [MLDSA_K-1:0][7:0] hintsum; +reg [MLDSA_OMEGA-1:0][7:0] y_bytes, padding; + + +sigdecode_h #( + .REG_SIZE(REG_SIZE) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .encoded_h_i(y_tb), + .sigdecode_h_enable(en_tb), + .dest_base_addr(MLDSA_MEM_ADDR_WIDTH'(0)), + .mem_wr_req(), + .mem_wr_data(), + .sigdecode_h_done(), + .sigdecode_h_error() +); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + // hint_4bit_tb = 0; + // index_tb = 0; + zeroize_tb = 0; + en_tb = 0; + y_tb = 'h0; + hintsum = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + // cptra_pwrgood_tb = '0; + reset_n_tb = 0; + + // #(2 * CLK_PERIOD); + // cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + +task init_y_array; + hintsum = {8'd40, 8'd35, 8'd30, 8'd25, 8'd20, 8'd15, 8'd10, 8'd5}; + y_bytes = {8'd100, 8'd74, 8'd51, 8'd43, 8'd16, + 8'd9, 8'd7, 8'd5, 8'd3, 8'd1, + 8'd121, 8'd100, 8'd33, 8'd17, 8'd0, + 8'd77, 8'd66, 8'd55, 8'd44, 8'd33, + 8'd65, 8'd54, 8'd43, 8'd32, 8'd21, + 8'd4, 8'd3, 8'd2, 8'd1, 8'd0, + 8'd9, 8'd8, 8'd7, 8'd6, 8'd5, + 8'd255, 8'd191, 8'd127, 8'd63, 8'd31}; + padding = {35{8'h00}}; + // hintsum = {8'd5, 8'd4, 8'd4, 8'd3, 8'd2, 8'd2, 8'd1, 8'd0}; + // y_bytes = {8'd99, 8'd88, 8'd77, 8'd66, 8'd55}; + // padding = {75{8'h00}}; +endtask + +task sigdecode_h_test_check; + reg [7:0] hintsum_curr, hintsum_prev, hintsum_y, rem_hintsum; + reg [7:0] ptr; + $display("Starting sigdecode h test"); + en_tb = 'b1; + @(posedge clk_tb); + en_tb = 'b0; + y_tb = {hintsum, y_bytes}; //((MLDSA_OMEGA+MLDSA_K)*8)'(0); + @(posedge clk_tb); + + //Check output + hintsum_prev = 0; + ptr = 0; + for (int poly = 0; poly < 8; poly++) begin + $display("Poly %0d", poly); + hintsum_y = y_tb[75+poly]; + hintsum_curr = hintsum_y - hintsum_prev; + + if (hintsum_y < hintsum_prev) begin + $error("Invalid signature, exiting"); + break; + end + + while(!dut.sdh_ctrl_inst.poly_done_rd) @(posedge clk_tb); + @(posedge clk_tb); //Wait a clk for bitmap to be updated + + rem_hintsum = hintsum_curr; + // $display("hintsum = %0d, y = %0d, prev = %0d, rem = %0d", hintsum_curr, hintsum_y, hintsum_prev, rem_hintsum); + if (hintsum_curr > 0) begin + while (rem_hintsum > 0) begin + // $display("ptr = %0d, index = %0d", ptr, y_tb[ptr]); + if (~dut.bitmap[y_tb[ptr]]) begin + $error("Expected 1 in bitmap index %0d", y_tb[ptr]); + end + ptr++; + rem_hintsum--; + end + end + else begin + if (dut.bitmap > 256'h0) + $error("Curr poly hintsum = %0d, expecting all 0s in bitmap", hintsum_curr); + end + + hintsum_prev = hintsum_y; + @(posedge clk_tb); + end +endtask + +initial begin + init_sim(); + reset_dut(); + init_y_array(); + sigdecode_h_test_check(); + repeat(1000) @(posedge clk_tb); + $finish; +end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..28877c1a214e94c93c1956cd1337de880720dd2a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/compile.yml @@ -0,0 +1,51 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [skdecode_pkg] +schema_version: 2.4.0 +requires: [] +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/skdecode_defines_pkg.sv +--- +provides: [skdecode] +schema_version: 2.4.0 +requires: + - mldsa_defines + - ntt_top + - skdecode_pkg + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/skdecode_top.sv + - $COMPILE_ROOT/rtl/skdecode_ctrl.sv + - $COMPILE_ROOT/rtl/skdecode_s1s2_unpack.sv + - $COMPILE_ROOT/rtl/skdecode_t0_unpack.sv + - $COMPILE_ROOT/rtl/skdecode_defines_pkg.sv + + tops: [skdecode] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/sk_decode/config/design_lint/skdecode/sglint_waivers +--- +provides: [skdecode_tb] +schema_version: 2.4.0 +requires: + - skdecode + - skdecode_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/skdecode_tb.sv + tops: [skdecode_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying s1 bytes hex to $PWD" && cp $COMPILE_ROOT/tb/s1_bytes.hex . && cp $COMPILE_ROOT/tb/s2_bytes.hex . && cp $COMPILE_ROOT/tb/t0_bytes.hex . && cp $COMPILE_ROOT/tb/s1_out.hex . && cp $COMPILE_ROOT/tb/s2_out.hex . && cp $COMPILE_ROOT/tb/t0_out.hex .' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/design_lint/skdecode/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/design_lint/skdecode/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode.vf new file mode 100644 index 0000000000000000000000000000000000000000..01a1352f4352563c26b94c7f701ca333e2e45f5d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode.vf @@ -0,0 +1,60 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_top.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_s1s2_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_t0_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode_pkg.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode_pkg.vf new file mode 100644 index 0000000000000000000000000000000000000000..43a60c3011ed97e6f2a0316b6b9a1e94abdeb6a6 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode_pkg.vf @@ -0,0 +1,2 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..9fe08d8176879f8487b21272598d42338146d795 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/config/skdecode_tb.vf @@ -0,0 +1,61 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly2x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_dsp.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_mult_reduction.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_special_adder.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_mult_redux46.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_div2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_shuffle_buffer.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_twiddle_lookup.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_top.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_add_sub.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_BFU_mult.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_gs_butterfly.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_pwm.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_masked_butterfly1x2.sv +${ADAMSBRIDGE_ROOT}/src/ntt_top/rtl/ntt_hybrid_butterfly_2x2.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_top.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_ctrl.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_s1s2_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_t0_unpack.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/tb/skdecode_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_ctrl.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_ctrl.sv new file mode 100644 index 0000000000000000000000000000000000000000..b271d4836f04f84fa6ebdc1800d9d6dd636b9123 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_ctrl.sv @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// skdecode_ctrl.sv +// --------------------- +// Enables unpack modules and keeps track of memory writes + +module skdecode_ctrl + import mldsa_params_pkg::*; + import skdecode_defines_pkg::*; + #( + parameter MLDSA_L = 7, + parameter MLDSA_K = 8, + parameter MLDSA_N = 256 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire skdecode_enable, //One enable for all of s0, s1, t0 unpack + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire s1s2_valid, + input wire t0_valid, + input wire s1s2_error, + input wire t0_buf_stall, + + output mem_if_t mem_a_wr_req, + output mem_if_t mem_b_wr_req, + output mem_if_t kmem_a_rd_req, + output mem_if_t kmem_b_rd_req, + output logic s1s2_enable, + output logic t0_enable, + output logic skdecode_done, + output logic s1_done, + output logic s2_done, + output logic t0_done, + output logic s1s2_buf_stall + ); + + //Memory interface wires + logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_wr_addr, mem_wr_addr_nxt, mem_offset; + logic [MLDSA_MEM_ADDR_WIDTH-1:0] kmem_rd_addr, kmem_rd_addr_nxt; + + logic incr_wr_addr, incr_skdec_count; + logic rst_wr_addr, rst_skdec_count; + logic incr_rd_addr, rst_rd_addr; + logic last_poly_last_addr; + logic skdecode_busy; + logic [3:0] num_poly, num_inst; + mem_rw_mode_e mem_rw_mode, kmem_a_rw_mode; + mem_rw_mode_e kmem_b_rw_mode; + logic [8:0] skdecode_count; + logic [3:0] poly_count; + logic s1s2_enable_fsm, t0_enable_fsm; + logic [2:0] stall_count; + logic incr_stall_count; + logic rst_stall_count; + logic mem_rd_stall_local, s1s2_buf_stall_fsm; + logic s1_mode, s2_mode, t0_mode; + + skdec_read_state_e read_fsm_state_ps, read_fsm_state_ns; + skdec_write_state_e write_fsm_state_ps, write_fsm_state_ns; + + //Write FSM arcs + logic arc_SKDEC_WR_IDLE_SKDEC_WR_S1; + logic arc_SKDEC_WR_S1_SKDEC_WR_STAGE; + logic arc_SKDEC_WR_S2_SKDEC_WR_STAGE; + logic arc_SKDEC_WR_T0_SKDEC_WR_STAGE; + logic arc_SKDEC_WR_STAGE_SKDEC_WR_S2; + logic arc_SKDEC_WR_STAGE_SKDEC_WR_T0; + logic arc_SKDEC_WR_STAGE_SKDEC_WR_IDLE; + + //Read FSM arcs + logic arc_SKDEC_RD_IDLE_SKDEC_RD_S1; + logic arc_SKDEC_RD_S1_SKDEC_RD_STAGE; + logic arc_SKDEC_RD_S2_SKDEC_RD_STAGE; + logic arc_SKDEC_RD_T0_SKDEC_RD_STAGE; + logic arc_SKDEC_RD_STAGE_SKDEC_RD_S2; + logic arc_SKDEC_RD_STAGE_SKDEC_RD_T0; + logic arc_SKDEC_RD_STAGE_SKDEC_RD_IDLE; + + //skdecode counter + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + skdecode_count <= 'h0; + else if (zeroize) + skdecode_count <= 'h0; + else if (s1s2_error) + skdecode_count <= 'h0; + else if (rst_skdec_count) + skdecode_count <= 'h0; + else if (incr_skdec_count) begin + skdecode_count <= (skdecode_count == ((num_poly * MLDSA_N)/num_inst)-1) ? 'h0 : skdecode_count + 'h1; + end + end + + //Write addr counter + always_comb mem_wr_addr_nxt = mem_wr_addr + 'h1; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + mem_wr_addr <= 'h0; + else if (zeroize) + mem_wr_addr <= 'h0; + else if (skdecode_enable) + mem_wr_addr <= dest_base_addr; + else if (arc_SKDEC_WR_STAGE_SKDEC_WR_T0) + mem_wr_addr <= mem_a_wr_req.addr; //Latch the last addr written, so we can continue from there for T0 poly //TODO revisit + else if (incr_wr_addr) + mem_wr_addr <= mem_wr_addr_nxt; + end + + //Read addr counter + always_comb kmem_rd_addr_nxt = t0_enable_fsm ? kmem_rd_addr + 'h2 : kmem_rd_addr + 'h1; + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + kmem_rd_addr <= 'h0; + else if (zeroize) + kmem_rd_addr <= 'h0; + else if (skdecode_enable) + kmem_rd_addr <= src_base_addr; + else if (incr_rd_addr) + kmem_rd_addr <= kmem_rd_addr_nxt; + end + + //Stall counter - needed only for s1s2 unpacking. For t0, sample buffer generates full that is used as stall condition + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + stall_count <= 'h0; + else if (zeroize) + stall_count <= 'h0; + else if (rst_stall_count) + stall_count <= 'h0; + else if (incr_stall_count) begin + stall_count <= (stall_count == 'h3) ? 'h0 : stall_count + 'h1; + end + end + + always_comb s1s2_buf_stall_fsm = (s1s2_enable_fsm) & (stall_count == 'h3); + + //Flags + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + s1_mode <= 'b0; + s2_mode <= 'b0; + t0_mode <= 'b0; + end + else if (zeroize) begin + s1_mode <= 'b0; + s2_mode <= 'b0; + t0_mode <= 'b0; + end + else begin + if (arc_SKDEC_WR_IDLE_SKDEC_WR_S1) s1_mode <= 'b1; + else if (arc_SKDEC_WR_STAGE_SKDEC_WR_S2) s1_mode <= 'b0; + + if (arc_SKDEC_WR_STAGE_SKDEC_WR_S2) s2_mode <= 'b1; + else if (arc_SKDEC_WR_STAGE_SKDEC_WR_T0) s2_mode <= 'b0; + + if (arc_SKDEC_WR_STAGE_SKDEC_WR_T0) t0_mode <= 'b1; + else if (arc_SKDEC_WR_STAGE_SKDEC_WR_IDLE) t0_mode <= 'b0; + end + end + + always_comb begin + //write fsm lags behind read fsm, so calculate flags using write states + skdecode_busy = (write_fsm_state_ps != SKDEC_WR_IDLE); + skdecode_done = (write_fsm_state_ps == SKDEC_WR_IDLE); + //last addr flag only used in read + last_poly_last_addr = (skdecode_count == (((num_poly * MLDSA_N)/num_inst)-1)); + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + s1_done <= 'b0; + s2_done <= 'b0; + t0_done <= 'b0; + end + else if (zeroize) begin + s1_done <= 'b0; + s2_done <= 'b0; + t0_done <= 'b0; + end + else begin + if (arc_SKDEC_WR_S1_SKDEC_WR_STAGE) + s1_done <= 'b1; + if (arc_SKDEC_WR_S2_SKDEC_WR_STAGE) + s2_done <= 'b1; + if (arc_SKDEC_WR_T0_SKDEC_WR_STAGE) + t0_done <= 'b1; + end + end + + //--------------------------------- + //Read fsm + //--------------------------------- + always_comb begin + arc_SKDEC_RD_IDLE_SKDEC_RD_S1 = (read_fsm_state_ps == SKDEC_RD_IDLE) & skdecode_enable; + arc_SKDEC_RD_S1_SKDEC_RD_STAGE = (read_fsm_state_ps == SKDEC_RD_S1) & last_poly_last_addr; + arc_SKDEC_RD_S2_SKDEC_RD_STAGE = (read_fsm_state_ps == SKDEC_RD_S2) & last_poly_last_addr; + arc_SKDEC_RD_T0_SKDEC_RD_STAGE = (read_fsm_state_ps == SKDEC_RD_T0) & last_poly_last_addr; + + arc_SKDEC_RD_STAGE_SKDEC_RD_S2 = (write_fsm_state_ps == SKDEC_WR_STAGE) & s1_done & ~s2_done & ~t0_done; + arc_SKDEC_RD_STAGE_SKDEC_RD_T0 = (write_fsm_state_ps == SKDEC_WR_STAGE) & s1_done & s2_done & ~t0_done; + arc_SKDEC_RD_STAGE_SKDEC_RD_IDLE = (write_fsm_state_ps == SKDEC_WR_STAGE) & s1_done & s2_done & t0_done; + + //TODO error conditions + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + read_fsm_state_ps <= SKDEC_RD_IDLE; + else if (zeroize) + read_fsm_state_ps <= SKDEC_RD_IDLE; + else + read_fsm_state_ps <= read_fsm_state_ns; + end + + always_comb begin + read_fsm_state_ns = read_fsm_state_ps; + incr_rd_addr = 'b0; + rst_rd_addr = 'b0; + kmem_a_rw_mode = RW_IDLE; + kmem_b_rw_mode = RW_IDLE; + incr_stall_count = 'b0; + rst_stall_count = 'b0; + incr_skdec_count = 'b0; + rst_skdec_count = 'b0; + s1s2_enable_fsm = 'b0; + t0_enable_fsm = 'b0; + num_poly = 'h0; + num_inst = 'h0; + + unique case(read_fsm_state_ps) + SKDEC_RD_IDLE: begin + read_fsm_state_ns = arc_SKDEC_RD_IDLE_SKDEC_RD_S1 ? SKDEC_RD_S1 : SKDEC_RD_IDLE; + rst_rd_addr = 'b1; + rst_stall_count = 'b1; + rst_skdec_count = 'b1; + end + SKDEC_RD_S1: begin + read_fsm_state_ns = arc_SKDEC_RD_S1_SKDEC_RD_STAGE ? SKDEC_RD_STAGE : SKDEC_RD_S1; + incr_stall_count = 'b1; + incr_rd_addr = ~s1s2_buf_stall_fsm; + kmem_a_rw_mode = ~s1s2_buf_stall_fsm & ~kmem_rd_addr[0] ? RW_READ : RW_IDLE; + kmem_b_rw_mode = ~s1s2_buf_stall_fsm & kmem_rd_addr[0] ? RW_READ : RW_IDLE; + incr_skdec_count = 'b1; + s1s2_enable_fsm = 'b1; + num_poly = MLDSA_L; + num_inst = 'd8; + end + SKDEC_RD_S2: begin + read_fsm_state_ns = arc_SKDEC_RD_S2_SKDEC_RD_STAGE ? SKDEC_RD_STAGE : SKDEC_RD_S2; + incr_stall_count = 'b1; + incr_rd_addr = ~s1s2_buf_stall_fsm; + kmem_a_rw_mode = ~s1s2_buf_stall_fsm & ~kmem_rd_addr[0] ? RW_READ : RW_IDLE; + kmem_b_rw_mode = ~s1s2_buf_stall_fsm & kmem_rd_addr[0] ? RW_READ : RW_IDLE; + incr_skdec_count = 'b1; + s1s2_enable_fsm = 'b1; + num_poly = MLDSA_K; + num_inst = 'd8; + end + SKDEC_RD_T0: begin + read_fsm_state_ns = arc_SKDEC_RD_T0_SKDEC_RD_STAGE ? SKDEC_RD_STAGE : SKDEC_RD_T0; + incr_stall_count = 'b1; + incr_rd_addr = ~t0_buf_stall; + kmem_a_rw_mode = ~t0_buf_stall ? RW_READ : RW_IDLE; + kmem_b_rw_mode = ~t0_buf_stall ? RW_READ : RW_IDLE; + incr_skdec_count = 'b1; + t0_enable_fsm = 'b1; + num_poly = MLDSA_K; + num_inst = 'd4; + end + SKDEC_RD_STAGE: begin + read_fsm_state_ns = arc_SKDEC_RD_STAGE_SKDEC_RD_S2 ? SKDEC_RD_S2 : + arc_SKDEC_RD_STAGE_SKDEC_RD_T0 ? SKDEC_RD_T0 : + arc_SKDEC_RD_STAGE_SKDEC_RD_IDLE ? SKDEC_RD_IDLE : SKDEC_RD_STAGE; + end + default: begin + read_fsm_state_ns = SKDEC_RD_IDLE; + end + endcase + end + + //--------------------------------- + //Write fsm + //--------------------------------- + always_comb begin + //TODO add error conditions + arc_SKDEC_WR_IDLE_SKDEC_WR_S1 = (write_fsm_state_ps == SKDEC_WR_IDLE) & skdecode_enable; + arc_SKDEC_WR_S1_SKDEC_WR_STAGE = (write_fsm_state_ps == SKDEC_WR_S1) & (read_fsm_state_ps == SKDEC_RD_STAGE) & !s1s2_valid; + arc_SKDEC_WR_S2_SKDEC_WR_STAGE = (write_fsm_state_ps == SKDEC_WR_S2) & (read_fsm_state_ps == SKDEC_RD_STAGE) & !s1s2_valid; + arc_SKDEC_WR_T0_SKDEC_WR_STAGE = (write_fsm_state_ps == SKDEC_WR_T0) & (read_fsm_state_ps == SKDEC_RD_STAGE) & !t0_valid; + arc_SKDEC_WR_STAGE_SKDEC_WR_S2 = (write_fsm_state_ps == SKDEC_WR_STAGE) & s1_done & ~s2_done & ~t0_done; + arc_SKDEC_WR_STAGE_SKDEC_WR_T0 = (write_fsm_state_ps == SKDEC_WR_STAGE) & s1_done & s2_done & ~t0_done; + arc_SKDEC_WR_STAGE_SKDEC_WR_IDLE = (write_fsm_state_ps == SKDEC_WR_STAGE) & s1_done & s2_done & t0_done; + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + write_fsm_state_ps <= SKDEC_WR_IDLE; + else if (zeroize) + write_fsm_state_ps <= SKDEC_WR_IDLE; + else + write_fsm_state_ps <= write_fsm_state_ns; + end + + always_comb begin + write_fsm_state_ns = write_fsm_state_ps; + incr_wr_addr = 'b0; + rst_wr_addr = 'b0; + mem_rw_mode = RW_IDLE; + + unique case(write_fsm_state_ps) + SKDEC_WR_IDLE: begin + write_fsm_state_ns = arc_SKDEC_WR_IDLE_SKDEC_WR_S1 ? SKDEC_WR_S1 : SKDEC_WR_IDLE; + rst_wr_addr = 'b1; + end + SKDEC_WR_S1: begin + write_fsm_state_ns = arc_SKDEC_WR_S1_SKDEC_WR_STAGE ? SKDEC_WR_STAGE : SKDEC_WR_S1; + incr_wr_addr = s1s2_valid; + mem_rw_mode = s1s2_valid ? RW_WRITE : RW_IDLE; + end + SKDEC_WR_S2: begin + write_fsm_state_ns = arc_SKDEC_WR_S2_SKDEC_WR_STAGE ? SKDEC_WR_STAGE : SKDEC_WR_S2; + incr_wr_addr = s1s2_valid; + mem_rw_mode = s1s2_valid ? RW_WRITE : RW_IDLE; + end + SKDEC_WR_T0: begin + write_fsm_state_ns = arc_SKDEC_WR_T0_SKDEC_WR_STAGE ? SKDEC_WR_STAGE : SKDEC_WR_T0; + incr_wr_addr = t0_valid; + mem_rw_mode = t0_valid ? RW_WRITE : RW_IDLE; + end + SKDEC_WR_STAGE: begin + write_fsm_state_ns = arc_SKDEC_WR_STAGE_SKDEC_WR_S2 ? SKDEC_WR_S2 : + arc_SKDEC_WR_STAGE_SKDEC_WR_T0 ? SKDEC_WR_T0 : + arc_SKDEC_WR_STAGE_SKDEC_WR_IDLE ? SKDEC_WR_IDLE : SKDEC_WR_STAGE; + end + default: begin + write_fsm_state_ns = SKDEC_WR_IDLE; + end + endcase + end + + //Outputs + always_comb begin + mem_a_wr_req.addr = t0_mode ? mem_wr_addr : (s1_mode | s2_mode) ? (mem_wr_addr << 1) : 'h0; + mem_a_wr_req.rd_wr_en = t0_mode & mem_a_wr_req.addr[0] ? RW_IDLE : mem_rw_mode; + + mem_b_wr_req.addr = t0_mode ? mem_wr_addr : (s1_mode | s2_mode) ? (mem_wr_addr << 1) + 'h1 : 'h0; + mem_b_wr_req.rd_wr_en = t0_mode & ~mem_a_wr_req.addr[0]? RW_IDLE : mem_rw_mode; + + kmem_a_rd_req.addr = t0_enable_fsm ? kmem_rd_addr : kmem_rd_addr; + kmem_a_rd_req.rd_wr_en = t0_enable_fsm ? kmem_a_rw_mode : kmem_a_rw_mode; + + kmem_b_rd_req.addr = t0_enable_fsm ? kmem_rd_addr + 'h1 : kmem_rd_addr; + kmem_b_rd_req.rd_wr_en = t0_enable_fsm ? kmem_b_rw_mode : kmem_b_rw_mode; + + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + s1s2_enable <= 'b0; + t0_enable <= 'b0; + s1s2_buf_stall <= 'b0; + end + else if (zeroize) begin + s1s2_enable <= 'b0; + t0_enable <= 'b0; + s1s2_buf_stall <= 'b0; + end + else begin + s1s2_enable <= s1s2_enable_fsm; + t0_enable <= t0_enable_fsm; + s1s2_buf_stall <= s1s2_buf_stall_fsm; + end + + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_defines_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_defines_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..90a412ad440783e3e4b912dc3c1a9e8f392b4020 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_defines_pkg.sv @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// skdecode_defines_pkg.sv +// -------- +// Skdecode parameters for Mldsa +//====================================================================== + +`ifndef ABR_SKDECODE_DEFINES +`define ABR_SKDECODE_DEFINES + +package skdecode_defines_pkg; + + typedef enum logic [2:0] {SKDEC_RD_IDLE, SKDEC_RD_STAGE, SKDEC_RD_S1, SKDEC_RD_S2, SKDEC_RD_T0} skdec_read_state_e; + typedef enum logic [2:0] {SKDEC_WR_IDLE, SKDEC_WR_STAGE, SKDEC_WR_S1, SKDEC_WR_S2, SKDEC_WR_T0} skdec_write_state_e; + +endpackage + +`endif diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_s1s2_unpack.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_s1s2_unpack.sv new file mode 100644 index 0000000000000000000000000000000000000000..8c6896866dfccc92f0f0d3cb0a753c7dbb8ec679 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_s1s2_unpack.sv @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// skdecode_s1s2_unpack.sv +// -------- +// This mux unpacks s1 and s2 polynomials from sk input. 3-bit input values +// are converted into 24-bit output values which are the final coefficients of +// s1 and s2 poly to be stored in memory + +// coeff = eta - sk_data[eta_size-1:0] +// where eta_size = bitlen(2*eta), eta = 2 and sk_data is part of the incoming sk + +// Input data must be in the range of -2 to 2 (mapped to 0 to 4 in positive range) +// Any value outside of this range is invalid and will trigger an error interrupt to FW and stops the process + +module skdecode_s1s2_unpack + #( + parameter REG_SIZE = 24, + parameter MLDSA_ETA = 2, + parameter ETA_SIZE = 3, //$clog2(2*MLDSA_ETA), + parameter MLDSA_Q = 8380417 + ) + ( + input wire [ETA_SIZE-1:0] data_i, + input wire enable, + output logic [REG_SIZE-1:0] data_o, + output logic valid_o, + output logic error_o + ); + + logic [REG_SIZE-1:0] eta_minus_data; + + always_comb begin + data_o = '0; + valid_o = '0; + error_o = '0; + eta_minus_data = '0; + + if (enable) begin + error_o = 'b0; + eta_minus_data = REG_SIZE'(MLDSA_ETA - data_i); + + unique case(data_i) + 3'h0: data_o = 'h2; + 3'h1: data_o = 'h1; + 3'h2: data_o = 'h0; + 3'h3: data_o = MLDSA_Q-1; + 3'h4: data_o = MLDSA_Q-2; + default: begin + data_o = 'h0; + error_o = 'b1; + end + endcase + + valid_o = 'b1; + end + end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_t0_unpack.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_t0_unpack.sv new file mode 100644 index 0000000000000000000000000000000000000000..97e00b4b5d56b6dd8ee246ce940fc1a7a261afd5 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_t0_unpack.sv @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// skdecode_t0_unpack.sv +// ---------------------------- +// Unpacks t0 from sk by calculating the following equation: +// coeff = (2**(d-1)) - data[d-1:0] where d is a Mldsa param = 13 +// The result of this modular subtraction is a 24-bit value (2**12-a mod q) +// that is stored in memory as coefficients for further processing + +module skdecode_t0_unpack + #( + parameter REG_SIZE = 23, + parameter MLDSA_Q = 8380417, + parameter MLDSA_D = 13 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire enable, + input wire sub_i, + input wire [MLDSA_D-1:0] data_i, + output logic [REG_SIZE:0] data_o, //TODO: clean up. At top level, data_o is 24-bits, so add 1 more bit here and assign 0 + output logic valid_o + ); + + logic [REG_SIZE-1:0] opa0; + logic [REG_SIZE-1:0] opb0; + logic [REG_SIZE-1:0] r0; + logic [REG_SIZE-1:0] opb1; + logic [REG_SIZE-1:0] r1; + logic [REG_SIZE-1:0] r0_reg; + + logic carry0; + logic carry1; + logic carry0_reg; + logic sub_n; + + assign opa0 = (1 << (MLDSA_D-1)); + assign opb0 = sub_i ? REG_SIZE'(~data_i) : REG_SIZE'(data_i); + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_0( + .a_i(opa0), + .b_i(opb0), + .cin_i(sub_i), + .s_o(r0), + .cout_o(carry0) + ); + + abr_adder #( + .RADIX(REG_SIZE) + ) + adder_inst_1( + .a_i(r0_reg), + .b_i(opb1), + .cin_i(sub_n), + .s_o(r1), + .cout_o(carry1) + ); + + always_ff @(posedge clk or negedge reset_n) + begin + if(!reset_n) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + sub_n <= '0; + end + else if (zeroize) begin + r0_reg <= '0; + carry0_reg <= '0; + opb1 <= '0; + sub_n <= '0; + end + else if (enable) begin + r0_reg <= r0; + carry0_reg <= carry0; + opb1 <= sub_i ? MLDSA_Q : ~MLDSA_Q; + sub_n <= !sub_i; + end + end + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + valid_o <= 'b0; + else if (zeroize) + valid_o <= 'b0; + else + valid_o <= enable; + end + + assign data_o = sub_n ? (carry0_reg ^ carry1) ? (REG_SIZE+1)'(r1) : (REG_SIZE+1)'(r0_reg) + : (carry0_reg) ? (REG_SIZE+1)'(r0_reg) : (REG_SIZE+1)'(r1); + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_top.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_top.sv new file mode 100644 index 0000000000000000000000000000000000000000..a02e5b182344df5e1fb22c5a33e7c659c554b108 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/rtl/skdecode_top.sv @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// skdecode_top.sv +// -------- +// 1. Decodes sk input from reg API into s1, s2 and t0 polynomials. +// 2. Output coeffs are all in 24-bit format. 4 coeffs are written to memory per addr. +// 3. Dual writes take place per cycle, hence 8 values are processed per cycle fpr s1s2 unpack +// 4. One enable pulse from HLC will trigger all 3 polynomial decoding and control +// is transferred back to HLC only after the last poly has been written to memory +// 5. Any invalid input in sk will trigger an error within skdecode and operation +// is stopped. An error interrupt must be set (TODO: by HLC?) to notify RV core +// TODO: sk reg to skdecode interface. For now, assuming a mux. Can be shift reg? +// 6. Note, this module interfaces with a key memory to retrieve sk input. Since the memory +// interface is 32-bit data port, 8 s1s2 modules can be run in parallel to process 24-bits of data per cycle +// and 4 t0 unpack modules can be run in parallel to process 52-bits of data per cycle. t0 operation +// requires 2 memory reads per cycle and s1s2 requires 1 memory read +//====================================================================== + +module skdecode_top + import mldsa_params_pkg::*; + import skdecode_defines_pkg::*; + #( + parameter MLDSA_ETA = 2, + parameter MLDSA_D = 13, + parameter ETA_SIZE = 3, + parameter REG_SIZE = 24, + parameter AHB_DATA_WIDTH = 32 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire skdecode_enable, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] keymem_src_base_addr, + input wire [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire [AHB_DATA_WIDTH-1:0] keymem_a_rd_data, + input wire [AHB_DATA_WIDTH-1:0] keymem_b_rd_data, + + output mem_if_t keymem_a_rd_req, + output mem_if_t keymem_b_rd_req, + output mem_if_t mem_a_wr_req, + output mem_if_t mem_b_wr_req, + output logic [3:0][REG_SIZE-1:0] mem_a_wr_data, + output logic [3:0][REG_SIZE-1:0] mem_b_wr_data, + output logic skdecode_error, + output logic skdecode_done, + output logic s1_done, + output logic s2_done, + output logic t0_done + ); + + logic s1s2_enable, t0_enable, s1s2_enable_reg, t0_enable_reg; + logic s1s2_enable_reg_d2, t0_enable_reg_d2; + logic [7:0] s1s2_valid; + logic [3:0] t0_valid; + logic [7:0] s1s2_error; + logic [7:0][REG_SIZE-1:0] s1s2_data; + logic [3:0][REG_SIZE-1:0] t0_data; + logic t0_done_reg; + + //IO flops + mem_if_t mem_a_wr_req_int, mem_b_wr_req_int, mem_a_wr_req_reg, mem_b_wr_req_reg; + logic [7:0][ETA_SIZE-1:0] s1s2_buf_data; + logic [3:0][MLDSA_D-1:0] t0_buf_data; + logic [3:0][REG_SIZE-1:0] mem_a_wr_data_int, mem_b_wr_data_int, mem_a_wr_data_reg, mem_b_wr_data_reg; + logic [AHB_DATA_WIDTH-1:0] keymem_a_rd_data_reg, keymem_b_rd_data_reg; + + logic s1s2_buf_stall, t0_buf_stall; + logic t0_data_valid; + logic s1s2_data_valid; + logic t0_buf_full; + logic s1s2_buf_stall_reg; + logic s1s2_buf_full; + + logic s1s2_keymem_b_valid; + + //Read address counters + logic [MLDSA_MEM_ADDR_WIDTH-1:0] keymem_rd_addr, keymem_rd_addr_nxt; + + + //IO flops + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + s1s2_enable_reg <= 'h0; + t0_enable_reg <= 'h0; + s1s2_enable_reg_d2 <= 'h0; + t0_enable_reg_d2 <= 'h0; + mem_a_wr_req_reg.rd_wr_en <= RW_IDLE; + mem_b_wr_req_reg.rd_wr_en <= RW_IDLE; + mem_a_wr_req_reg.addr <= 'h0; + mem_b_wr_req_reg.addr <= 'h0; + mem_a_wr_data_reg <= 'h0; + mem_b_wr_data_reg <= 'h0; + t0_done_reg <= 'b0; + s1s2_keymem_b_valid <= 'b0; + end + else if (zeroize) begin + s1s2_enable_reg <= 'h0; + t0_enable_reg <= 'h0; + s1s2_enable_reg_d2 <= 'h0; + t0_enable_reg_d2 <= 'h0; + mem_a_wr_req_reg.rd_wr_en <= RW_IDLE; + mem_b_wr_req_reg.rd_wr_en <= RW_IDLE; + mem_a_wr_req_reg.addr <= 'h0; + mem_b_wr_req_reg.addr <= 'h0; + mem_a_wr_data_reg <= 'h0; + mem_b_wr_data_reg <= 'h0; + t0_done_reg <= 'b0; + s1s2_keymem_b_valid <= 'b0; + end + else begin + s1s2_enable_reg <= s1s2_enable; + t0_enable_reg <= t0_enable; + s1s2_enable_reg_d2 <= s1s2_enable_reg; + t0_enable_reg_d2 <= t0_enable_reg; + mem_a_wr_req_reg <= mem_a_wr_req_int; + mem_b_wr_req_reg <= mem_b_wr_req_int; + mem_a_wr_data_reg <= mem_a_wr_data_int; + mem_b_wr_data_reg <= mem_b_wr_data_int; + t0_done_reg <= t0_done; + s1s2_keymem_b_valid <= s1s2_enable & (keymem_b_rd_req.rd_wr_en == RW_READ); + end + end + + //Data flop with enable to sync with buf full + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + keymem_a_rd_data_reg <= 'h0; + keymem_b_rd_data_reg <= 'h0; + end + else if (zeroize) begin + keymem_a_rd_data_reg <= 'h0; + keymem_b_rd_data_reg <= 'h0; + end + else if (~t0_buf_full & ~s1s2_buf_full) begin + keymem_a_rd_data_reg <= s1s2_keymem_b_valid ? keymem_b_rd_data: keymem_a_rd_data; + keymem_b_rd_data_reg <= keymem_b_rd_data; + + end + end + + //Flags + always_comb begin + mem_a_wr_data_int = |s1s2_valid ? s1s2_data[3:0] : |t0_valid ? t0_data[3:0] : 'h0; + mem_b_wr_data_int = |s1s2_valid ? s1s2_data[7:4] : |t0_valid ? t0_data[3:0] : 'h0; + skdecode_error = |s1s2_error; + end + + //Assign outputs + always_comb begin + mem_a_wr_req = mem_a_wr_req_reg; + mem_b_wr_req = mem_b_wr_req_reg; + mem_a_wr_data = mem_a_wr_data_reg; + mem_b_wr_data = mem_b_wr_data_reg; + end + + //8 s1s2 unpack instances to process 3*8 = 24-bits per cycle. In this case, one addr of key mem is read per cycle + generate + for (genvar i = 0; i < 8; i++) begin + skdecode_s1s2_unpack #( + .REG_SIZE(REG_SIZE) + ) + s1s2_unpack_inst ( + .data_i(s1s2_buf_data[i]), + .enable(s1s2_data_valid), //from buffer + .data_o(s1s2_data[i]), + .valid_o(s1s2_valid[i]), + .error_o(s1s2_error[i]) + ); + end + endgenerate + + //4 t0 unpack instances to process 13*4 = 52-bits per cycle. This makes it simpler to interface with key mem that can provide + //atmost 64-bits per cycle. Remaining bits are accumulated in buffer. in this case, 2 addr of key mem are read per cycle + generate + for (genvar i = 0; i < 4; i++) begin + skdecode_t0_unpack #( + .REG_SIZE(REG_SIZE-1) + ) + t0_unpack_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .enable(t0_data_valid), //from buffer + .sub_i('1), + .data_i(t0_buf_data[i]), + .data_o(t0_data[i]), + .valid_o(t0_valid[i]) + ); + end + endgenerate + + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) + s1s2_buf_stall_reg <= 'b0; + else if (zeroize) + s1s2_buf_stall_reg <= 'b0; + else + s1s2_buf_stall_reg <= s1s2_buf_stall; + end + + always_comb begin + t0_buf_stall = t0_buf_full; //(t0_buf_full & t0_enable_reg); + end + + abr_sample_buffer #( + .NUM_WR(16), + .NUM_RD(13), + .BUFFER_DATA_W(4) + ) + t0_sample_buffer_inst ( + .clk(clk), + .rst_b(reset_n), + .zeroize(zeroize), + .data_valid_i((t0_buf_full | ~t0_enable) ? 16'h0 : {16{t0_enable_reg}}), + .data_i({keymem_b_rd_data_reg, keymem_a_rd_data_reg}), + .buffer_full_o(t0_buf_full), + .data_valid_o(t0_data_valid), + .data_o(t0_buf_data) + ); + + abr_sample_buffer #( + .NUM_WR(4), + .NUM_RD(3), + .BUFFER_DATA_W(8) + ) + s1s2_sample_buffer_inst ( + .clk(clk), + .rst_b(reset_n), + .zeroize(zeroize), + .data_valid_i(s1s2_buf_stall_reg/*(s1s2_buf_full | ~s1s2_enable)*/ ? 4'h0 : {4{s1s2_enable_reg}}), + .data_i(keymem_a_rd_data_reg), + .buffer_full_o(s1s2_buf_full), + .data_valid_o(s1s2_data_valid), + .data_o(s1s2_buf_data) + ); + + skdecode_ctrl + skdecode_ctrl_inst ( + .clk(clk), + .reset_n(reset_n), + .zeroize(zeroize), + .skdecode_enable(skdecode_enable), + .src_base_addr(keymem_src_base_addr), + .dest_base_addr(dest_base_addr), + .s1s2_valid(|s1s2_valid), + .t0_valid(|t0_valid), + .s1s2_error(|s1s2_error), //TODO: enable later when tb is fixed to drive input values within range + .t0_buf_stall(t0_buf_stall), //input from buffer to ctrl + .mem_a_wr_req(mem_a_wr_req_int), + .mem_b_wr_req(mem_b_wr_req_int), + .kmem_a_rd_req(keymem_a_rd_req), + .kmem_b_rd_req(keymem_b_rd_req), + .s1s2_enable(s1s2_enable), + .t0_enable(t0_enable), + .skdecode_done(skdecode_done), + .s1_done(s1_done), + .s2_done(s2_done), + .t0_done(t0_done), + .s1s2_buf_stall(s1s2_buf_stall)//(s1s2_buf_full) + ); + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/stimulus/tests/directed/skdecode_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/stimulus/tests/directed/skdecode_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..07d2d66ef0b01fa861f183030ef96b805a3ea369 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/stimulus/tests/directed/skdecode_normal_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: skdecode_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/tb/skdecode_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/tb/skdecode_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..0d4b2e39d9601813c01dbcc3b88d884f41e66e0b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_decode/tb/skdecode_tb.sv @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// skdecode_tb.sv +// --------------- +//====================================================================== + +`default_nettype none + +module skdecode_tb + import mldsa_params_pkg::*; + import skdecode_defines_pkg::*; +#( + parameter REG_SIZE = 24, + parameter MEM_ADDR_WIDTH = 15, + parameter MLDSA_ETA = 2, + parameter ETA_SIZE = 3, //$clog2(2*MLDSA_ETA), + parameter MLDSA_Q = 8380417 +) +(); + +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg [31 : 0] error_ctr; + +reg clk_tb; +reg reset_n_tb; +reg cptra_pwrgood_tb; +reg zeroize_tb; +reg en_tb; +reg [7:0][2:0] s1s2_data_i; +reg [3:0][12:0] t0_data_i; +reg [MLDSA_MEM_ADDR_WIDTH-1:0] dest_base_tb; +reg [31:0] ahb_data_tb, keymem_a_data_tb, keymem_b_data_tb; +reg [6:0][255:0][2:0] s1_array_rnd; +reg [6:0][255:0][23:0] s1_out_rnd; +reg [167:0][3:0][7:0] s1_array, s1_array_rev; + +reg [7:0][255:0][2:0] s2_array_rnd; +reg [7:0][255:0][23:0] s2_out_rnd; + +reg [7:0][255:0][12:0] t0_array_rnd; +reg [7:0][255:0][23:0] t0_out_rnd; + +reg [191:0][3:0][7:0] s2_array; +reg [831:0][3:0][7:0] t0_array; +reg [(256*8)-1:0][REG_SIZE-1:0] t0_out_array, s2_out_array; +reg [(256*7)-1:0][REG_SIZE-1:0] s1_out_array; + +typedef struct { + logic [255:0][2:0] poly_rnd_array; + logic [255:0][23:0] poly_exp_array; +} s_poly_arrays_t; + +typedef struct { + logic [255:0][12:0] poly_rnd_array; + logic [255:0][23:0] poly_exp_array; +} t_poly_arrays_t; + +mem_if_t keymem_a_rd_req_tb; +mem_if_t keymem_b_rd_req_tb; +logic skdecode_error_tb; + +skdecode_top dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .skdecode_enable(en_tb), + .keymem_src_base_addr(MLDSA_MEM_ADDR_WIDTH'(0)), + .dest_base_addr(dest_base_tb), + .keymem_a_rd_data(keymem_a_data_tb), + .keymem_b_rd_data(keymem_b_data_tb), + .keymem_a_rd_req(keymem_a_rd_req_tb), + .keymem_b_rd_req(keymem_b_rd_req_tb), + .mem_a_wr_req(), + .mem_b_wr_req(), + .mem_a_wr_data(), + .mem_b_wr_data(), + .skdecode_error(skdecode_error_tb), + .skdecode_done(), + .s1_done(), + .s2_done(), + .t0_done() +); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + error_ctr = 32'h00000000; + + clk_tb = 0; + reset_n_tb = 0; + cptra_pwrgood_tb = 0; + // hint_4bit_tb = 0; + // index_tb = 0; + zeroize_tb = 0; + en_tb = 0; + s1s2_data_i = 'h0; + t0_data_i = 'h0; + dest_base_tb = 'h0; + ahb_data_tb = 'h0; + keymem_a_data_tb = 'h0; + keymem_b_data_tb = 'h0; + end +endtask + + //---------------------------------------------------------------- + // display_test_result() + // + // Display the accumulated test results. + //---------------------------------------------------------------- + task display_test_result; + begin + if (error_ctr == 0) + begin + $display("*** All test cases completed successfully."); + $display("* TESTCASE PASSED"); + end + else + begin + $display("*** %02d errors detected during testing.", error_ctr); + $display("* TESTCASE FAILED"); + end + end + endtask // display_test_result + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + // cptra_pwrgood_tb = '0; + reset_n_tb = 0; + + // #(2 * CLK_PERIOD); + // cptra_pwrgood_tb = 1; + + #(2 * CLK_PERIOD); + reset_n_tb = 1; + + $display("End of reset"); + end +endtask // reset_dut + + +//---------------------------------------------------------------- +// Randomize Poly function +// +// +//---------------------------------------------------------------- +function s_poly_arrays_t random_s_poly_gen(); + s_poly_arrays_t result; + for (int coeff_no = 0; coeff_no < 256; coeff_no++) begin + result.poly_rnd_array[coeff_no] = $urandom_range(0, 4); + if (result.poly_rnd_array[coeff_no] <= MLDSA_ETA) + result.poly_exp_array[coeff_no] = ((MLDSA_ETA - result.poly_rnd_array[coeff_no]) % MLDSA_Q); + else + result.poly_exp_array[coeff_no] = (MLDSA_Q + MLDSA_ETA - result.poly_rnd_array[coeff_no]) % MLDSA_Q; + end + return result; +endfunction + +function t_poly_arrays_t random_t_poly_gen(); + t_poly_arrays_t result; + for (int coeff_no = 0; coeff_no < 256; coeff_no++) begin + result.poly_rnd_array[coeff_no] = $urandom_range(0, 13'h1fff); + if (result.poly_rnd_array[coeff_no] <= 13'h1000) + result.poly_exp_array[coeff_no] = ((13'h1000 - result.poly_rnd_array[coeff_no]) % MLDSA_Q); + else + result.poly_exp_array[coeff_no] = (MLDSA_Q + 13'h1000 - result.poly_rnd_array[coeff_no]) % MLDSA_Q; + end + return result; +endfunction + +//---------------------------------------------------------------- +// skdecode_rand_test() +// +//---------------------------------------------------------------- +task skdecode_rand_test(); + logic [167:0][31:0] s1_array_tb; + logic [191:0][31:0] s2_array_tb; + logic [831:0][31:0] t0_array_tb; + int i; + string sval; + int check_count; + s_poly_arrays_t s_poly_rnd_array; + t_poly_arrays_t t_poly_rnd_array; + + for (int vec_no=0; vec_no<7; vec_no++) begin + s_poly_rnd_array = random_s_poly_gen(); + s1_array_rnd[vec_no] = s_poly_rnd_array.poly_rnd_array; + s1_out_rnd[vec_no] = s_poly_rnd_array.poly_exp_array; + end + //reshape the array + s1_array_tb = s1_array_rnd; + s1_out_array = s1_out_rnd; + + for (int vec_no=0; vec_no<8; vec_no++) begin + s_poly_rnd_array = random_s_poly_gen(); + s2_array_rnd[vec_no] = s_poly_rnd_array.poly_rnd_array; + s2_out_rnd[vec_no] = s_poly_rnd_array.poly_exp_array; + end + //reshape the array + s2_array_tb = s2_array_rnd; + s2_out_array = s2_out_rnd; + + for (int vec_no=0; vec_no<8; vec_no++) begin + t_poly_rnd_array = random_t_poly_gen(); + t0_array_rnd[vec_no] = t_poly_rnd_array.poly_rnd_array; + t0_out_rnd[vec_no] = t_poly_rnd_array.poly_exp_array; + end + //reshape the array + t0_array_tb = t0_array_rnd; + t0_out_array = t0_out_rnd; + + $display("Starting random test\n"); + @(posedge clk_tb); + en_tb = 1; + @(posedge clk_tb); + en_tb = 1'b0; + dest_base_tb = 15'h0; + + $display("Wait a cycle to emulate mem read\n"); + @(posedge clk_tb); + + $display("Starting s1 poly\n"); + fork + begin + while ((keymem_a_rd_req_tb.addr < 168) & (keymem_b_rd_req_tb.addr < 168)) begin + if (keymem_a_rd_req_tb.rd_wr_en == RW_READ) + keymem_a_data_tb <= s1_array_tb[keymem_a_rd_req_tb.addr]; + + if (keymem_b_rd_req_tb.rd_wr_en == RW_READ) + keymem_b_data_tb <= s1_array_tb[keymem_b_rd_req_tb.addr]; + + @(posedge clk_tb); + end + end + begin + $display("Waiting for s1s2 valid\n"); + while (!dut.s1s2_valid[0]) @(posedge clk_tb); + $display("Received s1s2 valid\n"); + for (int k = 0; k < 224; k++) begin + for (int j = 0; j < 8; j++) begin + if (dut.s1s2_data[j] != s1_out_array[(8*k)+j]) begin + $display("Error: s1 data mismatch. Exp: %6h, Obs: %6h", s1_out_array[(8*k)+j], dut.s1s2_data[j]); + error_ctr = error_ctr + 1; + end + else check_count++; + end + @(posedge clk_tb); + end + end + join + + if (check_count == 1792) + $display("s1 unpack passed, check count = %d", check_count); + else + $display("s1 unpack failed, check count = %d", check_count); + + $display("Waiting for s1 done, value = %0d\n", dut.s1_done); + @(posedge clk_tb iff (dut.s1_done == 1'b1)); + + check_count = 0; + @(posedge clk_tb); //Wait a cycle to emulate delay in fsm for last mem write + + $display("Starting s2 poly\n"); + fork + begin + while ((keymem_a_rd_req_tb.addr < (168+192)) & (keymem_b_rd_req_tb.addr < (168+192))) begin + if (keymem_a_rd_req_tb.rd_wr_en == RW_READ) + keymem_a_data_tb <= s2_array_tb[keymem_a_rd_req_tb.addr - 168]; + + if (keymem_b_rd_req_tb.rd_wr_en == RW_READ) + keymem_b_data_tb <= s2_array_tb[keymem_b_rd_req_tb.addr - 168]; + + @(posedge clk_tb); + end + end + begin + $display("Waiting for s1s2 valid\n"); + while (!dut.s1s2_valid[0]) @(posedge clk_tb); + $display("Received s1s2 valid\n"); + for (int k = 0; k < 256; k++) begin + for (int j = 0; j < 8; j++) begin + if (dut.s1s2_data[j] != s2_out_array[(8*k)+j]) begin + $display("Error: s2 data mismatch. Exp: %6h, Obs: %6h", s2_out_array[(8*k)+j], dut.s1s2_data[j]); + error_ctr = error_ctr + 1; + end + else check_count++; + end + @(posedge clk_tb); + end + end + join + + if (check_count == 2048) + $display("s2 unpack passed, check count = %d", check_count); + else + $display("s2 unpack failed, check count = %d", check_count); + + $display("Waiting for s2 done, value = %0d\n", dut.s2_done); + + @(posedge clk_tb iff (dut.s2_done == 1'b1)); + + check_count = 0; + @(posedge clk_tb); //Wait a cycle to emulate delay in fsm for last mem write + + $display("Starting t0 poly\n"); + fork + begin + while ((keymem_a_rd_req_tb.addr < (168+192+832)) & (keymem_b_rd_req_tb.addr < (168+192+832))) begin + if (keymem_a_rd_req_tb.rd_wr_en == RW_READ) + keymem_a_data_tb <= t0_array_tb[keymem_a_rd_req_tb.addr-360]; + + if (keymem_b_rd_req_tb.rd_wr_en == RW_READ) + keymem_b_data_tb <= t0_array_tb[keymem_b_rd_req_tb.addr-360]; + + @(posedge clk_tb); + end + end + begin + $display("Waiting for t0 valid\n"); + while (!dut.t0_valid[0]) @(posedge clk_tb); + $display("Received t0 valid\n"); + for (int k = 0; k < 512; k++) begin + for (int j = 0; j < 4; j++) begin + if (dut.t0_data[j] != t0_out_array[(4*k)+j]) begin + $display("Error: t0 data mismatch. Exp: %6h, Obs: %6h", t0_out_array[(4*k)+j], dut.t0_data[j]); + error_ctr = error_ctr + 1; + end + else check_count++; + end + @(posedge clk_tb); + end + end + join + + if (check_count == 2048) + $display("T0 unpack passed, check count = %d", check_count); + else + $display("T0 unpack failed, check count = %d", check_count); + + $display("Waiting for t0 done, value = %0d\n", dut.t0_done); + + @(posedge clk_tb iff (dut.t0_done == 1'b1)); + + while (!dut.skdecode_done) @(posedge clk_tb); + $display("Random Test done\n"); +endtask + +//---------------------------------------------------------------- +// skdecode_error_test() +// +//---------------------------------------------------------------- +task skdecode_error_test(); + logic [167:0][31:0] s1_array_tb; + logic [167:0][31:0] s2_array_tb; + logic [831:0][31:0] t0_array_tb; + int i; + int rand_address; + string sval; + int check_count; + s_poly_arrays_t poly_rnd_array; + + $display("Starting error test\n"); + + for (int vec_no=0; vec_no<7; vec_no++) begin + poly_rnd_array = random_s_poly_gen(); + s1_array_rnd[vec_no] = poly_rnd_array.poly_rnd_array; + s1_out_rnd[vec_no] = poly_rnd_array.poly_exp_array; + end + //reshape the array + s1_array_tb = s1_array_rnd; + s1_out_array = s1_out_rnd; + + rand_address = $urandom_range(0,167); + + @(posedge clk_tb); + en_tb = 1; + @(posedge clk_tb); + en_tb = 1'b0; + dest_base_tb = 15'h0; + + //Wait a cycle to emulate mem read + @(posedge clk_tb); + + $display("Starting s1 poly\n"); + + while ((!skdecode_error_tb) && (keymem_a_rd_req_tb.addr < 168) & (keymem_b_rd_req_tb.addr < 168)) begin + if (keymem_a_rd_req_tb.rd_wr_en == RW_READ) begin + if (rand_address == keymem_a_rd_req_tb.addr) + keymem_a_data_tb <= $urandom_range(5,7); + else + keymem_a_data_tb <= s1_array_tb[keymem_a_rd_req_tb.addr]; + end + + if (keymem_b_rd_req_tb.rd_wr_en == RW_READ) + keymem_b_data_tb <= s1_array_tb[keymem_b_rd_req_tb.addr]; + + @(posedge clk_tb); + end + + if (!skdecode_error_tb) begin + $display("Error: invalid s1 is not detected at %d!", rand_address); + error_ctr = error_ctr + 1; + end + else + $display("invalid s1 is detected at %d!", rand_address); + + @(posedge clk_tb); //Wait a cycle to emulate delay in fsm for last mem write + + +endtask + +//---------------------------------------------------------------- +// skdecode_test +// The main test functionality. +// +//---------------------------------------------------------------- + +initial begin + init_sim(); + reset_dut(); + + skdecode_rand_test(); + + skdecode_error_test(); + + display_test_result(); + $finish; +end + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/compile.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/compile.yml new file mode 100644 index 0000000000000000000000000000000000000000..9f64bb443638ede0935ef2c0d0fbff01758970ea --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/compile.yml @@ -0,0 +1,37 @@ +# Copyright (C) Microsoft Corporation. All rights reserved. + +# Go here for details on compile.yml syntax: +# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster + +--- +provides: [skencode] +schema_version: 2.4.0 +requires: + - mldsa_defines + - skdecode_pkg + - abr_libs +targets: + rtl: + directories: [$COMPILE_ROOT/rtl] + files: + - $COMPILE_ROOT/rtl/skencode.sv + + tops: [skencode] + rtl_lint: + directories: [] + waiver_files: + - $MSFT_REPO_ROOT/src/sk_decode/config/design_lint/skencode/sglint_waivers +--- +provides: [skencode_tb] +schema_version: 2.4.0 +requires: + - skencode + - skdecode_pkg +targets: + rtl: + directories: [$COMPILE_ROOT/tb] + files: + - $COMPILE_ROOT/tb/skencode_tb.sv + tops: [skencode_tb] + sim: + pre_exec: 'echo "[PRE-EXEC] Copying s1 bytes hex to $PWD" && cp $COMPILE_ROOT/tb/pack_eta.py .' diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/design_lint/skencode/sglint_waivers b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/design_lint/skencode/sglint_waivers new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/skencode.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/skencode.vf new file mode 100644 index 0000000000000000000000000000000000000000..06599f9475cf6e332a2c9aa917a897e60b611ce7 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/skencode.vf @@ -0,0 +1,36 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/skencode_tb.vf b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/skencode_tb.vf new file mode 100644 index 0000000000000000000000000000000000000000..2c705bd207ef92b2083eb06c065329fad6b6b32b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/config/skencode_tb.vf @@ -0,0 +1,38 @@ ++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl ++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/tb +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv +${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv +${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv +${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv +${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv +${ADAMSBRIDGE_ROOT}/src/sk_encode/tb/skencode_tb.sv \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/rtl/skencode.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/rtl/skencode.sv new file mode 100644 index 0000000000000000000000000000000000000000..854ff2b3b332609a3ec69f14af1e22e0883ccc97 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/rtl/skencode.sv @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//====================================================================== +// +// skencode.sv +// -------- +// The skencode module performs the encoding of secret key components into a packed format. +// This module supports the MLDSA scheme, encoding sk inputs into s1, s2 polynomials. +// The output coefficients are packed into 24-bit format. +// The design supports dual memory writes per cycle, processing 8 values per cycle for s1 and s2 encoding. +// The module operates under the control of a single enable pulse, triggering the encoding process for all polynomials. +// Upon completion, control is transferred back to the host. If any invalid input is detected, the module raises +// an error flag, halting the operation. Error handling and notifications are left to the host's implementation. +// 8 instances of the s1s2 encoder can operate simultaneously, each handling 24 bits of data per cycle. +// +//====================================================================== + +module skencode + import mldsa_params_pkg::*; + import skdecode_defines_pkg::*; + #( + parameter MEM_ADDR_WIDTH = 15, + parameter MLDSA_Q = 23'd8380417, + parameter MLDSA_L = 'h7, + parameter MLDSA_K = 'h8, + parameter MLDSA_N = 'd256, + parameter REG_SIZE = 24, + parameter AHB_DATA_WIDTH = 32 + ) + ( + input wire clk, + input wire reset_n, + input wire zeroize, + + input wire skencode_enable, + input wire [MEM_ADDR_WIDTH-1:0] dest_base_addr, + input wire [MEM_ADDR_WIDTH-1:0] src_base_addr, + input wire [3:0][REG_SIZE-1:0] mem_a_rd_data, + input wire [3:0][REG_SIZE-1:0] mem_b_rd_data, + + output mem_if_t keymem_a_wr_req, + output mem_if_t mem_a_rd_req, + output mem_if_t mem_b_rd_req, + output logic [AHB_DATA_WIDTH-1:0] keymem_a_wr_data, + + output logic skencode_done + ); + + localparam THE_LAST_ADDR = ((MLDSA_K * MLDSA_N)/4)+((MLDSA_L * MLDSA_N)/4)-1; + localparam THE_LAST_API = ((MLDSA_K +MLDSA_L)*MLDSA_N*3)/32; + + // Main State Machine States + // TODO: Define the state names in a pakcage. + localparam IDLE = 3'b000, + READ = 3'b001, + READ_and_ENC = 3'b010, + READ_ENC_and_CONSUME = 3'b011, + ENC_and_CONSUME = 3'b100, + CONSUME = 3'b101, + CONSUME_LAST = 3'b110, + DONE = 3'b111; + + // Main State Machine States + localparam WAIT_BUFFER = 3'b001, + WRITE = 3'b010, + STALL = 3'b011, + GET_LAST = 3'b100; + + + logic [2:0] main_state, next_main_state, write_state, next_write_state; + logic error_flag; + logic [7:0][2:0] encoded_coeffs; + logic [7:0] encoding_error; + logic [23:0] one_encoding_string; + logic [95:0] buffer; + logic [1:0] producer_selector, consumer_selector; + logic write_buffer; + logic [31:0] num_mem_operands, num_api_operands; // encoded each four coeff will increment these by one + logic [MEM_ADDR_WIDTH-1:0] locked_dest_addr, locked_src_addr; // this ensures that addresses are captured when the block is enabled + + assign one_encoding_string = {encoded_coeffs[7],encoded_coeffs[6],encoded_coeffs[5],encoded_coeffs[4], + encoded_coeffs[3],encoded_coeffs[2],encoded_coeffs[1],encoded_coeffs[0]}; + + + // State Machine: Updates main_state and write_state based on current conditions and next states. + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + main_state <= IDLE; + write_state <= IDLE; + end + else if (zeroize) begin + main_state <= IDLE; + write_state <= IDLE; + end + else begin + if (error_flag) begin + main_state <= IDLE; + write_state <= IDLE; + end + else begin + main_state <= next_main_state; + write_state <= next_write_state; + end + end + end + + // Determines next state for main_state based on current main_state and conditions. + always_comb begin + case (main_state) + IDLE: begin + if (skencode_enable) + next_main_state = READ; + else + next_main_state = IDLE; + end + READ: begin + next_main_state = READ_and_ENC; + end + READ_and_ENC: begin + next_main_state = READ_ENC_and_CONSUME; + end + READ_ENC_and_CONSUME: begin + if ((num_mem_operands+1) == THE_LAST_ADDR) begin + next_main_state = ENC_and_CONSUME; + end + else begin + next_main_state = READ_ENC_and_CONSUME; + end + end + ENC_and_CONSUME: begin + next_main_state = CONSUME; + end + CONSUME: begin + next_main_state = CONSUME_LAST; + end + CONSUME_LAST: begin + next_main_state = DONE; + end + DONE: begin + next_main_state = IDLE; + end + default: begin + next_main_state = IDLE; + end + endcase + end + + // Determines next state for write_state based on current write_state and conditions. + always_comb begin + case (write_state) + IDLE: begin + if (main_state == READ_ENC_and_CONSUME) + next_write_state = WAIT_BUFFER; + else + next_write_state = IDLE; + end + WAIT_BUFFER: begin + if (producer_selector == 'h1) + next_write_state = WRITE; + else + next_write_state = WAIT_BUFFER; + end + WRITE: begin + if (consumer_selector == 'h1) + next_write_state = STALL; + else + next_write_state = WRITE; + end + STALL: begin + if (num_api_operands == THE_LAST_API) begin + next_write_state = GET_LAST; + end + else begin + next_write_state = WAIT_BUFFER; + end + end + GET_LAST: begin + next_write_state = DONE; + end + DONE: begin + next_write_state = IDLE; + end + default: begin + next_write_state = IDLE; + end + endcase + end + + // Write request generation + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + keymem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + num_api_operands <= 'h0; + consumer_selector <= 'h0; + end + else if (zeroize) begin + keymem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + num_api_operands <= 'h0; + consumer_selector <= 'h0; + end + else begin + if (write_state == WRITE) + consumer_selector <= consumer_selector + 'h1; + else + consumer_selector <= 'h0; + + if (write_state == IDLE ) begin + num_api_operands <= 'h0; + end + else if (write_state == WRITE || (write_state == WAIT_BUFFER && producer_selector == 'h1)) begin + num_api_operands <= num_api_operands +'h1; + end + + if (write_state == WRITE || (write_state == WAIT_BUFFER && producer_selector == 'h1)) begin + keymem_a_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_api_operands}; + end + else begin + keymem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + end + end + + // Controls and updates the state of various internal signals and registers based on the state machine and input signals. + // Resets or initializes all signals execpt for the write operation related logics. + // Locks destination and source addresses when skencode_enable is active. + // Manages write_buffer and producer_selector based on the main state machine. + // Issues read requests to memory and increments num_mem_operands during appropriate states. + // Signals completion (skencode_done) based on operation progress. + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + write_buffer <= 'h0; + producer_selector <= 'h0; + num_mem_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + skencode_done <= 'h0; + mem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else if (zeroize) begin + write_buffer <= 'h0; + producer_selector <= 'h0; + num_mem_operands <= 'h0; + locked_dest_addr <= 'h0; + locked_src_addr <= 'h0; + skencode_done <= 'h0; + mem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + end + else begin + if (skencode_enable) begin + locked_dest_addr <= dest_base_addr; + locked_src_addr <= src_base_addr; + end + + if (main_state == READ_and_ENC || main_state == READ_ENC_and_CONSUME || main_state == ENC_and_CONSUME) begin + write_buffer <= 'h1; + end + else begin + write_buffer <= 'h0; + end + + if (main_state == READ_ENC_and_CONSUME || main_state == ENC_and_CONSUME) + producer_selector <= producer_selector + 1'b1; + else + producer_selector <= 'h0; + + if (main_state == READ || main_state == READ_and_ENC || main_state == READ_ENC_and_CONSUME) begin + mem_a_rd_req <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_mem_operands}; + mem_b_rd_req <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_mem_operands + 1}; + num_mem_operands <= num_mem_operands +2'h2; + end + else begin + mem_a_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + mem_b_rd_req <= '{rd_wr_en: RW_IDLE, addr: '0}; + num_mem_operands <= 'h0; + end + + if (main_state == DONE) begin + skencode_done <= 'h1; + end + else begin + skencode_done <= 'h0; + end + end + end + + // Manages the 96-bit buffer register based on the write_buffer signal and producer_selector state. + // Accumulates 24-bit encoded strings into the 96-bit buffer, preparing data for further processing or output. + always_ff @(posedge clk or negedge reset_n) begin + if (!reset_n) begin + buffer <= 'h0; + end + else if (zeroize) begin + buffer <= 'h0; + end + else begin + if (write_buffer) begin + if (producer_selector == 2'h0) + buffer[23:0] <= one_encoding_string; + else if (producer_selector == 2'h1) + buffer[47:24] <= one_encoding_string; + else if (producer_selector == 2'h2) + buffer[71:48] <= one_encoding_string; + else + buffer[95:72] <= one_encoding_string; + end + end + end + + // Assigns the appropriate 32-bit portion of the buffer to keymem_a_wr_data based on consumer_selector. + always_comb begin : API_org + case(consumer_selector) + 2'h0: keymem_a_wr_data = buffer[31:0]; + 2'h1: keymem_a_wr_data = buffer[63:32]; + 2'h2: keymem_a_wr_data = buffer[95:64]; + 2'h3: keymem_a_wr_data = 'h0; // Ignored case + endcase + end : API_org + + always_comb begin : encoding + for (int i = 0; i < 4; i++) begin + unique case(mem_a_rd_data[i]) + 'h0: begin + encoded_coeffs[i] = 'h2; + encoding_error[i] = 'h0; + end + 'h1: begin + encoded_coeffs[i] = 'h1; + encoding_error[i] = 'h0; + end + 'h2: begin + encoded_coeffs[i] = 'h0; + encoding_error[i] = 'h0; + end + MLDSA_Q-1: begin + encoded_coeffs[i] = 'h3; + encoding_error[i] = 'h0; + end + MLDSA_Q-2: begin + encoded_coeffs[i] = 'h4; + encoding_error[i] = 'h0; + end + default: begin + encoded_coeffs[i] = 'h0; + encoding_error[i] = 'h1; + end + endcase + unique case(mem_b_rd_data[i]) + 'h0: begin + encoded_coeffs[i+4] = 'h2; + encoding_error[i+4] = 'h0; + end + 'h1: begin + encoded_coeffs[i+4] = 'h1; + encoding_error[i+4] = 'h0; + end + 'h2: begin + encoded_coeffs[i+4] = 'h0; + encoding_error[i+4] = 'h0; + end + MLDSA_Q-1: begin + encoded_coeffs[i+4] = 'h3; + encoding_error[i+4] = 'h0; + end + MLDSA_Q-2: begin + encoded_coeffs[i+4] = 'h4; + encoding_error[i+4] = 'h0; + end + default: begin + encoded_coeffs[i+4] = 'h0; + encoding_error[i+4] = 'h1; + end + endcase + end + end : encoding + + assign error_flag = (|encoding_error) & main_state inside {READ_ENC_and_CONSUME, ENC_and_CONSUME, CONSUME, CONSUME_LAST}; + + `ABR_ASSERT_NEVER(SKENCODE_ERROR_FLAG, error_flag, clk, !reset_n) + +endmodule \ No newline at end of file diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/stimulus/tests/directed/skencode_normal_test.yml b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/stimulus/tests/directed/skencode_normal_test.yml new file mode 100644 index 0000000000000000000000000000000000000000..7988b9594b4786ef78cdaec8b90a461d303329bc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/stimulus/tests/directed/skencode_normal_test.yml @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +--- +testname: skencode_normal_test +seed: 1 diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/tb/pack_eta.py b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/tb/pack_eta.py new file mode 100644 index 0000000000000000000000000000000000000000..1a6873afa18f73e575716d810f17119dfbf14851 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/tb/pack_eta.py @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +import random + +# Constants +Q = 8380417 +VALID_COEFFICIENTS = [Q - 2, Q - 1, 0, 1, 2] +INVALID_COEFFICIENTS = [Q + 1, -1, Q + 2, 123456] # Example invalid values +K = 8 +L = 7 +N = 256 +TOTAL_COEFFICIENTS = (K + L) * N + +def map_coefficient(coef): + """Map the input coefficient to the corresponding 3-bit value.""" + mapping = { + Q - 2: 4, + Q - 1: 3, + 0: 2, + 1: 1, + 2: 0 + } + return mapping.get(coef, None) + +def generate_random_coefficients(num_coeffs, include_invalid=False): + """Generate a list of random coefficients, including invalid ones if specified.""" + coefficients = [] + for _ in range(num_coeffs): + if include_invalid and random.random() < 0.2: + # 20% chance to pick an invalid coefficient + coefficients.append(random.choice(INVALID_COEFFICIENTS)) + else: + # 80% chance to pick a valid coefficient + coefficients.append(random.choice(VALID_COEFFICIENTS)) + return coefficients + +def generate_files(input_coefficients, input_file, output_file): + """Generate files for the input coefficients and their expected outputs.""" + output_lines = [] + + # Write input coefficients to input file + with open(input_file, 'w') as f_input: + for coef in input_coefficients: + f_input.write(f"{coef:X}\n") + + # Process coefficients for expected output + for i in range(0, len(input_coefficients), 32): + current_line = 0 + for j in range(32): + if i + j < len(input_coefficients): + coef = input_coefficients[i + j] + mapped_value = map_coefficient(coef) + if mapped_value is not None: + # Shift the current line to the right by 3 and add the mapped value to the left + current_line = (mapped_value << (j * 3)) | current_line + + if current_line is not None: + # Convert the line to a 96-bit hex string + final_hex = f"{current_line:024X}" + # Add the line to output lines + output_lines.append(final_hex) + + # Write expected output lines to the output file + with open(output_file, 'w') as f_output: + for line in output_lines: + f_output.write(f"{line}\n") + +# Generate normal and error test vectors +normal_coefficients = generate_random_coefficients(TOTAL_COEFFICIENTS) +error_coefficients = generate_random_coefficients(TOTAL_COEFFICIENTS, include_invalid=True) + +# Output the files with specified names +generate_files(normal_coefficients, 'input_sk.hex', 'output_encoded_sk.hex') +generate_files(error_coefficients, 'error_input_sk.hex', 'error_output_encoded_sk.hex') diff --git a/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/tb/skencode_tb.sv b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/tb/skencode_tb.sv new file mode 100644 index 0000000000000000000000000000000000000000..ea63c120d5506c79ef20b765ec5d0f476415dbdd --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/src/sk_encode/tb/skencode_tb.sv @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//====================================================================== +// +// skencode_tb.sv +// --------------- +// Testbench for skencode module +//====================================================================== + +`default_nettype none + +module skencode_tb + import mldsa_params_pkg::*; + import skdecode_defines_pkg::*; +#( + parameter REG_SIZE = 24, + parameter MEM_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH, + parameter MLDSA_Q = 23'd8380417, + parameter AHB_DATA_WIDTH = 32, + parameter MLDSA_L = 'h7, + parameter MLDSA_K = 'h8 +) +(); +localparam NUM_OF_COEFF = MLDSA_N * (MLDSA_L + MLDSA_K); +parameter CLK_HALF_PERIOD = 5; +parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD; + +//---------------------------------------------------------------- +// Register and Wire declarations. +//---------------------------------------------------------------- +reg clk_tb; +reg reset_n_tb; +reg zeroize_tb; +reg skencode_enable_tb; +reg [MEM_ADDR_WIDTH-1:0] src_base_addr_tb; +reg [MEM_ADDR_WIDTH-1:0] dest_base_addr_tb; +wire [3:0][REG_SIZE-1:0] mem_a_rd_data_tb; +wire [3:0][REG_SIZE-1:0] mem_b_rd_data_tb; +wire skencode_done_tb; +mem_if_t mem_a_rd_req_tb; +mem_if_t mem_b_rd_req_tb; +wire [AHB_DATA_WIDTH-1:0] keymem_a_wr_data_tb; +mem_if_t keymem_a_wr_req_tb; +wire skencode_error_tb; + +reg [23:0] input_mem [0:NUM_OF_COEFF-1]; +reg [AHB_DATA_WIDTH*3-1:0] expected_output_mem [0:NUM_OF_COEFF/32-1]; +reg [AHB_DATA_WIDTH*3-1:0] actual_output_mem [0:NUM_OF_COEFF/32-1]; + +skencode #( + .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH), + .MLDSA_Q(MLDSA_Q), + .REG_SIZE(REG_SIZE), + .AHB_DATA_WIDTH(AHB_DATA_WIDTH) +) dut ( + .clk(clk_tb), + .reset_n(reset_n_tb), + .zeroize(zeroize_tb), + .skencode_enable(skencode_enable_tb), + .src_base_addr(src_base_addr_tb), + .dest_base_addr(dest_base_addr_tb), + .mem_a_rd_req(mem_a_rd_req_tb), + .mem_b_rd_req(mem_b_rd_req_tb), + .mem_a_rd_data(mem_a_rd_data_tb), + .mem_b_rd_data(mem_b_rd_data_tb), + .keymem_a_wr_req(keymem_a_wr_req_tb), + .keymem_a_wr_data(keymem_a_wr_data_tb), + .skencode_done(skencode_done_tb), + .skencode_error(skencode_error_tb) +); + +wire [AHB_DATA_WIDTH-1:0] dummy_mem_out0, dummy_mem_out1; + +genvar k; +generate + for (k = 0; k < 4; k = k +1) begin : mem_blocks + dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(REG_SIZE), + .DEPTH(NUM_OF_COEFF) + ) + input_memory ( + .clk(clk_tb), + .addr_a(mem_a_rd_req_tb.addr), + .data_in_a(24'h0), + .we_a(1'b0), + .data_out_a(mem_a_rd_data_tb[k]), + .addr_b(mem_b_rd_req_tb.addr), + .data_in_b(24'h0), + .we_b(1'b0), + .data_out_b(mem_b_rd_data_tb[k]) + ); + end : mem_blocks +endgenerate + +dual_port_memory #( + .ADDR_WIDTH(MEM_ADDR_WIDTH), + .DATA_WIDTH(AHB_DATA_WIDTH), + .DEPTH(NUM_OF_COEFF) + ) + output_memory ( + .clk(clk_tb), + .addr_a(keymem_a_wr_req_tb.addr), + .data_in_a(keymem_a_wr_data_tb), + .we_a((keymem_a_wr_req_tb.rd_wr_en == RW_WRITE)), + .data_out_a(dummy_mem_out0), + .addr_b(15'b0), + .data_in_b(32'b0), + .we_b(1'b0), + .data_out_b(dummy_mem_out1) + ); + +//---------------------------------------------------------------- +// clk_gen +// +// Always running clock generator process. +//---------------------------------------------------------------- +always +begin : clk_gen + #CLK_HALF_PERIOD; + clk_tb = !clk_tb; +end // clk_gen + +task init_sim; + begin + $display("Start of init\n"); + clk_tb = 0; + reset_n_tb = 0; + zeroize_tb = 0; + skencode_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + end +endtask + +//---------------------------------------------------------------- +// reset_dut() +// +// Toggle reset to put the DUT into a well known state. +//---------------------------------------------------------------- +task reset_dut; + begin + $display("*** Toggle reset."); + reset_n_tb = 0; + #(3 * CLK_PERIOD); + reset_n_tb = 1; + $display("End of reset"); + end +endtask // reset_dut + +task overwrite_memory_content(reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + + // Overwrite input memory with the values from input_mem + for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin + mem_blocks[0].input_memory.mem[i+src_base_addr] = input_mem[4*i + 0]; + mem_blocks[1].input_memory.mem[i+src_base_addr] = input_mem[4*i + 1]; + mem_blocks[2].input_memory.mem[i+src_base_addr] = input_mem[4*i + 2]; + mem_blocks[3].input_memory.mem[i+src_base_addr] = input_mem[4*i + 3]; + end +endtask + +task read_memory_content(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr); + int i, j; + // Read output memory into the actual_output_mem array + for (i = 0; i < (NUM_OF_COEFF)/32; i = i + 1) begin + actual_output_mem[i][31:0] = output_memory.mem[3*i+0+dest_base_addr]; + actual_output_mem[i][63:32] = output_memory.mem[3*i+1+dest_base_addr]; + actual_output_mem[i][95:64] = output_memory.mem[3*i+2+dest_base_addr]; + end +endtask + +task read_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + string input_file = "input_sk.hex"; + string output_file = "output_encoded_sk.hex"; + integer file, ret; + int i; + string line; + + // Read input file + file = $fopen(input_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", input_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", input_mem[i]); + i = i + 1; + end + end + $fclose(file); + overwrite_memory_content(src_base_addr); + + // Read expected output file + file = $fopen(output_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", output_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", expected_output_mem[i]); + i = i + 1; + end + end + $fclose(file); +endtask + + +task read_error_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + string input_file = "error_input_sk.hex"; + string output_file = "error_output_encoded_sk.hex"; + integer file, ret; + int i; + string line; + + // Read input file + file = $fopen(input_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", input_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", input_mem[i]); + i = i + 1; + end + end + $fclose(file); + overwrite_memory_content(src_base_addr); + + // Read expected output file + file = $fopen(output_file, "r"); + if (file == 0) $error("Cannot open %s for reading\n", output_file); + i = 0; + while (!$feof(file)) begin + if($fgets(line,file)) begin + ret = $sscanf(line, "%h", expected_output_mem[i]); + i = i + 1; + end + end + $fclose(file); +endtask + +task skencode_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + $display("Starting skencode test\n"); + read_test_vectors(src_base_addr); + @(posedge clk_tb); + skencode_enable_tb = 1; + src_base_addr_tb = src_base_addr; + dest_base_addr_tb = dest_base_addr; + @(posedge clk_tb); + skencode_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + + $display("Waiting for skencode to complete\n"); + wait (skencode_done_tb); + read_memory_content(dest_base_addr); + + $display("Checking output data\n"); + for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin + if (actual_output_mem[i] !== expected_output_mem[i]) begin + $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]); + end + end + $display("Test completed\n"); +endtask + + +task skencode_error_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [MEM_ADDR_WIDTH-1:0] src_base_addr); + int i, j; + $display("Starting skencode error test\n"); + read_error_test_vectors(src_base_addr); + @(posedge clk_tb); + skencode_enable_tb = 1; + src_base_addr_tb = src_base_addr; + dest_base_addr_tb = dest_base_addr; + @(posedge clk_tb); + skencode_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + + $display("Waiting for skencode to complete\n"); + wait (skencode_done_tb | skencode_error_tb); + if (skencode_done_tb) begin + $display("Error: Error flag should have been asserted..."); + end + else begin + @(posedge clk_tb); + zeroize_tb = 1; + @(posedge clk_tb); + zeroize_tb = 0; + repeat(3) @(posedge clk_tb); + $display("Starting skencode test again\n"); + read_test_vectors(src_base_addr); + @(posedge clk_tb); + skencode_enable_tb = 1; + src_base_addr_tb = src_base_addr; + dest_base_addr_tb = dest_base_addr; + @(posedge clk_tb); + skencode_enable_tb = 0; + src_base_addr_tb = 0; + dest_base_addr_tb = 0; + + $display("Waiting for skencode to complete\n"); + wait (skencode_done_tb); + read_memory_content(dest_base_addr); + + $display("Checking output data\n"); + for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin + if (actual_output_mem[i] !== expected_output_mem[i]) begin + $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]); + end + end + $display("Test completed\n"); + end +endtask + +initial begin + $system($sformatf("python3 pack_eta.py")); + init_sim(); + reset_dut(); + $display("Reading test vectors from hex files\n"); + skencode_test('h0, 'h0); + skencode_test('h40, 'h20); + skencode_error_test('h0, 'h0); + $finish; +end + +endmodule + +module dual_port_memory +#( + parameter ADDR_WIDTH = 15, + parameter DATA_WIDTH = 32, + parameter DEPTH = 256 +) +( + input wire clk, + + // Port A + input wire [ADDR_WIDTH-1:0] addr_a, + input wire [DATA_WIDTH-1:0] data_in_a, + input wire we_a, // Write enable for port A + output reg [DATA_WIDTH-1:0] data_out_a, + + // Port B + input wire [ADDR_WIDTH-1:0] addr_b, + input wire [DATA_WIDTH-1:0] data_in_b, + input wire we_b, // Write enable for port B + output reg [DATA_WIDTH-1:0] data_out_b +); + + // Memory array + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + + // Port A logic + always @(posedge clk) begin + if (we_a) begin + mem[addr_a] <= data_in_a; + end + data_out_a <= mem[addr_a]; + end + + // Port B logic + always @(posedge clk) begin + if (we_b) begin + mem[addr_b] <= data_in_b; + end + data_out_b <= mem[addr_b]; + end + +endmodule diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/rdl_post_process.py b/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/rdl_post_process.py new file mode 100644 index 0000000000000000000000000000000000000000..76272b5b12b33a81ef9e6906c70faf8ebac6c2ee --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/rdl_post_process.py @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import sys +import os +import re + +def scrub_line_by_line(fname): + + # Open file + rhandle = open(fname, "r+") + mod_cnt = 0 + mod_lines = "" + + found_hard_reset = None + + # Line by line manipulation + # Look for unpacked arrays (could be struct arrays or signal arrays) + # Look for unpacked struct types + # NOTE: Will not detect unpacked arrays where the array identifier + # and dimensions are on separate lines + for line in rhandle: + has_assign = re.search(r'\bassign\b', line) + has_reg_strb = re.search(r'\bdecoded_reg_strb\b', line) + has_unpacked = re.search(r'\[\d+\]', line) + has_struct = re.search(r'\bstruct\b\s*(?:unpacked)?', line) + is_endmodule = re.search(r'\bendmodule\b', line) + has_reset = re.search(r'\bnegedge\b', line) + has_enum = re.search(r'\btypedef enum\b', line) + if (has_reset is not None and found_hard_reset is None): + substring = re.search(r"negedge (\w+.\w+)", line) + reset_name = substring.group(1) + # Find the hard reset if it exists + # hard_reset_b, error_reset_b and cptra_pwrgood are used interchangeably + found_hard_reset = re.search(r'hard_reset|pwrgood|error_reset',reset_name) + # Skip lines with logic assignments or references to signals; we + # only want to scrub signal definitions for unpacked arrays + if (has_assign is not None or has_reg_strb is not None): + mod_lines+=line + elif (has_enum is not None): + line = re.sub('enum', 'enum logic [31:0]', line) + mod_lines+=line + mod_cnt+=1 + elif (has_struct is not None): + line = re.sub(r'(\bstruct\b)\s*(?:unpacked)?', r'\1 packed', line) + mod_lines+=line + mod_cnt+=1 + elif (has_unpacked is not None): + while(has_unpacked is not None): + # whitespace + # | existing dimensions (packed) + # | | identifier + # | | | unpacked dimensions (ignore this iteration) + # |___ |____________ |______ |_______ unpacked dimension to modify + # | \| \ | \ | \ | + line = re.sub(r'(\s*)(\[[\w-]+:0\])*(\s*\w+)\s*(\[\d+\])*\[(\d+)\]', r'\1[\5-1:0]\2\3\4', line) + has_unpacked = re.search(r'\[\d+\]', line) + mod_lines+=line + mod_cnt+=1 + elif (is_endmodule is not None): + mod_lines+="\n" + mod_lines+="`ABR_ASSERT_KNOWN(ERR_HWIF_IN, hwif_in, clk, !" + reset_name + ")\n" + mod_lines+="\n" + mod_lines+=line + else: + mod_lines+=line + #print(f"modified {mod_cnt} lines with unpacked arrays in {fname}") + + # Close file for reading, reopen to write modified contents + rhandle.close() + whandle = open(fname, "w") + whandle.write(mod_lines) + whandle.close() + +if __name__ == "__main__": + # Get filename to scrub from arguments + if (len(sys.argv) == 1): + print(f"{os.path.basename(sys.argv[0])} requires an argument to specify target file!") + else: + fname = sys.argv[1] + print(f"file name to modify is {fname}") + + # Convert Unpacked Arrays/structs to Packed + scrub_line_by_line(fname) diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/reg_gen.py b/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/reg_gen.py new file mode 100644 index 0000000000000000000000000000000000000000..a4c6cbf677f1166937280db050e0694eb15dcdca --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/reg_gen.py @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# This script generates systemverilog registers from rdl files +# Currently, this script uses peakrdl-regblock version 0.6.0 +# +# pip install peakrdl-regblock==0.6.0 +# +# TODO: To update this script to the latest version (0.11.0) +# 1. Import ALL_UDPS +# from peakrdl_regblock.udps import ALL_UDPS +# 2. Register ALL_UDPS after creating instance of compiler +# rdlc = RDLCompiler() +# +# Register all UDPs that 'regblock' requires +# for udp in ALL_UDPS: +# rdlc.register_udp(udp) + +from systemrdl import RDLCompiler, RDLCompileError, RDLWalker +from systemrdl import RDLListener +from systemrdl.node import FieldNode +from peakrdl_regblock import RegblockExporter +from peakrdl_uvm import UVMExporter +from peakrdl_html import HTMLExporter +from peakrdl_regblock.udps import ALL_UDPS +from peakrdl_regblock.cpuif.passthrough import PassthroughCpuif +from math import log, ceil, floor +import sys +import os +import re +import rdl_post_process + +#output directory for dumping files +rtl_output_dir = os.path.abspath(os.path.dirname(sys.argv[1])) +repo_root = os.environ.get('ADAMSBRIDGE_ROOT') + +# Listener to retrieve the address width at the CPU IF and write as a param to the pkg +class SVPkgAppendingListener(RDLListener): + + def __init__(self, file_path): + self.file_path = file_path + self.orig_file = "" + + def enter_Addrmap(self,node): + self.regfile_name = os.path.join(self.file_path, node.inst_name) + pkg_file_path = str(self.regfile_name + "_pkg.sv") + self.file = open(pkg_file_path, 'r') + for line in self.file.readlines(): + if (re.search(r'\bendpackage\b', line) is None): + self.orig_file += line + self.file.close() + self.file = open(pkg_file_path, 'w') + self.file.write(self.orig_file) + self.file.write("\n localparam " + node.inst_name.upper() + "_ADDR_WIDTH = " + "32'd" + str(int(floor(log(node.total_size, 2)) + 1)) + ";") + + def exit_Addrmap(self, node): + self.file.write("\n\nendpackage") + self.file.close() + + def get_regfile_name(self): + return self.regfile_name + +# Create an instance of the compiler +rdlc = RDLCompiler() + +# Register all UDPs that 'regblock' requires +for udp in ALL_UDPS: + rdlc.register_udp(udp) + +try: + if not repo_root: + print("ADAMSBRIDGE_ROOT environment variable is not defined.") + # Compile your RDL files + # #compile the kv defines so that rdl files including kv controls have the definition + rdlc.compile_file(os.path.join(repo_root, "src/mldsa_top/rtl/kv_def.rdl")) + rdlc.compile_file(sys.argv[1]) + + # Elaborate the design + root = rdlc.elaborate() + + # Export a SystemVerilog implementation + exporter = RegblockExporter() + exporter.export( + root, rtl_output_dir, + cpuif_cls=PassthroughCpuif, + retime_read_response=False + ) + + # Export a UVM register model + exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/uvm")) + exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_uvm.sv") + # The below lines are used to generate a baseline/starting point for the include files "_covergroups.svh" and "_sample.svh" + # The generated files will need to be hand-edited to provide the desired functionality. + # Uncomment these lines and run this script directly on the target RDL file to generate the files. +# exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/cov")) +# exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_covergroups.svh") +# exporter = UVMExporter(user_template_dir=os.path.join(repo_root, "tools/templates/rdl/smp")) +# exporter.export(root, os.path.join(rtl_output_dir, os.path.splitext(os.path.basename(sys.argv[1]))[0]) + "_sample.svh") + + # Traverse the register model! + walker = RDLWalker(unroll=True) + pkglistener = SVPkgAppendingListener(rtl_output_dir) + walker.walk(root, pkglistener) + + # Scrub the output SystemVerilog files to modify the coding style + # - Change unpacked arrays to packed, unpacked structs to packed + # TODO just make a new exporter template instead of scrubbing? + rdl_post_process.scrub_line_by_line(str(pkglistener.get_regfile_name() + ".sv")) + rdl_post_process.scrub_line_by_line(str(pkglistener.get_regfile_name() + "_pkg.sv")) + +except RDLCompileError: + # A compilation error occurred. Exit with error code + sys.exit(1) diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/reg_gen.sh b/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/reg_gen.sh new file mode 100644 index 0000000000000000000000000000000000000000..c75505c1ab2d4ec236f4912e5b350bbe20a78819 --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/scripts/reg_gen.sh @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +python3 tools/scripts/reg_gen.py src/mldsa_top/rtl/mldsa_reg.rdl diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/main.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/main.sv new file mode 100644 index 0000000000000000000000000000000000000000..10c531d0c8b1556a47802f4b36866db43cd811ac --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/main.sv @@ -0,0 +1,14 @@ +{% import 'uvm_reg.sv' as uvm_reg with context %} +{%- macro top() %} +{%- for node in top_node.descendants(in_post_order=True) -%} + {{child_cg(node)}} +{%- endfor -%} +{% endmacro -%} + +{% macro child_cg(node) -%} + {%- if isinstance(node, RegNode) -%} + {%- if not node.is_virtual -%} + {{uvm_reg.cg_definition(node)}} + {%- endif -%} + {%- endif -%} +{%- endmacro %} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/top_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/top_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..4502c01c3bd77f54fcc2ba4823b78056fd9d315d --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/top_pkg.sv @@ -0,0 +1,20 @@ +{%- import 'main.sv' as main with context -%} +{%- raw -%} +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +{% endraw %} +{{ "`ifndef" }} {{top_node.get_path()|upper}}_COVERGROUPS + {{ "`define" }} {{top_node.get_path()|upper}}_COVERGROUPS + {{main.top()|indent}} +{{ "`endif" }} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/uvm_reg.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/uvm_reg.sv new file mode 100644 index 0000000000000000000000000000000000000000..bf30f1187bc160f3e95f01c06caf4fdfbc0fef3b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/cov/uvm_reg.sv @@ -0,0 +1,288 @@ +{% import 'utils.sv' as utils with context %} + +//------------------------------------------------------------------------------ +// uvm_reg definition +//------------------------------------------------------------------------------ +{% macro class_definition(node) -%} +{%- if class_needs_definition(node) %} +// {{get_class_friendly_name(node)}} +class {{get_class_name(node)}} extends uvm_reg; +{%- if use_uvm_factory %} + `uvm_object_utils({{get_class_name(node)}}) +{%- endif %} + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; +{% for field in node.fields() %} + {{bit_covergroup_name(node)|indent}} {{bit_covergroup_inst(field)}}[{{field.width}}]; +{%- endfor %} + {{fld_covergroup_name(node)|indent}} fld_cg; + {{child_insts(node)|indent}} + {{function_new(node)|indent}} + {{function_sample_values(node)|indent}} + {{function_sample(node)|indent}} + + {{function_build(node)|indent}} +endclass : {{get_class_name(node)}} +{% endif -%} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Definitions +//------------------------------------------------------------------------------ +{% macro cg_definition(node) %} +{{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"COVERGROUPS -----------------------*/"}} +covergroup {{bit_covergroup_name(node)}} with function sample(input bit reg_bit); + option.per_instance = 1; + {{bit_coverpoint()|indent}} +endgroup +covergroup {{fld_covergroup_name(node)}} with function sample({{covergroup_inputs(node)}}); + option.per_instance = 1; + {{fld_coverpoints(node)|indent}} +endgroup +{% endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Inputs +//------------------------------------------------------------------------------ +{% macro covergroup_inputs(node) %} +{% for field in node.fields() -%} +input bit [{{field.width}}-1:0] {{get_inst_name(field)}}{% if not loop.last %}{{","}}{% endif %} +{% endfor %} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Coverpoint Definitions +//------------------------------------------------------------------------------ +{%- macro fld_coverpoints(node) -%} +{%- for field in node.fields() -%} +{{field_coverpoint(field)}} +{%- endfor -%} +{%- endmacro -%} + + +//------------------------------------------------------------------------------ +// Singular Coverpoint Definition +//------------------------------------------------------------------------------ +{%- macro bit_coverpoint() -%} +reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; +} +reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); +} +{% endmacro %} +{%- macro field_coverpoint(field) -%} +{{get_inst_name(field)}}_cp : coverpoint {{get_inst_name(field)}}; +{% endmacro %} + + +//------------------------------------------------------------------------------ +// Child instances +//------------------------------------------------------------------------------ +{% macro child_insts(node) -%} +{%- for field in node.fields() -%} +rand uvm_reg_field {{get_inst_name(field)}}; +{% endfor -%} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// new() function +//------------------------------------------------------------------------------ +{% macro function_new(node) -%} +function new(string name = "{{get_class_name(node)}}"); + super.new(name, {{node.get_property('regwidth')}}, build_coverage(UVM_CVR_ALL)); +endfunction : new +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample() function declaration +//------------------------------------------------------------------------------ +{% macro function_sample(node) -%} +extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample_values() function declaration +//------------------------------------------------------------------------------ +{% macro function_sample_values(node) -%} +extern virtual function void sample_values(); +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample() function definition +//------------------------------------------------------------------------------ +{%- macro function_sample_def(node) -%} +function void {{get_class_name(node)}}::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample(data[{{field.lsb}} + bt]); +{%- endfor %} + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample({{covergroup_sample_args(node)}}); + end +endfunction +{% endmacro -%} + + +//------------------------------------------------------------------------------ +// sample_values() function definition +//------------------------------------------------------------------------------ +{%- macro function_sample_values_def(node) -%} +function void {{get_class_name(node)}}::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample({{get_inst_name(field)}}.get_mirrored_value() >> bt); +{%- endfor %} + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample({{covergroup_sample_values_args(node)}}); + end +endfunction +{% endmacro %} + + +//------------------------------------------------------------------------------ +// build() function +//------------------------------------------------------------------------------ +{% macro function_build(node) -%} +virtual function void build(); + {%- for field in node.fields() %} + {%- if use_uvm_factory %} + this.{{get_inst_name(field)}} = uvm_reg_field::type_id::create("{{get_inst_name(field)}}"); + {%- else %} + this.{{get_inst_name(field)}} = new("{{get_inst_name(field)}}"); + {%- endif %} + this.{{get_inst_name(field)}}.configure(this, {{field.width}}, {{field.lsb}}, "{{get_field_access(field)}}", {{field.is_volatile|int}}, {{"'h%x" % field.get_property('reset', default=0)}}, {{field.get_property('reset') is not none|int}}, 1, 0); + {%- endfor %} + if (has_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) {{bit_covergroup_inst(field)}}[bt] = new(); +{%- endfor %} + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); +endfunction : build +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Name +//------------------------------------------------------------------------------ +{% macro bit_covergroup_name(node) -%} {{get_class_name(node)}}_bit_cg {%- endmacro %} +{% macro bit_covergroup_inst(field) -%} {{"%s_bit_cg"|format(get_inst_name(field))}} {%- endmacro %} +{% macro fld_covergroup_name(node) -%} {{get_class_name(node)}}_fld_cg {%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Constructor Arguments +//------------------------------------------------------------------------------ +{% macro covergroup_new_args(node) -%} + {%- for field in node.fields() %} {{covergroup_new_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_new_arg(field) -%} + {{get_inst_name(field)}}.get_reset() +{%- endmacro %} +{% macro covergroup_sample_args(node) -%} + {%- for field in node.fields() %} {{covergroup_sample_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_sample_arg(field) -%} + data[{{field.msb}}:{{field.lsb}}]{{"/*%s*/"|format(get_inst_name(field))}} +{%- endmacro %} +{% macro covergroup_sample_values_args(node) -%} + {%- for field in node.fields() %} {{covergroup_sample_values_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_sample_values_arg(field) -%} + {{get_inst_name(field)}}.get_mirrored_value() +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// build() actions for uvm_reg instance (called by parent) +//------------------------------------------------------------------------------ +{% macro build_instance(node) -%} +{%- if node.is_array %} +foreach(this.{{get_inst_name(node)}}[{{utils.array_iterator_list(node)}}]) begin + {%- if use_uvm_factory %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = {{get_class_name(node)}}::type_id::create($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}})); + {%- else %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = new($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}})); + {%- endif %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.configure(this); + {{add_hdl_path_slices(node, get_inst_name(node) + utils.array_iterator_suffix(node))|trim|indent}} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.build(); + this.default_map.add_reg(this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}, {{get_array_address_offset_expr(node)}}); +end +{%- else %} +{%- if use_uvm_factory %} +this.{{get_inst_name(node)}} = {{get_class_name(node)}}::type_id::create("{{get_inst_name(node)}}"); +{%- else %} +this.{{get_inst_name(node)}} = new("{{get_inst_name(node)}}"); +{%- endif %} +this.{{get_inst_name(node)}}.configure(this); +{{add_hdl_path_slices(node, get_inst_name(node))|trim}} +this.{{get_inst_name(node)}}.build(); +this.default_map.add_reg(this.{{get_inst_name(node)}}, {{"'h%x" % node.raw_address_offset}}); +{%- endif %} +{%- endmacro %} + +//------------------------------------------------------------------------------ +// Load HDL path slices for this reg instance +//------------------------------------------------------------------------------ +{% macro add_hdl_path_slices(node, inst_ref) -%} +{%- if node.get_property('hdl_path') %} +{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path')}}", -1, -1); +{%- endif -%} + +{%- if node.get_property('hdl_path_gate') %} +{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path_gate')}}", -1, -1, 0, "GATE"); +{%- endif -%} + +{%- for field in node.fields() %} +{%- if field.get_property('hdl_path_slice') is none -%} +{%- elif field.get_property('hdl_path_slice')|length == 1 %} +{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_slice')[0]}}", {{field.lsb}}, {{field.width}}); +{%- elif field.get_property('hdl_path_slice')|length == field.width %} +{%- for slice in field.get_property('hdl_path_slice') %} +{%- if field.msb > field.lsb %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1); +{%- else %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1); +{%- endif %} +{%- endfor %} +{%- endif %} +{%- endfor -%} + +{%- for field in node.fields() %} +{%- if field.get_property('hdl_path_gate_slice') is none -%} +{%- elif field.get_property('hdl_path_gate_slice')|length == 1 %} +{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_gate_slice')[0]}}", {{field.lsb}}, {{field.width}}, 0, "GATE"); +{%- elif field.get_property('hdl_path_gate_slice')|length == field.width %} +{%- for slice in field.get_property('hdl_path_gate_slice') %} +{%- if field.msb > field.lsb %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1, 0, "GATE"); +{%- else %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1, 0, "GATE"); +{%- endif %} +{%- endfor %} +{%- endif %} +{%- endfor %} +{%- endmacro %} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/main.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/main.sv new file mode 100644 index 0000000000000000000000000000000000000000..f6dc1c077e75bb24449252a424f136d11ff36ffe --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/main.sv @@ -0,0 +1,16 @@ +{%- import 'uvm_reg.sv' as uvm_reg with context -%} +{%- macro top() -%} +{%- for node in top_node.descendants(in_post_order=True) -%} + {{child_smp(node)}} +{%- endfor -%} +{%- endmacro -%} + +{%- macro child_smp(node) -%} + {%- if isinstance(node, RegNode) -%} + {% if not node.is_virtual %} +{{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"SAMPLE FUNCTIONS -----------------------*/"}} +{{uvm_reg.function_sample_def(node)}} +{{uvm_reg.function_sample_values_def(node)}} + {%- endif %} + {%- endif -%} +{%- endmacro %} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/top_pkg.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/top_pkg.sv new file mode 100644 index 0000000000000000000000000000000000000000..429fcd633da5380f71075c62db8dfde9723bca9a --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/top_pkg.sv @@ -0,0 +1,20 @@ +{%- import 'main.sv' as main with context -%} +{%- raw -%} +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +{% endraw %} +{{ "`ifndef" }} {{top_node.get_path()|upper}}_SAMPLE + {{ "`define" }} {{top_node.get_path()|upper}}_SAMPLE + {{main.top()|indent}} +{{ "`endif" }} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/uvm_reg.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/uvm_reg.sv new file mode 100644 index 0000000000000000000000000000000000000000..bf30f1187bc160f3e95f01c06caf4fdfbc0fef3b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/smp/uvm_reg.sv @@ -0,0 +1,288 @@ +{% import 'utils.sv' as utils with context %} + +//------------------------------------------------------------------------------ +// uvm_reg definition +//------------------------------------------------------------------------------ +{% macro class_definition(node) -%} +{%- if class_needs_definition(node) %} +// {{get_class_friendly_name(node)}} +class {{get_class_name(node)}} extends uvm_reg; +{%- if use_uvm_factory %} + `uvm_object_utils({{get_class_name(node)}}) +{%- endif %} + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; +{% for field in node.fields() %} + {{bit_covergroup_name(node)|indent}} {{bit_covergroup_inst(field)}}[{{field.width}}]; +{%- endfor %} + {{fld_covergroup_name(node)|indent}} fld_cg; + {{child_insts(node)|indent}} + {{function_new(node)|indent}} + {{function_sample_values(node)|indent}} + {{function_sample(node)|indent}} + + {{function_build(node)|indent}} +endclass : {{get_class_name(node)}} +{% endif -%} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Definitions +//------------------------------------------------------------------------------ +{% macro cg_definition(node) %} +{{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"COVERGROUPS -----------------------*/"}} +covergroup {{bit_covergroup_name(node)}} with function sample(input bit reg_bit); + option.per_instance = 1; + {{bit_coverpoint()|indent}} +endgroup +covergroup {{fld_covergroup_name(node)}} with function sample({{covergroup_inputs(node)}}); + option.per_instance = 1; + {{fld_coverpoints(node)|indent}} +endgroup +{% endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Inputs +//------------------------------------------------------------------------------ +{% macro covergroup_inputs(node) %} +{% for field in node.fields() -%} +input bit [{{field.width}}-1:0] {{get_inst_name(field)}}{% if not loop.last %}{{","}}{% endif %} +{% endfor %} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Coverpoint Definitions +//------------------------------------------------------------------------------ +{%- macro fld_coverpoints(node) -%} +{%- for field in node.fields() -%} +{{field_coverpoint(field)}} +{%- endfor -%} +{%- endmacro -%} + + +//------------------------------------------------------------------------------ +// Singular Coverpoint Definition +//------------------------------------------------------------------------------ +{%- macro bit_coverpoint() -%} +reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; +} +reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); +} +{% endmacro %} +{%- macro field_coverpoint(field) -%} +{{get_inst_name(field)}}_cp : coverpoint {{get_inst_name(field)}}; +{% endmacro %} + + +//------------------------------------------------------------------------------ +// Child instances +//------------------------------------------------------------------------------ +{% macro child_insts(node) -%} +{%- for field in node.fields() -%} +rand uvm_reg_field {{get_inst_name(field)}}; +{% endfor -%} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// new() function +//------------------------------------------------------------------------------ +{% macro function_new(node) -%} +function new(string name = "{{get_class_name(node)}}"); + super.new(name, {{node.get_property('regwidth')}}, build_coverage(UVM_CVR_ALL)); +endfunction : new +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample() function declaration +//------------------------------------------------------------------------------ +{% macro function_sample(node) -%} +extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample_values() function declaration +//------------------------------------------------------------------------------ +{% macro function_sample_values(node) -%} +extern virtual function void sample_values(); +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample() function definition +//------------------------------------------------------------------------------ +{%- macro function_sample_def(node) -%} +function void {{get_class_name(node)}}::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample(data[{{field.lsb}} + bt]); +{%- endfor %} + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample({{covergroup_sample_args(node)}}); + end +endfunction +{% endmacro -%} + + +//------------------------------------------------------------------------------ +// sample_values() function definition +//------------------------------------------------------------------------------ +{%- macro function_sample_values_def(node) -%} +function void {{get_class_name(node)}}::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample({{get_inst_name(field)}}.get_mirrored_value() >> bt); +{%- endfor %} + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample({{covergroup_sample_values_args(node)}}); + end +endfunction +{% endmacro %} + + +//------------------------------------------------------------------------------ +// build() function +//------------------------------------------------------------------------------ +{% macro function_build(node) -%} +virtual function void build(); + {%- for field in node.fields() %} + {%- if use_uvm_factory %} + this.{{get_inst_name(field)}} = uvm_reg_field::type_id::create("{{get_inst_name(field)}}"); + {%- else %} + this.{{get_inst_name(field)}} = new("{{get_inst_name(field)}}"); + {%- endif %} + this.{{get_inst_name(field)}}.configure(this, {{field.width}}, {{field.lsb}}, "{{get_field_access(field)}}", {{field.is_volatile|int}}, {{"'h%x" % field.get_property('reset', default=0)}}, {{field.get_property('reset') is not none|int}}, 1, 0); + {%- endfor %} + if (has_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) {{bit_covergroup_inst(field)}}[bt] = new(); +{%- endfor %} + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); +endfunction : build +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Name +//------------------------------------------------------------------------------ +{% macro bit_covergroup_name(node) -%} {{get_class_name(node)}}_bit_cg {%- endmacro %} +{% macro bit_covergroup_inst(field) -%} {{"%s_bit_cg"|format(get_inst_name(field))}} {%- endmacro %} +{% macro fld_covergroup_name(node) -%} {{get_class_name(node)}}_fld_cg {%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Constructor Arguments +//------------------------------------------------------------------------------ +{% macro covergroup_new_args(node) -%} + {%- for field in node.fields() %} {{covergroup_new_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_new_arg(field) -%} + {{get_inst_name(field)}}.get_reset() +{%- endmacro %} +{% macro covergroup_sample_args(node) -%} + {%- for field in node.fields() %} {{covergroup_sample_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_sample_arg(field) -%} + data[{{field.msb}}:{{field.lsb}}]{{"/*%s*/"|format(get_inst_name(field))}} +{%- endmacro %} +{% macro covergroup_sample_values_args(node) -%} + {%- for field in node.fields() %} {{covergroup_sample_values_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_sample_values_arg(field) -%} + {{get_inst_name(field)}}.get_mirrored_value() +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// build() actions for uvm_reg instance (called by parent) +//------------------------------------------------------------------------------ +{% macro build_instance(node) -%} +{%- if node.is_array %} +foreach(this.{{get_inst_name(node)}}[{{utils.array_iterator_list(node)}}]) begin + {%- if use_uvm_factory %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = {{get_class_name(node)}}::type_id::create($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}})); + {%- else %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = new($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}})); + {%- endif %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.configure(this); + {{add_hdl_path_slices(node, get_inst_name(node) + utils.array_iterator_suffix(node))|trim|indent}} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.build(); + this.default_map.add_reg(this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}, {{get_array_address_offset_expr(node)}}); +end +{%- else %} +{%- if use_uvm_factory %} +this.{{get_inst_name(node)}} = {{get_class_name(node)}}::type_id::create("{{get_inst_name(node)}}"); +{%- else %} +this.{{get_inst_name(node)}} = new("{{get_inst_name(node)}}"); +{%- endif %} +this.{{get_inst_name(node)}}.configure(this); +{{add_hdl_path_slices(node, get_inst_name(node))|trim}} +this.{{get_inst_name(node)}}.build(); +this.default_map.add_reg(this.{{get_inst_name(node)}}, {{"'h%x" % node.raw_address_offset}}); +{%- endif %} +{%- endmacro %} + +//------------------------------------------------------------------------------ +// Load HDL path slices for this reg instance +//------------------------------------------------------------------------------ +{% macro add_hdl_path_slices(node, inst_ref) -%} +{%- if node.get_property('hdl_path') %} +{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path')}}", -1, -1); +{%- endif -%} + +{%- if node.get_property('hdl_path_gate') %} +{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path_gate')}}", -1, -1, 0, "GATE"); +{%- endif -%} + +{%- for field in node.fields() %} +{%- if field.get_property('hdl_path_slice') is none -%} +{%- elif field.get_property('hdl_path_slice')|length == 1 %} +{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_slice')[0]}}", {{field.lsb}}, {{field.width}}); +{%- elif field.get_property('hdl_path_slice')|length == field.width %} +{%- for slice in field.get_property('hdl_path_slice') %} +{%- if field.msb > field.lsb %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1); +{%- else %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1); +{%- endif %} +{%- endfor %} +{%- endif %} +{%- endfor -%} + +{%- for field in node.fields() %} +{%- if field.get_property('hdl_path_gate_slice') is none -%} +{%- elif field.get_property('hdl_path_gate_slice')|length == 1 %} +{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_gate_slice')[0]}}", {{field.lsb}}, {{field.width}}, 0, "GATE"); +{%- elif field.get_property('hdl_path_gate_slice')|length == field.width %} +{%- for slice in field.get_property('hdl_path_gate_slice') %} +{%- if field.msb > field.lsb %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1, 0, "GATE"); +{%- else %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1, 0, "GATE"); +{%- endif %} +{%- endfor %} +{%- endif %} +{%- endfor %} +{%- endmacro %} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/uvm/main.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/uvm/main.sv new file mode 100644 index 0000000000000000000000000000000000000000..e3bdff560f200920ca4f173e40346b6a633266bc --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/uvm/main.sv @@ -0,0 +1,37 @@ +{% import 'uvm_reg.sv' as uvm_reg with context %} +{% import 'uvm_vreg.sv' as uvm_vreg with context %} +{% import 'uvm_reg_block-mem.sv' as uvm_reg_block_mem with context %} +{% import 'uvm_reg_block.sv' as uvm_reg_block with context %} + + +{% macro top() -%} +{{include_covergroups(top_node)}} + {%- for node in top_node.descendants(in_post_order=True) -%} + {{child_def(node)}} + {%- endfor -%} + {{child_def(top_node)}} +{{include_sample(top_node)}} +{%- endmacro %} + + +{% macro child_def(node) -%} + {%- if isinstance(node, RegNode) -%} + {%- if node.is_virtual -%} + {{uvm_vreg.class_definition(node)}} + {%- else -%} + {{uvm_reg.class_definition(node)}} + {%- endif -%} + {%- elif isinstance(node, (RegfileNode, AddrmapNode)) -%} + {{uvm_reg_block.class_definition(node)}} + {%- elif isinstance(node, MemNode) -%} + {{uvm_reg_block_mem.class_definition(node)}} + {%- endif -%} +{%- endmacro %} + +{% macro include_covergroups(node) -%} +`include "{{get_class_name(node)}}_covergroups.svh" +{%- endmacro %} + +{% macro include_sample(node) -%} +`include "{{get_class_name(node)}}_sample.svh" +{%- endmacro %} diff --git a/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/uvm/uvm_reg.sv b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/uvm/uvm_reg.sv new file mode 100644 index 0000000000000000000000000000000000000000..bf30f1187bc160f3e95f01c06caf4fdfbc0fef3b --- /dev/null +++ b/snapshots/chipsalliance_adams-bridge_pr82/tools/templates/rdl/uvm/uvm_reg.sv @@ -0,0 +1,288 @@ +{% import 'utils.sv' as utils with context %} + +//------------------------------------------------------------------------------ +// uvm_reg definition +//------------------------------------------------------------------------------ +{% macro class_definition(node) -%} +{%- if class_needs_definition(node) %} +// {{get_class_friendly_name(node)}} +class {{get_class_name(node)}} extends uvm_reg; +{%- if use_uvm_factory %} + `uvm_object_utils({{get_class_name(node)}}) +{%- endif %} + protected uvm_reg_data_t m_current; + protected uvm_reg_data_t m_data; + protected bit m_is_read; +{% for field in node.fields() %} + {{bit_covergroup_name(node)|indent}} {{bit_covergroup_inst(field)}}[{{field.width}}]; +{%- endfor %} + {{fld_covergroup_name(node)|indent}} fld_cg; + {{child_insts(node)|indent}} + {{function_new(node)|indent}} + {{function_sample_values(node)|indent}} + {{function_sample(node)|indent}} + + {{function_build(node)|indent}} +endclass : {{get_class_name(node)}} +{% endif -%} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Definitions +//------------------------------------------------------------------------------ +{% macro cg_definition(node) %} +{{"/*-----------------------"}} {{get_class_name(node)|upper}} {{"COVERGROUPS -----------------------*/"}} +covergroup {{bit_covergroup_name(node)}} with function sample(input bit reg_bit); + option.per_instance = 1; + {{bit_coverpoint()|indent}} +endgroup +covergroup {{fld_covergroup_name(node)}} with function sample({{covergroup_inputs(node)}}); + option.per_instance = 1; + {{fld_coverpoints(node)|indent}} +endgroup +{% endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Inputs +//------------------------------------------------------------------------------ +{% macro covergroup_inputs(node) %} +{% for field in node.fields() -%} +input bit [{{field.width}}-1:0] {{get_inst_name(field)}}{% if not loop.last %}{{","}}{% endif %} +{% endfor %} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Coverpoint Definitions +//------------------------------------------------------------------------------ +{%- macro fld_coverpoints(node) -%} +{%- for field in node.fields() -%} +{{field_coverpoint(field)}} +{%- endfor -%} +{%- endmacro -%} + + +//------------------------------------------------------------------------------ +// Singular Coverpoint Definition +//------------------------------------------------------------------------------ +{%- macro bit_coverpoint() -%} +reg_bit_cp : coverpoint reg_bit { + bins value[2] = {0,1}; +} +reg_bit_edge_cp : coverpoint reg_bit { + bins rise = (0 => 1); + bins fall = (1 => 0); +} +{% endmacro %} +{%- macro field_coverpoint(field) -%} +{{get_inst_name(field)}}_cp : coverpoint {{get_inst_name(field)}}; +{% endmacro %} + + +//------------------------------------------------------------------------------ +// Child instances +//------------------------------------------------------------------------------ +{% macro child_insts(node) -%} +{%- for field in node.fields() -%} +rand uvm_reg_field {{get_inst_name(field)}}; +{% endfor -%} +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// new() function +//------------------------------------------------------------------------------ +{% macro function_new(node) -%} +function new(string name = "{{get_class_name(node)}}"); + super.new(name, {{node.get_property('regwidth')}}, build_coverage(UVM_CVR_ALL)); +endfunction : new +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample() function declaration +//------------------------------------------------------------------------------ +{% macro function_sample(node) -%} +extern protected virtual function void sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample_values() function declaration +//------------------------------------------------------------------------------ +{% macro function_sample_values(node) -%} +extern virtual function void sample_values(); +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// sample() function definition +//------------------------------------------------------------------------------ +{%- macro function_sample_def(node) -%} +function void {{get_class_name(node)}}::sample(uvm_reg_data_t data, + uvm_reg_data_t byte_en, + bit is_read, + uvm_reg_map map); + m_current = get(); + m_data = data; + m_is_read = is_read; + if (get_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample(data[{{field.lsb}} + bt]); +{%- endfor %} + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample({{covergroup_sample_args(node)}}); + end +endfunction +{% endmacro -%} + + +//------------------------------------------------------------------------------ +// sample_values() function definition +//------------------------------------------------------------------------------ +{%- macro function_sample_values_def(node) -%} +function void {{get_class_name(node)}}::sample_values(); + if (get_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) this.{{bit_covergroup_inst(field)}}[bt].sample({{get_inst_name(field)}}.get_mirrored_value() >> bt); +{%- endfor %} + end + if (get_coverage(UVM_CVR_FIELD_VALS)) begin + this.fld_cg.sample({{covergroup_sample_values_args(node)}}); + end +endfunction +{% endmacro %} + + +//------------------------------------------------------------------------------ +// build() function +//------------------------------------------------------------------------------ +{% macro function_build(node) -%} +virtual function void build(); + {%- for field in node.fields() %} + {%- if use_uvm_factory %} + this.{{get_inst_name(field)}} = uvm_reg_field::type_id::create("{{get_inst_name(field)}}"); + {%- else %} + this.{{get_inst_name(field)}} = new("{{get_inst_name(field)}}"); + {%- endif %} + this.{{get_inst_name(field)}}.configure(this, {{field.width}}, {{field.lsb}}, "{{get_field_access(field)}}", {{field.is_volatile|int}}, {{"'h%x" % field.get_property('reset', default=0)}}, {{field.get_property('reset') is not none|int}}, 1, 0); + {%- endfor %} + if (has_coverage(UVM_CVR_REG_BITS)) begin +{%- for field in node.fields() %} + foreach({{bit_covergroup_inst(field)}}[bt]) {{bit_covergroup_inst(field)}}[bt] = new(); +{%- endfor %} + end + if (has_coverage(UVM_CVR_FIELD_VALS)) + fld_cg = new(); +endfunction : build +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Name +//------------------------------------------------------------------------------ +{% macro bit_covergroup_name(node) -%} {{get_class_name(node)}}_bit_cg {%- endmacro %} +{% macro bit_covergroup_inst(field) -%} {{"%s_bit_cg"|format(get_inst_name(field))}} {%- endmacro %} +{% macro fld_covergroup_name(node) -%} {{get_class_name(node)}}_fld_cg {%- endmacro %} + + +//------------------------------------------------------------------------------ +// Covergroup Constructor Arguments +//------------------------------------------------------------------------------ +{% macro covergroup_new_args(node) -%} + {%- for field in node.fields() %} {{covergroup_new_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_new_arg(field) -%} + {{get_inst_name(field)}}.get_reset() +{%- endmacro %} +{% macro covergroup_sample_args(node) -%} + {%- for field in node.fields() %} {{covergroup_sample_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_sample_arg(field) -%} + data[{{field.msb}}:{{field.lsb}}]{{"/*%s*/"|format(get_inst_name(field))}} +{%- endmacro %} +{% macro covergroup_sample_values_args(node) -%} + {%- for field in node.fields() %} {{covergroup_sample_values_arg(field)}} {% if loop.last %} {{''}} {% else %} {{","}} {% endif %} {%- endfor %} +{%- endmacro %} +{% macro covergroup_sample_values_arg(field) -%} + {{get_inst_name(field)}}.get_mirrored_value() +{%- endmacro %} + + +//------------------------------------------------------------------------------ +// build() actions for uvm_reg instance (called by parent) +//------------------------------------------------------------------------------ +{% macro build_instance(node) -%} +{%- if node.is_array %} +foreach(this.{{get_inst_name(node)}}[{{utils.array_iterator_list(node)}}]) begin + {%- if use_uvm_factory %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = {{get_class_name(node)}}::type_id::create($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}})); + {%- else %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = new($sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}})); + {%- endif %} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.configure(this); + {{add_hdl_path_slices(node, get_inst_name(node) + utils.array_iterator_suffix(node))|trim|indent}} + this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.build(); + this.default_map.add_reg(this.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}, {{get_array_address_offset_expr(node)}}); +end +{%- else %} +{%- if use_uvm_factory %} +this.{{get_inst_name(node)}} = {{get_class_name(node)}}::type_id::create("{{get_inst_name(node)}}"); +{%- else %} +this.{{get_inst_name(node)}} = new("{{get_inst_name(node)}}"); +{%- endif %} +this.{{get_inst_name(node)}}.configure(this); +{{add_hdl_path_slices(node, get_inst_name(node))|trim}} +this.{{get_inst_name(node)}}.build(); +this.default_map.add_reg(this.{{get_inst_name(node)}}, {{"'h%x" % node.raw_address_offset}}); +{%- endif %} +{%- endmacro %} + +//------------------------------------------------------------------------------ +// Load HDL path slices for this reg instance +//------------------------------------------------------------------------------ +{% macro add_hdl_path_slices(node, inst_ref) -%} +{%- if node.get_property('hdl_path') %} +{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path')}}", -1, -1); +{%- endif -%} + +{%- if node.get_property('hdl_path_gate') %} +{{inst_ref}}.add_hdl_path_slice("{{node.get_property('hdl_path_gate')}}", -1, -1, 0, "GATE"); +{%- endif -%} + +{%- for field in node.fields() %} +{%- if field.get_property('hdl_path_slice') is none -%} +{%- elif field.get_property('hdl_path_slice')|length == 1 %} +{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_slice')[0]}}", {{field.lsb}}, {{field.width}}); +{%- elif field.get_property('hdl_path_slice')|length == field.width %} +{%- for slice in field.get_property('hdl_path_slice') %} +{%- if field.msb > field.lsb %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1); +{%- else %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1); +{%- endif %} +{%- endfor %} +{%- endif %} +{%- endfor -%} + +{%- for field in node.fields() %} +{%- if field.get_property('hdl_path_gate_slice') is none -%} +{%- elif field.get_property('hdl_path_gate_slice')|length == 1 %} +{{inst_ref}}.add_hdl_path_slice("{{field.get_property('hdl_path_gate_slice')[0]}}", {{field.lsb}}, {{field.width}}, 0, "GATE"); +{%- elif field.get_property('hdl_path_gate_slice')|length == field.width %} +{%- for slice in field.get_property('hdl_path_gate_slice') %} +{%- if field.msb > field.lsb %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb - loop.index0}}, 1, 0, "GATE"); +{%- else %} +{{inst_ref}}.add_hdl_path_slice("{{slice}}", {{field.msb + loop.index0}}, 1, 0, "GATE"); +{%- endif %} +{%- endfor %} +{%- endif %} +{%- endfor %} +{%- endmacro %} diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_alias_width_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_alias_width_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..f093111b2aace451d4f671f87d8d0b0ae8b8432f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_alias_width_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_assert_imm_nz_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_assert_imm_nz_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..7e5bcdfe5b022885e0ac2309efaf85803561831e --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_assert_imm_nz_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(expect_filename=test.golden_filename, verilator_flags2=['--assert'], fails=True) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_auto1.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_auto1.v new file mode 100644 index 0000000000000000000000000000000000000000..a7cba372ad8d0469ac56dd0c1752cb640ac0cadf --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_auto1.v @@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + localparam // synopsys enum En_State + EP_State_IDLE = {3'b000,5'd00}, + EP_State_CMDSHIFT0 = {3'b001,5'd00}, + EP_State_CMDSHIFT13 = {3'b001,5'd13}, + EP_State_CMDSHIFT14 = {3'b001,5'd14}, + EP_State_CMDSHIFT15 = {3'b001,5'd15}, + EP_State_CMDSHIFT16 = {3'b001,5'd16}, + EP_State_DWAIT = {3'b010,5'd00}, + EP_State_DSHIFT0 = {3'b100,5'd00}, + EP_State_DSHIFT1 = {3'b100,5'd01}, + EP_State_DSHIFT15 = {3'b100,5'd15}; + + reg [7:0] /* synopsys enum En_State */ + m_state_xr; // Last command, for debugging + /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ + // Beginning of automatic ASCII enum decoding + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + always @(m_state_xr) begin + case ({m_state_xr}) + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; + endcase + end + // End of automatics + + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + m_state_xr <= EP_State_IDLE; + end + if (cyc==2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + end + if (cyc==3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + end + if (cyc==4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + end + if (cyc==9) begin + if (m_stateAscii_xr != "dwait ") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_genx_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_genx_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..09c1b53929df396febb12ad3b46e085cc21fa702 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_genx_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_case_genx_bad.v:14:9: Use of x/? constant in generate case statement, (no such thing as 'generate casez') + : ... note: In instance 't' + 14 | 32'b1xxx: initial begin end + | ^~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_zx_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_zx_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..a99363d78b431219d48f0e5d7b8da9c309fd3c37 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_case_zx_bad.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + value + ); + + input [3:0] value; + always @ (/*AS*/value) begin + casez (value) + 4'b0000: $stop; + 4'b1xxx: $stop; + default: $stop; + endcase + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_extends1.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_extends1.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_extends1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_extern_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_extern_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_extern_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_field_name.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_field_name.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_field_name.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_hier_construction.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_hier_construction.v new file mode 100644 index 0000000000000000000000000000000000000000..e624881362d46688d15297a07dbe9a1de63a93f8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_hier_construction.v @@ -0,0 +1,89 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Petr Nohavica +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +interface class IBottomMid; + pure virtual function void moo(int i); +endclass + +interface class IBottom; + pure virtual function bit foo(); +endclass + +interface class IMid extends IBottomMid; + pure virtual function string bar(); +endclass + +class bottom_class implements IBottom; + string name; + + function new(string name); + this.name = name; + endfunction + + virtual function bit foo(); + $display("%s", name); + return 1'b0; + endfunction +endclass + +class middle_class extends bottom_class implements IMid, IBottom; + function new(string name); + super.new($sformatf("middle %0s", name)); + endfunction + + virtual function bit foo(); + $display("%s", name); + return 0; + endfunction + + virtual function void moo(int i); + $display("moo: %d", i); + endfunction + + virtual function string bar(); + return name; + endfunction +endclass + +class top_class extends middle_class; + int i; + function new(string name, int i); + super.new($sformatf("%0s %0d", name, i)); + this.i = i; + endfunction +endclass + +class sky_class extends top_class; + function new(string name); + super.new(name, 42); + endfunction +endclass + + +module t; + + initial begin + sky_class s = new("ahoj"); + bottom_class b = s; + top_class t = s; + IMid im; + + `checks( b.name, "middle ahoj 42" ); + `checks( s.name, "middle ahoj 42" ); + `checks( t.name, "middle ahoj 42" ); + `checkh( t.i, 42); + `checks(s.bar(), "middle ahoj 42"); + im = s; + im.moo(42); + + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_misstatic_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_misstatic_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..368cfffae4b0d8000ed973335cd86e92a571a683 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_misstatic_bad.out @@ -0,0 +1,14 @@ +%Error: t/t_class_misstatic_bad.v:31:5: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + : ... note: In instance 't' + 31 | nonstatic(); + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_class_misstatic_bad.v:38:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + : ... note: In instance 't' + 38 | Cls::nonstatic(); + | ^~~~~~~~~ +%Error: t/t_class_misstatic_bad.v:44:10: Cannot call non-static member function 'nonstatic' without object (IEEE 1800-2023 8.10) + : ... note: In instance 't' + 44 | Cls::nonstatic(); + | ^~~~~~~~~ +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_new_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_new_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..0b66b6eb5e22fc08a3e03e1ab2606fc002976e17 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_new_bad.out @@ -0,0 +1,34 @@ +%Error: t/t_class_new_bad.v:27:19: class 'new()' cannot be static (IEEE 1800-2023 18.3) + : ... note: In instance 't' + 27 | static function new(); + | ^~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_class_new_bad.v:32:20: class 'new()' cannot be virual (IEEE 1800-2023 18.3) + : ... note: In instance 't' + 32 | virtual function new(); + | ^~~ +%Error: t/t_class_new_bad.v:39:19: class 'new()' cannot be virual (IEEE 1800-2023 18.3) + : ... note: In instance 't' + 39 | function ClsNew3::new(); + | ^~~ +%Error: t/t_class_new_bad.v:47:16: Too many arguments in function call to FUNC 'new' + : ... note: In instance 't' + 47 | c1 = new(3); + | ^ +%Error: t/t_class_new_bad.v:48:16: Too many arguments in function call to FUNC 'new' + : ... note: In instance 't' + 48 | c2 = new(3); + | ^ +%Error: t/t_class_new_bad.v:49:12: Missing argument on non-defaulted argument 'i' in function call to FUNC 'new' + : ... note: In instance 't' + 49 | c3 = new(); + | ^~~ +%Error: t/t_class_new_bad.v:50:12: dynamic new() not expected in this context (data type must be dynamic array) + : ... note: In instance 't' + 50 | c1 = new[2]; + | ^~~ +%Error: Internal Error: t/t_class_new_bad.v:50:12: ../V3Width.cpp:#: Node has no type + : ... note: In instance 't' + 50 | c1 = new[2]; + | ^~~ + ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_new_this.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_new_this.v new file mode 100644 index 0000000000000000000000000000000000000000..01e230494d500b5461c17002ec28ebb1474f28b0 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_new_this.v @@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +interface class ICls; + pure virtual function string get(); +endclass + +class Cls; + string name; + ICls icls; + function new(string name, ICls icls); + this.name = name; + this.icls = icls; + endfunction +endclass + +class Testcase implements ICls; + Cls cls = new("test_class", this); + virtual function string get(); + return "In ICls"; + endfunction + function Testcase clone(); + Testcase a = new this; + return a; + endfunction +endclass + +module t; + + initial begin + Testcase test; + Testcase cloned; + test = new; + if (test.cls.name != "test_class") $stop; + if (test.cls.icls.get() != "In ICls") $stop; + + cloned = test.clone(); + if (cloned.cls.name != "test_class") $stop; + + test.cls.icls = null; // Prevent leak + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_static.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_static.py new file mode 100644 index 0000000000000000000000000000000000000000..f989a35fba48e9296a99e2bbd170562f05e90b6f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_static.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_type.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_type.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_type.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_type.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_type.v new file mode 100644 index 0000000000000000000000000000000000000000..d00d1ece4ce0f0a309d5aa200af6aeb467f68b88 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_type.v @@ -0,0 +1,165 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +// See also t_class_param.v + +class Parcls #(type T); + static function int get_p; + return T::get_p(); + endfunction +endclass + +class Cls; + static function int get_p; + return 20; + endfunction +endclass + +class ParclsDefaultType #(type T=Cls); + static function int get_p; + return T::get_p(); + endfunction +endclass + +typedef Cls cls_t; +typedef cls_t cls2_t; + +class Singleton #(type T=int); + static function Singleton#(T) self; + static Singleton#(T) c = new; + return c; + endfunction + function int get_size; + return $bits(T); + endfunction +endclass + +class SingletonUnusedDefault #(type T=int); + static function SingletonUnusedDefault#(T) self; + static SingletonUnusedDefault#(T) c = new; + return c; + endfunction +endclass + +class Empty; +endclass + +class Foo #(type IF=Empty) extends IF; + typedef Foo foo_t; + int a = 1; +endclass + +class Bar #(type A=int, type B=A) extends Foo#(); + function int get_size_A; + return $bits(A); + endfunction + function int get_size_B; + return $bits(B); + endfunction +endclass + +class Empty2; +endclass + +class Baz #(type T=Empty2) extends Foo#(); +endclass + +class Getter1 extends Baz#(); + function int get_1; + foo_t f = new; + return f.a; + endfunction +endclass + +class MyInt1; + int x = 1; +endclass + +class MyInt2; + int x = 2; +endclass + +class ExtendsMyInt #(type T=MyInt1) extends T; + typedef ExtendsMyInt#(T) this_type; + function int get_this_type_x; + this_type t = new; + return t.x; + endfunction +endclass + +class StaticX; + static int val = 1; +endclass + +class GetStaticXVal #(type T = int); + static function int get; + return T::val; + endfunction +endclass + +module t; + + initial begin + automatic ParclsDefaultType#(Cls) pdt1 = new; + automatic ParclsDefaultType#(cls_t) pdt2 = pdt1; + automatic ParclsDefaultType#(cls2_t) pdt3 = pdt2; + automatic Parcls#(Cls) p1 = new; + automatic Parcls#(cls_t) p2 = p1; + automatic Parcls#(cls2_t) p3 = p2; + + automatic Singleton #(int) s_int1 = Singleton#(int)::self(); + automatic Singleton #(int) s_int2 = Singleton#(int)::self(); + automatic Singleton #(bit) s_bit1 = Singleton#(bit)::self(); + automatic Singleton #(bit) s_bit2 = Singleton#(bit)::self(); + automatic SingletonUnusedDefault #(bit) sud1 = SingletonUnusedDefault#(bit)::self(); + automatic SingletonUnusedDefault #(bit) sud2 = SingletonUnusedDefault#(bit)::self(); + + automatic Getter1 getter1 = new; + + automatic ExtendsMyInt#() ext1 = new; + automatic ExtendsMyInt#(MyInt2) ext2 = new; + + automatic GetStaticXVal#(StaticX) get_statix_x_val = new; + + typedef bit my_bit_t; + Bar#(.A(my_bit_t)) bar_a_bit = new; + Bar#(.B(my_bit_t)) bar_b_bit = new; + Bar#() bar_default = new; + + if (bar_a_bit.get_size_A != 1) $stop; + if (bar_a_bit.get_size_B != 1) $stop; + if (bar_b_bit.get_size_A != 32) $stop; + if (bar_b_bit.get_size_B != 1) $stop; + if (bar_default.get_size_A != 32) $stop; + if (bar_default.get_size_B != 32) $stop; + + if (pdt1 != pdt2) $stop; + if (pdt2 != pdt3) $stop; + if (p1 != p2) $stop; + if (p2 != p3) $stop; + + if (s_int1 != s_int2) $stop; + if (s_bit1 != s_bit2) $stop; + if (sud1 != sud2) $stop; + + if (s_int1.get_size() != 32) $stop; + if (s_bit1.get_size() != 1) $stop; + + if (p1.get_p() != 20) $stop; + if (pdt1.get_p() != 20) $stop; + if (Parcls#(cls2_t)::get_p() != 20) $stop; + + if (getter1.get_1() != 1) $stop; + + if (ext1.get_this_type_x() != 1) $stop; + if (ext2.get_this_type_x() != 2) $stop; + + if (get_statix_x_val.get() != 1) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_typedef.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_typedef.v new file mode 100644 index 0000000000000000000000000000000000000000..d9f9f73ce167419422207ff4ab7e479347a99d95 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_typedef.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +class Foo #(type T=int); + typedef Foo#(T) this_type; + function int get_x; + return T::get_s_x(); + endfunction +endclass + +class Bar #(type S=int); + typedef Bar #(S) this_type; + typedef Foo#(this_type) foo_type; + function int get_x; + foo_type f = new; + return f.get_x(); + endfunction + static function int get_s_x; + return S::x; + endfunction +endclass + +class Cls1; + static int x = 1; + typedef Bar#(Cls1) type_id; +endclass + +class Cls2; + static int x = 2; + typedef Bar#(Cls2) type_id; +endclass + +typedef int my_int; + +class ClsTypedefParam #(type T=my_int); + int x; +endclass + +class uvm_sequencer #(type REQ=int, RSP=REQ); + int x; + typedef uvm_sequencer #(REQ, RSP) this_type; +endclass + +module t; + initial begin + Cls1::type_id bar1 = new; + Cls2::type_id bar2 = new; + + ClsTypedefParam #(int) cls_int = new; + ClsTypedefParam#() cls_def; + + uvm_sequencer #(int, int) uvm_seq1 = new; + uvm_sequencer #(int, int)::this_type uvm_seq2; + + if (bar1.get_x() != 1) $stop; + if (bar2.get_x() != 2) $stop; + + cls_int.x = 1; + cls_def = cls_int; + if (cls_def.x != 1) $stop; + + uvm_seq1.x = 2; + uvm_seq2 = uvm_seq1; + if (uvm_seq2.x != 2) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_typedef6.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_typedef6.v new file mode 100644 index 0000000000000000000000000000000000000000..53f200f0ebc76b01e40ae6aa1686e01ab340313b --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_param_typedef6.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + + +`define stop $stop +`define checkd(gotv,expv) \ + do if ((gotv) !== (expv)) begin \ + $write("%%Error: %s:%0d: got=%0d exp=%0d\n", \ + `__FILE__,`__LINE__, (gotv), (expv)); \ + `stop; \ + end while(0); + +class pipeline_class #( + parameter type XWORD = logic +); + + typedef struct packed { + XWORD pc; + } if_id_t; + +endclass + +module pipe_reg #( + parameter type T = logic +)(); + initial begin + #1; + `checkd($bits(T), 8); + end +endmodule + +module the_top #() (); + + typedef logic [7:0] my_t; + typedef pipeline_class #(my_t)::if_id_t if_id2_t; + typedef if_id2_t if_id_t; + pipe_reg #(if_id_t) if_id_reg(); + + initial begin + #1; + #1; + `checkd($bits(if_id_t), 8); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_static_member.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_static_member.v new file mode 100644 index 0000000000000000000000000000000000000000..d4eef9eb2b9beb7973d2a1da52c7a28382a3447a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_static_member.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +class Cls; + class InnerCls; + static function int f_inner_cs_st(); + ++c_st; return c_st; + endfunction + endclass + + int c_no = 2; + //automatic int c_au = 2; // automatic not a legal keyword here + static int c_st = 22; + + function int f_c_no (); + ++c_no; return c_no; + endfunction + function int f_c_st (); + ++c_st; return c_st; + endfunction + + static function int f_cs_st (); + ++c_st; return c_st; + endfunction +endclass + +module t; + + Cls a = new; + Cls b = new; + + int v; + + initial begin + v = a.f_c_no(); `checkh(v, 3); + v = a.f_c_no(); `checkh(v, 4); + v = b.f_c_no(); `checkh(v, 3); + v = b.f_c_no(); `checkh(v, 4); + v = a.f_c_st(); `checkh(v, 23); + v = a.f_c_st(); `checkh(v, 24); + v = b.f_c_st(); `checkh(v, 25); + v = b.f_c_st(); `checkh(v, 26); + // + v = Cls::f_cs_st(); `checkh(v, 27); + v = Cls::InnerCls::f_inner_cs_st(); `checkh(v, 28); + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_super_new2.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_super_new2.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_class_super_new2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_config_top.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_config_top.py new file mode 100644 index 0000000000000000000000000000000000000000..ca0397f5840d5e2198a08a317b5bf43bb2a3fd0a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_config_top.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary', '--top cfg2']) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_constraint_method_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_constraint_method_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..30c3d4f77edfc2baaf78f7ff79007495eb329372 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_constraint_method_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_covergroup_in_class_colliding.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_covergroup_in_class_colliding.py new file mode 100644 index 0000000000000000000000000000000000000000..319c0ff4a91e5200e477781c498f9e7e97294d50 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_covergroup_in_class_colliding.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_detectarray_1.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_detectarray_1.py new file mode 100644 index 0000000000000000000000000000000000000000..51e61aa39044fd73e0c7884d7fd9d16beec7ce6f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_detectarray_1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["-Wno-UNOPTFLAT", "-fno-dfg"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dfg_3872.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dfg_3872.py new file mode 100644 index 0000000000000000000000000000000000000000..0b27c3dc012b9b3969cf152146efdca650b3fe67 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dfg_3872.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dfg_stats_patterns_pre_inline.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dfg_stats_patterns_pre_inline.out new file mode 100644 index 0000000000000000000000000000000000000000..a34f6037c3dd995364a71604024b6481eddb7e05 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dfg_stats_patterns_pre_inline.out @@ -0,0 +1,96 @@ +DFG 'pre inline' patterns with depth 1 + 9 (CONCAT _A:1 _B:a):b + 8 (REDXOR _A:a):1 + 3 (AND _A:a _B:a)*:a + 3 (NOT vA:a)*:a + 2 (REPLICATE _A:a cA:a)*:b + 1 (CONCAT '0:a _A:b):A + 1 (CONCAT _A:1 _B:1):a + 1 (NOT _A:a):a + 1 (REDXOR _A:a)*:1 + 1 (REPLICATE _A:1 cA:a)*:b + 1 (REPLICATE _A:a cA:b)*:b + 1 (REPLICATE _A:a cA:b)*:c + 1 (SEL@0 _A:a)*:1 + 1 (SEL@0 _A:a)*:b + 1 (SEL@A _A:a):1 + +DFG 'pre inline' patterns with depth 2 + 6 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:b):c):d + 3 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a + 3 (REDXOR (AND _A:a _B:a)*:a):1 + 1 (CONCAT '0:a (REPLICATE _A:a cA:a)*:b):A + 1 (CONCAT (REDXOR _A:a)*:1 (CONCAT _B:1 _C:b):c):d + 1 (CONCAT (REDXOR _A:a):1 (CONCAT _B:1 _C:1):b):c + 1 (CONCAT (REDXOR _A:a):1 (REDXOR _B:b)*:1):c + 1 (CONCAT (SEL@0 _A:a)*:1 (CONCAT _B:1 _C:b):c):d + 1 (NOT (REPLICATE _A:a cA:b)*:b):b + 1 (REDXOR (REPLICATE _A:1 cA:a)*:b):1 + 1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 + 1 (REDXOR (REPLICATE _A:a cA:a)*:b):1 + 1 (REDXOR (REPLICATE _A:a cA:b)*:b):1 + 1 (REDXOR (REPLICATE _A:a cA:b)*:c):1 + 1 (REDXOR (SEL@0 _A:a)*:b):1 + 1 (REPLICATE (NOT _A:a):a cA:a)*:b + 1 (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c + 1 (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c + 1 (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b + 1 (REPLICATE (SEL@A _A:a):1 cA:b)*:c + 1 (SEL@0 (AND _A:a _B:a)*:a)*:1 + 1 (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c + 1 (SEL@A (AND _A:a _B:a)*:a):1 + +DFG 'pre inline' patterns with depth 3 + 3 (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 + 2 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT '0:a (REPLICATE (REPLICATE _A:b cA:a)*:a cA:a)*:c):A + 1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e + 1 (CONCAT (REDXOR (REPLICATE _A:1 cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (CONCAT _C:1 _D:d):e):f):g + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b)*:1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:1):c):d):e + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:a)*:b):1 (CONCAT (REDXOR _B:c):1 (REDXOR _C:b)*:1):d):e + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:b):1 (CONCAT (REDXOR _B:c)*:1 (CONCAT _C:1 _D:d):e):f):g + 1 (CONCAT (REDXOR (REPLICATE _A:a cA:b)*:c):1 (CONCAT (REDXOR _B:b):1 (CONCAT _C:1 _D:d):e):f):g + 1 (CONCAT (REDXOR (SEL@0 _A:a)*:b):1 (REDXOR (REPLICATE _B:c cA:c)*:a)*:1):d + 1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b + 1 (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b + 1 (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 + 1 (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 + 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 + 1 (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 + 1 (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 + 1 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c + 1 (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a + 1 (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d + 1 (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d + 1 (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c + 1 (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 + 1 (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c + 1 (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 + +DFG 'pre inline' patterns with depth 4 + 1 (CONCAT '0:a (REPLICATE (REPLICATE (REPLICATE _A:b cA:a)*:c cA:a)*:a cA:a)*:d):A + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (REDXOR _C:a):1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (REDXOR (AND _A:a _B:a)*:a):1 (CONCAT (SEL@0 _C:a)*:1 (CONCAT _D:1 _E:b):c):d):e):f + 1 (CONCAT (REDXOR (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 (CONCAT (SEL@0 (AND _A:a _B:a)*:a)*:1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:c):d):e):b):f + 1 (CONCAT (REDXOR (REPLICATE (NOT _A:a):a cA:a)*:b):1 (CONCAT (REDXOR (SEL@0 _B:b)*:c):1 (REDXOR (REPLICATE _A:a cA:a)*:b)*:1):d):e + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:a)*:a):1 (CONCAT (REDXOR _C:d)*:1 (CONCAT _D:1 _E:e):f):g):h):i + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:b cA:b)*:c)*:1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:c):1 (CONCAT (REDXOR _C:d):1 (REDXOR _D:c)*:1):e):f):g + 1 (CONCAT (REDXOR (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):1 (CONCAT (REDXOR (REPLICATE _B:b cA:b)*:d)*:1 (CONCAT (REDXOR _C:d):1 (CONCAT _D:1 _E:1):e):f):g):h + 1 (CONCAT (REDXOR (REPLICATE (SEL@A _A:a):1 cA:b)*:c):1 (CONCAT (REDXOR (REPLICATE _B:c cB:b)*:d):1 (CONCAT (REDXOR _C:b):1 (CONCAT _D:1 _E:e):a):f):g):h + 1 (CONCAT (REDXOR (SEL@0 (REPLICATE _A:a cA:a)*:b)*:c):1 (REDXOR (REPLICATE (REPLICATE _B:d cA:a)*:a cA:a)*:b)*:1):e + 1 (CONCAT (SEL@0 (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a)*:1 (CONCAT (REDXOR (REPLICATE _A:1 cA:b)*:c):1 (CONCAT (REDXOR _B:d):1 (CONCAT _C:1 _D:a):e):f):g):c + 1 (NOT (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):a + 1 (REDXOR (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c):1 + 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a):1 + 1 (REDXOR (REPLICATE (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b cA:b)*:d)*:1 + 1 (REDXOR (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d):1 + 1 (REDXOR (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c):1 + 1 (REDXOR (SEL@0 (REPLICATE (NOT _A:a):a cA:a)*:b)*:c):1 + 1 (REPLICATE (NOT (REPLICATE (REPLICATE _A:a cA:b)*:c cA:b)*:b):b cA:b)*:d + 1 (REPLICATE (REPLICATE (REPLICATE (REPLICATE _A:1 cA:a)*:b cB:a)*:c cB:a)*:a cB:a)*:d + 1 (REPLICATE (REPLICATE (REPLICATE (SEL@A _A:a):1 cA:b)*:c cB:b)*:d cB:b)*:b + 1 (REPLICATE (REPLICATE (SEL@A (AND _A:a _B:a)*:a):1 cA:b)*:c cB:b)*:d + 1 (REPLICATE (SEL@A (AND (NOT vA:a)*:a (NOT vB:a)*:a)*:a):1 cA:b)*:c + 1 (SEL@0 (REPLICATE (NOT (REPLICATE _A:a cA:b)*:b):b cA:b)*:c)*:d + diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dist_getsetorder.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dist_getsetorder.py new file mode 100644 index 0000000000000000000000000000000000000000..ee921e959e7d153ae9eb2663981d797c336079d0 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dist_getsetorder.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Hacky import order checker, used to ensure all getters +# come before setters for consistent codegen when using autocxx (#5182) +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('dist') + + +def get_source_files(): + git_files = test.run_capture("cd " + test.root + " && git ls-files") + if test.verbose: + print("MF " + git_files) + files = {} + for filename in git_files.split(): + if filename == '': + continue + files[filename] = True + return files + + +if not os.path.exists(test.root + "/.git"): + test.skip("Not in a git repository") + +### Must trim output before and after our file list +files = get_source_files() + +for filename in sorted(files.keys()): + filename = os.path.join(test.root, filename) + if not os.path.exists(filename): # git file might be deleted but not yet staged + continue + if not re.search(r'include.*verilated.*\.[ch].*$', filename): + continue + if re.search(r'gtkwave', filename): + continue + + contents = test.file_contents(filename) + "\n\n" + seen_setters = {} + seen_getters = {} + lineno = 0 + for line in contents.splitlines(): + lineno += 1 + if re.search(r'^\s*\/\/', line): # skip commented lines + continue + #print("L "+line) + if re.search(r'^class', line): + seen_setters = {} + seen_getters = {} + if test.verbose: + print("C " + line) + continue + m = re.search(r'\s*void\s+([a-zA-Z0-9_]+)\([a-zA-Z0-9_]+.*', line) + if m: + setter_name = m.group(1) + if test.verbose: + print("S " + setter_name + " " + line) + seen_setters[setter_name] = True + m = re.search(r'\s*[a-zA-Z0-9_]+\s+([a-zA-Z0-9_]+)\(\s*\)', line) + if m: + getter_name = m.group(1) + if getter_name == "cycle" and re.search(r'verilated_sc_trace', filename): + continue # hardcoded check for cycle() which looks like a setter but isn't + if test.verbose: + print("G " + setter_name + " " + line) + if getter_name in seen_setters and getter_name not in seen_getters: + test.error(filename + ":" + str(lineno) + ": '" + getter_name + + "()' came after its setter; swap order") + seen_getters[getter_name] = True + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_export_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_export_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..33a25fe95eb011218f55beea5f42d4cc7cbec9cb --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_export_bad.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t; + export "DPI-C" task dpix_bad_missing; +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_export_context_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_export_context_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..b84ad228c96b82e23e35884584771b2e57e1e172 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_export_context_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["--exe", test.pli_filename], make_main=False) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_if_cond.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_if_cond.py new file mode 100644 index 0000000000000000000000000000000000000000..7323376c7253d500beab94fb6b55f6bdf3837a70 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_if_cond.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(v_flags2=["t/t_dpi_if_cond_c.cpp"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_import_c.cpp b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_import_c.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8bd090c6e0fd473a225c33f6aac2b159163be470 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_import_c.cpp @@ -0,0 +1,207 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "svdpi.h" + +#include +#include + +//====================================================================== + +// clang-format off +#if defined(VERILATOR) +# include "Vt_dpi_import__Dpi.h" +#elif defined(VCS) +# include "../vc_hdrs.h" +#elif defined(CADENCE) +# define NEED_EXTERNS +#else +# error "Unknown simulator for DPI test" +#endif +// clang-format on + +typedef struct { + int a; + int b; +} substruct_t; + +#ifdef NEED_EXTERNS +extern "C" { +// If get ncsim: *F,NOFDPI: Function {foo} not found in default libdpi. +// Then probably forgot to list a function here. + +extern unsigned char dpii_f_bit(unsigned char i); +extern svBitVecVal dpii_f_bit8(const svBitVecVal* i); +extern svBitVecVal dpii_f_bit9(const svBitVecVal* i); +extern svBitVecVal dpii_f_bit16(const svBitVecVal* i); +extern svBitVecVal dpii_f_bit17(const svBitVecVal* i); +extern svBitVecVal dpii_f_bit32(const svBitVecVal* i); +extern long long dpii_f_bit33(const svBitVecVal* i); +extern long long dpii_f_bit64(const svBitVecVal* i); +extern long long dpii_f_bit95(const svBitVecVal* i, svBitVecVal* o); +extern int dpii_f_int(int i); +extern char dpii_f_byte(char i); +extern short int dpii_f_shortint(short int i); +extern long long dpii_f_longint(long long i); +extern void* dpii_f_chandle(void* i); +extern const char* dpii_f_string(const char* i); +extern const char* dpii_f_null(); +extern double dpii_f_real(double i); +extern float dpii_f_shortreal(float i); + +extern void dpii_v_bit(unsigned char i, unsigned char* o); +extern void dpii_v_int(int i, int* o); +extern void dpii_v_uint(unsigned int i, unsigned int* o); +extern void dpii_v_byte(char i, char* o); +extern void dpii_v_shortint(short int i, short int* o); +extern void dpii_v_ushort(unsigned short i, unsigned short* o); +extern void dpii_v_longint(long long i, long long* o); +extern void dpii_v_ulong(unsigned long long i, unsigned long long* o); +extern void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o); +extern void dpii_v_substruct(const svBitVecVal* i, int* o); +extern void dpii_v_chandle(void* i, void** o); +extern void dpii_v_string(const char* i, const char** o); +extern void dpii_v_real(double i, double* o); +extern void dpii_v_shortreal(float i, float* o); + +extern void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o); +extern void dpii_v_substruct(const svBitVecVal* i, int* o); +extern void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o); +extern void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o); +extern void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o); + +extern void dpii_v_reg(unsigned char i, unsigned char* o); +extern void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o); +extern void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o); +extern void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o); +extern void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o); + +extern int dpii_f_strlen(const char* i); + +extern void dpii_f_void(); +extern int dpii_t_void(); +extern int dpii_t_void_context(); +extern int dpii_t_int(int i, int* o); + +extern int dpii_fa_bit(int i); +} +#endif + +//====================================================================== + +unsigned char dpii_f_bit(unsigned char i) { return 0x1 & ~i; } +svBitVecVal dpii_f_bit8(const svBitVecVal* i) { return 0xffUL & ~*i; } +svBitVecVal dpii_f_bit9(const svBitVecVal* i) { return 0x1ffUL & ~*i; } +svBitVecVal dpii_f_bit16(const svBitVecVal* i) { return 0xffffUL & ~*i; } +svBitVecVal dpii_f_bit17(const svBitVecVal* i) { return 0x1ffffUL & ~*i; } +svBitVecVal dpii_f_bit32(const svBitVecVal* i) { return ~*i; } +long long dpii_f_bit33(const svBitVecVal* i) { + return ((1ULL << 33) - 1) & ~((long long)(i[1]) << 32ULL | i[0]); +} +long long dpii_f_bit64(const svBitVecVal* i) { return ~((long long)(i[1]) << 32ULL | i[0]); } + +int dpii_f_int(int i) { return ~i; } +char dpii_f_byte(char i) { return ~i; } +short int dpii_f_shortint(short int i) { return ~i; } +long long dpii_f_longint(long long i) { return ~i; } +void* dpii_f_chandle(void* i) { return i; } +const char* dpii_f_string(const char* i) { return i; } +const char* dpii_f_null() { return nullptr; } +double dpii_f_real(double i) { return i + 1.5; } +float dpii_f_shortreal(float i) { return i + 1.5f; } + +void dpii_v_bit(unsigned char i, unsigned char* o) { *o = 1 & ~i; } +void dpii_v_int(int i, int* o) { *o = ~i; } +void dpii_v_uint(unsigned int i, unsigned int* o) { *o = ~i; } +void dpii_v_byte(char i, char* o) { *o = ~i; } +void dpii_v_shortint(short int i, short int* o) { *o = ~i; } +void dpii_v_ushort(unsigned short i, unsigned short* o) { *o = ~i; } +void dpii_v_longint(long long i, long long* o) { *o = ~i; } +void dpii_v_ulong(unsigned long long i, unsigned long long* o) { *o = ~i; } +void dpii_v_chandle(void* i, void** o) { *o = i; } +void dpii_v_string(const char* i, const char** o) { *o = i; } +void dpii_v_real(double i, double* o) { *o = i + 1.5; } +void dpii_v_shortreal(float i, float* o) { *o = i + 1.5f; } + +void dpii_v_reg(unsigned char i, unsigned char* o) { *o = (~i) & 1; } +void dpii_v_reg15(const svLogicVecVal* i, svLogicVecVal* o) { + o[0].aval = (~i[0].aval) & 0x7fffUL; + o[0].bval = 0; +} +void dpii_v_reg95(const svLogicVecVal* i, svLogicVecVal* o) { + o[0].aval = (~i[0].aval); + o[1].aval = (~i[1].aval); + o[2].aval = (~i[2].aval) & 0x7fffffffUL; + o[0].bval = 0; + o[1].bval = 0; + o[2].bval = 0; +} +void dpii_v_integer(const svLogicVecVal* i, svLogicVecVal* o) { + o[0].aval = (~i[0].aval); + o[0].bval = 0; +} +void dpii_v_time(const svLogicVecVal* i, svLogicVecVal* o) { + o[0].aval = (~i[0].aval); + o[1].aval = (~i[1].aval); + o[0].bval = 0; + o[1].bval = 0; +} + +void dpii_v_struct(const svBitVecVal* i, svBitVecVal* o) { + o[0] = ~i[0]; + o[1] = ~i[1]; + o[2] = ~i[2]; +} +void dpii_v_substruct(const svBitVecVal* i, int* o) { + // To be most like other tools, this should automagically take the substruct_t + // as an argument, and not require this cast... + substruct_t* issp = (substruct_t*)i; + o[0] = issp->b - issp->a; +} +void dpii_v_bit64(const svBitVecVal* i, svBitVecVal* o) { + o[0] = ~i[0]; + o[1] = ~i[1]; +} +void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o) { + o[0] = (~i[0]); + o[1] = (~i[1]); + o[2] = (~i[2]) & 0x7fffffffUL; +} +void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) { + o[0] = ~i[0]; + o[1] = ~i[1]; + o[2] = ~i[2]; +} + +int dpii_f_strlen(const char* i) { return strlen(i); } + +int dpii__under___score(int i) { return i + 1; } + +//====================================================================== + +void dpii_f_void() {} + +#ifdef VCS +void dpii_t_void() {} +void dpii_t_void_context() {} +void dpii_t_int(int i, int* o) { *o = i; } +#else +int dpii_t_void() { return svIsDisabledState(); } +int dpii_t_void_context() { return svIsDisabledState(); } +int dpii_t_int(int i, int* o) { + *o = i; + bool disabled = svIsDisabledState(); // Tasks generally need this + svAckDisabledState(); + return disabled; +} +#endif + +int dpii_fa_bit(int i) { return ~i; } diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_sys.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_sys.v new file mode 100644 index 0000000000000000000000000000000000000000..13673964ea8f8d388feca99b706c4111b500a9af --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_sys.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// Global is the most likely usage scenario +import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); +import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); + +module t (); + +`ifndef verilator + `error "Only Verilator supports PLI-ish DPI calls." +`endif + + initial begin + $dpii_sys(1); + if ($dpii_func(2) != 3) $stop; + $dpii_sys(10); + if ($dpii_func(2) != 12) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_sys_c.cpp b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_sys_c.cpp new file mode 100644 index 0000000000000000000000000000000000000000..d1e6baf8f988b0a8d69d848eb0b11c9bb50056be --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_dpi_sys_c.cpp @@ -0,0 +1,43 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2009-2009 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "svdpi.h" + +#include + +//====================================================================== + +// clang-format off +#if defined(VERILATOR) +# include "Vt_dpi_sys__Dpi.h" +#elif defined(VCS) +# include "../vc_hdrs.h" +#elif defined(CADENCE) +# define NEED_EXTERNS +#else +# error "Unknown simulator for DPI test" +#endif +// clang-format on + +#ifdef NEED_EXTERNS +extern "C" { + +extern void dpii_sys_task(int i); +extern int dpii_sys_func(int i); +} +#endif + +//====================================================================== + +static int hidden = 0; + +void dpii_sys_task(int i) { hidden = i; } +int dpii_sys_func(int i) { return i + hidden; } diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_bad_dup.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_bad_dup.out new file mode 100644 index 0000000000000000000000000000000000000000..34dd352ea1c878f2f39cda67ef03cc153c7e030f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_bad_dup.out @@ -0,0 +1,8 @@ +%Error: t/t_enum_bad_dup.v:10:19: Duplicate declaration of enum value: DUP_VALUE + 10 | DUP_VALUE = 3 + | ^~~~~~~~~ + t/t_enum_bad_dup.v:9:19: ... Location of original declaration + 9 | typedef enum { DUP_VALUE = 2, + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_huge_methods_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_huge_methods_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..e33e10acf0c3c1dbef8c3ad635bdd025fceaed2e --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_huge_methods_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_x_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_x_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..6e2d59774efb601c9b89d0ef4b10438526597ac5 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_enum_x_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + enum bit [1:0] { BADX = 2'b1x } BAD1; + + enum logic [3:0] { e0 = 4'b1xx1, + e1 + } BAD2; + + initial begin + $stop; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_event_control_star.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_event_control_star.v new file mode 100644 index 0000000000000000000000000000000000000000..7df4ae1d0600942fac343788e3de2f51cfa9b494 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_event_control_star.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Based on ivtest's nested_impl_event1.v by Martin Whitaker. + +module t(); + + reg a; + reg b; + reg c; + + always @* begin // @(b or c) + a = b; + $display("[%0t] Triggered 1 @(b or c)", $time); + + @* a = c; // @(c) + $display("[%0t] Triggered 2 @(c)", $time); + end + + initial begin + #10; + b = 0; + #10; + b = 1; + #10; + c = 0; + #10; + c = 1; + #10; + c = 0; + #10; + $write("*-* All Finished *-*\n"); + $finish(0); + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_export_packed_struct2.cpp b/snapshots/verilator_verilator_pr6833/test_regress/t/t_export_packed_struct2.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c97e3939260aa06a1119ba132eb324dbeae91cd1 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_export_packed_struct2.cpp @@ -0,0 +1,122 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2024 by Kefa Chen. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +//************************************************************************* + +#include + +#include +#include + +#include VM_PREFIX_INCLUDE +#include VM_PREFIX_ROOT_INCLUDE + +#include "TestCheck.h" +#include "Vt_export_packed_struct2___024unit__03a__03acls_in__Vclpkg.h" + +/* +// Packed struct in package +package TEST_TYPES; + typedef union packed { + logic [64:0] a; + logic [2:0] b; + } sub_t; + typedef struct packed { + struct packed { // Anonymous packed struct + logic a; + } anon; + TEST_TYPES::sub_t [2:0][2:0][2:0] b; + } in_t; + typedef struct packed { + TEST_TYPES::sub_t [2:0][2:0][2:0] b; + struct packed {logic a;} anon; + } out_t; +endpackage + +// Packed struct in class +class cls_in; + typedef struct packed { + logic a; + TEST_TYPES::sub_t [2:0][2:0][2:0] b; + } in_t; + in_t in; +endclass //cls +*/ + +#define CONCAT_IMPL(a, b) a##b +#define CONCAT(a, b) CONCAT_IMPL(a, b) +#define CONCAT5(a, b, c, d, e) CONCAT(CONCAT(CONCAT(CONCAT(a, b), c), d), e) +#define EXPORTED_STRUCT_NAME(STRUCT_NAME, NUMBER) \ + CONCAT5(VM_PREFIX, _, STRUCT_NAME, __struct__, NUMBER) +#define EXPORTED_UNION_NAME(UNION_NAME, NUMBER) \ + CONCAT5(VM_PREFIX, _, UNION_NAME, __union__, NUMBER) +#define SUB_T EXPORTED_UNION_NAME(sub_t, 0) +#define IN_T EXPORTED_STRUCT_NAME(in_t, 0) +#define IN2_T EXPORTED_STRUCT_NAME(in_t, 1) +#define OUT_T EXPORTED_STRUCT_NAME(out_t, 0) + +int errors = 0; + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + contextp->debug(0); + contextp->randReset(2); + contextp->commandArgs(argc, argv); + + const std::unique_ptr adder{new VM_PREFIX{contextp.get()}}; + + { + IN_T in; + IN2_T tmp; + OUT_T out; + for (int i = 0; i < 3; ++i) { + for (int j = 0; j < 3; ++j) { + for (int k = 0; k < 3; ++k) { + VL_SET_WQ(in.b[i][j][k].a, 0x1234123412341234UL); + // Set last bit zero and upper bits one + in.b[i][j][k].a[2] = 0xfe; + } + } + } + in.anon.a = 0x1; + + adder->op1 = in.get(); + adder->eval(); + out.set(adder->out); + + std::memset(reinterpret_cast(&tmp), 0xff, sizeof(tmp)); + // `set` function should clear upper bits of `tmp.a` + tmp.set(adder->rootp->add__DOT__op2); + + for (int i = 0; i < 3; ++i) { + for (int j = 0; j < 3; ++j) { + for (int k = 0; k < 3; ++k) { + TEST_CHECK_EQ(tmp.b[i][j][k].a[0], 0x12341234); + TEST_CHECK_EQ(tmp.b[i][j][k].a[1], 0x12341234); + TEST_CHECK_EQ(tmp.b[i][j][k].a[2], 0); + } + } + } + TEST_CHECK_EQ(tmp.a, 0x1); + + for (int i = 0; i < 3; ++i) { + for (int j = 0; j < 3; ++j) { + for (int k = 0; k < 3; ++k) { + TEST_CHECK_EQ(out.b[i][j][k].a[0], 0x24682468); + TEST_CHECK_EQ(out.b[i][j][k].a[1], 0x24682468); + TEST_CHECK_EQ(out.b[i][j][k].a[2], 0x0); + } + } + } + TEST_CHECK_EQ(out.anon.a, 0x0); + } + + printf("*-* All Finished *-*\n"); + return errors; +} diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_invalid_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_invalid_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..139abb1ab277df1b61866d8bb3a7a84e7b841628 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_invalid_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, verilator_flags2=['--invalid-dash'], expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_main_sc_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_main_sc_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..6912ff255c9ccc61fc83166b19ae87713198d8b1 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_main_sc_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(verilator_flags2=['--exe --build --main --sc'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_make_cmake.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_make_cmake.v new file mode 100644 index 0000000000000000000000000000000000000000..2478ff8194365dcdb056b96859bb989b9b878a3a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_make_cmake.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_output_groups_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_output_groups_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..830b04e8031790214e05661bcb6783e901e5c600 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_output_groups_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(verilator_flags2=['--output-groups -2'], + fails=True, + expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_values_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_values_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..ff3be40f50b8fbb711535d069023287214e28991 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_values_bad.out @@ -0,0 +1,6 @@ +%Error: --output-split-cfuncs must be >= 0: -1 + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: --output-split-ctrace must be >= 0: -1 +%Error: --preproc-token-limit must be > 0: 0 +%Error: --reloop-limit must be >= 2: -1 +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_werror_bad1.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_werror_bad1.py new file mode 100644 index 0000000000000000000000000000000000000000..61de16fab212caea79956bb5a05a92b7e75773c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_flag_werror_bad1.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_flag_werror.v" + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_for_disable_dot.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_for_disable_dot.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_for_disable_dot.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_forceable_net_cmt_trace.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_forceable_net_cmt_trace.py new file mode 100644 index 0000000000000000000000000000000000000000..50e9098404ea1a5e0e2727f965f12603cf9d7319 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_forceable_net_cmt_trace.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.pli_filename = "t/t_forceable_net.cpp" +test.top_filename = "t/t_forceable_net.v" +test.golden_filename = "t/t_forceable_net_trace.vcd.out" + +test.compile(make_top_shell=False, + make_main=False, + verilator_flags2=['-DCMT=1', '--exe', '--trace-vcd', test.pli_filename]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_foreach_noivar_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_foreach_noivar_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..2101e39020405b66a327c1ea96ad4f46ff5bf383 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_foreach_noivar_bad.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = 't/t_foreach_noivar.v' + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_fork_delay_finish.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_fork_delay_finish.py new file mode 100644 index 0000000000000000000000000000000000000000..1c061c8c99f4ca0d375dc3be1bc726b5e4f5eeee --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_fork_delay_finish.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_fork_join_none_class_cap.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_fork_join_none_class_cap.py new file mode 100644 index 0000000000000000000000000000000000000000..c53b5526261f426ecf0e1d0b31f3499571ddba1c --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_fork_join_none_class_cap.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_io_order.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_io_order.v new file mode 100644 index 0000000000000000000000000000000000000000..c7b90d5c57779080cb267e47522d99e51f6ea837 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_io_order.v @@ -0,0 +1,75 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire ain = crc[0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic bout; // From test of Test.v + // End of automatics + + Test test(/*AUTOINST*/ + // Outputs + .bout (bout), + // Inputs + .ain (ain)); + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc < 10) begin + if (bout != ~ain) $stop; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + bout, + // Inputs + ain + ); + + input logic ain; + output logic bout; + + function automatic void inv + (input logic w_in, + output logic w_out); + w_out = ~w_in; + endfunction + + always_comb + inv(.w_out(bout), + .w_in(ain)); + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_lib_sub_timing.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_lib_sub_timing.py new file mode 100644 index 0000000000000000000000000000000000000000..7c9bdb51b5223ae00ac51a5428d7bbd9747a41f9 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_lib_sub_timing.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') # UNOPTTHREADS in vltmt +test.top_filename = "t/t_func_lib_sub.v" + +test.compile(verilator_flags2=["--binary"]) + +#test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_nansi_dup_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_nansi_dup_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..06efe7e21357a69d3b59bfd9f8db9cdef5e7b651 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_nansi_dup_bad.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +typedef int T; + +module test; + + task t4; + input [7:0] bad4; + reg bad4; + reg bad4; // <--- Error (duplicate) + endtask + + task t5; + input [7:0] bad5; + input [7:0] bad5; // <--- Error (duplicate) + reg bad5; + endtask + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_nansi_mism_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_nansi_mism_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..b5d0038a3d3c8fba8cb1e76f70b72c8e63e545b1 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_nansi_mism_bad.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +typedef int T; + +module test; + + task t1; + input [15:0] bad1; + shortint bad1; // <--- Error (type doesn't match above) + endtask + + task t2; + input [31:0] bad2; + T bad2; // <--- Error (type doesn't match above) + endtask + + task t3; + input [7:0] bad3; + reg [3:0] bad3; // <--- Error (type doesn't match above) + endtask + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_real_param.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_real_param.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_func_real_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_gen_cond_const.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_gen_cond_const.py new file mode 100644 index 0000000000000000000000000000000000000000..4aa451103a382a5e9ce42d7b7a6f481aa0477ecb --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_gen_cond_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--language 1364-2001"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_gen_defparam_nfound_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_gen_defparam_nfound_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..e33e10acf0c3c1dbef8c3ad635bdd025fceaed2e --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_gen_defparam_nfound_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_hier_block.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_hier_block.py new file mode 100644 index 0000000000000000000000000000000000000000..ff13a4925293edd2ca2902dde0ffbb264013f2a8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_hier_block.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.priority(30) +test.scenarios('vlt_all') + +# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist. +test.clean_objs() + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--stats', + '--hierarchical', + '--Wno-TIMESCALEMOD', # + '-GPARAM_A=100', + '-pvalue+PARAM_B=200', + '-DPARAM_OVERRIDE', # + '--CFLAGS', + '"-pipe -DCPP_MACRO=cplusplus"' + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1) +test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0") +test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1") +test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2") +test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14) +test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus") + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_hier_block_trace_vcd.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_hier_block_trace_vcd.py new file mode 100644 index 0000000000000000000000000000000000000000..6e06e809d65504b587be90b03a0a3a135361ec62 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_hier_block_trace_vcd.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.priority(30) +test.scenarios('vlt_all') +test.top_filename = "t/t_hier_block.v" + +# CI environment offers 2 VCPUs, 2 thread setting causes the following warning. +# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. +# So use 6 threads here though it's not optimal in performance, but ok. + +test.compile( + v_flags2=['t/t_hier_block.cpp'], + verilator_flags2=[ + '--hierarchical', + '--Wno-TIMESCALEMOD', + '--trace-vcd', + '--no-trace-underscore', # To avoid handle mismatches + ], + threads=(6 if test.vltmt else 1)) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_incr_void.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_incr_void.v new file mode 100644 index 0000000000000000000000000000000000000000..75284fcd7c712c1adfbc674dd604a744d5c038bf --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_incr_void.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Drew Ranck. +// SPDX-License-Identifier: CC0-1.0 + +module t + (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc = 0; + + always @ (posedge clk) begin : main + cyc <= cyc + 1; + + if (cyc > 100) begin + $write("*-* All Finished *-*\n"); + $finish(); + end + end + + + + logic [3:0] count_d; + logic [3:0] count_q = '0; + + logic [3:0] want_count_d; + logic [3:0] want_count_q = '0; + + always_ff @(posedge clk) begin : flops + count_q <= count_d; + want_count_q <= want_count_d; + end + + always @(posedge clk) begin : simple_check + if (cyc > 0) begin + if (count_q !== want_count_q) begin + $error("%m: cyc=%0d, count_q (%0d) !== want_count_q (%0d)", + cyc, count_q, want_count_q); + $stop; // don't finish to fail the test. + end + end + end + + always_comb begin : update_golden_counts + want_count_d = want_count_q; + want_count_d += 1'b1; + end + + // make sure an implicit void cast on n++ works as expected. + always_comb begin : update_counts + count_d = count_q; + count_d++; + end + + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_initial_dlyass.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_initial_dlyass.v new file mode 100644 index 0000000000000000000000000000000000000000..5e86b628caab1fc562eca8eeff2e74fa80efb565 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_initial_dlyass.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc; initial cyc = 0; + integer a; + integer b; + + initial begin + a <= 22; + b <= 33; + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==99) begin + if (a != 22) $stop; + if (b != 33) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_inside_tolerance_unsup.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_inside_tolerance_unsup.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_inside_tolerance_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface1_modport_noinl.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface1_modport_noinl.py new file mode 100644 index 0000000000000000000000000000000000000000..39ec887e7794904a0038817cc75886e88a358a76 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface1_modport_noinl.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_interface1_modport.v" + +test.compile(v_flags2=["-fno-inline"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_array4.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_array4.v new file mode 100644 index 0000000000000000000000000000000000000000..f3042fa2dd28a0e41dcba831c496594167018176 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_array4.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +interface Ifc; + logic req, grant; + logic [7:0] addr, data; +endinterface + +class Cls; + virtual Ifc bus; + int m_i; + function new(virtual Ifc s, int i); + bus = s; + m_i = i; + endfunction + task request(); + bus.req <= 1'b1; + endtask + task wait_for_bus(); + @(posedge bus.grant); + endtask +endclass + +module devA (Ifc s); +endmodule +module devB (Ifc s); +endmodule + +module t; + Ifc s14[1:4] (); + devA a1 (s14[1]); + devB b1 (s14[2]); + devA a2 (s14[3]); + devB b2 (s14[4]); + + Ifc s65[6:5] (); + devA a3 (s65[5]); + devB b3 (s65[6]); + + initial begin + Cls t14[1:4]; + Cls t65[6:5]; + t14[1] = new(s14[1], 1); + t14[2] = new(s14[2], 2); + t14[3] = new(s14[3], 3); + t14[4] = new(s14[4], 4); + t65[5] = new(s65[5], 5); + t65[6] = new(s65[6], 6); + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_array_parameter_access.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_array_parameter_access.py new file mode 100644 index 0000000000000000000000000000000000000000..dbdaf45516d2d2b77ef132ea373121e692d3c3c5 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_array_parameter_access.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_derived_type.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_derived_type.v new file mode 100644 index 0000000000000000000000000000000000000000..cee8559bc769669010eb2a9c9b90db4f79c43545 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_derived_type.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: SystemVerilog interface test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +interface intf #( + parameter type data_t = bit, + parameter int arr[2][4] +) (); + data_t data; + // TODO -- some kind of issue with multi-dimensional array constness: + // %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr' + // : ... note: In instance 't.sub16' + // 19 | logic [arr[0][0]-1:0] other_data; + // | ^~~ + // `define SHOW_2D_BUG + `ifdef SHOW_2D_BUG + logic [arr[0][0]-1:0] other_data; + `else + logic [$bits(data)-1:0] other_data; + `endif +endinterface + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // finish report + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + +endmodule + +module sub #( + parameter int width, + parameter int arr[2][4] +) (); + typedef struct packed { + logic [3:3] [0:0] [width-1:0] field; + } user_type_t; + + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); + + logic [width-1:0] signal; + + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_dups.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_dups.v new file mode 100644 index 0000000000000000000000000000000000000000..6a6925b7c93c5f5958205bd1507a605ca78bf9a0 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_dups.v @@ -0,0 +1,168 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [4:0] din_data = crc[4:0]; + wire [0:0] din_valid = crc[6]; + wire [0:0] dout0_ready = crc[16]; + wire [0:0] dout1_ready = crc[17]; + wire [0:0] dout2_ready = crc[18]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic din_ready; // From test of Test.v + logic [0:0] dout0_data; // From test of Test.v + logic dout0_valid; // From test of Test.v + logic [1:0] dout1_data; // From test of Test.v + logic dout1_valid; // From test of Test.v + logic [2:0] dout2_data; // From test of Test.v + logic dout2_valid; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .din_ready (din_ready), + .dout0_valid (dout0_valid), + .dout0_data (dout0_data[0:0]), + .dout1_valid (dout1_valid), + .dout1_data (dout1_data[1:0]), + .dout2_valid (dout2_valid), + .dout2_data (dout2_data[2:0]), + // Inputs + .din_valid (din_valid), + .din_data (din_data[4:0]), + .dout0_ready (dout0_ready), + .dout1_ready (dout1_ready), + .dout2_ready (dout2_ready)); + + // Aggregate outputs into a single result vector + wire [63:0] result = {48'h0, din_ready, + 2'd0, dout2_valid, dout2_data, + 2'd0, dout1_valid, dout1_data, + 2'd0, dout0_valid, dout0_data}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h6fd1bead9df31b07 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +interface dti + #(W_DATA = 64 + )(); + + logic [W_DATA-1:0] data; + logic valid; + logic ready; + + modport producer (output data, + output valid, + input ready); + modport consumer (input data, + input valid, + output ready); +endinterface : dti + +module Test + ( + output logic din_ready, + input logic din_valid, + input logic [4:0] din_data, + input logic dout0_ready, + output logic dout0_valid, + output logic [0:0] dout0_data, + input logic dout1_ready, + output logic dout1_valid, + output logic [1:0] dout1_data, + input logic dout2_ready, + output logic dout2_valid, + output logic [2:0] dout2_data + ); + + // Interface declarations + dti #(.W_DATA(5)) din(); + dti #(.W_DATA(1)) dout0(); + dti #(.W_DATA(2)) dout1(); + dti #(.W_DATA(3)) dout2(); + + // Interface wiring to top level ports + assign din.valid = din_valid; + assign din.data = din_data; + assign din_ready = din.ready; + + assign dout0_valid = dout0.valid; + assign dout0_data = dout0.data; + assign dout0.ready = dout0_ready; + + assign dout1_valid = dout1.valid; + assign dout1_data = dout1.data; + assign dout1.ready = dout1_ready; + + assign dout2_valid = dout2.valid; + assign dout2_data = dout2.data; + assign dout2.ready = dout2_ready; + + assign din.ready = 0; + assign dout0.data = 0; + assign dout1.data = 0; + assign dout2.data = 0; + + typedef struct packed { + logic [1:0] ctrl; + logic [2:0] data; + } din_t; + + din_t din_s; + assign din_s = din.data; + + always_comb begin + dout0.valid = 0; + dout1.valid = 0; + dout2.valid = 0; + + case (din_s.ctrl) + 0 : dout0.valid = din.valid; + 1 : dout1.valid = din.valid; + 2 : dout2.valid = din.valid; + default: ; + endcase + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_gen11.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_gen11.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_gen11.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_gen7.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_gen7.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_gen7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_generic_array.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_generic_array.v new file mode 100644 index 0000000000000000000000000000000000000000..cce0e00fd96c0d67640029a8840f83236d541d00 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_generic_array.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +interface inf; + int v; +endinterface + +module GenericModule (interface a); + initial begin + #1; + if (a.v != 7) $stop; + end +endmodule + +module t; + inf inf_inst[3](); + GenericModule genericModule (inf_inst[2]); + initial begin + inf_inst[2].v = 7; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_generic_iface_param.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_generic_iface_param.py new file mode 100644 index 0000000000000000000000000000000000000000..5b1a2f8cc6bd935c4110e55b7e2b51f3e1d42dc9 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_generic_iface_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--timing']) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_parameter_access.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_parameter_access.py new file mode 100644 index 0000000000000000000000000000000000000000..dbdaf45516d2d2b77ef132ea373121e692d3c3c5 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_interface_parameter_access.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_json_only_begin_hier.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_json_only_begin_hier.out new file mode 100644 index 0000000000000000000000000000000000000000..771c33e1cb97fa919089c806b16384178a17b273 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_json_only_begin_hier.out @@ -0,0 +1,54 @@ +{"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", + "modulesp": [ + {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"test","level":1,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + "stmtsp": [ + {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"GENBLOCK","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","implied":true,"unnamed":false,"genforp": [],"itemsp": []}, + {"type":"GENBLOCK","name":"FOR_GENERATE[0]","addr":"(I)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], + "itemsp": [ + {"type":"CELL","name":"submod_for","addr":"(J)","loc":"d,27:21,27:31","origName":"submod_for","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"GENBLOCK","name":"genblk1","addr":"(L)","loc":"d,28:19,28:24","implied":false,"unnamed":true,"genforp": [], + "itemsp": [ + {"type":"CELL","name":"submod_2","addr":"(M)","loc":"d,29:25,29:33","origName":"submod_2","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]}, + {"type":"CELL","name":"submod_3","addr":"(N)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]}, + {"type":"GENBLOCK","name":"FOR_GENERATE[1]","addr":"(O)","loc":"d,27:21,27:31","implied":false,"unnamed":false,"genforp": [], + "itemsp": [ + {"type":"CELL","name":"submod_for","addr":"(P)","loc":"d,27:21,27:31","origName":"submod_for","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []}, + {"type":"GENBLOCK","name":"genblk1","addr":"(Q)","loc":"d,28:19,28:24","implied":false,"unnamed":true,"genforp": [], + "itemsp": [ + {"type":"CELL","name":"submod_2","addr":"(R)","loc":"d,29:25,29:33","origName":"submod_2","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]}, + {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]} + ]}, + {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + "stmtsp": [ + {"type":"GENBLOCK","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","implied":false,"unnamed":false,"genforp": [], + "itemsp": [ + {"type":"VAR","name":"l1_sig","addr":"(U)","loc":"d,13:14,13:20","dtypep":"(V)","origName":"l1_sig","isSc":false,"isPrimaryIO":false,"isPrimaryClock":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"isStdRandomizeArg":false,"lifetime":"VSTATICI","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"GENBLOCK","name":"nested_gen","addr":"(W)","loc":"d,14:23,14:33","implied":false,"unnamed":false,"genforp": [], + "itemsp": [ + {"type":"CELL","name":"submod_nested","addr":"(X)","loc":"d,15:21,15:34","origName":"submod_nested","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]}, + {"type":"CELL","name":"submod_l1","addr":"(Z)","loc":"d,17:17,17:26","origName":"submod_l1","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]}, + {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} + ]}, + {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"submod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": []} +],"filesp": [], + "miscsp": [ + {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", + "typesp": [ + {"type":"BASICDTYPE","name":"integer","addr":"(G)","loc":"d,24:12,24:13","dtypep":"(G)","keyword":"integer","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(V)","loc":"d,13:14,13:20","dtypep":"(V)","keyword":"logic","generic":true,"rangep": []} + ]}, + {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", + "modulep": [ + {"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"hasGenericIface":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + "stmtsp": [ + {"type":"SCOPE","name":"@CONST-POOL@","addr":"(CB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BB)","varsp": [],"blocksp": [],"inlinesp": []} + ]} + ]} +]} diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_json_only_flat_vlvbound.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_json_only_flat_vlvbound.py new file mode 100644 index 0000000000000000000000000000000000000000..9903be78042c750f4ff1e0af89f7b4276c241acf --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_json_only_flat_vlvbound.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".tree.json" + +test.compile(verilator_flags2=['--no-std', '--json-only', '--no-json-edit-nums', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_let_arg_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_let_arg_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..5a21b803a737f39eb0385d554f7851480aabe43e --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_let_arg_bad.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + let NO_ARG = 10; + let ONE_ARG(a) = 10; + + initial begin + if (NO_ARG(10) != 10) $stop; // BAD extra arg + if (ONE_ARG != 10) $stop; // BAD need arg + if (ONE_ARG() != 10) $stop; // BAD need arg + if (ONE_ARG(10, 20) != 10) $stop; // BAD extra arg + if (ONE_ARG(.b(1)) != 10) $stop; // BAD wrong arg name + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_didnotconverge_nodbg_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_didnotconverge_nodbg_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..abd364a1445ded23914065c11328c0ab185cfb6e --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_didnotconverge_nodbg_bad.py @@ -0,0 +1,26 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_lint_didnotconverge_bad.v" + +if not os.path.exists(test.root + "/.git"): + test.skip("Not in a git repository") + +test.compile(make_flags=['CPPFLAGS_ADD=-UVL_DEBUG']) + +test.execute(fails=True, expect_filename=test.golden_filename) + +test.extract(in_filename=test.golden_filename, + out_filename=test.root + "/docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst", + lines="1") + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_dtype_compare_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_dtype_compare_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..55203b6c971211d774012ddd520e6db1bba72dfe --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_dtype_compare_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_latch_4.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_latch_4.py new file mode 100644 index 0000000000000000000000000000000000000000..f81c3d68de12a629f04772923ab46a801909a3e2 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_latch_4.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_syncasyncnet_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_syncasyncnet_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..d675d43ad21c20a1df8abeff09135f7a69d90caf --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_syncasyncnet_bad.out @@ -0,0 +1,10 @@ +%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:14:10: Signal flopped as both synchronous and async: 'rst_both_l' + t/t_lint_syncasyncnet_bad.v:52:15: ... Location of async usage + 52 | q4 <= (~rst_both_l) ? 1'b0 : d; + | ^~~~~~~~~~ + t/t_lint_syncasyncnet_bad.v:34:14: ... Location of sync usage + 34 | q2 <= (rst_both_l) ? d : 1'b0; + | ^~~~~~~~~~ + ... For warning description see https://verilator.org/warn/SYNCASYNCNET?v=latest + ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_warn_line_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_warn_line_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..0c219e8a75fc82224b2ce146a2dfcd2db9f643e4 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_warn_line_bad.v @@ -0,0 +1,14 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Check that `line `__LINE__ still shows proper warning context + +`line `__LINE__ "the_line_file" 1 +`line `__LINE__ "the_line_file" 2 + +module t; + int warn_t = 64'h1; // Not suppressed - should warn +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_width_arraydecl.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_width_arraydecl.v new file mode 100644 index 0000000000000000000000000000000000000000..7a6438621eff4c960951cf268e862e9377b0ce89 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_width_arraydecl.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +localparam UADDR_WIDTH = 4'd10; +localparam UROM_WIDTH = 5'd17; +localparam UROM_DEPTH = 11'd1024; + + +module t( + input clk, + input [UADDR_WIDTH-1:0] mAddr, + output logic [UROM_WIDTH-1:0] mOutput); + + // Issue #3959 + reg [UROM_WIDTH-1:0] uRam[UROM_DEPTH]; + + always @(posedge clk) mOutput <= uRam[mAddr]; + + // Issue #6045 + typedef enum logic [1:0] { e_0, e_1, e_2, e_3 } enum_e; + + typedef struct packed { + integer unsigned x; + integer unsigned y; + } foo_s; + + typedef struct packed { + integer unsigned y; + } bar_s; + + // Warning due to concatenation, but this is actually a member assignment + localparam foo_s FOO = '{ + y: (1 << e_0) | (1 << e_3) + , default: '0 + }; + + // No warning + localparam bar_s BAR = '{ + y: (1 << e_0) | (1 << e_3) + }; + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_width_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_width_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..4e6affbc7c63052668d849e487106d71c25f67d3 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_lint_width_bad.v @@ -0,0 +1,48 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (); + + // See also t_math_width + + // This shows the uglyness in width warnings across param modules + // TODO: Would be nice to also show relevant parameter settings + p #(.WIDTH(4)) p4 (.in(4'd0)); + p #(.WIDTH(5)) p5 (.in(5'd0)); + + //==== + localparam [3:0] XS = 'hx; // User presumably intended to use 'x + + //==== + wire [4:0] c = 1'b1 << 2; // No width warning, as is common syntax + wire [4:0] d = (1'b1 << 2) + 5'b1; // Has warning as not obvious what expression width is + + //==== + localparam WIDTH = 6; + wire one_bit; + wire [2:0] shifter = 1; + wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); + + //==== + // We presently warn here, in theory we could detect if the number of one bit additions could overflow the LHS + wire one = 1; + wire [2:0] cnt = (one + one + one + one); + + // Not harmless > or >= compared with something wider (as different results if "a" wider) + localparam [40:0] THREE = 3; + int a; + initial for (a = 0; a > THREE; ++a) $display(a); + initial for (a = 0; a >= THREE; ++a) $display(a); + + initial if (THREE) $stop; + +endmodule + +module p + #(parameter WIDTH=64) + (input [WIDTH-1:0] in); + wire [4:0] out = in; +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_pow3.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_pow3.v new file mode 100644 index 0000000000000000000000000000000000000000..aeaba1b0d4d11c8931ec6ac89e053241f8cfa33a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_pow3.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) + +module t; + + bit fail; + + // IEEE says for ** the size is L(i). Thus Icarus Verilog is wrong in sizing some of the below. + + initial begin + // NC=67b6cfc1b29a21 VCS=c1b29a20(wrong) IV=67b6cfc1b29a21 Verilator=67b6cfc1b29a21 + $display("15 ** 14 = %0x expect 67b6cfc1b29a21", 64'b1111 ** 64'b1110); + // NC=1 VCS=0 IV=0 Verilator=1 (wrong,fixed) + $display("15 **-4'sd2 = %0x expect 0 (per IEEE negative power)", ((-4'd1 ** -4'sd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((-4'd1 ** -4'd2))); + // NC=1 VCS=0 IV=67b6cfc1b29a21(wrong) Verilator=1 + $display("15 ** 14 = %0x expect 1 (LSB 4-bits of 67b6cfc1b29a21)", ((4'd15 ** 4'd14))); + // NC=8765432187654321 VCS=8765432187654000(wrong) IV=8765432187654321 Verilator=8765432187654321 + $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); + $display("\n"); + + `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); + `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 + `checkh( (-4'd1 ** -4'd2), 4'h1); + `checkh( (4'd15 ** 4'd14), 4'h1); + `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); + + `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) + `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) + + `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b + `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 + `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 + `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) + `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) + `checkh(( 8'sh6 ** 8'sh3), 8'hd8 ); // a**b (216) + + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + + `checkh((-8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh((-8'sh1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h0 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h1 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'h3 ** -8'sh0), 8'h1 ); // a**0 always 1 + `checkh(( 8'sh3 ** -8'sh0), 8'h1 ); // a**0 always 1 + + `checkh((-8'sh3 ** -8'sh3), 8'h0 ); // 0 (a<-1) // NCVERILOG bug + `checkh((-8'sh1 ** -8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** -8'sh3), 8'hff); // -1^odd=-1, -1^even=1 +// `checkh(( 8'h0 ** -8'sh3), 8'hx ); // x // NCVERILOG bug + `checkh(( 8'h1 ** -8'sh3), 8'h1 ); // 1**b always 1 + `checkh(( 8'h3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + `checkh(( 8'sh3 ** -8'sh3), 8'h0 ); // 0 // NCVERILOG bug + + + if (fail) $stop; + else $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_repl2_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_repl2_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..9f5fecdc7efb0020df9e9c8d87a19dd1f482ff1a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_repl2_bad.out @@ -0,0 +1,12 @@ +%Error: t/t_math_repl2_bad.v:28:30: Replication value of < 0 or X/Z not legal (IEEE 1800-2023 11.4.12.1): '32'hfffffffb' + : ... note: In instance 't' + 28 | out <= {{(P24 - P29){1'b0}}, in}; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Warning-WIDTHTRUNC: t/t_math_repl2_bad.v:28:14: Operator ASSIGNDLY expects 24 bits on the Assign RHS, but Assign RHS's REPLICATE generates 30 bits. + : ... note: In instance 't' + 28 | out <= {{(P24 - P29){1'b0}}, in}; + | ^~ + ... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest + ... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_repl_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_repl_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_repl_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_wide_inc.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_wide_inc.v new file mode 100644 index 0000000000000000000000000000000000000000..1d62ca03f12d3d12ee906f55b7465bbd332b46ed --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_math_wide_inc.v @@ -0,0 +1,89 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2023 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer i; + reg [6:0] w7; + reg [14:0] w15; + reg [30:0] w31; + reg [62:0] w63; + reg [94:0] w95; + + integer cyc = 0; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d\n", $time, cyc); +`endif + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + w7 = {7{1'b1}}; + w15 = {15{1'b1}}; + w31 = {31{1'b1}}; + w63 = {63{1'b1}}; + w95 = {95{1'b1}}; + end + else if (cyc == 1) begin + if (w7++ != {7{1'b1}}) $stop; + if (w7 != {7{1'b0}}) $stop; + if (w7-- != {7{1'b0}}) $stop; + if (w7 != {7{1'b1}}) $stop; + if (++w7 != {7{1'b0}}) $stop; + if (w7 != {7{1'b0}}) $stop; + if (--w7 != {7{1'b1}}) $stop; + if (w7 != {7{1'b1}}) $stop; + + if (w15++ != {15{1'b1}}) $stop; + if (w15 != {15{1'b0}}) $stop; + if (w15-- != {15{1'b0}}) $stop; + if (w15 != {15{1'b1}}) $stop; + if (++w15 != {15{1'b0}}) $stop; + if (w15 != {15{1'b0}}) $stop; + if (--w15 != {15{1'b1}}) $stop; + if (w15 != {15{1'b1}}) $stop; + + if (w31++ != {31{1'b1}}) $stop; + if (w31 != {31{1'b0}}) $stop; + if (w31-- != {31{1'b0}}) $stop; + if (w31 != {31{1'b1}}) $stop; + if (++w31 != {31{1'b0}}) $stop; + if (w31 != {31{1'b0}}) $stop; + if (--w31 != {31{1'b1}}) $stop; + if (w31 != {31{1'b1}}) $stop; + + if (w63++ != {63{1'b1}}) $stop; + if (w63 != {63{1'b0}}) $stop; + if (w63-- != {63{1'b0}}) $stop; + if (w63 != {63{1'b1}}) $stop; + if (++w63 != {63{1'b0}}) $stop; + if (w63 != {63{1'b0}}) $stop; + if (--w63 != {63{1'b1}}) $stop; + if (w63 != {63{1'b1}}) $stop; + + if (w95++ != {95{1'b1}}) $stop; + if (w95 != {95{1'b0}}) $stop; + if (w95-- != {95{1'b0}}) $stop; + if (w95 != {95{1'b1}}) $stop; + if (++w95 != {95{1'b0}}) $stop; + if (w95 != {95{1'b0}}) $stop; + if (--w95 != {95{1'b1}}) $stop; + if (w95 != {95{1'b1}}) $stop; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_mod_dot.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_mod_dot.py new file mode 100644 index 0000000000000000000000000000000000000000..c0aa692c8696d3b686953793d6c037d780fd34c9 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_mod_dot.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# This doesn't use the general compile rule as we want to make sure we form +# prefix properly using post-escaped identifiers +test.run(cmd=[ + os.environ["VERILATOR_ROOT"] + "/bin/verilator", + "--binary", + "--Mdir " + test.obj_dir + "/t_mod_dot", + 't/t_mod_dot.v', +], + verilator_run=True) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_no_std_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_no_std_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..9bce31e775c9f41651200f8b61f5980a9c3e4eff --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_no_std_bad.v @@ -0,0 +1,10 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// verilator lint_off DECLFILENAME +module t; + import std::*; +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_balance_cats_sc.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_balance_cats_sc.py new file mode 100644 index 0000000000000000000000000000000000000000..d9b6693a37b1dba2af7b5447b321ecb8b5633d2f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_balance_cats_sc.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_opt_balance_cats.v" + +test.compile(verilator_flags2=[ + "--stats", "--build", "--gate-stmts", "10000", "--expand-limit", "128", "--sc" +]) + +test.file_grep(test.stats, r'Optimizations, FuncOpt concat trees balanced\s+(\d+)', 1) +test.file_grep(test.stats, r'Optimizations, FuncOpt concat splits\s+(\d+)', 0) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_const_no_expand.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_const_no_expand.py new file mode 100644 index 0000000000000000000000000000000000000000..e72a9737fe6713e632db9c767ff84cb30114342e --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_const_no_expand.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = "t/t_opt_const.v" + +test.compile(verilator_flags2=[ + "-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand", "--stats", "t/t_opt_const.cpp" +]) + +test.execute() + +if test.vlt: + test.file_grep(test.stats, r'Optimizations, Const bit op reduction\s+(\d+)', 4) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_table_real_off.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_table_real_off.py new file mode 100644 index 0000000000000000000000000000000000000000..effecdb53c52ce8ff96dd74f2ca6775dd962ee8f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_opt_table_real_off.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator_st') +test.top_filename = 't/t_opt_table_real.v' +test.golden_filename = 't/t_opt_table_real.out' + +test.compile(verilator_flags2=["--stats -fno-table"]) + +if test.vlt_all: + test.file_grep_not(test.stats, r'Optimizations, Tables created\s+(\d+)') + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_order_dpi_export_8.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_order_dpi_export_8.py new file mode 100644 index 0000000000000000000000000000000000000000..38f29b4e608dcf9b5a40570af1fc667ff9788d72 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_order_dpi_export_8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_package.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_package.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_package.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_package_export_bad2.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_package_export_bad2.v new file mode 100644 index 0000000000000000000000000000000000000000..ae1ac13fe97e6e54da199e39928e7075b1d94adc --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_package_export_bad2.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2024 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +package Pkg1; +endpackage + +package Pkg10; + // verilator lint_off PKGNODECL + export Pkg1b::*; // BAD - typo in package name +endpackage + +module t; +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_package_import_param.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_package_import_param.py new file mode 100644 index 0000000000000000000000000000000000000000..cca4c9e73b713e68872237561942cce65ab59ef7 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_package_import_param.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_param_real.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_param_real.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_param_real.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_param_wide_io.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_param_wide_io.v new file mode 100644 index 0000000000000000000000000000000000000000..12fdc58f8eba89c055e144179266a12819c7e4bd --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_param_wide_io.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// See issue #1991 + +module t + #( + parameter[96:0] P = 97'h12344321_12344321_12344327 + ) + ( + input [P&7 - 1:0] in, + output [P&7 - 1:0] out + ); + + assign out = in; + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_process_copy_constr.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_process_copy_constr.py new file mode 100644 index 0000000000000000000000000000000000000000..34b0247e980b63078eafa23f2a094aaee72c1af4 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_process_copy_constr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--timing"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_public_clk.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_public_clk.py new file mode 100644 index 0000000000000000000000000000000000000000..f37ad07c86e33121efc59b5cba92ffa9bd07e2bb --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_public_clk.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_public_unpacked_port.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_public_unpacked_port.py new file mode 100644 index 0000000000000000000000000000000000000000..fc5a55e3fc35ed4797c76a246e6344b928854246 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_public_unpacked_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_rand_member_mode_deriv.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_rand_member_mode_deriv.py new file mode 100644 index 0000000000000000000000000000000000000000..f989a35fba48e9296a99e2bbd170562f05e90b6f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_rand_member_mode_deriv.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_randomize_unpacked_bad.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_randomize_unpacked_bad.v new file mode 100644 index 0000000000000000000000000000000000000000..d6a85358ab561b5b211029afc85c7df6578cb9f4 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_randomize_unpacked_bad.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class ex; + randc struct {logic m_x;} s; // <--- Bad: randc illegal on unpacked struct + + randc struct packed {logic m_x;} p_s; // Ok +endclass : ex + +module foo; + initial begin + ex e; + void'(e.randomize()); + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_randsequence_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_randsequence_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_randsequence_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_select_bound1.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_select_bound1.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_select_bound1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_select_crazy.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_select_crazy.v new file mode 100644 index 0000000000000000000000000000000000000000..ff33ddd6ed6bdd566ea34b5b92199d88d4a5f57c --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_select_crazy.v @@ -0,0 +1,43 @@ +// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference +// as the select expression +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 + +interface foo_intf; + logic a; +endinterface + +function integer the_other_func (input integer val); + return val; +endfunction + +module t; + genvar the_genvar; + generate + for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop + foo foo_inst(); + end + endgenerate + + bar bar_inst(); + + logic x; + assign x = foo_loop[bar_inst.THE_LP].foo_inst.y; + //localparam N = 2; + //assign x = foo_loop[N].foo_inst.y; + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module foo(); + logic y; +endmodule + +module bar(); + localparam THE_LP = 2; +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_semaphore_class_nested.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_semaphore_class_nested.v new file mode 100644 index 0000000000000000000000000000000000000000..c18f65b45231f8227c57f9e892fd4ef20ec04b35 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_semaphore_class_nested.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +class semaphore_cls; + class InnerKeyClass; + int innerKeys; + function new(int keyCount = 0); + innerKeys = keyCount; + endfunction + endclass + // Test an implementation similar to what Verilator will do internally + InnerKeyClass m_keys; + function new(int keyCount = 0); + m_keys = new(keyCount); + endfunction + function void put(int keyCount = 1); + m_keys.innerKeys += keyCount; + endfunction + task get(int keyCount = 1); + wait (m_keys.innerKeys >= keyCount); + m_keys.innerKeys -= keyCount; + endtask + function int try_get(int keyCount = 1); + if (m_keys.innerKeys >= keyCount) begin + m_keys.innerKeys -= keyCount; + return 1; + end + else begin + return 0; + end + endfunction +endclass + +`define SEMAPHORE_T semaphore_cls + +`include "t_semaphore.v" diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_sequence_sexpr_unsup.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_sequence_sexpr_unsup.v new file mode 100644 index 0000000000000000000000000000000000000000..d2ffb3a48f4bf5a797c7406ba60796ffbca46643 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_sequence_sexpr_unsup.v @@ -0,0 +1,133 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + int a; + int b; + int cyc = 0; + int res0, res1; + + localparam DELAY = 1; + + always @(posedge clk) begin + cyc <= cyc + 1; + end + + // NOTE this grammar hasn't been checked with other simulators, + // is here just to avoid uncovered code lines in the grammar. + // NOTE using 'property weak' here as sequence/endsequence not supported + sequence s_a; + a; + endsequence : s_a + sequence s_var; + logic l1, l2; + a; + endsequence + + sequence s_within; + a within(b); + endsequence + + sequence s_and; + a and b; + endsequence + + sequence s_or; + a or b; + endsequence + + sequence s_throughout; + a throughout b; + endsequence + + sequence s_intersect; + a intersect b; + endsequence + + sequence s_uni_cycdelay_id; + ## DELAY b; + endsequence + sequence s_uni_cycdelay_pid; + ## ( DELAY ) b; + endsequence + sequence s_uni_cycdelay_range; + ## [1:2] b; + endsequence + sequence s_uni_cycdelay_star; + ## [*] b; + endsequence + sequence s_uni_cycdelay_plus; + ## [+] b; + endsequence + + sequence s_cycdelay_id; + a ## DELAY b; + endsequence + sequence s_cycdelay_pid; + a ## ( DELAY ) b; + endsequence + sequence s_cycdelay_range; + a ## [1:2] b; + endsequence + sequence s_cycdelay_star; + a ## [*] b; + endsequence + sequence s_cycdelay_plus; + a ## [+] b; + endsequence + + sequence s_booleanabbrev_brastar_int; + a [* 1 ]; + endsequence + sequence s_booleanabbrev_brastar; + a [*]; + endsequence + sequence s_booleanabbrev_plus; + a [+]; + endsequence + sequence s_booleanabbrev_eq; + a [= 1]; + endsequence + sequence s_booleanabbrev_eq_range; + a [= 1:2]; + endsequence + sequence s_booleanabbrev_minusgt; + a [-> 1]; + endsequence + sequence s_booleanabbrev_minusgt_range; + a [-> 1:2]; + endsequence + + sequence p_arg_seqence(sequence inseq); + inseq; + endsequence + + sequence s_firstmatch_a; + first_match (a); + endsequence + sequence s_firstmatch_ab; + first_match (a, res0 = 1); + endsequence + sequence s_firstmatch_abc; + first_match (a, res0 = 1, res1 = 2); + endsequence + + cover sequence (s_a) $display(""); + cover sequence (@(posedge a) disable iff (b) s_a) $display(""); + cover sequence (disable iff (b) s_a) $display(""); + + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_std_randomize.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_std_randomize.py new file mode 100644 index 0000000000000000000000000000000000000000..466368b3d6395cb04882605d1a2e67924b471377 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_std_randomize.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_std_randomize_with.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_std_randomize_with.v new file mode 100644 index 0000000000000000000000000000000000000000..0c457184df6dd60705f665336fba7b78f1749508 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_std_randomize_with.v @@ -0,0 +1,53 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by PlanV GmbH. +// SPDX-License-Identifier: CC0-1.0 + +class external_cl; + int x; + int y; + + function new(); + x = 0; + y = 0; + endfunction +endclass + +module t; + initial begin + int a, b; + int limit = 10; + external_cl obj; + + // Test 1: Basic std::randomize with 'with' clause + if (std::randomize(a, b) with { 2 < a; a < 7; b < a; } != 1) $stop; + if (!(2 < a && a < 7 && b < a)) $stop; + $display("Test 1 passed: a=%0d, b=%0d", a, b); + + // Test 2: Local variable and class member with mutual constraints + obj = new; + if (std::randomize(a, obj.x) with { a > 10; a < 20; obj.x > a; obj.x < a + 5; } != 1) $stop; + if (!(a > 10 && a < 20 && obj.x > a && obj.x < a + 5)) $stop; + $display("Test 2 passed: a=%0d, obj.x=%0d (obj.x between a+1 and a+4)", a, obj.x); + + // Test 3: Reference external variable in constraint + if (std::randomize(a) with { a > 0; a < limit; } != 1) $stop; + if (!(a > 0 && a < limit)) $stop; + $display("Test 3 passed: a=%0d, limit=%0d", a, limit); + + // Test 4: Randomize class member variables + obj = new; + if (std::randomize(obj.x, obj.y) with { obj.x > 5; obj.x < 20; obj.y == obj.x + 1; } != 1) $stop; + if (!(obj.x > 5 && obj.x < 20 && obj.y == obj.x + 1)) $stop; + $display("Test 4 passed: obj.x=%0d, obj.y=%0d", obj.x, obj.y); + + // Test 5: Multiple class members and local variable + if (std::randomize(a, obj.x, obj.y) with { a > 0; a < 5; obj.x > a; obj.y > obj.x; obj.y < a + 10; } != 1) $stop; + if (!(a > 0 && a < 5 && obj.x > a && obj.y > obj.x && obj.y < a + 10)) $stop; + $display("Test 5 passed: a=%0d, obj.x=%0d, obj.y=%0d", a, obj.x, obj.y); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_stream.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_stream.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_stream.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_stream_unpack_narrower.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_stream_unpack_narrower.py new file mode 100644 index 0000000000000000000000000000000000000000..efe8cc01c1b4ba6a3b2020ce56a4787ec303ebaf --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_stream_unpack_narrower.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_cons_cast.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_cons_cast.py new file mode 100644 index 0000000000000000000000000000000000000000..d4f9864418d093ead81237ce575c0909289b80c8 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_cons_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_notfound_bad.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_notfound_bad.out new file mode 100644 index 0000000000000000000000000000000000000000..37612f978c7d77d09d89b85c1aa580801f7230ab --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_notfound_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_struct_notfound_bad.v:13:9: Member 'nfmember' not found in structure + : ... note: In instance 't' + 13 | s.nfmember = 0; + | ^~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_packed_init_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_packed_init_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..5be41342110fd58b71da790d51608f4abb64ea14 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_struct_packed_init_bad.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +#test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_structu_dataType_assignment.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_structu_dataType_assignment.v new file mode 100644 index 0000000000000000000000000000000000000000..734b4dd4625cfc3d3815970535c562a8374f60e1 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_structu_dataType_assignment.v @@ -0,0 +1,187 @@ +// DESCRIPTION: Verilator: Verilog Test module for specialized type default values +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Mostafa Gamal. +// SPDX-License-Identifier: CC0-1.0 + +/* verilator lint_off UNPACKED */ + +module top(); + + typedef struct { // IEEE 1800-2023 5.10 + int a; + shortint b; + } ab_struct; + + typedef struct { // IEEE 1800-2023 10.9.2 + int x; + int y; + } st_struct; + + typedef struct { // IEEE 1800-2023 10.9.2 + logic [7:0] a; + bit b; + bit signed [31:0] c; + int s; + } sa_struct; + + + typedef struct { // IEEE 1800-2023 10.9.2 + int A; + struct { + int B, C; + } BC1, BC2; + } DEF_struct; + + + typedef struct { // IEEE 1800-2023 10.9.2 + int A; + struct { + int B, C; + struct { + int D, E; + struct { + int F; + shortint G; + } FG1; + } DE1; + } BC1; + } HIJ_struct; + + // struct ab + ab_struct ab; + ab_struct abkey[1:0]; + + // struct st + st_struct st; + int k = 1; + + // struct sa + sa_struct sa; + + // struct DEF + DEF_struct DEF; + + // struct HIJ + HIJ_struct HIJ; + + initial begin + // struct ab + ab = '{0, 0}; //constant member by position + if (ab.a != 0) $stop; + if (ab.b != 0) $stop; + + + ab = '{default: 0}; //default value + if (ab.a != 0) $stop; + if (ab.b != 0) $stop; + + + ab = '{int: 1, shortint: 0}; //data type and default value + if (ab.a != 1) $stop; + if (ab.b != 0) $stop; + + + abkey[1:0] = '{'{a:1, b:2}, '{int:2, shortint:3}}; // member: value & data_type: value + if (abkey[1].a != 1) $stop; + if (abkey[1].b != 2) $stop; + if (abkey[0].a != 2) $stop; + if (abkey[0].b != 3) $stop; + + + // struct st + st = '{1, 2+k}; //constant member by position + if (st.x != 1) $stop; + if (st.y != 2+k) $stop; + + st = '{x:2, y:3+k}; //member: value + if (st.x != 2) $stop; + if (st.y != 3+k) $stop; + + st = '{int:2, int:3+k}; //data_type: value override + if (st.x != 3+k) $stop; + if (st.y != 3+k) $stop; + + + // struct sa + sa = '{default:'1}; + if (sa.a != '1) $stop; + if (sa.b != '1) $stop; + if (sa.c != '1) $stop; + if (sa.s != '1) $stop; + + sa = '{default:'1, int: 5}; + if (sa.a != '1) $stop; + if (sa.b != '1) $stop; + if (sa.c != '1) $stop; + if (sa.s != 5) $stop; + + + sa = '{default:'1, int: 5, b: 0}; + if (sa.a != '1) $stop; + if (sa.b != 0) $stop; + if (sa.c != '1) $stop; + if (sa.s != 5) $stop; + + + // struct DEF + DEF = '{A:1, BC1:'{B:2, C:3}, BC2:'{B:4,C:5}}; + if (DEF.A != 1) $stop; + if (DEF.BC1.B != 2) $stop; + if (DEF.BC1.C != 3) $stop; + if (DEF.BC2.B != 4) $stop; + if (DEF.BC2.C != 5) $stop; + + + DEF = '{int:0, BC1:'{int:10}, BC2:'{default:5}}; + if (DEF.A != 0) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 5) $stop; + if (DEF.BC2.C != 5) $stop; + + DEF = '{default:1, BC1:'{int:10}, BC2:'{default:5}}; + if (DEF.A != 1) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 5) $stop; + if (DEF.BC2.C != 5) $stop; + + DEF = '{default:10}; + if (DEF.A != 10) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 10) $stop; + if (DEF.BC2.C != 10) $stop; + + DEF = '{int:10}; + if (DEF.A != 10) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 10) $stop; + if (DEF.BC2.C != 10) $stop; + + // struct HIJ + HIJ = '{int:10, default: 5}; + if (HIJ.A != 10) $stop; + if (HIJ.BC1.B != 10) $stop; + if (HIJ.BC1.C != 10) $stop; + if (HIJ.BC1.DE1.D != 10) $stop; + if (HIJ.BC1.DE1.E != 10) $stop; + if (HIJ.BC1.DE1.FG1.F != 10) $stop; + if (HIJ.BC1.DE1.FG1.G != 5) $stop; + + HIJ = '{shortint:10, default: 5}; + if (HIJ.A != 5) $stop; + if (HIJ.BC1.B != 5) $stop; + if (HIJ.BC1.C != 5) $stop; + if (HIJ.BC1.DE1.D != 5) $stop; + if (HIJ.BC1.DE1.E != 5) $stop; + if (HIJ.BC1.DE1.FG1.F != 5) $stop; + if (HIJ.BC1.DE1.FG1.G != 10) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_sys_system.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_sys_system.v new file mode 100644 index 0000000000000000000000000000000000000000..fc3bc66bc22f8d7a67c5c5a772946b1f9fd1a97d --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_sys_system.v @@ -0,0 +1,39 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + integer i; + string s; + + initial begin +`ifndef VERILATOR + `ifndef VCS + `ifndef NC + $system(); // Legal per spec, but not supported everywhere and nonsensical + `endif + `endif +`endif + $system("ls"); // IData + $system("exit 0"); // QData + $system("echo hello"); // WDATA +`ifndef VCS + i = $system("exit 0"); + if (i!==0) $stop; + i = $system("exit 10"); + if (i!==10) $stop; + i = $system("exit 20"); // Wide + if (i!==20) $stop; + s = "exit 10"; + i = $system(s); // String + if (i!==10) $stop; +`endif + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_dlyassign.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_dlyassign.v new file mode 100644 index 0000000000000000000000000000000000000000..42cefffce8268fd105f74d93f3faf1e9b8906a3a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_dlyassign.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +// bug3781 +module t; + logic clk; + logic [7:0] data; + logic [3:0] ptr; + logic [7:0] mem[16]; + + initial begin + clk = 1'b0; + fork forever #5 clk = ~clk; join_none + ptr = '0; + #10 data = 1; + #10 if (mem[ptr] != data) $stop; + #10 data = 2; + #10 if (mem[ptr] != data) $stop; + #10 data = 3; + #10 if (mem[ptr] != data) $stop; + #10 $write("*-* All Finished *-*\n"); + $finish; + end + + always @(posedge clk) begin + mem[ptr] <= #1 data; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_fork_join.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_fork_join.out new file mode 100644 index 0000000000000000000000000000000000000000..46f216b1e08390cbb13925bc61105f6c596f27b1 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_fork_join.out @@ -0,0 +1,25 @@ +[0] fork..join process 4 +[2] fork..join process 3 +[4] fork..join process 2 +[8] fork..join process 1 +[16] fork in fork starts +[16] fork..join process 8 +[20] fork..join process 7 +[24] fork..join process 6 +[32] fork..join process 5 +[32] fork..join in fork ends +[64] main process +fork..join_any process 2 +back in main process +fork..join_any process 1 +fork..join_any process 1 +back in main process +fork..join_any process 2 +in main process +fork..join_none process 1 +fork..join_none process 2 +fork..join_none process 3 +fork..join_none process 2 again +fork..join_none process 1 again +fork..join_none process 3 again +*-* All Finished *-* diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_fork_rec_method.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_fork_rec_method.py new file mode 100644 index 0000000000000000000000000000000000000000..c53b5526261f426ecf0e1d0b31f3499571ddba1c --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_fork_rec_method.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_wait_long.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_wait_long.v new file mode 100644 index 0000000000000000000000000000000000000000..c9417b9130ac576a14ba461dc0adcb766e9bee38 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_timing_wait_long.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +`timescale 1ns/1ps + +module timing_wait_long(); + localparam real FULL_TIME = 5e6; + /* verilator lint_off WIDTHTRUNC */ + localparam [22:0] FIT_TIME = int'(5e6); + localparam [21:0] TRUNCATED_TIME = int'(5e6); // 805696 + /* verilator lint_on WIDTHTRUNC */ + + real realvar_time = 5e6; + time timevar; + initial begin + #5ms; + $display("Current realtime: %d == %d", time'($realtime), time'(1 * 5e9)); + + realvar_time = realvar_time + 1; + #realvar_time; + $display("Current realtime: %d == %d", time'($realtime), time'(2 * 5e6 + 1)); + + timevar = time'(realvar_time - 2); + #timevar; + $display("Current realtime: %d == %d", time'($realtime), time'(3 * 5e6)); + + $display("FULL_TIME: %f", FULL_TIME); + #FULL_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(4 * 5e6)); + + $display("FIT_TIME: %d -- %f", FIT_TIME, real'(FIT_TIME)); + #FIT_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6)); + + $display("TRUNCATED_TIME: %d -- %f", TRUNCATED_TIME, real'(TRUNCATED_TIME)); + #TRUNCATED_TIME; + $display("Current realtime: %d == %d", time'($realtime), time'(5 * 5e6 + real'(int'(5e6) % 2**22))); + + $write("*-* All Finished *-*\n"); + $finish(); + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_fst_sc.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_fst_sc.v new file mode 100644 index 0000000000000000000000000000000000000000..52c148bd5b6cb51d6fac054809803a3c3c21c955 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_fst_sc.v @@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc; + reg rstn; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; + + logic [4:0] state; + + Test test (/*AUTOINST*/ + // Outputs + .state (state[4:0]), + // Inputs + .clk (clk), + .rstn (rstn)); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + rstn <= ~'1; + end + else if (cyc<10) begin + rstn <= ~'1; + end + else if (cyc<90) begin + rstn <= ~'0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( + input clk, + input rstn, + output logic [4:0] state + ); + + logic [4:0] state_w; + logic [4:0] state_array [3]; + assign state = state_array[0]; + + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end + + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) + state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) + state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_no_top_name.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_no_top_name.py new file mode 100644 index 0000000000000000000000000000000000000000..ebe166cbc335a01bfabd80fef3dcaadc430b99a3 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_no_top_name.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary --main-top-name '-' --trace-vcd -Wno-MULTITOP"]) + +test.execute() + +test.vcd_identical(test.trace_filename, test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_split_cfuncs_dpi_export.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_split_cfuncs_dpi_export.v new file mode 100644 index 0000000000000000000000000000000000000000..aa82f7813b36f40879e816703ca6aad3c2cbcae5 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_split_cfuncs_dpi_export.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Varun Koyyalagunta. +// SPDX-License-Identifier: CC0-1.0 + +module t (); + + function automatic void func(); + endfunction + export "DPI-C" function func; + + initial begin + $dumpfile("dump.vcd"); + $dumpvars(); + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_two_dump_cc.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_two_dump_cc.out new file mode 100644 index 0000000000000000000000000000000000000000..d65b1e2e940683967da900d32c8f6e480bde3826 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_two_dump_cc.out @@ -0,0 +1,128 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module topa $end + $var wire 1 # clk $end + $scope module t $end + $var wire 1 # clk $end + $var wire 32 $ cyc [31:0] $end + $var wire 32 % c_trace_on [31:0] $end + $scope module sub $end + $var wire 32 & inside_sub_a [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module topb $end + $var wire 1 ( clk $end + $scope module t $end + $var wire 1 ( clk $end + $var wire 32 + cyc [31:0] $end + $var wire 32 , c_trace_on [31:0] $end + $var real 64 ) r $end + $scope module sub $end + $var wire 32 - inside_sub_a [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#10 +1# +b00000000000000000000000000000001 $ +b00000000000000000000000000000000 % +1( +r0 ) +b00000000000000000000000000000001 & +b00000000000000000000000000000001 + +b00000000000000000000000000000000 , +b00000000000000000000000000000010 - +#15 +0# +0( +#20 +1# +b00000000000000000000000000000010 $ +b00000000000000000000000000000011 % +1( +r0.1 ) +#25 +0# +0( +#30 +1# +b00000000000000000000000000000011 $ +b00000000000000000000000000000100 % +1( +r0.2 ) +#35 +0# +0( +#40 +1# +b00000000000000000000000000000100 $ +b00000000000000000000000000000101 % +1( +r0.3 ) +#45 +0# +0( +#50 +1# +b00000000000000000000000000000101 $ +b00000000000000000000000000000110 % +1( +r0.4 ) +#55 +0# +0( +#60 +1# +b00000000000000000000000000000110 $ +b00000000000000000000000000000111 % +1( +r0.5 ) +#65 +0# +0( +#70 +1# +b00000000000000000000000000000111 $ +b00000000000000000000000000001000 % +1( +r0.6 ) +#75 +0# +0( +#80 +1# +b00000000000000000000000000001000 $ +b00000000000000000000000000001001 % +1( +r0.7 ) +#85 +0# +0( +#90 +1# +b00000000000000000000000000001001 $ +b00000000000000000000000000001010 % +1( +r0.7999999999999999 ) +#95 +0# +0( +#100 +1# +b00000000000000000000000000001010 $ +b00000000000000000000000000001011 % +1( +r0.8999999999999999 ) +#105 +0# +0( +#110 +1# +b00000000000000000000000000001011 $ +b00000000000000000000000000001100 % +1( +r0.9999999999999999 ) diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_two_dumpfst_cc.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_two_dumpfst_cc.out new file mode 100644 index 0000000000000000000000000000000000000000..f64a6554a2d479135e0c2e20922ade4e1c1a2ad4 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_trace_two_dumpfst_cc.out @@ -0,0 +1,136 @@ +$date + Sat Mar 30 14:01:55 2024 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module topa $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc [31:0] $end +$var integer 32 # c_trace_on [31:0] $end +$scope module sub $end +$var integer 32 $ inside_sub_a [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$scope module topb $end +$var wire 1 % clk $end +$scope module t $end +$var wire 1 % clk $end +$var integer 32 & cyc [31:0] $end +$var integer 32 ' c_trace_on [31:0] $end +$var real 64 ( r $end +$scope module sub $end +$var integer 32 ) inside_sub_a [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#10 +$dumpvars +b00000000000000000000000000000010 ) +r0 ( +b00000000000000000000000000000000 ' +b00000000000000000000000000000001 & +1% +b00000000000000000000000000000001 $ +b00000000000000000000000000000000 # +b00000000000000000000000000000001 " +1! +$end +#15 +0! +0% +#20 +1% +1! +b00000000000000000000000000000010 " +b00000000000000000000000000000011 # +r0.1 ( +#25 +0! +0% +#30 +1% +1! +r0.2 ( +b00000000000000000000000000000100 # +b00000000000000000000000000000011 " +#35 +0! +0% +#40 +1% +1! +b00000000000000000000000000000100 " +b00000000000000000000000000000101 # +r0.3 ( +#45 +0! +0% +#50 +1% +1! +r0.4 ( +b00000000000000000000000000000110 # +b00000000000000000000000000000101 " +#55 +0! +0% +#60 +1% +1! +b00000000000000000000000000000110 " +b00000000000000000000000000000111 # +r0.5 ( +#65 +0! +0% +#70 +1% +1! +r0.6 ( +b00000000000000000000000000001000 # +b00000000000000000000000000000111 " +#75 +0! +0% +#80 +1% +1! +b00000000000000000000000000001000 " +b00000000000000000000000000001001 # +r0.7 ( +#85 +0! +0% +#90 +1% +1! +r0.7999999999999999 ( +b00000000000000000000000000001010 # +b00000000000000000000000000001001 " +#95 +0! +0% +#100 +1% +1! +b00000000000000000000000000001010 " +b00000000000000000000000000001011 # +r0.8999999999999999 ( +#105 +0! +0% +#110 +1% +1! +r0.9999999999999999 ( +b00000000000000000000000000001100 # +b00000000000000000000000000001011 " diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_array_pull.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_array_pull.v new file mode 100644 index 0000000000000000000000000000000000000000..b29d1d5b5380f73f615d051e018cea187c43f32d --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_array_pull.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2018 by Rod Steward. +// SPDX-License-Identifier: CC0-1.0 + +module IOBUF ( input T, input I, output O, inout IO ); + assign O = IO; + assign IO = T ? 1'bz : I; +endmodule + +module t + ( + input [7:0] inlines, + output [7:0] outlines, + inout [7:0] iolines, + + input inctrl + ); + + generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D + IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) ); + pullup d_pup (iolines[i]); + end + endgenerate + + IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) ); + pullup d_0_pup (iolines[0]); + + IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) ); + pullup d_1_pup (iolines[1]); + + IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) ); + pullup d_2_pup (iolines[2]); + + IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) ); + pullup d_3_pup (iolines[3]); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_struct_packed.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_struct_packed.v new file mode 100644 index 0000000000000000000000000000000000000000..df1f8aa6e4b6de196905b10102c013328cbe4c4f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_struct_packed.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +typedef struct packed { + bit x; +} p_struct_t; + +module p_mh (inout p_struct_t p_i, inout p_struct_t p_o); + // OK: module p_mh (input p_struct_t p_i, output p_struct_t p_o); + assign p_o.x = p_i.x; +endmodule + +module t; + p_struct_t p_i, p_o; + + p_mh p_mh(p_i, p_o); + + initial begin + p_i.x = 1; + #1; + // issue #4925 + if (p_o.x != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_top_en_out_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_top_en_out_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..6b0e5e22871e43a5158ea501dc3722be50710125 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_tri_top_en_out_bad.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(make_top_shell=False, + make_main=1, + verilator_make_gmake=True, + verilator_flags2=["--exe --pins-inout-enables --no-timing -Wno-STMTDLY"]) + +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__out') +test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + ".h", r'internal_sub_io__en') + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_typename.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_typename.out new file mode 100644 index 0000000000000000000000000000000000000000..f8ebfd10d748abb77624178ae95983e7a3941ee0 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_typename.out @@ -0,0 +1,29 @@ +"real" ==? "real" +"bit" ==? "bit" +"int" ==? "int" +"logic" ==? "logic" +"string" ==? "string" +"real" ==? "real" +"logic" ==? "logic" +"bit" ==? "bit" +"bit[2:0]" ==? "bit[2:0]" +"bit$[3:2]" ==? "bit$[3:2]" +"bit$[3:1][4:5]" ==? "bit$[3:1][4:5]" + +"bit" ==? "bit" +"bit[2:0]" ==? "bit[2:0]" +"int" ==? "int" +"bit[9:1]" ==? "bit[9:1]" +"bit[9:1]" ==? "bit[9:1]" +"string$[longint]" ==? "string$[longint]" +"int$[$]" ==? "int$[$]" +"int$[$:3]" ==? "int$[$:3]" +"bit$[]" ==? "bit$[]" + +"enum{A=32'h0;B=32'h1;C=32'h63;}A::__typeimpmod1" ==? "enum{A=32'sd0,B=32'sd1,C=32'sd99}A::" +"struct{bit A;bit B;}t.AB_t" ==? "struct{bit A;bit B;}" +"struct{bit A;bit B;}t.AB_t$[0:9]" ==? "struct{bit A;bit B;}top.AB_t$[0:9]" +"union{bit A;bit B;}t.UAB_t" ==? "union{bit A;bit B;}" +"class{}Cls" ==? "class{}t.Cls " + +*-* All Finished *-* diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_udp_bad_multi_output.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_udp_bad_multi_output.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_udp_bad_multi_output.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_udp_param_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_udp_param_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_udp_param_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_unconnected_bad.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_unconnected_bad.py new file mode 100644 index 0000000000000000000000000000000000000000..31228c9a7ae0c26c6e137c7467f12bdbb7f1674a --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_unconnected_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_unpacked_struct_eq.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_unpacked_struct_eq.v new file mode 100644 index 0000000000000000000000000000000000000000..b2a064a65974f2336e5695026ece32d5fe4bee1c --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_unpacked_struct_eq.v @@ -0,0 +1,68 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + typedef struct{ + bit [31:0] subarr[4]; + } arr_str_t; + typedef struct { + string txt; + struct { + bit m0; + bit [3:0] m1; + bit [7:0] arr[2][3]; + arr_str_t str[5]; + } sub; + } struct_t; + struct_t s1; + struct_t s2; + struct_t s3; + + assign {s1.sub.m0, s1.sub.m1} = {1'b0, 4'h5}; + assign {s2.sub.m0, s2.sub.m1} = {1'b0, 4'h5}; + assign s1.txt = "text"; + assign s2.txt = "text"; + + assign {s1.sub.arr[0][0], s2.sub.arr[0][0]} = {8'h01, 8'h01}; + assign {s1.sub.arr[0][1], s2.sub.arr[0][1]} = {8'h02, 8'h02}; + assign {s1.sub.arr[0][2], s2.sub.arr[0][2]} = {8'h03, 8'h03}; + assign {s1.sub.arr[1][0], s2.sub.arr[1][0]} = {8'h04, 8'h04}; + assign {s1.sub.arr[1][1], s2.sub.arr[1][1]} = {8'h05, 8'h05}; + assign {s1.sub.arr[1][2], s2.sub.arr[1][2]} = {8'h06, 8'h06}; + + assign {s3.sub.m0, s3.sub.m1} = {1'b0, 4'h5}; + assign s3.txt = "text"; + + assign s3.sub.arr[0][0] = 8'h01; + assign s3.sub.arr[0][1] = 8'h02; + assign s3.sub.arr[0][2] = 8'h03; + assign s3.sub.arr[1][0] = 8'h24; // One mismatch + assign s3.sub.arr[1][1] = 8'h05; + assign s3.sub.arr[1][2] = 8'h06; + + initial begin + #1; + if(s3 == s1) $stop; + if(s1 == s2 && s3 != s1) begin + $write("*-* All Finished *-*\n"); + $finish; + end else begin + $fatal; + end + end +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_unroll_nested_unroll.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_unroll_nested_unroll.py new file mode 100644 index 0000000000000000000000000000000000000000..c47ce67e5e2d87c586010ed976f6fe0ac502b865 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_unroll_nested_unroll.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') +test.top_filename = 't/t_unroll_nested.v' +test.golden_filename = 't/t_unroll_nested.out' + +test.compile(v_flags2=['+define+TEST_FULL', '--stats']) + +test.execute(expect_filename=test.golden_filename) + +test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled iterations\s+(\d+)', 107) +test.file_grep(test.stats, r'Optimizations, Loop unrolling, Unrolled loops\s+(\d+)', 27) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_var_dup2.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_var_dup2.v new file mode 100644 index 0000000000000000000000000000000000000000..d2b18006f777736808cffb7d6794172ea7ba2e14 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_var_dup2.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Legal with ANSI Verilog 2001 style ports +module t + ( + output wire ok_ow, + output reg ok_or); + + wire ok_o_w; + reg ok_o_r; +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_var_dup3.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_var_dup3.py new file mode 100644 index 0000000000000000000000000000000000000000..c2d9851140c139d8e8a9a34cabde6c6157dcc2df --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_var_dup3.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint() + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_virtual_interface_param_bind.v b/snapshots/verilator_verilator_pr6833/test_regress/t/t_virtual_interface_param_bind.v new file mode 100644 index 0000000000000000000000000000000000000000..9b70d86ccb5cd9eb8e81b9732e0f01dd142d2210 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_virtual_interface_param_bind.v @@ -0,0 +1,30 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +interface b_if; + int x = 1; +endinterface + +module t; + bind m b_if if_bind (); + m #(.p(2)) m_i (); + + typedef virtual b_if vif_t; + initial begin + vif_t vif = t.m_i.if_bind; + int y = t.m_i.if_bind.x; + + if (vif.x != 1) $stop; + if (y != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module m #( + parameter p = 1 +) (); +endmodule diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_vlt_match_contents.vlt b/snapshots/verilator_verilator_pr6833/test_regress/t/t_vlt_match_contents.vlt new file mode 100644 index 0000000000000000000000000000000000000000..e568f5af02578f9adfe52227c7182bd0ec54a63f --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_vlt_match_contents.vlt @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2024 by Ethan Sifferman. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +lint_off -rule DECLFILENAME -file "*/t_vlt_match_contents.v" -contents "* MATCH_VERSION*" +lint_off -rule UNUSEDSIGNAL -file "*/t_vlt_match_contents.v" -contents "* MATCH_VERSION*" -match "*MATCH_VERSION*" +lint_off -rule UNUSEDSIGNAL -file "*/t_vlt_match_contents.v" -contents "* MATCH_VERSION*" -match "*usignal_contents_suppress*" +lint_off -rule UNUSEDSIGNAL -file "*/t_vlt_match_contents.v" -contents "* NOT_VERSION*" -match "*usignal_contents_mismatch*" diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_vpi_zero_time_cb.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_vpi_zero_time_cb.py new file mode 100644 index 0000000000000000000000000000000000000000..aff674d1e917e440567a8eb50b61b54bc67a208d --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_vpi_zero_time_cb.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile( + make_main=False, + make_pli=True, + sim_time=2100, + iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DIVERILOG"], + v_flags2=["+define+USE_VPI_NOT_DPI"], + verilator_flags2=["--exe --vpi --no-l2name", test.pli_filename, "-LDFLAGS '-ldl -rdynamic'"]) + +test.execute(use_libvpi=True, all_run_flags=['+PLUS +INT=1234 +STRSTR']) + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_vthread.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_vthread.py new file mode 100644 index 0000000000000000000000000000000000000000..670b5c0fa448e9a8f8cb4e74d04d6016173cf702 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_vthread.py @@ -0,0 +1,51 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_vthread.v" + + +def gen(filename, n): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_vthread.py\n") + fh.write("module genmod #(int val = 0)(clk, o);\n") + fh.write(" input clk;\n") + fh.write(" output int o;\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" o <= val;\n") + fh.write(" end\n") + fh.write("endmodule\n") + fh.write("module t (clk, o);\n") + fh.write(" input clk;\n") + fh.write(" output int o;\n") + for i in range(0, n + 1): + fh.write(" int r" + str(i) + ";\n") + fh.write(" genmod #(.val(" + str(i) + ")) rm" + str(i) + " (.clk, .o(r" + str(i) + + "));\n") + fh.write(" always @ (posedge clk) begin\n") + fh.write(" o <= r" + str(n) + ";\n") + fh.write(' $write("*-* All Finished *-*\\n");' + "\n") + fh.write(' $finish;' + "\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename, 6000) + +test.compile( + # use --trace-vcd to generate trace files that can be parallelized + verilator_flags2=["--stats --trace-vcd --verilate-jobs 2"]) + +test.execute() + +test.file_grep(test.stats, r'Verilate jobs: 2') + +test.passes() diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_x_rand_stability_zeros.out b/snapshots/verilator_verilator_pr6833/test_regress/t/t_x_rand_stability_zeros.out new file mode 100644 index 0000000000000000000000000000000000000000..fe1f4ba0a3747aa25a2f6a16f9c88c4664608308 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_x_rand_stability_zeros.out @@ -0,0 +1,17 @@ +uninitialized = 0x00000000 +x_assigned (initial) = 0x00000000 +uninitialized2 = 0x00000000 +big = 0x0000000000000000000000000000000000000000000000000000000000000000 +random_init = 0x952aaa76 +top.t.the_sub_yes_inline_1 no_init 0x0 +top.t.the_sub_yes_inline_2 no_init 0x0 +top.t.the_sub_no_inline_1 no_init 0x0 +top.t.the_sub_no_inline_2 no_init 0x0 +rand = 0xe3e54aaa +rand = 0xe85acf2d +rand = 0x15e12c6a +rand = 0x0f7f28c0 +rand = 0xe189c52a +x_assigned = 0x486aeb2d +Last rand = 0xf0700dbf +*-* All Finished *-* diff --git a/snapshots/verilator_verilator_pr6833/test_regress/t/t_xml_flat_vlvbound.py b/snapshots/verilator_verilator_pr6833/test_regress/t/t_xml_flat_vlvbound.py new file mode 100644 index 0000000000000000000000000000000000000000..046b5ff50dfb4d099eb20c71c2ce49fef0839c29 --- /dev/null +++ b/snapshots/verilator_verilator_pr6833/test_regress/t/t_xml_flat_vlvbound.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +out_filename = test.obj_dir + "/V" + test.name + ".xml" + +test.compile(verilator_flags2=['--no-std', '-Wno-DEPRECATED --xml-only', '--flatten'], + verilator_make_gmake=False, + make_top_shell=False, + make_main=False) + +test.files_identical(out_filename, test.golden_filename) + +test.passes()