Datasets:
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task_categories:
- text-generation
language:
- code
tags:
- hardware
- rtl
- verilog
- systemverilog
- fpga
- asic
- digital-design
- code-generation
pretty_name: CVDP Example Problems
size_categories:
- 1K<n<10K
---
# hardware-cvdp-examples
CVDP Example Problems - 5 comprehensive hardware design problems
## Dataset Overview
This dataset is part of a comprehensive collection of hardware design datasets for training and evaluating LLMs on Verilog/SystemVerilog code generation and hardware design tasks.
## Files
- **cvdp_problems.json**: 5 CVDP example problems with full content
- **analysis.json**: Analysis of CVDP problems
## Usage
```python
from datasets import load_dataset
# Load the dataset
dataset = load_dataset('AbiralArch/hardware-cvdp-examples')
# Access the data
data = dataset['train']
```
## Citation
If you use this dataset in your research, please cite:
```bibtex
@dataset{hardware_design_dataset,
title={hardware-cvdp-examples},
author={Architect-Chips},
year={2025},
url={https://huggingface.co/datasets/AbiralArch/hardware-cvdp-examples}
}
```
## License
This dataset is provided for research and educational purposes. Please check individual source licenses.
## Acknowledgments
This dataset combines data from multiple sources in the hardware design community. We thank all contributors and original dataset creators.
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