-- ============================================================================
-- tlm_p3_gate testbench — 10 test vectors including AES canonical
-- Authors: Ahmad Ali Parr, Jessica L. Williams (SNAPKITTYWEST)
-- Run with: ghdl -a *.vhd && ghdl -e tlm_p3_gate_tb && ghdl -r tlm_p3_gate_tb
-- ============================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tlm_p3_gate_tb is
end entity tlm_p3_gate_tb;

architecture behavioral of tlm_p3_gate_tb is
    signal a0, a1, a2, a3 : std_logic_vector(7 downto 0) := (others => '0');
    signal y0, y1, y2, y3 : std_logic_vector(7 downto 0);
    signal clk        : std_logic := '0';
    signal test_passed : boolean  := true;

    component tlm_p3_gate
        port (
            a0 : in  std_logic_vector(7 downto 0);
            a1 : in  std_logic_vector(7 downto 0);
            a2 : in  std_logic_vector(7 downto 0);
            a3 : in  std_logic_vector(7 downto 0);
            y0 : out std_logic_vector(7 downto 0);
            y1 : out std_logic_vector(7 downto 0);
            y2 : out std_logic_vector(7 downto 0);
            y3 : out std_logic_vector(7 downto 0)
        );
    end component;

    procedure check(
        constant name         : in string;
        constant exp0, exp1, exp2, exp3 : in std_logic_vector(7 downto 0);
        signal   act0, act1, act2, act3 : in std_logic_vector(7 downto 0);
        signal   ok : inout boolean
    ) is
        variable fail : boolean := false;
    begin
        if act0 /= exp0 then report name & ": y0 fail exp=" & to_hstring(exp0) & " got=" & to_hstring(act0) severity error; fail := true; end if;
        if act1 /= exp1 then report name & ": y1 fail exp=" & to_hstring(exp1) & " got=" & to_hstring(act1) severity error; fail := true; end if;
        if act2 /= exp2 then report name & ": y2 fail exp=" & to_hstring(exp2) & " got=" & to_hstring(act2) severity error; fail := true; end if;
        if act3 /= exp3 then report name & ": y3 fail exp=" & to_hstring(exp3) & " got=" & to_hstring(act3) severity error; fail := true; end if;
        if fail then ok := false; else report name & ": PASS" severity note; end if;
    end procedure;

begin
    uut: entity work.tlm_p3_gate
        port map (a0=>a0, a1=>a1, a2=>a2, a3=>a3, y0=>y0, y1=>y1, y2=>y2, y3=>y3);

    clk <= not clk after 5 ns;

    stim: process
    begin
        report "=== tlm_p3_gate MixColumns Testbench ===" severity note;

        -- Test 1: AES canonical D4 BF 5D 30 → 04 66 81 E5
        a0<=x"D4"; a1<=x"BF"; a2<=x"5D"; a3<=x"30"; wait for 20 ns;
        check("T1 D4_BF_5D_30", x"04",x"66",x"81",x"E5", y0,y1,y2,y3, test_passed);

        -- Test 2: Zero → Zero
        a0<=x"00"; a1<=x"00"; a2<=x"00"; a3<=x"00"; wait for 20 ns;
        check("T2 Zero",        x"00",x"00",x"00",x"00", y0,y1,y2,y3, test_passed);

        -- Test 3: 01 02 04 08 (low bytes, no MSB)
        a0<=x"01"; a1<=x"02"; a2<=x"04"; a3<=x"08"; wait for 20 ns;
        check("T3 b7=0",        x"0D",x"1A",x"34",x"29", y0,y1,y2,y3, test_passed);

        -- Test 4: 80 80 80 80 (all MSBs set, reduction fires)
        a0<=x"80"; a1<=x"80"; a2<=x"80"; a3<=x"80"; wait for 20 ns;
        check("T4 b7=1",        x"1B",x"1B",x"1B",x"1B", y0,y1,y2,y3, test_passed);

        -- Test 5: FF 00 00 00
        a0<=x"FF"; a1<=x"00"; a2<=x"00"; a3<=x"00"; wait for 20 ns;
        check("T5 FF_00_00_00", x"E2",x"1B",x"00",x"E2", y0,y1,y2,y3, test_passed);

        -- Test 6: AA 55 AA 55 (alternating)
        a0<=x"AA"; a1<=x"55"; a2<=x"AA"; a3<=x"55"; wait for 20 ns;
        check("T6 AA_55_AA_55", x"FF",x"00",x"FF",x"00", y0,y1,y2,y3, test_passed);

        -- Test 7: FF FF FF FF (all ones — should XOR to zero)
        a0<=x"FF"; a1<=x"FF"; a2<=x"FF"; a3<=x"FF"; wait for 20 ns;
        check("T7 FF_FF_FF_FF", x"00",x"00",x"00",x"00", y0,y1,y2,y3, test_passed);

        -- Test 8: 3C 3C 3C 3C (repeated byte)
        a0<=x"3C"; a1<=x"3C"; a2<=x"3C"; a3<=x"3C"; wait for 20 ns;
        check("T8 3C_3C_3C_3C", x"00",x"00",x"00",x"00", y0,y1,y2,y3, test_passed);

        -- Test 9: 01 00 00 00 (single bit)
        a0<=x"01"; a1<=x"00"; a2<=x"00"; a3<=x"00"; wait for 20 ns;
        check("T9 01_00_00_00", x"01",x"01",x"00",x"01", y0,y1,y2,y3, test_passed);

        -- Test 10: 80 00 00 00 (MSB only, triggers reduction)
        a0<=x"80"; a1<=x"00"; a2<=x"00"; a3<=x"00"; wait for 20 ns;
        check("T10 80_00_00_00",x"9B",x"1B",x"00",x"9B", y0,y1,y2,y3, test_passed);

        report "=== Testbench done ===" severity note;
        if test_passed then
            report "ALL TESTS PASSED" severity note;
        else
            report "FAILURES DETECTED" severity error;
        end if;
        wait;
    end process;

end architecture behavioral;