vhdl/anu_entropy_bridge.vhd

-- ============================================================================
-- ANu Entropy Bridge — VHDL RTL
-- Vacuum Fluctuation → P3Q Seed Interface
-- Authors: Ahmad Ali Parr, Jessica L. Williams (SNAPKITTYWEST)
-- ============================================================================
--
-- Interface mapping:
--   Vacuum Fluctuations (ADC) → Entropy Normalization → P3Q 256-bit Seed
--   Timestamp → T=SQL Hash → Worm Chain Index
--
-- ANu Normalization: MSB of each 16-bit ADC sample becomes one seed bit.
-- After 256 valid samples the seed register is full and q_seed_valid pulses.
--
-- T=SQL Hash:
--   t_sql_index = (timestamp[63:32] XOR timestamp[31:0]) XOR T_SQL_SALT
--   Deterministic, zero-latency (combinational).
--   Collisions are mathematically inevitable (Pigeonhole, 64→32 bit).
--   P4 settler resolves collisions via monotone sequence counter.
--
-- Evidence boundary:
--   VHDL models the interface — does not physically connect to vacuum energy.
-- ============================================================================

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity anu_entropy_bridge is
    port (
        clk         : in  std_logic;
        rst_n       : in  std_logic;
        -- Raw Vacuum Fluctuation Input (Analog-to-Digital converted)
        vac_raw     : in  std_logic_vector(15 downto 0);
        vac_valid   : in  std_logic;
        -- T=SQL Temporal Indexing
        timestamp_in : in  std_logic_vector(63 downto 0);
        -- Output to P3Q Quantum Interface
        q_seed_valid : out std_logic;
        q_seed_data  : out std_logic_vector(255 downto 0);
        t_sql_index  : out std_logic_vector(31 downto 0)
    );
end entity anu_entropy_bridge;

architecture rtl of anu_entropy_bridge is
    signal seed_reg  : std_logic_vector(255 downto 0) := (others => '0');
    signal bit_count : unsigned(7 downto 0)            := (others => '0');

    -- T=SQL Hash Constant (DEADBEEF — explicit, not magic)
    constant T_SQL_SALT : std_logic_vector(31 downto 0) := x"DEADBEEF";
begin

    -- ── ANu Normalization ─────────────────────────────────────────────────
    -- Quantize: MSB of raw fluctuation (vac_raw[15]) → next seed bit.
    -- Equivalent to: S_i = sign(ξ(t_i) − μ) where μ = mid-scale voltage.
    process(clk, rst_n)
    begin
        if rst_n = '0' then
            seed_reg     <= (others => '0');
            bit_count    <= (others => '0');
            q_seed_valid <= '0';
            q_seed_data  <= (others => '0');
        elsif rising_edge(clk) then
            q_seed_valid <= '0';

            if vac_valid = '1' then
                -- Accumulate one entropy bit per valid ADC sample
                seed_reg(to_integer(unsigned(bit_count))) <= vac_raw(15);

                if bit_count = 255 then
                    bit_count    <= (others => '0');
                    q_seed_valid <= '1';     -- Seed buffer full → trigger P3Q
                    q_seed_data  <= seed_reg; -- Latch complete 256-bit seed
                else
                    bit_count <= bit_count + 1;
                end if;
            end if;
        end if;
    end process;

    -- ── T=SQL Indexing ────────────────────────────────────────────────────
    -- Deterministic hash: fold 64-bit timestamp to 32-bit Worm Chain index.
    -- Index(t) = (t[63:32] XOR t[31:0]) XOR SALT
    -- Combinational: zero latency, no registers.
    process(timestamp_in)
    begin
        t_sql_index <= (timestamp_in(63 downto 32) xor
                        timestamp_in(31 downto 0))
                       xor T_SQL_SALT;
    end process;

end architecture rtl;